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| white electronic designs corporation ? (602) 437-1520 www.whiteedc.com white electronic designs access times of 12, 15, 17, 20, ns packaging 16mm x 18mm, 143 pbga organized as 512kx32, user configurable as 1mx16 or 2mx8 february 2003 rev.5 note: this data sheet describes a product that is subject to change without notice. i/o 0-31 data inputs/outputs a 0-18 address inputs we 1-4 write enables cs 1-4 chip selects oe output enable v cc power supply gnd ground nc not connected commercial, industrial and military temperature ranges ttl compatible inputs and outputs 5 volt power supply low power cmos 512k x 8 8 i/o 0-7 we cs 1 1 512k x 8 8 i/o 8-15 we cs 2 2 512k x 8 8 i/o 16-23 we cs 3 3 512k x 8 8 i/o 24-31 we cs 4 4 a 0 - 18 oe - a2 a1 a0 gnd gnd v cc v cc a18 a17 a16 gnd cs2 a3 a4 d14 d15 nc cs4 d24 d25 oe a15 nc d9 d8 nc d12 d13 gnd v cc d26 d27 we4 d31 d30 d10 d11 gnd gnd gnd gnd v cc v cc v cc v cc d28 d29 we2 gnd gnd gnd gnd gnd v cc v cc v cc v cc v cc nc gnd gnd gnd gnd gnd gnd v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc gnd gnd gnd gnd gnd gnd cs1 v cc v cc v cc v cc v cc gnd gnd gnd gnd gnd nc d1 d0 v cc v cc v cc v cc gnd gnd gnd gnd d23 d22 d2 d3 nc d7 d5 v cc gnd d17 d16 cs3 d20 d21 we1 a6 a5 d 6 d 4 nc we3 d19 d18 a14 a13 nc gnd a7 a8 a9 v cc v cc gnd gnd a10 a11 a12 v cc white electronic designs corporation phoenix az (602) 437-1520 white electronic designs operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 vcc+0.5 v junction temperature t j 150 c supply voltage v cc -0.5 7.0 v ! ! ! " supply voltage v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il -0.5 +0.8 v operating temp (mil) t a -55 +125 c # $ oe capacitance c oe v in = 0 v, f = 1.0 mhz 30 pf we 1-4 capacitance c we v in = 0 v, f = 1.0 mhz 10 pf c s 1-4 capacitance c cs v in = 0 v, f = 1.0 mhz 10 pf data i/o capacitance c i/o v i/o = 0 v, f = 1.0 mhz 10 pf address input capacitance c ad v in = 0 v, f = 1.0 mhz 30 pf # $ $ input leakage current i li v cc = 5.5, v in = g nd to v cc 10 a output leakage current i lo cs = v ih , oe = v ih , v out = gnd to v cc 10 a operating supply current x 32 mode i cc x 32 cs = v il , oe = v ih , f = 5mhz, vcc = 5.5 660 ma standby current i sb cs = v ih , oe = v ih , f = 5mhz, vcc = 5.5 80 ma output low voltage v ol i ol = 8ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v note: dc test conditions: v ih = v cc -0.3v, v il = 0.3v # !% & h x x standby high z standby l l h read data out active l h h out disable high z active l x l write data in active this parameter is guaranteed by design but not tested. !$' ( $ junction to ambient (no airflow) theta ja 16.5 c/w 1 junction to ball theta jb 11.3 c/w 1 junction to case (top) theta jc 9.8 c/w 1 note: refer to application note "pbga thermal resistance correlation" at www.whiteedc.com in the application notes section for modeling conditions. white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs notes: vz is programmable from -2v to +7v. iol & ioh programmable from 0 to 16ma. tester impedance z0 = 75 . vz is typically the midpoint of voh and vol. iol & ioh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. ! ( input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v )*+ )*, )*- )+. $ #' read cycle time t rc 1 2 1 5 1 7 2 0 ns address access time t aa 1 2 1 5 1 7 2 0 ns output hold from address change t oh 0 0 0 0 ns chip select access time t acs 1 2 1 5 1 7 2 0 ns output enable to output valid t oe 7 8 9 1 0 ns chip select to output in low z t clz 1 1 2 2 2 ns output enable to output in low z t olz 1 0 0 0 0 ns chip disable to output in high z t chz 1 7 1 2 1 2 1 2 ns output disable to output in high z t ohz 1 7 1 2 1 2 1 2 ns )*+ )*, )*- )+. $ #' write cycle time t wc 1 2 1 5 1 7 2 0 ns chip select to end of write t cw 1 0 1 3 1 5 1 5 ns address valid to end of write t aw 1 0 1 3 1 5 1 5 ns data valid to end of write t dw 8 1 0 1 1 1 2 ns write pulse width t wp 1 0 1 3 1 5 1 5 ns address setup time t as 0 2 2 2 ns address hold time t ah 0 0 0 0 ns output active from end of write t ow 1 2 2 2 3 ns write enable to output in high z t whz 1 7 8 9 1 1 ns data hold time t dh 00 00 1. this parameter is guaranteed by design but not tested. 1. this parameter is guaranteed by design but not tested. current source current source i ol i oh c eff = 50 pf d.u.t. v z 1.5v (bipolar supply) white electronic designs corporation phoenix az (602) 437-1520 white electronic designs ws32k32-xhx / ! 0 ! 0 ! a ddress t wc t aw t as t ah t cw t wp t dw t dh cs we data i/o data valid write cycle 2, cs controlled a ddress t rc cs oe data i/o t aa t acs t chz t clz t oe t olz t ohz high impedance data valid read cycle 2 (we = v ih ) a ddress data i/o previous data valid data valid read cycle 1 (cs = oe = v il , we = v ih ) t oh t aa t rc a ddress t wc t aw t cw t ah t as t wp t whz t dw t ow t dh data valid cs data i/o we write cycle 1, we controlled ! 0 ! white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs " !# ! 0 all linear dimensions are millimeters and parenthetically in inches 0.61 (0.024) bsc 1.27 (0.050) bsc a b c d e f g h j k l m 13.97 (0.550) bsc 16.25 (0.640) max 18.25 (0.719) max 13.97 (0.550) bsc 2.21 (0.087) max bottom view 12 11 10 9 8 7 6 5 4 3 2 1 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs ! 1 2 3 ,*+ 4+ 5 $6 0 7 ! / ! 7 !""#$ %"#$ !&#$ "#$ $ $ &#$ %'&#$ ! $ white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs 512k x 32 sram multi-chip package rev 0 initial release march, 2002 advanced rev 1 switch rows and columns header position (pg. 1) march, 2002 advanced rev 2 switch rows and columns header position (pg. 1) may, 2002 advanced rev 3 change mechanical outline to more accurate design (pg. 1, 5) may, 2002 advanced rev 4 remove references to 25-55ns speed grades (pg. 1, 2, 3) august 2002 advanced rev 5 changes (pg. 1, 2) january, 2003 final 1.1 add thermal resistance table 1.2 change product status to final |
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