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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 8-bit single-chip microcomputer 740 family / 38000 series 3819 users manual group
keep safety first in your circuit designs ! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
preface this users manual describes mitsubishis cmos 8- bit microcomputers 3819 group. after reading this manual, the user should have a through knowledge of the functions and features of the 3819 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the 740 family software manual.
before using this user's manual this user's manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. organization l chapter 1 hardware this chapter describes features of the microcomputer, operation of each peripheral function and electric characteristics. l chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. l chapter 3 appendix this chapter includes precautions for systems development using the microcomputer, a list of control registers, the masking confirmation (mask rom version), and mark specifications which are to be submitted when ordering. 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows : note 2. bit attributesthe attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is arranged name function at reset rw b 0 1 2 3 4 0 0 0 0 0 5 5 5 6 7 1 [ b0 b1 b2 b3 b4 b5 b6 b7 contents immediately after reset release bit attributes (note 1) processor mode bits stack page selection bit nothing arranged for these bits. these are write disabled bits. when these bits are read out, the contents are "0". fix this bit to "0". main clock (x in -x out ) stop bit internal system clock selection bit 00: single-chip mode 01: 10: 11: not available b1b0 0 : 0 page 1 : 1 page 0 : operating 1 : stopped 0 : x in -x out selected 1 : x cin -x cout selected : bit that is not used for control of the corresponding function 0 note 1. contents immediately after reset release 0??at reset release 1??at reset release undefinedundefined or reset release contents determined by option at reset release (d) note [ rread read enabled 5 read disabled wwrite write enabled 5 write disabled ??write [ (note 2) [ cpu mode register (cpum) [address:3b 16 ] bits
3819 group users manual i table of contents table of contents chapter 1. hardware description ........................................................................................................................................ 2 features ............................................................................................................................................. 2 applications ...................................................................................................................................... 2 pin configuration (top view) ........................................................................................................ 2 functional block diagram (package:100p6s-a) ......................................................................... 3 pin description ................................................................................................................................. 4 part numbering ................................................................................................................................ 6 group expansion ............................................................................................................................. 7 functional description .................................................................................................................... 8 central processing unit (cpu) ..................................................................................................... 8 cpu mode register ...................................................................................................................... 8 memory .............................................................................................................................................. 9 special function register (sfr) area ........................................................................................... 9 ram ............................................................................................................................................. 9 rom ............................................................................................................................................ 9 interrupt vector area .................................................................................................................... 9 zero page .................................................................................................................................... 9 special page ................................................................................................................................ 9 i/o ports .......................................................................................................................................... 11 direction registers ...................................................................................................................... 11 high-breakdown-voltage output ports ....................................................................................... 11 interrupts ......................................................................................................................................... 17 interrupt control ......................................................................................................................... 17 interrupt operation ..................................................................................................................... 17 notes on use ............................................................................................................................. 17 timers .............................................................................................................................................. 19 timer 1 and timer 2 ................................................................................................................... 19 timer 3 and timer 4 ................................................................................................................... 19 timer 5 and timer 6 ................................................................................................................... 19 timer 6 pwm mode ................................................................................................................... 19 serial i/o ......................................................................................................................................... 23 serial i/o control registers (sio1con, sio2con, sio3con) 0019 16 , 001d 16 , 001e 16 ............ 23 serial i/o automatic transfer control register (sioac) 001a 16 .............................................................. 26 serial i/o automatic transfer data pointer (siodp) 0018 16 ..................................................................... 27 serial i/o automatic transfer interval register (sioai) 001c 16 ............................................................... 27 a-d converter ................................................................................................................................. 31 a-d conversion register (ad) 002d 16 .............................................................................................................. 31 ad/da control register (adcon) 002c 16 ...................................................................................................... 31 comparison voltage generator .................................................................................................. 31 channel selector ........................................................................................................................ 31 comparator and control circuit .................................................................................................. 31 d-a converter ................................................................................................................................. 32 fld controller ................................................................................................................................ 33 fldc mode registers (fldm1, fldm2) 0036 16 , 0037 16 ....................................................................... 34 fld data pointer and fld data pointer reload register (flddp) 0038 16 .......................................... 36 interrupt interval determination function .................................................................................. 41 noise filter .................................................................................................................................. 41 zero cross detection circuit ........................................................................................................ 44 noise filter ...................................................................................................................................... 45
3819 group users manual table of contents ii reset circuit ................................................................................................................................. 46 clock generating circuit ............................................................................................................... 48 frequency control ...................................................................................................................... 48 oscillation control ...................................................................................................................... 48 notes on programming ................................................................................................................ 51 processor status register ........................................................................................................... 51 interrupts ................................................................................................................................... 51 decimal calculations .................................................................................................................. 51 timers ........................................................................................................................................ 51 multiplication and division instructions....................................................................................... 51 ports .......................................................................................................................................... 51 serial i/o .................................................................................................................................... 51 a-d converter ............................................................................................................................ 51 instruction execution timing ....................................................................................................... 51 at the stp instruction release ................................................................................................... 51 data required for mask orders .................................................................................................. 52 prom programming method ....................................................................................................... 52 absolute maximum ratings .......................................................................................................... 53 recommended operating conditions ......................................................................................... 53 electrical characteristics .............................................................................................................. 55 zero cross detection input characteristics .............................................................................. 57 a-d converter characteristics ...................................................................................................... 57 d-a converter characteristics ...................................................................................................... 57 timing requirements ..................................................................................................................... 58 switching characteristics ............................................................................................................. 58 timing diagram .............................................................................................................................. 59 power source current characteristic examples ....................................................................... 60 port standard characteristic examples ...................................................................................... 61 a-d conversion standard characteristics .................................................................................. 63 d-a conversion standard characteristics .................................................................................. 64 functional description supplement ............................................................................................ 65 interrupt ..................................................................................................................................... 65 timing after interrupt ................................................................................................................. 66 a-d converter ............................................................................................................................ 67 chapter 2. application 2.1 i/o port ..................................................................................................................................... 70 2.1.1 related registers .............................................................................................................. 70 2.1.2 handling of unused pins ................................................................................................... 71 2.2 timer ......................................................................................................................................... 72 2.2.1 related registers .............................................................................................................. 72 2.2.2 timer application examples .............................................................................................. 77 2.3 serial i/o .................................................................................................................................. 86 2.3.1 related registers .............................................................................................................. 86 2.3.2 serial i/o connection examples ........................................................................................ 91 2.3.3 setting of serial i/o mode ................................................................................................. 93 2.3.4 serial i/o application examples ........................................................................................ 94 2.4 a-d conversion ..................................................................................................................... 105 2.4.1 related registers ............................................................................................................ 105 2.4.2 a-d conversion application example .............................................................................. 107
3819 group users manual iii table of contents 2.5 fld controller ....................................................................................................................... 109 2.5.1 related registers ............................................................................................................ 109 2.5.2 fld controller application examples .............................................................................. 115 2.6 interrupt interval determination function ......................................................................... 139 2.6.1 related registers ............................................................................................................ 139 2.6.2 interrupt interval determination function ......................................................................... 142 2.7 zero cross detection circuit ............................................................................................... 147 2.7.1 related registers ............................................................................................................ 147 2.7.2 connection example of zero cross detection circuit ....................................................... 149 2.7.3 zero cross detection circuit application example 1 ......................................................... 150 2.7.4 zero cross detection circuit application example 2 ......................................................... 152 2.8 reset ....................................................................................................................................... 154 2.8.1 connection example of reset ic ..................................................................................... 154 2.9 clock generating circuit ...................................................................................................... 155 2.9.1 related registers ........................................................................................................... 155 2.9.2 clock generating circuit application examples .............................................................. 160 chapter 3. appendix 3.1 notes on use ........................................................................................................................ 170 3.1.1 notes on interrupts ......................................................................................................... 170 3.1.2 notes on the fld controller and the serial i/o automatic transfer function .................... 170 3.1.3 notes on the a-d converter ............................................................................................ 170 3.1.4 notes on the reset pin ................................................................................................ 171 3.1.5 notes on input and output pins ....................................................................................... 171 3.1.6 notes on clock synchronous serial i/o ........................................................................... 172 3.1.7 notes on built-in prom .................................................................................................. 173 3.2 countermeasures against noise ........................................................................................ 174 3.2.1 shortest wiring length ..................................................................................................... 174 3.2.2 connection of a bypass capacitor across the v ss line and the v cc line ........................ 175 3.2.3 wiring to analog input pins ............................................................................................. 176 3.2.4 oscillator concerns ......................................................................................................... 176 3.2.5 setup for i/o ports .......................................................................................................... 177 3.2.6 providing of watchdog timer function by software .......................................................... 177 3.3 control registers ................................................................................................................... 179 3.4 mask rom ordering method .............................................................................................. 196 3.5 mark specification form ...................................................................................................... 198 3.6 package outline .................................................................................................................... 199 3.7 memory map .......................................................................................................................... 200 3.8 pin configuration .................................................................................................................. 201
3819 group users manual table of contents iv list of figures chapter 1. hardware fig. 1 structure of cpu mode register ................................................................................................. 8 fig. 2 memory map .................................................................................................................................. 9 fig. 3 memory map of special function register (sfr) .................................................................... 10 fig. 4 port block diagram (1) ............................................................................................................... 13 fig. 5 port block diagram (2) ............................................................................................................... 14 fig. 6 port block diagram (3) ............................................................................................................... 15 fig. 7 port block diagram (4) ............................................................................................................... 16 fig. 8 interrupt control ........................................................................................................................... 18 fig. 9 structure of interrupt related registers ..................................................................................... 18 fig. 10 timer block diagram ................................................................................................................. 20 fig. 11 structure of timer related registers ........................................................................................ 21 fig. 12 timing in timer 6 pwm mode ................................................................................................. 22 fig. 13 serial i/o block diagram .......................................................................................................... 24 fig. 14 structure of serial i/o control registers ................................................................................. 25 fig. 15 serial i/o timing in the serial i/o ordinary mode (for lsb first) ....................................... 26 fig. 16 structure of serial i/o automatic transfer control register .................................................. 26 fig. 17 bit allocation of serial i/o automatic transfer ram ............................................................. 27 fig. 18 serial i/o automatic transfer interval timing ......................................................................... 27 fig. 19 serial i/o1 register transfer operation in full duplex mode ................................................ 28 fig. 20 timing chart during serial i/o automatic transfer (internal clock selected, s rdy used) ..................................................................................... 29 fig. 21 timing chart during serial i/o automatic transfer (internal clock selected, s clk11 and s clk12 used) .............................................................. 29 fig. 22 timing during serial i/o automatic transfer (external clock selected) .............................. 30 fig. 23 structure of a-d control register ............................................................................................ 31 fig. 24 a-d converter block diagram .................................................................................................. 32 fig. 25 d-a converter block diagram .................................................................................................. 32 fig. 26 equivalent connection circuit of d-a converter .................................................................... 32 fig. 27 fld control circuit block diagram .......................................................................................... 33 fig. 28 structure of fldc mode register 1 ....................................................................................... 34 fig. 29 structure of fldc mode register 2 ....................................................................................... 34 fig. 30 segment/digit setting example ................................................................................................ 35 fig. 31 fld automatic display ram and bit allocation .................................................................... 37 fig. 32 example of using the fld automatic display ram (1) ....................................................... 38 fig. 33 example of using the fld automatic display ram (2) (continued) .................................. 39 fig. 34 fldc timing ............................................................................................................................... 40 fig. 35 block diagram of interrupt interval determination circuit ..................................................... 41 fig. 36 structure of interrupt interval determination control register .............................................. 42 fig. 37 interrupt interval determination operation example (at rising edge active) ...................... 42 fig. 38 interrupt interval determination operation example (at both-sided edge active) ............. 43 fig. 39 external circuit example for zero cross detection ................................................................ 44 fig. 40 structure of zero cross detection control register ................................................................ 44 fig. 41 block diagram of zero cross detection circuit ...................................................................... 44 fig. 42 noise filter circuit diagram ...................................................................................................... 45
3819 group users manual v table of contents fig. 43 timing of noise filter circuit ..................................................................................................... 45 fig. 44 example of reset circuit ........................................................................................................... 46 fig. 45 reset sequence ........................................................................................................................ 46 fig. 46 internal state at reset ............................................................................................................... 47 fig. 47 ceramic resonator external circuit ......................................................................................... 48 fig. 48 external clock input circuit ...................................................................................................... 48 fig. 49 clock generating circuit block diagram ................................................................................. 49 fig. 50 state transition of system clock ............................................................................................. 50 fig. 51 programming and testing of one time prom version ...................................................... 52 fig. 52 zero cross detection input characteristics ............................................................................ 57 fig. 53 circuit for measuring output switching characteristics ........................................................ 58 fig. 54 power source current characteristic example ....................................................................... 60 fig. 55 power source current characteristic example (in wait mode) ............................................ 60 fig. 56 standard characteristic example of high-breakdown-voltage p-channel open-drain output port .................. 61 fig. 57 standard characteristic example of cmos output port at p-channel drive ..................... 61 fig. 58 standard characteristic example of cmos output port at n-channel drive ..................... 62 fig. 59 a-d conversion standard characteristics ............................................................................... 63 fig. 60 d-a conversion standard characteristics ............................................................................... 64 fig. 61 timing chart after an interrupt occurs ................................................................................... 66 fig. 62 time up to execution of the interrupt processing routine .................................................. 66 fig. 63 a-d conversion equivalent circuit ........................................................................................... 68 fig. 64 a-d conversion timing chart .................................................................................................... 68 chapter 2. application fig. 2.1.1 structure of port pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b) ............................................ 70 fig. 2.1.2 structure of port p2 direction register .............................................................................. 70 fig. 2.1.3 structure of port pi direction register (i = 4, 5, 6, 7, 8, a, b) ..................................... 71 fig. 2.2.1 structure of timer i (i = 1, 3, 4, 5, 6) .............................................................................. 72 fig. 2.2.2 structure of timer 2 ............................................................................................................. 72 fig. 2.2.3 structure of timer 6 pwm register ................................................................................... 73 fig. 2.2.4 structure of timer 12 mode register ................................................................................. 73 fig. 2.2.5 structure of timer 34 mode register ................................................................................. 74 fig. 2.2.6 structure of timer 56 mode register ................................................................................. 74 fig. 2.2.7 structure of interrupt request register 1 ........................................................................... 75 fig. 2.2.8 structure of interrupt request register 2 ........................................................................... 75 fig. 2.2.9 structure of interrupt control register 1 ............................................................................ 76 fig. 2.2.10 structure of interrupt control register 2 .......................................................................... 76 fig. 2.2.11 connection of timers and setting of division ratios [clock function] .......................... 78 fig. 2.2.12 setting of related registers (1) [clock function] ............................................................. 78 fig. 2.2.13 setting of related registers (2) [clock function] ............................................................. 79 fig. 2.2.14 control procedure [clock function] .................................................................................. 80 fig. 2.2.15 example of a peripheral circuit ........................................................................................ 81 fig. 2.2.16 connection of the timer and setting of the division ratio [piezoelectric buzzer output] .... 81 fig. 2.2.17 setting of related registers [piezoelectric buzzer output] ............................................. 82 fig. 2.2.18 control procedure [piezoelectric buzzer output] ............................................................ 82 fig. 2.2.19 a method for judging if video synchronization signal exists ....................................... 83 fig. 2.2.20 setting of related registers [measurement of frequency] ............................................. 84 fig. 2.2.21 control procedure [measurement of frequency] ............................................................. 85 fig. 2.3.1 structure of serial i/o automatic transfer data pointer .................................................. 86 fig. 2.3.2 structure of serial i/o 1 control register .......................................................................... 86
3819 group users manual table of contents vi fig. 2.3.3 structure of serial i/o automatic transfer control register ............................................. 87 fig. 2.3.4 structure of serial i/o 1 register ....................................................................................... 87 fig. 2.3.5 structure of serial i/o automatic transfer interval register ............................................ 88 fig. 2.3.6 structure of serial i/o 2 control register .......................................................................... 88 fig. 2.3.7 structure of serial i/o 3 control register .......................................................................... 89 fig. 2.3.8 structure of interrupt request register 1 ........................................................................... 89 fig. 2.3.9 structure of interrupt control register 1 ............................................................................ 90 fig. 2.3.10 serial i/o connection examples (1) ................................................................................. 91 fig. 2.3.11 serial i/o connection examples (2) ................................................................................. 92 fig. 2.3.12 setting of serial i/o mode ................................................................................................ 93 fig. 2.3.13 connection diagram [output of serial data] ................................................................... 94 fig. 2.3.14 timing chart [output of serial data] ................................................................................ 94 fig. 2.3.15 setting of related registers [output of serial data] ........................................................ 95 fig. 2.3.16 setting of transmission data [output of serial data] ..................................................... 95 fig. 2.3.17 control procedure [output of serial data] ....................................................................... 96 fig. 2.3.18 connection diagram [data transmission or reception using automatic transfer] ....... 97 fig. 2.3.19 timing chart [data transmission or reception using automatic transfer] .................... 97 fig. 2.3.20 setting of related registers [data transmission or reception using automatic transfer] ................ 98 fig. 2.3.21 setting of transmission data [data transmission or reception using automatic transfer] ............. 99 fig. 2.3.22 control procedure [data transmission or reception using automatic transfer] ............................... 100 fig. 2.3.23 connection diagram [cyclic transmission or reception of block data between microcomputers] ........... 101 fig. 2.3.24 timing chart [cyclic transmission or reception of block data between microcomputers] ............... 102 fig. 2.3.25 setting of related registers [cyclic transmission or reception of block data between microcomputers] ........... 102 fig. 2.3.26 control in the master unit .............................................................................................. 103 fig. 2.3.27 control in the slave unit ................................................................................................. 104 fig. 2.4.1 structure of ad/da control register ................................................................................ 105 fig. 2.4.2 structure of a-d conversion register .............................................................................. 105 fig. 2.4.3 structure of interrupt request register 2 ........................................................................ 106 fig. 2.4.4 structure of interrupt control register 2 ......................................................................... 106 fig. 2.4.5 connection diagram [conversion of analog input voltage] ......................................... 107 fig. 2.4.6 setting of related registers [conversion of analog input voltage] ............................. 107 fig. 2.4.7 control procedure [conversion of analog input voltage] ............................................. 108 fig. 2.5.1 structure of port p0 segment/digit switch register ....................................................... 109 fig. 2.5.2 structure of port p2 digit/port switch register ............................................................... 109 fig. 2.5.3 structure of port p8 segment/port switch register ....................................................... 110 fig. 2.5.4 structure of port pa segment/port switch register ....................................................... 110 fig. 2.5.5 structure of fldc mode register 1 ................................................................................ 111 fig. 2.5.6 structure of fldc mode register 2 ................................................................................ 112 fig. 2.5.7 structure of fld data pointer ......................................................................................... 113 fig. 2.5.8 structure of fld data pointer reload register ............................................................... 113 fig. 2.5.9 structure of interrupt request register 2 ........................................................................ 114 fig. 2.5.10 structure of interrupt control register 2 ....................................................................... 114 fig. 2.5.11 connection diagram [fld automatic display and key-scan using segment pin] ... 115 fig. 2.5.12 timing chart [fld automatic display and key-scan using segment pin] .............. 115 fig. 2.5.13 enlarged view of seg 24 to seg 31 during tscan ....................................................... 116 fig. 2.5.14 setting of related registers (1) [fld automatic display and key-scan using segment pin] .... 116 fig. 2.5.15 setting of related registers (2) [fld automatic display and key-scan using segment pin] .... 117 fig. 2.5.16 example of fld digit allocation [fld automatic display and key-scan using segment pin] . 119 fig. 2.5.17 control procedure [fld automatic display and key-scan using segment pin] ...... 120
3819 group users manual vii table of contents fig. 2.5.18 control procedure of segment key-scan ..................................................................... 121 fig. 2.5.19 connection diagram [fld automatic display and key-scan using digit pin] .......... 122 fig. 2.5.20 timing chart [fld automatic display and key-scan using digit pin] ...................... 122 fig. 2.5.21 setting of related registers (1) [fld automatic display and key-scan using digit pin] ........... 123 fig. 2.5.22 setting of related registers (2) [fld automatic display and key-scan using digit pin] ........... 124 fig. 2.5.23 example of fld digit allocation [fld automatic display and key-scan using digit pin] ......... 126 fig. 2.5.24 control procedure [fld automatic display and key-scan using digit pin] .............. 127 fig. 2.5.25 control procedure of digit key-scan ............................................................................. 128 fig. 2.5.26 connection diagram [fld display by software] .......................................................... 129 fig. 2.5.27 timing chart [fld display by software] ....................................................................... 129 fig. 2.5.28 enlarged view of key-scan of ports p3 0 to p3 7 ......................................................... 130 fig. 2.5.29 setting of related registers [fld display by software] .............................................. 130 fig. 2.5.30 example of fld digit allocation [fld display by software] ...................................... 131 fig. 2.5.31 control procedure [fld display by software] .............................................................. 132 fig. 2.5.32 connection diagram [5 5 7 dot display] ...................................................................... 133 fig. 2.5.33 timing chart [5 5 7 dot display] ................................................................................... 133 fig. 2.5.34 setting of related registers (1) [5 5 7 dot display] .................................................... 134 fig. 2.5.35 setting of related registers (2) [5 5 7 dot display] .................................................... 135 fig. 2.5.36 example of fld digit allocation and segment arrangment ....................................... 137 fig. 2.5.37 setting example of display data (in case of using dig 11 pin) ................................. 137 fig. 2.5.38 control procedure [5 5 7 dot display] ......................................................................... 138 fig. 2.6.1 structure of interrupt interval determination register ................................................... 139 fig. 2.6.2 structure of interrupt interval determination control register ...................................... 139 fig. 2.6.3 structure of interrupt edge selection register ............................................................... 140 fig. 2.6.4 structure of interrupt request register 1 ........................................................................ 140 fig. 2.6.5 structure of interrupt control register 1 ......................................................................... 141 fig. 2.6.6 connection diagram [reception of remote-control signal] ........................................... 142 fig. 2.6.7 function block diagram [reception of remote-control signal] ..................................... 142 fig. 2.6.8 timing chart of data determination ................................................................................. 143 fig. 2.6.9 setting of related registers [reception of remote-control signal] ............................... 144 fig. 2.6.10 control procedure (1) [reception of remote-control signal] ...................................... 145 fig. 2.6.11 control procedure (2) [reception of remote-control signal] (timer 2 interrupt) ..... 146 fig. 2.7.1 structure of zero cross detection control register ........................................................ 147 fig. 2.7.2 structure of interrupt edge selection register ............................................................... 147 fig. 2.7.3 structure of interrupt request register 1 ........................................................................ 148 fig. 2.7.4 structure of interrupt control register 1 ......................................................................... 148 fig. 2.7.5 connection example of zero cross detection circuit .................................................... 149 fig. 2.7.6 setting of related registers [clock count using zcr interrupt (without using a noise filter)] ................................ 150 fig. 2.7.7 control procedure [clock coun t using zcr interrupt (without using a noise filter)] ....................... 151 fig. 2.7.8 setting of related registers [clock coun t using zcr interrupt (using a noise filter)] ................... 152 fig. 2.7.9 control procedure [clock coun t using zcr interrupt (using a noise filter)] ..................................... 153 fig. 2.8.1 example of poweron reset circuit ................................................................................... 154 fig. 2.8.2 ram back-up system ........................................................................................................ 154 fig. 2.9.1 structure of timer i ........................................................................................................... 155 fig. 2.9.2 structure of timer 2 .......................................................................................................... 155 fig. 2.9.3 structure of timer 12 mode register .............................................................................. 156 fig. 2.9.4 structure of timer 34 mode register .............................................................................. 156 fig. 2.9.5 structure of cpu mode register ...................................................................................... 157 fig. 2.9.6 structure of interrupt request register 1 ........................................................................ 157 fig. 2.9.7 structure of interrupt request register 2 ........................................................................ 158
3819 group users manual table of contents viii fig. 2.9.8 structure of interrupt control register 1 ......................................................................... 158 fig. 2.9.9 structure of interrupt control register 2 ......................................................................... 159 fig. 2.9.10 connection diagram [status transition upon a power failure] ................................... 160 fig. 2.9.11 status transition diagram upon a power failure .......................................................... 160 fig. 2.9.12 setting of related registers [status transition upon a power failure] ....................... 161 fig. 2.9.13 control procedure [status transition upon a power failure] ...................................... 162 fig. 2.9.14 connection diagram [counting without clock errors during a power failure] .......... 163 fig. 2.9.15 timing chart of counting without clock errors during a power failure ..................... 163 fig. 2.9.16 structure of a clock counter .......................................................................................... 164 fig. 2.9.17 setting of related registers (1) [counting without clock errors during a power failure] ........... 165 fig. 2.9.18 setting of related registers (2) [counting without clock errors during a power failure] ........... 166 fig. 2.9.19 control procedure (1) [counting without clock errors during a power failure] ....... 167 fig. 2.9.20 control procedure (2) [counting without clock errors during a power failure] ....... 168 fig. 3.1.1 structure of interrupt control register 2 .......................................................................... 170 fig. 3.2.1 wiring for the reset pin ................................................................................................ 174 fig. 3.2.2 wiring for clock i/o pins .................................................................................................. 175 fig. 3.2.3 wiring for the v pp pin of the one time prom and the eprom version ............... 175 fig. 3.2.4 bypass capacitor across the v ss line and the v cc line ............................................. 175 fig. 3.2.5 analog signal line and a resistor and a capacitor ....................................................... 176 fig. 3.2.6 wiring for a large current signal line ............................................................................. 176 fig. 3.2.7 wiring to a signal line where potential levels change frequently .............................. 176 fig. 3.2.8 setup for i/o ports ............................................................................................................ 177 fig. 3.2.9 watchdog timer by software ............................................................................................ 177 fig. 3.3.1 structure of port pi direction register ............................................................................ 179 fig. 3.3.2 structure of port p2 direction register ........................................................................... 179 fig. 3.3.3 structure of serial i/o automatic transfer data pointer ............................................... 180 fig. 3.3.4 structure of serial i/o 1 control register ....................................................................... 180 fig. 3.3.5 structure of serial i/o automatic transfer control register .......................................... 181 fig. 3.3.6 structure of serial i/o automatic transfer interval register ......................................... 181 fig. 3.3.7 structure of serial i/o 2 control register ....................................................................... 182 fig. 3.3.8 structure of serial i/o 3 control register ....................................................................... 182 fig. 3.3.9 structure of timer 12 mode register .............................................................................. 183 fig. 3.3.10 structure of timer 34 mode register ............................................................................ 183 fig. 3.3.11 structure of timer 56 mode register ............................................................................ 184 fig. 3.3.12 structure of ad/da control register .............................................................................. 185 fig. 3.3.13 structure of interrupt interval determination register ................................................. 186 fig. 3.3.14 structure of interrupt interval determination control register .................................... 186 fig. 3.3.15 structure of port p0 segment/digit switch register ..................................................... 187 fig. 3.3.16 structure of port p2 digit/port switch register ............................................................. 187 fig. 3.3.17 structure of port p8 segment/port switch register ..................................................... 188 fig. 3.3.18 structure of port pa segment/port switch register ..................................................... 188 fig. 3.3.19 structure of fldc mode register 1 .............................................................................. 189 fig. 3.3.20 structure of fldc mode register 2 .............................................................................. 190 fig. 3.3.21 structure of fld data pointer ....................................................................................... 191 fig. 3.3.22 structure of fld data pointer reload register ............................................................. 191 fig. 3.3.23 structure of zero cross detection control register ...................................................... 192 fig. 3.3.24 structure of interrupt edge selection register ............................................................. 192 fig. 3.3.25 structure of cpu mode register .................................................................................... 193 fig. 3.3.26 structure of interrupt request register 1 ...................................................................... 193 fig. 3.3.27 structure of interrupt request register 2 ...................................................................... 194 fig. 3.3.28 structure of interrupt control register 1 ....................................................................... 194 fig. 3.3.29 structure of interrupt control register 2 ....................................................................... 195
3819 group users manual ix table of contents list of tables chapter 1. hardware table 1. interrupt vector addresses and priority ......................................................................................... 17 table 2. s clk11 and s clk12 selection ........................................................................................................ 29 table 3. p6 7 /s rdy1 /cs selection ................................................................................................................ 30 table 4. pins in fld automatic display mode ............................................................................................ 35 table 5. interrupt sources, vector addresses and interrupt priority ............................................................ 65 table 6. change of a-d conversion register during a-d conversion .......................................................... 67 chapter 2. application table 2.1.1 handling of unused pins .......................................................................................................... 71 table 2.5.1 fld automatic display ram map [fld automatic display and key-scan segment pin] ........ 118 table 2.5.2 fld automatic display ram map example [fld automatic display and key-scan segment pin] ......... 119 table 2.5.3 fld automatic display ram map [fld automatic display and key-scan digit pin] ............. 125 table 2.5.4 fld automatic display ram map example [fld automatic display and key-scan digit pin] ............... 126 table 2.5.5 fld automatic display ram map example [fld display by software] (automatic display is not performed because of not using fld controller) ........................... 131 table 2.5.6 fld automatic display ram map [5 5 7 dot display] ............................................................ 136 chapter 3. appendix table 3.1.1 programming adapter ............................................................................................................ 173 table 3.1.2 setting of programming adapter switch ................................................................................ 173 table 3.1.3 setting of prom programmer address ................................................................................. 173
chapter 1 hardware
p8 7 /seg 15 81 m38197ma-xxxfp p8 6 /seg 14 82 p8 5 /seg 13 83 p8 4 /seg 12 84 p8 3 /seg 11 85 p8 2 /seg 10 86 p8 1 /seg 9 87 p8 0 /seg 8 88 pa 7 /seg 7 89 pa 6 /seg 6 90 v cc 91 pa 5 /seg 5 92 pa 4 /seg 4 93 pa 3 /seg 3 94 pa 2 /seg 2 95 pa 1 /seg 1 96 pa 0 /seg 0 97 v ee 98 av ss 99 v ref 100 p1 6 /dig 14 50 p1 7 /dig 15 49 p2 0 /dig 16 48 p2 1 /dig 17 47 p2 2 /dig 18 46 p2 3 /dig 19 45 p2 4 44 p2 5 43 p2 6 42 p2 7 41 v ss 40 x out 39 x in 38 pb 0 /x cout 37 pb 1 /x cin 36 reset 35 p4 0 /int 0 34 p4 1 33 p4 2 /int 2 32 p4 3 /int 3 31 p7 7 /an 7 1 p7 6 /an 6 2 p7 5 /an 5 3 p7 4 /an 4 4 p7 3 /an 3 5 p7 2 /an 2 6 p7 1 /an 1 7 p7 0 /an 0 8 pb 3 9 pb 2 /da 10 p5 7 /s rdy3 /an 15 11 p5 6 /s clk3 /an 14 12 p5 5 /s out3 /an 13 13 p5 4 /s in3 /an 12 14 p5 3 /s rdy2 /an 11 15 p5 2 /s clk2 /an 10 16 p5 1 /s out2 /an 9 17 p5 0 /s in2 /an 8 18 p6 7 /s rdy1 /cs/s clk12 19 p6 6 /s clk11 20 p6 5 /s out1 21 p6 4 /s in1 22 p6 3 /cntr 1 23 p6 2 /cntr 0 24 p6 1 /pwm 25 p6 0 26 p4 7 /t3 out 27 p4 6 /t1 out 28 p4 5 /int 1 /zcr 29 p4 4 /int 4 30 p9 0 /seg 16 80 p9 1 /seg 17 79 p9 2 /seg 18 78 p9 3 /seg 19 77 p9 4 /seg 20 76 p9 5 /seg 21 75 p9 6 /seg 22 74 p9 7 /seg 23 73 p3 0 /seg 24 72 p3 1 /seg 25 71 p3 2 /seg 26 70 p3 3 /seg 27 69 p3 4 /seg 28 68 p3 5 /seg 29 67 p3 6 /seg 30 66 p3 7 /seg 31 65 p0 0 /seg 32 /dig 0 64 p0 1 /seg 33 /dig 1 63 p0 2 /seg 34 /dig 2 62 p0 3 /seg 35 /dig 3 61 p0 4 /seg 36 /dig 4 60 p0 5 /seg 37 /dig 5 59 p0 6 /seg 38 /dig 6 58 p0 7 /seg 39 /dig 7 57 p1 0 /seg 40 /dig 8 56 p1 1 /seg 41 /dig 9 55 p1 2 /dig 10 54 p1 3 /dig 11 53 p1 4 /dig 12 52 p1 5 /dig 13 51 description the 3819 group is a 8-bit microcomputer based on the 740 family core technology. the 3819 group has a flourescent display automatic display circuit and an 16-channel 8-bit a-d converter as additional functions. the various microcomputers in the 3819 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3819 group, re- fer to the section on group expansion. features l basic machine-language instructions ...................................... 71 l the minimum instruction execution time ......................... 0.48 m s (at 8.4 mhz oscillation frequency) l memory size ................................................................................. rom ............................................. 4k to 60 k bytes ram ........................................... 192 to 2048 bytes l programmable input/output ports ............................................ 54 l high-breakdown-voltage output ports ...................................... 52 l interrupts ................................................. 20 sources, 16 vectors l timers ............................................................................. 8-bit 5 6 l serial i/o (serial i/o1 has an automatic transfer function) ...................................................... 8-bit 5 3(clock-synchronized) l pwm output circuit ............... 8-bit 5 1(also functions as timer 6) l a-d converter ............................................... 8-bit 5 16 channels l d-a converter ................................................. 8-bit 5 1 channels l zero cross detection input ............................................ 1 channel l fluorescent display function segments ........................................................................ 16 to 42 digits .................................................................................. 6 to 16 l 2 clock generating circuit clock (x in -x out ) ................................. internal feedback resistor sub-clock (x cin -x cout ) ......... without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscil- lator) l power source voltage in high-speed mode .................................................. 4.0 to 5.5 v (at 8.4 mhz oscillation frequency and high-speed selected) in middle-speed mode ............................................... 2.8 to 5.5 v (at 8.4 mhz oscillation frequency) in low-speed mode .................................................... 2.8 to 5.5 v (at 32 khz oscillation frequency) l power dissipation in high-speed mode .......................................................... 35 mw (at 8.4 mhz oscillation frequency) in low-speed mode ............................................................ 60 m w (at 3 v power source voltage and 32 khz oscillation frequency ) l operating temperature range .................................... C10 to 85c application musical instruments, household appliance, etc. package type : 100p6s-a 100-pin plastic-molded qfp pin configuration (top view) 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 2
3 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional block diagram (package : 100p6s-a) interrupt interval determination circuit rom cpu p7 (8) i/o port p7 123 45678 p8 (8) i/o port p8 81 82 83 84 85 86 87 88 a-d converter (8) p9 (8) output port p9 73 74 75 76 77 78 79 80 pa (8) i/o port pa 89 90 92 93 94 95 96 97 pb (4) i/o port pb 9103637 p6 (8) i/o port p6 19 20 21 22 23 24 25 26 99 100 av ss v ref p5 (8) i/o port p5 11 12 13 14 15 16 17 18 p4 (8) i/o port p4(6) input port p4(2) 27 28 29 30 31 32 33 34 p3 (8) output port p3 65 66 67 68 69 70 71 72 s i/o3(8) s i/o2(8) s i/o1(8) 16 p2 (8) output port p2(4) i/o port p2(4) 48 47 46 45 44 43 42 41 p1 (8) output port p1 56 55 54 53 52 51 50 49 p0 (8) output port p0 64 63 62 61 60 59 58 57 d-a converter (8) ps pc l s y x a pc h ram data bus timer 1 (8) timer 2 (8) timer 3 (8) timer 4 (8) timer 5 (8) timer 6 (8) t1 out si/o automatic transfer controller fld automatic display controller si/o automatic transfer ram 32 bytes fld automatic display ram 96 bytes clock generating circuit x cout sub-clock output x cin sub-clock input clock output x out clock input x in 92 v ee 40 (0 v) v ss 91 (5 v) v cc 35 reset input reset 39 38 x cout x cin zero cross detection circuit int 0 int 1 /zcr int 2 t3 out pwm cntr 0 cntr 1 local data bus int 3 , int 4
4 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ?reset input pin for active l v cc , v ss pin description pin name function function except a port function power source ?apply voltage of 4.0 to 5.5 v to v cc , and 0 v to v ss . ?applies voltage supplied to pull-down resistors of ports p0, p1, p2 0 Cp2 3 , p3, and p9. ?reference voltage input pin for a-d converter and d-a converter ?gnd input pin for a-d converter and d-a converter ?connect av ss to v ss . ?input and output pins for the main clock generating circuit ?feedback resistor is built in between x in pin and x out pin. ?connect a ceramic resonator or a quartz-crystal oscillator between the x in pin and x out pin to set oscillation frequency. ?if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?this clock is used as the oscillating source of system clock. ?8-bit output port ?this port builds in pull-down resistor between port p0 and the v ee pin. ?at reset this port is set to v ee level. ?the high-breakdown-voltage p-channel open-drain v ee v ref av ss reset x in x out p0 0 /seg 32 / dig 0 Cp0 7 / seg 39 /dig 7 p1 0 /seg 40 / dig 8 Cp1 7 / dig 15 p2 0 /dig 16 C p2 3 /dig 19 p2 4 Cp2 7 ?8-bit output port with the same function as port p0 ?4-bit output port with the same function as port p0 ?4-bit i/o port ?i/o direction register allows each pin to be individually programmed as either input or output. ?at reset this port is set to input mode. ?ttl input level ?cmos 3-state output p3 0 /seg 24 C p3 7 /seg 31 p4 0 /int 0 , p4 5 /int 1 / zcr p4 2 /int 2 C p4 4 /int 4 p4 1 p4 6 /t1 out , p4 7 /t3 out pull-down power source analog reference voltage reset input analog power source clock input clock output output port p0 output port p1 output port p2 i/o port p2 output port p3 input port p4 i/o port p4 ?8-bit output port with the same function as port p0 ?2-bit input port ?cmos compatible input level ?6-bit cmos i/o port with the same function as ports p2 4 Cp2 7 ?cmos compatible input level ?cmos 3-state output fld automatic display pins fld automatic display pins fld automatic display pins fld automatic display pins external interrupt input pins a zero cross detection circuit input pin (p4 5 ) timer output pins
5 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ?8-bit output port with the same function as port p0 p5 0 /s in2 /an 8 , p5 1 /s out2 /an 9 , p5 2 /s clk2 /an 10 , p5 3 /s rdy2 /an 11 p5 4 /s in3 /an 12 , p5 5 /s out3 /an 13 , p5 6 /s clk3 /an 14 , p5 7 /s rdy3 /an 15 p6 0 p6 1 /pwm p6 2 /cntr 0 , p6 3 /cntr 1 p6 4 /s in1 , p6 5 /s out1 , p6 6 /s clk11 , p6 7 /s rdy1 /cs/ s clk12 pin description (continued) pin name function function except a port function i/o port p5 ?8-bit cmos i/o port with the same function as ports p2 4 Cp2 7 ?cmos compatible input level ?cmos 3-state output ?8-bit cmos i/o port with the same function as ports p2 4 Cp4 7 ?cmos compatible input level ?cmos 3-state output ?8-bit cmos i/o port with the same function as ports p2 4 Cp2 7 ?cmos compatible input level ?cmos 3-state output ?8-bit i/o port with the same function as ports p2 4 Cp2 7 ?cmos compatible input level ?the high-breakdown-voltage p-channel open-drain ?8-bit i/o port with the same function as ports p2 4 Cp2 7 ?cmos compatible input level ?the high-breakdown voltage p-channel open- drain ?4-bit cmos i/o port with the same function as ports p2 4 Cp2 7 ?cmos compatible input level ?cmos 3-state output serial i/o2 function pins a-d conversion input pins serial i/o3 function pins a-d conversion input pins pwm output pin (timer output pin) timer input pins serial i/o1 function pins a-d conversion input pins fld automatic display pins i/o pins for sub-clock generating circuit (con- nect a ceramic resonator or a quarts-crystal oscillator) d-a conversion output pin p7 0 /an 0 C p7 7 /an 7 p8 0 /seg 8 C p8 7 /seg 15 p9 0 /seg 16 C p9 7 /seg 23 pa 0 /seg 0 C pa 7 /seg 7 pb 0 /x cout , pb 1 /x cin pb 2 /da pb 3 i/o port p6 i/o port p7 i/o port p8 output port p9 i/o port pa i/o port pb
6 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers part numbering package type fp : 100p6s-a package fs : 100d0 package rom number omitted in some types. rom/prom size 1 2 3 4 5 6 7 8 9 a b c d e f : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. ram size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes memory type m e : mask rom version : eprom or one time prom version product m3819 fpm a xxx 7
7 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers group expansion mitsubishi plans to expand the 3819 group as follows: (1) support for mask rom, one time prom, and eprom ver- sions rom/prom capacity .................................. 40 k to 60 k bytes ram capacity .............................................. 1024 to 2048 bytes (2) packages 100p6s-a ........................... 0.65 mm-pitch plastic molded qfp 100d0 ........................... ceramic lcc(built-in eprom version) currently supported products are listed below. as of may 1996 ram size (bytes) remarks package product (p) rom size (bytes) rom size for user in ( ) m38197ma-xxxfp m38197ma-xxxkp m38198mc-xxxkp m38199mf-xxxkp m38198mc-xxxfp m38198ec-xxxfp m38198ecfp m38198ecfs m38199mf-xxxfp m38199ef-xxxfp m38199effp m38199effs mask rom version mask rom version mask rom version mask rom version mask rom version one time prom version one time prom version (blank) eprom version mask rom version one time prom version one time prom version (blank) eprom version 1024 1536 2048 100p6s-a 100p6p-e 100p6s-a 100d0 100p6s-a 100d0 40960 (40830) 49152 (49022) 61440 (61310) memory expansion plan products under development : the development schedule and specifications may be revised without notice. 4k 256 512 768 1,024 1,536 2,048 rom size (bytes) ram size (bytes) under development 8k 12k 16k 20k 24k 28k 32k 36k 40k 44k 48k 52k 56k 60k m38199mf/ef mass product mass product m38197ma m38198mc/ec
8 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional description central processing unit (cpu) the 3819 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst, slw instruction cannot be used. the mul, div, wit and stp instruction can be used. cpu mode register the cpu mode register is allocated at address 003b 16 . the cpu mode register contains the stack page selection bit and the inter- nal system clock selection bit. fig. 1 structure of cpu mode register processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : stack page selection bit 0 : ram in the zero page is used as stack area 1 : ram in page 1 is used as stack area x cout drivability selection bit 0 : low drive 1 : high drive port x c switch bit 0 : i/o port function 1 : x cin -x cout oscillating function main clock (x in -x out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) internal system clock selection bit 0 : x in -x out selected (middle/high-speed mode) 1 : x cin -x cout selected (low-speed mode) b7 cpu mode register (cpum (cm) : address 003b 16 ) b0
9 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 192 256 384 512 640 768 896 1024 1536 2048 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram rom sfr area zero page special page ram area ram capacity (bytes) address xxxx 16 rom capacity (bytes) address yyyy 16 reserved area 0f00 16 0f1f 16 not used ram area for serial i/o automatic transfer not used 0f80 16 ram area for fld automatic display 0fdf 16 not used reserved rom area (common rom area,128 bytes) interrupt vector area reserved rom area rom area address zzzz 16 memory special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the reset is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 2 memory map
10 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 3 memory map of special function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 port p0 (p0) port p1 (p1) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) serial i/o automatic transfer data pointer (siodp) serial i/o1 control register (sio1con) serial i/o automatic transfer control register (sioac) serial i/o1 register (sio1) serial i/o automatic transfer interval register (sioai) 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 timer 1 (t1) timer 2 (t2) timer 3 (t3) timer 4 (t4) timer 5 (t5) timer 6 (t6) serial i/o3 register (sio3) timer 6 pwm register (t6pwm) timer 12 mode register (t12m) timer 34 mode register (t34m) interrupt interval determination register (iid) interrupt interval determination control register (iidcon) port p0 segment/digit switch register (p0sdr) port p2 digit/port switch register (p2dpr) port p8 segment/port switch register (p8spr) fldc mode register 2 (fldm2) zero cross detection control register (zcrcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) 003f 16 interrupt control register 2 (icon2) port pa (pa) port pa direction register (pad) port pb (pb) port pb direction register (pbd) serial i/o2 control register (sio2con) serial i/o3 control register (sio3con) serial i/o2 register (sio2) timer 56 mode register (t56m) d-a conversion register (da) ad-da control register (adcon) a-d conversion register (ad) port pa segment/port switch register (paspr) fldc mode register 1 (fldm1) fld data pointer (flddp) port p9 (p9)
11 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers i/o ports direction registers the 3819 group has 54 programmable i/o pins arranged in 8 i/o ports (ports p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5Cp8, pa, and pb). the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, each pin can be set to be input or output. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin which is set for output, the value of the port latch is read, not the value of the pin itself. a pin which is set for input the value of the pin itself is read because the pin is in floating state. if a pin set for input is written to, only the port latch is written to and the pin remains floating. high-breakdown-voltage output ports the 3819 group microprocessors have 7 ports with high-break- down-voltage pins (ports p0, p1, p2 0 Cp2 3 , p3, p8, p9, pa). the high-breakdown-voltage ports have p-channel open-drain output with v cc C40 v of breakdown voltage. each pin in ports p0, p1, p2 0 Cp2 3 , p3, and p9 has an internal pull-down resistor connected to v ee . ports p8 and pa have no in- ternal pull-down resistors, so that connect an external resistor to each port. at reset, the p-channel output transistor of each port latch is turned off, so it becomes v ee level (l) by the pull-down resistor. writing 1 (weak drivability) to bit 7 of the fldc mode register 1 (address 0036 16 ) shows the rising transition of the output transis- tors for reducing transient noise. at reset, bit 7 of the fldc mode register 1 is set to 0 (strong drivability). pin name input/output i/o format non-port function related sfr s diagram no. p0 0 /seg 32 / dig 0 C p0 7 /seg 39 / dig 7 p1 0 /seg 40 / dig 8 C p1 7 /dig 15 p2 0 /dig 16 C p2 3 /dig 19 p2 4 Cp2 7 p3 0 /seg 24 C p3 7 /seg 31 p4 0 /int 0 p4 5 /int 1 / zcr high-breakdown- voltage p-channel open-drain output with pull-down resistor high-breakdown- voltage p-channel open-drain output with pull-down resistor high-breakdown- voltage p-channel open-drain output with pull-down resistor ttl level input cmos 3-state output high-breakdown- voltage p-channel open-drain output with pull-down resistor cmos compatible input level p4 2 /int 2 C p4 4 /int 4 p4 6 /t1 out , p4 7 /t3 out p4 1 cmos compatible input level cmos 3-state output port p0 port p1 port p2 port p3 port p4 output output output input/output, individual bits output input input/output, individual bits fld automatic dis- play function fld automatic dis- play function fld automatic dis- play function fld automatic dis- play function external interrupt input zero cross detec- tion circuit input (p4 5 ) timer output fldc mode register 1 fldc mode register 2 port p0 segment/digit switch register fldc mode register 1 fldc mode register 2 fldc mode register 1 fldc mode register 2 port p2 digit/port switch register fldc mode register 1 fldc mode register 2 interrupt edge selection register zero cross detection control register timer 12 mode register timer 34 mode register (1) (1) (2) (3) (4) (5) (6) (7) (4) (8)
12 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p6 2 /cntr 0 , p6 3 /cntr 1 p6 4 /s in1 p6 5 /s out1 , p6 6 /s clk11 p6 7 /s rdy1 / cs/s clk12 port p5 pin name input/output i/o format non-port function related sfr s diagram no. p5 0 /s in2 / an 8 p5 1 /s out2 / an 9 , p5 2 /s clk2 / an 10 p5 3 /s rdy2 / an 11 p5 4 /s in3 / an 12 p5 5 /s out3 / an 13 , p5 6 /s clk3 / an 14 p5 7 /s rdy3 / an 15 p6 0 cmos compatible input level cmos 3-state output input/output, individual bits serial i/o2 func- tion i/o a-d conversion in- put serial i/o2 control register ad/da control regis- ter (9) serial i/o3 func- tion i/o a-d conversion in- put serial i/o3 control register ad/da control regis- ter timer 56 mode regis- ter pwm (timer) out- put p6 1 /pwm timer input interrupt edge selec- tion register serial i/o1 func- tion i/o serial i/o1 control register serial i/o automatic transfer control regis- ter cmos compatible input level cmos 3-state output cmos compatible input level high-breakdown- voltage p-channel open-drain output with pull-down resistor high-breakdown- voltage p-channel open-drain output with pull-down resistor cmos compatible input level high-breakdown- voltage p-channel open-drain output p7 0 /an 0 C p7 7 /an 7 p8 0 /seg 8 C p8 7 /seg 15 p9 0 /seg 16 C p9 7 /seg 23 pa 0 /seg 0 C pa 7 /seg 7 pb 0 /x cout , pb 1 /x cin pb 2 /da pb 3 cmos compatible input level cmos 3-state output fld automatic display function a-d conversion in- put i/o for sub-clock generating circuit d-a conversion output ad/da control regis- ter fldc mode register segment/port switch register fldc mode register fldc mode register segment/port switch register cpu mode register ad/da control regis- ter output input/output, individual bits input/output, individual bits port p6 port p7 port p8 port p9 port pa (10) (11) (9) (10) (11) (4) (8) (7) (9) (10) (11) (12) (13) (5) (13) (14) (15) (16) note : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate poten- tial, a current will flow from v cc to v ss through the input-stage gate. port pb cmos compatible input level cmos 3-state output (4)
13 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 4 port block diagram (1) (4) ports p2 4 ?2 7 , p4 1 , p6 0 , pb 3 direction register port latch data bus (3) ports p2 0 ?2 3 (2) ports p1 2 ?1 7 (1) ports p0, p1 0 , p1 1 port latch d/p switch register dimmer signal (note) shift signal to next stage blanking signal for key-scan data bus shift signal from previous stage port latch v ee shift signal from previous stage data bus shift signal to next stage dimmer signal (note) shift signal to next stage data bus shift signal from previous stage port latch s/d switch register local data bus blanking signal for key-scan dimmer signal (note) v ee v ee ] ] ] ] : high-breakdown-voltage p-channel transistor note: the dimmer signal sets the toff timing.
14 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 5 port block diagram (2) direction register port latch data bus port latch dimmer signal (note) data bus v ee ] direction register port latch data bus (6) ports p4 0 , p4 5 data bus int 0 , int 1 interrupt input zero cross detection circuit input (only p4 5 ) local data bus (5) ports p3, p9 int 2 Cint 4 interrupt input cntr 0 ,cntr 1 input timer 1 output selection bit timer 3 output selection bit timer 6 output selection bit timer 1 output timer 3 output timer 6 output ] : high-breakdown-voltage p-channel transistor note: the dimmer signal sets the toff timing. (7) ports p4 2 Cp4 4 , p6 2 , p6 3 (8) ports p4 6 , p4 7 , p6 1
15 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 6 port block diagram (3) (10) ports p5 1 , p5 2 , p5 5 , p5 6 , p6 5 , p6 6 (11) ports p5 3 , p5 7 , p6 7 direction register port latch data bus serial i/o input direction register port latch data bus direction register port latchdata bus direction register port latch data bus (9) ports p5 0 , p5 4 , p6 4 (12) port p7 a-d conversion input analog input pin selection bit serial i/o port selection bit p-channel output disable signal output off control signal a-d conversion input analog input pin selection bit s out or s clk (only p5 2 , p5 6 , p6 6 ) serial clock input s rdy output enable bit serial ready output or s clk cs input a-d conversion input analog input pin selection bit (only p6 7 ) a-d conversion input analog input pin selection bit
16 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 7 port block diagram (4) read data bus ] local data bus (13) ports p8, pa ] : high-breakdown-voltage p-channel transistor note: the dimmer signal sets the toff timing. direction register port latchdata bus d-a conversion output d-a output enable bit direction register port latch data bus sub-clock generating circuit input direction register port latch data bus directionregister port latch s/p switch register dimmer signal (note) port x c switch bit port x c switch bit port pb 1 oscillation circuit port x c switch bit (14) port pb 0 (15) port pb 1 (16) port pb 2
17 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupts interrupts occur by 20 sources: 5 external, 14 internal, and 1 soft- ware. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk instruction interrupt. interrupt operation when an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. the interrupt disable flag is set to inhibit other interrupts from interfering. the corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. notes on use when the active edge of an external interrupt (int 0 to int 4 ) is changed or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. therefore, please take following sequence; (1) disable the external interrupt which is selected. (2) change the active edge. (3) clear the interrupt request bit which is selected to 0. (4) enable the external interrupt which is selected. table 1. interrupt vector addresses and priority interrupt request generating conditions high fffd 16 interrupt source priority low fffc 16 remarks reset (note 2) non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when interrupt interval determination is operating valid when serial i/o ordinary mode is selected valid when serial i/o automatic transfer mode is selected valid when serial i/o2 is se- lected valid when serial i/o3 is se- lected stp release timer underflow 1 notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 /zcr input at detection of either rising or falling edge of int 2 input int 0 int 1 /zcr int 2 remote control/ counter overflow serial i/o1 serial i/o automatic transfer serial i/o2 serial i/o3 timer 1 timer 2 timer 3 timer 4 timer 5 timer 6 int 3 2 3 at 8-bit counter overflow at completion of data transfer at completion of the last data transfer at completion of data transfer at completion of data transfer at timer 1 underflow at timer 2 underflow at timer 3 underflow at timer 4 underflow at timer 5 underflow at timer 6 underflow at detection of either rising or falling edge of int 3 input external interrupt (active edge selectable) valid when int 4 interrupt is selected external interrupt (active edge selectable) valid when a-d conversion in- terrupt is selected at detection of either rising or falling edge of int 4 input at completion of a-d conver- sion at falling edge of the last digit immediately before blanking period starts at rising edge of each digit at brk instruction execution valid when fld blanking in- terrupt is selected valid when fld digit interrupt is selected non-maskable software inter- rupt fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 4 5 6 7 8 9 10 11 12 13 14 15 16 17 int 4 a-d conversion fld blanking fld digit brk instruction
18 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers b7 interrupt edge selection register (intedge : address 003a 16 ) int 0 interrupt edge selection bit int 1 /zcr interrupt edge selection bit int 2 interrupt edge selection bit int 3 interrupt edge selection bit int 4 interrupt edge selection bit int 4 /ad conversion interrupt switch bit cntr 0 pin active edge switch bit cntr 1 pin active edge switch bit b0 0 : falling edge active 1 : rising edge active 0 : no interrupt request issued 1 : interrupt request issued 0 : int 4 interrupt 1 : a-d conversion interrupt 0 : rising edge count 1 : falling edge count b7 interrupt request register 1 (ireq1 : address 003c 16 ) int 0 interrupt request bit int 1 /zcr interrupt request bit int 2 interrupt request bit remote control/counter overflow interrupt request bit serial i/o1 interrupt request bit serial i/o automatic transfer interrupt request bit serial i/o2 interrupt request bit serial i/o3 interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit b0 b7 interrupt request register 2 (ireq2 : address 003d 16 ) timer 3 interrupt request bit timer 4 interrupt request bit timer 5 interrupt request bit timer 6 interrupt request bit int 3 interrupt request bit int 4 interrupt request bit ad conversion interrupt request bit fld blanking interrupt request bit fld digit interrupt request bit not used (returns 0 when read) b0 0 : interrupts disabled 1 : interrupts enabled b7 interrupt control register 1 (icon1 : address 003e 16 ) int 0 interrupt enable bit int 1 /zcr interrupt enable bit int 2 interrupt enable bit remote control/counter overflow interrupt enable bit serial i/o1 interrupt enable bit serial i/o automatic transfer interrupt enable bit serial i/o2 interrupt enable bit serial i/o3 interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit b0 b7 interrupt control register 2 (icon2 : address 003f 16 ) timer 3 interrupt enable bit timer 4 interrupt enable bit timer 5 interrupt enable bit timer 6 interrupt enable bit int 3 interrupt enable bit int 4 interrupt enable bit ad conversion interrupt enable bit fld blanking interrupt enable bit fld digit interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) b0 fig. 8 interrupt control fig. 9 structure of interrupt-related registers interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset
19 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timers the 3819 group has 6 built-in timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. each timer has the 8-bit timer latch. the timers count down. once a timer reaches 00 16 , at the next count pulse the contents of each timer latch is loaded into the corresponding timer, and sets the corresponding interrupt request bit to 1. the count can be stopped by setting the stop bit of each timer to 1. the internal clock f can be set to either the high-speed mode or low-speed mode with the cpu mode register. at the same time, timer internal count source is switched to either f(x in ) or f(x cin ). timer 1 and timer 2 the count sources of timer 1 and timer 2 can be selected by set- ting the timer 12 mode register. a rectangular waveform of timer 1 underflow signal divided by 2 is output from the p4 6 /t1 out pin. the waveform polarity changes each time timer 1 overflows. the active edge of the external clock cntr 0 can be switched with the bit 6 of the interrupt edge selection register. at reset or when executing the stp instruction, all bits of the timer 12 mode register are cleared to 0, timer 1 is set to ff 16 , and timer 2 is set to 01 16 . timer 3 and timer 4 the count sources of timer 3 and timer 4 can be selected by set- ting the timer 34 mode register. a rectangular waveform of timer 3 underflow signal divided by 2 is output from the p4 7 /t3 out pin. the waveform polarity changes each time timer 3 overflows. the active edge of the external clock cntr 1 can be switched with the bit 7 of the interrupt edge selection register. timer 5 and timer 6 the count sources of timer 5 and timer 6 can be selected by set- ting the timer 56 mode register. a rectangular waveform of timer 6 underflow signal divided by 2 is output from the p6 1 /pwm pin. the waveform polarity changes each time timer 6 overflows. timer 6 pwm mode timer 6 can output a rectangular waveform with duty cycle n/(n + m) from the p6 1 /pwm pin by setting the timer 56 mode register (refer to fig. 12). the n is the value set in timer 6 latch (address 0025 16 ) and m is the value in the timer 6 pwm register (address 0027 16 ). if n is 0, the pwm output is l, if m is 0, the pwm out- put is h(n=0 is prior than m=0). in the pwm mode, interrupts occur at the rising edge of the pwm output.
20 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 10 timer block diagram x cin 1/16 p4 6 /t1 out internal system clock selection bit p6 2 /cntr 0 p6 1 /pwm x in p4 6 direction register p4 6 latch 10 01 00 timer 1 count source selection bit timer 3 interrupt request timer 1 interrupt request timer 2 interrupt request timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) timer 3 latch (8) timer 3 (8) 0 1 1/2 timer 1 output selection bit timer 1 count stop bit ff 16 data bus reset stp instruction timer 4 interrupt request timer 5 interrupt request timer 6 interrupt request timer 2 count source selection bit timer 2 count stop bit 10 01 00 timer 3 count source selection bit timer 3 count stop bit timer 4 count source selection bit timer 4 count stop bit timer 5 count source selection bit timer 5 count stop bit timer 6 count source selection bit timer 6 count stop bit 10 01 00 0 1 0 1 0 1 0 1 p4 7 direction register p4 7 latch timer 3 output selection bit p6 1 direction register p6 1 latch timer 6 output selection bit p4 7 /t3 out p6 3 /cntr 1 timer 4 latch (8) timer 4 (8) timer 5 latch (8) timer 5 (8) timer 6 latch (8) timer 6 (8) timer 6 pwm register (8) pwm 1/2 timer 6 operating mode selection bit rising/falling edge switch rising/falling edge switch 01 16 1/2
21 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timer 1 count stop bit 0 : operating 1 : stopped timer 2 count stop bit 0 : operating 1 : stopped timer 1 count source selection bit 0 : f(x in )/16 or f(x cin )/16 1 : f(x cin ) not used (returns 0 when read) timer 2 count source selection bits b5 b4 0 0 : timer 1 underflow 0 1 : f(x cin ) 1 0 : external count input cntr 0 1 1 : not available timer 1 output selection bit (p4 6 ) 0 : i/o port 1 : timer 1 output not used (returns 0 when read) b7 timer 12 mode register (t12m : address 0028 16 ) b0 timer 3 count stop bit 0 : operating 1 : stopped timer 4 count stop bit 0 : operating 1 : stopped timer 3 count source selection bit 0 : f(x in )/16 or f(x cin )/16 1 : timer 2 underflow not used (returns 0 when read) timer 4 count source selection bits b5 b4 0 0 : f(x in )/16 or f(x cin )/16 0 1 : timer 3 underflow 1 0 : external count input cntr 1 1 1 : not available timer 3 output selection bit (p4 7 ) 0 : i/o port 1 : timer 3 output not used (returns 0 when read) timer 34 mode register (t34m : address 0029 16 ) b7 b0 timer 5 count stop bit 0 : operating 1 : stopped timer 6 count stop bit 0 : operating 1 : stopped timer 5 count source selection bit 0 : f(x in )/16 or f(x cin )/16 1 : timer 4 underflow timer 6 operation mode selection bit 0 : timer mode 1 : pwm mode timer 6 count source selection bits b5 b4 0 0 : f(x in )/16 or f(x cin )/16 0 1 : timer 5 underflow 1 0 : timer 4 underflow 1 1 : not available timer 6 (pwm) output selection bit (p6 1 ) 0 : i/o port 1 : timer 6 output not used (returns 0 when read) (do not write 1) b7 timer 56 mode register (t56m : address 002a 16 ) b0 fig. 11 structure of timer-related registers
22 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 12 timing in timer 6 pwm mode t s n 5 t s m 5 t s (n + m) 5 t s timer 6 count source timer 6 pwm output timer 6 interrupt request timer 6 interrupt request note: if the value set in timer 6 is n and the value set in the timer 6 pwm register is m, a pwm waveform with duty cycle n/(n + m) and period (n + m) 5 t s (t s : the frequency of the timer 6 count source) is output.
23 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o the 3819 group has built-in 8-bit clock synchronized serial i/o 5 3 channels (serial i/o1, serial i/o2, and serial i/o3). serial i/o1 builds in the automatic transfer function. the function can be switched to the serial i/o ordinary mode with the serial i/o automatic transfer control register (address 001a 16 ). serial i/o2 and serial i/o3 can be used only in the serial i/o ordi- nary mode. the i/o pins of the serial i/o function are also used as i/o ports p5 and p6 4 Cp6 7 , and their operation is selected with the serial i/o control registers (addresses 0019 16 , 001d 16 , and 001e 16 ). serial i/o control registers (sio1con, sio2con, sio3con) 0019 16 , 001d 16 , 001e 16 each of the serial i/o control registers (addresses 0019 16 , 001d 16 , and 001e 16 ) consists of 8 selection bits which control the serial i/o function.
24 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 13 serial i/o block diagram s clk1 1/8 1/128 1/64 1/32 1/16 si/o automatic transfer ram (0f00 16 to 0f1f 16 ) main data bus local data bus main address bus local address bus si/o automatic transfer controller si/o automatic transfer data pointer serial i/o automatic transfer interrupt request si/o automatic transfer interval register 1/256 internal synchronous clock selection bit synchronous clock selection bit ? ? internal system clock selection bit external clock (note) s rdy1 p6 7 latch cs serial i/o counter 1(3) serial i/o shift register 1(8) ? p6 6 latch ? serial i/o1 port selection bit p6 5 latch ? ? serial i/o1 port selection bit address decorder synchronization circuit frequency divider serial i/o1 interrupt request ? ? x in x cin p6 6 /s clk11 p6 5 /s out1 p6 4 /s in1 p6 7 /s rdy1 / cs/s clk12 s clk2 1/8 1/128 1/64 1/32 1/16 1/256 internal synchronous clock selection bit synchronous clock selection bit ? ? external clock s rdy2 p5 3 latch s rdy2 output selection bit serial i/o counter 2(3) serial i/o shift register 2(8) ? ? serial i/o2 port selection bit p5 1 latch ? ? serial i/o2 port selection bit frequency divider serial i/o2 interrupt request ? p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p5 3 /s rdy2 ? synchronization circuit p5 2 latch s clk3 1/8 1/128 1/64 1/32 1/16 1/256 internal synchronous clock selection bit ? ? external clock s rdy3 p5 7 latch s rdy2 output selection bit serial i/o counter 3(3) serial i/o shift register 3(8) ? ? serial i/o3 port selection bit p5 5 latch ? ? serial i/o3 port selection bit frequency divider serial i/o3 interrupt request ? p5 6 /s clk3 p5 5 /s out3 p5 4 /s in3 p5 7 /s rdy3 ? synchronization circuit p5 6 latch note: selected with the synchronous clock selection bit, s rdy1 output selection bit, serial i/o1 port selection bit (these 3 bits are of the serial i/o1 control register), automatic transfer control bit, and synchronous clock output pin selection bit (these 2 bits are ofthe serial i/o automatic transfer register).
25 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers b0 internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(x in )/8 or f(x cin )/8 0 0 1 : f(x in )/16 or f(x cin )/16 0 1 0 : f(x in )/32 or f(x cin )/32 0 1 1 : f(x in )/64 or f(x cin )/64 1 1 0 : f(x in )/128 or f(x cin )/128 1 1 1 : f(x in )/256 or f(x cin )/256 serial i/o1 port selection bit (p6 5 , p6 6 , and p6 7 ] ) 0 : i/o port 1 : s out1 ,s clk11 ,and s clk12 ] output pins s rdy1 output selection bit (p6 7 ) 0 : i/o port 1 : s rdy1 /cs ] output pin (note) transfer direction selection bit 0 : lsb first 1 : msb first synchronous clock selection bit 0 : external clock 1 : internal clock p6 5 /s out1 p-channel output disable bit 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) b7 serial i/o1 control register (sio1con(sc1) : address 0019 16 ) b0 internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(x in )/8 or f(x cin )/8 0 0 1 : f(x in )/16 or f(x cin )/16 0 1 0 : f(x in )/32 or f(x cin )/32 0 1 1 : f(x in )/64 or f(x cin )/64 1 1 0 : f(x in )/128 or f(x cin )/128 1 1 1 : f(x in )/256 or f(x cin )/256 serial i/o2 port selection bit (p5 1 , and p5 2 ) 0 : i/o port 1 : s out2 and s clk2 output pins s rdy2 output selection bit (p5 3 ) 0 : i/o port 1 : s rdy2 output pin transfer direction selection bit 0 : lsb first 1 : msb first synchronous clock selection bit 0 : external clock 1 : internal clock p5 1 /s out2 p-channel output disable bit 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) b7 serial i/o2 control register (sio2con(sc2) : address 001d 16 ) b0 internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(x in )/8 or f(x cin )/8 0 0 1 : f(x in )/16 or f(x cin )/16 0 1 0 : f(x in )/32 or f(x cin )/32 0 1 1 : f(x in )/64 or f(x cin )/64 1 1 0 : f(x in )/128 or f(x cin )/128 1 1 1 : f(x in )/256 or f(x cin )/256 serial i/o3 port selection bit (p5 5 and p5 6 ) 0 : i/o port 1 : s out3 and s clk3 output pins s rdy3 output selection bit (p5 7 ) 0 : i/o port 1 : s rdy3 and s clk3 output pins transfer direction selection bit 0 : lsb first 1 : msb first synchronous clock selection bit 0 : external clock 1 : internal clock p5 5 /s out3 p-channel output disable bit 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) b7 serial i/o3 control register (sio3con(sc3) : address 001e 16 ) ] : valid only in serial i/o automatic transfer mode. note: when the external clock is selected in the serial i/o1 automatic transfer mode, the s rdy1 signal pin becomes the cs signal input pin. fig. 14 structure of serial i/o control registers
26 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (1) serial i/o ordinary mode either an internal clock or an external clock can be selected as the synchronous clock for serial i/o transfer. a dedicated divider is built in as the internal clock for selecting of 6 clocks. if internal clock is selected, transfer starts with a write signal to a serial i/o register (addresses 001b 16 , 001f 16 , or 0026 16 ). after 8 bits have been transferred, the s out pin goes to high impedance state. if external clock is selected, control the clock externally be- cause the contents of the serial i/o register continue to shift during inputting the transfer clock. in this case, note that the s out pin does not go to high impedance state at the comple- tion of data transfer. the interrupt request bit is set at the completion of the trans- fer of 8 bits, regardless of whether the internal or external clock is selected. fig. 15 serial i/o timing in the serial i/o ordinary mode (for lsb first) (2) serial i/o automatic transfer mode the serial i/o1 has the automatic transfer function. for auto- matic transfer, switch to the automatic transfer mode by setting the serial i/o automatic transfer control register (ad- dress 001a 16 ). the following memory spaces and registers used to enable automatic transfer mode: ? 32-byte serial i/o automatic transfer ram ? a serial i/o automatic transfer control register ? a serial i/o automatic transfer interval register ? a serial i/o automatic transfer data pointer when using serial i/o automatic transfer, set the serial i/o1 control register (address 0019 16 ) in the same way as the se- rial i/o ordinary mode. however, note that when external clock is selected, port p6 7 becomes the cs input pin by set- ting the bit 4 (the s rdy1 output selection bit ) of the serial i/o1 control register to 1. serial i/o automatic transfer control register (sioac) 001a 16 the serial i/o automatic transfer control register (address 001a 16 ) consists of 4 bits which control automatic transfer. fig. 16 structure of serial i/o automatic transfer control register d 1 synchronous clock interrupt request bit set if internal clock is selected, the s out pin goes to high impedance state at the completion of data transfer. note : d 0 d 2 d 3 d 4 d 5 d 6 d 7 (note) transfer clock serial i/o register write signal serial i/o output s out serial i/o input s in receive enable signal s rdy automatic transfer control bit 0 : serial i/o ordinary mode (serial i/o1 interrupt) 1 : automatic transfer mode (serial i/o1 automatic transfer interrupt) automatic transfer start bit 0 : transfer completion 1 : transferring(starts by writing 1) transfer mode switch bit 0 : fullduplex(transmit and receive) mode 1 : transmit-only mode synchronous clock output pin selection bit 0 : s clk11 1 : s clk12 not used (return 0 when read) b7 serial i/o automatic transfer control register (sioac : address 001a 16 ) b0
27 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o automatic transfer data pointer (siodp) 0018 16 the serial i/o automatic transfer data pointer (address 0018 16 ) consists of 5 bits which indicate addresses in serial i/o automatic transfer ram (the value which adds 0f00 16 to the serial i/o auto- matic transfer data pointer is actual address in memory). set the value (the number of transfer data-1) to the serial i/o au- tomatic transfer data pointer for specifying the storage address of first data. l serial i/o automatic transfer ram the serial i/o automatic transfer ram is the 32 bytes from ad- dress 0f00 16 to address 0f1f 16 . l setting of serial i/o automatic transfer data when data is stored in the serial i/o automatic transfer ram, store the first data at the address set with the serial i/o auto- matic transfer data pointer so that the last data can be stored at address 0f00 16 . serial i/o automatic transfer interval register (sioai) 001c 16 the serial i/o automatic transfer interval register (address 001c 16 ) consists of a 5-bit counter that determines the transfer in- terval ti during automatic transfer. when writing the value n to the serial i/o automatic transfer inter- val register, ti=(n+2) 5 tc (tc: the length of one bit of the transfer clock) occurs. however, note that this transfer interval setting is valid only when selecting the internal clock as the clock source. fig. 17 bit allocation of serial i/o automatic transfer ram fig. 18 serial i/o automatic transfer interval timing bit address 0f00 16 0f01 16 0f02 16 0f1d 16 0f1e 16 0f1f 16 76 543210 do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 t c t i 1-byte data transfer clock serial i/o output s out serial i/o input s in di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7
28 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l setting of serial i/o automatic transfer timing the timing of serial i/o automatic transfer is set with the serial i/o1 control register (address 0019 16 ) and the serial i/o auto- matic transfer interval register (address 001c 16 ). the serial i/o1 control register sets the transfer clock speed, and the serial i/o automatic transfer interval register sets the serial i/o automatic transfer interval. this setting of transfer in- terval is valid only when selecting the internal clock as the clock source. l start of serial i/o automatic transfer automatic transfer mode is set by writing 1 to the bit 0 of the serial i/o automatic transfer control register (address 001a 16 ), then automatic transfer starts by writing 1 to the bit 1. the bit 1 of the serial i/o automatic transfer control register is always 1 during automatic transfer; writing 0 can complete the serial i/o automatic transfer. l operation in serial i/o automatic transfer modes there are two modes for serial i/o automatic transfer: full du- plex mode and transmit-only mode. either internal or external clock can be selected for each of these modes. (2.1) operation in full duplex mode in full duplex mode, data can be transmitted and received at the same time. data in the automatic transfer ram is transmitted in sequence in accordance with the serial i/o automatic transfer data pointer and simultaneously reception data is written to the auto- matic transfer ram. the transfer timing of each bit is the same as that in ordinary op- eration mode, and the transfer clock stops at h after eight transfer clocks are counted. when selecting the internal clock, the transfer clock remains at h for the time set with the serial i/o automatic transfer interval regis- ter, then the data at the next address (the address is indicated with the serial i/o automatic transfer data pointer) are transferred. if when selecting the external clock, the setting of the automatic transfer interval register is invalid, so control the transfer clock ex- ternally. the last data transfer completes when the contents of the serial i/o automatic transfer pointer reach 00 16 . at that point, the serial i/o automatic transfer interrupt request bit is set to 1 and the bit 1 of the serial i/o automatic transfer control register is cleared to 0 to complete the serial i/o automatic transfer. (2.2) operation in transmit-only mode the operation in transmit-only mode is the same as that in full du- plex mode, except for that data is not transferred from the serial i/o1 register to the serial i/o automatic transfer ram. fig. 19 serial i/o1 register transfer operation in full duplex mode ? ? ? do 7 do 6 do 5 do 4 do 3 do 2 do 1 do 0 transfer clock di 1 di 0 do 7 do 6 do 5 do 4 do 3 do 2 di 2 di 1 di 7 di 6 di 5 di 4 di 3 di 2 di 1 di 0 do 7 do 6 do 5 do 4 do 3 do 7 do 6 do 5 do 4 do 3 do 2 do 1 di 0 transfer direction selection bit lsb first (sc1 5 = 0 ) : msb msb first (sc1 5 = 1 ) : lsb lsb msb s out s in serial i/o1 register di 0
29 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2.3) when selecting the internal clock when selecting the internal clock, the p6 7 /s rdy1 /cs/s clk12 pin can be used as the s rdy1 pin by setting sc1 4 to 1. when selecting the internal clock, the p6 7 pin can be used as the synchronous clock output pin s clk12 by setting sioac 3 to 1. in this case, the s clk11 pin goes to high impedance state. select the function of the p6 7 /s rdy1 /cs/s clk12 and p6 6 /s clk11 with the following registers (refer to table 2): l the bit 3 (sc1 3 ), the bit 4(sc1 4 ), and the bit 6(sc1 6 ) of the se- rial i/o1 control register l the bit 3 (sioac 3 ) of the serial i/o automatic transfer control register when using both the s clk11 and s ckl12 by switching, switch the p6 7 /s rdy1 /cs/s clk12 to the p6 7 (sc1 4 =0) and set the p6 7 direc- tion register to input mode. note that switch sioac 3 during h of transfer clock at the completion of automatic transfer. table 2. s clk11 and s clk12 selection sc1 6 1 sc1 4 0 sc3 3 1 sioac 3 0 1 p6 6 /s clk11 s clk11 high impedance p6 7 /s clk12 p6 7 s clk12 note : sc1 3 : serial i/o1 port selection bit sc1 4 : s rdy1 output selection bit sc1 6 : synchronous clock selection bit sioac 3 : synchronous clock output pin selection bit fig. 20 timing diagram during serial i/o automatic transfer (internal clock selected, s rdy used) fig. 21 timing during serial i/o automatic transfer (internal clock selected, s clk11 and s clk12 used) di 6 di 0 do 0 do 7 bit 1 write signal of serial i/o automatic transfer control register serial i/o output s out serial i/o input s in di 0 transfer interval bit 1 of serial i/o automatic transfer control register write signal from ram to serial i/o1 register write signal from serial i/o1 register to ram transfer clock data pointer (internal or s clk output) receive enabled signal s rdy n-1 0 n do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 6 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 7 do 0 di 7 bit 1 write signal of serial i/o automatic transfer control register serial i/o output s out serial i/o input s in transfer interval bit 1 of serial i/o automatic transfer control register write signal from ram to serial i/o1 register write signal from serial i/o1 register to ram data pointer m-1 0 m do 0 bit 3 of serial i/o automatic transfer control register transfer clock (internal) s clk11 output s clk12 output n do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 0 do 6 do 7 do 0 do 1 do 2 do 3 di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 0 di 0 di 1 di 2 di 3 di 6
30 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 3. p6 7 /s rdy1 /cs selection (2.4) when selecting the external clock when selecting the external clock, the internal clock and the set- ting of transfer interval with the serial i/o automatic transfer interval register are invalid, but the serial i/o output pin s out1 and the internal transfer clock can be controlled from the outside by setting the s rdy1 pin to the cs (input) pin. when the cs input is l, the s out1 pin and the internal transfer clock are enabled. when the cs input is h, the s out1 pin goes to high impedance state and the internal transfer clock goes to h. select the function of the p6 7 /s rdy1 /cs/s clk12 with the following registers (refer to table ga-2): l the bit 4 (sc1 4 ) and the bit 6 (sc1 6 ) of the serial i/o1 control register l the bit 0 (sioac 0 ) of the serial i/o automatic transfer control register switch the cs pin from l to h or from h to l during h of the transfer clock (s clk11 input) after transferring 1-byte data. when selecting the external clock, set the external clock to l af- ter 9 cycles or more of the internal clock f after setting the start bit. after transferring 1-byte data, leave 11 cycles or more of the internal clock f free for the transfer interval. when not using the cs input, note that the s out pin will not go to high impedance state, even after transfer is completed. when not using the cs input, or when cs is l, control the exter- nal clock because the data in the serial i/o register will continue to shift while the external clock is input, even after the completion of automatic transfer (note that the automatic transfer interrupt re- quest bit is set and the bit 1 of the serial i/o automatic transfer register is cleared at the point when the specified number of bytes of data have been transferred.) sc1 6 0 sc1 4 0 1 sioac 0 5 0 1 p6 7 /s rdy1 /cs p6 7 s rdy1 cs note : sc1 4 : s rdy1 output selection bit sc1 6 : synchronous clock selection bit sioac 0 : automatic transfer control bit fig. 22 timing during serial i/o automatic transfer (external clock selected) x bit 1 write signal of serial i/o automatic transfer control register serial i/o output s out serial i/o input s in note: data marked with x is invalid. bit 1 of serial i/o automatic transfer control register write signal from ram to serial i/o1 register write signal from serial i/o1 register to ram transfer clock (internal) data pointer cs n-1 n do 0 x transfer clock s clk input external input x do 1 do 2 do 3 do 4 do 5 do 6 do 7 di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 x xx
31 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter the functional blocks of the a-d converter are described below. a-d conversion register (ad) 002d 16 the a-d conversion register is a read-only register that stores the result of an a-d conversion. this register should not be read dur- ing a-d conversion. ad/da control register (adcon) 002c 16 the ad/da control register controls the a-d and the d-a conver- sion process. bits 0 to 3 of this register select analog input pins. bit 4 is the ad conversion completion bit. the value of this bit re- mains at 0 during an a-d conversion, then changes to 1 when the a-d conversion is completed. the a-d conversion starts by writing 0 to this bit. bit 6 controls the output of d-a converter. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref by 256, and outputs the divided voltages. channel selector the channel selector selects one of the input ports p7 7 /an 7 Cp7 0 / an 0 , p5 7 /s rdy3 /an 15 Cp5 0 /s in2 /an 8 , and inputs to the compara- tor. comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad conversion interrupt request bit to 1. note that the comparator is constructed linked to a capacitor, so set f(x in ) to 500 khz or more during a-d conversion. note : when using the a-d conversion interrupt, set the int 4 /ad conver- sion interrupt switch bit (the bit 5 of the interrupt selection register) to 1. fig. 23 structure of a-d control register analog input pin selection bits b3 b2 b1 b0 0 0 0 0 : p7 0 /an 0 0 0 0 1 : p7 1 /an 1 0 0 1 0 : p7 2 /an 2 0 0 1 1 : p7 3 /an 3 0 1 0 0 : p7 4 /an 4 0 1 0 1 : p7 5 /an 5 0 1 1 0 : p7 6 /an 6 0 1 1 1 : p7 7 /an 7 1 0 0 0 : p5 0 /s in2 /an 8 1 0 0 1 : p5 1 /s out2 /an 9 1 0 1 0 : p5 2 /s clk2 /an 10 1 0 1 1 : p5 3 /s rdy2 /an 11 1 1 0 0 : p5 4 /s in3 /an 12 1 1 0 1 : p5 5 /s out3 /an 13 1 1 1 0 : p5 6 /s clk3 /an 14 1 1 1 1 : p5 7 /s rdy3 /an 15 ad conversion completion bit 0 : conversion in progress 1 : conversion completed not used (returns 0 when read) da output enable bit 0 : disable 1 : enable not used (returns 0 when read) b7 ad/da control register (adcon : address 002c 16 ) b0
32 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 24 a-d converter block diagram d-a converter the 3819 group has internal d-a converter with 8-bit resolutions 5 1 channel. d-a conversion is performed by setting the value in the d-a con- version register. the result of d-a conversion is output from the da pin by setting the da output enable bit to 1 . at this time, the corresponding bit (pb 2 /da) of the port pb direction register should be set to 0 (input status). the output analog voltage v is determined with the value n (n: decimal number) in the d-a conversion register as follows: v=v ref 5 n/256 (n=0 to 255) ] v ref : the reference voltage at reset, the d-a conversion register is cleared to 00 16 , the da output enable bits are cleared to 0, and the pb 2 /da pin goes to high impedance state. the d-a output does not build in a buffer, so connect an external buffer when driving a low-impedance load. set v cc to 3.0 v or more when using the d-a converter. fig. 25 d-a converter block diagram fig. 26 equivalent connection circuit of d-a converter channel selector a-d control circuit a-d conversion register resistor ladder v ref av ss comparator a-d conversion interrupt request b7 b0 4 8 p7 0 /an 0 (address 002d 16 ) ad-da control register (address 002c 16 ) p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 p5 0 /s in2 /an 8 p5 1 /s out2 /an 9 p5 2 /s clk2 /an 10 p5 3 /s rdy2 /an 11 p5 4 /s in3 /an 12 p5 5 /s out3 /an 13 p5 6 /s clk3 /an 14 p5 7 /s rdy3 /an 15 data bus data bus pb 2 /da d-a conversion register (8) r-2r resistor ladder da output enable bit av ss v ref "0" "1" msb "0" "1" r 2r lsb pb 2 /da d-a conversion register da output enable bit 2r 2r 2r 2r 2r 2r 2r r r rrrr 2r
33 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers g1 (seg pa) 0f80 16 fld automatic display ram g2 (seg pa) g15 (seg pa) g16 (seg pa) g1 (seg p8) g2 (seg p8) 0f8f 16 0f90 16 g15 (seg p8) g16 (seg p8) g1 (seg p9) g2 (seg p9) 0f9f 16 0fa0 16 g15 (seg p9) g16 (seg p9) g1 (seg p3) g2 (seg p3) 0faf 16 0fb0 16 g15 (seg p3) g16 (seg p3) g1 (seg p0) g2 (seg p0) 0fbf 16 0fc0 16 g15 (seg p0) g16 (seg p0) g1 (seg p1) g2 (seg p1) 0fcf 16 0fd0 16 g15 (seg p1) g16 (seg p1) 0fdf 16 local address bus main address bus address decoder fld data pointer (address 0038 16 ) fld data pointer reload register (address 0038 16 ) timing generator fld blanking interrupt fld digit interrupt pa 1 /seg 1 s/p pa 0 /seg 0 s/p pa 2 /seg 2 s/p pa 3 /seg 3 s/p pa 4 /seg 4 s/p pa 5 /seg 5 s/p pa 6 /seg 6 s/p pa 7 /seg 7 s/p 0014 16 0035 16 8 p8 1 /seg 9 s/p p8 0 /seg 8 s/p p8 2 /seg 10 s/p p8 3 /seg 11 s/p p8 4 /seg 12 s/p p8 5 /seg 13 s/p p8 6 /seg 14 s/p p8 7 /seg 15 s/p 0010 16 0034 16 8 p9 1 /seg 17 p9 0 /seg 16 p9 2 /seg 18 p9 3 /seg 19 p9 4 /seg 20 p9 5 /seg 21 p9 6 /seg 22 p9 7 /seg 23 0012 16 8 p0 1 /seg 33 /dig 1 s/d p0 0 /seg 32 /dig 0 s/d p0 2 /seg 34 /dig 2 s/d p0 3 /seg 35 /dig 3 s/d p0 4 /seg 36 /dig 4 s/d p0 5 /seg 37 /dig 5 s/d p0 6 /seg 38 /dig 6 s/d p0 7 /seg 39 /dig 7 s/d 0000 16 0032 16 8 p2 1 /dig 17 d/p p2 0 /dig 16 d/p p2 2 /dig 18 d/p p2 3 /dig 19 d/p 4 fldc mode register 1 (address 0036 16 ) p1 1 /seg 41 /dig 9 s/d p1 0 /seg 40 /dig 8 s/d p1 2 /dig 10 p1 3 /dig 11 p1 4 /dig 12 p1 5 /dig 13 p1 6 /dig 14 p1 7 /dig 15 0002 16 0037 16 8 p3 1 /seg 25 p3 0 /seg 24 p3 2 /seg 26 p3 3 /seg 27 p3 4 /seg 28 p3 5 /seg 29 p3 6 /seg 30 p3 7 /seg 31 0006 16 8 main data bus local data bus 0004 16 0033 16 fld controller the 3819 group has fluorescent display (fld) drive and control circuits. the fld controller consists of the following components: ? 42 pins for segments ? 20 pins for digits ? fldc mode register 1 ? fldc mode register 2 ? fld data pointer ? fld data pointer reload register ? port p0 segment/digit switch register ? port p2 digit/port switch register ? port pa segment/port switch register ? port p8 segment/port switch register ? 96-byte fld automatic display ram the segment pins can be used from 16 up to 42 pins (maximum) and the digit pins can be used from 6 up to 16 pins (maximum). the segment and the digit pins can be used up to 52 pins (maxi- mum) in total. in the fld automatic display mode ports p1 2 to p1 7 become digit pins dig 10 to dig 15 automatically. fig. 27 fld control circuit block diagram
34 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fldc mode registers (fldm 1, fldm 2) 0036 16 , 0037 16 the fldc mode register 1 (address 0036 16 ) and fldc mode reg- ister 2 (address 0037 16 ) are a seven bit register and an eight bit register respectively which are used to control the fld automatic display and set the blanking time t scan for key-scan. fig. 28 structure of fldc mode register 1 fig. 29 structure of fldc mode register 2 t scan control bits b1 b0 0 0 : 0 fld digit interrupt (at rising edge of each digit) 0 1 : 1 5 t disp 1 0 : 2 5 t disp 1 1 : 3 5 t disp t off control bits (setting of digit/segment off time) b5 b4 b3 b2 0 0 0 0 : 1/16 5 t disp 0 0 0 1 : 2/16 5 t disp 0 0 1 0 : 3/16 5 t disp 0 0 1 1 : 4/16 5 t disp 0 1 0 0 : 5/16 5 t disp 0 1 0 1 : 6/16 5 t disp 0 1 1 0 : 7/16 5 t disp 0 1 1 1 : 8/16 5 t disp 1 0 0 0 : 9/16 5 t disp 1 0 0 1 : 10/16 5 t disp 1 0 1 0 : 11/16 5 t disp 1 0 1 1 : 12/16 5 t disp 1 1 0 0 : 13/16 5 t disp 1 1 0 1 : 14/16 5 t disp 1 1 1 0 : 15/16 5 t disp 1 1 1 1 : 16/16 5 t disp not used (returns 0 when read) high-breakdown-voltage drivability selection bit 0 : strong drivability 1 : weak drivability b7 fldc mode register 1 (fldm 1 : address 0036 16 ) b0 fld blanking interrupt (at falling edge of the last digit) automatic display control bit(p0, p1, p2 0 ?2 3 , p3, p8, p9, pa) 0 : ordinary mode 1 : automatic display mode display start bit 0 : display stopped 1 : display in progress (display starts by writing ??to this bit which is set to ?? t disp control bits (digit time setting, at 8 mhz oscillation frequency) b5 b4 b3 b2 0 0 0 0 : 128 m s 0 0 0 1 : 256 m s 0 0 1 0 : 384 m s 0 0 1 1 : 512 m s 0 1 0 0 : 640 m s 0 1 0 1 : 768 m s 0 1 1 0 : 896 m s 0 1 1 1 : 1024 m s 1 0 0 0 : 1152 m s 1 0 0 1 : 1280 m s 1 0 1 0 1 1 1 1 pl 0 segment/digit switch bit 0 : digit 1 : segment pl 1 segment/digit switch bit 0 : digit 1 : segment b7 fldc mode register 2 (fldm 2 : address 0037 16 ) b0 not available
35 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers dig 10 g 10 dig 9 g 11 dig 10 g 10 pa 7 pa 1 pa 0 pa 3 pa 2 pa 5 pa 4 pa 6 p8 7 p8 1 p8 0 p8 3 p8 2 p8 5 p8 4 p8 6 seg 23 seg 17 seg 16 seg 19 seg 18 seg 21 seg 20 seg 22 port pa (has the segment/port switch register) number of segments number of digits 0 0 0 0 0 0 0 0 24 8 port p8 (has the segment/port switch register) 0 0 0 0 0 0 0 0 port p9 (segment only) pa 7 pa 1 pa 0 pa 3 pa 2 pa 5 pa 4 pa 6 seg 15 p8 1 p8 0 p8 3 p8 2 seg 13 seg 12 seg 14 seg 23 seg 17 seg 16 seg 19 seg 18 seg 21 seg 20 seg 22 0 0 0 0 0 0 0 0 30 10 1 0 0 0 0 1 1 1 seg 7 seg 1 seg 0 seg 3 seg 2 seg 5 seg 4 seg 6 seg 15 seg 9 seg 8 seg 11 seg 10 seg 13 seg 12 seg 14 seg 23 seg 17 seg 16 seg 19 seg 18 seg 21 seg 20 seg 22 1 1 1 1 1 1 1 1 36 16 1 1 1 1 1 1 1 1 seg 39 seg 33 seg 32 seg 35 seg 34 seg 37 seg 36 seg 38 dig 8 g 8 port p3 (segment only) number of segments number of digits 24 8 port p0 (has the segment/digit switch register) 1 1 1 1 1 1 1 1 port p1 (has the segment/digit switch register) seg 39 seg 33 seg 32 seg 35 seg 34 seg 37 seg 36 seg 38 30 10 1 1 1 1 1 1 1 1 dig 7 g 13 seg 33 seg 32 seg 35 seg 34 dig 5 g 15 dig 4 g 16 dig 6 g 14 36 16 0 1 1 1 1 0 0 0 seg 31 seg 25 seg 24 seg 27 seg 26 seg 29 seg 28 seg 30 seg 31 seg 25 seg 24 seg 27 seg 26 seg 29 seg 28 seg 30 seg 31 seg 25 seg 24 seg 27 seg 26 seg 29 seg 28 seg 30 0 0 dig 9 g 7 dig 10 g 6 dig 11 g 5 dig 12 g 4 dig 13 g 3 dig 14 g 2 dig 15 g 1 seg 40 1 1 seg 41 dig 11 g 9 dig 12 g 8 dig 13 g 7 dig 14 g 6 dig 15 g 5 dig 8 g 12 0 0 dig 11 g 9 dig 12 g 8 dig 13 g 7 dig 14 g 6 dig 15 g 5 port p2 (has the digit/port switch register) 1 1 1 1 dig 16 g 4 dig 17 g 3 dig 18 g 2 dig 19 g 1 1 1 1 1 dig 16 g 4 dig 17 g 3 dig 18 g 2 dig 19 g 1 0 0 0 0 p2 0 p2 1 p2 2 p2 3 l pins for fld automatic display ports p0, p1, p2 0 Cp2 3 , p3, p8, p9, and pa is selected for the fld automatic display function by setting the automatic display control bit of the fldc mode register 2 (address 0037 16 ) to 1. when using the fld automatic display mode, set the number of segments and digits for each port. table 4. pins in fld automatic display mode port name pa 0 Cpa 7 p8 0 Cp8 7 p9 0 Cp9 7 p3 0 Cp3 7 p0 0 Cp0 7 p1 0 , p1 1 p1 2 Cp1 7 p2 0 Cp2 3 automatic display pins seg 0 Cseg 7 or pa 0 Cpa 7 seg 8 Cseg 15 or p8 0 Cp8 7 seg 16 Cseg 23 seg 24 Cseg 31 seg 32 Cseg 41 or dig 0 Cdig 9 dig 10 Cdig 15 dig 16 Cdig 19 or p2 0 Cp2 3 setting method the individual bits of the segment/port switch register (address 0035 16 ) can be set each pin to either segment (1) or general-purpose i/o port (0). the individual bits of the segment/port switch register (address 0034 16 ) can be used to set each pin to either segment (1) or general-purpose i/o port (0). none (segment only) none (segment only) the individual bits of the segment/digit switch register (address 0032 16 ) and the bit 6, 7 of the fldc mode register 2 can be used to set each pin to segment (1) or digit (0). (note) none (digit only) the individual bits of the digit/port switch register (address 0033 16 ) can be used to set each pin to digit (1) or general-purpose output port (0). (note) note : be sure to set digits in sequence. fig. 30 segment/digit setting example
36 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l fld automatic display ram the fld automatic display ram area is the 96 bytes from ad- dresses 0f80 16 to 0fdf 16 . the fld automatic display ram area can store 6-byte segment data up to 16 digits (maximum). addresses 0f80 16 to 0f8f 16 are used for pa segment data, addresses 0f90 16 to 0f9f 16 are used for p8 segment data, addresses 0fa0 16 to 0faf 16 are used for p9 segment data, addresses 0fb0 16 to 0fbf 16 are used for p3 segment data, addresses 0fc0 16 to 0fcf 16 are used for p0 segment data, and addresses 0fd0 to 0fdf 16 are used for p1 segment data. fld data pointer and fld data pointer reload register (flddp) 0038 16 both the fld data pointer and fld data pointer reload register are 7-bit registers allocated at address 0038 16 . when writing data to this address, the data is written to the fld data pointer reload register, when reading data from this address, the value in the fld data pointer is read. the fld data pointer indicates the data address in the fld auto- matic display ram to be transferred to a segment. the fld data pointer reload register indicates the first digit address of the most significant segment. the value which adds 0f80 16 to these data is actual address in memory. the contents of the fld data pointer indicate the first address of segment p1(the contents of the fld data pointer reload register) at the start of automatic display. the fldc data pointer content changes repeatedly as follows: when transferring the segment p1 data to the segment, the content decreases by C16; when transfer- ring the segment p0 data, it decreases by C16; when transferring the segment p3 data, it decreases by C16; when transferring the segment p9 data, it decreases by C16; when transferring the seg- ment p8 data, it decreases by C16; when transferring the segment pa data, it increases by +79. once it reaches 00, at the next tim- ing the value in the fld data pointer reload register is transferred to the fld data pointer. in this way, the 6-byte data of p1, p0, p3, p9, p8 and pa segments for 1 digit are transferred.
37 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0f80 16 7 bit address seg 7 6 seg 6 5 seg 5 4 seg 4 3 seg 3 2 seg 2 1 seg 1 0 seg 0 the last digit (the last data of segment pa) 0f81 16 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 0f8e 16 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 0f8f 16 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 0f90 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 0f91 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 segment pa data area the last digit (the last data of segment p8) segment p8 data area 0f9e 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 0f9f 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 0fa0 16 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 0fa1 16 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 the last digit (the last data of segment p9) segment p9 data area 0fae 16 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 0faf 16 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 0fb0 16 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 0fb1 16 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 the last digit (the last data of segment p3) segment p3 data area 0fbe 16 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 0fbf 16 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 0fc0 16 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 0fc1 16 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 the last digit (the last data of segment p0) segment p0 data area 0fce 16 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 0fcf 16 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 0fd0 16 seg 41 seg 40 0fd1 16 seg 41 seg 40 the last digit (the last data of segment p1) segment p1 data area 0fde 16 seg 41 seg 40 0fdf 16 seg 41 seg 40 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fig. 31 fld automatic display ram and bit allocation
38 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l data setup when data is stored in the fld automatic display ram, the last data of segment pa is stored at address 0f80 16 , the last data of segment p8 is stored at address 0f90 16 , the last data of segment p9 is stored at address 0fa0 16 , the last data of segment p3 is stored at address 0fb0 16 , the last data of seg- ment p0 is stored at address 0fc0 16 , and the last data of segment p1 is stored at address 0fd0 16 to allocate in se- quence from the last data respectively. the first data of the segment pa, p8, p9, p3, p0, and p1 is stored at an address which adds the value of (the digit numberC1) to the corre- sponding address 0f80 16 , 0f90 16 , 0fa0 16 , 0fb0 16 , 0fc0 16 , and 0fd0 16 . set the low-order 4 bits of the fld data pointer reload register to the value given by the number of digitsC1. 1 is always writ- ten to bit 6 and bit 4, and 0 is always written to bit 5. note that 0 is always read from bits 6, 5 and 4 when reading. fig. 32 example of using the fld automatic display ram (1) for 30 segments and 15 digits (fld data pointer reload register = 14) 0f80 16 7 bit address 6543 2 10 0f81 16 0f82 16 0f83 16 0f84 16 0f85 16 0f86 16 0f87 16 0f88 16 0f89 16 0f8a 16 0f8b 16 0f8c 16 0f8d 16 0f8e 16 0f8f 16 0f90 16 0f91 16 0f92 16 0f93 16 0f94 16 0f95 16 0f96 16 0f97 16 0f98 16 0f99 16 0f9a 16 0f9b 16 0f9c 16 0f9d 16 0f9e 16 0f9f 16 0fa0 16 0fa1 16 0fa2 16 0fa3 16 0fa4 16 0fa5 16 0fa6 16 0fa7 16 0fa8 16 0fa9 16 0faa 16 0fab 16 0fac 16 0fad 16 0fae 16 0faf 16 note : shaded areas are used. for 30 segments and 15 digits (fld data pointer reload register = 14) 0fb0 16 7 bit address 6543 2 10 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 0fca 16 0fcb 16 0fcc 16 0fcd 16 0fce 16 0fcf 16 0fd0 16 0fd1 16 0fd2 16 0fd3 16 0fd4 16 0fd5 16 0fd6 16 0fd7 16 0fd8 16 0fd9 16 0fda 16 0fdb 16 0fdc 16 0fdd 16 0fde 16 0fdf 16
39 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 33 example of using the fld automatic display ram (2) (continued) for 42 segments and 8 digits (fld data pointer reload register = 7) 0f80 16 7 bit address 6543 2 10 0f81 16 0f82 16 0f83 16 0f84 16 0f85 16 0f86 16 0f87 16 0f88 16 0f89 16 0f8a 16 0f8b 16 0f8c 16 0f8d 16 0f8e 16 0f8f 16 0f90 16 0f91 16 0f92 16 0f93 16 0f94 16 0f95 16 0f96 16 0f97 16 0f98 16 0f99 16 0f9a 16 0f9b 16 0f9c 16 0f9d 16 0f9e 16 0f9f 16 0fa0 16 0fa1 16 0fa2 16 0fa3 16 0fa4 16 0fa5 16 0fa6 16 0fa7 16 0fa8 16 0fa9 16 0faa 16 0fab 16 0fac 16 0fad 16 0fae 16 0faf 16 note : shaded areas are used. for 42 segments and 8 digits (fld data pointer reload register = 7) 0fb0 16 7 bit address 6543 2 10 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 0fca 16 0fcb 16 0fcc 16 0fcd 16 0fce 16 0fcf 16 0fd0 16 0fd1 16 0fd2 16 0fd3 16 0fd4 16 0fd5 16 0fd6 16 0fd7 16 0fd8 16 0fd9 16 0fda 16 0fdb 16 0fdc 16 0fdd 16 0fde 16 0fdf 16
40 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers g n g n-1 g n-2 g 1 t scan t disp segment output fld digit interrupt occurs at the rising edge of each digit fld blanking interrupt occurs at the falling edge of the last digit segment setting by software t off t disp digit segment l timing setting the digit time (t disp ) can be set with the fldc mode register 2 (address 0037 16 ). the t scan and digit/segment off time (t off ) can be set with the fldc mode register 1 (address 0036 16 ). note that flickering will occur if the repetition frequency (1/ (t disp 5 number of digits + t scan )) is an integral multiple of the digit timing t disp . l fld automatic display start to perform fld automatic display, set the following registers. ? port p0 segment/digit switch register ? port p2 digit/port switch register ? port p8 segment/port switch register ? port pa segment/port switch register ? fldc mode register 1 ? fldc mode register 2 ? fld data pointer automatic display mode is selected by writing 1 to the bit 0 of the fldc mode register 2 (address 0037 16 ), and the auto- matic display is started by writing 1 to the bit 1. during automatic display bit 1 of the fldc mode register 2 al- ways keeps 1, automatic display can be interrupted by writing 0 to the bit 1. l key-scan if key-scan is performed with the segment during the key-scan blanking period t scan , take the following sequence: 1. write 0 to the bit 0 (automatic display control bit) of the fldc mode register 2 (address 0037 16 ). 2. set the port corresponding to the segment for key-scan to the output port. 3. perform the key-scan. 4. after the key-scan is performed, write 1 (automatic display mode) to the bit 0 of fldc mode register 2 (address 0037 16 ). note on performance of key-scan in the above 1 to 4 sequence. 1. do not write 0 to the bit 1 of fldc mode register 2 (ad- dress 0037 16 ). 2. do not write 1 to the port corresponding to the digit. fig. 34 fldc timing
41 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupt interval determination function the 3819 group builds in an interrupt interval determination circuit. this interrupt interval determination circuit has an 8-bit binary up counter. using this counter, it determines a duration of time from the rising transition (falling transition) of an input signal pulse on the p4 2 /int 2 pin to the rising transition (falling transition) of the signal pulse that is input next. how to determine the interrupt interval is described below. enable the int 2 interrupt by setting the bit 2 of the interrupt con- trol register 1 (address 003e 16 ). select the rising interval or falling interval by setting the bit 2 of the interrupt edge selection register (address 003a 16 ). set the bit 0 of the interrupt interval determination control regis- ter (address 0031 16 ) to 1 (interrupt interval determination operating). a select the sampling clock of 8-bit binary up counter by setting the bit 1 of the interrupt interval determination control register. when writing 0, f(x in )/256 is selected (the sampling interval: 32 m s at f(x in ) = 8.38 mhz) ; when 1, f(x in )/512 is selected (the sampling interval: 64 m s at f(x in ) = 8.38 mhz). ? when the signal of polarity which is set on the int 2 pin (rising or falling transition) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock. ? when the signal of polarity above ? is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 0030 16 ), and the remote control interrupt request occurs. immediately after that, the 8-bit binary up counter is cleared to 00 16 . the 8-bit binary up counter con- tinues to count up again from 00 16 . ? when count value reaches ff 16 , the 8-bit binary up counter stops counting up. then, simultaneously when the next counter sampling clock is input, the counter sets value ff 16 to the in- terrupt interval determination register to generate the counter overflow interrupt request. noise filter the p4 2 /int 2 pin builds in the noise filter. the noise filter operation is described below. select the sampling clock of the input signal with the bits 2 and 3 of the interrupt interval determination control register. when not using the noise filter, set 00 2 . the p4 2 /int 2 input signal is sampled in synchronization with the selected clock. when sampling the same level signal in series, the signal is recognized as the interrupt signal, and the interrupt request occurs. when setting the bit 4 of interrupt interval determination control register to 1, the interrupt request can occur at both rising and falling edges. when using the noise filter, set the minimum pulse width of the int 2 input signal to 2 cycles or more. note : in the low-speed mode (cm 7 =1), the interrupt interval determination function can not operate. fig. 35 block diagram of interrupt interval datermination circuit int 2 interrupt input the counter sampling clock selection bit f(x in )/256 f(x in )/512 noise filter sampling clock selection bit one-sided/both-sided detection selection bit noise filter 8-bit binary up counter interrupt interval determination register the counter overflow interrupt request or remote control interrupt request address 0030 16 data bus divider 1/256 1/64 1/128 f(x in )
42 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 36 structure of interrupt interval determination control register fig. 37 interrupt interval determination operation example (at rising edge active) interrupt interval determination circuit operating selection bit 0 : stopped 1 : operating counter sampling clock selection bit 0 : f(x in )/256 1 : f(x in )/512 noise filter sampling clock selection bits(int 2 ) 0 0 : filter stop 0 1 : f(x in )/64 1 0 : f(x in )/128 1 1 : f(x in )/256 one-sided/both-sided edge detection selection bit 0 : one-sided edge detection 1 : both-sided edge detection not used (return 0 when read) b7 interrupt interval determination control register (iidcon : address 0031 16 ) b0 noise filter sampling clock (when iidcon 4 = 0) int 2 pin acceptance of interrupt counter sampling clock 6 3 ff 6 3 ff 1 8-bit binary up counter value interrupt interval determination register value remote control interrupt request remote control interrupt request counter overflow interrupt request remote control interrupt request n 2 3 4 5 6 0 1 2 3 0 1 fe ff 0 0 n
43 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 38 interrupt interval determination operation example (at both-sided edge active) noise filter sampling clock (when iidcon 4 = 1) int 2 pin acceptance of interrupt counter sampling clock ff n 1 8-bit binary up counter value interrupt interval determination register value remote control interrupt request n n 0 1 0 1 fe ff 0 0 0 1 2 3 4 0 1 0 1 remote control interrupt request 1 4 remote control interrupt request 1 remote control interrupt request 4 1 remote control interrupt request 1 1 remote control interrupt request 1 1 ff counter overflow interrupt request
44 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers zero cross detection circuit the zero cross detection circuit compares the voltage applied to p4 5 /int 1 /zcr pin and v ss . the result can be read from the zero cross detection circuit input bit (bit 7) of the zero cross detection control register. it is set to 1 when the input voltage is higher than v ss and to 0 when it is lower than v ss . the input signal to p4 5 / int 1 /zcr pin can select to either pass through the zero cross de- tection comparator or not to do. when using 100 v ac as input signal, insert an external circuit be- tween it and p4 5 /int 1 /zcr pin. set the input current limiting resistors used in the external circuit to a value which satisfies the absolute maximum rating of port p4 5 . fig. 39 external circuit example for zero cross detection fig. 41 block diagram of zero cross detection circuit fig. 40 structure of zero cross detection control register v cc r 1 r 2 p4 5 /int 1 /zcr v ss 100v ac zero cross detection on/off selection bit 0 : without passing through zero cross detection comparator 1 : passing through zero cross detection comparator not used (returns 0 when read) noise filter sampling clock selection bits (int 1 ) b3 b2 0 0 : not use noise filter 0 1 : f(x in )/64 or f(x cin )/64 1 0 : f(x in )/128 or f(x cin )/128 1 1 : f(x in )/256 or f(x cin )/256 one-sided/both-sided edge detection selection bit 0 : one-sided edge detection 1 : both-sided edge detection not used (return 0 when read) zero cross detection circuit input bit (read only) 0 : less than 0 v 1 : 0 v or more b7 zero cross detection control register (zcrcon : address 0039 16 ) b0 p4 5 /int 1 /zcr zero cross detection on/off selection bit 0 1 zero cross detection circuit input bit rising/falling edge switch noise filter when not using the filter when using the filter int 1 /zcr interrupt request one-sided/both-sided edge detection selection bit noise filter sampling clock selection bit zero cross detection comparator f(x cin ) f(x in ) divider 1/64 1/256 1/28
45 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers noise filter the noise filter uses a sampling clock to remove the noise compo- nent digitally from the input signal of p4 5 /int 1 /zcr pin. the sampling clock can be selected from 8 m s, 16 m s, or 32 m s (at f(x in )= 8.38 mhz) and this is used to change the noise component to be removed. it is also possible to generate an internal trigger and int 1 /zcr interrupt request directly without passing through the noise filter. when passing through the noise filter, either both- sided edge detection or one-sided edge detection can be selected as the interrupt request generating source. the zero cross detec- tion control register is used for this selection. furthermore, switch between rising edge and falling edge is performed with the bit 1 of the interrupt edge selection register (address 003a 16 ). fig. 42 noise filter circuit diagram fig. 43 timing of noise filter circuit input signal from p4 5 /int 1 /zcr pin sampling clock reset r qd c r qd c qs r r qd c 1 0 one-sided/both-sided edge detection selection bit (bit 4 of zcrcon) int 1 /zcr interrupt request c ba reset sampling clock input signal from p4 5 /int 1 /zcr pin a b c (one-sided edge) (both-sided edge) int 1 /zcr interrupt request p4 5 /int 1 /zcr (note 1) 0 v (note 2) switched with bit 4 of zcrcon : ignored this because of treating this as noise : int 1 /zcr interrupt request occurs notes 1 2
46 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 m s or more. then the reset pin is returned to an h level (the power source voltage should be between 2.8 v and 5.5 v, and x in oscillation is stable), reset is released. in order to give the x in clock time to stabilize, internal operation does not begin until after about 4000 x in clock cycles (256 cycles of f(x in )/16) are completed. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order) and ad- dress fffc 16 (low-order). make sure that the reset input voltage is 0.5 v or less for 2.8 v of v cc . fig. 44 example of reset circuit fig. 45 reset sequence note : reset release voltage : v cc = 2.8 v power source voltage poweron (note) v cc reset v cc reset power source voltage detection circuit 0 v reset input voltage 0.2v cc 0 v about 4000 x in clock cycles reset internal reset f(x in ) and f( f ) are in the relationship : f(x in ) = 8 ? f( f ) a question mark (?) indicates an undefined state that depends on the previous state. notes 1 : 2 : ? ?? sync data address f x in reset address from vector table ? ? fffc fffd ad h , ad l ? ? ? ad l ad h
47 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 46 internal status at reset 0 1001000 00 16 (0000 16 ) ? ? ? (1) port p0 5 : undefined the contents of all other registers and ram are undefined at reset, so set their initial values. note : register contentsaddress 00 16 (0002 16 ) ? ? ? (2) port p1 00 16 (0004 16 ) ? ? ? (3) port p2 0f 16 (0005 16 ) ? ? ? (4) port p2 direction register 00 16 (0006 16 ) ? ? ? (5) port p3 00 16 (0008 16 ) ? ? ? (6) port p4 00 16 (0009 16 ) ? ? ? (7) port p4 direction register 00 16 (000a 16 ) ? ? ? (8) port p5 00 16 (000b 16 ) ? ? ? (9) port p5 direction register 00 16 (000c 16 ) ? ? ? (10) port p6 00 16 (000d 16 ) ? ? ? (11) port p6 direction register 00 16 (000e 16 ) ? ? ? (12) port p7 00 16 (000f 16 ) ? ? ? (13) port p7 direction register 00 16 (0010 16 ) ? ? ? (14) port p8 00 16 (0011 16 ) ? ? ? (15) port p8 direction register 00 16 (0012 16 ) ? ? ? (16) port p9 00 16 (0014 16 ) ? ? ? (17) port pa 00 16 (0015 16 ) ? ? ? (18) port pa direction register 00 16 (0016 16 ) ? ? ? (19) port pb 00 16 (0017 16 ) ? ? ? (20) port pb direction register 00 16 (0019 16 ) ? ? ? (21) serial i/o1 control register 00 16 (001a 16 ) ? ? ? (22) serial i/o automatic transfer 00 16 (001c 16 ) ? ? ? (23) serial i/o automatic transfer 00 16 (001d 16 ) ? ? ? (24) serial i/o2 control register 00 16 (001e 16 ) ? ? ? (25) serial i/o3 control register ff 16 (0020 16 ) ? ? ? (26) timer 1 01 16 (0021 16 ) ? ? ? (27) timer 2 ff 16 (0022 16 ) ? ? ? (28) timer 3 ff 16 (0023 16 ) ? ? ? (29) timer 4 ff 16 (0024 16 ) ? ? ? (30) timer 5 ff 16 (0025 16 ) ? ? ? (31) timer 6 register contentsaddress 00 16 (0028 16 ) ? ? ? (32) timer 12 mode register 00 16 (0029 16 ) ? ? ? (33) timer 34 mode register 00 16 (002a 16 ) ? ? ? (34) timer 56 mode register 00 16 (002b 16 ) ? ? ? (35) d-a conversion register 10 16 (002c 16 ) ? ? ? (36) ad/da control register 00 16 (0031 16 ) ? ? ? (37) interrupt interval determination control register 00 16 (0032 16 ) ? ? ? (38) port p0 segment/digit switch register 00 16 (0033 16 ) ? ? ? (39) port p2 digit/port switching register 00 16 (0034 16 ) ? ? ? (40) port p8 segment/port switch register 00 16 (0035 16 ) ? ? ? (41) port pa segment/port switch 00 16 (0036 16 ) ? ? ? (42) fldc mode register 1 00 16 (0037 16 ) ? ? ? (43) fldc mode register 2 00 16 (0039 16 ) ? ? ? (44) zero cross detection control register 00 16 (003a 16 ) ? ? ? (45) interrupt edge selection register (003b 16 ) ? ? ? (46) cpu mode register 00 16 (003c 16 ) ? ? ? (47) interrupt request register 1 00 16 (003d 16 ) ? ? ? (48) interrupt request register 2 00 16 (003e 16 ) ? ? ? (49) interrupt control register 1 00 16 (003f 16 ) ? ? ? (50) interrupt control register 2 5 (ps) ? ? ? (51) processor status register contents of address fffd 16 (pc h ) ? ? ? (52) program counter control register interval register contents of address fffc 16 (pc l ) ? ? ? 5555 1 55
48 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers clock generating circuit the 3819 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after poweron, only the x in oscillation circuit starts oscillation, and x cin and x cout pins function as i/o ports. frequency control middle-speed mode the internal clock f is the frequency of x in divided by 8. after re- set, this mode is selected. high-speed mode the internal clock f is half the frequency of x in . low-speed mode the internal clock f is half the frequency of x cin . note : if you switch the mode between middle/high-speed and low-speed, stabilize both x in and x cin oscillations. the sufficient time is re- quired for the x cin oscillation to stabilize, especially immediately after poweron and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3f(x cin ). low-power dissipation mode when stopping the main clock x in in the low-speed mode, the low- power dissipation operation starts. to stop the main clock, set the bit 5 of the cpu mode register to 1. when the main clock x in is restarted, set enough time for oscillation to stabilize by program- ming. the low-power dissipation operation 200 m a or less (at f(x in ) = 32 khz) can be realized by reducing the x cin Cx cout drivability. to re- duce the x cin Cx cout drivability, clear the bit 3 of the cpu mode register to 0. at reset or when executing the stp instruction, this bit is set to 1 and strong drivability is selected to help the oscilla- tion to start. oscillation control stop mode if the stp instruction is executed, the internal clock f stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in or x cin divided by 16 is in- put to timer 1, and the output of timer 1 is connected to timer 2. the bits of the timer 12 mode register are cleared to 0. set the timer 1 and timer 2 interrupt enable bits to disabled (0) before ex- ecuting the stp instruction. oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock f is not supplied to the cpu until timer 1 underflows. when using an external resonator, it is neces- sary for oscillating to stabilize. wait mode if the wit instruction is executed, the internal clock f stops at an h level. the states of x in and x cin are the same as the state be- fore executing the wit instruction. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. fig. 47 ceramic resonator external circuit fig. 48 external clock input circuit x cin x cout c cin c cout r d r f x in x out c in c out x cin x cout x in x out open open external oscillation circuit or pulse external oscillation circuit v cc v ss v cc v ss
49 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes main clock stop bit (note 3) middle/ high-speed mode high-speed mode or low-speed mode main clock division ratio selection bit (note 3) middle-speed mode timing f (internal clock) wit instruction qs r stp instruction x in x out port x c switch bit (note 3) internal system clock selection bit low-speed mode (note 1, 3) timer 1 count source selection bit (note 2) x cin x cout 1 0 reset interrupt disable flag i interrupt request 1/4 1/2 1/2 timer 1 1 0 1 0 1 0 sq r qs r stp instruction 1 : when selecting the low-speed mode, set the port x c switch bit to 1. 2 : refer to the structure of timer 12 mode register. 3 : refer to the structure of cpu mode register (next page). fig. 49 clock generating circuit block diagram
50 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 50 state transitions of system clock switch the mode by the allows shown between the mode blocks. (do not switch between the mode directly without an allow.) the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. timer operates in the wait mode. when the stop mode is released in middle/high-speed mode, a delay of approximately 0.5 ms occurs automatically by timer 1. when the stop mode is released in low-speed mode, a delay of approximately 0.125 s occurs automatically by timer 1. the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock. low power dissipation mode ( f =16 khz) cm 7 = 1 (32 khz selected) cm 6 = 0 (high-speed) cm 5 = 1 (x in stopped) cm 4 = 1 (32 khz oscillating) cm 6 1 0 cm 4 0 1 b7 cpu mode register (cpum (cm) : address 003b 16 ) cm 4 : port x c switch bit 0 : i/o port function 1 : x cin -x cout oscillating function cm 5 : main clock (x in -x out ) stop bit 0 : oscillating 1 : stopped cm 6 : main clock division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) cm 7 : internal system clock selection bit 0 : x in -x out selected (middle/high-speed mode) 1 : x cin -x cout selected (low-speed mode) b0 notes 1 : 2 : 3 : 4 : 5 : reset cm 6 1 0 cm 4 1 0 cm 4 1 0 cm 6 1 0 cm 4 1 0 cm 7 1 0 cm 6 1 0 cm 7 1 0 cm 5 1 0 cm 6 1 0 cm 5 1 0 high-speed mode ( f = 4 mhz) cm 7 = 0 (8 mhz selected) cm 6 = 0 (high-speed) cm 5 = 0 (x in oscillating) cm 4 = 1 (32 khz oscillating) cm 6 1 0 middle-speed mode ( f =1 mhz) cm 7 = 0 (8 mhz selected) cm 6 = 1 (middle-speed) cm 5 = 0 (x in oscillating) cm 4 = 1 (32 khz oscillating) middle-speed mode ( f =1 mhz) cm 7 = 0 (8 mhz selected) cm 6 = 1 (middle-speed) cm 5 = 0 (x in oscillating) cm 4 = 0 (32 khz stopped) high-speed mode ( f = 4 mhz) cm 7 = 0 (8 mhz selected) cm 6 = 0 (high-speed) cm 5 = 0 (x in oscillating) cm 4 = 0 (32 khz stopped) low-speed mode ( f =16 khz) cm 7 = 1 (32 khz selected) cm 6 = 1 (middle-speed) cm 5 = 0 (x in oscillating) cm 4 = 1 (32 khz oscillating) low-speed mode ( f = 16 khz) cm 7 = 1 (32 khz selected) cm 6 = 0 (high-speed) cm 5 = 0 (x in oscillating) cm 4 = 1 (32 khz oscillating) low power dissipation mode ( f =16 khz) cm 7 = 1 (32 khz selected) cm 6 = 1 (middle-speed) cm 5 = 1 (x in stopped) cm 4 = 1 (32 khz oscillating) cm 6 1 0 cm 5 0 1 cm 6 1 0 cm 5 1 0
51 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after execut- ing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flag are invalid. the carry flag can be used to indicate whether a carry or borrow has occurred. initialize the carry flag before each calculation. clear the carry flag before an adc and set the flag before an sbc. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. ? the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction register as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o when using an external clock, input h to the external clock input pin and clear the serial i/o interrupt request bit before executing serial i/o transfer and serial i/o automatic transfer. when using the internal clock, set the synchronous clock to inter- nal clock, then clear the serial i/o interrupt request bit before executing a serial i/o transfer and serial i/o automatic transfer. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is 500 khz or more during an a-d conver- sion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in or x cin frequency. at the stp instruction release at the stp instruction release, all bits of the timer 12 mode regis- ter are cleared. the x cout drivability selection bit (the cpu mode register) is set to 1 (high drive) in order to start oscillating.
52 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical copies) prom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after writing, the procedure shown in figure 51 is recommended to verify programming. package 100p6s-a 100d0 name of programming adapter pca4738f-100a pca4738l-100a fig. 51 programming and testing of one time prom version the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution : functional check in target device programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer
53 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers absolute maximum ratings conditions symbol ratings unit parameter power source voltage pull-down power source voltage input voltage p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 input voltage p4 0 , p4 5 input voltage p8 0 Cp8 7 , pa 0 Cpa 7 input voltage reset, x in input voltage x cin output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , pa 0 Cpa 7 output voltage p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 , x out , x cout power dissipation operating temperature storage temperature v cc v ee v i v i v i v i v i v o v o p d t opr t stg C0.3 to 7.0 v cc C40 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 v cc C40 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 v cc C40 to v cc +0.3 C0.3 to v cc + 0.3 600 C10 to 85 C40 to 125 v v v v v v v v v mw c c all voltages are based on v ss . output transistors are cut off. t a = 25c recommended operating conditions (vcc = 4.0 to 5.5 v, t a = C10 to 85c, unless otherwise noted) min. 4.0 2.8 v cc C38 2.0 3.0 0 0.75v cc 0.4v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 0 typ. 5.0 5.0 0 0 max. 5.5 5.5 v cc v cc v cc v cc v cc v cc v cc v cc v cc 0.25v cc 0.16v cc 0.2v cc 0.2v cc 0.2v cc symbol v cc v ss v ee v ref av ss v ia v ih v ih v ih v ih v ih v il v il v il v il v il parameter power source voltage power source voltage pull-down power source voltage analog reference voltage (when using a-d converter) analog reference voltage (when using d-a converter) analog power source voltage analog input voltage an 0 Can 15 h input voltage p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 h input voltage p2 4 Cp2 7 h input voltage p8 0 Cp8 7 , pa 0 Cpa 7 h input voltage reset h input voltage x in , x cin l input voltage p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 l input voltage p2 4 Cp2 7 l input voltage p8 0 Cp8 7 , pa 0 Cpa 7 l input voltage reset l input voltage x in , x cin unit v v v v v v v v v v v v v v v v v v high-speed mode middle/low-speed mode limits
54 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , (note 1) pa 6 , pa 7 recommended operating conditions (vcc = 4.0 to 5.5 v, t a = C10 to 85c, unless otherwise noted) ma ma ma ma ma ma ma ma ma ma ma ma khz mhz khz C240 C60 100 C120 C30 50 C40 C10 10 C18 C5.0 5.0 250 8.4 50 min. typ. max. symbol parameter unit s i oh(peak) s i ol(peak) s i oh(avg) s i ol(avg) i oh(peak) i oh(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) limits h total peak output current p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pa 0 Cpa 5 , (note 1) pb 0 Cpb 3 l total peak output current p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , (note 1) pb 0 Cpb 3 h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , (note 1) pa 6 , pa 7 h total average output current p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pa 0 Cpa 5 , (note 1) pb 0 Cpb 3 l total average output current p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , (note 1) pb 0 Cpb 3 h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , (note 2) pa 0 Cpa 7 h peak output current p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , (note 2) pb 0 Cpb 3 l peak output current p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , (note 3) pb 0 Cpb 3 h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , (note 3) pa 0 Cpa 7 h average output current p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , (note 3) pb 0 Cpb 3 l average output current p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , (note 3) pb 0 Cpb 3 clock input frequency for timers 2 and 4 (duty cycle 50%) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (note 4, 5) notes 1 : the total output current is the sum of all the currents flowing through all the applicable ports.the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current in an average value measured over 100 ms. 4: when the oscillation frequency has a 50% duty cycle. 5: when using the microcomputer in low-speed operation mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. 32.768
55 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers electrical characteristics (vcc = 4.0 to 5.5 v, t a = C10 to 85c, unless otherwise noted) v v v v v v m a m a m a m a m a m a m a m a m a m a v min. typ. max. symbol parameter limits unit test conditions v oh v oh v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC i h i h i h i h i l i l i l i l i load i leak v ram h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , pa 0 Cpa 7 h output voltage p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 l output voltage p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 hysteresis int 0 Cint 4 , s in1 , s in2 , s in3 , s clk11 , s clk2 , s clk3 , cs, cntr 0 , cntr 1 hysteresis reset, x in hysteresis x cin h input current p2 4 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 h input current p8 0 Cp8 7 , pa 0 Cpa 7 (note) h input current reset, x cin h input current x in l input current p2 4 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , pb 0 Cpb 3 l input current p8 0 Cp8 7 , pa 0 Cpa 7 (note) l input current reset, x cin l input current x in i oh =C18 ma i oh =C10 ma i ol =10 ma when using a non-port function v i =v cc v i =v cc v i =v cc v i =v cc v i =v ss v i =v ss v i =v ss v i =v ss v cc C2.0 v cc C2.0 150 2 0.4 0.5 0.5 4.0 C4.0 500 2.0 5.0 5.0 5.0 C5.0 C5.0 C5.0 900 C10 5.5 output load current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p9 0 Cp9 7 output leakage current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , pa 0 Cpa 7 ram hold voltage v ee =v cc C36 v, v ol =v cc , output transistors off v ee =v cc C38 v, v ol =v cc C38 v, output transistors off when clock is stopped note : except when reading ports p8 or pa.
56 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers electrical characteristics (v cc = 4.0 to 5.5 v, t a = C10 to 85c, unless otherwise noted) symbol test conditions ? high-speed mode f(x in ) = 8.4 mhz f(x cin ) = 32 khz output transistors off ? high-speed mode f(x in ) = 8.4 mhz (in wit state) f(x cin ) = 32 khz output transistors off ? middle-speed mode f(x in ) = 8.4 mhz f(x cin ) = stopped output transistors off ? middle-speed mode f(x in ) = 8.4 mhz (in wit state) f(x cin ) = stopped output transistors off ? low-speed mode f(x in ) = stopped, f(x cin ) = 32 khz low-power dissipation mode set (cm 3 ) = 0 output transistors off ? low-speed mode f(x in ) = stopped f(x cin ) = 32 khz (in wit state) low-power dissipation mode set (cm 3 ) = 0 output transistors off increase at a-d converter operating f(x in ) = 8.4 mhz increase at zero cross detection (p4 5 = v cc ) all oscillation stopped (in stp state) output transistors off limits min. typ. 7.5 1 3 1 60 20 0.6 1 0.1 max. 15 200 40 1 10 unit ma ma ma ma m a m a ma ma m a t a = 25c t a = 85c i cc parameter power source current
57 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers zero cross detection input characteristics (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C10 to 85c, unless otherwise noted) symbol f zcr d v t parameter input frequency of zero cross detection voltage error of zero cross detection distinction test conditions 50 hz or 60 hz limits min. C100 typ. 50, 60 0 max. 1000 100 unit hz mv a-d converter characteristics (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C10 to 85c, high-speed operation mode f(x in ) = 500 khz to 8.4 mhz, unless otherwise noted) symbol C C t conv i vref i ia r ladder parameter resolution absolute accuracy (excluding quantization error) conversion time reference power source input current analog port input current ladder resistor test conditions v cc = v ref = 5.12 v v ref = 5 v limits min. 49 50 max. 8 2.5 50 200 5.0 unit bits lsb t c ( f ) m a m a k w typ. 1 150 0.5 35 d-a converter characteristics (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, v ref = 3.0 to v cc , t a = C10 to 85c, unless otherwise noted) symbol C C t su r o i vref parameter resolution absolute accuracy setting time output resistor reference power source input current (note) test conditions limits min. 1 max. 8 1.0 2.5 3 4 3.2 unit bits % % m s k w ma typ. 2.5 v cc = 4.0 to 5.5 v v cc = 3.0 to 5.5 v note : exclude currents flowing through the a-d converter ladder resistor fig. 52 zero cross detection input characteristics 100v ac p4 5 /int 1 /zcr clamp correction input waveform zero cross detection comparator output 5.7 v 0 v C 0.7 v v i v t 1/f zcr
58 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p5 6 /s clk3 , p5 2 /s clk2 , p6 6 /s clk11 serial clock output port note : ports p8 and pa need external resistors. c l p0, p1, p2 0 Cp2 3 , p3, p8, p9, pa high-breakdown-voltage p-channel open-drain output port c l (note) v ee symbol t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(xc in ) t wh(xc in ) t wl(xc in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(s clk Cs in ) t h(s clk Cs in ) timing requirements (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C10 to 85c, unless otherwise noted) parameter reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width sub-clock input cycle time (x cin input) sub-clock input h pulse width sub-clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 Cint 4 input h pulse width int 0 Cint 4 input l pulse width serial i/o clock input cycle time serial i/o clock input h pulse width serial i/o clock input l pulse width serial i/o input setup time serial i/o input hold time limits min. 2.0 119 30 30 20 5.0 5.0 4.0 1.6 1.6 80 80 1.0 400 400 200 200 typ. max. unit m s ns ns ns m s m s m s m s m s m s ns ns m s ns ns ns ns switching characteristics (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C10 to 85c, unless otherwise noted) symbol t wh(s clk ) t wl(s clk ) t d(s clk Cs out ) t v(s clk Cs out ) t r(s clk ) t f(s clk ) t r(pchCstrg) t f(pchCweak) parameter serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time serial i/o output hold time serial i/o clock output rising time serial i/o clock output falling time high-breakdown-voltage p-channel open- drain output rising time (note 1) test conditions c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf v ee = v cc C36 v limits min. t c(s clk ) /2C160 t c(s clk ) /2C160 0 typ. 55 1.8 max. 0.2t c(s clk ) 40 40 unit ns ns ns ns ns ns ns m s notes 1 : when the bit 7 of the fldc mode register 1 (address 0036 16 ) is at 0. 2: when the bit 7 of the fldc mode register 1 (address 0036 16 ) is at 1. fig. 53 circuit for measuring output switching characteristics high-breakdown-voltage p-channel open- drain output falling time (note 2) c l = 100 pf v ee = v cc C36 v
59 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing diagram t c(x in ) t wl(x in ) t wh(x in ) t w(reset) t wl(cntr) t wh(cntr) t c(s clk ) 0.8v cc 0.2v cc 0.2v cc 0.8v cc int 0 - int 4 reset 0.8v cc x in 0.2v cc 0.2v cc s clk 0.8v cc t d(s clk - s out ) t h(s clk - s in ) t f t wl(s clk ) t wh(s clk ) s in s out t r 0.8v cc 0.2v cc cntr 0 cntr 1 t c(cntr) t wl(int) t wh(int) 0.8v cc 0.2v cc t c(x cin ) t wl(x cin ) t wh(x cin ) 0.8v cc x cin 0.2v cc t su(s in - s clk ) t v(s clk - s out )
60 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers power source current characteristic examples figures 54 and 55 show power source current characteristic examples. [measuring condition : 25 c, f(x cin ) = 32 khz, a-d conversion operating, in high-speed mode] fig. 54 power source current characteristic example fig. 55 power source current characteristic example (in wait mode) [measuring condition : 25 c, f(x cin ) = 32 khz, a-d conversion operating, in high-speed mode] 0 0 frequency f(x in )(mhz) power source current (ma) rectangular waveform 10 8 6 5 4 3 2 108 6 4 2 1 9 7 9 7 5 3 1 at 5.0 v 8.4 0 0 1.0 0.8 0.6 0.5 0.4 0.3 0.2 10 8 6 4 2 1 0.9 at 5.0 v 0.7 9 7 5 3 0.1 8.4 frequency f(x in )(mhz) power source current (ma) rectangular waveform
61 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers port standard characteristic examples figures 56, 57, and 58 show port standard characteristic examples. fig. 56 standard characteristic example of high-breakdown-voltage p-channel open-drain output port fig. 57 standard characteristic example of cmos output port at p-channel drive [port p8 7 i oh Cv oh characteristic] (pins with same characteristic : p0, p1, p2 0 Cp2 3 , p3, p8, p9, pa) (pins with same characteristic : p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , 4 7 , p5, p6, p7, pb) [port p7 7 i oh Cv oh characteristic (p-channel drive)] 0123456 0 ?0 ?0 ?0 ?0 ?0 v oh (v) i oh (ma) vcc = 5.0v 25 ? vcc = 3.0v 25 ? vcc = 3.0v 90 ? vcc = 5.0v 90 ? vcc = 5.5v 90 ? vcc = 5.5v 25 ? 01 234 5 6 0 ?0 ?0 ?0 ?0 ?00 v oh (v) i oh (ma) vcc = 3.0 v 90 ? vcc = 3.0 v 25 ? vcc = 5.0 v 90 ? vcc = 5.5 v 90 ? vcc = 5.5 v 25 ? vcc = 5.0 v 25 ?
62 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 58 standard characteristic example of cmos output port at n-channel drive [port p7 7 i ol Cv ol characteristic (n-channel drive)] (pins with same characteristic : p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , 4 7 , p5, p6, p7, pb) 01 234 5 6 0 10 20 30 40 50 v ol (v) i ol (ma) vcc = 3.0 v 90 ? vcc = 3.0 v 25 ? vcc = 5.0 v 90 ? vcc = 5.5 v 90 ? vcc = 5.0 v 25 ? vcc = 5.5 v 25 ?
63 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d conversion standard characteristics figure 59 shows the a-d conversion standard characteristics. the lower-side line on the graph indicates the absolute precision error. it represents the deviation from the ideal value. for example, the conversion of output code from 00 16 to 01 16 occurs ideally at the point of an 0 = 10 mv, but the measured value is C4 mv. accordingly, the measured point of conversion is represented as 10 C 4 = 6 mv. the upper-side line on the graph indicates the width of input voltages equivalent to output codes. for example, the measured width of the input voltage for output code 49 16 is 23 mv, so the differential nonlinear error is represented as 23 C 20 = 3 mv (0.1 lsb). fig. 59 a-d conversion standard characteristics m38197ma-000fp a-d converter step width measurement measured when a power source voltage is stable in the high-speed mode
64 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers d-a conversion standard characteristics figure 60 shows the d-a conversion standard characteristics. the lower-side line on the graph indicates the absolute precision error. in this case, it represents the difference between the ideal analog output value for an input code and the measured value. the upper-side line on the graph indicates the change width of output analog value to a one-bit change of input code. fig. 60 d-a conversion standard characteristics m38197eafp d-a converter step width measurement measured when a power source voltage is stable in the high-speed mode
65 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when interrupt interval determination operates valid when serial i/o ordinary mode is selected valid when serial i/o automatic transfer mode is selected valid when serial i/o 2 is selected valid when serial i/o 3 is selected stp release timer underflow external interrupt (active edge selectable) valid when int 4 interrupt is selected external interrupt (active edge selectable) valid when a-d converter interrupt is selected valid when fld blanking interrupt is selected valid when fld digit interrupt is selected non-maskable software interrupt functional description supplement interrupt 3819 group permits interrupts on the basis of 20 sources. it is vector interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. this priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 5. table 5. interrupt sources, vector addresses and interrupt priority fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 interrupt sources reset (note) int 0 interrupt int 1 /zcr interrupt int 2 interrupt remote control/counter overflow interrupt serial i/o 1 interrupt serial i/o 1 automatic transfer interrupt serial i/o 2 interrupt serial i/o 3 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 4 interrupt timer 5 interrupt timer 6 interrupt int 3 interrupt int 4 interrupt a-d conversion interrupt fld blanking interrupt fld digit interrupt brk instruction interrupt high-order low-order vector addresses note : reset functions in the same way as an interrupt with the highest priority.
66 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing after interrupt the interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. figure 61 shows a timing chart after an interrupt occurs, and figure 62 shows the time up to execution of the interrupt processing routine. fig. 61 timing chart after an interrupt occurs fig. 62 time up to execution of the interrupt processing routine : cpu operation code fetch cycle (this is an internal signal which cannot be observed from the external unit.) : vector address of each interrupt : jump destination address of each interrupt : ?0 16 ? or ?1 16 sync b l , b h a l , a h sps generation of interrupt request main routine interrupt processing routine 7 to 23 cycles (at performing 8.4 mhz, 1.7 m s to 5.5 m s) 2 cycles 5 cycles start of interrupt processing 0 to 16* cycles * : at execution of div instruction waiting time for post-processing of pipeline stack push and vector fetch f data bus not used pc h pc l ps a l a h address bus s , sps s-2 , spss-1, sps pc b l b h a l , a h sync rd wr
67 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter a-d conversion is started by setting a-d conversion completion bit to 0. during a-d conversion, internal operations are performed as follows. 1. after the start of a-d conversion, a-d conversion register goes to 00 16 . 2. the highest-order bit of a-d conversion register is set to 1, and the comparison voltage vref is input to the comparator. then, vref is compared with analog input voltage v in . 3. as a result of comparison, when vref < v in , the highest-order bit of a-d conversion register becomes 1. when vref > v in , the highest-order bit becomes 0. by repeating the above operations up to the lowest-order bit of the a-d conversion register, an analog value converts into a digital value. a-d conversion completes at 50 clock cycles (11.9 m s at f(x in ) = 8.4 mhz) after it is started, and the result of the conversion is stored into the a-d conversion register. concurrently with the completion of a-d conversion, a-d conversion interrupt request occurs, so that the a-d conversion interrupt request bit is set to 1. relative formula for a reference voltage v ref of a-d converter and vref when n = 0 vref = 0 when n = 1 to 255 vref = 5 (nC0.5) n : the value of a-d converter (decimal numeral) v ref 256 table 6. change of a-d conversion register during a-d conversion at start of conversion first comparison second comparison third comparison after completion of eighth comparison value of comparison voltage (v ref ) *1 : a result of the first comparison *3 : a result of the third comparison *5 : a result of the fifth comparison *7 : a result of the seventh comparison *2 : a result of the second comparison *4 : a result of the fourth comparison *6 : a result of the sixth comparison *8 : a result of the eighth comparison 0 2 v ref 512 v ref C 2 v ref 4 v ref 512 v ref C 2 v ref 4 v ref 8 v ref 512 v ref C a result of a-d conversion 00000000 change of a-d conversion register 10000000 *11000000 *1*2100000 *1 *2 *3 *4 *5 *6 *7 *8
68 3819 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers figures 63 shows a-d conversion equivalent circuit, and figure 64 shows a-d conversion timing chart. fig. 64 a-d conversion timing chart fig. 63 a-d conversion equivalent circuit v ss v cc av ss v cc an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 v ref av ss a-d control register build-in d-a converter v ref reference clock a-d conversion register a-d conversion interrupt request chopper amplifier sampling clock v in about 2 k w c b1b2 b0 b3 write signal for ad/da control register a-d conversion completion flag sampling clock f 50 cycles
chapter 2 application 2.1 i/o port 2.2 timer 2.3 serial i/o 2.4 a-d conversion 2.5 fld controller 2.6 interrupt interval determination function 2.7 zero cross detection circuit 2.8 reset 2.9 clock generating circuit
70 3819 group users manual mitsubishi microcomputer 3819 group 2.1 i/o port 2. application 2.1 i/o port 2.1.1 related registers fig. 2.1.1 structure of port pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b) fig. 2.1.2 structure of port p2 direction register port p2 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name port p2 direction register (p2d) [address:05 16 ] 4 5 6 7 port p2 direction register 0 0 0 0 0 : port p2 4 input mode 1 : port p2 4 output mode 0 : port p2 5 input mode 1 : port p2 5 output mode 0 : port p2 6 input mode 1 : port p2 6 output mode 0 : port p2 7 input mode 1 : port p2 7 output mode 5 5 5 5 2 3 1 1 55 55 0 1 1 1 55 55 because p2 0 to p2 3 are output ports, these bits do not have a direction register function and nothing is allocated. port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read l port latch in input mode write : port latch read : value of pins l 0 0 0 0 0 0 0 0 port pi (pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b) [address:00 16 , 02 16 , 04 16 , 06 16 , 08 16 , 0a 16 , 0c 16 , 0e 16 , 10 16 , 12 16 , 14 16 , 16 16 ] note : ( note ) port pb register [address:16 16 ] port pb is a four-bit port (pb 0 to pb 3 ). accordingly, when bits 4 to 7 are read out, the contents are 0.
71 3819 group users manual mitsubishi microcomputer 3819 group 2.1 i/o port 2. application p0, p1, p2 0 Cp2 3 , p3, p9 p2 4 Cp2 7 , p4 1 Cp4 4 , p4 6 , p4 7 , p5, p6, p7, p8, pa, pb p4 0 p4 5 v ee , av ss v ref fig. 2.1.3 structure of port pi direction register (i = 4, 5, 6, 7, 8, a, b) 2.1.2 handling of unused pins table 2.1.1 handling of unused pins open ? set to the input mode and connect to v cc or v ss through each resistor. ? set to the output mode and open at l or h. connect to v ss (gnd) through the resistor. connect to v cc through the resistor. connect to v ss (gnd). connect to v ss (gnd) through the resistor. name of pins/ports handling port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 4, 5, 6, 7, 8, a, b) [address:09 16 , 0b 16 , 0d 16 , 0f 16 , 11 16 , 15 16 , 17 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ( note ) 5 5 5 5 5 5 5 5 note : ( note ) port p4 direction register [address:09 16 ] ports p4 0 and p4 5 are input ports. accordingly, these bits do not have a direction register function.
72 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.2 timer 2.2 t imer 2.2.1 related registers fig. 2.2.1 structure of timer i (i = 1, 3, 4, 5, 6) fig. 2.2.2 structure of timer 2 timer i b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer i (ti) (i = 1, 3, 4, 5, 6) [address:20 16 , 22 16 , 23 16 , 24 16 , 25 16 ] the count value of the timer i is set. the value set in this register is written to both the timer i and the timer i latch at the same time. when the timer i is read out, the value (count value) of the timer i is read out. l l l timer 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 timer 2 (t2) [address:21 16 ] the count value of the timer 2 is set. the value set in this register is written to both the timer 2 and the timer 2 latch at the same time. when the timer 2 is read out, the value (count value) of the timer 2 is read out. l l l
73 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.2 timer fig. 2.2.4 structure of timer 12 mode register fig. 2.2.3 structure of timer 6 pwm register timer 6 pwm register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? timer 6 pwm register (t6pwm) [address:27 16 ] in timer 6 pwm mode set the width of "l" of the pwm rectangular waveform. duty of the pwm rectangular waveform : n/(n + m) cycle : (n + m) 5 ts n = a set value of the timer 6 m = a set value of the timer 6 pwm register ts = a cycle of the timer 6 count source selection of the timer 6 pwm mode set the timer 6 operation mode selection bit of the timer 56 mode register (address : 2a 16 ) to "1". l l l timer 12 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 12 mode register (t12m) [address:28 16 ] name timer 1 count stop bit timer 2 count stop bit timer 1 count source selection bit timer 2 count source selection bits timer 1 output selection bit (p4 6 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : f(x cin ) 00 : timer 1 underflow 01 : f(x cin ) 10 : external count input cntr 0 11 : not available 0 : i/o port 1 : timer 1 output b5 b4 nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " 5 5
74 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.2 timer fig. 2.2.6 structure of timer 56 mode register fig. 2.2.5 structure of timer 34 mode register timer 34 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 34 mode register (t34m) [address:29 16 ] name timer 3 count stop bit timer 4 count stop bit timer 3 count source selection bit timer 4 count source selection bits timer 3 output selection bit (p4 7 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : timer 2 underflow 00 : f(x in )/16 or f(x cin )/16 01 : timer 3 underflow 10 : external count input cntr 1 11 : not available 0 : i/o port 1 : timer 3 output b5 b4 nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " 5 5 timer 56 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 56 mode register (t56m) [address:2a 16 ] name timer 5 count stop bit timer 6 count stop bit timer 5 count source selection bit timer 6 count source selection bits timer 6 (pwm) output selection bit (p6 1 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : timer 4 underflow 00 : f(x in )/16 or f(x cin )/16 01 : timer 5 underflow 10 : timer 4 underflow 11 : not available 0 : i/o port 1 : timer 6 output b5 b4 fix this bit to "0." timer 6 operation mode selection bit 0 : timer mode 1 : pwm mode 0
75 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.2 timer fig. 2.2.7 structure of interrupt request register 1 fig. 2.2.8 structure of interrupt request register 2 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request register 1 (ireq1) [address:3c 16 ] name int 0 interrupt request bit int 1 /zcr interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request serial i/o 1 interrupt request bit serial i/o automatic transfer interrupt request bit l l [ [ [ [ 4 5 6 7 0 0 0 0 serial i/o 2 interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request serial i/o 3 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ "0" is set by software, but not "1." int 2 interrupt request bit remote control/counter overflow interrupt request bit l l interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 2 (ireq2) [address:3d 16 ] name timer 3 interrupt request bit timer 4 interrupt request bit timer 5 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request timer 6 interrupt request bit [ [ [ [ 5 6 7 0 0 0 : no interrupt request 1 : interrupt request nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." fld blanking interrupt request bit fld digit interrupt request bit l l int 4 interrupt request bit a-d conversion interrupt request bit l l 0 : no interrupt request 1 : interrupt request [ [ [ "0" is set by software, but not "1." 4 0 0 : no interrupt request 1 : interrupt request int 3 interrupt request bit [ 0 [
76 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.2 timer fig. 2.2.9 structure of interrupt control register 1 fig. 2.2.10 structure of interrupt control register 2 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address:3e 16 ] name int 0 interrupt enable bit int 1 /zcr interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 serial i/o 2 interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled serial i/o 3 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o 1 interrupt enable bit serial i/o automatic transfer interrupt enable bit l l int 2 interrupt enable bit remote control/counter overflow interrupt enable bit l l interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control reigster 2 (icon2) [address:3f 16 ] name timer 3 interrupt enable bit timer 4 interrupt enable bit timer 5 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer 6 interrupt enable bit 5 6 7 0 0 0 : interrupt disabled 1 : interrupt enabled fix this bit to "0." fld blanking interrupt enable bit fld digit interrupt enable bit l l int 4 interrupt enable bit a-d conversion interrupt enable bit l l 0 : interrupt disabled 1 : interrupt enabled 4 0 0 : interrupt disabled 1 : interrupt enabled int 3 interrupt enable bit 0 0
77 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.2 timer 2.2.2 timer application examples (1) basic functions and uses [ [ [ [ [ function 1 ] ] ] ] ] control of event interval (timers 1 to 6) the timer count stop bit is set to 0 after setting a count value to a timer. then a timer interrupt request occurs after a certain period. [ [ [ [ [ use ] ] ] ] ] ? generation of an output signal timing ? generation of a waiting time [ [ [ [ [ function 2 ] ] ] ] ] control of cyclic operation : generation of synchronous timing (timers 1 to 6) the value of a timer latch is automatically written to a timer each time a timer underflows, and a timer interrupt request occurs. [ [ [ [ [ use ] ] ] ] ] ? generation of cyclic interrupts ? clock function (measurement of one second) ? application example 1 ? control of a main routine cycle [ [ [ [ [ function 3 ] ] ] ] ] output of rectangular waveform (timers 1 and 3) the output level of the t out pin is inverted every time a timer underflows. to output long-interval rectangular waveforms (when division of 8 bits or more is necessary), the timers 2 and 3 are connected . [ [ [ [ [ use ] ] ] ] ] ? a piezoelectric buzzer output ? application example 2 ? generation of the remote-control carrier waveforms [ [ [ [ [ function 4] count of external pulse (timers 2 and 4) external pulses input to the cntr pin are selected as a timer count source. [ [ [ [ [ use ] ] ] ] ] ? measurement of frequency (judging if the video synchronization signal exits) ? application example 3 ? division of external pulses and generation of interrupts in a cycle based on an external pulse. (count of a reel pulse) [ [ [ [ [ function 5 ] ] ] ] ] output of pwm signal (timer 6) the pulses with each specified intervals of h and l are output. [ [ [ [ [ use ] ] ] ] ] ? control of an electronic volume (connected with vca)
78 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.2 timer (2) timer application example 1: clock function (measurement of one second) outline : the input clock is divided by a timer so that the clock counts up every second. specifications : ? the clock f(x in ) = 4.19 mhz (2 ) is divided by a timer. ? the timer 3 interrupt request bit is checked in the main routine, and the clock is counted up when an interrupt request occurs. ? another interrupt processing is executed in a parallel, so a timer interrupt occurs every 244 m s. figure 2.2.11 shows a connection of timers and a setting of division ratios, figures 2.2.12 and 2.2.13 show a setting of related registers, and figure 2.2.14 shows a control procedure. fig. 2.2.11 connection of timers and setting of division ratios [clock function] fig. 2.2.12 setting of related registers (1) [clock function] 22 000 00 1 timer 1 count : stopped set to "0" at starting to count timer 2 count : operating timer 1 count source : f(x in )/16 timer 2 count source : timer 1 underflow timer 1 output selection : i/o port t12m timer 12 mode register (address:28 16 ) 010 timer 3 count source : timer 2 underflow timer 3 output selection : i/o port timer 3 count : operating t34m timer 34 mode register (address:29 16 ) timer 3 interrupt request bit 1/16 0 or 1 1/256 1/16 f(x in ) = 4.19 mhz fixed timer 1 timer 2 timer 3 1 second 244 m s timer 1 interrupt request bit 1/64 0 or 1 0 : no interrupt request 1 : interrupt request
79 2. application mitsubishi microcomputer 3819 group 2.2 timer 3819 group users manual fig. 2.2.13 setting of related registers (2) [clock function] 63 t1 timer 1 (address:20 16 ) 255 t2 timer 2 (address:21 16 ) 15 t3 timer 3 (address:22 16 ) set "division ratio ?1" 1 0 timer 1 interrupt : enabled timer 2 interrupt : disabled icon1 interrupt control register 1 (address:3e 16 ) timer 2 interrupt request timer 1 interrupt request ireq1 interrupt request register 1 (address:3c 16 ) 0 timer 3 interrupt : disabled icon2 interrupt control register 2 (address:3f 16 ) 0 timer 3 interrupt request (becomes "1" every second) ireq2 interrupt request register 2 (address:3d 16 )
80 2. application mitsubishi microcomputer 3819 group 2.2 timer 3819 group users manual control procedure : figure 2.2.14 shows a control procedure. fig. 2.2.14 control procedure [clock function] reset 00000001 2 00000100 2 1 0 64 ?1 256 ?1 16 ?1 0 initialization sei t12m t34m icon1 icon2 t1 t2 t3 t12m cli .... .... .... .... (address:28 16 ) (address:29 16 ) (address:3e 16 ), bit6 (address:3f 16 ), bit0 (address:20 16 ) (address:21 16 ) (address:22 16 ) (address:28 16 ), bit0 ireq2 (address:3d 16 ), bit0 0 count up clock second?ear main processing t2 t3 ireq2 .... (address:21 16 ) (address:22 16 ) (address:3d 16 ), bit0 256 ?1 16 ?1 0 [processing for completion of setting clock] ( note ) note : this processing is performed only at completing to set the clock. y 0 1 n clock stop? ireq2 (address:3d 16 ), bit0? all interrupts : disabled connect the timers 1 to 3. timer 1 interrupt : enabled set ?ivision ratio ?1?to each timer. start the timer counting. interrupts : enabled check if the clock has already been set. check a lapse of 1 second. set the timer 3 interrupt request bit to ?? (when an interrupt is not used, set to ??by software.) count up the clock. specify so that all processing within the loop marked is repeated in a cycle of 1 second or less in the main processing. when restarting the clock from zero second after completing to set the clock, reset timers. reset the timers 2 and 3 in this order. however, the timer 1 should not be reset since it is used to generate an interrupt every 244 m s. j j l l l l l l l l l l l l
81 2. application mitsubishi microcomputer 3819 group 2.2 timer 3819 group users manual (3) timer application example 2: piezoelectric buzzer output outline : the rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. specifications : ? the rectangular waveform, 2 khz (2048 hz) which is divided clock f(x in ) = 4.19 mhz is output from the t3 out pin. ? the level of the t3 out pin fixes to h while a piezoelectric buzzer output is stopped. figure 2.2.15 shows an example of a peripheral circuit, and figure 2.2.16 shows a connection of the timer and setting of the division ratio. fig. 2.2.16 connection of the timer and setting of the division ratio [piezoelectric buzzer output] fig. 2.2.15 example of a peripheral circuit 1/16 1/2 f(x in ) = 4.19 mhz fixed timer 3 fixed 1/64 t3 out 244 m s 244 m s 3819 group pipipi.... t3 out set a division ratio so that the underflow output cycle of the timer 3 becomes this value. the "h" level is output while a piezoelectric buzzer output is stopped.
82 2. application mitsubishi microcomputer 3819 group 2.2 timer 3819 group users manual fig. 2.2.17 setting of related registers [piezoelectric buzzer output] control procedure : figure 2.2.18 shows a control procedure. fig. 2.2.18 control procedure [piezoelectric buzzer output] t34m (address:29 16 ), bit6 1 63 t3 timer 3 (address:22 16 ) set "division ratio C 1" 0 10 timer 3 count source : f(x in )/16 timer 3 output selection : set to 1 during outputting a piezoelectric buzzer. set to 0 during stopping outputting of a piezoelectric buzzer. timer 3 count : operating t34m timer 34 mode register (address:29 16 ) reset initialization p4 p4d icon2 t34m t3 .... .... .... (address:08 16 ), bit7 (address:09 16 ), bit7 (address:3f 16 ), bit7, bit0 (address:29 16 ) (address:22 16 ) 1 1 0 01000000 2 64 C 1 t34m (address:29 16 ), bit6 0 a piezoelectric buzzer is requested? y n main processing set the port condition during stopping outputting a piezoelectric buzzer ( h level output ). timer 3 interrupts : disabled the t3 out output is stopped at this point (stop outputting a piezoelectric buzzer ). the piezoelectric buzzer request occured in the main processing is processed in the output unit. during stopping outputting a piezoelectric buzzer (p4 7 ) during outputting a piezoelectric buzzer (t3 out ) output unit l l l
83 2. application mitsubishi microcomputer 3819 group 2.2 timer 3819 group users manual * (4) timer application example 3 : measurement of frequency (judging if video synchronization signal exists) outline : the pulses input to the external count input pin (cntr) are counted by a timer to judge if the frequency is within a certain range. specifications : ? the video synchronization signal is input to the cntr 1 pin and counted by the timer 4. ? a count value is read out at the interval of about 2 ms (timer 1 interrupt interval : 244 m s 5 8). when the count value is 28 to 40, it is regarded as the existence of the video synchro- nization signal. ? because the timer is a down-counter, the count value is compared with 227 to 215. 227 to 215 = 255 (initialized value of counter) C 28 to 40 (the number of valid value). figure 2.2.19 shows a method for judging if video synchronization signal exists, and figure 2.2.20 shows a setting of related registers. * fig 2.2.19 a method for judging if video synchronization signal exists video synchronization signal 63.5 m s (15.7 khz) 244 m s 5 8 63.5 m s = 31 counts
84 2. application mitsubishi microcomputer 3819 group 2.2 timer 3819 group users manual fig. 2.2.20 setting of related registers [measurement of frequency] 63 t1 timer 1 (address:20 16 ) set "division ratio ?1" 255 t4 timer 4 (address:23 16 ) set ?55?to this register immediately before count- ing pulse. (after a certain time, this value is decreased by the number of input pulses) 1 timer 1 interrupt : enabled icon1 interrupt control register 1 (address:3e 16 ) 0 0 timer 4 interrupt : disabled icon2 interrupt control register 2 (address:3f 16 ) 0 judgment of timer 4 interrupt request bit (when this bit is set to ??at reading out the count value of the timer 4 (address:23 16 ), 256 pulses or more are input (at setting 255 to the timer 4).) ireq2 interrupt request register 2 (address:3d 16 ) 01 0 timer 1 count source : f(x in )/16 timer 1 output selection : i/o port (not to be used timer 1 output) timer 1 count : stopped set to ??at starting to count. t12m timer 12 mode register (address:28 16 ) timer 4 count source : external count input from cntr 1 pin. timer 4 count : operating t34m timer 34 mode register (address:29 16 ) 0 10
85 2. application mitsubishi microcomputer 3819 group 2.2 timer 3819 group users manual control procedure : figure 2.2.21 shows a control procedure. fig. 2.2.21 control procedure [measurement of frequency] all interrupts : disabled select the input pulse from the cntr 1 pin as the timer 4 count source. timer 1 interrupt : enabled set the division ratio so that the timer 1 interrupt occurs every 244 m s. start a timer counting. interrupts : enabled set so that the processing synchro- nizing signal judgment is performed every time eight timer 1 interrupts occur. when the count value is 256 or more, the processing is performed as out of range. read the count value. store the count value in the accumu- lator (a). initialize the count value. set the timer 4 interrupt request bit to ?? 00000001 2 00100000 2 1 0 64 ?1 0 reset initialization sei t12m t34m icon1 icon2 t1 t12m cli .... .... .... .... (address:28 16 ) (address:29 16 ) (address:3e 16 ), bit6 (address:3f 16 ), bit7 (address:20 16 ) (address:28 16 ), bit0 ~ ~ (a) t4 (address:23 16 ) t4 ireq2 (address:23 16 ) (address:3d 16 ), bit1 256 ?1 0 1 0 timer 1 interrupt processing routine fsync 0 fsync 1 processing for a result of judgment rti ireq2 (address:3d 16 ), bit1? 214 (a) 228? < < compare the count value read with the reference value. store the comparison result in flag fsync. out of range in range 1/8 l l l l l l l l l l l l l
86 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual 2.3 serial i/o 2.3.1 related registers fig. 2.3.1 structure of serial i/o automatic transfer data pointer fig. 2.3.2 structure of serial i/o 1 control register when an external clock is selected in the serial i/o 1 automatic transfer mode, the s rdy1 signal pin is used as the cs signal input pin. serial i/o automatic transfer data pointer b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 6 7 0 serial i/o automatic transfer data pointer (siodp) [address:18 16 ] 0 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." indicate an address of serial i/o automatic transfer ram. ? ? ? ? ? 0 5 5 5 5 serial i/o 1 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 serial i/o 1 control register (sio1con) [address:19 16 ] name internal synchronous clock selection bits synchronous clock selection bit 000 : f(x in )/8 or f(x cin )/8 001 : f(x in )/16 or f(x cin )/16 010 : f(x in )/32 or f(x cin )/32 011 : f(x in )/64 or f(x cin )/64 110 : f(x in )/128 or f(x cin )/128 111 : f(x in )/256 or f(x cin )/256 0 : external clock 1 : internal clock p6 5 /s out1 p-channel output disable bit b2 b1b0 serial i/o 1 port selection bit (p6 5 ,p6 6 ,p6 7 ) [ transfer direction selection bit 0 : lsb first 1 : msb first s rdy1 output selection bit (p6 7 ) 0 : i/o port 1 : s rdy1 /cs signal pin ( note ) 0 : i/o port 1 : s out1 , s clk11 , s clk12 signal pins [ [ [ valid only in the serial i/o automatic transfer mode 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) note :
87 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual fig. 2.3.4 structure of serial i/o 1 register fig. 2.3.3 structure of serial i/o automatic transfer control register serial i/o automatic transfer control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 1 3 5 7 0 0 0 0 0 0 0 0 serial i/o automatic transfer control register (sioac) [address:1a 16 ] name automatic transfer control bit 0 : serial i/o ordinary mode (serial i/o 1 interrupt) 1 : automatic transfer mode (serial i/o automatic transfer interrupt) nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." automatic transfer start bit synchronous clock output pin selection bit 0 : s clk11 1 : s clk12 transfer mode switch bit 0 : fullduplex (transmit / receive) mode 1 : transmit-only mode 0 : transfer completion 1 : transferring (starts by writing 1) 5 6 4 5 5 5 serial i/o 1 register b7 b6 b5 b4 b3 b2 b1 b0 function serial i/o 1 register (sio1) [address:1b 16 ] a shift register for serial transmission and reception. at transmitting : set a transmission data. at receiving : store a reception data. b 0 1 2 3 4 5 6 7 at reset rw ? ? ? ? ? ? ? ? l l
88 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual fig. 2.3.5 structure of serial i/o automatic transfer interval register fig. 2.3.6 structure of serial i/o 2 control register serial i/o automatic transfer interval register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 6 7 0 serial i/o automatic transfer interval register (sioai) [address:1c 16 ] 0 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." ti = (n + 2) 5 tc ti = a length of transfer interval n = a setting value tc = a length of a bit of transfer clock 0 0 0 0 0 0 5 5 5 5 serial i/o 2 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 0 0 0 0 0 0 0 serial i/o 2 control register (sio2con) [address:1d 16 ] name internal synchronous clock selection bits synchronous clock selection bit 000 : f(x in )/8 or f(x cin )/8 001 : f(x in )/16 or f(x cin )/16 010 : f(x in )/32 or f(x cin )/32 011 : f(x in )/64 or f(x cin )/64 110 : f(x in )/128 or f(x cin )/128 111 : f(x in )/256 or f(x cin )/256 0 : external clock 1 : internal clock b2 b1b0 serial i/o 2 port selection bit (p5 1 ,p5 2 ) transfer direction selection bit 0 : lsb first 1 : msb first s rdy2 output selection bit (p5 3 ) 0 : i/o port 1 : s rdy2 signal pin 0 : i/o port 1 : s out2 , s clk2 signal pins 7 p5 1 /s out2 p-channel output disable bit 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) 0
89 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual fig. 2.3.7 structure of serial i/o 3 control register fig. 2.3.8 structure of interrupt request register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 1 (ireq1) [address:3c 16 ] name int 0 interrupt request bit int 1 /zcr interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request serial i/o 1 interrupt request bit serial i/o automatic transfer interrupt request bit l l [ [ [ [ 4 5 6 7 0 0 0 0 serial i/o 2 interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request serial i/o 3 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ "0" is set by software, but not "1." int 2 interrupt request bit remote control/counter overflow interrupt request bit l l serial i/o 3 control register b7 b6 b5 b4 b3 b2 b1 b0 b function r w 0 1 2 3 4 5 6 0 0 0 0 0 0 0 serial i/o 3 control register (sio3con) [address:1e 16 ] name internal synchronous clock selection bits synchronous clock selection bit 000 : f(x in )/8 or f(x cin )/8 001 : f(x in )/16 or f(x cin )/16 010 : f(x in )/32 or f(x cin )/32 011 : f(x in )/64 or f(x cin )/64 110 : f(x in )/128 or f(x cin )/128 111 : f(x in )/256 or f(x cin )/256 0 : external clock 1 : internal clock b2 b1b0 serial i/o 3 port selection bit (p5 5 ,p5 6 ) transfer direction selection bit 0 : lsb first 1 : msb first s rdy3 output selection bit (p5 7 ) 0 : i/o port 1 : s rdy3 signal pin 0 : i/o port 1 : s out3 , s clk3 signal pins 7 0 p5 5 /s out3 p-channel output disable bit 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) at reset
90 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual fig. 2.3.9 structure of interrupt control register 1 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address:3e 16 ] name int 0 interrupt enable bit int 1 /zcr interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 serial i/o 2 interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o 3 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o1 interrupt enable bit serial i/o automatic transfer interrupt enable bit l l int 2 interrupt enable bit remote control/counter overflow interrupt enable bit l l
91 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual 2.3.2 serial i/o connection examples (1) control of peripheral ic equipped with cs pin in any application, the automatic transfer function is available. figure 2.3.10 shows connection examples of a peripheral ic equipped with the cs pin. fig. 2.3.10 serial i/o connection examples (1) port s clk s out cs clk data (1) only transmission (using the s in pin as an i/o port) 3819 group peripheral ic (osd controller etc.) port s clk s out s in port cs clk in out cs clk in out (4) connecting ics 3819 group peripheral ic 1 peripheral ic 2 port s clk s out s in cs clk in out (2) transmission and reception 3819 group peripheral ic (e prom etc.) 2 the out pin of the peripheral ic is an n-channel open-drain output. it is in high impedance during receiving data. ?ort?is an output port controlled by software. note : (3) transmission and reception (pins s in and s out are connected) (pins in and out in peripheral ic are connected) port s clk s out s in cs clk in out 3819 group peripheral ic (e prom etc.) 2 [ [
92 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual (2) connection with microcomputer figure 2.3.11 shows connection examples of the other microcomputers. fig. 2.3.11 serial i/o connection examples (2) (1) selecting an internal clock (possible of using an automatic transfer function) s clk s out s in clk out in (3) using the s rdy signal output function (selecting an external clock, and not using an automatic transfer function) 3819 group microcomputer (5) using the clk signal output pin switch (s clk12 ) function (selecting an internal clock, and using an automatic transfer function) s clk s out s in clk out in 3819 group microcomputer s clk11 s out s in clk out in 3819 group microcomputer s rdy rdy s clk12 port clk out in cs peripheral ic (2) selecting an external clock (possible of using an automatic transfer function) s clk s out s in clk out in (4) using the cs signal reception function (selecting an external clock, and using an automatic transfer function) 3819 group microcomputer s clk s out s in clk out in 3819 group microcomputer cs cs
93 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual 2.3.3 setting of serial i/o mode whether s rdy signal output, cs signal receive and clk signal output pin switch (s clk12 ) functions can be selected to use or not by the following conditions: ? serial i/o circuits ( serial i/o 1 or serial i/o 2 ) ? the automatic transfer function is on or off ( at the serial i/o 1 only) ? transfer clock ( internal clock or external clock) figure 2.3.12 shows a setting of serial i/o mode. fig. 2.3.12 setting of serial i/o mode serial i/o 1 automatic transfer function off automatic transfer function on internal clock external clock internal clock external clock use s clk12 pin not use s clk12 pin serial i/o 2 serial i/o 3 internal clock external clock output s rdy signal not output s rdy signal output s rdy signal not output s rdy signal use cs function not use cs function
94 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual 2.3.4 serial i/o application examples (1) output of serial data (control of a peripheral ic) outline : the port is connected to the cs pin of a peripheral ic and the serial transmission is controlled. fig. 2.3.13 connection diagram [output of serial data] specifications : ? the serial i/o 1 is used (the automatic transfer function is not used) ? synchronous clock frequency: 131 khz ( f(x in ) = 4.19 mhz is divided by 32) ? transmission direction: lsb first ? the serial i/o 1 interrupt is not used. ? the port p6 7 is connected to the cs pin (l active) of the peripheral ic for a transmission control (the output level of the port p6 7 is controlled by software). figre 2.3.14 shows an output timing chart of serial data. fig. 2.3.14 timing chart [output of serial data] p6 7 p6 6 /s clk11 p6 5 /s out1 3819 group cs clk data peripheral ic cs clk data cs clk data do 0 do 1 do 2 do 3
95 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual fig. 2.3.16 setting of transmission data [output of serial data] fig. 2.3.15 setting of related registers [output of serial data] 0 serial i/o 1 interrupt : disabled icon1 interrupt control register 1 (address:3e 16 ) serial i/o 1 interrupt request (using this bit, check the completion of transmitting 1-byte base data (becomes 1 when the data transmission is completed).) ireq1 interrupt request register 1 (address:3c 16 ) set a transmission data. check that transmission of the previous data is completed before writing data (bit 3 of the interrupt request register 1 is set to 1). sio1 serial i/o 1 register (address:1b 16 ) 01 0 sio1con serial i/o 1 control register (address:19 16 ) 0 0 11 not use the s rdy1 signal output function internal synchronous clock : f(x in )/32 use the serial i/o 1 lsb first internal clock 0 cmos output 0 serial i/o ordinary mode sioac serial i/o automatic transfer control register (address:1a 16 ) 1 set p6 7 output level to h p6 port p6 register (address:0c 16 ) set p6 7 to output mode p6d port p6 direction register (address:0d 16 ) 1
96 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual control procedure : when the registers are set as shown in fig. 2.3.15, the serial i/o 1 can transmit one-byte data simply by writing data to the serial i/o 1 register. thus, after setting the cs signal to l, write the transmission data to the serial i/o 1 register on a one-byte base, and return the cs signal to h when the desired number of bytes have been transmitted. fig. 2.3.17 control procedure [output of serial data] set the serial i/o 1. set the cs signal output level to ?. set the cs signal output port. set the cs signal output level to ?. set the serial i/o 1 interrupt request bit to ?? write a transmission data. (start to transmit 1-byte data) check the completion of transmitting 1-byte data. use any of ram area as a counter for counting the number of transmitted bytes. check that transmission of the target num- ber of bytes has been completed. return the cs signal output level to ??when transmission of the target number of bytes is completed. reset p6 (address:0c 16 ), bit7 0 0 n y 1 ireq1 (address:3c 16 ), bit3? complete to transmit data? initialization sio1con sioac p6 p6d .... .... (address:19 16 ) (address:1a 16 ) (address:0c 16 ), bit7 (address:0d 16 ), bit7 01001010 2 00000000 2 1 1 ireq1 (address:3c 16 ), bit3 0 sio1 (address:1b 16 ) p6 (address:0c 16 ), bit7 1 a transmission data l l l l l l l l l l
97 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual out do 0 do 1 do 2 do 7 in di 0 di 1 di 2 di 7 clk do 0 do 1 di 0 di 1 1 block a cycle of blocks is controlled by software. (synchronize with a main routine.) p6 6 /s clk11 p6 5 /s out1 p6 4 /s in1 3819 group clk in out sub-microcomputer clk out in (2) data transmission or reception using automatic transfer outline : serial transmission or reception is controlled by using a serial automatic transfer function. fig. 2.3.18 connection diagram [data transmission or reception using automatic transfer] specifications : ? the serial i/o 1 is used (the automatic transfer function is used). ? transmission clock frequency: 131 khz (f(x in ) = 4.19 mhz is divided by 32) ? transmission direction : lsb first ? number of bytes for transmission or reception : each 8 bytes/block ? transmission interval: 244 m s (corresponding to a transmission clock of 32 bits) ? the serial i/o automatic transfer interrupt is not used. figure 2.3.19 shows a transmission or reception timing chart using an automatic transfer. fig. 2.3.19 timing chart [data transmission or reception using automatic transfer]
98 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual fig. 2.3.20 setting of related registers [data transmission or reception using automatic transfer] 1 automatic transfer mode sioac serial i/o automatic transfer control register (address:1a 16 ) 0 0 0 fullduplex (transmit/receive) mode synchronous clock output pin : s clk11 set to a transfer completion state (stop transferring) in initialization. (after setting a transmission data, set to 1 at starting automatic transfer.) set the number of transfer bytes C 1 (in this example, (8 bytes C 1) = 7 is set after completing to transfer 1-byte data, and before starting to transfer the next data.) siodp serial i/o automatic transfer data pointer (address:18 16 ) 0111 0 serial i/o automatic transfer interrupt : disabled icon1 interrupt control register 1 (address:3e 16 ) 0 1 set an interval of transfer clock,32 bits. (set so that setting value + 2 = 32.) sioai serial i/o automatic transfer interval register (address:1c 16 ) 11 0 1 01 0 sio1con serial i/o1 control register (address:19 16 ) 0 0 11 internal synchronous clock : f(x in )/32 use serial i/o 1 not use s rdy1 signal output function lsb first internal clock 0 cmos output
99 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual fig. 2.3.21 setting of transmission data [data transmission or reception using automatic transfer] this register is not used at using automatic transfer. sio1 serial i/o1 register (address:1b 16 ) sioram do 7 do 6 do 1 do 0 0f00 16 0f01 16 0f06 16 0f07 16 di 7 di 6 di 1 di 0 0f00 16 0f01 16 0f06 16 0f07 16 ..... ..... ..... ..... execution of automatic transfer serial i/o automatic transfer ram (address:0f00 16 to 0f1f 16 ) in this example, address ?f08 16 to 0f1f 16 ?which are not used for an automatic transfer can be used as ordinary ram.
100 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual control procedure : in this example, a serial communication is performed at the beginning of the main routine which loops in a certain cycle. fig. 2.3.22 control procedure [data transmission or reception using automatic transfer] initialize the serial i/o 1 set the related functions for using automatic transfer. generate the timing of a certain cycle by using the timer or other functions. control so that the main routine is executed in a certain cycle. set one block (8 byte) of transmission data in the ram. set the data pointer (set ? byte ?1?. start the automatic transfer. it is possible to execute the other process- ing during an automatic transfer. (a part of the main processing is executed.) check the completion of an automatic transfer. transfer a data stored to the serial i/o automatic transfer ram to ram for processing of reception data. perform the following processing in the main processing. reset initialization sio1con sioac sioai siodp icon1 ... ... (address:19 16 ) (address:1a 16 ) (address:1c 16 ) (address:18 16 ) (address:3e 16 ), bit3 01001010 2 00000001 2 30 8 ?1 0 siodp (address:18 16 ) 7 sioac (address:1a 16 ), bit 1 1 1 sioac (address:1a 16 ), bit1? 0 n has the time specified for the cycle control of a main routine elapsed? y serial i/o automatic transfer ram (address:0f00 16 to 0f07 16 ) a transmission data serial i/o automatic transfer ram (address:0f00 16 to 0f07 16 ) ram for processing of a reception data main processing 1. the processing of the data transferred into the ram for processing of reception data. 2. the preparation of the next transmission data. l l l l l l l l l l l
101 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual (3) cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] outline : when a clock synchronous serial i/o is used for communication, synchronization of the clock and the data between the transmitter and receiver sides may be lost because of noise included in the synchronizing clock. thus, it is necessary to be corrected constantly. this heading adjustment is carried out by using the interval between blocks in this example. fig. 2.3.23 connection diagram [cyclic transmission or reception of block data between microcomputers] specifications : ? synchronous clock frequency : 131 khz (f(x in ) = 4.19 mhz is divided by 32) ? byte cycle : 488 m s ? number of bytes for transmission or reception : each 8 byte/block ? block transmission cycle : 16 ms ? block transmission period : 3.5 ms ? interval between blocks : 12.5 ms ? heading adjustive time : 8 ms ? transmission direction : lsb first limitations of the specifications 1. reading of the reception data and setting of the next transmission data must be completed within the time obtained from byte cycle C time for transmitting 1-byte data (in this example, the time taken from generating of the serial i/o 1 interrupt request to generating of the next synchronizing clock is 431 m s). 2. heading adjustive time < interval between blocks must be satisfied. 3. although the transmission direction can be switched for the serial i/o of 3819 group, it cannot be switched for some serial i/os of 740 family including 38000 series (only lsb first). be sure to check when deciding specifications. s clk s in s out master unit s clk s in s out slave unit
102 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual the communication is performed according to the timing shown below. in the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. when a clock is input again after one block (8 byte) is received, the clock is ignored. figure 2.3.25 shows a setting of related registers. fig. 2.3.24 timing chart [cyclic transmission or reception of block data between microcomputers] fig. 2.3.25 setting of related registers [cyclic transmission or reception of block data between microcomputers] d 0 byte cycle block transmission period block transmission cycle d 1 d 2 d 7 d 0 interval between blocks processing for heading adjustment heading adjustive time not be effected by external clock not use the s rdy1 signal output function sio1con serial i/o 1 control register (address:19 16 ) internal synchronous clock : f(x in )/32 use the serial i/o 1 not use the s rdy1 signal output function lsb first internal clock 0 0 0 110 1 sio1con serial i/o 1 control register (address:19 16 ) use the serial i/o 1 lsb first external clock 0 0 01 master unit slave unit sioac serial i/o automatic transfer control register (address:1a 16 ) serial i/o ordinary mode 0 when an automatic transfer function is not used, the s clk11 is used as an i/o pin for a synchronizing clock (the s clk12 is not selected). note : [when using the serial i/o 1] 0 cmos output 0 cmos output
103 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual control procedure : (1) control in the master unit after a setting of the related registers is completed as shown in figure 2.3.25, in the master unit transmission or reception of one-byte data is started simply by writing transmission data to the serial i/o 1 register. to perform the communication in the timing shown in the specifications, therefore, take the timing into account and write transmission data. read out the reception data when the serial i/o 1 interrupt request bit is set to 1, or before the next transmission data is written to the serial i/o 1 register. a processing example in the master unit using timer interrupts is shown below. fig. 2.3.26 control in the master unit interrupt processing routine executed every 488 m s write a transmission data read a reception data n within a block transfer period? y y complete to transmit a block? n rti write the first transmission data (first byte) in a block count a block interval counter n start a block transfer? y generate a certain block interval by using a timer or other functions. check the block interval counter and determine to start of a block transfer. l l
104 2. application mitsubishi microcomputer 3819 group 2.3 serial i/o 3819 group users manual (2) control in the slave unit after a setting of the related registers is completed as shown in figure 2.3.25, the slave unit becomes the state which is received a synchronizing clock at all times, and the serial i/o 1 interrupt request bit is set to 1 every time an 8-bit synchronous clock is received. for transmitting or receiving data according to the synchronizing clock input in the timing shown in the specifications, read out the reception data and write the next transmission data to the serial i/o 1 register in the following conditions. ? when the serial i/o 1 interrupt occurs. ? when the serial i/o 1 interrupt request bit is set to 1 as the result of checking. when the serial i/o 1 interrupt request bit is not set to 1 within a certain time (heading adjustive time), the first byte of the transmission data in a block is written to the serial i/o 1 register, then the next reception data is processed as the first byte of the reception data in a block. a processing example in the slave unit using serial i/o interrupts and timer interrupts (for a heading adjustment) is shown below. fig. 2.3.27 control in the slave unit serial i/o 1 interrupt processing routine write a transmission data read a reception data n within a block transfer period? y y a received byte counter 3 8? n rti write any data (ff 16 ) a received byte counter +1 heading adjustive counter initialized value (note) timer interrupt processing routine heading adjustive counter ?1 n heading adjustive counter = 0? y rti write the first transmission data (first byte) in a block a received byte counter 0 check the received byte counter to judge if a block has been transfered. in this example, set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counter. for example : when the heading adjustive time is 8ms and the timer interrupt cycle is 1ms, set 8 as the initialized value. note : l
105 2. application mitsubishi microcomputer 3819 group 2.4 a-d conversion 3819 group users manual 2.4 a-d conversion 2.4.1 related registers fig. 2.4.2 structure of a-d conversion register fig. 2.4.1 structure of ad/da control register ad/da control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name analog input pin selection bits ad/da control register (adcon) [address:2c 16 ] 0 0 0 0 : p7 0 /an 0 0 0 0 1 : p7 1 /an 1 0 0 1 0 : p7 2 /an 2 0 0 1 1 : p7 3 /an 3 0 1 0 0 : p7 4 /an 4 0 1 0 1 : p7 5 /an 5 0 1 1 0 : p7 6 /an 6 0 1 1 1 : p7 7 /an 7 1 0 0 0 : p5 0 /s in2 /an 8 1 0 0 1 : p5 1 /s out2 /an 9 1 0 1 0 : p5 2 /s clk2 /an 10 1 0 1 1 : p5 3 /s rdy2 /an 11 1 1 0 0 : p5 4 /s in3 /an 12 1 1 0 1 : p5 5 /s out3 /an 13 1 1 1 0 : p5 6 /s clk3 /an 14 1 1 1 1 : p5 7 /s rdy3 /an 15 b3 b2 b1 b0 1 0 : conversion in progress 1 : conversion completed a-d conversion completion bit 4 1 0 2 3 0 0 0 0 0 5 5 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 5 0 0 : disable 1 : enable d-a output enable bit 6 0 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 7 a-d conversion register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw a-d conversion register (ad) [address:2d 16 ] the read-only register which a-d conversion results are stored. 5 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? 5 5 5 5 5 5 5
106 2. application mitsubishi microcomputer 3819 group 2.4 a-d conversion 3819 group users manual fig. 2.4.3 structure of interrupt request register 2 fig. 2.4.4 structure of interrupt control register 2 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control reigster 2 (icon2) [address:3f 16 ] name timer 3 interrupt enable bit timer 4 interrupt enable bit timer 5 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer 6 interrupt enable bit 5 6 7 0 0 0 : interrupt disabled 1 : interrupt enabled fix this bit to "0." fld blanking interrupt enable bit fld digit interrupt enable bit l l int 4 interrupt enable bit a-d conversion interrupt enable bit l l 0 : interrupt disabled 1 : interrupt enabled 4 0 0 : interrupt disabled 1 : interrupt enabled int 3 interrupt enable bit 0 0 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 2 (ireq2) [address:3d 16 ] name timer 3 interrupt request bit timer 4 interrupt request bit timer 5 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request timer 6 interrupt request bit [ [ [ [ 5 6 7 0 0 0 : no interrupt request 1 : interrupt request nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." fld blanking interrupt request bit fld digit interrupt request bit l l int 4 interrupt request bit a-d conversion interrupt request bit l l 0 : no interrupt request 1 : interrupt request [ [ [ "0" is set by software, but not "1." 4 0 0 : no interrupt request 1 : interrupt request int 3 interrupt request bit [ 0 [
107 2. application mitsubishi microcomputer 3819 group 2.4 a-d conversion 3819 group users manual 2.4.2 a-d conversion application example conversion of analog input voltage outline : the analog input voltage input from the sensor is converted into digital values. figure 2.4.5 shows a connection diagram, and figure 2.4.6 shows a setting of related registers. fig. 2.4.5 connection diagram [conversion of analog input voltage] specifications : ? the an 0 pin is used as an analog input pin. ? the analog input voltage input from the sensor is converted into digital values. fig. 2.4.6 setting of related registers [conversion of analog input voltage] 0 analog input pin selection : p7 0 /an 0 adcon ad/da control register (address:2c 16 ) 0 0 0 start a-d conversion p7 0 /an 0 3819 group sensor v ref av ss v cc v ss store a result of a-d conversion ad a-d conversion register (address:2d 16 ) (read-only) note : read out a result of a-d conversion after bit 4 of the ad/da control register (adcon) is set to ??
108 2. application mitsubishi microcomputer 3819 group 2.4 a-d conversion 3819 group users manual control procedure : by setting the related registers as shown in figure 2.4.6, the analog input voltage input from the sensor are converted into digital values. fig. 2.4.7 control procedure [conversion of analog input voltage] ~ ~ read out ad (address:2d 16 ) ~ ~ adcon (address:2c 16 ), bit0 ?bit3 0000 2 adcon (address:2c 16 ), bit4 0 0 adcon (address:2c 16 ), bit4? 1 select the an 0 pin as an analog input pin. start a-d conversion. check the completion of a-d conversion. read out the conversion result. l l l l
109 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 2.5 fld controller 2.5.1 related registers fig. 2.5.1 structure of port p0 segment/digit switch register fig. 2.5.2 structure of port p2 digit/port switch register port p0 segment/digit switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p0 segment/digit switch register 0 0 0 0 0 0 0 0 port p0 segment/digit switch register (p0sdr) [address:32 16 ] 0 : dig 0 1 : seg 32 0 : dig 1 1 : seg 33 0 : dig 2 1 : seg 34 0 : dig 3 1 : seg 35 0 : dig 4 1 : seg 36 0 : dig 5 1 : seg 37 0 : dig 6 1 : seg 38 0 : dig 7 1 : seg 39 port p2 digit/port switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name port p2 digit/port switch register (p2dpr) [address:33 16 ] 0 1 2 3 port p2 digit/port switch register 0 0 0 0 0 : port p2 0 output-only 1 : dig 16 0 : port p2 1 output-only 1 : dig 17 0 : port p2 2 output-only 1 : dig 18 0 : port p2 3 output-only 1 : dig 19 4 5 0 0 5 5 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." 6 7 0 0 5 5
110 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller fig. 2.5.4 structure of port pa segment/port switch register fig. 2.5.3 structure of port p8 segment/port switch register port pa segment/port switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pa segment/port switch register 0 0 0 0 0 0 0 0 port pa segment/port switch register (paspr) [address:35 16 ] 0 : port pa 0 for i/o 1 : seg 0 0 : port pa 1 for i/o 1 : seg 1 0 : port pa 2 for i/o 1 : seg 2 0 : port pa 3 for i/o 1 : seg 3 0 : port pa 4 for i/o 1 : seg 4 0 : port pa 5 for i/o 1 : seg 5 0 : port pa 6 for i/o 1 : seg 6 0 : port pa 7 for i/o 1 : seg 7 port p8 segment/port switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p8 segment/port switch register 0 0 0 0 0 0 0 0 port p8 segment/port switch register (p8spr) [address:34 16 ] 0 : port p8 0 for i/o 1 : seg 8 0 : port p8 1 for i/o 1 : seg 9 0 : port p8 2 for i/o 1 : seg 10 0 : port p8 3 for i/o 1 : seg 11 0 : port p8 4 for i/o 1 : seg 12 0 : port p8 5 for i/o 1 : seg 13 0 : port p8 6 for i/o 1 : seg 14 0 : port p8 7 for i/o 1 : seg 15
111 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller fig. 2.5.5 structure of fldc mode register 1 fldc mode register 1 b7 b6 b5 b4 b3 b2 b1 b function at reset rw 0 0 fldc mode register 1 (fldm1) [address:36 16 ] name tscan control bits 0 0 : fld digit interrupt (at rising edge of each digit) 0 1 : 1 5 tdisp 1 0 : 2 5 tdisp 1 1 : 3 5 tdisp (at falling edge of the last digit) 6 0 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 5 toff control bit (setting of digit/segment off time) 0 0 0 0 : 1/16 5 tdisp 0 0 0 1 : 2/16 5 tdisp 0 0 1 0 : 3/16 5 tdisp 0 0 1 1 : 4/16 5 tdisp 0 1 0 0 : 5/16 5 tdisp 0 1 0 1 : 6/16 5 tdisp 0 1 1 0 : 7/16 5 tdisp 0 1 1 1 : 8/16 5 tdisp 1 0 0 0 : 9/16 5 tdisp 1 0 0 1 : 10/16 5 tdisp 1 0 1 0 : 11/16 5 tdisp 1 0 1 1 : 12/16 5 tdisp 1 1 0 0 : 13/16 5 tdisp 1 1 0 1 : 14/16 5 tdisp 1 1 1 0 : 15/16 5 tdisp 1 1 1 1 : 16/16 5 tdisp b5 b4 b3 b2 3 2 4 5 0 0 0 0 1 0 b1b0 7 0 high-breakdown-voltage drivability selection bit 0 : strong drivability 1 : weak drivability b0 fld blanking interrupt
112 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller fig. 2.5.6 structure of fldc mode register 2 fldc mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 0 0 fldc mode register 2 (fldm2) [address:37 16 ] name 2 4 0 3 tdisp control bits (digit time setting) (at 8 mhz oscillation frequency) 0 0 0 0 : 128 m s 0 0 0 1 : 256 m s 0 0 1 0 : 384 m s 0 0 1 1 : 512 m s 0 1 0 0 : 640 m s 0 1 0 1 : 768 m s 0 1 1 0 : 896 m s 0 1 1 1 : 1024 m s 1 0 0 0 : 1152 m s 1 0 0 1 : 1280 m s 1 0 1 0 not available 1 1 1 1 b5 b4 b3 b2 automatic display control bit (p0,p1,p2 0 Cp2 3 ,p3,p8,p9,pa) 0 : display stopped 1 : display in progress (display starts by writing 1 to this bit which is set to 0.) display start bit 0 : ordinary mode 1 : automatic display mode 5 .... 0 0 0 6 0 p1 0 segment/digit switch bit 0 : digit (dig 8 ) 1 : segment (seg 40 ) 7 0 p1 1 segment/digit switch bit 0 : digit (dig 9 ) 1 : segment (seg 41 )
113 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller fig. 2.5.7 structure of fld data pointer fig. 2.5.8 structure of fld data pointer reload register fld data pointer reload register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 fld data pointer reload register (flddp) [address:38 16 ] indicate the first digit address of the high-order segment. ? ? ? ? ? nothing is allocated for this bit. this is a write disabled bit. ? 7 5 5 5 5 5 5 5 5 5 ? 5 6 ? fld data pointer b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 fld data pointer (flddp) [address:38 16 ] indicate the address of data which is transfered to the segment of the fld automatic display ram. ? ? ? ? ? nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 0 7 5 5 ? 5 5 5 5 5 5 6 ? 5
114 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control reigster 2 (icon2) [address:3f 16 ] name timer 3 interrupt enable bit timer 4 interrupt enable bit timer 5 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer 6 interrupt enable bit 5 6 7 0 0 0 : interrupt disabled 1 : interrupt enabled fix this bit to "0." fld blanking interrupt enable bit fld digit interrupt enable bit l l int 4 interrupt enable bit a-d conversion interrupt enable bit l l 0 : interrupt disabled 1 : interrupt enabled 4 0 0 : interrupt disabled 1 : interrupt enabled int 3 interrupt enable bit 0 0 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 2 (ireq2) [address:3d 16 ] name timer 3 interrupt request bit timer 4 interrupt request bit timer 5 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request timer 6 interrupt request bit [ [ [ [ 5 6 7 0 0 0 : no interrupt request 1 : interrupt request nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." fld blanking interrupt request bit fld digit interrupt request bit l l int 4 interrupt request bit a-d conversion interrupt request bit l l 0 : no interrupt request 1 : interrupt request [ [ [ "0" is set by software, but not "1." 4 0 0 : no interrupt request 1 : interrupt request int 3 interrupt request bit [ 0 [ fig. 2.5.10 structure of interrupt control register 2 fig. 2.5.9 structure of interrupt request register 2
115 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual 2.5.2 fld controller application examples (1) fld automatic display and key-scan using segment pin outline : the pannel with fluorescent display (fld) is displayed by using fld automatic display function. then the key is read in with using segment pin by software. fig. 2.5.11 connection diagram [fld automatic display and key-scan using segment pin] specifications : ? the automatic display function is used. ? 10 digits and 10 segments are used. ? toff = 15.27 m s, tdisp = 244.39 m s, tscan = 733.17 m s (at f(x in ) = 4.19 mhz) ? the fld blanking interrupt is used. ? the segment pin is used for the key-scan. figure 2.5.12 shows a timing chart of the key-scan using an fld automatic display and segments, and figure 2.5.13 shows an enlarged view of seg 24 to seg 31 during tscan. fig. 2.5.12 timing chart [fld automatic display and key-scan using segment pin] tscan tdisp key-scan fld blanking interrupt request occurs dig 2 (p0 2 ) dig 3 (p0 3 ) dig 4 (p0 4 ) dig 11 (p1 3 ) seg 24 ?eg 33 (p3 0 ?3 7 ,p0 0 ,p0 1 ) l l l l l l l l l l l l p1 0 ?1 3 p0 0 ,p0 1 p3 0 ?3 7 digit segment segment sun mon tue wed thu fri sat am pm p0 2 ?0 7 p2 4 ?2 7 3819 group ch l r sp lp rec level key matrix pannel with fluorescent display (fld)
116 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual after switching a segment pin to an output port, the waveform shown below is created by software, and the key-scan is performed. fig. 2.5.13 enlarged view of seg 24 to seg 31 during tscan figures 2.5.14 and 2.5.15 show a setting of related registers. fig. 2.5.14 setting of related registers (1) [fld automatic display and key-scan using segment pin] l l l seg 24 (p3 0 ) seg 25 (p3 1 ) seg 26 (p3 2 ) seg 31 (p3 7 ) l l l stop displaying 1 automatic display mode fldm2 fldc mode register 2 (address:37 16 ) 0 0 0 tdisp = 244.39 m s set ports p1 1 and p1 0 to digit (dig 9 , dig 8 ) 0 0 0 0 toff = 1/16 5 tdisp = 15.27 m s 1 tscan = 3 5 tdisp = 733.17 m s fldm1 fldc mode register 1 (address:36 16 ) 1 0 0 dull the output waveform of the high-breakdown-voltage port 0 0 1 set the value of the number of digits C 1 flddp fld data pointer (address:38 16 ) 1001 0 0 0
117 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual fig. 2.5.15 setting of related registers (2) [fld automatic display and key-scan using segment pin] 01 0 p0sdr port p0 segment/digit switch register (address:32 16 ) 1 0 00 set ports p0 1 and p0 0 to segment (seg 33 , seg 32 ) set ports p0 7 ?0 2 to digit (dig 7 ?ig 2 ) 0 set ports p2 3 ?2 0 to output-only port p2dpr port p2 digit/port switch register (address:33 16 ) 0 0 0 0 0 set ports p8 7 ?8 0 to i/o port p8spr port p8 segment/port switch register (address:34 16 ) 00 0 0 00 0 set ports pa 7 ?a 0 to i/o port paspr port pa segment/port switch register (address:35 16 ) 000 0 0 00 0 set the fld blanking interrupt request bit to ?? ireq2 interrupt request register 2 (address:3d 16 ) 0 fld blanking interrupt : enabled icon2 interrupt control register 2 (address:3f 16 ) 0 1 set ports p2 7 ?2 4 to the input mode p2d port p2 direction register (address:05 16 ) 0 00 0 start displaying fldm2 fldc mode register 2 (address:37 16 ) 00 1 1 0 00 0
118 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual setting of fld automatic display ram : table 2.5.1 fld automatic display ram map [fld automatic display and key-scan using segment pin] address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0fb0 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 25 seg 24 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 33 seg 32 ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) : area which is used to set a display value : area which is available as ordinary ram
119 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual fld digit allocation : fig. 2.5.16 example of fld digit allocation [fld automatic display and key-scan using segment pin] table 2.5.2 fld automatic display ram map example [fld automatic display and key-scan using segment pin] sun mon tue wed thu fri sat am pm ch l r sp lp rec level dig 2 dig 3 dig 9 dig 8 dig 7 dig 6 dig 5 dig 4 dig 10 dig 11 a b c d e f g address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0fb0 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 ch sun mon wed fri sat g f e d c b a pm am ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) : unused g f e d c b a g f e d c b a g f e d c b a g f e d c b a g f e d c b a g f e d c b a rec lp sp thu tue level l r
120 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual control procedure : figure 2.5.17 shows a control procedure. fig. 2.5.17 control procedure [fld automatic display and key-scan using segment pin] set related functions for using the fld automatic display. set segment/digit /port. set the bits 7 to 4 of the port p2 direction register used for the key-scan to input mode. to turn on the display of the corresponding segment : set to ?? to turn off the display of the corresponding segment : set to ?? ( note ) set the fld blanking interrupt request bit to ?? wait until completing to write data to the fld blanking interrupt request bit. fld blanking interrupt : enabled start the fld automatic display. note : the display data is re-written at any time. reset initialization fldm1 fldm2 flddp p0sdr p2dpr p8spr paspr p2d .... .... (address:36 16 ) (address:37 16 ) (address:38 16 ) (address:32 16 ) (address:33 16 ) (address:34 16 ) (address:35 16 ) (address:05 16 ) 10000011 2 00000001 2 00001001 2 00000011 2 00000000 2 00000000 2 00000000 2 00000000 2 ireq2 (address:3d 16 ), bit6 0 fld automatic display ram (address:0fb0 16 to 0fc9 16 ) wait for 1 or more cycles icon2 (address:3f 16 ) fldm2 (address:37 16 ) , bit6 1 , bit1 1 main processing a data to be displayed l l l l l l l l l
121 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual ~ ~ rti fld blanking interrupt processing routine push register to stack etc. (address:37 16 ), bit0 (address:02 16 ), bit0-bit3 (address:00 16 ) (address:06 16 ) fldm2 p1 p0 p3 .... .... 0 0000 2 00 16 00 16 set data table for key-scan to p3 (address:06 16 ) n y complete key-scan?( note ) wait for key-scan transfer the contents of p2 (address:04 16 ) to work ram renew data table pointer for key-scan set key-scan completion flag initialize data table pointer for key-scan p3 p0 fldm2 (address:06 16 ) (address:00 16 ) (address:37 16 ), bit0 00 16 00 16 1 segment key-scan switch the fld automatic display pin to the ordinary port. wait until the ??level output of port p3 i is stabilized. read keys. (set the port p2 direction register (p2d) (address:05 16 ) to input mode in the initialization.) renew the data table reference pointer for the next key-scan. set the flag for checking if the key-scan has been completed. output ??level from all key-scan ports. switch the fld automatic display pin to the automatic display mode. note : when the key-scan is not completed within the tscan setting time, it is divided and performed [ i = 0 to 7 [ l l l l l l l l segment key-scan (fld blanking interrupt) : fig. 2.5.18 control procedure of segment key-scan
122 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller (2) fld automatic display and key-scan using digit pin outline : the pannel with fluorescent display (fld) is displayed by using fld automatic display function. then the key is read in with using digit output waveforms. specifications : ? the automatic display function is used. ? 10 digits and 10 segments are used. ? toff = 15.27 m s, tdisp = 244.39 m s, tscan = 0 m s (at f(x in ) = 4.19 mhz) ? the fld digit interrupt is used. ? the digit pin is used for the key-scan. fig. 2.5.20 timing chart [fld automatic display and key-scan using digit pin] fig. 2.5.19 connection diagram [fld automatic display and key-scan using digit pin] tscan = 0 m s tdisp fld digit interrupt request occurs dig 2 (p0 2 ) dig 3 (p0 3 ) dig 4 (p0 4 ) dig 11 (p1 3 ) seg 24 ?eg 33 (p3 0 ?3 7 ,p0 0 ,p0 1 ) l l l l l l l l l l l l fld digit interrupt request occurs fld digit interrupt request occurs fld digit interrupt request occurs p0 0 ,p0 1 p0 2 ?0 7 p1 0 ?1 3 segment segment digit sun mon tue wed thu fri sat am pm p3 0 ?3 7 p2 4 ?2 7 3819 group ch l r sp lp rec level key matrix pannel with fluorescent display (fld)
123 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual fig. 2.5.21 setting of related registers (1) [fld automatic display and key-scan using digit pin] p0sdr 01 0 port p0 segment/digit switch register (address:32 16 ) 1 0 00 set ports p0 1 and p0 0 to segment (seg 33 , seg 32 ) set ports p0 7 Cp0 2 to digit (dig 7 Cdig 2 ) 0 set ports p2 3 Cp2 0 to output-only port p2dpr port p2 digit/port switch register (address:33 16 ) 0 0 0 0 toff = 1/16 5 tdisp = 15.27 m s 0 tscan = 0 m s fldm1 fldc mode register 1 (address:36 16 ) 0 0 0 dull the output waveform of the high-breakdown-voltage port 0 0 1 stop displaying 1 automatic display mode fldm2 fldc mode register 2 (address:37 16 ) 0 0 0 tdisp = 244.39 m s 0 0 0 0 set ports p1 1 and p1 0 to digit (dig 9 , dig 8 ) set the value of the number of digits C 1 flddp fld data pointer (address:38 16 ) 1001 0 0 0 p8spr 0 0 0 port p8 segment/port switch register (address:34 16 ) 0 0 00 set ports p8 7 Cp8 0 to i/o port 0
124 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller fig. 2.5.22 setting of related registers (2) [fld automatic display and key-scan using digit pin] 0 set ports pa 7 ?a 0 to ordinary port paspr port pa segment/port switch register (address:35 16 ) 00 0 0 00 0 set the fld digit interrupt request bit to ? ireq2 interrupt request register 2 (address:3d 16 ) 0 fld digit interrupt : enabled icon2 interrupt control register 2 (address:3f 16 ) 0 1 set ports p2 7 ?2 4 to the input mode p2d port p2 direction register (address:05 16 ) 0 00 0 start displaying fldm2 fldc mode register 2 (address:37 16 ) 00 1 1 0 00 0
125 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual setting of fld automatic display ram : table 2.5.3 fld automatic display ram map [fld automatic display and key-scan using digit pin] address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0fb0 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 31 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 30 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 29 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 28 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 27 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 26 seg 25 seg 24 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 25 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 24 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 33 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 32 seg 33 seg 32 ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) : area which is used to set a display value : area which is available as ordinary ram
126 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller fld digit allocation : fig. 2.5.23 example of fld digit allocation [fld automatic display and key-scan using digit pin] table 2.5.4 fld automatic display ram map example [fld automatic display and key-scan using digit pin] sun mon tue wed thu fri sat am pm ch l r sp lp rec level dig 2 dig 3 dig 9 dig 8 dig 7 dig 6 dig 5 dig 4 dig 10 dig 11 a b c d e f g address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0fb0 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 ch sun mon wed fri sat g f e d c b a pm am ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) : unused g f e d c b a g f e d c b a g f e d c b a g f e d c b a g f e d c b a g f e d c b a rec lp sp thu tue level l r
127 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual control procedure : figure 2.5.24 shows a control procedure. fig. 2.5.24 control procedure [fld automatic display and key-scan using digit pin] set the related functions for the fld automatic display. set segment/digit/port. set the bits 7 to 4 of the port p2 direction register used for the key- scan to the input mode. to turn on the display of the corresponding segment : set to ?? to turn off the display of the corresponding segment : set to ?? ( note ) set the fld digit interrupt request bit to ?? wait until completing to write data to the fld digit interrupt request bit. fld digit interrupt : enabled start the fld automatic display. note : the display data is rewritten at any time. reset initialization fldm1 fldm2 flddp p0sdr p2dpr p8spr paspr p2d .... .... (address:36 16 ) (address:37 16 ) (address:38 16 ) (address:32 16 ) (address:33 16 ) (address:34 16 ) (address:35 16 ) (address:05 16 ) 10000000 2 00000001 2 00001001 2 00000011 2 00000000 2 00000000 2 00000000 2 00000000 2 ireq2 (address:3d 16 ), bit6 0 wait for 1 or more cycles icon2 (address:3f 16 ) fldm2 (address:37 16 ) , bit6 1 , bit1 1 ~ ~ fld automatic display ram (address:0fb0 16 to 0fc9 16 ) a data to be displayed l l l l l l l l l
128 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller digit key-scan (fld digit interrupt) : fig. 2.5.25 control procedure of digit key-scan fld digit interrupt processing routine push register to stack etc. .... wait for key-scan transfer the contents of p2 (address:04 16 ) to work ram store the contents of work ram into buffer ~ ~ rti digit key-scan wait until the digit output is stabilized since the digit output waveform may dull because of the printed circuit board (pcb) pattern wiring length or other factors. read keys. (set the port p2 direction register (p2d) (address:05 16 ) to the input mode in the initialization.) l l l
129 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual (3) fld display by software (example of without using fld controller) outline : the fld display and the key read-in are performed by using timer interrupts. fig. 2.5.26 connection diagram [fld display by software] specifications : ? the display is controlled by software. ? 10 digits and 10 segments are used. ? the timer 1 interrupts are used. ? the segment pin is used for key-scan. fig. 2.5.27 shows a timing chart of fld display by software, and fig. 2.5.28 shows an enlarged view of key-scan of ports p3 0 to p3 7 . fig. 2.5.27 timing chart [fld display by software] key-scan p0 2 p0 3 p0 4 p1 3 p3 0 ?3 7 , p0 0 ,p0 1 l l l l l l l l l l l l p1 0 ?1 3 p0 0 ,p0 1 p3 0 ?3 7 digit segment segment sun mon tue wed thu fri sat am pm p0 2 ?0 7 p2 4 ?2 7 3819 group ch l r sp lp rec level key matrix pannel with fluorescent display (fld)
130 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual the waveform shown below is created by software, and the key-scan is performed. fig. 2.5.28 enlarged view of key-scan of ports p3 0 to p3 7 figure 2.5.29 shows a setting of related registers. fig. 2.5.29 setting of related registers [fld display by software] l l l p3 0 p3 1 p3 2 p3 7 l l l stop displaying 0 ordinary mode fldm2 fldc mode register 2 (address:37 16 ) 0 0 0 0 0 set ports p2 7 ?2 4 to the input mode p2d port p2 direction register (address:05 16 ) dull the output waveform of the high-breakdown-voltage port fldm1 fldc mode register 1 (address:36 16 ) 1
131 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual fld digit allocation : fig. 2.5.30 example of fld digit allocation [fld display by software] table 2.5.5 fld automatic display ram map example [fld display by software] (automatic display is not performed because of not using fld controller) sun mon tue wed thu fri sat am pm ch l r sp lp rec level dig 2 dig 3 dig 9 dig 8 dig 7 dig 6 dig 5 dig 4 dig 10 dig 11 a b c d e f g address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0fb0 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 ch sun mon wed fri sat g f e d c b a pm am ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 3 (p0 3 ) ? dig 2 (p0 2 ) : unused g f e d c b a g f e d c b a g f e d c b a g f e d c b a g f e d c b a g f e d c b a rec lp sp thu tue level l r
132 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual control procedure : figure 2.5.31 shows a control procedure. fig. 2.5.31 control procedure [fld display by software] set the bits 7 to 4 of the port p2 direction register used for the key-scan to the input mode. segment key-scan fld display : off read keys. (set the port p2 direction register (p2d) (address:05 16 ) to the input mode in the initialization.) timer 1 interrupt processing routine n y complete key-scan? push register to stack etc. p0 p1 p3 .... .... (address:00 16 ) (address:02 16 ), bit0?it3 (address:06 16 ) 00 16 0000 2 00 16 set data table for key-scan to port p3 (address:06 16 ) wait for key-scan transfer the contents of port p2 (address:04 16 ) to work ram renew data table pointer for key-scan ~ ~ rti ~ ~ reset initialization fldm1 fldm2 p2d .... .... (address:36 16 ), bit7 (address:37 16 ), bit1, bit0 (address:05 16 ) 1 00 2 00000000 2 n y complete to display all digits? p0 (address:00 16 ),bit2?it7 digit p1 (address:02 16 ),bit0?it3 data ~ ~ wait until the ??level output of port p3 is stabilized. p0 (address:00 16 ), bit0, bit1 segment p3 (address:06 16 ) data l l l l
133 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual (4) 5 5 7 dot display outline : the 5 5 7 dot display is performed by using the fld automatic display function. specifications : ? the automatic display function is used. ? 16 digits and 35 segments are used. ? toff = 288 m s, tdisp = 512 m s, tscan = 512 m s (at f(x in ) = 8 mhz) figure 2.5.33 shows a timing chart of fld automatic display. fig. 2.5.32 connection diagram [5 5 7 dot display] fig. 2.5.33 timing chart [5 5 7 dot display] dig 4 (p0 4 ) dig 5 (p0 5 ) dig 6 (p0 6 ) dig 19 (p2 3 ) seg 0 ?eg 35 (pa 0 ?a 7 , p8 0 ?8 7 , p9 0 ?9 7 , p3 0 ?3 7 , p0 0 ?0 2 ) l l l l l l l l l l l l dig 4 ?ig 19 35 segments 16 digits seg 0 ?eg 34 3819 group
134 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller figures 2.5.34 and 2.5.35 show a setting of related registers. fig. 2.5.34 setting of related registers (1) [5 5 7 dot display] toff = 9/16 5 tdisp = 288 m s 0 tscan = 512 m s fldm1 fldc mode register 1 (address:36 16 ) 0 0 0 high-breakdown-voltage port drivability : strong 0 1 0 stop displaying 1 automatic display mode fldm2 fldc mode register 2 (address:37 16 ) 0 1 1 tdisp = 512 m s 0 0 0 0 set ports p1 1 and p1 0 to digit (dig 9 , dig 8 ) p0sdr 11 0 port p0 segment/digit switch register (address:32 16 ) 1 0 01 set ports p0 3 Cp0 0 to segment (seg 35 Cseg 32 ) (however, seg 35 is unused.) set ports p0 7 Cp0 4 to digit (dig 7 Cdig 4 ) 0 set ports p2 3 Cp2 0 to digit (dig 19 Cdig 16 ) p2dpr port p2 digit/port switch register (address:33 16 ) 1 1 1 1
135 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual fig. 2.5.35 setting of related registers (2) [5 5 7 dot display] 1 set ports pa 7 ?a 0 to segment (seg 7 ?eg 0 ) paspr port pa segment/port switch register (address:35 16 ) 111 1 11 1 start displaying fldm2 fldc mode register 2 (address:37 16 ) 00 1 1 1 0 1 0 set the value of ?he number of digits ?1 flddp fld data pointer reload register (address:38 16 ) 1 11 1 0 0 0 p8spr 11 1 port p8 segment/port switch register (address:34 16 ) 1 1 11 set ports p8 7 ?8 0 to segment (seg 15 ?eg 8 ) 1
136 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller setting of fld automatic display ram : table 2.5.6 fld automatic display ram map [5 5 7 dot display] address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 : area which is used to set a display value : area which is available as ordinary ram ? dig 19 (p2 3 ) ? dig 18 (p2 2 ) ? dig 17 (p2 1 ) ? dig 16 (p2 0 ) ? dig 15 (p1 7 ) ? dig 14 (p1 6 ) ? dig 13 (p1 5 ) ? dig 12 (p1 4 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 19 (p2 3 ) ? dig 18 (p2 2 ) ? dig 17 (p2 1 ) ? dig 16 (p2 0 ) ? dig 15 (p1 7 ) ? dig 14 (p1 6 ) ? dig 13 (p1 5 ) ? dig 12 (p1 4 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 19 (p2 3 ) ? dig 18 (p2 2 ) ? dig 17 (p2 1 ) ? dig 16 (p2 0 ) ? dig 15 (p1 7 ) ? dig 14 (p1 6 ) ? dig 13 (p1 5 ) ? dig 12 (p1 4 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 19 (p2 3 ) ? dig 18 (p2 2 ) ? dig 17 (p2 1 ) ? dig 16 (p2 0 ) ? dig 15 (p1 7 ) ? dig 14 (p1 6 ) ? dig 13 (p1 5 ) ? dig 12 (p1 4 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) ? dig 19 (p2 3 ) ? dig 18 (p2 2 ) ? dig 17 (p2 1 ) ? dig 16 (p2 0 ) ? dig 15 (p1 7 ) ? dig 14 (p1 6 ) ? dig 13 (p1 5 ) ? dig 12 (p1 4 ) ? dig 11 (p1 3 ) ? dig 10 (p1 2 ) ? dig 9 (p1 1 ) ? dig 8 (p1 0 ) ? dig 7 (p0 7 ) ? dig 6 (p0 6 ) ? dig 5 (p0 5 ) ? dig 4 (p0 4 ) 0f80 16 0f81 16 0f82 16 0f83 16 0f84 16 0f85 16 0f86 16 0f87 16 0f88 16 0f89 16 0f8a 16 0f8b 16 0f8c 16 0f8d 16 0f8e 16 0f8f 16 0f90 16 0f91 16 0f92 16 0f93 16 0f94 16 0f95 16 0f96 16 0f97 16 0f98 16 0f99 16 0f9a 16 0f9b 16 0f9c 16 0f9d 16 0f9e 16 0f9f 16 0fa0 16 0fa1 16 0fa2 16 0fa3 16 0fa4 16 0fa5 16 0fa6 16 0fa7 16 0fa8 16 0fa9 16 0faa 16 0fab 16 0fac 16 0fad 16 0fae 16 0faf 16 0fb0 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 0fca 16 0fcb 16 0fcc 16 0fcd 16 0fce 16 0fcf 16 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 seg 34 seg 33 seg 32
137 2. application mitsubishi microcomputer 3819 group 2.5 fld controller 3819 group users manual fld digit allocation : fig. 2.5.36 example of fld digit allocation and segment arrangment setting example of display data (in case of using dig 11 ) : fig. 2.5.37 setting example of display data (in case of using dig 11 pin) seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 26 seg 27 seg 28 seg 29 seg 30 seg 31 seg 32 seg 33 seg 34 dig 4 dig 5 dig 6 dig 7 dig 8 dig 9 dig 10 dig 11 dig 12 dig 13 dig 14 dig 15 dig 16 dig 17 dig 18 dig 19 dig 11 address 0f80 16 bit7 0 bit6 0 bit5 0 bit4 0 bit3 0 bit2 0 bit1 0 bit0 0 ? ? ? ? ? ? ? ? 0f85 16 0 0 0 0 0 0 0 0 0f86 16 0 1 0 0 0 1 0 0 0f87 16 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? 0f95 16 0 0 0 0 0 0 0 0 0f96 16 1 1 0 0 0 1 0 1 0f97 16 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? 0fa5 16 0 0 0 0 0 0 0 0 0fa6 16 0 0 0 1 1 1 1 1 0fa7 16 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? 0fb5 16 0 0 0 0 0 0 0 0 0fb6 16 0 1 1 0 0 0 1 1 0fb7 16 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? 0fbf 16 0 0 0 0 0 0 0 0 0fc0 16 1 0 0 ? ? ? 0fc5 16 0 0 0 0fc6 16 1 0 0 0fc7 16 0 0 0 ? ? ? 0fcf 16 0 0 0 ? dig 11 (p1 4 ) ? dig 11 (p1 4 ) ? dig 11 (p1 4 ) ? dig 11 (p1 4 ) ? dig 11 (p1 4 ) : unused l l l l l l l l l l l l l l l l l l l l l
138 3819 group users manual 2. application mitsubishi microcomputer 3819 group 2.5 fld controller control procedure : figure 2.5.38 shows a control procedure. fig. 2.5.38 control procedure [5 5 7 dot display] reset initialization fldm2 (address:37 16 ), bit1 1 ~ ~ fld automatic display ram (address:0f80 16 to 0fcf 16 ) a data to be displayed fldm1 fldm2 p0sdr p2dpr p8spr paspr flddp (address:36 16 ) (address:37 16 ) (address:32 16 ) (address:33 16 ) (address:34 16 ) (address:35 16 ) (address:38 16 ) 00100001 2 00001101 2 00001111 2 00001111 2 11111111 2 11111111 2 00001111 2 set the related functions for using the fld automatic display. set segment/digit/port. to turn on the display of the corresponding segment : set to ?? to turn off the display of the corresponding segment : set to ?? ( note ) start the fld automatic dislay note : the display data is rewritten at any time. l l l l l .... ....
139 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function 2.6 interrupt interval determination function 2.6.1 related registers fig. 2.6.2 structure of interrupt interval determination control register fig. 2.6.1 structure of interrupt interval determination register interrupt interval determination register b7 b6 b5 b4 b3 b2 b1 b0 function at reset rw interrupt interval determination register (iid) [address:30 16 ] this register stores the values obtaind by counting the following interval with a counter sampling clock. falling edge interval rising edge interval both-sided edge interval (selected by the interrupt edge selection register) this register is read-only. l l l note : when the noise filter sampling clock selection bits (bits 2 and 3) of the interrupt interval determination control register (iidcon) (address: 31 16 ) is set to 00 (when no noise filter is used), the both-sided edge detection function is not available. 0 1 2 3 4 5 6 7 b ? ? ? ? ? ? ? ? 5 5 5 5 5 5 5 5 interrupt interval determination control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 0 0 0 0 0 interrupt interval determination control register (iidcon) [address:31 16 ] name interrupt interval determination circuit operating selection bit counter sampling clock selection bit noise filter sampling clock selection bits (int 2 ) one-sided/both-sided edge detection selection bit 0 : stopped 1 : operating 0 : f(x in )/256 1 : f(x in )/512 00 : filter stop 01 : f(x in )/64 10 : f(x in )/128 11 : f(x in )/256 0 : one-sided edge detection 1 : both-sided edge detection (note) 6 5 7 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." 0 0 0 5 5 5 note : when the noise filter sampling clock selection bits (bits 2 and 3) of the interrupt interval determination control register (iidcon) (address: 31 16 ) is set to 00 (when no noise filter is used), the both-sided edge detection function is not available.
140 2. application mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function 3819 group users manual fig. 2.6.3 structure of interrupt edge selection register fig. 2.6.4 structure of interrupt request register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 1 (ireq1) [address:3c 16 ] name int 0 interrupt request bit int 1 /zcr interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request serial i/o 1 interrupt request bit serial i/o automatic transfer interrupt request bit l l [ [ [ [ 4 5 6 7 0 0 0 0 serial i/o 2 interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request serial i/o 3 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ "0" is set by software, but not "1." int 2 interrupt request bit remote control/counter overflow interrupt request bit l l interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt edge selecton reigster (intedge) [address:3a 16 ] name int 0 interrupt edge selection bit int 1 /zcr interrupt edge selection bit int 2 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active int 3 interrupt edge selection bit 4 0 0 : falling edge active 1 : rising edge active int 4 interrupt edge selection bit 5 6 7 cntr 0 pin active edge switch bit 0 0 0 cntr 1 pin active edge switch bit int 4 /a-d conversion interrupt switch bit 0 : int 4 interrupt 1 : a-d conversion interrupt 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active
141 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function fig. 2.6.5 structure of interrupt control register 1 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address:3e 16 ] name int 0 interrupt enable bit int 1 /zcr interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 serial i/o 2 interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled serial i/o 3 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o 1 interrupt enable bit serial i/o automatic transfer interrupt enable bit l l int 2 interrupt enable bit remote control/counter overflow interrupt enable bit l l
142 2. application mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function 3819 group users manual 2.6.2 interrupt interval determination function reception of remote-control signal outline : remote-control signal is read in by both of the interrupt interval determination function using a noise filter and a timer interrupt. fig. 2.6.6 connection diagram [reception of remote-control signal] specifications : ? operation at f(x in ) = 8 mhz in the high-speed mode. ? the one-sided edge interval is measured. ? the noise filter is used. ? the remote control interrupt request is checked within the timer 2 interrupt (488 m s cycle) processing routine. figure 2.6.7 shows a function block diagram, and figure 2.6.8 shows a timing chart of data determination. fig. 2.6.7 function block diagram [reception of remote-control signal] p4 2 /int 2 reciever unit 3819 group remote-control reciever unit noise filter interrupt interval determination register determination of header or 0/1 1-byte reception data check ? recognition of each code ? read out a register ? compare the readout value with the reference value microcomputer hardware microcomputer software ? eliminate noise ? one-sided edge detection ? one-sided edge interval judgment
143 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function fig. 2.6.8 timing chart of data determination ? (overflow) input (int 2 ) interrupt request timer interrupt (488 m s) read interrupt interval determination register data determination ignore header 01 ignore ignore 1 check of an excess bit ~ ~ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ~ ~ ? ? ? ? ? ? ? ? ? ? ? ? ?
144 2. application mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function 3819 group users manual figure 2.6.9 shows a setting of related registers. fig. 2.6.9 setting of related registers [reception of remote-control signal] ireq1 1 interrupt request register 1 (address:3c 16 ) determination of the remote-control interrupt request bit (counter overflow interrupt request bit) int 2 pin : falling edge active intedge interrupt edge selection register (address:3a 16 ) 0 counter sampling clock : f(x in )/512 1 interrupt interval determination circuit operating iidcon interrupt interval determination control register (address:31 16 ) 1 1 0 noise filter sampling clock : f(x in )/128 1 one-sided edge detection main clock division ratio : select the high-speed mode. cpum cpu mode register (address:3b 16 ) 0 remote-control interrupt : disabled (counter overflow interrupt : disabled) icon1 interrupt control register 1 (address:3e 16 ) 0 determine header or data (0 or 1) with this value iid interrupt interval determination register (address:30 16 )
145 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function control procedure : when the registers are set as shown in figure 2.6.9, remote-control signals are receivable. figure 2.6.10 shows a control procedure and figure 2.6.11 shows reception of remote-control signal (timer 2 interrupt). fig. 2.6.10 control procedure (1) [reception of remote-control signal] ~ ~ reset initialization sei cpum intedge iidcon ireq1 nop icon1 cli .... .... (address:3b 16 ), bit6 (address:3a 16 ), bit2 (address:31 16 ) (address:3c 16 ), bit2 (address:3e 16 ), bit2 0 0 00010111 2 0 0
146 2. application mitsubishi microcomputer 3819 group 2.6 interrupt interval determination function 3819 group users manual fig. 2.6.11 control procedure (2) [reception of remote-control signal] (timer 2 interrupt) n y n y n n n y in range of 0 in range of 1 y y out of range of 0 or 1 rti n y n y rti rti rti rti rti start chacking an excess bit starting to receive a data etc. time error time error ?umber of bits?error (an excess bit is found) during checking an excess bit? an excess bit determined counter over? fixed data complete to receive? in range of data, 0 or 1? in range of header? iid (address : 0030 16 ) = ff? during checking an excess bit? input edge? push register to stack etc. clear edge read iid (address : 0030 16 ) shift a reception data timer 2 interrupt cy 1 ? cy 0 ?
147 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.7 zero cross detection circuit 2.7 zero cross detection circuit 2.7.1 related registers fig. 2.7.2 structure of interrupt edge selection register fig. 2.7.1 structure of zero cross detection control register interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt edge selecton reigster (intedge) [address:3a 16 ] name int 0 interrupt edge selection bit int 1 /zcr interrupt edge selection bit int 2 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active int 3 interrupt edge selection bit 4 0 0 : falling edge active 1 : rising edge active int 4 interrupt edge selection bit 5 6 7 0 0 0 int 4 /a-d conversion interrupt switch bit cntr 0 pin active edge switch bit 0 : int 4 interrupt 1 : a-d conversion interrupt 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active cntr 1 pin active edge switch bit zero cross detection control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 7 0 0 0 0 0 0 0 zero cross detection control register (zcrcon) [address:39 16 ] name zero cross detection on/off selection bit one-sided/both-sided edge detection selection bit zero cross detection circuit input bit (read-only) 0 : without passing through zero cross detection comparator 1 : passing through zero cross detection comparator 0 : one-sided edge detection 1 : both-sided edges detection ( note ) 00 : note use noise filter 01 : f(x in )/64 or f(x cin )/64 10 : f(x in )/128 or f(x cin )/128 11 : f(x in )/256 or f(x cin )/256 0 : less than 0 v 1 : 0 v or more b3 b2 5 nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0." 5 noise filter sampling clock selection bits (int 1 ) 6 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." 5 5 when the noise filter sampling clock selection bits (bits 2 and 3) of the zero cross detection control register (zcrcon) (address: 39 16 ) is set to 00 (when no noise filter is used), the both-sided edge detection function is not available. note :
148 2. application mitsubishi microcomputer 3819 group 2.7 zero cross detection circuit 3819 group users manual fig. 2.7.3 structure of interrupt request register 1 fig. 2.7.4 structure of interrupt control register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 1 (ireq1) [address:3c 16 ] name int 0 interrupt request bit int 1 /zcr interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request serial i/o 1 interrupt request bit serial i/o automatic transfer interrupt request bit l l [ [ [ [ 4 5 6 7 0 0 0 0 serial i/o 2 interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request serial i/o 3 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ "0" is set by software, but not "1." int 2 interrupt request bit remote control/counter overflow interrupt request bit l l interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address:3e 16 ] name int 0 interrupt enable bit int 1 /zcr interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 serial i/o 2 interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled serial i/o 3 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o 1 interrupt enable bit serial i/o automatic transfer interrupt enable bit l l int 2 interrupt enable bit remote control/counter overflow interrupt enable bit l l 0 : no interrupt request 1 : interrupt request
149 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.7 zero cross detection circuit 2.7.2 connection example of zero cross detection circuit figure 2.7.5 shows a connection example of the zero cross detection circuit. r 1 is a current limiting resistor. determine its value according to the current standard of the clamp diode. in this case, the ac input is not the effective value of 100 v but is the peak value of 140 v. r 2 is a noise elimination resistor. connect a resistor of about 1 k w near the port. fig. 2.7.5 connection example of zero cross detection circuit 3819 group p4 5 /int 1 /zcr r 2 r 1 140 v ?40 v ac 100 v peak value effective value v cc v ss
150 2. application mitsubishi microcomputer 3819 group 2.7 zero cross detection circuit 3819 group users manual 2.7.3 zero cross detection circuit application example 1 clock count using zcr interrupt (without using a noise filter) outline : the clock is counted up every second by using the zcr interrupts. specifications : ? the noise filter is not used. ? the commercial frequency (50 hz or 60 hz) is input. ? the clock is counted up by using the zcr interrupts. figure 2. 7. 6 shows a setting of related registers. fig. 2.7.6 setting of related registers [clock count using zcr interrupt (without using a noise filter)] passing through the zero cross detection circuit ( note ) zcrcon zero cross detection control register (address:39 16 ) 1 0 0 noise filter sampling clock : without using a noise filter zcr active edge : falling edge active ( note ) intedge interrupt edge selection register (address:3a 16 ) 0 ireq1 interrupt request register 1 (address:3c 16 ) set the int 1 /zcr interrupt request bit to 0 0 icon1 interrupt control register 1 (address:3e 16 ) int 1 /zcr interrupt : enabled 1 ireq1 interrupt request register 1 (address:3c 16 ) zcr interrupt request when changing the values of bit 0 of the zero cross detection control register and bit 1 of the interrupt edge selection register, make sure the following contents. 1. during changeing, set bit 1 of the interrupt control register 1 to 0. 2. after changeing, set bit 1 of the interrupt request register 1 to 0. note :
151 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.7 zero cross detection circuit control procedure : set the related registers according to figure 2.7.6. at the falling edge of the commercial frequency (50 hz or 60 hz), the zcr interrupt occurs. a the clock is counted up every second in the zcr interrupt processing routine. figure 2.7.7 shows a control procedure. fig. 2.7.7 control procedure [clock count using zcr interrupt (without using a noise filter)] all interrupts : disabled main clock division ratio : select the high-speed mode setting of the zero cross detection control register set the int 1 /zcr interrupt request bit to ? zcr interrupt : enabled input 50 hz (60 hz) interrupts : enabled note 1 : when using the index x mode flag (t). note 2 : when using the decimal mode flag (d). push into the register used in the interrupt processing routine. input 50 hz (60 hz) pop registers which is pushed to stack . ~ ~ reset initialization sei clt cld cpum zcrcon ireq1 nop icon1 1 second counter (internal ram) cli .... .... (address:3b 16 ), bit6 (address:39 16 ) (address:3c 16 ), bit1 (address:3e 16 ), bit1 0 00000001 2 0 1 50(60) zcr interrupt processing routine clt (note 1) cld (note 2) push register to stack rti 1 0 = 0 1 second counter = 0? 1 second counter ?1 1 second counter 50(60) clock count up (second?ear) pop registers l l l l l l l l l l
152 2. application mitsubishi microcomputer 3819 group 2.7 zero cross detection circuit 3819 group users manual 2.7.4 zero cross detection circuit application example 2 clock count using zcr interrupt (using a noise filter) outline : the clock is counted up every second by using the zcr interrupts. specifications : ? f(x in )=4 mhz ? the noise filter (sampling clock : f(x in )/256) is used. (pulse less than 64 m s is eliminated as a noise.) ? the commercial frequency (50 hz or 60 hz) is input. ? the clock is counted up by using the zcr interrupts. figure 2.7.8 shows a setting of related registers. fig. 2.7.8 setting of related registers [clock count using zcr interrupt (using a noise filter)] zcr active edge : falling edge active ( note ) intedge interrupt edge selection register (address:3a 16 ) 0 ireq1 interrupt request register 1 (address:3c 16 ) set the int 1 /zcr interrupt request bit to ? 0 icon1 interrupt control register 1 (address:3e 16 ) int 1 /zcr interrupt : enabled 1 ireq1 interrupt request register 1 (address:3c 16 ) zcr interrupt request passing through the zero cross detection circuit ( note ) zcrcon zero cross detection control register (address:39 16 ) 1 1 1 noise filter sampling clock : f(x in )/256 0 selection of one-sided edge detection when changing the values of bit 0 of the zero cross detection control register and bit 1 of the interrupt edge selection register, make sure the following contents. 1. during changeing, set bit 1 of the interrupt control register 1 (disable zcr interrupt) to ?? 2. after changeing, set bit 1 of the interrupt request register 1 (no zcr interrupt request) to ?? however, the value of bit 1 of the interrupt request register 1 is changed with a maximum delay of 2 sampling clocks by using a noise filter. thus, after changing, set this bit to ??after a wait of 2 sampling clocks. note :
153 2. application 3819 group users manual mitsubishi microcomputer 3819 group 2.7 zero cross detection circuit control procedure : set the related registers according to figure 2.7.8. at the falling edge of the commercial frequency (50 hz or 60 hz), the zcr interrupt occurs. a the clock is counted up every second in the zcr interrupt processing routine. figure 2.7.9 shows a control procedure. fig. 2.7.9 control procedure [clock count using zcr interrupt (using a noise filter)] zcr interrupt processing routine ( note 1 ) clt ( note 2 ) cld ( note 3 ) push register to stack rti ~ ~ reset initialization sei clt cld cpum zcrcon wait of 2 sampling clocks ireq1 nop icon1 1 second counter (internal ram) cli .... .... (address:3b 16 ), bit6 (address:39 16 ) (address:3c 16 ), bit1 (address:3e 16 ), bit1 0 00000001 2 0 1 50(60) = 0 1 second counter = 0? 1 second counter ?1 1 second counter 50(60) clock count up (second?ear) pop registers all interrupts : disabled main clock division ratio : select the high-speed mode setting of the zero cross detection control register set the int 1 /zcr interrupt request bit to ? zcr interrupt : enabled input 50 hz (60 hz) interrupts : enabled note 2 : when using the index x mode flag (t). note 3 : when using the decimal mode flag (d). push into the register used in the interrupt processing routine. input 50 hz (60 hz) pop registers which is pushed to stack note 1 : the zcr interrupt occurs with delay of the zero cross by a minimum of 1 sampling clock or a maximum of 2 sampling clocks because a noise filter is used. l l l l l l l l l l 1 0
154 2. application 3819 group users manual mits ubishi microcomputer 3819 group 2.8 reset 2.8 reset 2.8.1 connection example of reset ic fig. 2.8.1 example of poweron reset circuit figure 2.8.2 shows the system example which switch to the ram backup mode by detecting a drop of the system power source voltage with the int interrupt. fig. 2.8.2 ram back-up system m62022l 3819 group v cc 1 5 3 91 35 40 0.1 m f power source gnd delay capacity 4 output m62009l, m62009p, m62009fp 7 5 4 91 35 3 6 2 1 v cc 1 reset int gnd cd v1 v cc 2 system power source voltage +5 3819 group v cc + reset v ss reset int
155 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual 2.9 clock generating circuit 2.9.1 related registers fig. 2.9.2 structure of timer 2 fig. 2.9.1 structure of timer i (i = 1, 3) timer i b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer i (ti) (i = 1, 3) [address:20 16 , 22 16 ] the counter value of the timer i is set. the value set in this register is written to both the timer i and the timer i latch at the same time. when the timer i is read out, the value (count value) of the timer i is read out. l l l timer 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 timer 2 (t2) [address:21 16 ] the counter value of the timer 2 is set. the value set in this register is written to both the timer 2 and the timer 2 latch at the same time. when the timer 2 is read out, the value (count value) of the timer 2 is read out. l l l
156 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.4 structure of timer 34 mode register fig. 2.9.3 structure of timer 12 mode register timer 12 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 12 mode register (t12m) [address:28 16 ] name timer 1 count stop bit timer 2 count stop bit timer 1 count source selection bit timer 2 count source selection bits timer 1 output selection bit (p4 6 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : f(x cin ) 00 : timer 1 underflow 01 : f(x cin ) 10 : external count input cntr 0 11 : not available 0 : i/o port 1 : timer 1 output b5 b4 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 5 5 timer 34 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 34 mode register (t34m) [address:29 16 ] name timer 3 count stop bit timer 4 count stop bit timer 3 count source selection bit timer 4 count source selection bits timer 3 output selection bit (p4 7 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : timer 2 underflow 00 : f(x in )/16 or f(x cin )/16 01 : timer 3 underflow 10 : external count input cntr 1 11 : not available 0 : i/o port 1 : timer 3 output b5 b4 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 5 5
157 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.5 structure of cpu mode register fig. 2.9.6 structure of interrupt request register 1 cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 1 cpu mode register (cpum) [address:3b 16 ] name processor mode bits stack page selection bit 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : 0 : 0 page 1 : 1 page 5 6 7 0 0 0 1 main clock (x in -x out ) stop bit main clock division ratio selection bit internal system clock selection bit 0 : operating 1 : stopped 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) 0 : x in -x out selected (middle/high-speed mode) 1 : x cin -x cout selected (low-speed mode) b1b0 0 : i/o port function 1 : x cin Cx cout oscillating function 4 port xc switch bit x cout drivability selection bit 0 : low 1 : high interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 1 (ireq1) [address:3c 16 ] name int 0 interrupt request bit int 1 /zcr interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request serial i/o 1 interrupt request bit serial i/o automatic transfer interrupt request bit l l [ [ [ [ 4 5 6 7 0 0 0 0 serial i/o 2 interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request serial i/o 3 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ "0" is set by software, but not "1." int 2 interrupt request bit remote control/counter overflow interrupt request bit l l
158 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.8 structure of interrupt control register 1 fig. 2.9.7 structure of interrupt request register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 2 (ireq2) [address:3d 16 ] name timer 3 interrupt request bit timer 4 interrupt request bit timer 5 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request timer 6 interrupt request bit [ [ [ [ 5 6 7 0 0 0 : no interrupt request 1 : interrupt request nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." fld blanking interrupt request bit fld digit interrupt request bit l l int 4 interrupt request bit a-d conversion interrupt request bit l l 0 : no interrupt request 1 : interrupt request [ [ [ "0" is set by software, but not "1." 4 0 0 : no interrupt request 1 : interrupt request int 3 interrupt request bit [ 0 [ interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address:3e 16 ] name int 0 interrupt enable bit int 1 /zcr interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 serial i/o 2 interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled serial i/o 3 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o 1 interrupt enable bit serial i/o automatic transfer interrupt enable bit l l int 2 interrupt enable bit remote control/counter overflow interrupt enable bit l l
159 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.9 structure of interrupt control register 2 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control reigster 2 (icon2) [address:3f 16 ] name timer 3 interrupt enable bit timer 4 interrupt enable bit timer 5 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer 6 interrupt enable bit 5 6 7 0 0 0 : interrupt disabled 1 : interrupt enabled fix this bit to "0." fld blanking interrupt enable bit fld digit interrupt enable bit l l int 4 interrupt enable bit a-d conversion interrupt enable bit l l 0 : interrupt disabled 1 : interrupt enabled 4 0 0 : interrupt disabled 1 : interrupt enabled int 3 interrupt enable bit 0 0
160 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual 2.9.2 clock generating circuit application examples (1) status transition upon a power failure outline : the clock is counted up every second by using the timer interrupt during a power failure. specifications : ? keep a power consumption as low as possible while maintaining a clock function. ? f(x in ) = 4.19 mhz, f(x cin ) = 32.768 khz ? port processing input port : fix to h or l level in the external unit. output port : fix to an output level which does not cause a current flow to the external unit. fig. 2.9.10 connection diagram [ example ] when a circuit turns on led at l output level, fix the output level to h. i/o port : input port fix to h or l level in the external unit . output port output the data which does not consume current. v ref : supplying to the reference voltage input pin is stopped by the external circuit. p4 5 /zcr (using as the input port) : fix to h level in the external unit . figure 2.9.11 shows a status transition diagram upon a power failure, figure 2.9.12 shows a setting of related registers, and figure 2.9.13 shows a control procedure. [status transition upon a power failure] fig. 2.9.11 status transition diagram upon a power failure input port ( note ) 3819 group power failure detection signal signal is detected by inputting to each input port, interrupt input pin, and analog input pin. note : x in x cin internal system clock f(x in )/2 f(x cin )/2 change the internal system clock to f(x in )/2 (high-speed mode). after detecting a power failure, change the internal system clock to f(x cin ) and stop operating of f(x in ). f(x in )/8 release reset detection of power failure selection of x cin oscillating function
161 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.12 setting of related registers [status transition upon a power failure] main clock f(x in ) : high-speed mode ( note 1 ) cpum cpu mode register (address:3b 16 ) 0 0 0 0 0 0 x cin Cx cout : oscillating cpum cpu mode register (address:3b 16 ) 0 0 1 0 0 0 ( note 2 ) internal system clock : f(x cin ) (low-speed mode) cpum cpu mode register (address:3b 16 ) 0 1 ( note 2 ) 1 0 0 0 main clock f(x in ) : stopped cpum cpu mode register (address:3b 16 ) 0 1 1 1 0 0 ( note 2 ) note 1 : only when selecting the high-speed mode. note 2 : when bit 6 is set to 1, the middle-speed mode is selected.
162 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual control procedure : set the related registers in the order shown below to prepare for a power failure. fig. 2.9.13 control procedure [status transition upon a power failure] reset initialization cpum (address:3b 16 ), bit6 0 cpum (address:3b 16 ), bit4 1 n y be concluded the condition recovered from a power failure? recovery processing from a power failure set so that a timer interrupt occurs every second. execute the wit instruction. n y detect a power failure? ~ ~ 1( note ) 1( note ) (address:3b 16 ), bit7 (address:3b 16 ), bit5 cpum cpum ~ ~ middle-speed mode when select the main clock f(x in )/2 (high-speed mode) select the x cin -x cout oscillating function internal system clock : select the low-speed mode f(x cin ). main clock f(x in ) : stopped at a power failure, the clock count is perform- ed during processing the timer interrupts (occur every second). note : do not switch at the same time. l l l l l l
163 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual power failure detection signal input port ( note ) 3819 group signal is detected by inputting to each input port, interrupt input pin, and analog input pin. note : x in x cin internal system clock f(x in )/2 f(x cin )/2 change the internal system clock to f(x in )/2 (high-speed mode). f(x in )/8 release reset detection of power failure selection of x cin oscillating function after detecting a power failure, change the internal system clock to f(x cin ) and stop operating of f(x in ). (2) counting without clock error during a power failure outline : it keeps counting without clock errors during a power failure. specifications : ? keep a power consumption as low as possible while maintaining a clock function. ? keep counting a clock correctly. ? f(x in ) = 4.19 mhz, f(x cin ) = 32.768 khz ? the timer 1 interrupt is used in a normal power state. the timer 3 interrupt is used during a power failure. ? port processing input port : fix to h or l level in the external unit. output port : fix to an output level which does not cause a current flow to the external unit. [ example ] when a circuit turns on led at l output level, fix the output level to h. i/o port : input port fix to h or l level in the external unit. output port output the data which does not consume current. v ref : supplying to the reference voltage input pin is stopped by the external circuit. p4 5 /zcr (using as the input port) : fix to h level in the external unit. figure 2.9.15 shows a timing chart of counting without clock errors during a power failure, figure 2.9.16 shows a structure of a clock counter, and figures 2.9.17 and 2.9.18 show a setting of related registers. fig. 2.9.15 timing chart of counting without clock errors during a power failure fig. 2.9.14 connection diagram [counting without clock errors during a power failure]
164 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.16 structure of a clock counter f(x in ) = 4.19 mhz 1/16 244 m s 1 second 1 minute counter timer 1 interrupt timer 3 interrupt 1/64 1/256 1/16 1/60 base counter timer 1 fixed 1 second counter minute/hour/day/ month/year f(x cin ) = 32.768 khz 244 m s 1/8 1/256 1/16 timer 2 timer 1 timer 3 software timer hardware timer when the system recovers from a power failure, add the switching process time taken for the recovery.
165 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.17 setting of related registers (1) [counting without clock errors during a power failure] set ?ivision ratio ?1 t1 timer 1 (address:20 16 ) 63 timer 3 count source : timer 2 underflow 0 timer 3 count : operating t34m timer 34 mode register (address:29 16 ) 1 timer 3 output selection : i/o port 0 set ?0 16 t12m timer 12 mode register (address:28 16 ) 00 0 0 0 0 x cin ? cout : oscillating cpum cpu mode register (address:3b 16 ) 0 0 00 1 0 ireq1 interrupt request register 1 (address:3c 16 ) set the timer 1 interrupt request bit to ? 0 ireq2 interrupt request register 2 (address:3d 16 ) set the timer 3 interrupt request bit to ? 0 main clock f(x in ) : high-speed mode cpum cpu mode register (address:3b 16 ) 0 0 00 internal system clock : f(x in )/2 (high-speed mode)
166 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.18 setting of related registers (2) [counting without clock errors during a power failure] t1 timer 1 (address:20 16 ) 7 set ?ivision ratio ?1?to each timer t2 timer 2 (address:21 16 ) 255 t3 timer 3 (address:22 16 ) 15 icon1 interrupt control register 1 (address:3e 16 ) timer 1 interrupt : enabled 1 internal system clock : f(x cin ) (low-speed mode) cpum cpu mode register (address:3b 16 ) 0 1 00 1 0 main clock f(x in ) : stopped cpum cpu mode register (address:3b 16 ) 0 1 00 1 icon1 interrupt control register 1 (address:3e 16 ) timer 1 interrupt : disabled 0 icon2 interrupt control register 2 (address:3f 16 ) timer 3 interrupt : enabled 1 0
167 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual control procedure : set the related registers in the order shown below to prepare for a power failure. fig. 2.9.19 control procedure (1) [counting without clock errors during a power failure] middle-speed mode select the x cin -x cout oscillating function main clock division ratio : select the high-speed mode set for being count the base and 1 second counters during the timer 1 interrupts. in the normal power state, these software counters generate one second. timer 1 count source : f(x cin ) timer 1 interrupt : disabled internal system clock : select the low-speed mode f(x cin ). main clock f(x in ) : stopped set for generating the timer 3 interrupts every second. generate 1 second by the hardware timer during a power failure. timer 3 interrupt : enabled generate the timer 3 interrupts every second (recover from a wait mode) note : do not switch at the same time. n y recovery processing from a power failure execute the wit instruction n y detect a power failure? icon2(address:3f 16 ), bit0 1 ~ ~ reset initialization cpum (address:3b 16 ), bit4 1 cpum t1 t12m t34m t34m ireq1 ireq2 base counter 1second counter icon1 (address:3b 16 ), bit6 (address:20 16 ) (address:28 16 ) (address:29 16 ), bit6, bit0 (address:29 16 ), bit2 (address:3c 16 ), bit6 (address:3d 16 ), bit0 (internal ram) (internal ram) (address:3e 16 ), bit6 0 64? 00 16 0 1 0 0 256? 16? 1 ~ ~ (address:28 16 ), bit2 (address:3e 16 ), bit6 (address:3b 16 ), bit7 (address:3b 16 ), bit5 (address:3c 16 ), bit6 (address:3d 16 ), bit0 (address:20 16 ) (address:21 16 ) (address:22 16 ) t12m icon1 cpum cpum ireq1 ireq2 t1 t2 t3 1 0 1( note ) 1( note ) 0 0 8? 256? 16? be concluded the condition recovered from a power failure? l l l l l l l l l l l l
168 2. application mitsubishi microcomputer 3819 group 2.9 clock generating circuit 3819 group users manual fig. 2.9.20 control procedure (2) [counting without clock errors during a power failure] timer 3 interrupt processing routine push register to stack etc. .... count 1 minitue counter (internal ram) renew time, day, month, year rti ~ ~ n y 1 minitue counter overflow ?
chapter 3 appendix 3.1 notes on use 3.2 countermeasures against noise 3.3 control registers 3.4 mask rom ordering method 3.5 mark specification form 3.6 package outline 3.7 memory map 3.8 pin configuration
170 3. appendix mitsubishi microcomputer 3819 group 3.1 notes on use 3819 group users manual 3.1 notes on use 3.1.1 notes on interrupts for the products able to switch the external interrupt detection edge, switch it as the following sequence. reason the interrupt circuit recognizes the switching of the detection edge as the change of external input signals. this may cause an unnecessary interrupt. fix the bit 7 of the interrupt control register 2 to 0. figure 3.1.1 shows the structure of the interrupt control register 2. clear an interrupt enable bit to 0 (interrupt disabled) switch the detection edge clear an interrupt request bit to 0 (no interrupt requ- est issued) nop (one or more instructions) set the interrupt enable bit to 1 ( interrupt enabled ) fig. 3.1.1 structure of interrupt control register 2 3.1.2 notes on the fld controller and the serial i/o automatic transfer function when using the fld controller function and the serial i/o automatic transfer function, set the system clock to the high- speed mode or the middle-speed mode. 3.1.3 notes on the a-d converter make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 m f to 1 m f. further, be sure to verify the operation of application products on the user side. reason an analog input pin includes the capacitor for analog voltage comparison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a-d comparison precision to be worse. pins av cc and av ss are a-d converter power source pins. connect them as following : l av cc : connect to the v cc line which is the analog system l av ss : connect to the v ss line which is the analog system b7 b0 interrupt control register 2 address 003f 16 interrupt control bits not used fix this bit to ?? 0
3. appendix 171 mitsubishi microcomputer 3819 group 3.1 notes on use 3819 group users manual the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. thus, make sure the following during an a-d conversion. l f(x in ) is 500 khz or more . l do not execute the stp instruction and wit instruction. 3.1.4 notes on the reset pin n case where the reset signal rise time is long, connect a ceramic capacitor or others across the reset pin and the v ss pin. and use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, note the following : l make the length of the wiring which is connected to a capacitor. l be sure to check the operation of application products on the user side. reason if the several nanosecond or several ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer failure. 3.1.5 notes on input and output pins in stand-by state* for low-power dissipation, do not make input levels of an input and an i/o port undefined, especially for the i/o ports of the p-channel and the n-channel open-drain. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: l external circuit l variation of output levels during the ordinary operation when using built-in pull-up or pull-down resistor as an option, note on varied current values. l when setting as an input port : fix its input level l when setting as an output port : prevent current from flowing out to external reason even when setting as an output port with its direction register, in the following state : l p-channel......when the content of the data register (port latch) is 0 l n-channel......when the content of the data register (port latch) is 1 the transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes undefined depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an i/o port are undefined. this may cause power source current. * stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction
172 3. appendix mitsubishi microcomputer 3819 group 3.1 notes on use 3819 group users manual when the data register (port latch) of an i/o port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the data register of an i/o port, the following is executed to all bits of the data register. l as for a bit which is set to an input port : the pin state is read in the cpu, and is written to this bit after bit managing. l as for a bit which is set to an output port : the bit value is read in the cpu, and is written to this bit after bit managing. note the following : l even when a port which is set as an output port is changed for an input port, its data register holds the output data. l as for a bit of which is set to an input port , its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents * bit managing instructions : seb and clb instruction when not using the a-d converter, connect the a-d converter power source av ss pin as follows : l av ss : connect to the v ss pin reason if the av ss pin is opened, the microcomputer may have a failure because of noise or others. 3.1.6 notes on clock synchronous serial i/o when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to 1 at h of the s clk input level. also, write data to the transmit buffer register at h of the s clk input level.
3. appendix 173 mitsubishi microcomputer 3819 group 3.1 notes on use 3819 group users manual 3.1.7 notes on built-in prom (1) programming adapter to write into or read from data the internal prom, use the dedicated programming adapter and general-purpose prom programmer as shown in table 3.1.1. table 3.1.1 programming adapter microcomputer m38197eafs m38197eafp (one-time blank) programming adapter pca4738l-100a pca4738f-100a (2) write and read in prom mode, operation is the same as that of the m5m27c101, but programming conditions of prom programmer are not set automatically because there are no built-in device id codes. accurately set the following conditions for data write/read. do not apply 21 v to the vpp pin (is also used as port p4 0 ), or the product may be permanently damaged. l programming voltage : 12.5 v l setting of programming adapter switch : refer to table 3.1.2 l setting of prom programmer address : refer to table 3.1.3 table 3.1.2 setting of programming adapter switch programming adapter pca4738l-100a pca4738f-100a sw 1 p-channel sw 2 off (cmos) sw 3 off table 3.1.3 setting of prom programmer address microcomputer m38197eafs m38197eafp prom programmer completion address (note) address : fffd 16 prom programmer start address (note) address : 6080 16 note : because addresses 6000 16 to 607f 16 and fffe 16 to ffff 16 are the reserved rom area, do not use these addresses. (3) erasing contents of the windowed eprom (38197 eafs) are erased by an ultraviolet light source with the wavelength 2537-angstrom . at least 15 w sec/cm are required to erase eprom contents. 2
174 3. appendix mitsubishi microcomputer 3819 group 3.2 countermeasures against noise 3819 group users manual 3.2 countermeasures against noise countermeasures against noise are described below. the following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.2.1 shortest wiring length the wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) wiring for the reset pin make the length of wiring which is connected to the reset pin as short as possible. especially, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). reason the reset works to initialize a microcomputer. the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. fig. 3.2.1 wiring for the reset pin (2) wiring for clock input/output pins l make the length of wiring which is connected to clock i/o pins as short as possible. l make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. l separate the v ss pattern only for oscillation from other v ss patterns. reason a microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. reset reset circuit noise v ss v ss reset circuit v ss reset v ss
175 3. appendix 3819 group users manual mitsubishi microcomputer 3819 group 3.2 countermeasures against noise fig. 3.2.2 wiring for clock i/o pins (3) wiring for the v pp pin of the one time prom version and the eprom version l make the length of wiring which is connected to the v pp pin as short as possible. l connect an approximately 5 k w resistor to the v pp pin in serial. reason the v pp pin of the one time prom and the eprom version is the power source input pin for the built-in prom. when programming in the built-in prom, the impedance of the v pp pin is low to allow the electric current for wiring flow into the prom. because of this, noise can enter easily. if noise enters the v pp pin, abnormal in struction codes or data are read from the built-in prom, which may cause a program runaway. 3.2.2 connection of a bypass capacitor across the vss line and the vcc line connect an approximately 0.1 m f bypass capacitor across the v ss line and the v cc line as follows: l connect a bypass capacitor across the v ss pin and the v cc pin at equal length . l connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. l use lines with a larger diameter than other signal lines for v ss line and v cc line. fig. 3.2.3 wiring for the v pp pin of the one time prom and the eprom version fig. 3.2.4 bypass capacitor across the v ss line and the v cc line aaa aaa aaa aaa aa aa aa aa aaa aaa aa aa aa aa a a a x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines a a a a aa aa aa aa v ss v cc noise x in x out v ss x in x out v ss 3819 group p4 0 /v pp approximately 5k w
176 3. appendix mitsubishi microcomputer 3819 group 3.2 countermeasures against noise 3819 group users manual fig.3.2.5 analog signal line and a resistor and a capacitor 3.2.3 wiring to analog input pins l connect an approximately 100 w to 1 k w resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. l connect an approximately 1000 pf capacitor across the v ss pin and the analog input pin. besides, connect the capacitor to the v ss pin as close as possible. reason signals which is input in an analog input pin (such as an a-d converter input pin) are usually output signals from sensor. the sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. this long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. if a capacitor between an analog input pin and the v ss pin is grounded at a position far away from the v ss pin, noise on the gnd line may enter a microcomputer through the capacitor. 3.2.4. oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) keeping an oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. reason in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual induct- ance. (2) keeping an oscillator away from signal lines where potential levels change frequently install an oscillator away from signal lines where poten- tial levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. reason signal lines where potential levels change frequently (such as the cntr pin line) may affect other lines at signal rising or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. fig.3.2.7 wiring to a signal line where potential levels change frequently fig.3.2.6 wiring for a large current signal line analog input pin v ss sensor noise microcomputer x in x out v ss m microcomputer mutual inductance large current gnd x in x out v ss cntr do not cross
177 3. appendix 3819 group users manual mitsubishi microcomputer 3819 group 3.2 countermeasures against noise 3.2.5 setup for i/o ports setup i/o ports using hardware and software as follows: l connect a resistor of 100 w or more to an i/o port in series. l as for an input port, read data several times by a program for checking whether input levels are equal or not. l as for an output port, since the output data may reverse because of noise, rewrite data to its data register at fixed periods. l rewirte data to direction registers and pull-up control registers (only the product having it) at fixed periods. fig. 3.2.8 setup for i/o ports when a direction register is set to input port again at fixed periods, a several-nanosecond short pulse may be output from this port. if this is undesirable, connect a capacitor to this port to remove the noise pulse. 3.2.6 providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal opera- tion. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer pro- vided by software. in the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt process- ing routine detects errors of the main routine. this example assumes that interrupt processing is repeated multiple times in a single main routine process- ing. l assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: fig. 3.2.9 watchdog timer by software n+1 3 (counts of interrupt processing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. l watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing count after the initial value n has been set. l detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: ? if the swdt contents do not change after interrupt processing if the changed swdt contents are abnormal (in figure 3.2.9, the main routine determines that the interrupt processing routine has failed only if the swdt contents do not change). direction register data register data bus i/o port pins noise noise main routine (swdt) ? n cli main processing (swdt) interrupt processing routine errors 1 n = n interrupt processing routine (swdt) ? (swdt)1 interrupt processing (swdt) main routine errors > 0 0 rti return = n? 0?
178 3. appendix mitsubishi microcomputer 3819 group 3.2 countermeasures against noise 3819 group users manual l decrements the swdt contents by 1 at each interrupt processing. l determins that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). l detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: ? if the swdt contents are not initialized to the initial value n but continued to decrement and if they exceed the limit (and reach 0 or less).
179 mitsubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual 3.3 control registers fig. 3.3.2 structure of port p2 direction register fig. 3.3.1 structure of port pi direction register (i = 4, 5, 6, 7, 8, a, b) port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 4, 5, 6, 7, 8, a, b) [address:09 16 , 0b 16 , 0d 16 , 0f 16 , 11 16 , 15 16 , 17 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ( note ) 5 5 5 5 5 5 5 5 note : ( note ) port p4 direction register [address:09 16 ] ports p4 0 and p4 5 are input ports. accordingly, these bits do not have a direction register function. port p2 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name port p2 direction register (p2d) [address:05 16 ] 4 5 6 7 port p2 direction register 0 0 0 0 0 : port p2 4 input mode 1 : port p2 4 output mode 0 : port p2 5 input mode 1 : port p2 5 output mode 0 : port p2 6 input mode 1 : port p2 6 output mode 0 : port p2 7 input mode 1 : port p2 7 output mode 5 5 5 5 2 3 1 1 55 55 0 1 1 1 55 55 because p2 0 to p2 3 are output ports, these bits do not have a direction register function and nothing is allocated.
180 3. appendix mitsubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.3 structure of serial i/o automatic transfer data pointer fig. 3.3.4 structure of serial i/o 1 control register when an external clock is selected in the serial i/o 1 automatic transfer mode, the s rdy1 signal pin is used as the cs signal input pin. serial i/o automatic transfer data pointer b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 6 7 0 serial i/o automatic transfer data pointer (siodp) [address:18 16 ] 0 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." indicate an address of serial i/o automatic transfer ram. ? ? ? ? ? 0 5 5 5 5 serial i/o 1 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 serial i/o 1 control register (sio1con) [address:19 16 ] name internal synchronous clock selection bits synchronous clock selection bit 000 : f(x in )/8 or f(x cin )/8 001 : f(x in )/16 or f(x cin )/16 010 : f(x in )/32 or f(x cin )/32 011 : f(x in )/64 or f(x cin )/64 110 : f(x in )/128 or f(x cin )/128 111 : f(x in )/256 or f(x cin )/256 0 : external clock 1 : internal clock p6 5 /s out1 p-channel output disable bit b2 b1b0 serial i/o 1 port selection bit (p6 5 ,p6 6 ,p6 7 ) [ transfer direction selection bit 0 : lsb first 1 : msb first s rdy1 output selection bit (p6 7 ) 0 : i/o port 1 : s rdy1 /cs signal pin ( note ) 0 : i/o port 1 : s out1 , s clk11 , s clk12 signal pins [ [ [ valid only in the serial i/o automatic transfer mode 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) note :
181 mitsubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.6 structure of serial i/o automatic transfer interval register fig. 3.3.5 structure of serial i/o automatic transfer control register serial i/o automatic transfer control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 1 3 5 7 0 0 0 0 0 0 0 0 serial i/o automatic transfer control register (sioac) [address:1a 16 ] name automatic transfer control bit 0 : serial i/o ordinary mode (serial i/o 1 interrupt) 1 : automatic transfer mode (serial i/o automatic transfer interrupt) nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." automatic transfer start bit synchronous clock output pin selection bit 0 : s clk11 1 : s clk12 transfer mode switch bit 0 : fullduplex (transmit / receive) mode 1 : transmit-only mode 0 : transfer completion 1 : transferring (starts by writing 1) 5 6 4 5 5 5 serial i/o automatic transfer interval register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 6 7 0 serial i/o automatic transfer interval register (sioai) [address:1c 16 ] 0 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." ti = (n + 2) 5 tc ti = a length of transfer interval n = a setting value tc = a length of a bit of transfer clock 0 0 0 0 0 0 5 5 5 5
182 3. appendix mitsubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.8 structure of serial i/o 3 control register fig. 3.3.7 structure of serial i/o 2 control register serial i/o 2 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 0 0 0 0 0 0 0 serial i/o 2 control register (sio2con) [address:1d 16 ] name internal synchronous clock selection bits synchronous clock selection bit 000 : f(x in )/8 or f(x cin )/8 001 : f(x in )/16 or f(x cin )/16 010 : f(x in )/32 or f(x cin )/32 011 : f(x in )/64 or f(x cin )/64 110 : f(x in )/128 or f(x cin )/128 111 : f(x in )/256 or f(x cin )/256 0 : external clock 1 : internal clock b2 b1b0 serial i/o 2 port selection bit (p5 1 ,p5 2 ) transfer direction selection bit 0 : lsb first 1 : msb first s rdy2 output selection bit (p5 3 ) 0 : i/o port 1 : s rdy2 signal pin 0 : i/o port 1 : s out2 , s clk2 signal pins 7 p5 1 /s out2 p-channel output disable bit 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) serial i/o 3 control register b7 b6 b5 b4 b3 b2 b1 b0 b function r w 0 1 2 3 4 5 6 0 0 0 0 0 0 0 serial i/o 3 control register (sio3con) [address:1e 16 ] name internal synchronous clock selection bits synchronous clock selection bit 000 : f(x in )/8 or f(x cin )/8 001 : f(x in )/16 or f(x cin )/16 010 : f(x in )/32 or f(x cin )/32 011 : f(x in )/64 or f(x cin )/64 110 : f(x in )/128 or f(x cin )/128 111 : f(x in )/256 or f(x cin )/256 0 : external clock 1 : internal clock b2 b1b0 serial i/o 3 port selection bit (p5 5 ,p5 6 ) transfer direction selection bit 0 : lsb first 1 : msb first s rdy3 output selection bit (p5 7 ) 0 : i/o port 1 : s rdy3 signal pin 0 : i/o port 1 : s out3 , s clk3 signal pins 7 0 p5 5 /s out3 p-channel output disable bit 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) at reset 0
183 mitsubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.10 structure of timer 34 mode register fig. 3.3.9 structure of timer 12 mode register timer 12 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 12 mode register (t12m) [address:28 16 ] name timer 1 count stop bit timer 2 count stop bit timer 1 count source selection bit timer 2 count source selection bits timer 1 output selection bit (p4 6 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : f(x cin ) 00 : timer 1 underflow 01 : f(x cin ) 10 : external count input cntr 0 11 : not available 0 : i/o port 1 : timer 1 output b5 b4 nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " 5 5 timer 34 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 34 mode register (t34m) [address:29 16 ] name timer 3 count stop bit timer 4 count stop bit timer 3 count source selection bit timer 4 count source selection bits timer 3 output selection bit (p4 7 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : timer 2 underflow 00 : f(x in )/16 or f(x cin )/16 01 : timer 3 underflow 10 : external count input cntr 1 11 : not available 0 : i/o port 1 : timer 3 output b5 b4 nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0. " 5 5
184 3. appendix mitsubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.11 structure of timer 56 mode register timer 56 mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer 56 mode register (t56m) [address:2a 16 ] name timer 5 count stop bit timer 6 count stop bit timer 5 count source selection bit timer 6 count source selection bits timer 6 (pwm) output selection bit (p6 1 ) 0 : operating 1 : stopped 0 : operating 1 : stopped 0 : f(x in )/16 or f(x cin )/16 1 : timer 4 underflow 00 : f(x in )/16 or f(x cin )/16 01 : timer 5 underflow 10 : timer 4 underflow 11 : not available 0 : i/o port 1 : timer 6 output b5 b4 fix this bit to "0." timer 6 operation mode selection bit 0 : timer mode 1 : pwm mode 0
185 mitsubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.12 structure of ad/da control register ad/da control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name analog input pin selection bits ad/da control register (adcon) [address:2c 16 ] 0 0 0 0 : p7 0 /an 0 0 0 0 1 : p7 1 /an 1 0 0 1 0 : p7 2 /an 2 0 0 1 1 : p7 3 /an 3 0 1 0 0 : p7 4 /an 4 0 1 0 1 : p7 5 /an 5 0 1 1 0 : p7 6 /an 6 0 1 1 1 : p7 7 /an 7 1 0 0 0 : p5 0 /s in2 /an 8 1 0 0 1 : p5 1 /s out2 /an 9 1 0 1 0 : p5 2 /s clk2 /an 10 1 0 1 1 : p5 3 /s rdy2 /an 11 1 1 0 0 : p5 4 /s in3 /an 12 1 1 0 1 : p5 5 /s out3 /an 13 1 1 1 0 : p5 6 /s clk3 /an 14 1 1 1 1 : p5 7 /s rdy3 /an 15 b3 b2 b1 b0 1 0 : conversion in progress 1 : conversion completed a-d conversion completion bit 4 1 0 2 3 0 0 0 0 0 5 5 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 5 0 0 : disable 1 : enable d-a output enable bit 6 0 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 7
186 3. appendix mitsubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.14 structure of interrupt interval determination control register fig. 3.3.13 structure of interrupt interval determination register interrupt interval determination register b7 b6 b5 b4 b3 b2 b1 b0 function at reset rw interrupt interval determination register (iid) [address:30 16 ] this register stores the values obtaind by counting the following interval with a counter sampling clock. falling edge interval rising edge interval both-sided edge interval (selected by the interrupt edge selection register) this register is read-only. l l l note : when the noise filter sampling clock selection bits (bits 2 and 3) of the interrupt interval determination control register (iidcon) (address: 31 16 ) is set to 00 (when no noise filter is used), the both-sided edge detection function is not available. 0 1 2 3 4 5 6 7 b ? ? ? ? ? ? ? ? 5 5 5 5 5 5 5 5 interrupt interval determination control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 0 0 0 0 0 interrupt interval determination control register (iidcon) [address:31 16 ] name interrupt interval determination circuit operating selection bit counter sampling clock selection bit noise filter sampling clock selection bits (int 2 ) one-sided/both-sided edge detection selection bit 0 : stopped 1 : operating 0 : f(x in )/256 1 : f(x in )/512 00 : filter stop 01 : f(x in )/64 10 : f(x in )/128 11 : f(x in )/256 0 : one-sided edge detection 1 : both-sided edge detection (note) 6 5 7 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." 0 0 0 5 5 5 note : when the noise filter sampling clock selection bits (bits 2 and 3) of the interrupt interval determination control register (iidcon) (address: 31 16 ) is set to 00 (when no noise filter is used), the both-sided edge detection function is not available.
187 mits ubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.16 structure of port p2 digit/port switch register fig. 3.3.15 structure of port p0 segment/digit switch register port p0 segment/digit switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p0 segment/digit switch register 0 0 0 0 0 0 0 0 port p0 segment/digit switch register (p0sdr) [address:32 16 ] 0 : dig 0 1 : seg 32 0 : dig 1 1 : seg 33 0 : dig 2 1 : seg 34 0 : dig 3 1 : seg 35 0 : dig 4 1 : seg 36 0 : dig 5 1 : seg 37 0 : dig 6 1 : seg 38 0 : dig 7 1 : seg 39 port p2 digit/port switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name port p2 digit/port switch register (p2dpr) [address:33 16 ] 0 1 2 3 port p2 digit/port switch register 0 0 0 0 0 : port p2 0 output-only 1 : dig 16 0 : port p2 1 output-only 1 : dig 17 0 : port p2 2 output-only 1 : dig 18 0 : port p2 3 output-only 1 : dig 19 4 5 0 0 5 5 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." 6 7 0 0 5 5
188 3. appendix mits ubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.18 structure of port pa segment/port switch register fig. 3.3.17 structure of port p8 segment/port switch register port pa segment/port switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pa segment/port switch register 0 0 0 0 0 0 0 0 port pa segment/port switch register (paspr) [address:35 16 ] 0 : port pa 0 for i/o 1 : seg 0 0 : port pa 1 for i/o 1 : seg 1 0 : port pa 2 for i/o 1 : seg 2 0 : port pa 3 for i/o 1 : seg 3 0 : port pa 4 for i/o 1 : seg 4 0 : port pa 5 for i/o 1 : seg 5 0 : port pa 6 for i/o 1 : seg 6 0 : port pa 7 for i/o 1 : seg 7 port p8 segment/port switch register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p8 segment/port switch register 0 0 0 0 0 0 0 0 port p8 segment/port switch register (p8spr) [address:34 16 ] 0 : port p8 0 for i/o 1 : seg 8 0 : port p8 1 for i/o 1 : seg 9 0 : port p8 2 for i/o 1 : seg 10 0 : port p8 3 for i/o 1 : seg 11 0 : port p8 4 for i/o 1 : seg 12 0 : port p8 5 for i/o 1 : seg 13 0 : port p8 6 for i/o 1 : seg 14 0 : port p8 7 for i/o 1 : seg 15
189 mits ubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.19 structure of fldc mode register 1 fldc mode register 1 b7 b6 b5 b4 b3 b2 b1 b function at reset rw 0 0 fldc mode register 1 (fldm1) [address:36 16 ] name tscan control bits 0 0 : fld digit interrupt (at rising edge of each digit) 0 1 : 1 5 tdisp 1 0 : 2 5 tdisp 1 1 : 3 5 tdisp (at falling edge of the last digit) 6 0 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 5 toff control bit (setting of digit/segment off time) 0 0 0 0 : 1/16 5 tdisp 0 0 0 1 : 2/16 5 tdisp 0 0 1 0 : 3/16 5 tdisp 0 0 1 1 : 4/16 5 tdisp 0 1 0 0 : 5/16 5 tdisp 0 1 0 1 : 6/16 5 tdisp 0 1 1 0 : 7/16 5 tdisp 0 1 1 1 : 8/16 5 tdisp 1 0 0 0 : 9/16 5 tdisp 1 0 0 1 : 10/16 5 tdisp 1 0 1 0 : 11/16 5 tdisp 1 0 1 1 : 12/16 5 tdisp 1 1 0 0 : 13/16 5 tdisp 1 1 0 1 : 14/16 5 tdisp 1 1 1 0 : 15/16 5 tdisp 1 1 1 1 : 16/16 5 tdisp b5 b4 b3 b2 3 2 4 5 0 0 0 0 1 0 b1b0 7 0 high-breakdown-voltage drivability selection bit 0 : strong drivability 1 : weak drivability b0 fld blanking interrupt
190 3. appendix mits ubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.20 structure of fldc mode register 2 fldc mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 0 0 fldc mode register 2 (fldm2) [address:37 16 ] name 2 4 0 3 tdisp control bits (digit time setting) (at 8 mhz oscillation frequency) 0 0 0 0 : 128 m s 0 0 0 1 : 256 m s 0 0 1 0 : 384 m s 0 0 1 1 : 512 m s 0 1 0 0 : 640 m s 0 1 0 1 : 768 m s 0 1 1 0 : 896 m s 0 1 1 1 : 1024 m s 1 0 0 0 : 1152 m s 1 0 0 1 : 1280 m s 1 0 1 0 not available 1 1 1 1 b5 b4 b3 b2 automatic display control bit (p0,p1,p2 0 Cp2 3 ,p3,p8,p9,pa) 0 : display stopped 1 : display in progress (display starts by writing 1 to this bit which is set to 0.) display start bit 0 : ordinary mode 1 : automatic display mode 5 .... 0 0 0 6 0 p1 0 segment/digit switch bit 0 : digit (dig 8 ) 1 : segment (seg 40 ) 7 0 p1 1 segment/digit switch bit 0 : digit (dig 9 ) 1 : segment (seg 41 )
191 mits ubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.21 structure of fld data pointer fig. 3.3.22 structure of fld data pointer reload register fld data pointer reload register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 fld data pointer reload register (flddp) [address:38 16 ] indicate the first digit address of the high-order segment. ? ? ? ? ? nothing is allocated for this bit. this is a write disabled bit. ? 7 5 5 5 5 5 5 5 5 5 ? 5 6 ? fld data pointer b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 fld data pointer (flddp) [address:38 16 ] indicate the address of data which is transfered to the segment of the fld automatic display ram. ? ? ? ? ? nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." 0 7 5 5 ? 5 5 5 5 5 5 6 ? 5
192 3. appendix mits ubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.23 structure of zero cross detection control register fig. 3.3.24 structure of interrupt edge selection register interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt edge selecton reigster (intedge) [address:3a 16 ] name int 0 interrupt edge selection bit int 1 /zcr interrupt edge selection bit int 2 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active int 3 interrupt edge selection bit 4 0 0 : falling edge active 1 : rising edge active int 4 interrupt edge selection bit 5 6 7 0 0 0 int 4 /a-d conversion interrupt switch bit cntr 0 pin active edge switch bit 0 : int 4 interrupt 1 : a-d conversion interrupt 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active cntr 1 pin active edge switch bit zero cross detection control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 7 0 0 0 0 0 0 0 zero cross detection control register (zcrcon) [address:39 16 ] name zero cross detection on/off selection bit one-sided/both-sided edge detection selection bit zero cross detection circuit input bit (read-only) 0 : without passing through zero cross detection comparator 1 : passing through zero cross detection comparator 00 : note use noise filter 01 : f(x in )/64 or f(x cin )/64 10 : f(x in )/128 or f(x cin )/128 11 : f(x in )/256 or f(x cin )/256 0 : less than 0 v 1 : 0 v or more b3 b2 5 nothing is allocated for this bit. it is a write disabled bit. when this bit is read out, the value is "0." 5 noise filter sampling clock selection bits (int 1 ) 0 : one-sided edge detection 1 : both-sided edges detection ( note ) 6 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are "0." 5 5 when the noise filter sampling clock selection bits (bits 2 and 3) of the zero cross detection control register (zcrcon) (address: 39 16 ) is set to 00 (when no noise filter is used), the both-sided edge detection function is not available. note :
193 mits ubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.25 structure of cpu mode register fig. 3.3.26 structure of interrupt request register 1 cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 1 cpu mode register (cpum) [address:3b 16 ] name processor mode bits stack page selection bit 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : 0 : 0 page 1 : 1 page 5 6 7 0 0 1 main clock (x in -x out ) stop bit main clock division ratio selection bit internal system clock selection bit 0 : operating 1 : stopped 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) 0 : x in -x out selected (middle/high-speed mode) 1 : x cin -x cout selected (low-speed mode) b1b0 0 : i/o port function 1 : x cin Cx cout oscillating function 4 port xc switch bit x cout drivability selection bit 0 : low 1 : high interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 1 (ireq1) [address:3c 16 ] name int 0 interrupt request bit int 1 /zcr interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request serial i/o 1 interrupt request bit serial i/o automatic transfer interrupt request bit l l [ [ [ [ 4 5 6 7 0 0 0 0 serial i/o 2 interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request serial i/o 3 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ "0" is set by software, but not "1." int 2 interrupt request bit remote control/counter overflow interrupt request bit l l
194 3. appendix mits ubishi microcomputer 3819 group 3.3 control registers 3819 group users manual fig. 3.3.28 structure of interrupt control register 1 fig. 3.3.27 structure of interrupt request register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 2 (ireq2) [address:3d 16 ] name timer 3 interrupt request bit timer 4 interrupt request bit timer 5 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request timer 6 interrupt request bit [ [ [ [ 5 6 7 0 0 0 : no interrupt request 1 : interrupt request nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is "0." fld blanking interrupt request bit fld digit interrupt request bit l l int 4 interrupt request bit a-d conversion interrupt request bit l l 0 : no interrupt request 1 : interrupt request [ [ [ "0" is set by software, but not "1." 4 0 0 : no interrupt request 1 : interrupt request int 3 interrupt request bit [ 0 [ interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address:3e 16 ] name int 0 interrupt enable bit int 1 /zcr interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 serial i/o 2 interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled serial i/o 3 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o 1 interrupt enable bit serial i/o automatic transfer interrupt enable bit l l int 2 interrupt enable bit remote control/counter overflow interrupt enable bit l l
195 mits ubishi microcomputer 3819 group 3.3 control registers 3. appendix 3819 group users manual fig. 3.3.29 structure of interrupt control register 2 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control reigster 2 (icon2) [address:3f 16 ] name timer 3 interrupt enable bit timer 4 interrupt enable bit timer 5 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer 6 interrupt enable bit 5 6 7 0 0 0 : interrupt disabled 1 : interrupt enabled fix this bit to "0." fld blanking interrupt enable bit fld digit interrupt enable bit l l int 4 interrupt enable bit a-d conversion interrupt enable bit l l 0 : interrupt disabled 1 : interrupt enabled 4 0 0 : interrupt disabled 1 : interrupt enabled int 3 interrupt enable bit 0 0
196 3. appendix mitsubishi microcomputer 3819 group 3.4 mask rom ordering method 3819 group users manual 3.4 mask rom ordering method
197 mitsubishi microcomputer 3819 group 3.4 mask rom ordering method 3. appendix 3819 group users manual
198 3819 group users manual 3. appendix mitsubishi microcomputer 3819 group 3.5 mark specification form 3.5 mark specification form
199 mitsubishi microcomputer 3819 group 3.6 package outline 3. appendix 3819 group users manual 3.6 package outline
200 3. appendix mitsubishi microcomputer 3819 group 3.7 memory map 3819 group users manual 3.7 memory map 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 port p0 (p0) port p1 (p1) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) serial i/o automatic transfer data pointer (siodp) serial i/o1 control register (sio1con) serial i/o automatic transfer control register (sioac) serial i/o1 register (sio1) serial i/o automatic transfer interval register (sioai) 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 timer 1 (t1) timer 2 (t2) timer 3 (t3) timer 4 (t4) timer 5 (t5) timer 6 (t6) serial i/o3 register (sio3) timer 6 pwm register (t6pwm) timer 12 mode register (t12m) timer 34 mode register (t34m) interrupt interval determination register (iid) interrupt interval determination control register (iidcon) port p0 segment/digit switch register (p0sdr) port p2 digit/port switch register (p2dpr) port p8 segment/port switch register (p8spr) fldc mode register 2 (fldm2) zero cross detection control register (zcrcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) 003f 16 interrupt control register 2 (icon2) port pa (pa) port pa direction register (pad) port pb (pb) port pb direction register (pbd) serial i/o2 control register (sio2con) serial i/o3 control register (sio3con) serial i/o2 register (sio2) timer 56 mode register (t56m) d-a conversion register (da) ad-da control register (adcon) a-d conversion register (ad) port pa segment/port switch register (paspr) fldc mode register 1 (fldm1) fld data pointer (flddp) port p9 (p9)
201 3. appendix mitsubishi microcomputer 3819 group 3.8 pin configuration 3819 group users manual 3.8 pin configuration p8 7 /seg 15 81 m38197ma-xxxfp p8 6 /seg 14 82 p8 5 /seg 13 83 p8 4 /seg 12 84 p8 3 /seg 11 85 p8 2 /seg 10 86 p8 1 /seg 9 87 p8 0 /seg 8 88 pa 7 /seg 7 89 pa 6 /seg 6 90 v cc 91 pa 5 /seg 5 92 pa 4 /seg 4 93 pa 3 /seg 3 94 pa 2 /seg 2 95 pa 1 /seg 1 96 pa 0 /seg 0 97 v ee 98 av ss 99 v ref 100 p1 6 /dig 14 50 p1 7 /dig 15 49 p2 0 /dig 16 48 p2 1 /dig 17 47 p2 2 /dig 18 46 p2 3 /dig 19 45 p2 4 44 p2 5 43 p2 6 42 p2 7 41 v ss 40 x out 39 x in 38 pb 0 /x cout 37 pb 1 /x cin 36 reset 35 p4 0 /int 0 34 p4 1 33 p4 2 /int 2 32 p4 3 /int 3 31 p7 7 /an 7 1 p7 6 /an 6 2 p7 5 /an 5 3 p7 4 /an 4 4 p7 3 /an 3 5 p7 2 /an 2 6 p7 1 /an 1 7 p7 0 /an 0 8 pb 3 9 pb 2 /da 10 p5 7 /s rdy3 /an 15 11 p5 6 /s clk3 /an 14 12 p5 5 /s out3 /an 13 13 p5 4 /s in3 /an 12 14 p5 3 /s rdy2 /an 11 15 p5 2 /s clk2 /an 10 16 p5 1 /s out2 /an 9 17 p5 0 /s in2 /an 8 18 p6 7 /s rdy1 /cs/s clk12 19 p6 6 /s clk11 20 p6 5 /s out1 21 p6 4 /s in1 22 p6 3 /cntr 1 23 p6 2 /cntr 0 24 p6 1 /pwm 25 p6 0 26 p4 7 /t3 out 27 p4 6 /t1 out 28 p4 5 /int 1 /zcr 29 p4 4 /int 4 30 p9 0 /seg 16 80 p9 1 /seg 17 79 p9 2 /seg 18 78 p9 3 /seg 19 77 p9 4 /seg 20 76 p9 5 /seg 21 75 p9 6 /seg 22 74 p9 7 /seg 23 73 p3 0 /seg 24 72 p3 1 /seg 25 71 p3 2 /seg 26 70 p3 3 /seg 27 69 p3 4 /seg 28 68 p3 5 /seg 29 67 p3 6 /seg 30 66 p3 7 /seg 31 65 p0 0 /seg 32 /dig 0 64 p0 1 /seg 33 /dig 1 63 p0 2 /seg 34 /dig 2 62 p0 3 /seg 35 /dig 3 61 p0 4 /seg 36 /dig 4 60 p0 5 /seg 37 /dig 5 59 p0 6 /seg 38 /dig 6 58 p0 7 /seg 39 /dig 7 57 p1 0 /seg 40 /dig 8 56 p1 1 /seg 41 /dig 9 55 p1 2 /dig 10 54 p1 3 /dig 11 53 p1 4 /dig 12 52 p1 5 /dig 13 51 package type : 100p6s-a 100-pin plastic-molded qfp
mitsubishi semiconductors users manual 3819 group mar. first edition 1995 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1998 mitsubishi electric corporation
users manual 3819 group h-ed346-a ki-9503 printed in japan (rod) ? 1995 mitsubishi electric corporation. new publication, effective mar. 1995. specifications subject to change without notice.
rev. rev. no. date 1.0 first edition 980216 revision description list 3819 group users manual (1/1) revision description

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