ds 206 (v1.2) july 19, 2002 www.xilinx.com 1 data sheet, v3.0.100 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to change without notice. notice of disclaimer: xilinx is providing this design, code, or information "as is." by providing the design, code, or information as one possible imp lementation of this fea- ture, application, or standard, xilinx makes no representation that this implementation is free from any claims of infringement. you are responsibl e for obtaining any rights you may require for your implementation. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran- ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a p articular purpose. introduction with the xilinx logicore pci interface, a designer can build a customized, fully pci 2.3-compliant core with the highest possible sustained performance, 528 mbytes/sec. features ? fully pci 2.3-compliant core, 64/32-bit, 66/33 mhz interface customizable, programmable, single-chip solution predefined implementation for predictable timing incorporates xilinx smart-ip technology 3.3 v operation at 0-66 mhz 5.0 v operation at 0-33 mhz fully verified design tested with xilinx proprietary testbench and hardware available for configuration and download on the web: - web-based configuration and download tool - web-based user constraint file generator tool cardbus compliant supported initiator functions: - configuration read, configuration write - memory read, memory write, mrm, mrl - interrupt acknowledge, special cycles - i/o read, i/o write supported target functions: - type 0 configuration space header - up to 3 base address registers (mem or i/o with adjustable block size from 16 bytes to 2 gbytes) - medium decode speed - parity generation, parity error detection - configuration read, configuration write - memory read, memory write, mrm, mrl - interrupt acknowledge - i/o read, i/o write - target abort, target retry, target disconnect 0 logicore pci32 interface v3.0 ds 206 (v1.2) july 19, 2002 00 data sheet, v3.0.100 logicore facts pci64 resource utilization 1 slice four input luts 724 slice flip flops 732 iob flip flops 176 iobs 89 tbufs 352 gclks 1 2 pci32 resource utilization 1 slice four input luts 553 slice flip flops 566 iob flip flops 97 iobs 50 tbufs 288 gclks 1 2 provided with core documentation pci design guide pci implementation guide design file formats verilog/vhdl simulation model ngo netlist constraint files user constraint files (ucf) guide files (ncd) example design verilog/vhdl example design design tool requirements xilinx tools v4.2i, service pack 3 tested entry and verification tools 3 synplicity synplify synopsys fpga express exemplar leonardo spectrum xilinx xst 4 cadence verilog xl model technology modelsim 1. the resource utilization depends on configuration of the interface and the user design. unused resources are trimmed by the xilinx technology mapper. the utili- zation figures reported in this table are representative of a maximum configuration. 2. designs running at 66 mhz in devices other than virtex-ii require one gclkiob and two gclks. 3. see the implementation guide or product release notes for current supported ver- sions. 4. xst is command line option only. see implementation guide for details.
logicore pci32 interface v3.0 2 www.xilinx.com ds 206 (v1.2) july 19, 2002 1-800-255-7778 data sheet, v3.0.100 applications embedded applications in networking, industrial, and telecommunication systems pci add-in boards such as frame buffers, network adapters, and data acquisition boards hot swap compactpci boards cardbus compliant any applications that need a pci interface general description the logicore pci interface is a preimplemented and fully tested module for xilinx fpgas. the pinout for each device and the relative placement of the internal logic are pre- defined. critical paths are controlled by constraint and guide files to ensure predictable timing. this significantly reduces the engineering time required to implement the pci portion of your design. resources can instead be focused on your unique user application logic in the fpga and on the sys- tem-level design. as a result, logicore pci products min- imize your product development time. the core meets the setup, hold, and clock-to-timing require- ments as specified in the pci-x specification. the interface is verified through extensive simulation. other features that enable efficient implementation of a pci system include: block selectram? memory. blocks of on-chip ultra-fast ram with synchronous write and dual-port ram capabilities. used in pci designs to implement fifos. selectram memory. distributed on-chip ultra-fast ram with synchronous write option and dual-port ram capabilities. used in pci designs to implement fifos. internal three-state bus capability for data multiplexing. the interface is carefully optimized for best possible perfor- mance and utilization in xilinx fpga devices. smart-ip technology drawing on the architectural advantages of xilinx fpgas, xilinx smart-ip technology ensures the highest perfor- mance, predictability, repeatability, and flexibility in pci designs. the smart-ip technology is incorporated in every logicore pci interface. xilinx smart-ip technology leverages the xilinx architectural advantages, such as look-up tables and segmented routing, as well as floorplanning information, such as logic mapping and location constraints. this technology provides the best physical layout, predictability, and performance. in addition, these features allow for significantly reduced compile times over competing architectures. to guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, the pci interface is deliv- ered with smart-ip constraint files that are unique for a device and package combination. these constraint files guide the implementation tools so that the critical paths always are within specification. xilinx provides smart-ip constraint files for many device and package combinations. constraint files for unsupported device and package combinations may be generated using the web-based constraint file generator. functional description the logicore pci interface is partitioned into five major blocks and a user application as shown in figure 1 . logicore facts (cont) supported devices pci32/66 virtex v200fg256-6c virtex-e v200efg256-6c virtex-e v400efg676-6c 3.3v only 3.3v only 3.3v only pci32/33 virtex v300bg432-5c virtex v1000fg680-5c virtex-e v100ebg352-6c virtex-e v300ebg432-6c virtex-e v1000efg680-6c virtex-ii 2v1000fg456-4c/i/m virtex-ii pro 2vp7ff672-6c spartan-ii 2s30pq208-5c spartan-ii 2s50pq208-5c spartan-ii 2s100pq208-5c spartan-ii 2s150pq208-5c spartan-ii 2s200pq208-5c spartan-iie 2s50epq208-6c spartan-iie 2s100epq208-6c spartan-iie 2s150epq208-6c spartan-iie 2s200epq208-6c spartan-iie 2s300epq208-6c 3.3v, 5.0v 3.3v, 5.0v 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only 3.3v, 5.0v 3.3v, 5.0v 3.3v, 5.0v 3.3v, 5.0v 3.3v, 5.0v 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only xilinx provides technical support for this logicore product when used as described in the design guide and the implementation guide. xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if custom- ized beyond that allowed in the product documentation. note: universal card implementations require two bitstreams. note: virtex-e and spartan-iie recommended for cardbus. note: commercial devices; 0 c < t j <85c. note: for additional part/package combinations, see the ucf generator in the pci lounge. note: 2v1000 is supported over military temp. range. figure 1: logicore pci interface block diagram parity generator/ checker pci configuration space initiator state machine interrupt pin and line register latency timer register vendor id, rev id, other user data target state machine pci i/o interface user application adio[63:0] ad[63:0] pa r gnt- perr- serr- frame- irdy- req- trdy- devsel- stop- base address register 0 base address register 1 command/ status register base address register 2 req64- ack64- par64
logicore pci32 interface v3.0 ds 206 (v1.2) july 19, 2002 www.xilinx.com 3 data sheet, v3.0.100 1-800-255-7778 pci i/o interface block the i/o interface block handles the physical connection to the pci bus including all signaling, input and output syn- chronization, output three-state controls, and all request-grant handshaking for bus mastering. user application the logicore pci interface provides a simple, gen- eral-purpose interface for a wide range of applications. pci configuration space this block provides the first 64 bytes of type 0, version 2.3 configuration space header, as shown in ta b l e 1 , to sup- port software-driven ?plug-and-play? initialization and con- figuration. this includes information for command, status, and three base address registers (bars). the capability for extending configuration space has been built into the user application interface. this capability, including the ability to implement a capabilities pointer in configuration space, allows the user to implement functions such as power management and message signaled inter- rupts in the user application. parity generator/checker this block generates and checks even parity across the ad bus, the cbe# lines, and the parity signals. it also reports data parity errors via perr# and address parity errors via serr#. initiator state machine this block controls the pci interface initiator functions. the states implemented are a subset of those defined in appen- dix b of the pci local bus specification . the initiator control logic uses one-hot encoding for maximum performance. target state machine this block controls the pci interface target functions. the states implemented are a subset of those defined in appen- dix b of the pci local bus specification . the target control logic uses one-hot encoding for maximum performance. ta b le 1 : pci configuration space header interface configuration the logicore pci interface can easily be configured to fit unique system requirements by using the xilinx web-based configuration and download tool or by changing the hdl configuration file. the following customization options, among many others, are supported by the interface and are described in the product design guide. base address registers (number, size, and type) configuration space header rom burst transfer the pci bus derives its performance from its ability to sup- port burst transfers. the performance of any pci applica- tion depends largely on the size of the burst transfer. buffers to support pci burst transfer can efficiently be implemented using on-chip ram resources. supported pci commands table 2 illustrates the pci bus commands supported by the logicore pci interface. bandwidth the logicore pci interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. this interface supports a sustained bandwidth of up to 528 mbytes/sec. the design can be configured to take advantage of the ability of the logicore pci interface to do very long bursts. the flexible user application interface, combined with sup- port for many different pci features, gives users a solution that lends itself to use in many high-performance applica- tions. the user is not locked into one dma engine; hence, an optimized design that fits a specific application can be designed. 31 16 15 0 device id vendor id 00h status command 04h class code rev id 08h bist header type latency tim- er cache line size 0ch base address register 0 (bar0) 10h base address register 1 (bar1) 14h base address register 2 (bar2) 18h base address register 3 (bar3) 1ch base address register 4 (bar5) 20h base address register 5 (bar5) 24h cardbus cis pointer 28h subsystem id subsystem vendor id 2ch expansion rom base address 30h reserved capptr 34h reserved 38h max lat min gnt int pin int line 3ch reserved 40h-ffh note: shaded areas are not implemented and return zero.
logicore pci32 interface v3.0 4 www.xilinx.com ds 206 (v1.2) july 19, 2002 1-800-255-7778 data sheet, v3.0.100 recommended design experience the logicore pci interface is preimplemented, allowing engineering focus on the unique user application functions of a pci design. regardless, pci is a high-performance design that is challenging to implement in any technology. therefore, previous experience with building high-perfor- mance, pipelined fpga designs using xilinx implementa- tion software, constraint files, and guide files is recommended. the challenge to implement a complete pci design including user application functions varies depend- ing on configuration and functionality of your application. contact your local xilinx representative for a closer review and estimation for your specific requirements. timing specifications the maximum speed at which your user design is capable of running can be affected by the size and quality of the design. the following tables show the key timing parame- ters for the logicore pci interface. table 3 lists the timing parameters in the 66mhz imple- mentations and table 4 lists timing parameters in the 33mhz implementations. ta b le 2 : pci bus commands table 3: timing parameters, 66mhz implementations table 4: timing parameters, 33mhz implementations cbe [3:0] command pci initiator pci ta r ge t 0000 interrupt acknowledge yes yes 0001 special cycle yes ignore 0010 i/o read yes yes 0011 i/o write yes yes 0100 reserved ignore ignore 0101 reserved ignore ignore 0110 memory read yes yes 0111 memory write yes yes 1000 reserved ignore ignore 1001 reserved ignore ignore 1010 configuration read yes yes 1011 configuration write yes yes 1100 memory read multiple yes yes 1101 dual address cycle no ignore 1110 memory read line yes yes 1111 memory write invalidate no yes symbol parameter min max t cyc clk cycle time 15 1 30 t high clk high time 6 - t low clk low time 6 - t val clk to signal valid delay (bussed signals) 2 2 6 2 t val clk to signal valid delay (point to point signals) 2 2 6 2 t on floattoactivedelay 2 2 - t off active to float delay - 14 1 t su input setup time to clk (bussed signals) 3 2,3 - t su input setup time to clk (point to point signals) 5 2,3 - t h input hold time from clk 0 2,3 - t rstoff reset active to output float - 40 notes: 1. controlled by timespec constraints, included in product. 2. controlled by selectio configured for pci66_3. 3. controlled by guide file, included in product. symbol parameter min max t cyc clk cycle time 30 1 - t high clk high time 11 - t low clk low time 11 - t val clk to signal valid delay (bussed signals) 2 2 11 2 t val clk to signal valid delay (point to point signals) 2 2 11 2 t on floattoactivedelay 2 2 - t off active to float delay - 28 1 t su input setup time to clk (bussed signals) 7 2 - t su input setup time to clk (point to point signals) 10 2 - t h input hold time from clk 0 2 - t rstoff reset active to output float - 40 notes: 1. controlled by timespec constraints, included in product. 2. controlled by selectio configured for pci33_3 or pci33_5.
logicore pci32 interface v3.0 ds 206 (v1.2) july 19, 2002 www.xilinx.com 5 data sheet, v3.0.100 1-800-255-7778 ordering information this core may be downloaded from the xilinx ip center for use with the xilinx core generator system v4.1 and later. the xilinx core generator system tool is bundled with all alliance and foundation series software packages, at no additional charge. part numbers do-di-pci32-ip -access to the v3.0 pci32 33 mhz spartan and 66 mhz virtex families dx-di-pci32-sl -upgrade from pci32 33 mhz spartan only to v3.0 pci32 33 mhz spartan and 66 mhz virtex families DO-DI-PCI32-SP -access to the v3.0 pci32 spartan family to order the xilinx pci core, please visit the xilinx silicon xpresso cafe or contact your local xilinx sales representa- tive . revision history the following table shows the revision history for this document. date version revision 06/27/02 1.0 new template
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