? semiconductor components industries, llc, 2003 september, 2003 ? rev. 1 1 publication order number: emc2dxv5t1/d emc2dxv5t1, EMC5DXV5T1 preferred devices dual common base-collector bias resistor transistors npn and pnp silicon surface mount transistors with monolithic bias resistor network the brt (bias resistor transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base?emitter resistor. these digital transistors are designed to replace a single device and its external resistor bias network. the brt eliminates these individual components by integrating them into a single device. in the EMC5DXV5T1 series, two complementary brt devices are housed in the sot?553 package which is ideal for low power surface mount applications where board space is at a premium. ? simplifies circuit design ? reduces board space ? reduces component count ? available in 8 mm, 7 inch tape and reel ? lead free maximum ratings (t a = 25 c unless otherwise noted, common for q 1 and q 2 , ? minus sign for q 1 (pnp) omitted) rating symbol value unit collector-base voltage v cbo 50 vdc collector-emitter voltage v ceo 50 vdc collector current i c 100 madc thermal characteristics characteristic (one junction heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 357 (note 1) 2.9 (note 1) mw mw/ c thermal resistance ? junction-to-ambient r ja 350 (note 1) c/w characteristic (both junctions heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 500 (note 1) 4.0 (note 1) mw mw/ c thermal resistance ? junction-to-ambient r ja 250 (note 1) c/w junction and storage temperature t j , t stg ?55 to +150 c 1. fr?4 @ minimum pad 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. marking diagram preferred devices are recommended choices for future use and best overall value. 45 q1 q2 r1 r1 r2 r2 31 2 http://onsemi.com sot?553 case 463b xx d 1 5 1 5 xx = specific device code d = date code device package shipping 2 ordering information emc2dxv5t1 sot?553 4 mm pitch 4000/tape & reel emc2dxv5t5 sot?553 2 mm pitch 8000/tape & reel EMC5DXV5T1 sot?553 4 mm pitch 4000/tape & reel emc5dxv5t5 sot?553 2 mm pitch 8000/tape & reel
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 2 device marking and resistor values transistor 1 ? pnp transistor 2 ? npn device marking r1 (k) r2 (k) r1 (k) r2 (k) emc2dxv5t1 EMC5DXV5T1 uc u5 22 4.7 22 10 22 47 22 47 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit q1 transistor: pnp off characteristics collector-base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector-emitter cutoff current (v cb = 50 v, i b = 0) i ceo ? ? 500 nadc emitter-base cutoff current emc2dxv5t1 (v eb = 6.0, i c = 5.0 ma) EMC5DXV5T1 i ebo ? ? ? ? 0.2 1.0 madc on characteristics collector-base breakdown voltage (i c = 10 m a, i e = 0) v (br)cbo 50 ? ? vdc collector-emitter breakdown voltage (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc dc current gain emc2dxv5t1 (v ce = 10 v, i c = 5.0 ma) EMC5DXV5T1 h fe 60 20 100 35 ? ? collector?emitter saturation voltage (i c = 10 ma, i b = 0.3 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor emc2dxv5t1 EMC5DXV5T1 r1 15.4 3.3 22 4.7 28.6 6.1 k resistor ratio emc2dxv5t1 EMC5DXV5T1 r1/r2 0.8 0.38 1.0 0.47 1.2 0.56 q2 transistor: npn off characteristics characteristic symbol min typ max unit collector-base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector-emitter cutoff current (v cb = 50 v, i b = 0) i ceo ? ? 500 nadc emitter-base cutoff current emc2dxv5t1 (v eb = 6.0, i c = 5.0 ma) EMC5DXV5T1 i ebo ? ? ? ? 0.2 0.1 madc on characteristics collector-base breakdown voltage (i c = 10 m a, i e = 0) v (br)cbo 50 ? ? vdc collector-emitter breakdown voltage (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc dc current gain emc2dxv5t1 (v ce = 10 v, i c = 5.0 ma) EMC5DXV5T1 h fe 60 80 100 140 ? ? collector?emitter saturation voltage (i c = 10 ma, i b = 0.3 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor emc2dxv5t1 EMC5DXV5T1 r1 15.4 33 22 47 28.6 61 k resistor ratio emc2dxv5t1 EMC5DXV5T1 r1/r2 0.8 0.8 1.0 1.0 1.2 1.2
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 3 figure 1. derating curve 250 200 150 100 50 0 -50 0 50 100 150 t a , ambient temperature ( c) p d , power dissipation (milliwatts) r ja = 833 c/w
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 4 typical electrical characteristics e emc2dxv5t1 pnp transistor v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain figure 2. v ce(sat) versus i c figure 3. dc current gain 1000 10 i c , collector current (ma) 100 10 1 100 figure 4. output capacitance i c , collector current (ma) 0 10 20 30 v o = 0.2 v t a =-25 c 75 c 100 10 1 0.1 40 50 figure 5. output current versus input voltage 100 10 1 0.1 0.01 0.001 0 1 2 3 4 v in , input voltage (volts) 5 6 7 8 9 10 figure 6. input voltage versus output current 0.01 v ce(sat) , maximum collector voltage (volts) 0.1 1 10 40 i c , collector current (ma) 0 20 50 75 c 25 c t a =-25 c 50 010 203040 4 3 2 1 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) 25 c i c /i b = 10 25 c -25 c v ce = 10 v t a =75 c f = 1 mhz l e = 0 ma t a = 25 c 75 c 25 c t a =-25 c v o = 5 v
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 5 typical electrical characteristics e emc2dxv5t1 npn transistor v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain figure 7. v ce(sat) versus i c 10 02030 i c , collector current (ma) 10 1 0.1 t a =-25 c 75 c 25 c 40 50 figure 8. dc current gain figure 9. output capacitance 1 0.1 0.01 0.001 020 40 50 i c , collector current (ma) v ce(sat) , maximum collector voltage (volts) 1000 100 10 1 10 100 i c , collector current (ma) t a =75 c 25 c -25 c t a =-25 c 25 c figure 10. output current versus input voltage 75 c 25 c t a =-25 c 100 10 1 0.1 0.01 0.001 01 234 v in , input voltage (volts) 56 78 910 figure 11. input voltage versus output current 50 010203040 4 3 1 2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) 75 c v ce = 10 v f = 1 mhz i e = 0 ma t a = 25 c v o = 5 v v o = 0.2 v i c /i b = 10
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 6 typical electrical characteristics e EMC5DXV5T1 pnp transistor 25 c i c , collector current (ma) h fe , dc current gain figure 12. v ce(sat) versus i c figure 13. dc current gain figure 14. output capacitance figure 15. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c -25 c 100 1 1 1000 75 c 25 c 100 0 v in , input voltage (volts) 10 1 0.1 0.01 2468 12 t a =-25 c v ce(sat) , maximum collector voltage (volts) t a =75 c -25 c 0.01 0.1 1 40 i c , collector current (ma) 0 20 50 010203040 12 6 4 2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) i c /i b = 10 v ce = 10 v f = 1 mhz i e = 0 ma t a = 25 c v o = 5 v 30 10 60 100 10 10 8 15 25 35 45 5 series 1 10
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 7 typical electrical characteristics e EMC5DXV5T1 npn transistor v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain figure 16. v ce(sat) versus i c 0246810 100 10 1 0.1 0.01 0.001 v in , input voltage (volts) t a =-25 c 75 c 25 c figure 17. dc current gain figure 18. output capacitance 100 10 1 0.1 010 203040 50 i c , collector current (ma) figure 19. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c -25 c 100 10 1 100 25 c 75 c 50 010203040 1 0.8 0.6 0.4 0.2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) figure 20. input voltage versus output current 0 20 40 50 10 1 0.1 0.01 i c , collector current (ma) 25 c 75 c v ce(sat) , maximum collector voltage (volts) v ce = 10 v f = 1 mhz i e = 0 ma t a = 25 c v o = 5 v v o = 0.2 v i c /i b = 10 t a =-25 c t a =-25 c
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 8 the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 150 milliwatts. information for using the sot?553 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the to- tal design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the cor- rect pad geometry, the packages will self align when sub- jected to a solder reflow process. sot?553 power dissipation p d = t j(max) ? t a r ja p d = 150 c ? 25 c 833 c/w = 150 milliwatts the power dissipation of the sot?553 is a function of the pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . us- ing the values provided on the data sheet for the sot?553 package, p d can be calculated as follows: the 833 c/w for the sot?553 package assumes the use of the recommended footprint on a glass epoxy printed cir- cuit board to achieve a power dissipation of 150 milliwatts. there are other alternatives to achieving higher power dis- sipation from the sot?553 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dis- sipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. there- fore, the following items should always be observed in or- der to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and solder- ing should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum tem- perature ratings as shown on the data sheet. when using infrared heating with the reflow soldering meth- od, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maxi- mum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied dur- ing cooling. * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device. 1.35 0.0531 0.5 0.0197 mm inches scale 20:1 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118 sot?553
emc2dxv5t1, EMC5DXV5T1 http://onsemi.com 9 package dimensions sot?553 xv5 suffix 5?lead package case 463b?01 issue o g m 0.08 (0.003) x d 5 pl c j ?x? ?y? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. dim a min max min max inches 1.50 1.70 0.059 0.067 millimeters b 1.10 1.30 0.043 0.051 c 0.50 0.60 0.020 0.024 d 0.17 0.27 0.007 0.011 g 0.50 bsc 0.020 bsc j 0.08 0.18 0.003 0.007 k s a b y 12 3 4 5 s k 0.004 0.012 0.059 0.067 0.10 0.30 1.50 1.70
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