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ai00844 19 a0-a18 ee dq0-dq14 v cc m39832 g ef v ss 15 w erb rp frb dq15aC1 byte figure 1. logic diagram m39832 single chip 8 mbit (1mb x8 or 512kb x16) flash and 256 kbit parallel eeprom memory preliminary data 2.7v to 3.6v supply voltage for program, erase and read oparations flash array C boot block (top or bottom location) C parameter and main blocks C selectable x8/x16 data bus ( byte pin). eeprom array C x8 data bus only. 120ns access time (flash and eeprom array) write, program and erase status bits concurrent mode (read flash while writing to eeprom) 100,000 erase/write cycles 10 years data retention low power consumption C stand-by mode: 100 m a C automatic stand-by mode 64 bytes one time programmable memory (x8 data bus only) standard eprom/otp memory package extended temperature ranges description the m39832 is a memory device combining flash and eeprom into a single chip and using single supply voltage. the memory is mapped in two arrays: 8 mbit of flash memory and 256 kbit of eeprom memory. each space is independant for writing, in concurrent mode the flash memory can be read while the eeprom is being written. an additional 64 bytes of eprom are one time programmable. the m39832 eeprom memory array is organized in byte only (regardless on the byte pin). it may be written by byte or by page of 64 bytes and the integrity of the data can be secured with the help of the software data protection (sdp). tsop48 (ne) 12 x 20 mm february 1999 1/36 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice.
warning: nc = not connected. v ss dq8 dq1 a6 a1 ef a3 a2 ee dq14 a9 a10 dq12 w a15 dq10 dq6 v cc dq9 dq2 dq3 dq11 dq4 rp nc a18 a7 frb nc a17 ai00845 m39832 12 1 13 24 25 36 37 48 a0 a8 dq13 erb dq5 a5 dq0 a4 g a16 byte v ss dq15aC1 dq7 a13 a14 a12 a11 figure 2. tsop pin connections a0-a18 address inputs dq0-dq7 data input/outputs, commands input dq8-dq14 data input/outputs dq15aC1 data input/outputs or address input ee eeprom array enable ef flash array enable g output enable w write enable rp reset/block temporary unprotect er b eeprom ready/busy output fr b flash ready/busy output byte flash array byte/word organization v cc supply voltage v ss ground table 1. signal names description (contd) the m39832 flash memory array can be config- ured as 1mb x8 or 512kb x16 with the byte input pin. the m39832-t and m39832-b feature asymet- rically blocked architecture providing system mem- ory integration. both m39832-b and m39832-t devices have a flash array of 19 blocks, one boot block of 16 kbytes or 8 kwords, two parameter blocks of 8 kbytes or 4 kwords, one main block of 32 kbytes or 16 kwords and fifteen main blocks of 64 kbytes or 32 kwords. the m39832-t has the boot block at the top of the memory address space and the m39832-b locates the boot block starting at the bottom. the memory maps are showed in figures 3a and 3b. each block can be erased separately,any combination of blocks can be speci- fied for multi-block erase or the entire chip may be erased. the erase operations are managed auto- matically. the block erase operation can be sus- pended in order to read from or program to any block not being ersased, and then resumed. block protection provides additional data security. each block can be separately protected or unprotected against program or erase on programming equip- ment. all previously protected blocks can be tem- porarily unprotected in the application. the flash memory array is functionally compatible with the m29w800 single voltage flash memory device. during a program or erase cycle in the flash array or during a write in the eeprom array, status bits available on certain dqn pins provide information on the m39832 internal logic. pin description byte/word organization select ( byte) . the byte input selects the output configuration for the flash array: byte-wide (x8) mode or word-wide (x16) mode. the eeprom array and the 64 bytes otp row are always accessed byte-wide (x8). when byte is high, the word-wide mode is se- lected for the flash array (x16) and the data are read and programmed on dq0-dq15. the flash array is accessed with a0-a18 adrress lines. in this mode, data in the eeprom array (x8) are read and programmed on dq0-dq7 and the array is ac- cessed with a0-a14. the 64 bytes otp are read and programmed on dq0-dq7 and are accessed with a0-a5 and a6 = 0. when byte is low, the byte-wide mode is selected for the flash array (x8) and the data are read and 2/36 m39832
programmed on dq0-dq7. in this mode, dq8- dq14 are at high impedance and dq15aC1 is the lsb address bit, making the flash array to be accessed with aC1-a18 adress lines. in this mode, data in the eeprom array (x8) are read and programmed on dq0-dq7 and the array is ac- cessed with aC1-a13. the 64 bytes otp are read and programmed on dq0-dq7 and are accessed with a-1 - a4 and a6 = 0. address inputs (a0-a18). the address inputs for the memory array are latched during a write opera- tion on the falling edge at chip enable ( ee or ef) or write enable w. in word-wide organisation the address lines are a0-a18, in byte-wide organisa- tion dq15aC1 acts as an additional lsb address line. when a9 is raised to v id , either a read electronic signature manufacturer or device code, block protection status or a write block protection or block unprotection is enabled depending on the combination of levels on a0, a1, a6, a12 and a15. data input/output (dq0-dq7). these in- puts/outputs are used in the byte-wide and word- wide organisations. the input is data to be programmed in the memory array or a command to be written. both are latched on the rising edge of chip enable ( ee or ef) or write enable w. the output is data from the memory array, the elec- tronic signature manufacturer or device codes, the block protection status or the status register data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when chip enable ( ee or ef) and output enable g are active. the output is high impedance when the chip is deselected or the outputs are disabled and when rp is at a low level. data input/outputs (dq8-dq14 and dq15aC1). these inputs/outputs are additionally used in the word-wide organisation. when byte is high dq8- dq14 and dq15aC1 act as the msb of the data input or output, functioning as described for dq0- dq7 above, and dq8 - dq15 are dont care for command inputs or status outputs. when byte is low, dq8-dq14 are high impedance, dq15aC1 is the address aC1 input. memory array enable ( ee and ef). the memory array enable ( ee or ef) activates the memory control logic, input buffers, decoders and sense amplifiers. when the ee input is driven high, the eeprom memory array is not selected; when the ef input is driven high, the flash memory array is not selected. attempts to access both eeprom and flash arrays ( ee low and ef low) are forbid- den. switching between the two memory array enables ( ee and ef) must not be made on the same clock cycle, a delay of greater than t ehfl must be inserted. the m39832 is in standby when both ef and ee are high (when no internal erase or programming is running). the power consumption is reduced to the standby level and the outputs are in the high impedance state, independent of the output en- able g or write enable w inputs. after 150ns of inactivity and when the addresses are driven at cmos levels, the chip automatically enters a pseudo standby mode where consumption is reduced to the cmos standby value, while the outputs continue to drive the bus. output enable ( g). the output enable gates the outputs through the data buffers during a read operation. the data outputs are in the high imped- ance state when the output enable g is high. during block protect and block unprotect opera- tions, the g input must be forced to v id level (12v + 0.5v) (for flash memory array only). symbol parameter value unit t a ambient operating temperature C40 to 85 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltages C0.6 to 5 v v cc supply voltage C0.6 to 5 v v a9 , v g , v ef (2) a9, g, ef voltage C0.6 to 13.5 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliab ility. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns. table 2. absolute maximum ratings (1) 3/36 m39832
16k boot block ai01725b 8k parameter block 8k parameter block 32k main block top boot block fffffh 90000h 8ffffh 80000h 7ffffh c0000h bffffh 00000h 64k main block 64k main block 64k main block 64k main block 64k main block 64k main block b0000h affffh a0000h 9ffffh 60000h 5ffffh 70000h 6ffffh f0000h effffh e0000h dffffh d0000h cffffh 64k main block 64k main block 64k main block 64k main block 64k main block 64k main block 64k main block 50000h 4ffffh 30000h 2ffffh 40000h 3ffffh 64k main block 64k main block 10000h 0ffffh 20000h 1ffffh fffffh f0000h fc000h fbfffh fa000h f9fffh f8000h f7fffh 7ffffh 48000h 47fffh 40000h 3ffffh 60000h 5ffffh 58000h 57fffh 50000h 4ffffh 30000h 2ffffh 38000h 37fffh 78000h 77fffh 70000h 6ffffh 68000h 67fffh byte-wide word-wide 7ffffh 78000h 7e000h 7dfffh 7d000h 7cfffh 7c000h 7bfffh 00000h 28000h 27fffh 18000h 17fffh 20000h 1ffffh 08000h 07fffh 10000h 0ffffh byte-wide word-wide figure 3a. top boot block memory map and block address table 4/36 m39832
16k boot block ai01731b 8k parameter block 8k parameter block 32k main block bottom boot block fffffh 90000h 8ffffh 80000h 7ffffh c0000h bffffh 00000h 64k main block 64k main block 64k main block 64k main block 64k main block 64k main block b0000h affffh a0000h 9ffffh 60000h 5ffffh 70000h 6ffffh f0000h effffh e0000h dffffh d0000h cffffh 64k main block 64k main block 64k main block 64k main block 64k main block 64k main block 64k main block 50000h 4ffffh 30000h 2ffffh 40000h 3ffffh 64k main block 64k main block 10000h 0ffffh 20000h 1ffffh 0ffffh 00000h 08000h 07fffh 06000h 05fffh 04000h 03fffh fffffh 7ffffh 48000h 47fffh 40000h 3ffffh 60000h 5ffffh 58000h 57fffh 50000h 4ffffh 30000h 2ffffh 38000h 37fffh 78000h 77fffh 70000h 6ffffh 68000h 67fffh 07fffh 00000h 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h 28000h 27fffh 18000h 17fffh 20000h 1ffffh 08000h 07fffh 10000h 0ffffh byte-wide word-wide byte-wide word-wide figure 3b. bottom boot block memory map and block address table 5/36 m39832
address range (x8) address range (x16) a18 a17 a16 a15 a14 a13 a12 00000h-0ffffh 00000h-07fffh 0000xxx 10000h-1ffffh 08000h-0ffffh 0001xxx 20000h-2ffffh 10000h-17fffh 0010xxx 30000h-3ffffh 18000h-1ffffh 0011xxx 40000h-4ffffh 20000h-27fffh 0100xxx 50000h-5ffffh 28000h-2ffffh 0101xxx 60000h-6ffffh 30000h-37fffh 0110xxx 70000h-7ffffh 38000h-3ffffh 0111xxx 80000h-8ffffh 40000h-47fffh 1000xxx 90000h-9ffffh 48000h-4ffffh 1001xxx a0000h-affffh 50000h-57fffh 1010xxx b0000h-bffffh 58000h-5ffffh 1111xxx c0000h-cffffh 60000h-67fffh 1100xxx d0000h-dffffh 68000h-6ffffh 1101xxx e0000h-effffh 70000h-77fffh 1110xxx f0000h-f7fffh 78000h-7bfffh 11110xx f8000h-f9fffh 7c000h-7cfffh 1111100 fa000h-fbfffh 7d000h-7dfffh 1111101 fc000h-fffffh 7e000h-7ffffh 111111x table 3a. m39832-t block address table 6/36 m39832
address range (x8) address range (x16) a18 a17 a16 a15 a14 a13 a12 00000h-03fffh 00000h-01fffh 0 0 0 0 0 0 x 04000h-05fffh 02000h-02fffh 0 0 0 0010 06000h-07fffh 03000h-03fffh 0 0 0 0011 08000h-0ffffh 04000h-07fffh 0 0 0 0 1 x x 10000h-1ffffh 08000h-0ffffh 0 0 0 1 x x x 20000h-2ffffh 10000h-17fffh 0 0 1 0 x x x 30000h-3ffffh 18000h-1ffffh 0 0 1 1 x x x 40000h-4ffffh 20000h-27fffh 0 1 0 0 x x x 50000h-5ffffh 28000h-2ffffh 0 1 0 1 x x x 60000h-6ffffh 30000h-37fffh 0 1 1 0 x x x 70000h-7ffffh 38000h-3ffffh 0 1 1 1 x x x 80000h-8ffffh 40000h-47fffh 1 0 0 0 x x x 90000h-9ffffh 48000h-4ffffh 1 0 0 1 x x x a0000h-affffh 50000h-57fffh 1 0 1 0 x x x b0000h-bffffh 58000h-5ffffh 1 0 1 1 x x x c0000h-cffffh 60000h-67fffh 1 1 0 0 x x x d0000h-dffffh 68000h-6ffffh 1 1 0 1 x x x e0000h-effffh 70000h-77fffh 1 1 1 0 x x x f0000h-fffffh 78000h-7ffffh 1 1 1 1 x x x table 3b. m39832-b block address table 7/36 m39832
ef ee g w operation v il v ih v il v ih read in flash array v ih v il v il v ih read in eeprom array v il v ih v ih v il write in flash array v ih v il v ih v il write in eeprom array v il v ih v ih v ih output disable, dqn = hi-z v ih v il v ih v ih output disable, dqn = hi-z v ih v ih x x standby, dqn = hi-z note: x = v il or v ih . table 4. basic operations write enable ( w). addresses are latched on the falling edge of w, and data inputs are latched on the rising edge of w. eeprom ready/busy (er b) . the eeprom ready/busy pin outputs the status of the device when the eeprom memory array is under the write condition Cer b = 0: internal writing is in process, Cer b = 1: no internal writing in in process. this status pin can be used when reading (or fetching opcodes) in the flash memory array. the eeprom ready/busy output uses an open drain transistor, allowing therefore the use of the m39832 in multi-memory applications with all ready/busy outputs connected to a single ready/busy line (or-wired with an external pull-up resistor). flash ready/busy (fr b). flash ready/busy is an open-drain output and gives the internal state of flash array. when fr b is low, the flash array is busy with a program or erase operation and it will not accept any additional program or erase instruc- tions except the erase suspend instruction. when fr b is high, the flash array is ready for any read, program or erase operation. the fr b will also be high when the flash array is put in erase suspend or standby modes. reset/block temporary unprotect input ( rp) . the rp input provides hardware reset of the flash array and temporary unprotection of the protected flash block(s). reset of the flash array is acheived by pulling rp to v il for at least t plpx . when the reset pulse is given while the flash array is in read or standby modes, it will be available for new operations in t phel after the rising edge of rp. if the flash array is in erase, erase suspend or program modes the reset will take t plyh during which the fr b signal will be held at vil. the end of the flash array reset will be indicated by the rising edge of fr b. a hardware reset during an erase or program operation will corrupt the data being programmed or the block(s) being erased. see table 14 and figure 9. temporary block unpro- tection is made by holding rp at v id . in this condi- tion, previously protected blocks can be programmed or erased. the transition of rp from v ih to v id must be slower than t phphh . see table 15 and figure 9. when rp is returned from v id to v ih all blocks temporarily unprotected will be again protected. operations an operation is defined as the basic decoding of the logic level applied to the control input pins ( ef, ee, g, w) and the specified voltages applied on the relevant address pins. these operations are detailed in table 3. read. both chip enable and output enable (that is ef and g or ee and g) must be low in order to read the output of the memory. read operations are used to output the contents from the flash or eeprom array, the manufacturer identifier, the flash block protection status, the flash identifier, the eeprom identifier or the otp row content. notes: C the chip enable input mainly provides power control and should be used for device selection. the output enable input should be used to gate data onto the output in combination with active ef or ee input signals. C the data read depends on the previous instruc- tion entered into the memory. 8/36 m39832
mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rd (2,4) read/reset memory array 1+ addr. (3,7) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,7) byte aaaah 5555h aaaah read memory array until a new write cycle is initiated. word 5555h 2aaah 5555h data aah 55h f0h as (4) auto select 3+ addr. (3,7) byte aaaah 5555h aaaah read electronic signature or block protection status until a new write cycle is initiated. see note 5 and 6. word 5555h 2aaah 5555h data aah 55h 90h pg program 4 addr. (3,7) byte aaaah 5555h aaaah program address read data polling or toggle bit until program completes. word 5555h 2aaah 5555h data aah 55h a0h program data be block erase 6 addr. (3,7) byte aaaah 5555h aaaah aaaah 5555h block address additiona l block (8) word 5555h 2aaah 5555h 5555h 2aaah data aah 55h 80h aah 55h 30h 30h fae flash array erase 6 addr. (3,7) byte aaaah 5555h aaaah aaaah 5555h aaaah note 9 word 5555h 2aaah 5555h 5555h 2aaah 5555h data aah 55h 80h aah 55h 10h es (10) erase suspend 1 addr. (3,7) x read until toggle stops, then read all the data needed from any block(s) not being erased then resume erase. data b0h er erase resume 1 addr. (3,7) x read data polling or toggle bits until erase completes or erase is suspended another time data 30h notes: 1. commands not interpreted in this table w ill default to r ead array mode. 2. a wait of t plyh is necessary after a read/reset command if the memory was in an erase or program mode before starting any new operation (see table 14 and figure 9). 3. x = dont care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the command cycles. 5. signature address bits a0, a1, at v il will output manufacturer code (20h). address bits a0 at v ih and a1, at v il will output flash code. 6. block protection address: a0, at v il , a1 at v ih and a15-a18 within the block w ill output the block protection status. 7. for coded cycles address inputs a11-a18 are dont care. 8. optional, additional blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through dq3 value (see erase timer bit dq3 description). when full command is entered, read data polling or toggle bit until erase is completed or suspended. 9. read data polling, toggle bits or fr b until erase completes. 10.during erase suspend, read and data program functions are allowed in blocks not being erased. table 5a. flash instructions ( ef=0, ee=1) 9/36 m39832
mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. wotp (2) write otp row >3 addr. byte 5555h 2aaah 5555h addr 1 addr 2 addr 3 addr 4 word 5555h 2aaah 5555h data aah 55h b0h byte 1 byte 2 byte 3 byte 4 rotp (2) read otp row >3 addr. byte 5555h 2aaah 5555h addr 1 addr 2 addr 3 addr 4 word 5555h 2aaah 5555h data aah 55h 90h byte 1 byte 2 byte 3 byte 4 rt return from otp read 1 addr. x (1) data f0h ssdp (4) sdp enable 3 3 addr. byte 5555h 2aaah 5555h word 5555h 2aaah 5555h data aah 55h a0h ssdp (5) sdp disable 6 addr. byte 5555h 2aaah 5555h 5555h 2aaah 5555h word 5555h 2aaah 5555h 5555h 2aaah 5555h data aah 55h 80h aah 55h 20h notes: 1. x = dont care. 2. once the wotp has been initiated (first 3 cycles), from 1 up to 64 bytes can be written in one single write cycle (see write otp chapter in following pages). 3. once the rotp has been initiated (first 3 cycles), from 1 up to 64 bytes of the otp can be read (see read otp chapter in following pages). the rt (return) instruction must be sent to the device to exit rotp mode. 4. once sdp is set (ssdp instruction sent once), it is necessary to send ssdp prior to any byte or page to be written in the eeprom array (see figure 4 and eeprom array software data protection chapter in following pages). 5. see figure 5 and eeprom array software data protection chapter in following pages. table 5b. eeprom instructions ( ee=0, ef=1) 10/36 m39832
operation ee ef g w rp byte a0 a1 a6 a9 a12 a15 dq15 aC1 dq8- dq14 dq0-dq7 block protection (2,4) v ih v il v id v il pulse v ih x xxxv id xx x x x blocks unprotection (4) v ih v id v id v il pulse v ih x xxxv id v ih v ih xx x block protection verify (2,4) v ih v il v il v ih v ih xv il v ih v il v id a12 a15 x x block protect status (3) block unprotection verify (2,4) v ih v il v il v ih v ih xv il v ih v ih v id a12 a15 x x block protect status (3) block temporary unprotection v ih xx x v id x xxxx x x x x x write the eeprom identifier (5) v il v ih v ih v il v ih v il a0 a1 v il v id xxaC1 x 64 bytes user defined v ih v il v ih v ih a0 a1 v il v id xx x x 64 bytes user defined read the eeprom identifier (5) v il v ih v il v ih v ih v il a0 a1 v il v id xxaC1 x 64 bytes user defined v il v ih v ih v ih a0 a1 v il v id xx x x 64 bytes user defined notes: 1. x = v il or v ih 2. block address must be given on a12-a18 bits. 3. see table 8. 4. operation performed on programming equipment. 5. the 65 bytes user defined eeprom identifier are accessed on dq0-dq7 with a0 to a5 when byte = 1 (x16) or with aC1 to a4 when byte = 0 (x8) table 6. user bus operations (1) org. code device ee ef g w byte a0 a1 other addresses dq15 aC1 dq8- dq14 dq0- dq7 word- wide manufacturer v ih v il v il v ih v ih v il v il dont care 0 00h 20h flash m39832-t v ih v il v il v ih v ih v ih v il dont care 0 00h d7h m39832-b v ih v il v il v ih v ih v ih v il dont care 0 00h 5bh byte- wide manufacturer v ih v il v il v ih v il v il v il dont care dont care hi-z 20h flash m39832-t v ih v il v il v ih v il v ih v il dont care dont care hi-z d7h m39832-b v ih v il v il v ih v il v ih v il dont care dont care hi-z 5bh table 7. read electronic signature (following as instruction or with a9 = v id ) 11/36 m39832
dq name logic level definition note 7 data polling 1 erase complete or erase block in erase suspend indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. 0 erase on-going dq program complete or data of non erase block during erase suspend dq program on-going 6 toggle bit -1-0-1-0-1-0-1- erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete -1-1-1-1-1-1-1- erase complete or erase suspend on currently addressed block 5 error bit 1 program or erase error this bit is set to 1 in the case of programming or erase failure. 0 program or erase on-going 4 reserved 3 erase time bit 1 erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es). 0 erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c. 2 toggle bit -1-0-1-0-1-0-1- chip erase, erase or erase suspend on the currently addressed block. erase error due to the currently addressed block (when dq5 = 1). indicates the erase status and allows to identify the erased block 1 program on-going, erase on-going on another block or erase complete dq erase suspend read on non erase suspend block 1 reserved 0 reserved notes: logic level 1 is high, 0 is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. table 9. status bit code e g w a0 a1 a12-a18 other addresses dq0-dq7 protected block v il v il v ih v il v ih block address dont care 01h unprotected block v il v il v ih v il v ih block address dont care 00h table 8. read block protection with as instruction ( ef = 0, ee = 1) 12/36 m39832
write. a write operation can be used for two goals: C either write data in the eeprom memory array C or enter a sequence of bytes or word composing an instruction. the reader should note that programming a flash byte or word is an instruction (see instructions paragraph). writing data requires: C the chip enable (either ee or ef) to be low C the write enable ( w) to be low with output enable (g) high. addresses in flash array (or eeprom array) are latched on the falling edge of w or ef ( ee) which- ever occurs last; the data to be written in flash array (eeprom array) is latched on the rising edge of w or ef ( ee) whichever occurs first. specific read and write operations. device specific data is accessed through operations de- coding the v id level applied on a9 and the logic levels applied on address inputs (a0, a1, a6). these specific operations are: C read the manufacturer identifier C read the flash identifier C define and read the flash block protection status C read the eeprom identifier C write the eeprom identifier note: the otp row (64 bytes) is accessed with a specific software sequence detailed in the para- graph "write in otp row". instructions an instruction is defined as a sequence of specific write operations. each received byte or word is sequentially decoded (and not executed as stand- ard write operations) and the instruction is exe- cuted when the correct number of bytes or word are properly received and the time between two consecutive bytes or words is shorter than the time-out value. the sequencing of any instruction must be followed exactly, any invalid combination of instruction bytes or word or time-out between two consecutive bytes or word will reset the device logic into a read memory state (when addressing the flash array) or directly decoded as a single operation when addressing the eeprom array. for efficient decoding of the instruction, the two first bytes or words of an instruction are the coded cycles and are followed by a command confirma- tion byte or word. ai01698b write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h sdp is set write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h write data to be written in any address sdp enable algorithm page write instruction page write instruction write is enabled sdp set sdp not set write in memory write data + sdp set after twc figure 4. eeprom sdp enable flowcharts 13/36 m39832
read read operations and instructions can be used to: C read the contents of the memory array (flash and eeprom) C read the status bits and identifiers. read data (flash and eeprom) both chip enable ef (or ee) and output enable ( g) must be low in order to read the data from the memory. read the manufacturer identifier the manufacturers identifier can be read with two methods: a read operation or a read instruction. read operation. the manufacturers identifier can be read with a read operation with specific logic levels applied on a0, a1, a6 and the v id level on a9 (see table 7). read instruction. the manufacturers identifier can also be read with a single read operation immediatly following the as instruction (see table 5a and table 7). read the flash identifier the flash identifier can be read with two methods: a read operation or a read instruction. read operation. the flash identifier can be read with a single read operation with specific logic levels applied on a0, a1, a6 and the v id level on a9 (see table 7). read instruction. the flash identifier can also be read with a single read operation immediatly follow- ing the as instruction (see table 5a and table 7). ai01699b write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h unprotected state after twc (write cycle time) write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h page write instruction figure 5. eeprom sdp disable flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 6. eeprom and flash data polling flowchart 14/36 m39832
read the eeprom identifier the eeprom identifier (64 bytes, user defined) can be read with a single read operation with a6 = 0 and a9 = v id (see table 6). when accessing the 64 bytes of eeprom identi- fier, the only lsb addresses are decoded. the lsb addresses are a0 to a5 when byte = 1 (x16) and aC1 to a4 when byte = 0 (x8). each byte of the eeprom identifier can be individually accessed in read or write mode. read the otp row the otp row is mapped in the eeprom array ( ee = 0, ef = 1). read of the otp row (64 bytes) is by an instruction (rotp) composed of three specific write operations of data bytes at three specific memory locations (each location in a dif- ferent page) before reading the otp row content (see table 5b). when accessing the otp row, only the lsb ad- dresses are decoded and a6 must be 0. the lsb addresses are a0 to a5 when byte = 1 (x16) and aC1 to a4 when byte = 0 (x8). each read of the otp row has to be followed by the (rt) return instruction (see table 5b). read the flash block protection status reading the flash block protection status is by a read operation immediatly following the as instruc- tion (see table 5a and table 8). a12-a18 define the flash block whose protection has to be veri- fied. this read operation will output a 01h if the flash block is protected and a 00h if the flash block is not protected. the flash block protection status can also be verified with a single read operation (see chapter: flash array specific features), with v id on a9 (see table 6 and table 8). read the status bits the m39832 provides several write operation status flags which may be used to minimize the application write (or erase or program) time. these signals are available on the i/o port bits when programming (or erasing) are in progress. it should be noted that the ready/busy pins also reflects the status of the eeprom write and the flash pro- gramming/erasing. data polling flag, dq7. when erasing or pro- gramming into the flash block (or when writing into the eeprom block), bit dq7 outputs the comple- ment of the bit being entered for program- ming/writing on dq7. once the program instruc- tion or the write operation is performed, the true logic value is read on dq7 (in a read operation). flash memory block specific features: C data polling is effective after the fourth w pulse (for programming) or after the sixth w pulse (for erase). it must be performed at the address being programmed or at an address within the flash sector being erased. C during an erase instruction, dq7 outputs a 0. after completion of the instruction, dq7 will out- put the last bit programmed (that is a 1 after erasing). C if the byte to be programmed is in a protected flash sector, the instruction is ignored. C if all the flash sectors to be erased are pro- tected, dq7 will be set to 0 for about 100 m s, and then return to the previous addressed byte. no erasure will be performed. C if all sectors are protected, a bulk erase instruc- tion is ignored. toggle flag, dq6. the m39832 also offers another way for determining when the eeprom write or the flash memory program instruction is com- pleted. during the internal write operation, the dq6 will toggle from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory, when either g , ee or ef is low. when the internal cycle is completed the toggling will stop and the data read on dq0-dq7 is the addressed memory byte. the device is now acces- sible for a new read or write operation. the opera- tion is completed when two successive reads yield the same output data. flash memory block specific features: a. the toggle bit is effective after the fourth w pulse (for programming) or after the sixth w pulse (for erase). b. if the byte to be programmed belongs to a pro- tected flash sector, the instruction is ignored and: C if all the flash sectors selected for erasure are protected, dq6 will toggle to 0 for about 100 m s, and then return to the previous ad- dressed byte. C if all sectors are protected, the bulk erase in- struction is ignored. 15/36 m39832
read dq2, dq5 & dq6 start read dq2, dq6 fail pass ai01873 dq2, dq6 = toggle no no yes yes dq5 = 1 no yes dq2, dq6 = toggle figure 7b. flash ata toggle flowchart read dq5 & dq6 start read dq6 fail pass ai01370 dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle figure 7a. data toggle flowchart toggle bit, dq2 (flash array only). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. it can also be used to identify the block being erased. during erase or erase suspend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will set dq2 to 1 during erase and to dq2 during erase suspend. during flash array erase, a read operation will cause dq2 to toggle as all blocks are being erased. dq2 will be set to 1 during program operation and when erase is complete. after erase completion and if the error bit dq5 is set to 1, dq2 will toggle if the faulty block is addressed. error flag, dq5 (flash block only). this bit is set to 1 by the internal logic when there is a failure of programming, block erase, or chip erase that re- sults in invalid data in the memory block. in case of an error in block erase or program, the block in which the error occured or to which the pro- grammed data belongs, must be discarded. the dq5 failure condition will also appear if a user tries to program a 1 to a location that is previously programmed to 0. other blocks may still be used. the error bit resets after a read/reset (rd) in- struction. in case of success of program or erase, the error bit will be set to 0 . when a0 is high with a1 low. erase timer bit, dq3 (flash array only). this bit is set to 0 by internal logic when the last block erase command has been entered to the com- mand interface and it is awaiting the erase start. when the erase timeout period is finished, after 50ms to 90ms, dq3 returns to 1. write a byte (or a page) in eeprom it should be noticed that writing in the eeprom array is an operation, it is not an instruction (as for programming a byte in the flash array). write a byte in eeprom array a write operation is initiated when chip enable ee is low and write enable w is low with output 16/36 m39832
enable g high. addresses are latched on the falling edge of w, ee whichever occurs last. once initiated, the write operation is internally timed until completion, that is during a time t w . the status of the write operation can be found by reading the data polling and toggle bits (as de- tailed in the read chapter) or the er b output. this ready/busy output is driven low from the write of the byte being written until the completion of the internal write sequence. write a page in eeprom array the page write allows up to 64 bytes within the same eeprom page to be consecutively latched into the memory prior to initiating a programming cycle. all bytes must be located in a single page address, that is a6-a14 when byte is high (x16) or a5-a13 when byte is low (x8) must be the same for all bytes. once initiated, the page write opera- tion is internally timed until completion, that is dur- ing a time t wc . the status of the write operation can be seen by reading the data polling and toggle bits (as de- tailed in the read chapter) or the er b output. this ready/busy output is driven low from the write of the first byte to be written until the completion of the internal write sequence. a page write is composed of successive write operations which must be sequenced within a time period (between two consecutive write operations) that is smaller than the t wlwl value. if this period of time exceeds the t wlwl value, the internal program- ming cycle will start. eeprom array software data protection a protection instruction allows the user to inhibit all write modes to the eeprom array: the software data protection (referenced as sdp in the follow- ing). the sdp feature is useful for protecting the eeprom memory from inadvertent write cycles that may occur during uncontrolled bus conditions. the m39832 is shipped as standard in the unpro- tected state meaning that the eeprom memory contents can be changed by the user. after the sdp enable instruction, the device enters the protect mode where no further write operations have any effect on the eeprom memory contents. the device remains in this mode until a valid sdp disable instruction is received whereby the device reverts to the unprotected state. to enable the software data protection, the device has to be written (with a page write) with three specific data bytes at three specific memory loca- tions (each location in a different page) as shown in figure 4 and table 5b. this sequence provides an unlock key to enable the write action, and, at the same time, sdp continues to be set. any further write in eeprom when the sdp is set will use this same sequence of three specific data bytes at three specific memory locations followed by the bytes to write. the first sdp enable sequence can be di- rectly followed by the bytes to written. similarly, to disable the software data protection the user has to write specific data bytes into six different locations with a page write addressing different bytes in different pages, as shown in fig- ure 5 and table 5b. the software data protection state is non-volatile and is not changed by power on/off sequences. the sdp enable/disable instructions set/reset an inter- nal non-volatile bit and therefore will require a write time t wc , this write operation can be monitored only on the toggle bit (status bit dq6) and the er b pin. the ready/busy output is driven low from the first byte to be written (that is the first write aah, @5555h of the sdp set/reset sequence) until the completion of the internal write sequence. write otp row writing (only one time) in the otp row (64 bytes) is enabled by an instruction (wotp). this instruc- tion is composed of three specific write operations of data bytes at three specific memory locations (each location in a different page) followed by the the data to store in the otp row (refer to table 5b). when accessing the otp row, the only lsb ad- dresses are decoded and a6 must be 0. the lsb addresses are a0 to a5 when byte = 1 (x16) and aC1 to a4 when byte = 0 (x8). once at least one byte of the otp row has been written (even with ffh), the whole row becomes read only. write the eeprom block identifier the eeprom block identifier (64 bytes) can be written with a single write operation with a6 = 0 and the v id level on a9 (see table 6). when ac- cessing the 64 bytes of eeprom identifier, the only lsb addresses are decoded. the lsb ad- dresses are a0 to a5 when byte = 1 (x16) and a-1 to a4 when byte = 0 (x8). each byte of the eeprom identifier can be individually accessed in read or write mode. program in the flash array it should be noted that writing data into the eeprom array and the flash array is not per- formed in a similar way: the flash memory requires an instruction (see instruction chapter) for erasing and another instruction for programming one (or more) byte(s) or word(s), the eeprom memory is directly written with a simple operation (see opera- tion chapter). 17/36 m39832
program (pg) instruction. this instruction uses four write cycles. both for byte-wide configuration and for word-wide configuration. the program command a0h is written to address aaaah in the byte-wide configuration or to address 5555h in the word-wide configuration on the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or ef and the data to be written on the rising edge and starts the internal operation. read operations output the status register bits after the programming has started. memory programming is made only by writing 0 in place of 1. status bits dq6 and dq7 determine if programming is on-going and dq5 allows verification of any possible error. program- ming at an address not in blocks being erased is also possible during erase suspend. in this case, dq2 will toggle at the address being programmed. auto select (as) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address aaaah in the byte-wide configuration or address 5555h in the word-wide configuration for command set-up. a subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of a0 and a1. the manufacturer code is output when the addresses lines a0 and a1 are low, the flash code for top boot or bottom boot is output when a0 is high with a1 low. the as instruction allows access to the block pro- tection status. after giving the as instruction, a0 is set to v il with a1 at v ih , while a12-a18 define the address of the block to be verified. a read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. the erase in the flash array flash array erase (fae) instruction. this in- struction uses six write cycles. the erase set-up command 80h is written to address aaaah in the byte-wide configuration or the address 5555h in the word-wide configuration on the third cycle after the two coded cycles. the flash array erase con- firm command 10h is similarly written on the sixth cycle after another two coded cycles. if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to read array. it is not necessary to program the array with 00h first as it will be done automatically before erasing it to ffh. read opera- tions after the sixth rising edge of w or ef output the status register bits. during the execution of the erase, data polling bit dq7 returns 0, then 1 on completion. the toggle bits dq2 and dq6 toggle during erase operation and stop when erase is completed. after completion, the status bit dq5 returns 1 if there has been an erase failure. block erase (be) instruction. this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address aaah in the byte-wide configuration or address 5555h in the word-wide configuration on third cycle after the two coded cycles. the block erase confirm com- mand 30h is similarly written on the sixth cycle after another two coded cycles. during the input of the second command an address within the block to be erased is given and latched into the memory. addi- tional block erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further coded cy- cles. the erase will start after the erase timeout period (see erase timer bit dq3 description). thus, additional erase confirm commands for other blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the internal timer can be monitored through the level of dq3, if dq3 is 0 the block erase command has been given and the timeout is running, if dq3 is 1, the timeout has expired and the block(s) are being erased. if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the block with 00h as it will be done automatically before erasing it to ffh. read operations after the sixth rising edge of w or ef output the status register bits. during the execution of the erase , the memory accepts only the erase suspend es and read/re- set rd instructions. data polling bit dq7 returns 0 while the erasure is in progress and 1 when it has completed. the toggle bit dq2 and dq6 toggle during the erase operation. they stop when erase is completed. after completion the status bit dq5 returns 1 if there has been an erase failure. in such a situation, the toggle bit dq2 can be used to determine which block is not correctly erased. in the case of erase failure, a read/reset rd instruc- tion is necessary in order to reset the memory. 18/36 m39832
block address on a12 to a18 ee = v ih ai00853 g, a9 = v id , ef = v il n = 0 wait 4s wait 100s w = v il w = v ih g = v ih read dq0 at protection address: a0, a6 = v il , a1 = v ih and a12 to a18 defining block a9 = v ih ++n = 25 start fail pass yes no dq0 = 1 yes no a9 = v ih wait 4s figure 8. block protection flowchart 19/36 m39832
ai00850 a6, a12, a15 = v ih g, a9 = v ih data ef, g, a9 = v id wait 4s w = v ih ef, g = v ih read at unprotection address: a1, a6 = v ih , a0 = v il and a12 to a18 defining block (see note 1) wait 10ms wait 4s = 00h increment block n = 0 wait 4s w = v il ++n = 1000 start fail yes yes no pass no last block yes no ee = ef = v ih figure 9. block unprotecting flowchart note: 1. a6 is kept at v ih during unprotection algorithm in order to secure best unprotection verification. during all other protection status reads, a6 must be kept at v il . 20/36 m39832
erase suspend (es) instruction. the block erase operation may be suspended by this instruc- tion which consists of writing the command b0h without any specific address. no coded cycles are required. it permits reading of data from another block and programming in another block while an erase operation is in progress. erase suspend is accepted only during the block erase instruction execution. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit dq6 stops toggling when erase is suspended. the toggle bits will stop toggling between 0.1ms and 15ms after the erase suspend (es) command has been writ- ten. the device will then automatically be set to read memory array mode. when erase is sus- pended, a read from blocks being erased will output dq2 toggling and dq6 at 1. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instruc- tions. a program operation can be initiated during erase suspend in one of the blocks not being erased. it will result in both dq2 and dq6 toggling when the data is being programmed. a read/reset com- mand will definitively abort erasure and result in invalid data in the blocks being erased. erase resume (er) instruction. if an erase sus- pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. flash array specific features block protection (see figure 8). each block can be separately protected against program or erase on programming equipment. block protection pro- vides additional data security, as it disables all program or erase operations. this mode is acti- vated when both a9 and g are raised to v id and an address in the block is applied on a12-a18. block protection is initiated on the edge of w falling to v il . then after a delay of 100ms, the edge of w rising to v ih ends the protection operations. block protec- tion verify is achieved by bringing g, ef, a0 and a6 to v il and a1 to v ih , while w is at v ih and a9 at v id . ai00939 v cc / 2 v cc 0v figure 10. ac testing input output waveform ai00854 v cc c l = 30pf c l includes jig capacitance v out = 1.5v when the device under test is in the hi-z output state. 1n914 device under test 1n914 i oh i ol figure 11. output ac testing load circuit symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf note: 1. sampled only, not 100% tested. table 11. capacitance (1) (t a = 25 c, f = 1 mhz ) input rise and fall times 10ns input pulse voltages 0.v to v cc input and output timing ref. voltages v cc / 2 table 10. ac measurement conditions 21/36 m39832
under these conditions, reading the data output will yield 01h if the block defined by the inputs on a12-a18 is protected. any attempt to program or erase a protected block will be ignored by the device. remarks: C the verify operation is a read with a simulated worst case conditions. this allows a guarantee of the retention of the protection status C during the application life, the block protection status can be accessed with a regular read instruction without applying a "high voltage" v id on a9. this instruction is detailed in table 5 and table 8. blocks unprotection (see figure 9). all protected blocks can be unprotected simultaneously on pro- gramming equipment to allow updating of bit con- tents. all blocks must first be protected before the unprotection operation. block unprotection is acti- vated when a9, g and e are at v id and a12, a15 at v ih . unprotection is initiated by the edge of w falling to v il . after a delay of 10ms, the unprotection operation will end. unprotection verify is achieved by bringing g and e to v il while a0 is at v il , a6 and a1 are at v ih and a9 remains at v id . in these conditions, reading the output data will yield 00h if the block defined by the inputs a12-a18 has been succesfully unprotected. each block must be sepa- rately verified by giving its address in order to ensure that it has been unprotected. remarks: C the verify operation is a read with a simulated worst case conditions. this allows a guarantee of the retention of the protection status C during the application life, the block protection status can be accessed with a regular read instruction without "high voltage" v id on a9. this instruction is detailed in table 5 and table 8. block temporary unprotection. any previously protected block can be temporarily unprotected in order to change stored data. the temporary un- protection mode is activated by bringing rp to v id . during the temporary unprotection mode the pre- viously protected blocks are unprotected. a block can be selected and data can be modified by executing the erase or program instruction with the rp signal held at v id . when rp is returned to vih, all the previously protected blocks are again pro- tected. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read operations will read the memory array addressed and output the data read. a wait state of 10ms is necessary after read/reset prior to any valid read if the memory was in an erase mode when the rd instruction is given. glossary array: eeprom array (256 kbit) or flash array (8 mbit) block: part of the flash array (see figure 3a and 3b). page: 64 bytes of eeprom write and program: writing (into the eeprom array) and programming (the flash array is not performed in a similar way: C the flash memory requires an instruction (see instruction chapter) for erasing and another in- struction for programming one (or more) byte(s) or word(s) C the eeprom memory is directly written with a simple operation (see operation chapter). sdp: software data protection. used for protect- ing the eeprom array against false write opera- tions (as in noisy environments). power supply and current consump- tion power up. the m39832 internal logic is reset upon a power-up condition to read memory status. any write operation in eeprom is inhibited during the first 5 ms following the power-up. either ef, ee or w must be tied to v ih during power-up for the maximum security of the data contents and to remove the possibility of a byte being written on the first rising edge of ef, ee or w. any write cycle initiation is locked when vcc is below v lko . supply rails. normal precautions must be taken for supply voltage decoupling, each device in a system should have the v cc rail decoupled with a 0.1 m f capacitor close to the v cc and v ss pins. the printed circuit board trace width should be sufficient to carry the v cc program and erase currents re- quired. 22/36 m39832
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 (1) supply current (read flash) ee = v ih , ef = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (read eeprom) ee = v il , ef = v ih , g = v ih , f = 6mhz 10 ma i cc3 supply current (standby) ef = ee = v cc 0.2v 100 m a i cc4 supply current (flash block program or erase) byte program, sector or chip erase in progress 20 ma i cc5 supply current (eeprom write) during t wc 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc vcc + 0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = C100 m av cc C0.4 v v id a9 high voltage 11.5 12.5 v i id v id current a9 = v id 100 m a v lko v cc minimum for write, erase and program 1.9 2.3 v note: 1. when reading the flash block when an eeprom byte(s) is under a write cycle, the supply current is i cc1 + i cc5 . table 12. dc characteristics (t a = 0 to 70 c or C40 to 85 c; v cc = 2.7 to 3.6v) 23/36 m39832
ai01952 tavav tavqv taxqx telqx tehqz tehqx tglqv tglqx tghqx tghqz valid a0-a18 ee (ef) g dq0-dq7 telqv valid address valid and chip enable output enable data valid tehfl tehfl ef (ee) figure 12. read mode ac waveforms note: write enable ( w) = high 24/36 m39832
symbol alt parameter test condition m39832 unit -120 -150 min max min max t avav t rc address valid to next address valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 120 150 ns t avqv t acc address valid to output valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 120 150 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 120 150 ns t glqx (1) t olz output enable low to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 00ns t glqv (2) t oe output enable low to output valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 55 55 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 40 40 ns t ghqx t oh output enable high to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 00ns t ghqz (1) t df output enable high to output hi-z (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 40 40 ns t axqx t oh address transition to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 00ns t ehfl t ced ee ( ef) active to ef ( ee) 100 100 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of ee (or ef) without increasing t elqv . table 13. read ac characteristics (t a = 0 to 70 c or C20 to 85 c; v cc = 3.3v 0.3v) 25/36 m39832
ai01953 e (1) g w a0-a18 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx write cycle tdvwh twlwh tghwl rb twhrl twhrh figure 13. write ac waveforms, w controlled notes: address are latched on the falling edge of w, data is latched on the rising edge of w. e is either ef when ee = v ih or ee when ef = v ih . 26/36 m39832
e (1) ai01954 g w a0-a18 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx write cycle tdveh teleh tghel dq0-dq7 rb twhrl figure 14. write ac waveforms, e controlled notes: address are latched on the falling edge of e, data is latched on the rising edge of e. e is either ef when ee = v ih or ee when ef = v ih . 27/36 m39832
symbol alt parameter m39832 unit -120 -150 min max min max t avav t wc address valid to next address valid 120 150 ns t elwl (2) t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 50 65 ns t dvwh t ds input valid to write enable high 50 65 ns t whdx t dh write enable high to input transition 0 0 ns t wheh (2) t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 30 35 ns t avwl t as address valid to write enable low 0 0 ns t wlax t ah write enable low to address transition 50 65 ns t ghwl output enable high to write enable low 0 0 ns t vchel t vcs v cc high to chip enable low 50 50 m s t whqv1 (1) write enable high to output valid (program) 15 15 m s t whqv2 (1) write enable high to output valid (sector erase) 2.0 30 2.0 30 sec t whwl0 time out between 2 consecutive section erase 80 80 m s t whgl t oeh write enable high to output enable low 0 0 ns t whrl (3) t db write enable high to ready/busy output low 150 150 ns notes: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv 2. chip enable means (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ). 3. with a 3.3k w pull-up resistor. table 14. write ac characteristics, write enable controlled (t a = 0 to 70 c or C40 to 85 c; v cc = 2.7v to 3.6v) 28/36 m39832
symbol alt parameter m39832 unit -120 -150 min max min max t wlwl t blc byte load cycle (eeprom) 0.2 150 0.2 150 m s t whrh t wc write cycle time (eeprom) 10 10 ms t avav address valid to next address valid 120 150 ns t wlel t ws write enable low to memory block enable low 0 0 ns t eleh t cp memory block enable low to memory block enable high 50 65 ns t dveh t ds input valid to memory block enable high 50 65 ns t ehdx t dh memory block enable high to input transition 0 0 ns t ehwh t wh memory block enable high to write enable high 0 0 ns t ehel t cph memory block enable high to memory block enable low 30 35 ns t avel t as address valid to memory block enable low 0 0 ns t elax t ah memory block enable low to address transition 50 65 ns t ghel output enable high to memory block enable low 0 0 ns t vchwl t vcs v cc high to write enable low 50 50 m s t ehqv1 (1) memory block enable high to output valid (program) 15 15 m s t ehqv2 (1) memory block enable high to output valid (sector erase) 2.0 30 2.0 30 sec t ehgl t oeh memory block enable high to output enable low 0 0 ns t ehrl (2) t db eeprom block enable high to ready/busy output low 150 150 ns notes: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv . 2. with a 3.3k w pull-up resistor. table 15. write ac characteristics, ee or ef controlled (t a = 0 to 70 c or C40 to 85 c; v cc = 2.7v to 3.6v) 29/36 m39832
ai01955 e (5) g w a0-a18 dq7 ignore valid dq0-dq6 byte address (within sectors) data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle data verify read cycle data polling read cycles last cycle of program or erase telqv figure 15. data polling dq7 ac waveforms notes: 1. all other timings are as a normal read cycle. 2. dq7 and dq0-dq6 can transmit to valid at any point during the data output valid period. 3. t whq7v is the program or erase time. 4. during erasing operation byte address must be within sector being erased. 5. e is either ef when ee = v ih or ee when ef = v ih . 30/36 m39832
symbol parameter m39832 unit -120 -150 min max min max t whq7v1 (2) write enable high to dq7 valid (program, w controlled) 10 10 m s t whq7v2 (2) write enable high to dq7 valid (sector erase, w controlled) 1.5 30 1.5 30 sec t ehq7v1 (2) flash block enable high to dq7 valid (program, ef controlled) 10 10 m s t ehq7v2 (2) flash block enable high to dq7 valid (sector erase, ef controlled) 1.5 30 1.5 30 sec t q7vqv q7 valid to output valid (data polling) 50 55 ns notes: 1. all other timings are defined in read ac characteristics table. 2. t whq7v is the program or erase time. table 16. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c or C40 to 85 c; v cc = 2.7v to 3.6v) parameter m39832 unit min typ typical after 100k w/e cycles max flash array erase (preprogrammed) 5 5 sec flash array erase 12 12 sec flash array block erase 2.4 sec parameter block erase 2.3 sec main block (32kb) erase 2.7 sec main block (64kb) erase 3.3 15 sec chip program (byte) 8 8 sec byte program 10 10 m s word program 20 20 m s program/erase cycles (per block) 100,000 cycles table 17. program, erase times and program, erase endurance cycles (flash block) (t a = 0 to 70 c; v cc = 2.7v to 3.6v) 31/36 m39832
ai01956 e (2) g w a0-a18 dq6 dq0-dq5, tavqv stop toggle last cycle of program of erase valid valid valid ignore dq7 data toggle read cycle read cycle twhqv tehqv telqv tglqv data toggle read cycle figure 16. data toggle dq6 ac waveforms notes: 1. all other timings are as a normal read cycle. 2. e is either ef when ee = v ih or ee when ef = v ih . 32/36 m39832
ai00856 a0-a14 or aC1-a13 ee g dq0-dq7 w twlwl addr 0 erb addr 1 addr 2 addr n twhrh twlwh twhwl twhrl byte 0 byte 1 byte 2 byte n figure 17. eeprom page write mode ac waveforms, w controlled 33/36 m39832
ordering information scheme devices are shipped from the factory with the memory content set at all "1s" (ffh). for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. array matrix t top boot b bottom boot speed 12 120ns 15 150ns operating voltage w 2.7v to 3.6v package ne tsop48 12 x 20mm option t tape & reel packing temp. range 1 0 to 70 c 6 C40 to 85 c example: m39832 - b 15 w ne 6 t 34/36 m39832
tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 11.90 12.10 0.469 0.476 e 0.50 - - 0.020 - - l 0.50 0.70 0.020 0.028 a 0 5 0 5 n48 48 cp 0.10 0.004 drawing is not to scale. tsop48 - 48 lead plastic thin small outline, 12 x 20mm 35/36 m39832
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 36/36 m39832

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