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ftg for integrated core logic with 133-mhz fsb W238-02 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 document #: 38-07103 rev. *a revised december 26, 2002 1W238-02 features ? maximized emi suppression using cypress?s spread spectrum technology ? low jitter and tightly controlled clock skew ? highly integrated device providing clocks required for cpu, core logic, and sdram ? two copies of cpu clock at 66/100/133 mhz ? thirteen copies of sdram clocks at 100/133 mhz ? five copies of pci clock compliant to pci spec 2-1 and capable of driving a maximum load of 40 pf ? one copy of synchronous apic clock ? two copies of 48-mhz clock (non-spread spectrum) op- timized for usb reference input and video dot clock ? three copies of 66-mhz fixed clock ? one copy of 14.31818-mhz reference clock ? power down control ? smbus interface for turning off unused clocks key specifications cpu, sdram outputs cycle-to-cycle jitter:.............. 250 ps apic, 48-mhz, 3v66, pci outputs cycle-to-cycle jitter:................................................... 500 ps apic, 48-mhz, sdram output skew: ........................250 ps cpu, 3v66 output skew:............................................ 175 ps pci output skew:........................................................ 500 ps cpu to sdram skew (@ 133 mhz):......................... 0.5 ns cpu to sdram skew (@ 100 mhz):.................4.5 to 5.5 ns cpu to 3v66 skew (@ 66 mhz): .......................7.0 to 8.0 ns 3v66 to pci skew (3v66 lead):..........................1.5 to 3.5 ns pci to apic skew: ..................................................... 0.5 ns table 1. pin selectable functions tristate# fsel1 fsel0 function sdram 0 x 0 three -state three-state 0x1 test test 1 0 0 66 mhz 100 mhz 1 0 1 100 mhz 100 mhz 1 1 0 133 mhz 133 mhz 1 1 1 133 mhz 100 mhz block diagram pin configuration vddq3 vddq2 pci0_ich xtal pll ref freq pll 1 x2 x1 ref/fsel1 pci1:4 usb dot pll2 osc vddq3 smbus sdata logic sclk 3v66_0:1 cpu0:1 fsel0:1 apic0:1 divider, delay, and phase control logic 4 2 vddq3 2 2 sdram0:12 13 pwrdwn#/tristate# apic vddq2 gnd ref/fsel1 vddq3 x1 x2 gnd vddq3 3v66_0 3v66_1 3v66_agp gnd pci_ich pci1 pci2 vddq3 gnd pci3 pci4 gnda vdda sclk sdata W238-02 gnd vddq2 cpu0 cpu1 gnd sdram0 sdram1 vddq3 gnd sdram2 sdram3 sdram4 sdram5 vddq3 gnd sdram6 sdram7 sdram8 sdram9 vddq3 gnd sdram10 sdram11 vddq3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 31 30 29 gnd vddq3 usb dot gnd sdram12 pwrdwn#/tristate# fsel0 3v66_agp
W238-02 document #: 38-07103 rev. *a page 2 of 18 pin definitions pin name pin no. pin type pin description ref/fsel1 4 i/o reference clock/function select: 3.3v 14.318-mhz clock output. this pin also serves as a strap option for cpu frequency selection. see table 1 for detailed descriptions. x1 6 i crystal input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 7 i crystal output: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. pci0_ich, pci1:4 14, 15, 16, 19, 20 o pci clock 0 through 4: 3.3v 33-mhz pci clock outputs. pci1:4 can be individually turned off via smbus interface. 3v66_0:1 3v66_agp 10, 11, 12 o 66-mhz clock output: 3.3v fixed 66-mhz clock. usb 28 o usb clock output: 3.3v fixed 48-mhz, non-spread spectrum usb clock outputs. dot 29 o dot clock output: 3.3v 48-mhz, non-spread spectrum signal. fsel0 21 i clock function selection pins: lvttl-compatible input (latched) to select de- vice functions. see table 1 for detailed descriptions. this is a latched input. the status of this pin will be ignore after the internal por. pwrdwn#/ tristate# 30 i tristate#/pwrdwn#: during power-up, this pin defaults to the pwrdwn# input function. this pin can be configured as the tristate# input function by control register at byte[3], bit[1]. this input can be used as the vtt_pwrgd input to support intel vrm 8.5 implementation. cpu0:1 54, 53 o cpu clock outputs: clock outputs for the host bus interface and integrated test port. output frequencies run at 66 mhz, 100 mhz, or 133 mhz, depending on the configuration of fsel0:1 and tristate#. voltage swing set by v ddq2 . sdram0:12 51, 50, 47, 46, 45, 44, 41, 40, 39, 38, 35, 34, 31 o sdram clock outputs: 3.3v outputs running to 133 mhz. sdram0:7 can be individually turned off via smbus interface. apic 1 o synchronous apic clock outputs: clock outputs running synchronous with the pci clock outputs (33 mhz). voltage swing set by v ddq2 . sdata 25 i/o data pin for smbus circuitry. sclk 24 i clock pin for smbus circuitry. vddq3 5, 9, 17, 27, 33, 37, 43, 49 p 3.3v power connection: power supply for sdram output buffers, pci output buffers, 3v66 output buffers, reference output buffers, and 48-mhz output buffers. connect to 3.3v. vdda 23 o 3.3v power connection: power supply for core logic, pll circuitry. connect to 3.3v . vddq2 2, 55 p 2.5v power connection: power supply for ioapic and cpu output buffers. con- nect to 2.5v or 3.3v. gnda 22 g ground connections: ground for core logic, pll circuitry . gnd 3, 8, 13, 18, 26, 32, 36, 42, 48, 52, 56 g ground connections: connect all ground pins to the common system ground plane.
W238-02 document #: 38-07103 rev. *a page 3 of 18 overview the w238 is a highly integrated frequency timing generator, supplying all the required clock sources for an intel architec- ture platform using graphics integrated core logic. functional description i/o pin operation ref/sel1 is a dual-purpose l/o pin. upon power-up the pin acts as a logic input. cpu clock outputs will be determined by the status of fsel0:1 input pins. an external 10-k ? strapping resistor should be used. figure 1 shows a suggested method for strapping resistor connections. after 2 ms, the pin becomes an output. assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. if the power supply has not yet reached full value, output frequency initially may be below tar- get but will increase to target once supply voltage has stabi- lized. in either case, a short output clock cycle may be pro- duced from the cpu clock outputs when the outputs are enabled. pin selectable functions table 1 outlines the device functions selectable through tristate# and fsel0:1. specific outputs available at each pin are detailed in table 2 below. notes: 1. provided for board-level ?bed of nails? testing. 2. tclk is a test clock overdriven on the xtal_in input during test mode. 3. required for dc output impedance verification. 4. ?normal? mode of operation. 5. range of reference frequency allowed is min. = 14.316 mhz, nominal = 14.31818 mhz, max. = 14.32 mhz. 6. frequency accuracy of 48 mhz must be +167 ppm to match usb default. power-on reset timer output three-state data latch hold qd w238 v dd clock load 10 k ? output buffer (load option 1) 10 k ? (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option table 2. ck solano truth table tristate# fsel1 fsel0 cpu sdram 3v66 pci 48mhz ref apic notes 0 x 0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 1 0 x 1 tclk/4 tclk/4 tclk/6 tclk/12 tclk/2 tclk tclk/12 2, 3 1 0 0 66 mhz 100 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 4, 5, 6 1 0 1 100 mhz 100 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 4, 5, 6 1 1 1 133 mhz 133mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 1, 3, 5 1 1 1 133 mhz 100 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 1, 3, 5
W238-02 document #: 38-07103 rev. *a page 4 of 18 how to use pd# input to support vtt_pwrgd the pd# input can be used to support the vtt_pwrgd sig- nal specified in the intel vrm 8.5 specification. the vtt_pwrgd is used to indicated that the frequency select output pins (bsel[0:1]) from the cpu are valid and the clock generator can use them to determine the cpu fsb frequency. the assertion of pd# input pin during initial power-up will delay the start of the pll, keep all the multiplexed i/o pins as input and keep all the output inactive. the functionality of pd# will allow the system designer to use this input to support the vtt_pwrgd output from the vrm 8.5 module. please refer to the figure 2 for power-up sequence details. 3.3v & 2.5v pd# (connected to vtt_pwrgd) outputs input latch (pin 4 & pin21) 1 ms pll & output synchronization figure 2. power-up sequence with pd# (vtt_pwrgd) hold low
W238-02 document #: 38-07103 rev. *a page 5 of 18 offsets among clock signal groups figure 3 and figure 4 represent the phase relationship among the different groups of clock outputs from w238 when it is pro- viding a 66-mhz cpu clock and a 100-mhz cpu clock, re- spectively. it should be noted that when cpu clock is operating at 100 mhz, cpu clock output is 180 degrees out of phase with sdram clock outputs. cpu 66-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz apic 33-mhz 0 ns cpu 66 period sdram 100 period hub-pci figure 3. group offset waveforms (66-mhz cpu/100-mhz sdram) 40 ns 30 ns 20 ns 10 ns cpu 100-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz apic 33-mhz 0 ns sdram 100 period cpu 100 period hub-pci figure 4. group offset waveforms (100-mhz cpu/100-mhz sdram) 40 ns 30 ns 20 ns 10 ns
W238-02 document #: 38-07103 rev. *a page 6 of 18 cpu 133-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeats apic 33-mhz figure 5. group offset waveforms (133-mhz cpu/100-mhz sdram) 0 ns 40 ns 30 ns 20 ns 10 ns cpu 100-mhz sdram 133-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz apic 3-3mhz cycle repeat figure 6. group offset waveform (133-mhz cpu/133-mhz sdram) 0 ns 40 ns 30 ns 20 ns 10 ns
W238-02 document #: 38-07103 rev. *a page 7 of 18 power down control w238 provides one pwrdwn# signal to place the device in low-power mode. in low-power mode, the plls are turned off and all clock outputs are driven low. notes: 7. once the pwrdwn# signal is sampled low for two consecutive rising edges of cpu, clocks of interest will be held low on the ne xt high-to-low transition. 8. pwrdwn# is an asynchronous input and metastable conditions could exist. this signal is synchronized inside w238. 9. the shaded sections on the sdram, ref, and usb clocks indicate ?don?t care? states. 10. diagrams shown with respect to 100 mhz. similar operation when cpu is 66 mhz. table 3. w238 maximum allowed current w238 condition max. 2.5v supply consumption max. discrete cap loads, v ddq2 = 2.625v all static inputs = v ddq3 or v ss max. 3.3v supply consumption max. discrete cap loads v ddq3 = 3.465v all static inputs = v ddq3 or v ss powerdown mode (pwrdwn# = 0) 100 a500 a full active 66 mhz fsel1:0 = 00 (pwrdwn# =1) 30 ma 280 ma full active 100 mhz fsel1:0 = 01 (pwrdwn# =1) 40 ma 280 ma full active 133 mhz fsel1:0 = 10, 11 (pwrdwn# =1) 50 ma 400 ma 1 2 center 0ns 25ns 50ns 75ns vco internal cpu 100mhz 3v66 66mhz pci 33mhz apic 33mhz pwrdwn sdram 100mhz ref 14.318mhz usb 48mhz figure 7. w238 pwrdwn# timing diagram [7, 8, 9, 10]
W238-02 document #: 38-07103 rev. *a page 8 of 18 spread spectrum frequency timing generator the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 8 . as shown in figure 8 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 9 . this waveform, as discussed in ?spread spectrum clock generation for the reduction of radiated emissions? by bush, fessler, and hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is ?0.5% of the selected fre- quency. figure 9 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. spread spectrum clocking is activated or deactivated by se- lecting the appropriate value for bit 3 in data byte 0 of the smbus data stream. refer to page 10 for more details. figure 8. clock harmonic with and without sscg modulation frequency domain representation spread spectrum enabled emi reduction spread spectrum non- max. min. 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 9. typical modulation profile
W238-02 document #: 38-07103 rev. *a page 9 of 18 serial data interface the w238 features a two-pin, serial data interface that can be used to configure internal register settings that control partic- ular device functions. data protocol the clock driver serial protocol accepts only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. indexed bytes are not allowed. a block write begins with a slave address and a write condition. after the command code the core logic issues a byte count which describes how many more bytes will follow in the mes- sage. if the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count may not be 0. a block write command is allowed to transfer a maximum of 32 data bytes. the slave receiver ad- dress for w238 is 11010010. figure 10 shows an example of a block write. the command code and the byte count bytes are required as the first two bytes of any transfer. w238 expects a command code of 0000 0000. the byte count byte is the number of ad- ditional bytes required for the transfer, not counting the com- mand code and byte count bytes. additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. table 4 shows an example of a possible byte count value. a transfer is considered valid after the acknowledge bit corre- sponding to the byte count is read by the controller. the com- mand code and byte count bytes are ignored by the w238. however, these bytes must be included in the data write se- quence to maintain proper byte allocation. notes: 11. the acknowledgment bit is returned by the slave/receiver (w238). 12. data bytes 3 to 7 are reserved. 1 bit 7 bits 1 1 8 bits 1 start bit slave address r/w ack command code ack byte count = n ack data byte 1 ack data byte 2 ack ... data byte n ack stop 1 bit 8 bits 1 8 bits 1 8 bits 1 1 figure 10. an example of a block write [11] table 4. example of possible byte count value byte count byte notes msb lsb 0000 0000 not allowed. must have at least one byte 0000 0001 data for functional and frequency select register (currently byte 0 in spec) 0000 0010 reads first two bytes of data. (byte 0 then byte 1) 0000 0011 reads first three bytes (byte 0, 1, 2 in order) 0000 0100 reads first four bytes (byte 0, 1, 2, 3 in order) 0000 0101 reads first five bytes (byte 0, 1, 2, 3, 4 in order) [12] 0000 0110 reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order) [12] 0000 0111 reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) 0010 0000 max. byte count supported = 32 table 5. serial data interface control functions summary control function description common application output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and sys- tem power. examples are clock outputs to unused pci slots. spread spectrum enabling enables or disables spread spectrum clocking. for emi reduction. (reserved) reserved function for future device revision or production device testing. no user application. register bit must be written as 0.
W238-02 document #: 38-07103 rev. *a page 10 of 18 w238 serial configuration map 1. the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 2. all unused register bits (reserved and n/a) should be writ- ten to a ?0? level. 3. all register bits labeled ?initialize to 0" must be written to zero during initialization. failure to do so may result in high- er than normal operating current. the controller will read back the written value. notes: notes: 13. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 14. spread spectrum percentage is ?0.5%. byte 0: control register (1 = enable, 0 = disable) [13] bit pin# name default pin function bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 - spread spectrum (1 = on/0 = off) [14] 0 (disabled/enabled) bit 2 29 dot 1 (active/inactive) bit 1 28 usb 1 (active/inactive) bit 0 - reserved 0 reserved byte 1: control register (1 = enable, 0 = disable) [13] bit pin# name default pin description bit 7 40 sdram7 1 (active/inactive) bit 6 41 sdram6 1 (active/inactive) bit 5 44 sdram5 1 (active/inactive) bit 4 45 sdram4 1 (active/inactive) bit 3 46 sdram3 1 (active/inactive) bit 2 47 sdram2 1 (active/inactive) bit 1 50 sdram1 1 (active/inactive) bit 0 51 sdram0 1 (active/inactive) byte 2: control register (1 = enable, 0 = disable) bit pin# name default pin description bit 7 12 3v66_agp 1 (active/inactive) bit 6 31 sdram12 1 (active/inactive) bit 5 34 sdram11 1 (active/inactive) bit 4 35 sdram10 1 (active/inactive) bit 3 38 sdram9 1 (active/inactive) bit 2 39 sdram8 1 (active/inactive) bit 1 15 pci1 1 (active/inactive) bit 0 -- reserved 1 (active/inactive)
W238-02 document #: 38-07103 rev. *a page 11 of 18 byte 3: reserved register (1 = enable, 0 = disable) bit pin# name default pin description bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 -- reserved 0 reserved bit 2 -- reserved 0 reserved bit 1 30 pwrdwn#/ tristate# 1 1 = pwrdwn# 0 = tristate# bit 0 -- sdram 133 mode enable disabled =?0?, enabled =?1? 0 (disabled/enabled) byte 4: reserved register (1 = enable, 0 = disable) bit pin# name default pin function bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 - reserved 0 reserved bit 2 20 pci4 1 active/inactive bit 1 19 pci3 1 active/inactive bit 0 16 pci2 1 active/inactive byte 5: reserved register (1 = enable, 0 = disable) bit pin# name default pin description bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 - reserved 0 reserved bit 2 - reserved 0 reserved bit 1 - reserved 0 reserved bit 0 - reserved 0 reserved byte 6: reserved register (1 = enable, 0 = disable) bit pin# name default pin description bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 - reserved 0 reserved bit 2 - reserved 0 reserved bit 1 - reserved 0 reserved bit 0 - reserved 0 reserved
W238-02 document #: 38-07103 rev. *a page 12 of 18 dc electrical characteristics [15] absolute maximum dc power supply parameter description min. max. unit v dd3 3.3v core supply voltage ?0.5 4.6 v v ddq2 2.5v i/o supply voltage ?0.5 3.6 v v ddq3 3.3v supply voltage ?0.5 4.6 v t s storage temperature ?65 150 c absolute maximum dc i/o parameter description min. max. unit v ih3 3.3v input high voltage ?0.5 4.6 v v il3 3.3v input low voltage ?0.5 v esd prot. input esd protection 2000 v dc operating requirements parameter description condition min. typ. max. unit v dd3 3.3v core supply voltage 3.3v 5% 3.135 3.465 v v ddq3 3.3v i/o supply voltage 3.3v 5% 3.135 3.465 v v ddq2 2.5v i/o supply voltage 2.5v 5% 2.375 2.625 v v dd3 = 3.3v5% v ih3 3.3v input high voltage v dd3 2.0 v dd + 0.3 v v il3 3.3v input low voltage v ss ? 0.3 0.8 v i il input leakage current [16] 0 W238-02 document #: 38-07103 rev. *a page 13 of 18 i ol output low current pci0:7 v ol = 1.5v 20 40 90 ma ref2x/fs3 v ol = 1.5v 20 40 90 ma 48 mhz v ol = 1.5v 20 40 90 ma 24 mhz v ol = 1.5v 20 40 90 ma sdram0:12 v ol = 1.5v 60 100 160 ma cpu0:1 v ol = 1.25v 25 50 95 ma i oh output high current pci0:7 v oh = 1.5v 20 40 90 ma ref2x/fs3 v oh = 1.5v 20 40 90 ma 48 mhz v oh = 1.5v 20 40 90 ma 24 mhz v oh = 1.5v 20 40 90 ma sdram0:12 v oh = 1.5v 60 100 160 ma cpu0:1 v oh = 1.25v 25 50 95 ma dc operating requirements (continued) parameter description condition min. typ. max. unit
W238-02 document #: 38-07103 rev. *a page 14 of 18 ac electrical characteristics [15] t a = 0c to +70c, v ddq3 = 3.3v 5%, v ddq2 = 2.5v 5% f xtl = 14.31818 mhz spread spectrum function turned off ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. [17] notes: 17. period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5v clocks and at 1.5v for 3.3v clocks. 18. the time specified is measured from when v ddq3 achieves its nominal operating level (typical condition v ddq3 = 3.3v) until the frequency output is stable and operating within specification. 19. t rise and t fall are measured as a transition through the threshold region v ol = 0.4v and v oh = 2.0v (1 ma) jedec specification. 20. t low is measured at 0.4v for all outputs. 21. t high is measured at 2.0v for 2.5v outputs, 2.4v for 3.3v outputs. parameter description 66.6-mhz host 100-mhz host 133-mhz host unit notes min. max. min. max. min. max. t period host/cpuclk period 15.0 15.5 10.0 10.5 7.5 8.0 ns 17 t high host/cpuclk high time 5.2 n/a 3.0 n/a 1.87 n/a ns 18 t low host/cpuclk low time 5.0 n/a 2.8 n/a 1.67 n/a ns 19 t rise host/cpuclk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns t fall host/cpuclk fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns t period sdram clk period 10.0 10.5 10.0 10.5 10.0 10.5 ns 17 t high sdram clk high time 3.0 n/a 3.0 n/a 3.0 n/a ns 18 t low sdram clk low time 2.8 n/a 2.8 n/a 2.8 n/a ns 19 t rise sdram clk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns t fall sdram clk fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns t period apic 33-mhz clk period 30.0 n/a 30.0 n/a 30.0 n/a ns 17 t high apic 33-mhz clk high time 12.0 n/a 12.0 n/a 12.0 n/a ns 18 t low apic 33-mhz clk low time 12.0 n/a 12.0 n/a 12.0 n/a ns 19 t rise apic clk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns t fall apic clk fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns t period 3v66 clk period 15.0 16.0 15.0 16.0 15.0 16.0 ns 17, 20 t high 3v66 clk high time 5.25 n/a 5.25 n/a 5.25 n/a ns 18 t low 3v66 clk low time 5.05 n/a 5.05 n/a 5.05 n/a ns 19 t rise 3v66 clk rise time 0.5 2.0 0.5 2.0 0.5 2.0 ns t fall 3v66 clk fall time 0.5 2.0 0.5 2.0 0.5 2.0 ns t period pci clk period 30.0 n/a 30.0 n/a 30.0 n/a ns 17, 21 t high pci clk high time 12.0 n/a 12.0 n/a 12.0 n/a ns 18 t low pci clk low time 12.0 n/a 12.0 n/a 12.0 n/a ns 19 t rise pci clk rise time 0.5 2.0 0.5 2.0 0.5 2.0 ns t fall pci clk fall time 0.5 2.0 0.5 2.0 0.5 2.0 ns tp zl , tp zh output enable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns tp lz , tp zh output disable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns t stable all clock stabilization from power-up 33 3ms
W238-02 document #: 38-07103 rev. *a page 15 of 18 intel is a registered trademark of intel corporation group skew and jitter limits output group pin-pin skew max. cycle-cycle jitter duty cycle nom vdd skew, jitter measure point typical output impedance cpu 175 ps 250 ps 45/55 2.5v 1.25v 31 ? sdram 250 ps 250 ps 45/55 3.3v 1.5v 22 ? apic 250 ps 500 ps 45/55 2.5v 1.25v 21 ? 48mhz 250 ps 500 ps 45/55 3.3v 1.5v usb 31 ? dot 22 ? 3v66 175 ps 500 ps 45/55 3.3v 1.5v 31 ? pci 500 ps 500 ps 45/55 3.3v 1.5v 31 ? ref n/a 1000 ps 45/55 3.3v 1.5v 21 ? clock output wave 2.5v clocking 3.3v clocking test point test load t period duty cycle t high 2.0 1.25 0.4 t low t rise t fall t low t rise t fall t period duty cycle t high 2.4 1.5 0.4 output buffer interface interface figure 11. output buffer ordering information ordering code package name package type W238-02 h 56-pin ssop (300 mils)
W238-02 document #: 38-07103 rev. *a page 16 of 18 layout diagram 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 6 7 13 19 20 24 g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors g +2.5v supply 1 2 3 4 5 8 9 11 12 14 15 16 17 22 23 21 25 26 27 28 40 39 18 41 10 31 30 29 36 35 34 33 32 37 38 c1 c2 g v fb +3.3v supply c4 c1 & c3 = 10?22 f c2 & c4 = 0.005 f 10 f fb c1 c2 0.005 f fb = dale ilb1206 - 300 (300 ? @ 100 mhz) 0.005 f g g g g vddq2 vddq3 c3 c5 = 10 f c6 = 0.1 f g g 10 ? vddq3 c5 c6 g v g v g v g v g v g v g v g v g v vddq2 vddq3 vddq3 vddq3 vddq3 core vddq3 vddq3 w238 vddq2 vddq3 vddq3 g g g g g g g g g g g g g g g g g g g g 10 f ceramic caps
W238-02 document #: 38-07103 rev. *a page 17 of 18 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 56-pin shrink small outline package (ssop, 300 mils) summary of nominal dimensions in inches: body width: 0.296 lead pitch: 0.025 body length: 0.625 body height: 0.102
W238-02 document #: 38-07103 rev. *a page 18 of 18 document title: W238-02 ftg for integrated core logic w/ 133 mhz fsb document number: 38-07103 rev. ecn no. issue date orig. of change description of change ** 107459 08/08/01 ika new data sheet *a 122782 12/26/02 rbi add power up requirements to ac/dc electrical characteristics information.

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