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  1 ?2001 by catalyst semiconductor, inc. characteristics subject to change without notice features  two 8-bit dpps configured as programmable voltage sources in dac-like applications  common reference inputs  non-volatile nvram memory wiper storage  output voltage range includes both supply rails  2 independently addressable buffered output wipers  1 lsb accuracy, high resolution  serial microwire-like interface  single supply operation: 2.7v-5.5v  setting read-back without effecting outputs applications  automated product calibration.  remote control adjustment of equipment  offset, gain and zero adjustments in self- calibrating and adaptive control systems.  tamper-proof calibrations.  dac (with memory) substitute description the cat523 is a dual, 8-bit digitally-programmable potentiometer (dpp) configured for programmable voltage and dac-like applications. intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. the two independently programmable dpps have a common output voltage range which includes both supply rails. the wipers are buffered by rail to rail op amps. wiper settings, stored in non-volatile nvram memory, are not lost when the device is powered down and are automatically reinstated when power is returned. each wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the dpp? output. control of the cat523 is accomplished with a simple 3 wire, microwire-like serial interface. a chip select pin allows several cat523's to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the cat523? tri- stated data output pin. a rdy/ bsy output working in concert with an internal low voltage detector signals proper operation of non-volatile nvram memory erase/ write cycle. the cat523 is available in the 0 to 70 c commercial and ?0 c to + 85 c industrial operating temperature ranges and offered in 14-pin plastic dip and soic mount packages. functional diagram pin configuration cat523 configured digitally programmable potentiometer (dpp): programmable voltage applications dip package (p) soic package (j) cat523 doc. no. 2005, rev. a rdy/ bsy clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v refh v out1 v out2 v refl clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v refh v out1 v out2 v refl cat 523 cat 523 rdy/ bsy nc nc nc nc rdy/bsy prog program control di cs clk serial control serial data output register gnd v dd 14 7 5 2 4 v 13 12 ou t2 out1 v 6 do 8 9 31 + + v refh v refl 28k ? 28k ? wiper control register and nvram
cat523 2 doc. no. 2005, rev. a i dd1 supply current (read) normal operating 400 600 a i dd2 supply current (write) programming, v dd = 5v 1600 2500 a v dd = 3v 1000 1600 a v dd operating voltage range 2.7 5.5 v absolute maximum ratings supply voltage* v dd to gnd ?.5v to +7v inputs clk to gnd ?.5v to v dd +0.5v cs to gnd ?.5v to v dd +0.5v di to gnd ?.5v to v dd +0.5v rdy/bsy to gnd ?.5v to v dd +0.5v prog to gnd ?.5v to v dd +0.5v v ref h to gnd ?.5v to v dd +0.5v v ref l to gnd ?.5v to v dd +0.5v outputs d 0 to gnd ?.5v to v dd +0.5v v out 1?4 to gnd ?.5v to v dd +0.5v operating ambient temperature commercial (??or blank suffix) 0 c to +70 c industrial (??suffix) ?40 c to +85 c junction temperature +150 c storage temperature ?5 c to +150 c lead soldering (10 sec max) +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. power supply reliability characteristics symbol parameter min max units test method v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(2) latch-up 100 ma jedec standard 17 notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc + 1v. i ih input leakage current v in = v dd 10 a i il input leakage current v in = 0v -10 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v logic inputs v oh high level output voltage i oh = -40 av dd -0.3 v v il low level output voltage i ol = 1 ma, v dd = +5v 0.4 v i ol = 0.4 ma, v dd = +3v 0.4 v logic outputs
cat523 3 doc. no. 2005, rev. a potentiometer characteristics v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified symbol parameter conditions min typ max units r pot potentiometer resistance 28k ? r pot to r pot match +0.5 +1 % pot resistance tolerance +15 % voltage on v refh pin 2.7 v dd v voltage on v refl pin ov v dd - 2.7 v resolution 0.4 % inl integral linearity error 0.5 1 lsb dnl differential linearity error 0.25 0.5 lsb r out buffer output resistance 10 ? i out buffer output current 3 ma tc rpot tc of pot resistance 300 ppm/?c tc ratio ratiometric tc ppm/?c r iso isolation resistance ? v n noise nv/ hz c h /c l potentiometer capacitances 8/8 pf fc frequency response passive attenuator mhz ac electrical characteristics: v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified symbol parameter conditions min typ max units digital t csmin minimum cs low time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t dis di setup time 50 ns t dih di hold time 50 ns t do1 output delay to 1 150 ns t do0 output delay to 0 150 ns t hz output delay to high-z 400 ns t lz output delay to low-z 400 ns t busy erase/write cycle time 4 5 ms t ps prog setup time 150 ns t prog minimum pulse width 700 ns t clk h minimum clk high time 500 ns t clk l minimum clk low time 300 ns f c clock frequency dc 1 mhz analog t ds dpp settling time to 1 lsb c load = 10 pf, v dd = +5v 3 10 s c load = 10 pf, v dd = +3v 6 10 s notes: 1. all timing measurements are defined at the point of signal crossing v dd / 2. 2. these parameters are periodically sampled and are not 100% tested. cl=100pf, see note 1
cat523 4 doc. no. 2005, rev. a a. c. timing diagram t o 1 2 3 4 5 clk cs di do prog t h clk t l clk t csh t css t csmin t dis t dih t do0 t lz t do1 t hz rdy/bsy t prog t ps t o 1 2 3 4 5 t busy
cat523 5 doc. no. 2005, rev. a dpp addressing is as follows: dpp output a0 a1 v out1 0 0 v out2 1 0 pin description pin name function 1v dd power supply positive. 2 clk clock input pin.clock input pin. 3 rdy/ bsy ready/busy output 4 cs chip select 5 di serial data input pin. 6 do serial data output pin. 7 prog eeprom programming enable input 8 gnd power supply ground. 9v refl minimum dpp output voltage. 10 nc no connect. 11 nc no connect. 12 v out2 dpp output channel 2. 13 v out1 dpp output channel 1. 14 v refh maximum dpp output voltage. device operation the cat523 is a dual 8-bit configured digitally programmable potentiometer (dpp) whose outputs can be programmed to any one of 256 individual voltage steps. once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. upon power up the dpps return to the settings stored in non-volatile memory. each dpp can be written to and read from independently without effecting the output voltage during the read or write cycle. each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. digital interface the cat523 employs a 3 wire, microwire-like, serial control interface consisting of clock (clk), chip select (cs) and data in (di) inputs. for all operations, address and data are shifted in lsb first. in addition, all digital data must be preceded by a logic ??as a start bit. the dpp address and data are clocked into the di pin on the clock? rising edge. when sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. multiple devices may share a common input data line by selectively activating the cs control of the desired ic. data outputs (do) can also share a common line because the do pin is tri-stated and returns to a high impedance when not in use. chip select chip select (cs) enables and disables the cat523? read and write operations. when cs is high data may be read to or from the chip, and the data output (do) pin is active. data loaded into the dpp control registers will remain in effect until cs goes low. bringing cs to a logic low returns all dpp outputs to the settings stored in non- volatile memory and switches do to its high impedance tri-state mode. because cs functions like a reset the cs pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. clock the cat523? clock controls both data flow in and out of the ic and non-volatile memory cell programming. serial data is shifted into the di pin and out of the do pin on the clock? rising edge. while it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the dpp wiper control register. no clock is necessary upon system power-up. the cat523? internal power-on reset circuitry loads data from non-volatile memory to the dpps without using the external clock. as data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. standard cmos and ttl logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit.
cat523 6 doc. no. 2005, rev. a followed by a two bit dpp address and eight data bits are clocked into the dpp control register via the di pin. data enters on the clock? rising edge. the dpp output changes to its new setting on the clock cycle following d7, the last data bit. programming is achieved by bringing prog high for a minimum of 3 ms. prog must be brought high some- time after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the d7 bit. two clock cycles after the d7 bit the dac control register will be ready to receive the next set of address and data bits. the clock must be kept running through- out the programming cycle. internal control circuitry takes care of ramping the programming voltage for data transfer to the non-volatile memory cells. the cat523? non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 100 years without being refreshed. reading data each time data is transferred into a dpp wiper control register currently held data is shifted out via the d0 pin, thus in every data transaction a read cycle occurs. note, however, that the reading process is destructive. data must be removed from the register in order to be read. figure 2 depicts a read only cycle in which no change occurs in the dpp? output. this feature allows ps to poll dpps for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. in figure 2 cs returns low before the 13 th clock cycle completes. in doing so the non-volatile memory setting is reloaded into the dpp wiper control register. v ref v ref , the voltage applied between pins v refh andv refl , sets the dpp? zero to full scale output range where v refl = zero and v refh = full scale. v ref can span the full power supply range or just a fraction of it. in typical applications v refh andv refl are connected across the power supply rails. when using less than the full supply voltage v refh is restricted to voltages between v dd and v dd /2 and v refl to voltages between gnd and v dd /2. ready /busy /busy /busy /busy /busy when saving data to non-volatile memory, the ready/ busy output (rdy/ bsy ) signals the start and duration of the non-volatile erase/write cycle. upon receiving a command to store data (prog goes high) rdy/ bsy goes low and remains low until the programming cycle is complete. during this time the cat523 will ignore any data appearing at di and no data will be output on do. rdy/ bsy is internally anded with a low voltage detector circuit monitoring v dd. if v dd is below the minimum value required for non-volatile programming, rdy/ bsy will remain high following the program command indicating a failure to record the desired data in non-volatile memory. data output data is output serially by the cat523, lsb first, via the data out (do) pin following the reception of a start bit and two address bits by the data input (di). do becomes active whenever cs goes high and resumes its high impedance tri-state mode when cs returns low. tri-stating the do pin allows several 523s to share a single serial data line and simplifies interfacing multiple 523s to a microprocessor. writing to memory programming the cat523? non-volatile memory is accomplished through the control signals: chip select (cs) and program (prog). with cs high, a start bit figure 2. reading from memory figure 1. writing to memory rdy/bsy new dpp data current dpp data dpp value dpp value dpp value dpp output a0 a1 1 do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 o current dpp value non-volatile d0 d1 d2 d3 d4 d5 d6 d7 current dpp data
cat523 7 doc. no. 2005, rev. a cat523 gnd v dd v refh v refl control & data + op 07 v = ( ) -v out r f r + i -15v +15v +5v rr i f r i i r f v dpp for r = i r f v = 2v -v out i dpp v i v out application circuits since this value is the same as that which had been there previously no change in the dpp? output is noticed. had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle? conclusion. temporarily change output the cat523 allows temporary changes in dpp? output to be made without disturbing the settings retained in non-volatile memory. this feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. figure 3 shows the control and data signals needed to effect a temporary output change. dpp wiper settings may be changed as many times as required and can be made to any of the two dpps in any order or sequence. the temporary setting(s) remain in effect long as cs remains high. when cs returns low all two dpps will return to the output values stored in non-volatile memory. when it is desired to save a new setting acquired using figure 3. temporary change in output this feature, the new value must be reloaded into the dpp wiper control register prior to programming. this is because the cat523? internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no prog signal is received. d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o current dpp value non-volatile new dpp value volatile current dpp value non-volatile bipolar dpp output msb lsb 1111 1111 (.98 v ) + .01 v = .990 v v = +4.90v 1000 0000 (.98 v ) + .01 v = .502 v v = +0.02v 0111 1111 (.98 v ) + .01 v = .498 v v = -0.02v 0000 0001 (.98 v ) + .01 v = .014 v v = -4.86v 0000 0000 (.98 v ) + .01 v = .010 v v = -4.90v ref ref ref if v = 5v ref 255 255 out dpp input dpp output analog r = r output ref ref ref out 128 255 127 255 ref ref ref out 1 255 ref ref ref out ref ref ref out 0 255 v = 0.99 v fs ref v = 0.01 v zero ref v = (v - v ) + v dpp code 255 fs zero zero amplified dpp output cat523 gnd v dd v refh v refl control & data + op 07 v out -15v +15v +5v rr i f v = (1 + ) v out dpp r f r i
cat523 8 doc. no. 2005, rev. a application circuits (cont.) coarse-fine offset control by averaging dpp outputs for single power supply systems coarse-fine offset control by averaging dpp outputs for dual power supply systems + fine adjust dpp coarse adjust dpp gnd v refl v re h f v dd r c 127r c +v +5v +v ref -v -v ref r o r = c 1 a offset v offset ref (+v ) - (v ) r = o 1 a offset ref (-v ) + (v ) + + digitally trimmed voltage reference digitally controlled voltage reference cat523 lt 1029 i > 2 ma v+ gnd v dd v = 5.000v ref v refh v refl control & data cat523 gnd v dd v refh v refl control & data + 15k 10 f 5.1v 10k 4.02 k 1.00k 10 f 35v lm 324 1n5231b mpt3055el 28 - 32v output 0 - 25v @ 1a + fine adjust dpp coarse adjust dpp gnd v refl v refh v dd r c 127r c +v +5v v ref r = c 256 1 a v ref * fine adjust gives 1 lsb change in v when v = offset v ref 2 offset v offset
cat523 9 doc. no. 2005, rev. a application circuits (cont.) current sink with 4 decades of resolution current source with 4 decades of resolution gnd v refl v dd v refh +5v dpp + cat523 control & data dpp + 10k 10k 39 ? 1w lm385-2.5 5 a steps i = 2 - 255 ma sink 2n7000 10k 10k tip 30 39 ? 1w 5 meg 5 meg 3.9k + -15v 2n7000 +5v +15v 4.7 a 1 ma steps 2.2k gnd v refl v dd v refh +5v dpp + control & data dpp + 5 meg 5 meg 39 1w 39 1w 5 meg 5 meg 3.9k lm385-2.5 -15v 5 a steps i = 2 - 255 ma source 1 ma steps + 10k 10k +15v tip 29 bs170p bs170p 51k ? ? cat523
cat523 10 doc. no. 2005, rev. a ordering information notes: (1) the device used in the above example is a cat523ji-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 523 j product number package p: pdip j: soic cat optional company id i temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) -te13 tape & reel te13: 2000/reel copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 2005 revison: a issue date: 08/02/01 type: final


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