1 4732a?clock?06/03 features 32-khz voltage regulated oscillator 1.1 v to 2.2 v operating-voltage range integrated capacitors for digital trimming suitable for up to 12.5 pf quartz trimming inputs insenitive to stray capacitance output pulse formers mask options for motor period and pulse width low resistance output for bipolar stepping motor motor fast-test function description the E1467D is an integrated circuit in cmos silicon gate technology for analog clocks. it consists of a 32-khz oscillator, frequency divider, output pulse formers, push-pull motor drivers and alarm output. integrated capacitors are mask-selectable to accomodate the external quartz crystal. additional capacitance can be selected through pad bonding to trimming the oscillator frequency. 32-khz clock cmos ic with digital trimming and alarm E1467D
2 E1467D 4732a?clock?06/03 pad configuration figure 1. pad configuration vdd (1) vss 2 8 6 5 7 E1467D 1 9 13 12 11 10 4 3 alin / mot1l (2) oscin oscout (1) alout mot2 mot1r sc4 sc3 sc2 sc1 mtest (2) (1) the pads vdd and oscout are interchangeable per mask option (2) the pads for alin/-mtest and mot1l are interchangeable per mask option pin description name description vdd positive supply voltage vss negative supply voltage oscin oscillator input oscout oscillator output mot1/2 motor drive outputs alin alarm input alout alarm output sc1 ... sc4 oscillator trimming inputs
3 E1467D 4732a?clock?06/03 functional descripion oscillator an oscillator inverter with feedback resistor is provided to generate the 32768 hz clock fre- quency. values for the fixed capacitors at oscin and oscout are mask-selectable (see note 3 of ?operating characteristics?). four control inputs, sc1 to sc4, enable the users to add integrated trimming capacitors to oscin and oscout, providing 15 tuning steps. a frequency variation of typically 4 ppm for each tuning step is obtained by bonding the capac- itor pads to oscin. as none of these pads are bonded, the ic is in an untrimmed state. figure 2 shows the trimming curve characteristic. note: for applications which utilize this integrated trimming feature, atmel will determine optimum val- ues for the integrated capacitors c oscin and c oscout . motor drive output the E1467D contains two push-pull output buffers for driving bipolar stepping motors. during a motor pulse, the n-channel device of one buffer and the p-channel device of the other buffer will be activated. both n-channel transistors are on and conducting between output pulses. the outputs are protected against inductive voltage spikes with diodes to both supply pins. the motor output period and pulse width are mask-programmable, as listed below: available motor periods (t m ): 125, 250, 500 ms and 2, 16 s available maximum pulse widths (t m ): 15, 6, 23.4, 31.25, 46.9 ms available motor periods for motor test (t mt ): 250, 500 ms and 1 s note: the following constraints for combination of motor period and pulse widths have to be consid- ered: t m > 4 t m , t mt > 4 t m or alternatively t m = 2 t m , t mt = 2 t m alarm outputs the alarm output driver consists of a push-pull stage for driving a speaker via an external bipo- lar transistor. the output is configured for npn and pnp bipolar capability. the output is an alarm tone, modulated by a low frequency. tone frequencies, modulation frequencies, and on/off times are selectable via the metal mask option. alarm input a debounced alarm input is provided. alarm activation is connected either to v dd or v ss by a mask option. test functions for test purposes, the test pad is open. with a high resistance probe (r 10 m , c 20 pf), a test frequency f test of 128 hz can be measured at the alin/mtest pad. con- necting alin/mtest (for at least 32 ms) to the opposite polarity for alarm activation changes the motor period from the selected value to t mt (mask-selectable) while the pulse width remains unaffected. this feature can be used for testing the mechanical parts of the clock.
4 E1467D 4732a?clock?06/03 figure 2. functional test test crystal specification s c 4 s c 3 s c 2 s c 1 E1467D mot1l alin/ oscin oscout alout mot2 mot1r r 3 r 2 vdd vss r 1 1 2 3 45 6 7 8 9 10 11 12 13 vss vdd -mt oscillation frequency f osc = 32768 hz series resistance r s = 30 k static capacitance c 0 = 1.5 pf dynamic capacitance c 1 = 3.0 ff load capacitance c l optionally 10 or 12.5 pf absolute maximum ratings absolute maximum ratings define parameter limits which, if exceeded, may permanently change or damage the device. all inputs and outputs on atmel?s circuits are protected against electrostatic discharges. however, precautions to minimize the build-up of electrostatic charges during handling are recommended. the circuit is protected against supply voltage reversal for typically 5 minutes. parameters symbol value unit supply voltage v ss -0.3 to 5 v v input voltage range, all inputs v in (v ss - 0.3 v) v in (v dd + 0.3 v) v output short circuit duration indefinite power dissipation (dil package) p tot 125 mw operating ambient temperature range t amb -20 to +70 c storage temperature range t stg -40 to +125 c lead temperature during soldering at 2 mm distance, 10 s t sld 260 c
5 E1467D 4732a?clock?06/03 notes: 1. typical parameters represent the statistical mean values 2. see test circuit 3. values can be selected in 1 pf steps. a total capacitance (c oscin + c oscout ) of 38 pf is available 4. npn or pnp driving transistors defined by mask options 5. i scinh is the peak current of a pulsed current with a duty cycle of 1:63. average current is always smaller than 10 na operating characteristics v ss = 0 v, v dd = 1.5 v, t amb = +25c, unless otherwise specified. all voltage levels are measured with reference to v ss . test crystal as specified below. parameters test conditions symbol min. typ. max. unit operating voltage v dd 1.1 1.5 2.2 v operating temperature t amb -20 +70 c operating current r 1 = (2) i dd 1 3 a motor drive output motor output current v dd = 1.2 v, r 1 = 200 i m 4.3 ma motor period t m see option list s motor period during motor test t mt see option list ms motor pulse width t m see option list ms oscillator start-up voltage within 2 s v start 1.2 2.2 v frequency stability v dd =100mv, v dd = 1.1 to 2.2 v f/f 0.1 0.2 ppm integrated input capacitance (3) c oscin see option list pf integrated output capacitance c oscout see option list pf input current sc1 to sc4 v in =0.2v v in =v dd (5) i scinl i scinh 1 0.05 5 0.15 25 0.5 a a alarm/output output current for driving npn transistor v dd =1.2v n-channel r 3 =100k i ann 1 3 10 a p-channel r 2 =1k (2)(4) i anp -0.5 -1 ma output current for driving pnp-transistor v dd =1.2v n-channel r 3 =1k i apn 0.5 1 ma p-channel r 2 =100k (2)(4) i app -1 -2 -10 a alarm options tone frequency f a see option list hz modulation frequency f mod see option list hz on/off time t on /t off see option list s alarm input/motor test input current alin = v dd , peak current i ainh 0.6 3 10 a input current alin = v ss , peak current i ainl -0.6 -3 -10 a input debounce delay t ain 23.4 31.2 ms
6 E1467D 4732a?clock?06/03 figure 3. motor output signal during normal operation and during motor test figure 4. alarm operation motor output signal during normal mode and motortest alin/ mt mot1 vss vdd mot2 t m 1/f test a detail a: t m t mt vss vdd vss vdd 1/f a 1/f mod vdd vss detail b: alarm output signal t on alout signal on alarm input and alarm output during alarm activation b alin / mtest t < t ain t off vdd vss vdd vss t > t ain t < t v4 t > t v4
7 E1467D 4732a?clock?06/03 figure 5. typical trimming curve characteristic for t m of 2 s c ox means frequency deviation due to production process variations. trimming inputs sc1 ... sc4 are binary weighted, i.e., sc1 ... sc4 = 0 corresponds to trimming step 0 sc1 ... sc4 = 1 corresponds to trimming step 15 lsb = sc1 1.99991 1.99992 1.99993 1.99994 1.99995 1.99996 1.99997 1.99998 1.99999 2.00000 2.00001 2.00002 2.00003 2.00004 2.00005 2.00006 0 1234567891011121314 trimming step motor period (s) cox = 1.05 cox = 1.00 cox = 0.95
8 E1467D 4732a?clock?06/03 ordering information note: 1. on-chip stray capacitance included table 1. option list E1467D option motor alarm load cap. integrated capacitance cycle (t m ) s pulse (t m ) ms test (t mt ) ms frequency hz modulation frequency hz on/off time s driver type activation polarity pf c oscin (1) pf c oscout (1) pf -b 2 23.4 250 2048 8 0.5/0.5 npn v ss 10 17 12 -d 2 31.25 250 2048 8 0.5/0.5 npn v dd 10 17 12 -v2 0.5 23.4 250 2048 8 0.5/0.5 npn v ss 12.5 20 16 e2 2 46.9 250 2048 8 1/3 npn v ss 12.5 20 16 option pad designation pad 1 pad 2 pad 3 pad 4 pad 5 pad 6 pad 7 pad 8 pad 9 pad 10 pad 11 pad 12 pad 13 -b oscin v dd alout mot2 mot1 mot1 alin/ mtest v ss oscout sc4 sc3 sc2 sc1 -d oscin oscout alout mot2 mot1 mot1 alin/ mtest v ss v dd sc4 sc3 sc2 sc1 -v2 oscin v dd alout mot2 mot1 mot1 alin/ mtest v ss oscout sc4 sc3 sc2 sc1 -d oscin oscout alout mot2 mot1 alin/ test mot1 v ss v dd sc4 sc3 sc2 sc1
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