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JBT6L77-AS 2001-12-18 1 toshiba cmos digital integrated circuits silicon monolithic JBT6L77-AS source driver for tft lcd panels the JBT6L77-AS is a 64 gray-level and 240-channel-output source driver for tft lcd panels. grayscale data accepts 6-bit digital data inputs, which combined with the internal da converter and 11 external power supplies, allows display of up to 260,000 colors. based on high-speed cmos, the JBT6L77-AS offers both low power consumption and high-speed operation. features grayscale data : 18-bit digital (3 outputs 6 bits) parallel transfer method, selectable write direction panel drive outputs : 240 outputs, 64 gray levels, dac system, reference analog voltage inputs high-speed operation : 30 mhz (max) power supply voltage : digital power supply voltage 2.5 to 3.6 v analog power supply voltage 5.0 0.5 v operating temperature : ? 20 to 75c gate driver for tft lcd panel : jbt6l78-as cascading multiple devices
JBT6L77-AS 2001-12-18 2 block diagram di/o cph da0 to da5 db0 to db5 dc0 to dc5 do/i load v0 to v10 av dd dv dd v ss testb u/d sa1 sb1 sc1 sa80 sb80 sc80 shift register sampling register da converter output circuit load register control circuit block
JBT6L77-AS 2001-12-18 3 pad layout chip size: 1.56 13.28 (mm) : cross point output pad 240, 50 m pitch, two-step zigzag allocation sb80 sc80 sa80 dummy dummy dummy dummy dummy dummy dummy 11 dummy dummy dummy dummy dummy dummy 11 sb1 sc1 sa1 dummy chip center (0,0) 6 6 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6 6 3 2222 2 avdd vss dvdd v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 cph u/d teg dc5 dc4 dc3 dc2 dc1 load do/i testb dc0 v0 db5 db4 db3 db1 db0 da5 da4 da3 da2 da1 di/o da0 vss avdd db2 3 3 teg teg alignment mark alignment mark unit: m output side dummy output pins (sa1 to sc80) 45 40 60 40 60 40 60 40 20 20 90 50 40 90 45 input pins (v0 to v10, load, testb) 40 45 45 20 40 20 20 50 40 20 40 90 input pins (dvdd) 70 20 70 45 45 35 35 20 70 90 input pins (others) 45 50 45 20 20 50 50 90 25 25 input pins (avdd, vss) 75 37.5 37.5 20 75 20 75 45 90 45 100 50 50 50 short-side dummy pins alignment mark 90 90 30 30 30 30 30 30 pattern prohibited 50 50 50 50 x ( ) y ( )
JBT6L77-AS 2001-12-18 4 pad coordinates chip size: 13.28 1.56 (mm) number of pad: 396 [unit: m] no. name x point y point no. name x point y point no. name x point y point 1 av dd 6307.5 606 39 u/d 2495.0 606 77 db4 1135.0 606 2 av dd 6212.5 606 40 do/i 2335.0 606 78 db3 1295.0 606 3 av dd 6117.5 606 41 do/i 2265.0 606 79 db3 1365.0 606 4 av dd 6022.5 606 42 do/i 2195.0 606 80 db3 1435.0 606 5 av dd 5927.5 606 43 load 2050.0 606 81 db2 1595.0 606 6 av dd 5832.5 606 44 load 1990.0 606 82 db2 1665.0 606 7 v ss 5657.5 606 45 testb 1900.0 606 83 db2 1735.0 606 8 v ss 5562.5 606 46 testb 1840.0 606 84 db1 1895.0 606 9 v ss 5467.5 606 47 dv dd 1715.0 606 85 db1 1965.0 606 10 v ss 5372.5 606 48 dv dd 1625.0 606 86 db1 2035.0 606 11 v ss 5277.5 606 49 dv dd 1535.0 606 87 db0 2195.0 606 12 v ss 5182.5 -606 50 v10 1260.0 606 88 db0 2265.0 606 13 teg1 5035.0 -606 51 v10 1200.0 606 89 db0 2335.0 606 14 teg2 4965.0 606 52 v9 1060.0 606 90 da5 2495.0 606 15 teg3 4895.0 606 53 v9 1000.0 606 91 da5 2565.0 606 16 dc5 4735.0 606 54 v8 910.0 606 92 da5 2635.0 606 17 dc5 4665.0 606 55 v8 850.0 606 93 da4 2795.0 606 18 dc5 4595.0 606 56 v7 710.0 606 94 da4 2865.0 606 19 dc4 4435.0 606 57 v7 650.0 606 95 da4 2935.0 606 20 dc4 4365.0 606 58 v6 560.0 606 96 da3 3095.0 606 21 dc4 4295.0 606 59 v6 500.0 606 97 da3 3165.0 606 22 dc3 4135.0 606 60 v5 360.0 -606 98 da3 3235.0 606 23 dc3 4065.0 606 61 v5 300.0 606 99 da2 3395.0 606 24 dc3 3995.0 606 62 v4 210.0 606 100 da2 3465.0 606 25 dc2 3835.0 606 63 v4 150.0 606 101 da2 3535.0 606 26 dc2 3765.0 606 64 v3 10.0 606 102 da1 3695.0 606 27 dc2 3695.0 606 65 v3 50.0 606 103 da1 3765.0 606 28 dc1 3535.0 606 66 v2 140.0 606 104 da1 3835.0 606 29 dc1 3465.0 606 67 v2 200.0 606 105 da0 3995.0 606 30 dc1 3395.0 606 68 v1 340.0 606 106 da0 4065.0 606 31 dc0 3235.0 606 69 v1 400.0 606 107 da0 4135.0 606 32 dc0 3165.0 606 70 v0 490.0 606 108 di/o 4295.0 606 33 dc0 3095.0 606 71 v0 550.0 606 109 di/o 4365.0 606 34 cph 2935.0 606 72 db5 695.0 606 110 di/o 4435.0 606 35 cph 2865.0 606 73 db5 765.0 606 111 teg4 4595.0 606 36 cph 2795.0 606 74 db5 835.0 606 112 teg5 4665.0 606 37 u/d 2635.0 606 75 db4 995.0 606 113 teg6 4735.0 606 38 u/d 2565.0 606 76 db4 1065.0 606 114 teg7 4895.0 606
JBT6L77-AS 2001-12-18 5 [unit: m] no. name x point y point no. name x point y point no. name x point y point 115 teg8 4965.0 606 156 sb5 5326.0 481 197 sa19 3276.0 621 116 teg9 5035.0 606 157 sc5 5276.0 621 198 sb19 3226.0 481 117 v ss 5182.5 606 158 sa6 5226.0 481 199 sc19 3176.0 621 118 v ss 5277.5 606 159 sb6 5176.0 621 200 sa20 3126.0 481 119 v ss 5372.5 606 160 sc6 5126.0 481 201 sb20 3076.0 621 120 v ss 5467.5 606 161 sa7 5076.0 621 202 sc20 3026.0 481 121 v ss 5562.5 606 162 sb7 5026.0 481 203 sa21 2976.0 621 122 v ss 5657.5 606 163 sc7 4976.0 621 204 sb21 2926.0 481 123 av dd 5832.5 606 164 sa8 4926.0 481 205 sc21 2876.0 621 124 av dd 5927.5 606 165 sb8 4876.0 621 206 sa22 2826.0 481 125 av dd 6022.5 606 166 sc8 4826.0 481 207 sb22 2776.0 621 126 av dd 6117.5 606 167 sa9 4776.0 621 208 sc22 2726.0 481 127 av dd 6212.5 606 168 sb9 4726.0 481 209 sa23 2676.0 621 128 av dd 6307.5 606 169 sc9 4676.0 621 210 sb23 2626.0 481 129 dummy 6488.5 439 170 sa10 4626.0 481 211 sc23 2576.0 621 130 dummy 6488.5 339 171 sb10 4576.0 621 212 sa24 2526.0 481 131 dummy 6488.5 239 172 sc10 4526.0 481 213 sb24 2476.0 621 132 dummy 6488.5 139 173 sa11 4476.0 621 214 sc24 2426.0 481 133 dummy 6488.5 39 174 sb11 4426.0 481 215 sa25 2376.0 621 134 dummy 6488.5 61 175 sc11 4376.0 621 216 sb25 2326.0 481 135 dummy 6488.5 161 176 sa12 4326.0 481 217 sc25 2276.0 621 136 dummy 6488.5 261 177 sb12 4276.0 621 218 sa26 2226.0 481 137 dummy 6488.5 361 178 sc12 4226.0 481 219 sb26 2176.0 621 138 dummy 6488.5 461 179 sa13 4176.0 621 220 sc26 2126.0 481 139 dummy 6488.5 561 180 sb13 4126.0 481 221 sa27 2076.0 621 140 dummy 6276.0 621 181 sc13 4076.0 621 222 sb27 2026.0 481 141 dummy 6176.0 621 182 sa14 4026.0 481 223 sc27 1976.0 621 142 dummy 6076.0 621 183 sb14 3976.0 621 224 sa28 1926.0 481 143 sa1 5976.0 621 184 sc14 3926.0 481 225 sb28 1876.0 621 144 sb1 5926.0 481 185 sa15 3876.0 621 226 sc28 1826.0 481 145 sc1 5876.0 621 186 sb15 3826.0 481 227 sa29 1776.0 621 146 sa2 5826.0 481 187 sc15 3776.0 621 228 sb29 1726.0 481 147 sb2 5776.0 621 188 sa16 3726.0 481 229 sc29 1676.0 621 148 sc2 5726.0 481 189 sb16 3676.0 621 230 sa30 1626.0 481 149 sa3 5676.0 621 190 sc16 3626.0 481 231 sb30 1576.0 621 150 sb3 5626.0 481 191 sa17 3576.0 621 232 sc30 1526.0 481 151 sc3 5576.0 621 192 sb17 3526.0 481 233 sa31 1476.0 621 152 sa4 5526.0 481 193 sc17 3476.0 621 234 sb31 1426.0 481 153 sb4 5476.0 621 194 sa18 3426.0 481 235 sc31 1376.0 621 154 sc4 5426.0 481 195 sb18 3376.0 621 236 sa32 1326.0 481 155 sa5 5376.0 621 196 sc18 3326.0 481 237 sb32 1276.0 621
JBT6L77-AS 2001-12-18 6 [unit: m] no. name x point y point no. name x point y point no. name x point y point 238 sc32 1226.0 481 279 sb46 824.0 621 320 sa60 2874.0 481 239 sa33 1176.0 621 280 sc46 874.0 481 321 sb60 2924.0 621 240 sb33 1126.0 481 281 sa47 924.0 621 322 sc60 2974.0 481 241 sc33 1076.0 621 282 sb47 974.0 481 323 sa61 3024.0 621 242 sa34 1026.0 481 283 sc47 1024.0 621 324 sb61 3074.0 481 243 sb34 976.0 621 284 sa48 1074.0 481 325 sc61 3124.0 621 244 sc34 926.0 481 285 sb48 1124.0 621 326 sa62 3174.0 481 245 sa35 876.0 621 286 sc48 1174.0 481 327 sb62 3224.0 621 246 sb35 826.0 481 287 sa49 1224.0 621 328 sc62 3274.0 481 247 sc35 776.0 621 288 sb49 1274.0 481 329 sa63 3324.0 621 248 sa36 726.0 481 289 sc49 1324.0 621 330 sb63 3374.0 481 249 sb36 676.0 621 290 sa50 1374.0 481 331 sc63 3424.0 621 250 sc36 626.0 481 291 sb50 1424.0 621 332 sa64 3474.0 481 251 sa37 576.0 621 292 sc50 1474.0 481 333 sb64 -3524.0 621 252 sb37 526.0 481 293 sa51 1524.0 621 334 sc64 3574.0 481 253 sc37 476.0 621 294 sb51 1574.0 481 335 sa65 3624.0 621 254 sa38 426.0 481 295 sc51 1624.0 621 336 sb65 3674.0 481 255 sb38 376.0 621 296 sa52 1674.0 481 337 sc65 3724.0 621 256 sc38 326.0 481 297 sb52 1724.0 621 338 sa66 3774.0 481 257 sa39 276.0 621 298 sc52 1774.0 481 339 sb66 3824.0 621 258 sb39 226.0 481 299 sa53 1824.0 621 340 sc66 -3874.0 481 259 sc39 176.0 621 300 sb53 1874.0 481 341 sa67 -3924.0 621 260 sa40 126.0 481 301 sc53 1924.0 621 342 sb67 3974.0 481 261 sb40 76.0 621 302 sa54 1974.0 481 343 sc67 4024.0 621 262 sc40 26.0 481 303 sb54 2024.0 621 344 sa68 4074.0 481 263 sa41 24.0 621 304 sc54 2074.0 481 345 sb68 4124.0 621 264 sb41 74.0 481 305 sa55 2124.0 621 346 sc68 4174.0 481 265 sc41 124.0 621 306 sb55 2174.0 481 347 sa69 4224.0 621 266 sa42 174.0 481 307 sc55 2224.0 621 348 sb69 4274.0 481 267 sb42 224.0 621 308 sa56 2274.0 481 349 sc69 4324.0 621 268 sc42 274.0 481 309 sb56 2324.0 621 350 sa70 4374.0 481 269 sa43 324.0 621 310 sc56 2374.0 481 351 sb70 4424.0 621 270 sb43 374.0 481 311 sa57 2424.0 621 352 sc70 4474.0 481 271 sc43 424.0 621 312 sb57 2474.0 481 353 sa71 4524.0 621 272 sa44 474.0 481 313 sc57 2524.0 621 354 sb71 4574.0 481 273 sb44 524.0 621 314 sa58 2574.0 481 355 sc71 4624.0 621 274 sc44 574.0 481 315 sb58 2624.0 621 356 sa72 4674.0 481 275 sa45 624.0 621 316 sc58 2674.0 481 357 sb72 4724.0 621 276 sb45 674.0 481 317 sa59 2724.0 621 358 sc72 4774.0 481 277 sc45 724.0 621 318 sb59 2774.0 481 359 sa73 4824.0 621 278 sa46 774.0 481 319 sc59 2824.0 621 360 sb73 4874.0 481
JBT6L77-AS 2001-12-18 7 [unit: m] no. name x point y point 361 sc73 4924.0 621 362 sa74 4974.0 481 363 sb74 5024.0 621 364 sc74 5074.0 481 365 sa75 5124.0 621 366 sb75 5174.0 481 367 sc75 5224.0 621 368 sa76 5274.0 481 369 sb76 5324.0 621 370 sc76 5374.0 481 371 sa77 5424.0 621 372 sb77 5474.0 481 373 sc77 5524.0 621 374 sa78 5574.0 481 375 sb78 5624.0 621 376 sc78 5674.0 481 377 sa79 5724.0 621 378 sb79 5774.0 481 379 sc79 5824.0 621 380 sa80 5874.0 481 381 sb80 5924.0 621 382 sc80 5974.0 481 383 dummy 6024.0 621 384 dummy 6124.0 481 385 dummy 6224.0 621 386 dummy 6488.5 561 387 dummy 6488.5 461 388 dummy 6488.5 361 389 dummy 6488.5 261 390 dummy 6488.5 161 391 dummy 6488.5 61 392 dummy 6488.5 39 393 dummy 6488.5 139 394 dummy 6488.5 239 395 dummy 6488.5 339 396 dummy 6488.5 439 aligment mark 6464.0 605 aligment mark 6464.0 605
JBT6L77-AS 2001-12-18 8 pin function pin name i/o function di/o do/i i/o data transfer enable pin these pins are used to input/output grayscale data. input and output are switched as shown below according to the setting of the u/d pin. u/d di/o do/i h input output l output input when set for input a high on di/o or do/i is latched into the internal logic synchronously with the rising edge of cph. when the internal circuit is in standby state, the device is ready to transfer data. the grayscale data is latched in sequentially, starting at the next rise of cph. when set for output the pin is used to transfer the enable signal to the JBT6L77-AS at the next stage of the lcd driver. the pin enters standby state after outputting a high. u/d i transfer direction select pin this pin controls the direction in which the data is transferred into the sampling register. data is transferred synchronously with each rising edge of cph in one of the following sequences: when u/d is high, data is transferred in the order sa1 to sc1, sa2 to sc2, sa3 to sc3, ? when u/d is low, the direction is reversed to give sa80 to sc80, sa79 to sc79, sa78 to sc78, ? the voltage applied to this pin must be a dc-level voltage that is either high or low. cph i sampling clock input this clock input is used to transfer grayscale data. in sync with the rising edge of cph, writes grayscale data bus data to the sampling register. da0 to da5 db0 to db5 dc0 to dc5 i grayscale data bus the data inputs consist of 6-bit word for each three channel that are transferred in parallel at the rising edge of cph. the relationship between the grayscale data and the weight of each bit is as follows: grayscale data 32 dw5 16 dw4 8 dw3 4 dw2 2 dw1 dw0 ( * ) w a, b, c load i data load input pin when a high voltage supplys to the load input, the data is transferred from the sampling register to the load register synchronously at the rising edge of cph. (note) after high level is input to this pin (load), input cph for at least three cycles in the same cycle as that for sampling. when load low level, output is at high impedance. when load high level, output corresponds to grayscale data. v0 to v10 i reference analog input pins these pins are used to input the voltage used for the dac. v ss v0 v1 ? v9 v10 avdd or avdd v0 v1 ? v9 v10 v ss testb i test pin leave this pin open or v dd level. sa1 to sa80 sb1 to sb80 sc1 to sc80 o lcd panel drive pins av dd analog power supply pin dv dd digital power supply pin. v ss gnd pin
JBT6L77-AS 2001-12-18 9 device operation (1) starting data transfer a high input to the data transfer enable pin (di/o or do/i) is latched into the internal logic synchronously with the rising edge of cph, setting the device ready to transfer data. data transfer starts at the next rise of cph (see timing diagram 1 and 2). (2) data transfer method the data is latched in from the grayscale bus to the sampling register synchronously with each rising edge of cph. grayscale data for three outputs are latched into the device simultaneously in one transfer. grayscale data are written as three outputs in parallel during one transfer. data transfer completes after 80 transfers. then the device enters standby mode. data written to the sampling register are the operation result of the grayscale data bus. (3) terminating data transfer the data transfer enable pin (do/i or di/o) output goes high synchronously with the rising edge of cph one clock period before the last data is latched in. it is held high until the next rise of cph (see timing diagram 1 and 2). the output from this pin can be connected directly as input to the data transfer enable pin (di/o or do/i) of the next stage lcd driver. in this way, multiple devices can be easily cascaded to drive a large screen. (4) panel drive output when a high voltage supplies to the load input, the data in the sampling register is transferred to the load register and the device starts updating output to the lcd panel drive pins.
JBT6L77-AS 2001-12-18 10 (5) reference power supply circuit the connection between the device and the external reference power supply for reference analog supply is configured with 1, 7 or 8 resistors in series (total of 63 resistor ladders). external power supply for reference voltage r0 v0 v1 v3 v4 v5 v6 v7 v8 v9 JBT6L77-AS v10 r1 to r6 r7 to r14 r15 to r22 r23 to r30 r31 to r38 r39 to r46 r47 to r54 r55 to r61 r62 v2
JBT6L77-AS 2001-12-18 11 resistor name resistance value (
) resistor name resistance value (
) r0 6247 r32 62 r1 2186 r33 125 r2 1312 r34 125 r3 875 r35 125 r4 687 r36 187 r5 625 r37 62 r6 500 r38 125 r7 375 r39 125 r8 375 r40 125 r9 312 r41 125 r10 250 r42 125 r11 312 r43 125 r12 312 r44 187 r13 187 r45 125 r14 187 r46 125 r15 250 r47 125 r16 187 r48 187 r17 187 r49 125 r18 187 r50 187 r19 187 r51 125 r20 187 r52 187 r21 125 r53 187 r22 187 r54 187 r23 125 r55 250 r24 125 r56 187 r25 125 r57 312 r26 187 r58 312 r27 125 r59 375 r28 125 r60 437 r29 125 r61 687 r30 125 r62 6746 r31 187
JBT6L77-AS 2001-12-18 12 (6) grayscale data and output voltages the lcd drive output voltages are determined by the grayscale values and the 11 reverence analog inputs line voltages (v0 to v11). schematic representation of reference analog voltage inputs avss 00h 07h 0fh 17h 1fh 27h 2fh 37h 3eh 3fh v10 v9 v8 v7 v6 v5 v4 v3 v2 avdd v0
JBT6L77-AS 2001-12-18 13 grayscale data and output voltages (input voltage: v0 4.90 v, v10 0.10 v) ( * ) w a, b, c grayscale data dw5 dw4 dw3 dw2 dw1 dw0 output voltage 00h 0 0 0 0 0 0 v00h v0 4.90 01h 0 0 0 0 0 1 v01h 3.90 02h 0 0 0 0 1 0 v02h 3.55 03h 0 0 0 0 1 1 v03h 3.34 04h 0 0 0 1 0 0 v04h 3.20 05h 0 0 0 1 0 1 v05h 3.09 06h 0 0 0 1 1 0 v06h 2.99 07h 0 0 0 1 1 1 v07h v2 2.91 08h 0 0 1 0 0 0 v08h 2.85 09h 0 0 1 0 0 1 v09h 2.79 0ah 0 0 1 0 1 0 v0ah 2.74 0bh 0 0 1 0 1 1 v0bh 2.70 0ch 0 0 1 1 0 0 v0ch 2.65 0dh 0 0 1 1 0 1 v0dh 2.60 0eh 0 0 1 1 1 0 v0eh 2.57 0fh 0 0 1 1 1 1 v0fh v3 2.54 10h 0 1 0 0 0 0 v10h 2.50 11h 0 1 0 0 0 1 v11h 2.47 12h 0 1 0 0 1 0 v12h 2.44 13h 0 1 0 0 1 1 v13h 2.41 14h 0 1 0 1 0 0 v14h 2.38 15h 0 1 0 1 0 1 v15h 2.35 16h 0 1 0 1 1 0 v16h 2.33 17h 0 1 0 1 1 1 v17h v4 2.30 18h 0 1 1 0 0 0 v18h 2.28 19h 0 1 1 0 0 1 v19h 2.26 1ah 0 1 1 0 1 0 v1ah 2.24 1bh 0 1 1 0 1 1 v1bh 2.21 1ch 0 1 1 1 0 0 v1ch 2.19 1dh 0 1 1 1 0 1 v1dh 2.17 1eh 0 1 1 1 1 0 v1eh 2.15 1fh 0 1 1 1 1 1 v1fh v5 2.13
JBT6L77-AS 2001-12-18 14 ( * ) w a, b, c grayscale data dw5 dw4 dw3 dw2 dw1 dw0 output voltage 20h 1 0 0 0 0 0 v20h 2.10 21h 1 0 0 0 0 1 v21h 2.09 22h 1 0 0 0 1 0 v22h 2.07 23h 1 0 0 0 1 1 v23h 2.05 24h 1 0 0 1 0 0 v24h 2.03 25h 1 0 0 1 0 1 v25h 2.00 26h 1 0 0 1 1 0 v26h 1.99 27h 1 0 0 1 1 1 v27h v6 1.97 28h 1 0 1 0 0 0 v28h 1.95 29h 1 0 1 0 0 1 v29h 1.93 2ah 1 0 1 0 1 0 v2ah 1.91 2bh 1 0 1 0 1 1 v2bh 1.89 2ch 1 0 1 1 0 0 v2ch 1.87 2dh 1 0 1 1 0 1 v2dh 1.84 2eh 1 0 1 1 1 0 v2eh 1.82 2fh 1 0 1 1 1 1 v2fh v7 1.80 30h 1 1 0 0 0 0 v30h 1.78 31h 1 1 0 0 0 1 v31h 1.75 32h 1 1 0 0 1 0 v32h 1.73 33h 1 1 0 0 1 1 v33h 1.70 34h 1 1 0 1 0 0 v34h 1.68 35h 1 1 0 1 0 1 v35h 1.65 36h 1 1 0 1 1 0 v36h 1.62 37h 1 1 0 1 1 1 v37h v8 1.59 38h 1 1 1 0 0 0 v38h 1.55 39h 1 1 1 0 0 1 v39h 1.52 3ah 1 1 1 0 1 0 v3ah 1.47 3bh 1 1 1 0 1 1 v3bh 1.42 3ch 1 1 1 1 0 0 v3ch 1.36 3dh 1 1 1 1 0 1 v3dh 1.29 3eh 1 1 1 1 1 0 v3eh v9 1.18 3fh 1 1 1 1 1 1 v3fh v10 0.10
JBT6L77-AS 2001-12-18 15 timing diagrams 1 timing diagrams 2 cph da0 to da5 db0 to db5 dc0 to dc5 0 1 2 3 4 01 79 80 first data at next stage load 81 2 3 4 di/o, do/i (input) di/o, do/i (output) last data first data hi-z hi-z sa1 to sa80 sb1 to sb80 sc1 to sc80 sa1/ sa80 sa2/ sa79 sa79/ sa2 sa80/ sa1 sb1/ sb80 sb2/ sb79 sb3/ sb78 sb79/ sb2 sb80/ sb1 sc1/ sc80 sc2/ sc79 sc3/ sc78 sc79/ sc2 sc80/ sc1 cph di/o, do/i (input) 0 1 2 3 79 78 ( * ) upper stage: sa1 u/d high lower stage: sa80 u/d low ( * ) 80 sa3/ sa78 do/i, di/o (output) da0 to da5 db0 to db5 dc0 to dc5
JBT6L77-AS 2001-12-18 16 absolute maximum ratings (v ss 0 v) characteristics symbol rating unit relevant pin analog supply voltage dv dd 0.3 to 6.5 v digital supply voltage av dd 0.3 to 6.5 v input voltage v in 0.3 to dv dd 0.3 v reference analog voltage v (0:10) 0.3 to av dd 0.3 v v0 to v10 storage temperature tstg 55 to 125 c recommended operating conditions (v ss 0 v) characteristics symbol test condition rating unit relevant pin digital supply voltage dv dd 2.5 to 3.6 v analog supply voltage av dd 4.5 to 5.5 v reference analog voltage-1 (note 1) v0 to v10 0.1 to av dd 0.1 v operating temperature topr 20 to 75 c operating frequency f cph dc to 30 mhz cph output load capacitance c l 100 (max) pf/ pin sa1 to sa80 sb1 to sb80 sc1 to sc80 note 1: the following shows the relative magnitude of each reference analog voltage: v ss v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 av dd or v ss v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 v0 av dd
JBT6L77-AS 2001-12-18 17 electrical characteristics dc characteristics ( v ss 0 v, dv dd 2.5 to 3.6 v, av dd 4.5 v to 5.5 v, ta 20 to 75c) characteristics symbol test circuit test condition min typ. max unit relevant pin i ill1 10 (note 2) low level i ill2 400 testb input current high level i ih 10 a (note 3) low level v il 0 0.2 dv dd input voltage high level v ih 0.8 dv dd dv dd v (note 4) low level v ol i ol 0.1 ma 0 0.5 v output voltage high level v oh i oh 0.1 ma dv dd 0.5 dv dd di/o, do/i output off current i off (note 7) 10 output voltage range v out 0.1 av dd 0.1 a v do1 0.1 reference analog voltage 1.2 40 40 output voltage deviation v do2 1.2 reference analog voltage 4.9 30 30 mv sa1 to sa80 sb1 to sb80 sc1 to sc80 during operations (note 5) 4 current consumption (1) di dd when no, operations (note 6) 3 ma dv dd during operations (note 5) 8 when no, operations (note 6) 8 ma current consumption (2) ai dd load low (note 7) 100 a av dd note 2: da0 to da5, db0 to db5, dc0 to dc5, di/o, do/i, cph, load, u/d note 3: da0 to da5, db0 to db5, dc0 to dc5, di/o, do/i, cph, load, u/d, testb note 4: da0 to da5, db0 to db5, dc0 to dc5, di/o, do/i, cph, load note 5: dv dd 3.6 v, av dd 5.5 v, f cph 30 mhz, 1h 100 s, no load, checkerboard pattern, load 1 s at low level, typical value note 6: av dd 5.5 v, f cph 30 mhz, 1h 100 s, di/o: fixed low note 7: av dd 5.5 v, standby at load low, f cph 30 mhz, di/o: fixed low
JBT6L77-AS 2001-12-18 18 ac characteristics (v ss 0 v, dv dd 2.5 to 3.6 v, av dd 4.5 v to 5.5 v, ta 20 to 75c) characteristics symbol test circuit test condition min typ. max unit cph pulse width h t cwh 4 ns cph pulse width l t cwl 4 ns enable setup time t sdi 4 ns enable hold time t hdi 0 ns data setup time t sdd 4 ns data hold time t hdd 0 ns load setup time t sld 1 cph load hold time t hld 2 cph load pulse width h t lwh 10 s load pulse width l t lwl 1 s output delay time 1 t pddo c l 15 pf 15 ns output delay time 2 t pddx c l 100 pf 10 s
JBT6L77-AS 2001-12-18 19 cph do/i, di/o (output) last-1 t pddo dv dd 0.8 dv dd 0.8 last dv dd 0.8 load dv dd 0.8 t pddo dv dd 0.8 t lwh t sld cph load dv dd 0.8 dv dd 0.8 t lwl dv dd 0.2 di/o, do/i (input) t sdi t hdi dv dd 0.8 sa1 to sa80 sb1 to sb80 sc1 to sc80 t pddx t pddx t hld dv dd 0.2/ dv dd 0.2 cph dw0 to dw5 w a, b, c last-1 last dv dd 0.8 t cwh t cwl t hdd t sdd valid valid last valid dv dd 0.2 dv dd 0.2 dv dd 0.8
JBT6L77-AS 2001-12-18 20 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases this can cause the device to malfunction. this is especially true for devices in which the surface (back), or side of the chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. exposure to light both during regular operation and during inspection must be taken into account. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ebm restrictions on product use

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