? semiconductor components industries, llc, 2003 march, 2003 - rev. 3 1 publication order number: nid9n05cl/d nid9n05cl power mosfet 9 amps, 52 volts n-channel, logic level, clamped mosfet w/ esd protection in a dpak package benefits ? high energy capability for inductive loads ? low switching noise generation features ? diode clamp between gate and source ? esd protection - hbm 5000 v ? active over-voltage gate to drain clamp ? scalable to lower or higher r ds(on) ? internal series gate resistance applications ? automotive and industrial markets: solenoid drivers, lamp drivers, small motor drivers maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain-to-source voltage internally clamped v dss 52-59 vdc gate-to-source voltage - continuous v gs 12 vdc drain current - continuous @ t a = 25 c drain current - single pulse (tp = 10 s) i d i dm 9.0 35 a total power dissipation @ t a = 25 c p d 28.8 w operating and storage temperature range t j , t stg -55 to 175 c single pulse drain-to-source avalanche en- ergy - starting t j = 125 c (v dd = 50 v, i d(pk) = 1.5 a, v gs = 10 v, r g = 25 ) e as 160 mj thermal resistance - junction-to-case - junction-to-ambient (note 1) - junction-to-ambient (note 2) r jc r ja r ja 5.2 72 100 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 sec. t l 260 c 1. when surface mounted to an fr4 board using 1 pad size, (cu area 1.127 in 2 ) 2. when surface mounted to an fr4 board using minimum recommended pad size, (cu area 0.412 in 2 ) 9 amperes 52 v clamped r ds(on) = 90 m (typ.) device package shipping ordering information nid9n05clt4 dpak 2500/tape & reel dpak case 369a style 2 m pwr drain (pins 2, 4) source (pin 3) gate (pin 1) marking diagram d9n05cl = device code y = year ww = work week r g overvoltage protection esd protection http://onsemi.com yww x 1 = gate 2 = drain 3 = source 4 = drain 1 2 3 4 nid9n05cl dpak 75 units/rail d9n05cl
nid9n05cl http://onsemi.com 2 mosfet electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain-to-source breakdown voltage (note 3) (v gs = 0 vdc, i d = 1.0 madc) temperature coefficient (negative) v (br)dss 52 - 55 -10 59 - vdc mv/ c zero gate voltage drain current (v ds = 40 vdc, v gs = 0 vdc) (v ds = 40 vdc, v gs = 0 vdc, t j = 125 c) i dss - - - - 10 25 adc gate-body leakage current (v gs = 8 vdc, v ds = 0 vdc) (v gs = 14 vdc, v ds = 0 vdc) i gss - - - 22 10 - adc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 100 adc) threshold temperature coefficient (negative) v gs(th) 1.3 - 1.75 -4.5 2.5 - vdc mv/ c static drain-to-source on-resistance (note 3) (v gs = 4.0 vdc, i d = 1.5 adc) (v gs = 3.5 vdc, i d = 0.6 adc) (v gs = 3.0 vdc, i d = 0.2 adc) (v gs = 12 vdc, i d = 9.0 adc) (v gs = 12 vdc, i d = 12 adc) r ds(on) - - - 70 67 153 175 - 90 95 181 364 1210 - - m forward transconductance (note 3) (v ds = 15 vdc, i d = 9.0 adc) g fs - 24 - mhos dynamic characteristics input capacitance c iss - 155 250 pf output capacitance (v ds = 40 vdc, v gs = 0 v, f = 10 khz ) c oss - 60 100 transfer capacitance f = 10 khz) c rss - 25 40 input capacitance c iss - 175 - pf output capacitance (v ds = 25 vdc, v gs = 0 v, f = 10 khz ) c oss - 70 - transfer capacitance f = 10 khz) c rss - 30 - 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
nid9n05cl http://onsemi.com 3 mosfet electrical characteristics (t j = 25 c unless otherwise noted) characteristic unit max typ min symbol switching characteristics (note 4) turn-on delay time t d(on) - 130 200 ns rise time ( v gs = 10 vdc, v dd = 40 vdc, t r - 500 750 turn-of f delay time (v gs = 10 vdc , v dd = 40 vdc , i d = 9.0 adc, r g = 9.0 ) t d(off) - 1300 2000 fall time t f - 1150 1850 turn-on delay time t d(on) - 200 - ns rise time ( v gs = 10 vdc, v dd = 15 vdc, t r - 500 - turn-of f delay time (v gs = 10 vdc , v dd = 15 vdc , i d = 1.5 adc, r g = 2 k ) t d(off) - 2500 - fall time t f - 1800 - turn-on delay time t d(on) - 120 - ns rise time ( v gs = 10 vdc, v dd = 15 vdc, t r - 275 - turn-of f delay time (v gs = 10 vdc , v dd = 15 vdc , i d = 1.5 adc, r g = 50 ) t d(off) - 1600 - fall time t f - 1100 - gate charge q t - 4.5 7.0 nc (v gs = 4.5 vdc, v ds = 40 vdc, i d = 9.0 adc ) ( note 3 ) q 1 - 1.2 - i d = 9 . 0 adc) (note 3) q 2 - 2.7 - gate charge q t - 3.6 - nc (v gs = 4.5 vdc, v ds = 15 vdc, i d = 1.5 adc ) ( note 3 ) q 1 - 1.0 - i d = 1 . 5 adc) (note 3) q 2 - 2.0 - source-drain diode characteristics forward on-voltage (i s = 4.5 adc, v gs = 0 vdc) (note 3) (i s = 4.0 adc, v gs = 0 vdc) (i s = 4.5 adc, v gs = 0 vdc, t j = 125 c) v sd - - - 0.86 0.845 0.725 1.2 - - vdc reverse recovery time t rr - 700 - ns (i s = 4.5 adc, v gs = 0 vdc, di s /dt = 100 a/ s ) ( note 3 ) t a - 200 - di s /dt = 100 a/ s) (note 3) t b - 500 - reverse recovery stored charge q rr - 6.5 - c esd characteristics electro-static discharge capability human body model (hbm) esd 5000 - - v machine model (mm) 500 - - 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
nid9n05cl http://onsemi.com 4 0 0.15 12 10 0.1 0.05 0 614 0.2 0.35 16 2.5 1.5 1 0.5 100 10,000 1,000,000 08 8 2 1 v ds , drain-to-source voltage (volts) i d , drain current (amps) 0 v gs , gate-t o-source voltage (volts) figure 1. on-region characteristics figure 2. transfer characteristics i d , drain current (amps) 2 0.3 10 8 0.1 0 612 figure 3. on-resistance versus gate-to-source voltage v gs , gate-t o-source voltage (volts) figure 4. on-resistance versus drain current and gate voltage i d , drain current (amps) r ds(on) , drain-to-source resistance ( w ) r ds(on) , drain-to-source resistance ( w ) figure 5. on-resistance variation with temperature t j , junction temperature ( c) figure 6. drain-to-source leakage current versus voltage v ds , drain-to-source voltage (volts) r ds(on) , drain-to-source resistance (normalized) i dss , leakage (na) 18 -50 50 25 0 -25 75 125 100 16 40 30 20 50 3 4 12 8 v v ds 10 v t j = 25 c t j = -55 c t j = 100 c v gs = 12 v 150 175 v gs = 0 v i d = 9 a v gs = 12 v 16 0.2 0.5 v gs = 10 v i d = 4.5 a t j = 25 c t j = 150 c t j = 100 c 4 0 16 8 12 4 t j = 25 c 45 1000 6.5 v 5 v 4 v 3.8 v 4567 23 5 0.4 0.25 0.3 2 6 2 10 14 6 v t j = 25 c 4.6 v 4.2 v 3.4 v 3.2 v 2.8 v 6 2 18 10 14 9 78 4 v gs = 4 v 28 418 0.4 100,000 25 35
nid9n05cl http://onsemi.com 5 c rss 020304050 v ds , drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 200 0 300 100 10 v gs = 0 v t j = 25 c c oss c iss 400 500 frequency = 10 khz v ds v gs 10 0 0.4 drain-t o-source diode characteristics v sd , source-to-drain voltage (volts) figure 8. gate-to-source and drain-to-source voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 10,000 100 t, time (ns) v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current v gs , gate-t o-source voltage (volts) 0 5 3 1 0 q g , total gate charge (nc) 4 2 3 12 5 1.2 2 4 6 i d = 9 a t j = 25 c q gd q gs q t t r t d(off) t d(on) t f 1000 v dd = 40 v i d = 9 a v gs = 10 v 4 8 1.0 0.8 0.6 50 40 30 20 10 0 v ds , drain-to-source voltage (volts)
nid9n05cl http://onsemi.com 6 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, transient thermal resistance - general data and its use.o switching between the off-state and the on-state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) - t c )/(r q jc ). a power mosfet designated e-fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. although many e- fets can withstand the stress of drain- to- source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
nid9n05cl http://onsemi.com 7 safe operating area figure 11. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain-to-source voltage (volts) figure 12. thermal response 1 100 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.1 10 10 v gs = 12 v single pulse t c = 25 c 1 ms 100 m s 10 ms dc 10 m s r(t), effective transient thermal resistance (normalized) t, time (s) 1 10 001 0.2 d = 0.5 0.05 0.01 single pulse r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 110 0.1 0.01 0.001 0.0001 0.00001 0.1
nid9n05cl http://onsemi.com 8 package dimensions dpak case 369a-13 issue ab d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h -t- seating plane z dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.175 0.215 4.45 5.46 s 0.020 0.050 0.51 1.27 u 0.020 --- 0.51 --- v 0.030 0.050 0.77 1.27 z 0.138 --- 3.51 --- notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nid9n05cl/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada
|
