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a64e06161 preliminary 1m x 16 bit low voltage super ram document title 1m x 16 bit low voltage super ram revision histor y rev . no. h i s t o r y i s s u e date r e m a r k 0 . 0 i n i t i a l issu e october 12, 20 03 prelimi nar y 0.1 chan ge vc c rang e and vc c q range novemb er 30, 200 4 chan ge p a g e access time fro m 20ns to 25n s chan ge o perat ion curre nt (i cc1 ) from 25ma to 15ma(-7 0) chan ge o perat ion curre nt (i cc1 ) from 20ma to 12ma(-8 5) chan ge stan db y curre nt (i sb 1 ) from 80ua to 1 00ua delete r educ e memor y s i ze 1 6 m, partial arr a y refresh 16m chan ge o perat ion curre nt (i cc2 ) form 5ma to 3ma(-70, -85) chan ge par c u rrent 12m b= 9 0ua, 8mb= 80 u a , 4mb= 70ua chan ge t cr current + 8 5 c= 100 ua + 7 0 c= 90ua chan ge t cr current + 4 5 c= 85ua + 1 5 c= 7 5ua preliminary (november, 2004, version 0. 1) amic technology , corp.
a64e06161 preliminary 1m x 16 bit low voltage super ram features operatin g volta ge: vcc: 1.7 v to 1.95v vccq: 1.7v t o vcc access times: t aa = 70ns (max.) page access ti mes: t pa a = 25 ns (max) current: a64e06 161 series: operatin g curr ent (icc1) : 15ma (max.) standb y current (isb1) : 100 ua (ma x) deep p o w e r d o w n stan db y c u rrent (i zz ) : 10 p a (max . ) 4- w o rd p a g e le ngth supp ort 4 d i stinct op eratio n modes for r e d u cing stand b y po w e r : deep p o w e r d o w n (dpd) mo de reduc e memo r y size (rms) mode (4m, 8m, 12m) partial arra y r e fresh (par) mode (4m,8m, 12m) t e mperature c o mpe n sated r e fresh (t cr) mode industria l oper ating temp erat ure rang e: -25 q c to +85 q c for ? i availa bl e in 48 -ball mi ni bga (6x8) pack age. gener a l des c ription t he a64e061 61 is a lo w op er atin g current 16,777,2 16-b i t super ram or ganiz ed as 1, 048,5 76 w o r d b y 16 bit an d oper ated on l o w p o w e r su ppl y volt a ge from 1.7v to 1.95v. it is built usin g amic?s high performance cmos dram process. using h i dd en r e fresh techn i q ue, the a64e0 616 1 provi des a compati b le as ynchro nous i n te rface and data can be r ead i n 4- w o rd p age mode for fast access times. t he a64e0616 1 has an intern a l register nam ed the config u r ation re gister (cr) that controls the op eratio n. t he a64e0 616 1 is desig ne d for reduci ng c u rren t consumptio n durin g hi dde n self refresh an d op eratin g th roug h foll o w i n g mod e : dee p po w e r do w n ( d pd) mode, reduc e memo r y size (rms) mode, parti a l arra y refres h (par) mod e a nd t e mperatur e compe n sate d refresh (t cr) mode. t h is a64e061 61 is suited for lo w p o w e r app licatio n such a s mobil e p hon e and p d a or ot her b a tter y - o p e rated ha ndh el d device. pin configur ation mini bg a (6x8 ) top v i e w 1 2 3 4 5 6 a lb oe a 0 a 1 a 2 zz b i/o 8 hb a 3 a 4 ce i/o 0 c i/o 9 i / o 10 a 5 a 6 i/o 1 i/o 2 d vssq i/o 11 a1 7 a 7 i / o 3 vcc e vc c q i/o 12 n c a 1 6 i/o 4 vss f i/o 14 i / o 13 a1 4 a 1 5 i/o 5 i/o 6 g i/o 15 a 1 9 a 12 a13 we i/o 7 h a18 a8 a9 a10 a 11 nc a 6 4e06 16 1 g preliminary (november, 2004, version 0. 1) 1 amic technology , corp.
a64e06161 block diagra m decoder 16,777,216 memory array column i/o input data circuit control circuit vcc vccq i/o 7 i/o 0 a19 a18 a0 we hb input data circuit i/o 8 i/o 15 zz lb oe ce vss vssq pin descrip tion sy m b o l d e s c r i p t i o n a0 - a19 address i n p u t s ce chip e nab le i n put zz slee p enab le i nput (when zz is lo w , t he cr regist er can be load ed or t he d e vice ca n ent er dpd mode or par mode). i/o 0 - i/o 15 d a t a i nput / o ut put s we writ e enabl e i nput lb by te ena b l e inp u t (i/o 0 to i/ o 7 ) hb by te ena b l e inp u t (i/o 8 to i/ o 15 ) oe out put enabl e i nput v c c p o w e r v s s g r o u n d vccq provide is ol at e d po w e r t o i / o f o r improved noise imm unit y vssq provide is ol at e d / ground t o i / o f o r improved noise imm unit y nc no connecti on or vssq pr el imin ar y (november, 2004, version 0. 1) 2 amic technology , corp.
a64e06161 rec o mmend ed dc oper a t ing condi tions ( t a = 0 c to + 7 0 c or -25 c to 8 5 c) s y m b o l p a r a mete r m i n . m a x . u n i t v c c s u p p l y v o lt ag e 1. 7 1. 9 5 v v s s g r o u n d 0 0 v vccq supp l y v o lt ag e i / o onl y 1. 7 vcc v vssq ground i/o onl y 0 0 v v ih i nput hig h volt age 1. 4 vccq + 0. 2 v v il i nput lo w vo lt age -0. 2 + 0 . 4 v c l o u t put loa d - 3 0 pf absolu te ma ximum ratin g s* vcc to vss . . . . . . . . . . . . . . . . . . -0.3v to vcc+0.3v vccq to vssq . . . . . . . . . . . . . . . -0.3v to vccq+0.3v in , in /ou t vo lt to gn d . . . . . . . . -0 .3 v to vc c q + 0 . 3 v st orage t e mperat ure, t s t g . . . . . . . . -55 c to +1 2 5 c po w e r diss ipat ion, p t . . . . . . . . . . . . . . . . . . . . . 0 . 7 w so lde r ing t e m p . & t i me . . . . . . . . . . . . 2 6 0 c, 10 sec *c omment s st resses ab ov e t hose list e d und er "a bsol ut e ma xim u m rat i ngs " ma y cause perma nent d a mag e t o t h is dev ice. t hese are st ress rat i ngs onl y. f unct i onal op erat io n of t h is device at t h e s e or an y ot her cond it ions above t hose indic a t ed in t h e operat i ona l sect ions of t h is specif icat i on is not impl ie d o r int e n ded. exp o sur e t o t he abs olut e maximum rat i n g cond it ions f o r ext e nde d peri ods ma y af f e ct device r e lia bil i t y . dc elec trica l charac teris t ics (t a = 0 c to + 70 c o r -25 c to 85 c, vcc = 1.7v to 1.95v, vccq = 1. 7v to vcc gnd = 0v) s y m b o l p a r a mete r -70 -85 u n i t c o n d i t i ons m i n . m a x . m i n . m a x . ? i li ? i nput leak ag e current - 1 - 1 a v in = gnd t o vccq ? i lo ? out put leak ag e current - 1 - 1 a ce = v ih or zz = v il or oe = v ih or we = v il v i/o = gnd t o vccq i cc1 - 1 5 - 1 2 m a min. c y cl e, du t y = 100% ce = v il , zz = v ih v ih = vccq, v il = 0 v , i i/o = 0 m a i cc2 d y namic oper at ing current - 3 - 3 m a ce = v il , zz = v ih v ih = vccq, v il = 0 v , f = 1 m h z , i i/ o = 0 m a i sb 1 st andb y po w e r supp l y curre nt - 1 0 0 - 1 0 0 a ce vccq - 0. 2v zz vccq - 0. 2v v in 0v v ol out put lo w vo lt age - 0. 2 - 0. 2 v i ol = 0. 2 ma v oh out put high v o lt ag e vccq-0. 2 - vccq-0. 2 - v i oh = -0 .2 ma pr el imin ar y (november, 2004, version 0. 1) 3 amic technology , corp.
a64e06161 dee p po w e r do w n spe c ifications an d condition s sy m b o l d e s c r i p t i o n conditi ons ty p . ma x . units i zz deep p o w e r-d o w n v in = vccq or 0v; + 2 5 c zz = low cr[ 4] = 0 1 0 a partial arr a y refr esh spe c ification s conditions sy m b o l d e s c r i p t i o n conditi ons de ns ity a rray partition t y p . m a x . un i t s 12mb 3/ 4 90 a 8 m b 1 / 2 8 0 a i pa r partial array refresh current v in = vccq or 0v zz = l o w cr[ 4] = 1 4 m b 1 / 4 7 0 a not e : i pa r (ma x ) val ues me a s ured w i t h t c r set t o 85 c tempera t ur e compens a ted re fre s h specifica tions conditions sy m b o l d e s c r i p t i o n conditi ons de ns ity max ca se t e mp eratu r e s t y p . m a x . un i t s +8 5 c 1 0 0 a +7 0 c 9 0 a +4 5 c 8 0 a i tcr t e mperat u r e compe n sat e d ref r esh st andb y c u rre nt v in = vccq or 0v c h i p di sa bl ed 16mb +1 5 c 7 0 a not e : 1. i tcr (max) val ues me asure d w i t h f u ll array ref r esh. 2. t h is device as sumes a st and b y mo de if t he chip is dis a b l e d ( ce hi gh). truth ta ble ce zz oe we lb hb i/o 0 to i/o 7 mo de i/o 8 to i/o 15 mode vcc current h h x x x x not s e l e c t e d not s e l e c t e d i sb 1 h l x x x x not s e l e c t e d not s e l e c t e d i zz *2 h l x x x x not s e l e c t e d not s e l e c t e d i p a r * 2 l l x l x x not select e d not select e d loa d cr re gis t er l l r e a d r e a d i cc1 , i cc2 l h l h l h r e a d h i g h - z i cc1 , i cc2 h l h i g h - z r e a d i cc1 , i cc2 l l writ e writ e i cc1 , i cc2 l h x l l h writ e not writ e/ hi - z i cc1 , i cc2 h l not writ e/ h i - z writ e i cc1 , i cc2 l h h h x x high - z high - z i cc1, i cc2 n o te : 1 . x = h o r l 2. dpd is ena b l e w h e n cr re gist er a4 is ?0?; ot her w i s e , par is ena ble pr el imin ar y (november, 2004, version 0. 1) 4 amic technology , corp.
a64e06161 cap acita nce (t a = 2 5 c, f = 1. 0mhz) sy m b o l p a ram e t e r m i n . ma x . u n i t conditi ons c in * i nput cap a cit a n c e - 6 pf v in = 0 v c i/o * i nput / o ut put c apacit a n c e - 6 pf v i/o = 0v * t hese param et ers are samp led a nd not 1 0 0 % t e st ed. initializ ation t he a64e061 6 1 is init ia lize d i n t he po w e r-on seque nce acc o rdin g t o t he f o llo w i ng. 1. t o s t abilize i n t e rnal circ uits, a fter turning on t he po w e r, a 20 0 s or longer w a it t i me must prece de an y si gnal t o ggl ing. 2. af t e r t he w a it t i me, it can be n o rmal op erat i o n. po w e r on ch art vcc vcc(mi n ) ce zz 20 0us wait time n o r m al o p er a t i o n not e s: 1. f o llo w i ng p o w e r ap plicat i on, make ce high lev e l dur i ng t he w a it t i me 200 us int e rv al. 2. af t e r po w e r on seq uenc e, t he norm a l op er at ing zz must keep at high. standby mode state mac h ines power on in itia l sta t e a c ti v e m ode par mode (12m/8 m/4m bi ts) standny mode dpd mode (data inval i d ) wa i t 200us ce = v ih ce = v il zz = v ih ce = v il zz = v ih ce = v ih zz = v ih ce = v ih zz = v il ce = v ih , zz = v il ce = v ih , zz = v il ce = v ih , zz = v il ce = v il , zz = v ih hb or/and l b = v il ce = v ih , zz = v ih ce = v ih , zz = v ih note: dpd is ena ble w h en c r regist er a4 i s ?0?; ot her w i s e , par is enab le. pr el imin ar y (november, 2004, version 0. 1) 5 amic technology , corp.
a64e06161 con f igura t ion regis t er t he conf igur at ion r egist er (cr) d e f i n e s ho w t h e a64e06161 operat es and w h ether page mode read accesses ar e permit t ed. t he reg i st er is aut omat ica l l y load ed w i t h d e f ault set t i n g durin g po w e r on an d can b e upd at ed an yt i m e w h il e t he device is op erat ing in a n o rma l st at e. cr regis t er des c ription rese r v ed p a g e t c r zz en ab l e deep sl eep a r r a y on / o ff o n zz p a r top/bottom sel ecti o n p a r m e mo r y sel ecti o n a19 - a8 a7 a6 a5 a4 a3 a2 a1 a0 b i t ( s ) n a m e deser v e d a19 - a8 reserved reserved , all mu st b e se t to ?0 ? 7 page mo de o n / o f f 0 - page mod e disabl ed (def ault ) 1 - page mod e enabl ed 6, 5 t e mperat ure c o mpe n sat ed r egist er sect ion 11 - + 8 5 c (de f ault ) 00 - + 7 0 c 01 - + 4 5 c 10 - + 1 5 c 4 zz enab le de ep s l eep 0 - dpd mode enab led 1 - dpd mode disab l ed (d ef a u lt ) 3 array on /off o n zz 0 - par mode (def ault ) 1 - rms mode 2 par t op/ bot t o m half select i o n 0 - bot t o m (def ault ) 1 - t op 1 - 0 par memor y select i on 01 - 3/ 4 arra y ( 12m) 10 - 1/ 2 arra y ( 8 m) 11 - 1/ 4 arra y ( 4 m) pr el imin ar y (november, 2004, version 0. 1) 6 amic technology , corp.
a64e06161 cr regis t er upda te ? ti ming wav e form t wc ei ght lower- o r der addr es s bi ts ( a 7- a0) defi ne par regi s t er t cw t wr t zz c e t aw t as t wp t zz w e t zz m i n ce addr ess we zz figure 1 : cr re gis t e r upda te ?timing w a v e form notes: 1. v ih( m a x ) = v ccq + 0. 2v f o r pulse durat i ons les s t han 20ns. 2. v i l (mi n) = -1v f o r pulse d u rat i o n less t han 2 0 n s . 3. overshoot an d unders hoot sp ecif icat io ns are charact e riz ed and ar e not 10 0% t e st ed. 4. t y pic a l val ues are inclu ded f o r ref e rence o n l y and ar e no t guarant e ed o r t e st ed. t y p i c a l valu es are measure d at v cc = v cc(t y p.) an d t a = 2 5 c. 5. t he t i ming val ues f o r t he c r regist er upd a t e are sho w n i n t he ?part i a l a rra y m ode t i ming? t abl e a nd ? a c char act e ris t ics? t able. prel iminary (november, 2004, version 0. 1) 7 amic technology , corp.
a64e06161 page mode des c ription t he page mode op erat io n t a kes adv ant ag e of t he f a ct that adjac ent ad dre ss can be rea d in short e r pe riod of t i me t han rand om ad dr esses. w r it e oper at ions do n o t sup p o rt compara b l e page mod e f unct i on alit y. t h e page mod e oper at ion c an be e n a b le d a n d dis abl ed in t he c r reg i st er . i f t he cr regist er bit a7 is set t o a ?1?, page mode o perat i on i s ena ble d . t he a64e061 61 prov ides f o llo w i n g op er at ion mo de f o r reduci ng p o w e r: 1. deep p o w e r d o w n (dpd) mo de 2. reduc e memo r y size (rms) mode 3. part ial arra y r e f r esh (par) mode 4. t e mperat ure c o mpe n sat ed r e f r esh (t cr) mode 1. deep po w e r do w n (dpd) mo d e i n t h is mode, the int e rn al ref r esh is t u rned of f and all dat a int egrit y of t he arra y is lost . deep po w e r dow n (dp d ) mod e is ent er ed b y zz lo w a nd k eep 1 0us w i t h a4 r e gist er b i t set t o a ? 0?. t he device st a y s in t he deep po w e r do w n (dp d ) mode unt il zz is driven hi gh. i f t he a4 register bit is set equ al t o ?1?, deep p o w e r do w n (dp d ) mode w i ll not be act i vat ed. onc e t he a64e 06 1 61 e x it s t he d eep po w e r d o w n (dpd) mode, t he cont ent of t he cr regist er is dest r o y e d and t he cr regist e r w o u l d go int o t he def ault stat e upon n o rma l oper at ion. 2. red u ce me mo r y si ze (rms) mo d e i n t h is mode, the a64e0 6 1 6 1 can be operat ed as a reduc ed size dev ice. f o r exampl e, one ca n o perat e t h e 1 6 m a64e0 616 1 as a 4m or 8m memor y b l ock. reduce mem o r y size (rms) mode ca n be e n able d b y hav in g t he appr opri a t e set t i ng in t h e cr regist er. t he mod e is ef f e ct ive once zz goes h i gh and remains i n t he red u ce me mor y siz e (r ms) mode u n t il f u ll arra y rest or e d b y set t i ng t he cr reg i st e r agai n. at po w e r on, all f our sect i on o f t he devic e are act i vat ed an d t he a64e0 616 1 ent er int o it s def ault st at e of f u ll memor y siz e and ref r es h space. variable add r ess spa ce ? addre ss pattern s pa rtia l a rray re fres h mode ( a 3 =0 , a 4 = 1 ) a2 a 1 , a0 r e f r e s h s e c t i o n ad d r e s s s i z e d e n s i t y 0 11 one-fourth of the die 00000h - 3ffffh (a19 = a18 = 0) 256k 16 4m 0 10 half of the die 00000h - 7ffffh (a19 = 0) 512k 16 8m 0 01 t h ree-f ourt h s of t he die 00000h - bffffh (a19 : a18 11) 768k 16 12m 1 11 one-fourth of the die c0000h - ffffh (a19 = a18 = 1) 256k 16 4m 1 10 half of the die 80000h - fffffh (a19 = 1) 512k 16 8m 1 01 t h ree-f ourt h s of t he die 40000h - fffffh (a19: a18 00) 768k 16 12m red u ced mem o ry si ze mo d e ( a 3 = 1, a 4 = 1) 0 11 one-fourth of the die 00000h - 3ffffh (a19 = a18 = 0) 256k 16 4m 0 10 half of the die 00000h - 7ffffh (a19 = 0) 512k 16 8m 0 01 t h ree-f ourt h s of t he die 00000h - bffffh (a19 : a18 11) 768k 16 12m 1 11 one-fourth of the die c0000h - ffffh (a19 = a18 = 1) 256k 16 4m 1 10 half of the die 80000h - fffffh (a19 = 1) 512k 16 8m 1 01 t h ree-f ourt h s of t he die 40000h - fffffh (a19 : a18 00) 768k 16 12m prel iminary (november, 2004, version 0. 1) 8 amic technology , corp.
a64e06161 memor y blo ck spilt bottom address range 0 1 0 1 0 1 0 1 1/4 address space refresh active address space: a0-a17 a<18,19> = <0,0> 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1/2 address space refresh active address space: a0-a18 a<19> = <0> full address space refresh active address space: a0-a19 a<18,19> = 3/4 address space refresh active address space: a0-a19 a<18,19> = <0,0>,<1,0>,<0,1> top address range 1/4 address space refresh active address space: a0-a17 a<18,19> = <1,1> 3/4 address space refresh active address space: a0-a19 a<18,19> = <1,0>,<0,1>,<1,1> full address space refresh active address space: a0-a19 a<18,19> = 1/2 address space refresh active address space: a0-a18 a<19> = <1> prel iminary (november, 2004, version 0. 1) 9 amic technology , corp.
a64e06161 3 . pa rtia l a r ray re fresh (p a r ) mode i n t h is mod e , cust omers ca n t u rn of f sect io n of a64e0 6 1 61 in st and-b y mod e t o save st and b y curre nt . t h e a64e06 16 1 is divid ed i n t o f our 4m sect ions allo w i ng cert a i n sect io n t o be act i ve. t he arra y part i t i o n t o be ref r esh ed i s det ermin ed b y t he respect i v e bit in t he cr r egist er. w hen zz is active lo w , onl y t he p o rt io n of t he arra y t hat is set in the cr reg i st er is ref r eshe d an d t he dat a is keep at a c e rt ain sect io n of memor y . t he part ial arra y ref r esh (pa r ) mode is o n l y avail abl e dur in g st andb y t i m e ( zz low ) . on ce zz is t u rned high, t he a64 e 061 61 go es back t o opera t ing in f u ll arr a y ref r esh. f o r part ial arra y ref r esh (par ) mode t o b e act i vat ed, t he r egist er b i t , a4 must be set t o a ?1? valu e. t o chan ge t he ad dress space of t he part ial arra y ref r esh (pa r ) mode, t he c r regist er mu st be updat e d usin g t he cr regist er descri p t i on. i f t he c r regist er is n o t upd at ed af t e r po w e r o n , t he a64e0 616 1 w i l l be in it s def a u lt st at e and t h e w h ol e memor y arra y w i l l be ref r eshe d. partial arra y refresh ? e n tr y / exit part i a l arr a y mode/ deep power d o wn mode ce or ub / l b 1us suspen d t cd r t r zz f i g u r e 2: parti a l a r ra y refr es h ? en try / exi t partial arr a y mode timings pa ram e t e r d e s c r i p t i o n m i n . ma x . u n i t t zz w e zz low to we low 1 s t cdr chip deselect to zz low 0 s t r operat io n rec o ver y t i me (d eep po w e r do w n m o d e onl y) 200 s t zzmin deep p o w e r d o w n mo de t i me 10 s t zzce zz low to ce low 0 1 s t zzbe zz l o w to ld ub / low 0 1 s notes: 1. oe and t he dat a pins ar e in a ?don?t car e ? st at e w h ile t h e de vice is in part i a l arra y mo de. 2. all ot her t i mi ng par amet ers are as sho w n i n t he s w it chi n g charact e rist ics sect ion. 3. t r appli e s on l y i n t he de ep po w e r do w n m ode. 4. t e mp eratu r e co mp en sat ed refre s h (tcr) mo d e i n t h is mode, t he hi dde n ref r e s h rat e can b e opt imize d f o r t h e oper at ing t e m p erat ure. at hi g her t e mp erat ur e, t he dram c e ll must be ref r eshed more of t e n t han at lo w e r t e mperat ure. b y set t i ng t he t e mperat ur e of oper at ion i n cr regist er, t h e re fre s h ra te ca n be o p t i m i z e d to mee t th e l o w sta ndby current at giv en op erat in g t e mperat ur e. t here are f our selections (+15 c, +45 c, +70 c, +85 c) in t he cr regist er descript i on. prel iminary (november, 2004, version 0. 1) 10 amic technology , corp.
a64e06161 av oid timin g f o llo w i ng f i g u r e 3 is sho w yo u an ab norma l t i ming w h ich is not supp ort ed on sup e r ram . ce address less than 30ns we not e : address = a0 ~ a19 under cr reg i st er a7 = 0 address = a2 ~ a19 under c r regist er a7 = 1 figure 3 ope r a t ion w h e n pa ge mode is ena b le d t he max i mum ce pulse w i dt h sh ould not e x ce e d 10s t o acc o mmodat e or der l y sch ed uli ng o f ref r esh (f igure 4). ce 10us t cem not e : t i ming const r ai nt s w h e n pag e mode i s enab led. figure 4 : t i m i ng c ons tra i nt for t ce m prel iminary (november, 2004, version 0. 1) 11 amic technology , corp.
a64e06161 ac char ac te ristics (t a = 0 c to + 70 c or -25 c to 85 c, vcc = 1.7v to 1 . 95v, vcc q = 1. 7v to vcc gnd = 0v) symb o l p a r a mete r - 7 0 - 8 5 un i t m i n . m a x . m i n . m a x . read c y c l e t rc read c y c l e t i me 70 100 00 85 100 00 ns t sk ew a d d r e s s ske w - 1 0 - 1 0 n s t aa address acces s t i m e - 7 0 - 8 5 n s t ac e chip e nab le a ccess t i me - 70 - 85 ns t be b y t e en abl e access t i me - 35 - 45 ns t oe out put enabl e t o out put valid - 35 - 45 ns t clz chip e nab le t o out put in lo w z 5 - 5 - ns t blz b y t e en abl e t o out put in lo w z 5 - 5 - ns t olz out put enabl e t o out put in lo w z 5 - 5 - ns t chz chip d i sab l e t o out put in high z 0 14 0 14 ns t bhz b y t e dis a b l e t o out put in high z 0 14 0 14 ns t ohz out put disab l e t o out put in high z 0 14 0 14 ns t oh out put hold f r o m address ch ang e 10 - 10 - ns t as c address set u p t o ce lo w 0 - 0 - n s t ah c address h o ld t i me f r om ce high 0 - 0 - n s t ce h ce high pu lse w i t h 1 0 - 1 0 - n s t pc page r ead c ycle t i me 25 - 25 - ns t pa a page acc e ss t i me - 25 - 25 ns t np p c normal t o pa g e rea d c y cle t i me - 10 - 10 s w r it e c y cl e t wc w r it e c y cl e t i me 70 100 00 85 100 00 ns t sk ew a d d r e s s ske w - 1 0 - 1 0 n s t cw chip e nab le t o end of w r it e 70 - 85 - ns t bw b y t e en abl e t o end of w r it e 60 - 70 - ns t as a d d r e s s set u p t i m e 0 - 0 - n s t aw address va lid t o end of w r it e 70 - 85 - ns t wp w r it e pulse w i dt h 50 - 60 - ns t wr w r it e recover y t i me 0 - 0 - ns t wh z w r it e t o out put in high z - 14 - 14 ns t dw dat a t o w r it e t i me overlap 30 - 35 - ns t dh dat a hol d f r om w r it e t i me 0 - 0 - ns t ow out put act i ve f r om end of w r it e 5 - 5 - ns t as c address set u p t o ce lo w 0 - 0 - n s t ah c address h o ld t i me f r om ce high 0 - 0 - n s t ce h ce high pu lse w i t h 1 0 - 1 0 - n s t weh we high p u lse w i t h 1 0 - 1 0 - n s t ce m maximum ce pulse w i dt h - 1 0 - 1 0 s no te : t chz , t bhz and t ohz and t wh z are d e f i ne d as t he t i me at w h ich t h e out pu t s achiev e t h e ope n circu i t condit i on an d a r e not ref e rred t o out put volt a ge l e vels. prel iminary (november, 2004, version 0. 1) 12 amic technology , corp.
a64e06161 timing wav e forms read c ycl e 1 ( 1 , 2, 4, 6) address d out ce t skew t rc t skew t rc t aa t oh t aa t oh t asc read c ycl e 2- 1 ( 1 , 3, 6) t rc t rc t sk e w t skew t as c t aa t ahc t ceh t asc t ahc t aa t ace t cl z 5 t be t bl z 5 t oe t olz 5 t chz 5 t bhz 5 t ohz 5 t ace t cl z 5 t bl z 5 t oe t ol z 5 t oh z 5 t bhz 5 t ch z 5 addr es s ce hb lb , oe d out t be prel iminary (november, 2004, version 0. 1) 13 amic technology , corp.
a64e06161 read c ycl e 2- 2 ( 1 , 3, 6) t rc t rc t skew t skew t asc t ahc t ace t clz 5 t be t blz 5 t oe t olz 5 t bhz 5 t ohz 5 t blz 5 t oe t olz 5 t ohz 5 t bhz 5 t chz 5 address ce hb lb , oe d out t be t skew t aa t aa n o t e s : 1 . we is high f o r re a d c y c l e. 2. device is co nt i nuo usl y en abl e d ce = v il , hb = v il and, or lb = v il . 3. address val i d prior t o or coi n cident w i t h ce an d ( hb and, or lb ) t r ansit ion l o w . 4. oe = v il . 5. t r ansit ion is measur ed 5 0 0 m v f r om st eady st at e. t h is paramet er is sam p led and n o t 1 00% t e st ed. 6. zz is high f o r re a d c y c l e. timing wav e forms w o rd s pag e read c y cl e t i m i n g ch art addr es s a2 ~a1 9 t ske w t pc t pc t np pc t rc t sk e w t pc t ch z t oh t paa t ac e t oh z t bh z t oe t be pa ge add r es s (a 0 ~ a 1 ) ce i/ o ( o ut pu t ) oe, hb , l b a n a n+ 1 a n+ 2 a n+ 3 q n+ 2 q n+ 1 q n q n+3 t oh t paa t oh t pa a t oh t as c t ahc prel iminary (november, 2004, version 0. 1) 14 amic technology , corp.
a64e06161 timing wav e forms (con tinued ) w r i t e cycl e 1- 1 (6 ) (write ena b le controlle d) t wc t wc t skew t skew t asc t ahc t ceh t asc t ahc address ce hb lb , t aw t cw t aw t cw t bw t bw t wr 3 t wr 3 t as 1 t wp 2 t dw t dh t wh z 4 t ow t wp 2 t as 1 t wh z 4 t dh t dw t ow we data in data out w r i t e cycl e 1- 2 (6 ) (write ena b le controlle d) t wc t wc t skew t skew t asc t ahc address ce hb lb , t bw t bw t wr 3 t wr 3 t as 1 t wp 2 t dw t dh t wh z 4 t ow t wp 2 t as 1 t wh z 4 t dh t dw t ow we data in data out t weh t skew prel iminary (november, 2004, version 0. 1) 15 amic technology , corp.
a64e06161 timing wav e forms (con tinued ) w r i t e cycl e 2- 1 (6 ) (chip ena b le controlle d) t wc t wc t skew t skew t asc t ceh t asc address ce hb lb , t aw t cw 2 t aw t cw 2 t bw t wp t dw t dh t wh z 4 t ow t wp t whz 4 t dh t dw t ow we data in data out t ahc t ahc t bw t wr 3 t wr 3 timing wav e forms w r i t e cycl e 3- 1 (6 ) (by t e ena b le controlle d) t wc t wc t skew t skew t asc t ceh t asc address ce hb lb , t aw t cw t aw t cw t bw 2 t wp t dw t dh t wh z 4 t ow t wp t whz 4 t dh t dw t ow we data in data out t ahc t ahc t bw 2 t wr 3 t wr 3 t as 1 t as 1 prel iminary (november, 2004, version 0. 1) 16 amic technology , corp.
a64e06161 w r i t e cycl e 3- 2 (6 ) (by t e ena b le controlle d) t wc t wc t skew t skew t asc address ce hb lb , t aw t bw 2 t wp t dw t dh t wh z 4 t ow t wp t whz 4 t dh t dw t ow we data in data out t ahc t bw 2 t wr 3 t wr 3 t as 1 t as 1 t skew no te s: 1 . t as is me asure d f r om t he addr ess valid t o t h e begi nni ng of w r it e. 2. a w r it e occurs durin g t he ove r lap (t wp , t bw ) o f a low ce , we and ( hb and, or lb ). 3. t wr is measured f r om t he ear liest of ce or we or ( hb and, or lb ) goin g high t o t he e n d of t he w r it e cycl e. 4. oe level is hi gh or lo w . 5. t r ansit ion is measur ed 5 0 0 m v f r om st eady st at e. t h is paramet er is sam p led and n o t 1 00% t e st ed. 6. zz is high f o r w r it e c y c l e. ac tes t co nditions i nput pulse l e v els vccq * 0. 2 t o vccq * 0. 8 i nput rise an d f a ll t i me 2 ns (10% t o 9 0%) i nput and out p ut t i ming ref e rence l e vels 0. 5 * vccq out put loa d see f i gur es 5 30pf out test point 2.7k ? vccq 2.7k ? figure 5 . o u tp ut loa d circ ui t prel iminary (november, 2004, version 0. 1) 17 amic technology , corp.
a64e06161 ordering information part no . a c c e ss t i me ( n s) op erati n g cu r r en t max. (m a ) d e e p p o we r d o wn mode sta ndb y current max. ( a) pack ag e a64e0 616 1 g - 7 0 7 0 1 5 1 0 4 8 b m i n i bga a64e0 616 1 g - 8 5 8 5 1 2 1 0 4 8 b m i n i bga a64e0 616 1g-70i 7 0 1 5 1 0 4 8 b m i n i bga a64e0 616 1g-85i 8 5 1 2 1 0 4 8 b m i n i bga not e : -i is f o r indust r ial oper at i ng t e mper at ure range pr el imin ar y (november, 2004, version 0. 1) 18 amic technology , corp.
a64e06161 packag e information 48l d csp (6 x 8 mm) outline dimensions unit : mm (4 8 tfbg a ) a 1 a b c d e f g h top view ball#a1 corner side view c seating plane a a b c d e f g h 1 234 56 1 2 3 4 5 6 c 0.10 c s 0.25 s a b b (48x) bottom view ball*a1 corner e e 1 e b e d 1 d a 0.20(4x) 0.10 c dim e ns ions in m m sy m bol min. nom. max . a - - - - - - 1.20 a 1 0 . 20 0. 25 0. 30 d 5 . 90 6. 00 6. 10 e 7 . 90 8. 00 8. 10 d 1 - - - 3.75 - - - e 1 - - - 5.25 - - - e - - - 0.75 - - - b 0 . 30 0. 35 0. 40 note: 1. t h e ball diamet er, ball pit c h , s t and-off & pack a ge t h ick n ess are different from jed e c spec mo192 (low pr ofile bga family). 2. primary da t u m c and seating plane are defined by t h e s p herical crowns of t h e s o lder balls. 3. di mensi o n b i s measured at t h e maxi mum. t h ere shall be a minim u m clearance of 0.25m m be t w een t h e edge of t h e solder ball and t h e b o dy edge. 4. ball pad opening of su bst ra t e is 0 . 3mm (sm d ) sugges t to design t h e pcb land si ze as 0 . 3mm (nsmd) pr el imin ar y (november, 2004, version 0. 1) 19 amic technology , corp.

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