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1 ads7862 dual 500khz, 12-bit, 2 + 2 channel simultaneous sampling analog-to-digital converter features l 4 input channels l fully differential inputs l 2 m s total throughput per channel l guaranteed no missing codes l parallel interface l 1mhz effective sampling rate l low power: 40mw applications l motor control l multi-axis positioning systems l 3-phase power control description the ads7862 is a dual 12-bit, 500khz analog-to- digital converter (a/d) with 4 fully differential input channels grouped into two pairs for high speed simulta- neous signal acquisition. inputs to the sample-and-hold amplifiers are fully differential and are maintained dif- ferential to the input of the a/d converter. this provides excellent common-mode rejection of 80db at 50khz which is important in high noise environments. the ads7862 offers parallel interface and control in- puts to minimize software overhead. the output data for each channel is available as a 12-bit word. the ads7862 is offered in an tqfp-32 package and is full specified over the C40 c to +85 c operating range. ads7862 ? 1998 burr-brown corporation pds-1475b printed in u.s.a. may, 2000 sar interface conversion and control output registers comp convst busy rd cs data output 12 clock a0 cdac internal 2.5v reference s/h amp s/h amp ch a0 ch a0+ ref in ch a1 ch a1+ sar comp cdac mux mux ch b0 ch b0+ ch b1 ch b1+ ref out international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 ads7862 for most current data sheet and other product information, visit www.burr-brown.com sbas101
2 ads7862 specifications all specifications t min to t max , +v a = +v d = +5v, v ref = internal +2.5v and f clk = 8mhz, f sample = 500khz, unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. ads7862y ads7862yb parameter conditions min typ max min typ max units resolution 12 [ bits analog input input voltage range-bipolar v center = internal v ref at 2.5v Cv ref +v ref [[ v absolute input range +in C0.3 v cc + 0.3 v Cin C0.3 v cc + 0.3 v input capacitance 15 [ pf input leakage current clk = gnd 1 [ m a system performance no missing codes 12 [ bits integral linearity 0.75 2 0.5 1 lsb integral linearity match 0.5 1 [[ lsb differential linearity 0.75 0.5 1 lsb bipolar offset error referenced to ref in 0.75 3 0.5 2 lsb bipolar offset error match 3 2 lsb positive gain error referenced to ref in 0.15 0.75 0.1 0.5 % of fsr positive gain error match 2 1 lsb negative gain error referenced to ref in 0.15 0.75 0.1 0.5 % of fsr negative gain error match 2 1 lsb common-mode rejection ratio at dc 80 [ db v in = 1.25vp-p at 50khz 80 [ db noise 120 [ m vrms power supply rejection ratio 0.5 2 [[ lsb sampling dynamics conversion time per a/d 1.75 [ m s acquisition time 0.25 [ m s throughput rate 500 [ khz aperture delay 3.5 [ ns aperture delay matching 100 [ ps aperture jitter 50 [ ps small-signal bandwidth 40 [ mhz dynamic characteristics total harmonic distortion v in = 2.5vp-p at 100khz 75 [ db sinad v in = 2.5vp-p at 100khz 71 [ db spurious free dynamic range v in = 2.5vp-p at 100khz C78 [ db channel-to-channel isolation v in = 2.5vp-p at 100khz C80 [ db voltage reference internal 2.475 2.5 2.525 [[[ v internal drift 25 [ ppm/ c internal noise 50 [ m vp-p internal source current 2 [ ma internal load rejection 0.005 [ mv/ m a internal psrr 65 [ db external voltage range 1.2 2.5 2.6 [[[ v input current 0.05 1 [[ m a input capacitance 5 [ pf digital input/output logic family cmos [ logic levels: v ih i ih = +5 m a 3.0 +v dd + 0.3 [[ v v il i il = +5 m a C0.3 0.8 [[ v v oh i oh = C500 m a 3.5 [ v v ol i ol = 500 m a 0.4 [ v external clock 0.2 8 [[ mhz data format binary twos complement [ power supply requirements power supply voltage, +v 4.75 5 5.25 [[[ v quiescent current, +v a 58 [[ ma power dissipation 25 40 [[ mw [ specifications same as ads7862y.
3 ads7862 pin name description 1 ref in reference input 2 ref out +2.5v reference output. connect directly to ref in (pin 1) when using internal reference. 3 agnd analog ground 4+v a analog power supply, +5vdc. connect directly to digital power supply (pin 24). decouple to analog ground with a 0.1 m f ceramic capacitor and a 10 m f tantalum capacitor. 5 db11 data bit 11, msb 6 db10 data bit 10 7 db9 data bit 9 8 db8 data bit 8 9 db7 data bit 7 10 db6 data bit 6 11 db5 data bit 5 12 db4 data bit 4 13 db3 data bit 3 14 db2 data bit 2 15 db1 data bit 1 16 db0 data bit 0, lsb 17 busy high when a conversion is in progress. 18 convst convert start 19 clock an external cmos-compatible clock can be applied to the clock input to synchronize the conversion pro- cess to an external source. the clock pin controls the sampling rate by the equation: clock 16 ? f sample . 20 cs chip select 21 rd synchronization pulse for the parallel output. during a read operation, the first falling edge selects the a register and the second edge selects the b register, a0, then controls whether input 0 or input 1 is read. 22 a0 on the falling edge of convert start, when a0 is low channel a0 and channel b0 are converted and when it is high, channel a1 and channel b1 are converted. during a read operation, the first falling edge selects the a register and the second edge selects the b of rd register, a0, then controls whether input 0 or input 1 is read. 23 dgnd digital ground. connect directly to analog ground (pin 3). 24 +v d digital power supply, +5vdc 25 ch b1+ non-inverting input channel b1 26 ch b1C inverting input channel b1 27 ch b0+ non-inverting input channel b0 28 ch b0C inverting input channel b0 29 ch a1C inverting input channel a1 30 ch a1+ non-inverting input channel a1 31 ch a0C inverting input channel a0 32 ch a0+ non-inverting input channel a0 pin configuration top view pin descriptions absolute maximum ratings analog inputs to agnd: any channel input ........ C0.3v to (+v d + 0.3v) ref in ............................. C0.3v to (+v d + 0.3v) digital inputs to dgnd .......................................... C0.3v to (+v d + 0.3v) ground voltage differences: agnd, dgnd ................................... 0.3v +v d to agnd ......................... C0.3v to +6v power dissipation .......................................................................... 325mw maximum junction temperature ................................................... +150 c operating temperature range ........................................ C40 c to +85 c storage temperature range ......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifi- cations. ref in ref out agnd +v a db11 db10 db9 db8 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 +v d dgnd a0 rd cs clock convst busy db7 db6 db5 db4 db3 db2 db1 db0 9 10111213141516 ch a0+ ch a0 ch a1+ ch a1 ch b0 ch b0+ ch b1 ch b1+ 32 31 30 29 28 ads7862 27 26 25
4 ads7862 package/ordering information maximum maximum relative gain package specification accuracy error drawing temperature package ordering transport product (lsb) (%) package number (1) range marking (2) number (3) media ads7862y 2 0.75 tqfp-32 351 C40 c to +85 c a62 ads7862y/250 tape and reel ads7862y "" """ " ads7862y/2k5 tape and reel ads7862yb 1 0.5 tqfp-32 351 C40 c to +85 c a62 ads7862yb/250 tape and reel ads7862yb "" """ " ads7862yb/2k5 tape and reel note: (1) for detail drawing and dimension table, please see end of data sheet or package drawing file on web. (2) performance grade information is marked on the reel. (3) models with a slash(/) are available only in tape and reel in quantities indicated (e.g. /250 indicates 250 un its per reel, /2k5 indicates 2500 devices per reel). ordering 2500 pieces of ads7862y/2k5 will get a single 2500-piece tape and reel. for detailed tape and reel mechan ical information, refer to the www.burr-brown.com web site under applications and tape and reel orientation and dimensions. basic operation ref in ref out agnd +v a db11 db10 db9 db8 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 +v d dgnd a0 rd cs clock convst busy address select read input chip select clock input conversion start busy output ads7862y 10 f + 0.1 f +5v analog supply + 32 31 30 29 28 27 26 25 ch a0+ ch a0 ch a1+ ch a1 ch b0 ch b0+ ch b1 ch b1+ 9 10 11 12 13 14 15 16 db7 db6 db5 db4 db3 db2 db1 db0
5 ads7862 frequency spectrum (4096 point fft; f in = 199.9khz, ?.5db) frequency (khz) 0 ?0 ?0 ?0 ?0 ?00 ?20 amplitude (db) 0 62.5 125 250 187.5 typical performance curves at t a = +25 c, +v a = +v d = +5v, v ref = internal +2.5v and f clk = 8mhz, f sample = 500khz, unless otherwise noted. frequency spectrum (4096 point fft; f in = 99.9khz, ?.5db) frequency (khz) 0 ?0 ?0 ?0 ?0 ?00 ?20 amplitude (db) 0 62.5 125 250 187.5 change in signal-to-noise ratio and signal-to-(noise+distortion) vs temperature temperature ( c) 0.25 0.2 0.15 0.1 0.05 0 ?.05 ?.1 ?.15 ?.2 ?.25 delta from +25 c (db) ?0 25 85 snr sinad change in spurious free dynamic range and total harmonic distortion vs temperature temperature ( c) 0.65 0.45 0.25 0.05 ?.15 ?.35 ?.55 ?.75 0.65 0.45 0.25 0.05 ?.15 ?.35 ?.55 ?.75 sfdr delta from +25 c (db) thd delta from +25 c (db) ?0 25 85 sfdr thd change in positive gain match vs temperature (maximum deviation for all four channels) temperature ( c) 0.6 0.5 0.4 0.3 0.2 0.1 0 change in positive gain match (lsb) ?0 25 85 150 signal-to-noise ratio and signal-to-(noise+distortion) vs input frequency 10k 100k 1k 1m input frequency (hz) snr and sinad (db) 74 72 70 68 66 64 76 sinad snr
6 ads7862 integral linearity error vs code hex btc code 1 0.8 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 ?.8 ? ile (lsb) 800 000 7ff typical of all four channels typical performance curves (cont.) at t a = +25 c, +v a = +v d = +5v, v ref = internal +2.5v and f clk = 8mhz, f sample = 500khz, unless otherwise noted. change in negative gain match vs temperature (maximum deviation for all four channels) temperature ( c) 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 change in negative gain match (lsb) ?0 25 85 150 change in reference voltage vs temperature temperature ( c) 2.51 2.505 2.5 2.495 2.49 2.485 change in reference (v) ?0 25 85 150 change in bipolar zero vs temperature temperature ( c) 0.75 0.5 0.25 0 ?.25 ?.5 ?.75 change in bipolar zero (lsb) ?0 25 a channel b channel 85 150 change in bpz match vs temperature temperature ( c) 1 0.75 0.5 0.25 0 change in bipolar zero match (lsb) ?0 25 85 150 change in cmrr vs temperature temperature ( c) 86 85 84 83 82 81 80 79 78 change in cmrr (db) ?0 ? 25 55 85
7 ads7862 differential linearity error vs code hex btc code typical of all four channels 1 0.75 0.5 0.25 0 ?.25 ?.5 ?.75 ? dle (lsb) 800 000 7ff typical performance curves (cont.) at t a = +25 c, +v a = +v d = +5v, v ref = internal +2.5v and f clk = 8mhz, f sample = 500khz, unless otherwise noted. integral linearity error match vs code channel a0/channel a1 (same converter, different channels) hex btc code 0.25 0.2 0.15 0.1 0.05 0 ?.05 ?.1 ?.15 ?.2 ?.25 ile (lsb) 800 000 7ff integral linearity error match vs code channel a0/channel b1 (different converter, different channels) hex btc code 0.25 0.2 0.15 0.1 0.05 0 ?.05 ?.1 ?.15 ?.2 ?.25 ile (lsb) 800 000 7ff integral linearity error vs temperature positive ile negative ile temperature ( c) 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 ?.8 change in ile (lsb) ?0 25 85 150 differential linearity error vs temperature temperature ( c) 0.8 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 ?.8 dle error (lsb) ?0 25 positive dle negative dle 85 150 integral linearity error match vs temperature channel a0/channel b0 (different converter, different channels) temperature ( c) 0.19 0.18 0.17 0.16 0.15 0.14 0.13 0.12 change in ile match (lsb) ?0 25 85 150
8 ads7862 reference under normal operation, the ref out pin (pin 2) should be directly connected to the ref in pin (pin 1) to provide an internal +2.5v reference to the ads7862. the ads7862 can operate, however, with an external reference in the range of 1.2v to 2.6v for a corresponding full-scale range of 2.4v to 5.2v. the internal reference of the ads7862 is double-buffered. if the internal reference is used to drive an external load, a buffer is provided between the reference and the load ap- plied to pin 2 (the internal reference can typically source 2ma of currentload capacitance should not exceed 100pf). if an external reference is used, the second buffer provides isolation between the external reference and the cdac. this buffer is also used to recharge all of the capacitors of both cdacs during conversion. analog input the analog input is bipolar and fully differential. there are two general methods of driving the analog input of the ads7862: single-ended or differential (see figures 1 and 2). when the input is single-ended, the Cin input is held at the common-mode voltage. the +in input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode +v ref ) and the (common-mode Cv ref ). the value of v ref determines the range over which the common-mode voltage may vary (see figure 3). when the input is differential, the amplitude of the input is the difference between the +in and Cin input, or: (+in) C (Cin). the peak-to-peak amplitude of each input is 1/2v ref around this common voltage. however, since the inputs are 180 out of phase, the peak-to-peak amplitude of the differential voltage is +v ref to Cv ref . the value of v ref also determines the range of the voltage that may be common to both inputs (see figure 4). introduction the ads7862 is a high speed, low power, dual 12-bit a/d converter that operates from a single +5v supply. the input channels are fully differential with a typical common-mode rejection of 80db. the part contains dual 2 m s successive approximation a/ds, two differential sample-and-hold am- plifiers, an internal +2.5v reference with ref in and ref out pins and a high speed parallel interface. there are four analog inputs that are grouped into two channels (a and b) selected by the a0 input (a0 low selects channels a0 and b0, while a0 high selects channels a1 and b1). each a/d converter has two inputs (a0 and a1 and b0 and b1) that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. the part accepts an analog input voltage in the range of Cv ref to +v ref , centered around the internal +2.5v reference. the part will also accept bipolar input ranges when a level shift circuit is used at the front end (see figure 7). a conversion is initiated on the ads7862 by bringing the convst pin low for a minimum of 15ns. convst low places both sample-and-hold amplifiers in the hold state simultaneously and the conversion process is started on both channels. the busy output will then go high and remain high for the duration of the conversion cycle. depending on the status of the a0 pin, the data will either reflect a conversion of channel 0 (a0 low) or channel 1 (a0 high). the data can be read from the parallel output bus following the conversion by bringing both rd and cs low. conversion time for the ads7862 is 1.75 m s when an 8mhz external clock is used. the corresponding acquisition time is 0.25 m s. to achieve maximum output rate (500khz), the read function can be performed immediately at the start of the next conversion. note: this mode of operation is described in more detail in the timing and control section of this data sheet. sample-and-hold section the sample-and-hold amplifiers on the ads7862 allow the a/ds to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. the input bandwidth of the sample-and-hold is greater than the nyquist rate (nyquist equals one-half of the sampling rate) of the a/d even when the a/d is operated at its maximum throughput rate of 500khz. the typical small-signal bandwidth of the sample- and-hold amplifiers is 40mhz. typical aperture delay time or the time it takes for the ads7862 to switch from the sample to the hold mode following the convst pulse is 3.5ns. the average delta of repeated aperture delay values is typically 50ps (also known as aperture jitter). these specifications reflect the ability of the ads7862 to capture ac input signals accurately at the exact same moment in time. ads7862 ads7862 single-ended input common voltage ? ref to +v ref peak-to-peak differential input common voltage v ref peak-to-peak v ref peak-to-peak figure 1. methods of driving the ads7862 single-ended or differential.
9 ads7862 figure 3. single-ended input: common-mode voltage range vs v ref . 1.0 1.5 1.2 2.0 2.5 2.6 3.0 v ref (v) common voltage range (v) ? 0 1 2 3 4 5 2.7 2.3 4.1 0.9 v cc = 5v single-ended input differential input 1.0 1.5 1.2 2.0 2.5 2.6 3.0 v ref (v) common voltage range (v) ? 0 1 2 3 4 5 4.7 0.3 v cc = 5v 4.05 0.90 figure 2. using the ads7862 in the single-ended and differential input modes. figure 4. differential input: common-mode voltage range vs v ref . in each case, care should be taken to ensure that the output impedance of the sources driving the +in and Cin inputs are matched. otherwise, this may result in offset error, which will change with both temperature and input voltage. the input current on the analog inputs depend on a number of factors: sample rate, input voltage, and source impedance. essentially, the current into the ads7862 charges the inter- nal capacitor array during the sampling period. after this capacitance has been fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance (15pf) to a 12-bit settling level within 2 clock cycles. when the converter goes into the hold mode, the input impedance is greater than 1g w . care must be taken regarding the absolute analog input voltage. the +in input should always remain within the range of gnd C 300mv to v dd + 0.3v. cm +v ref +v ref ? ref single-ended inputs t +in cm voltage cm ? ref cm +1/2v ref differential inputs notes: common-mode voltage (differential mode) = common-mode voltage (single-ended mode) = in? (in+) + (in? 2 the maximum differential voltage between +in and ?n of the ads7862 is v ref . see figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs. t +in ?n cm voltage cm ?/2v ref ?n = cm voltage +v ref ? ref
10 ads7862 three timing diagrams are used to explain the operation of the ads7862. figure 8 shows the timing relationship be- tween the clock, convst (pin 18) and the conversion code (decimal) 8000 7000 6000 5000 4000 3000 2000 1000 0 number of conversions 2044 2045 2046 2047 2048 figure 5. histogram of 8,000 conversions of a dc input. figure 6. test circuits for timing specifications. figure 7. level shift circuit for bipolar input ranges. figure 8. conversion mode. transition noise figure 5 shows a histogram plot for the ads7862 following 8,000 conversions of a dc input. the dc input was set at output code 2046. all but one of the conversions had an output code result of 2046 (one of the conversions resulted in an output of 2047). the histogram reveals the excellent noise performance of the ads7862. bipolar inputs the differential inputs of the ads7862 were designed to accept bipolar inputs (Cv ref and +v ref ) around the internal reference voltage (2.5v), which corresponds to a 0v to 5v input range with a 2.5v reference. by using a simple op amp circuit featuring a single amplifier and four external resis- tors, the ads7862 can be configured to except bipolar inputs. the conventional 2.5v, 5v, and 10v input ranges can be interfaced to the ads7862 using the resistor values shown in figure 7. timing and control the ads7862 uses an external clock (clock, pin 19) which controls the conversion rate of the cdac. with an 8mhz external clock, the a/d sampling rate is 500khz which corresponds to a 2 m s maximum throughput time. data 1.4v test point 3k w 100pf c load t r data voltage waveforms for data rise and fall times t r , and t f . v oh v ol t f r 1 r 2 +in ?n ref out (pin 2) 2.5v 4k w 20k w bipolar input bipolar input r 1 r 2 10v 1k w 5k w 5v 2k w 10k w 2.5v 4k w 20k w opa132 ads7862 convst conversion mode sample hold convert clock t ckh t ckp t 3 t ckl note: the ads7862 will switch from the sample to the hold mode the instant convst goes low regardless of the state of the external clock. the conversion process is initiated with the first rising edge of the external clock following convst going low.
11 ads7862 figure 9. reading and writing to the ads7862 during the same cycle. description analog input full-scale input span Cv ref to +v ref (1) least significant (Cv ref to +v ref )/4096 (2) bit (lsb) +full scale 4.99878v 0111 1111 1111 7ff midscale 2.5v 0000 0000 0000 000 midscale C 1 lsb 2.49878v 1111 1111 1111 fff Cfull scale 0v 1000 0000 0000 800 notes: (1) Cv ref to +v ref around v ref . with a 2.5v reference, this corre- sponds to a 0v to 5v input span. (2) 1.22mv with a 2.5v reference. table i. ideal input voltages and output codes. digital output binary twos complement binary code hex code mode. figure 9, in conjunction with table i, shows the basic read/write functions of the ads7862 and highlights all of the timing specifications. figure 10 shows a more detailed description of initiating a conversion using convst. fig- ure 11 illustrates three consecutive conversions and, with the accompanying text, describes all of the read and write capabilities of the ads7862. the figure 11 timing diagram can be divided into three sections: (a) initiating a conversion (n C 2), (b) starting a second conversion (n C 1) while reading the data output from the previous conversion (n C 2), and (c) starting a third conversion (n) while reading both previous conversions (n C 2 and n C 1). in this sequence, channel 0 is converted symbol description min typ max units t conv conversion time 1.75 m s t acq acquisition time 0.25 m s t ckp clock period 125 5000 ns t ckl clock low 40 ns t ckh clock high 40 ns t 1 cs to rd setup time 0 ns t 2 cs to rd hold time 0 ns t 3 convst low 15 ns t 4 rd pulse width 30 ns t 5 rd to valid data (bus access) 16 25 ns t 6 rd to hi-z delay (bus relinquish) 10 20 ns t 7 time between conversion reads 40 ns t 8 address setup time 250 ns t 9 convst high 20 ns t 10 address hold time 20 ns t 11 convst to busy propagation delay 30 ns t 12 convst low prior to clock rising edge 10 ns t 13 convst low after clock rising edge 5ns t f data fall time 13 25 ns t r data rise time 20 30 ns timing specifications first followed by channel 1. channel 1 can be converted prior to channel 0 if the user wishes by simply starting the conversion process with the a0 pin at logic high (channel 1) followed by logic low (channel 0). t 12 t 13 t 3 t 9 t 11 conversion n conversion n ?1 results conversion n results busy a0 cs rd data conversion n + 1 1 clock convst 2 3 4 5 14 15 16 1 2 3 4 5 14 15 16 t conv t acq t 8 t 4 t 10 t 1 t 5 cha1 chb1 cha0 chb0 t 6 t 2 t 7
12 ads7862 note: all convst commands which occur more than 10ns before the rising edge of cycle ? of the external clock (region ?? will initiate a conversion on the rising edge of cycle ?? all convst commands which occur 5ns after the rising edge of cycle ? or 10ns before the rising edge of cycle 2 (region ?? will initiate a conversion on the rising edge of cycle ?? all convst commands which occur 5ns after the rising edge of cycle ? (region ?? will initiate a conversion on the rising edge of the next clock period. the convst pin should never be switched from high to low in the region 10ns prior to the rising edge of the clock and 5ns after the rising edge (gray areas). if convst is toggled in this gray area, the conversion could begin on either the same rising edge of the clock or the following edge. clock convst cycle 1 cycle 2 t ckp 125ns 10ns 5ns 10ns 5ns a b c figure 10. timing between clock and convst to start a conversion. figure 11. ads7862 timing diagram showing complete functionality. 1 1 1 section a clock convst a0 rd cs data busy time 0 1 2 3 4 5 min 250ns section b section c cha0 chb0 time (seconds) cha1 cha0 4 output-register data of ch0 still stored a0 selects between ch0 and ch1 at output conversion of ch0 low data level tri-state of output conversion of ch0 high data level output active 16 16 a0 = 1 conversion of ch1 min 250ns cs needed only during reading conversion of ch1 chb0 chb1 a0 = 0 conversion of ch0 a0 = 0 conversion of ch0 1st rd after convst cha at output 2nd rd after convst chb at output
13 ads7862 section a conversions are initiated by bringing the convst pin (pin 18) low for a minimum of 5ns (after the 5ns minimum requirement has been met, the convst pin can be brought high). the ads7862 will switch from the sample to the hold mode on the falling edge of the convst command. following the first rising edge of the external clock after a convst low, the ads7862 will begin conversion (this first rising edge of the external clock represents the start of clock cycle one; the ads7862 requires sixteen cycles to complete a conversion). the input channel is also latched in at this point in time. the a0 input (pin 22) must be selected 250ns prior to the convst pin going low so that the correct address will be selected prior to conversion. the busy output will go high immediately following convst going low. busy will stay high through the conversion process and return low when the conversion has ended. after convst has remained low for the minimum time, the ads7862 will switch from the hold mode to the conver- sion mode synchronous to the next rising edge of the external clock and conversion n C 2 will begin. both rd (pin 21) and cs (pin 20) can be high during and before a conversion. however, they must both be low to enable the output bus and read data out. section b the convst pin is switched from high to low a second time to initiate conversion n C 1. again, the address must be selected 250ns prior to convst going low to ensure that the new address is selected for conversion. both the rd and cs pins are brought low in order to enable the parallel output bus with the n C 2 conversion results of channel a0. while continuing to hold cs low, rd is held low for a minimum of 30ns which enables the output bus with the channel a0 results of conversion n C 2. the rd pin is toggled from high to low a second time in order to enable the output bus with the channel b0 results of conversion n C 2. section c convst is brought low for a third time to initiate conversion n (channel 0). while the conversion is in process, the results for both conversions n C 2 and n C 1 can be read. the address pin is brought high while cs and rd are brought low which enables the output bus with the channel a1 results of conversion n C 1. the rd pin is toggled from high to low for a second time in section c and the n C 1 conversion results for channel b1 appear at the output bus. the address pin (a0) is then brought low and the read process repeats itself with the most recent conversion results for channel 0 (n C 2) appearing at the output bus. reading data the ads7862 outputs full parallel data in binary twos complement data output format. the parallel output will be active when cs (pin 20) and rd (pin 21) are both low. the output data should not be read 125ns prior to the falling edge of convst and 10ns after the falling edge. any other combination of cs and rd will tri-state the parallel output. valid conversion data can be read on pins 5 through 16 (msb-lsb). refer to table i for ideal output codes. layout for optimum performance, care should be taken with the physical layout of the ads7862 circuitry. this is particu- larly true if the clock input is approaching the maximum throughput rate. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. thus, driving any single conver- sion for an n-bit sar converter, there are n windows in which large external transient voltages can affect the conver- sion result. such glitches might originate from switching power supplies, nearby digital logic or high power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the exter- nal event. their error can change if the external event changes in time with respect to the clock input. with this in mind, power to the ads7862 should be clean and well bypassed. a 0.1 m f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 m f to 10 m f capacitor is recommended. if needed, an even larger capacitor and a 5 w or 10 w series resistor may be used to low-pass filter a noisy supply. on average, the ads7862 draws very little current from an external reference as the reference voltage is internally buffered. if the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. a bypass capacitor is not necessary when using the internal reference (tie pin 1 directly to pin 2). the agnd and dgnd pins should be connected to a clean ground point. in all cases, this should be the analog ground. avoid connections which are too close to the ground- ing point of a microcontroller or digital signal processor. if required, run a ground trace directly from the converter to the power supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. applications an applications section will be added featuring the ads7862 interfacing to popular dsp processors. the updated data sheet will be available in the near future on the burr-brown web site: http: //www.burr-brown.com/
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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