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ultra-low voltage intel ? celeron ? processor (0.13 ) in the micro fc-bga package at 650 mhz and 400 mhz datasheet product features ultra-low voltage intel ? celeron ? processor (0.13) with the following processor core/bus speeds: ? 650/100 mhz at 1.10 v ? 400/100 mhz at 0.95 v supports the intel architecture with dynamic execution on-die primary 16-kbyte instruction cache and 16-kbyte write-back data cache on-die second level cache (256-kbyte) with advanced transfer cache architecture data prefetch logic integrated agtl termination integrated math co-processor micro-fcbga packaging technologies ? supports small form factor applied computing designs ? exposed die enables more efficient heat dissipation fully compatible with previous intel microprocessors ? binary compatible with all applications ? support for mmx? technology ? support for streaming simd extensions power management features ? quick start and deep sleep modes provide low power dissipation on-die thermal diode order number: 273804-002 may 2003 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the ultra low voltage intel ? celeron ? processor (0.13 ) in the micro fc-bga package at 650 mhz and 400 mhz may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are a vailable on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2003 alertview, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct connect, ct media, dialogic, dm3, ethere xpress, etox, flashfile, i386, i486, i960, icomp, instantip, intel, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intel sx2, intel create & share, intel gigablade, intel inbusiness, intel inside, intel inside lo go, intel netburst, intel netmerge, intel netstructure, intel p lay, intel play logo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, landesk, lanrov er, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, shiva, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, trillium, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsi diaries in the united states and other countries. *other names and brands may be claimed as the property of others. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
datasheet 3 contents contents 1.0 introduction ............................................................................................................................... .....9 1.1 overview.................................................................................................................... ...........9 1.2 state of the data........................................................................................................... ......10 1.3 terminology ................................................................................................................. .......10 1.4 references .................................................................................................................. .......10 2.0 ultra-low voltage intel ? celeron ? processor features ...........................................................13 2.1 new features in the ultra-low voltage intel ? celeron ? processor....................................13 2.1.1 100-mhz psb with agtl signaling......................................................................13 2.1.2 256-k on-die integrated l2 cache ........................................................................ 13 2.1.3 data prefetch logic ............................................................................................... 13 2.1.4 differential clocking ...............................................................................................13 2.1.5 signal differences between the mobile intel ? celeron ? processor in bga2 and micro-pga2 packages and the ultra-low voltage intel ? celeron ? processor in micro fc-bga packages..... 13 2.2 power management............................................................................................................ 14 2.2.1 clock control architecture .....................................................................................14 2.2.2 normal state..........................................................................................................14 2.2.3 auto halt state.......................................................................................................14 2.2.4 quick start state....................................................................................................15 2.2.5 halt/grant snoop state.......................................................................................16 2.2.6 deep sleep state................................................................................................... 16 2.2.7 operating system implications of low-power states ............................................16 2.3 agtl signals................................................................................................................ ......17 2.4 ultra-low voltage intel ? celeron ? processor cpuid ........................................................17 3.0 electrical specifications .............................................................................................................19 3.1 processor system signals..................................................................................................19 3.1.1 power sequencing requirements .........................................................................20 3.1.2 test access port (tap) connection ...................................................................... 21 3.1.3 catastrophic thermal protection ........................................................................... 21 3.1.4 unused signals...................................................................................................... 21 3.1.5 signal state in low-power states .......................................................................... 21 3.2 power supply requirements ..............................................................................................22 3.2.1 decoupling guidelines ........................................................................................... 22 3.2.2 voltage planes....................................................................................................... 23 3.2.3 pll rlc filter specification ..................................................................................23 3.2.4 voltage identification ............................................................................................. 26 3.2.5 vttpwrgd signal quality specification.............................................................. 27 3.3 system bus clock and processor clocking........................................................................28 3.4 maximum ratings ............................................................................................................. ..29 3.5 dc specifications ........................................................................................................... ....30 3.6 ac specifications........................................................................................................... ..... 34 3.6.1 system bus, clock, apic, tap, cmos, and open-drain ac specifications ........ 34 4.0 system signal simulations .........................................................................................................47 4.1 system bus clock (bclk) and picclk dc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
contents 4 datasheet specifications and ac signal quality specifications47 4.2 agtl ac signal quality specifications.............................................................................. 48 4.3 non-agtl signal quality specifications ............................................................................ 50 4.3.1 pwrgood, vttpwrgd signal quality specifications ...................................... 50 5.0 mechanical specifications .......................................................................................................... 53 5.1 surface mount micro fc-bga package............................................................................. 53 5.2 signal listings............................................................................................................. ........ 55 6.0 vcc thermal specifications ....................................................................................................... 65 6.1 thermal diode ............................................................................................................... ..... 66 7.0 processor initialization and configuration ............................................................................... 67 7.1 description................................................................................................................. ......... 67 7.1.1 quick start enable................................................................................................. 67 7.1.2 system bus frequency.......................................................................................... 67 7.1.3 apic enable .......................................................................................................... 67 7.2 clock frequencies and ratios............................................................................................ 67 8.0 processor interface ..................................................................................................................... 69 8.1 alphabetical signal reference............................................................................................ 69 8.1.1 a[35:3]# (i/o ? agtl)............................................................................................ 69 8.1.2 a20m# (i - 1.5v tolerant) ...................................................................................... 69 8.1.3 ads# (i/o - agtl)................................................................................................. 69 8.1.4 aerr# (i/o - agtl) ..............................................................................................69 8.1.5 ap[1:0]# (i/o - agtl) ............................................................................................ 69 8.1.6 bclk, bclk# (i).................................................................................................... 70 8.1.7 berr# (i/o - agtl) ..............................................................................................70 8.1.8 binit# (i/o - agtl)............................................................................................... 70 8.1.9 bnr# (i/o - agtl) ................................................................................................ 71 8.1.10 bp[3:2]# (i/o - agtl) ............................................................................................ 71 8.1.11 bpm[1:0]# (i/o - agtl) .........................................................................................71 8.1.12 bpri# (i - agtl) ................................................................................................... 71 8.1.13 breq0# (i/o - agtl)............................................................................................ 71 8.1.14 bsel[1:0] (o ? 3.3v tolerant)............................................................................... 71 8.1.15 clkref (analog).................................................................................................. 72 8.1.16 cmosref (analog) ..............................................................................................72 8.1.17 d[63:0]# (i/o - agtl) ............................................................................................ 72 8.1.18 dbsy# (i/o - agtl) ..............................................................................................72 8.1.19 defer# (i - agtl)................................................................................................ 72 8.1.20 dep[7:0]# (i/o - agtl).......................................................................................... 73 8.1.21 drdy# (i/o - agtl)..............................................................................................73 8.1.22 dpslp# (i - 1.5 v tolerant)................................................................................... 73 8.1.23 edgctrlp (i-analog) .......................................................................................... 73 8.1.24 ferr# (o - 1.5 v tolerant open-drain) ................................................................ 73 8.1.25 flush# (i - 1.5 v tolerant)................................................................................... 73 8.1.26 hit# (i/o - agtl), hitm# (i/o - agtl)................................................................. 73 8.1.27 ierr# (o - 1.5 v tolerant open-drain) ................................................................. 74 8.1.28 ignne# (i - 1.5 v tolerant) ................................................................................... 74 8.1.29 init# (i - 1.5 v tolerant)........................................................................................ 74 8.1.30 intr (i - 1.5 v tolerant) ........................................................................................ 74 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
datasheet 5 contents 8.1.31 lint[1:0] (i - 1.5 v tolerant)..................................................................................74 8.1.32 lock# (i/o - agtl) ..............................................................................................75 8.1.33 nctrl (i - analog) ................................................................................................75 8.1.34 nmi (i - 1.5 v tolerant) ..........................................................................................75 8.1.35 picclk (i ? 2.0 v tolerant) ...................................................................................75 8.1.36 picd[1:0] (i/o - 1.5 v tolerant open-drain) .......................................................... 75 8.1.37 pll1, pll2 (analog) ............................................................................................. 75 8.1.38 prdy# (o - agtl) ................................................................................................76 8.1.39 preq# (i - 1.5 v tolerant) ....................................................................................76 8.1.40 pwrgood (i ? 1.8 v tolerant).............................................................................76 8.1.41 req[4:0]# (i/o - agtl) .........................................................................................76 8.1.42 reset# (i - agtl)................................................................................................76 8.1.43 rp# (i/o - agtl) ...................................................................................................77 8.1.44 rs[2:0]# (i/o - agtl) ............................................................................................77 8.1.45 rsp# (i - agtl) ....................................................................................................77 8.1.46 rttimpedp (i-analog) .........................................................................................77 8.1.47 smi# (i - 1.5 v tolerant) ........................................................................................77 8.1.48 stpclk# (i - 1.5 v tolerant).................................................................................77 8.1.49 tck (i - 1.5 v tolerant) .........................................................................................78 8.1.50 tdi (i - 1.5 v tolerant) ...........................................................................................78 8.1.51 tdo (o - 1.5 v tolerant open-drain) ....................................................................78 8.1.52 testhi[2:1] (i - 1.25 v tolerant)...........................................................................78 8.1.53 testlo[2:1] (i - 1.5 v tolerant)............................................................................78 8.1.54 thermda, thermdc (analog)...........................................................................78 8.1.55 tms (i - 1.5 v tolerant) .........................................................................................78 8.1.56 trdy# (i/o - agtl) ..............................................................................................78 8.1.57 trst# (i - 1.5 v tolerant) .....................................................................................78 8.1.58 vid[4:0] (o ? open-drain)...................................................................................... 79 8.1.59 v ref (analog) ........................................................................................................79 8.1.60 vttpwrgd (i ? 1.25 v) .......................................................................................79 8.2 signal summaries............................................................................................................ ...79 figures 1 clock control states .......................................................................................................... .........15 2 pll rlc filter ................................................................................................................ ............23 3 pll filter specifications ..................................................................................................... ........24 4 vttpwrgd system-level connections ................................................................................... 27 5 noise estimation.............................................................................................................. ...........28 6 bclk (single ended)/picclk/tck generic clock timing waveform....................................... 39 7 differential bclk/bclk# waveform (common mode) .............................................................. 39 8 bclk/bclk# waveform (differential mode) ..............................................................................40 9 valid delay timings ........................................................................................................... .........40 10 setup and hold timings ....................................................................................................... ......40 11 cold/warm reset and configuration timings ............................................................................41 12 power-on sequence and reset timings .................................................................................... 42 13 power down sequencing and timings (v cc leading) ............................................................... 43 14 power down sequencing and timings (vcct leading)............................................................ 44 15 test timings (boundary scan) ................................................................................................. ..45 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
contents 6 datasheet 16 test reset timings........................................................................................................... .......... 45 17 quick start/deep sleep timing (bclk stopping method) ......................................................... 46 18 quick start/deep sleep timing (dpslp# assertion method) .................................................... 46 19 bclk (single ended)/picclk generic clock waveform .......................................................... 48 20 maximum acceptable overshoot/undershoot waveform........................................................... 49 21 vttpwrgd noise specification ............................................................................................... 52 22 micro fc-bga package ? top and bottom isometric views ..................................................... 54 23 micro fc-bga package ? top and side views ......................................................................... 54 24 micro fc-bga package ? bottom view ..................................................................................... 55 25 ball map ? top view.......................................................................................................... ......... 56 tables 1 new and revised ultra-low voltage intel ? celeron ? processor (0.13 ) signals ..................... 14 2 clock state characteristics ................................................................................................... ..... 16 3 ultra-low voltage intel ? celeron ? processor cpuid ................................................................ 17 4 ultra-low voltage intel ? celeron ? processor cpuid cache and tlb descriptors ................... 17 5 system signal groups .......................................................................................................... ...... 19 6 recommended resistors for ultra-low voltage intel ? celeron ? processor signals ................. 20 7 pll filter inductor recommendations .......................................................................................25 8 pll filter capacitor recommendations ..................................................................................... 25 9 pll filter resistor recommendations ....................................................................................... 25 10 ultra-low voltage intel ? celeron ? processor vid values ......................................................... 26 11 vttpwrgd noise specification ............................................................................................... 27 12 vttpwrgd transition time specification ................................................................................ 27 13 ultra-low voltage intel ? celeron ? processor absolute maximum ratings................................ 29 14 power specifications for the ultra-low voltage intel ? celeron ? processor ............................... 30 15 vcc tolerances for the ultra-low voltage intel ? celeron ? processor: vid = 1.1 v ................. 31 16 vcc tolerances for the ultra-low voltage intel ? celeron ? processor in the deep sleep state: vid = 1.1 v .................................................................................................. .31 17 vcc tolerances for the ultra-low voltage intel ? celeron ? processor: vid = 0.95 v ............... 32 18 vcc tolerances for the ultra-low voltage intel ? celeron ? processor in the deep sleep state: vid = 0.95 v ................................................................................................. 32 19 agtl signal group dc specifications ....................................................................................... 32 20 agtl bus dc specifications................................................................................................... ... 33 21 clkref, apic, tap, cmos, and open-drain signal group dc specifications ....................... 33 22 system bus clock ac specifications .........................................................................................35 23 valid ultra-low voltage intel ? celeron ? processor frequencies............................................... 35 24 agtl signal groups ac specifications ..................................................................................... 35 25 cmos and open-drain signal groups ac specifications .......................................................... 36 26 reset configuration ac specifications and power on/power down timings............................ 36 27 apic bus signal ac specifications ............................................................................................ 37 28 tap signal ac specifications ................................................................................................. ... 38 29 quick start/deep sleep ac specifications................................................................................. 39 30 bclk (differential) dc specifications and ac signal quality specifications ............................. 47 31 bclk (single ended) dc specifications and ac signal quality specifications......................... 47 32 picclk dc specifications and ac signal quality specifications .............................................. 48 33 100-mhz agtl signal group overshoot/undershoot tolerance at the processor core.......................................................................................................... ....... 49 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
datasheet 7 contents 34 non-agtl signal group overshoot/undershoot tolerance at the processor core .................. 50 35 vttpwrgd noise parameter specification..............................................................................51 36 vttpwrgd transition parameter recommendation ............................................................... 51 37 micro fc-bga package mechanical specifications ................................................................... 53 38 signal listing in order by ball number....................................................................................... 57 39 signal listing in order by signal name ...................................................................................... 6 0 40 voltage and no-connect ball locations .....................................................................................63 41 power specifications for the ultra-low voltage intel ? celeron ? processor ...............................65 42 thermal diode interface ...................................................................................................... .......66 43 thermal diode specifications ................................................................................................. ....66 44 bsel[1:0] encoding........................................................................................................... .........72 45 input signals ................................................................................................................ ...............79 46 output signals ............................................................................................................... .............80 47 input/output signals (single driver) ......................................................................................... ..80 48 input/output signals (multiple driver)....................................................................................... ..81 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
contents 8 datasheet revision history date revision description may 2003 002 removed figure 6, ?illustration of v cc static and transient tolerances. removed figure 7, ?illustration of deep sleep v cc static and transient tolerances. october 2002 001 initial document release www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 9 1.0 introduction using intel?s advanced 0.13-micron process technology with copper interconnect, the ultra-low voltage intel ? celeron ? processor offers high-performance and low power consumption. the ultra-low voltage intel celeron processor (0.13) in the micro fc-bga packages (hereafter referred to as the ulv intel celeron processor) is based on the same core as existing intel ? pentium ? iii processors. key performance features include internet streaming simd instructions, advanced transfer cache architecture, and a processor system bus speed of 100 mhz. these features are offered in a micro fc-bga packages for surface mount small form factor boards. the 256-kbyte integrated l2 cache based on the advanced transfer cache architecture runs at full speed and is designed to help improve performance. it complements the system bus by providing critical data faster and reducing total system power consumption. the processor also features data prefetch logic that speculatively fetches data to the l2 cache, resulting in improved performance. the intel celeron processor?s 64-bit wide assisted gunning transceiver logic (agtl) system bus provides a glueless, point-to-point interface for a memory controller hub. this document covers the electrical, mechanical, and thermal specifications for the ultra-low voltage intel celeron processor at 650 mhz at 1.10 v and 400 mhz at 0.95 v. 1.1 overview performance features ? supports the intel architecture with dynamic execution ? supports intel mmx ? technology ? supports streaming simd extensions for enhanced video, sound, and 3d performance ? integrated intel floating point unit compatible with the ieee 754 standard ? data prefetch logic on-die primary (l1) instruction and data caches ? 4-way set associative, 32-byte line size, 1 line per sector ? 16-kbyte instruction cache and 16-kbyte write-back data cache ? cacheable range controlled by processor programmable registers on-die second level (l2) cache ? 8-way set associative, 32-byte line size, 1 line per sector ? operates at full core speed ? 256-kbyte ecc protected cache data array agtl system bus interface ? 64-bit data bus, 100-mhz ? uniprocessor, two loads only (processor and chipset) ? integrated termination processor clock control www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 10 datasheet ? quick start for low power, low exit latency clock ?throttling? ? deep sleep mode for lower power dissipation thermal diode for measuring processor temperature 1.2 state of the data all information in this document is the best available information at the time of publication. revisions of this document will be provided on an as-required basis. 1.3 terminology 1.4 references p6 family of processors hardware developer?s manual (244001) intel ? architecture optimization reference manual (245127) intel ? architecture software developer?s manual ? volume i: basic architecture (245470) ? volume ii: instruction set reference (245471) ? volume iii: system programming guide (245472) ck-408 (ck-titan) clock synthesizer/driver specification (contact your intel field sales representative) mobile intel ? pentium ? iii processor-m i/o buffer models , ibis format ( contact your intel field sales representative) term definition # a ?#? symbol following a signal name indicates that the signal is active low. this means that when the signal is asserted (based on the name of the signal) it is in an electrical low state. otherwise, signals are driven in an electrical high state when they are asserted. in state machine diagrams, a signal name in a condition indicates the condition of that signal being asserted ! indicates the condition of that signal not being asserted. for example, the condition ?!stpclk# and hs? is equivalent to ?the active low signal stpclk# is unasserted (i.e., it is at 1.5v) and the hs condition is true.? l electrical low signal levels h electrical high signal levels 0 logical low. for example, bd[3:0] = ?1010? = ?hlhl? refers to a hexadecimal ?a,? and d[3:0]# = ?1010? = ?lhlh? also refers to a hexadecimal ?a.? 1 logical high. for example, bd[3:0] = ?1010? = ?hlhl? refers to a hexadecimal ?a,? and d[3:0]# = ?1010? = ?lhlh? also refers to a hexadecimal ?a.? ulv ultra-low voltage tbd specifications that are yet to be determined and will be updated in future revisions of the document. x don?t care condition www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 11 intel ? mobile voltage positioning -ii (imvp-ii) design guide (contact your intel field sales representative) mobile intel ? pentium ? iii processor-m /440mx platform design guide (contact your intel field sales representative) intel processor identification and the cpuid instruction application note ap-485 (241618) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
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ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 13 2.0 ultra-low voltage intel ? celeron ? processor features 2.1 new features in the ultra-low voltage intel ? celeron ? processor 2.1.1 100-mhz psb with agtl signaling the ulv intel ? celeron ? processor uses assisted gtl (agtl) signaling on the processor system bus (psb) interface. the main difference between agtl and gtl+ used on previous intel processors is v cct = 1.25 v for agtl versus 1.5 v for gtl+. the lower voltage swing enables high performance at lower power. 2.1.2 256-k on-die integrated l2 cache the 256-k on die integrated l2 cache on the ulv intel celeron processor is double the l2 cache size of previous intel celeron processors (0.18 ). the l2 cache runs at the processor core speed and the increased cache size provides superior processing power. 2.1.3 data prefetch logic the ulv intel celeron processor features data prefetch logic that speculatively fetches data to the l2 cache before an l1 cache request occurs. this reduces transactions between the cache and system memory reducing or eliminating bus cycle penalties, resulting in improved performance. the processor also includes extensions to memory order and reorder buffers that boost performance. 2.1.4 differential clocking differential clocking requires the use of two complementary clocks: bclk and bclk#. benefits of differential clocking include easier scaling to lower voltages, reduced emi, and less jitter. all references to bclk in this document apply to bclk# also even if not explicitly stated. the ulv intel celeron processor will also support single ended clocking. the processor will configure itself for differential or single ended clocking based on the waveforms detected on the bclk and bclk#/clkref signal lines. 2.1.5 signal differences between the mobile intel ? celeron ? processor in bga2 and micro-pga2 packages and the ultra-low voltage intel ? celeron ? processor in micro fc-bga packages a list of new and changed signals is shown in table 1 . www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 14 datasheet 2.2 power management 2.2.1 clock control architecture the ulv intel ? celeron ? processor clock control architecture ( figure 1 ) has been optimized for leading edge computer designs. the clock control architecture consists of six different clock states: normal, auto halt, quick start, halt/grant snoop and deep sleep states. the auto halt state provides a low-power clock state that may be controlled through the software execution of the hlt instruction. the quick start state provides a very low power and low exit latency clock state that may be used for hardware controlled ?idle? computer states. the deep sleep state provides extremely low-power states that may be used for ?power-on-suspend? computer states, which is an alternative to shutting off the processor?s power. the exit latency of the deep sleep state is 30 ms in the intel celeron processor. performing state transitions not shown in figure 1 is neither recommended nor supported. figure 2 provides the clock state characteristics, which are described in detail in the following sections. 2.2.2 normal state the normal state of the processor is the normal operating mode where the processor?s core clock is running and the processor is actively executing instructions. 2.2.3 auto halt state this is a low-power mode entered by the processor through the execution of the hlt instruction. a transition to the normal state is made by a halt break event (one of the following signals going active: nmi, intr, binit#, init#, reset#, flush#, or smi#). asserting the stpclk# signal while in the auto halt state will cause the processor to transition to the quick start state. deasserting stpclk# will cause the processor to return to the auto halt state without issuing a new halt bus cycle. table 1. new and revised ultra-low voltage intel ? celeron ? processor (0.13 ) signals signals function bclk, bclk# differential host clock signals. clkref host clock reference signal in single ended clocking mode. bsel[1:0] signals are output only instead of i/o. refer to section 3.2.3 for details. dpslp# deep sleep pin (replaces slp# pin on the mobile celeron processor (0.18 )) nctrl agtl output buffer pull down impedance control. vid[4:0] voltage identification (different implementation from mobile celeron processor (0.18 )). refer to section 3.2.4 for details. vttpwrgd power good signal for v cct , which indicates that, the vid signals are stable. refer to figure 4 for vttpwrgd system level connections. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 15 the smi# interrupt is recognized in the auto halt state. the return from the system management interrupt (smi) handler may be to either the normal state or the auto halt state. see the intel ? architecture software developer?s manual, volume iii: system programmer?s guide for more information. no halt bus cycle is issued when returning to the auto halt state from the system management mode (smm). the flush# signal is serviced in the auto halt state. after the on-chip and off-chip caches have been flushed, the processor will return to the auto halt state without issuing a halt bus cycle. transitions in the a20m# and preq# signals are recognized while in the auto halt state. 2.2.4 quick start state the processor is required to be configured for the quick start state by strapping the a15# signal low. in the quick start state the processor is only capable of acting on snoop transactions generated by the system bus priority device. because of its snooping behavior, quick start may only be used in a uniprocessor (up) configuration. a transition to the deep sleep state may be made by stopping the clock input to the processor or asserting the dpslp# signal. a transition back to the normal state (from the quick start state) is made only if the stpclk# signal is deasserted. while in this state the processor is limited in its ability to respond to input. it is incapable of latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to flush# or binit# assertions. while the processor is in the quick start state, it will not respond figure 1. clock control states notes: 1. state transition does not occur until the stop grant or auto halt acknowledge bus cycle completes halt break - a20m#, binit#, flush#, init#, intr, nmi, preq#, reset#, smi#, or apic interrupt hlt - hlt instruction executed hs - processor halt state 2. restrictions apply to the use of both methods of entering deep sleep. see deep sleep state description for details. quick start normal hs=false deep sleep 2 halt/grant snoop auto halt hs=true stpclk# 1 bclk stopped or dpslp# snoop occurs bclk on and !dpslp# (!stpclk# and !hs) or reset# snoop serviced hlt instruction 1 snoop serviced snoop occurs stpclk# 1 !stpclk# and hs halt break v0001-022 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 16 datasheet properly to any input signal other than stpclk#, reset#, or bpri#. if any other input signal changes, then the behavior of the processor will be unpredictable. no serial interrupt messages may begin or be in progress while the processor is in the quick start state. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the quick start state after initialization until stpclk# is deasserted. 2.2.5 halt/grant snoop state the processor will respond to snoop transactions on the system bus while in the auto halt or quick start state. when a snoop transaction is presented on the system bus the processor will enter the halt/grant snoop state. the processor will remain in this state until the snoop has been serviced and the system bus is quiet. after the snoop has been serviced, the processor will return to its previous state. if the halt/grant snoop state is entered from the quick start state, then the input signal restrictions of the quick start state still apply in the halt/grant snoop state, except for those signal transitions that are required to perform the snoop. 2.2.6 deep sleep state the deep sleep state is a very low power state that the processor may enter while maintaining its context. the deep sleep state is entered by stopping the bclk and bclk# inputs to the processor or by asserting the dpslp# signal, while it is in the quick start state. note that either one of the methods may be used to enter deep sleep but not both at the same time. when bclk and bclk# are stopped, they must obey the dc levels specified in table 33 . the processor will return to the quick start state from the deep sleep state when the bclk and bclk# inputs are restarted or the dpslp# signal is deasserted. due to the pll lock latency, there is a delay of up to 30 s after the clocks have started before this state transition happens. picclk may be removed in the deep sleep state. picclk should be designed to turn on when bclk and bclk# turn on or dpslp# is deasserted when transitioning out of the deep sleep state. 2.2.7 operating system implications of low-power states the time-stamp counter and the performance monitor counters are not ensured to count in the quick start state. the local apic timer and performance monitor counter interrupts should be disabled before entering the deep sleep state or the resulting behavior will be unpredictable. table 2. clock state characteristics clock state exit latency snooping? system uses normal n/a yes normal program execution auto halt 10 s yes s/w controlled entry idle mode quick start through snoop, to halt/ grant snoop state: immediate through stpclk#, to normal state: 10 s yes h/w controlled entry/exit mobile throttling halt/grant snoop a few bus clocks after snoop completion yes supports snooping in the low power states deep sleep 30 s no h/w controlled entry/exit mobile powered-on suspend support www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 17 2.3 agtl signals the ulv intel ? celeron ? processor system bus signals use a variation of the low-voltage swing gtl signaling technology. the agtl system bus depends on incident wave switching and uses flight time for timing calculations of the agtl signals, as opposed to capacitive derating. intel recommends analog signal simulation of the system bus including trace lengths. contact your field sales representative to receive the ibis models for the mobile intel celeron processor for simulation. the agtl system bus of the ulv intel celeron processor is designed to support high-speed data transfers with multiple loads on a long bus that behaves like a transmission line. however, in up embedded systems the system bus only has two loads (the processor and the chipset) and the bus traces are short. it is possible to change the layout and termination of the system bus to take advantage of this environment using the same agtl i/o buffers. this termination is provided on the processor core (except for the reset# signal). 2.4 ultra-low voltage intel ? celeron ? processor cpuid when the cpuid version information is loaded with eax=01h, the eax and ebx registers contain the values shown in table 3 . after a power-on reset, the edx register contains the processor version information (type, family, model, stepping). table 4 shows the cpuid cache and tlb descriptor values after the l2 cache is initialized. see the intel processor identification and the cpuid instruction application note ap-485 for further information. table 3. ultra-low voltage intel ? celeron ? processor cpuid eax[31:0] ebx[7:0] reserved [31:14] type [13:12] family [11:8] model [7:4] stepping [3:0] brand id x06bx01 table 4. ultra-low voltage intel ? celeron ? processor cpuid cache and tlb descriptors cache and tlb descriptors 01h, 02h, 03h, 04h, 08h, 0ch, 83h www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
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ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 19 3.0 electrical specifications 3.1 processor system signals table 5 lists the processor system signals by type. all agtl signals are synchronous with the bclk and bclk# signals. all tap signals are synchronous with the tck signal except trst#. all cmos input signals may be applied asynchronously. the apic data and tap outputs are open-drain and should be pulled up to 1.5 v using resistors with the values shown in table 6 . if open-drain drivers are used for input signals, then they should also be pulled up to the appropriate voltage using resistors with the values shown in table 6 . table 5. system signal groups group name signals agtl input bpri#, defer#, reset#, rsp# agtl output prdy# agtl i/o a[35:3]#, ads#, aerr#, ap[1:0]#, berr#, binit#, bnr#, bp[3:2]#, bpm[1:0]#, breq0#, d[63:0]#, dbsy#, dep[7:0]#, drdy#, hit#, hitm#, lock#, req[4:0]#, rp#, rs[2:0]#, trdy# 1.5 v cmos input a20m#, dpslp#, flush#, ignne#, init#, lint0/intr, lint1/nmi, preq#, smi#, stpclk# 1.8 v cmos input pwrgood 1.5 v open drain output ferr#, ierr# 3.3 v open drain output bsel[1:0], vid[4:0] 1.25 v input vttpwrgd clock bclk, bclk# (differential mode) 2.5 v clock input bclk (single ended mode) apic clock picclk apic i/o picd[1:0] thermal diode thermdc, thermda tap input tck, tdi, tms, trst# tap output tdo power/other clkref, cmosref, edgectrlp, nc, nctrl, pll1, pll2, rttimpedp, v cc , v cct , v ref , v ss, notes: 1. v cc is the power supply for the core logic. 2. pll1 and pll2 are power/ground for the pll analog section. see section 3.2.2 for details. 3. v cct is the power supply for the system bus buffers. 4. v ref is the voltage reference for the agtl input buffers. 5. vss is system ground. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 20 datasheet 3.1.1 power sequencing requirements unlike the mobile intel ? celeron ? processor (0.18 ), the ulv intel celeron processor (0.13 ) does have specific power sequencing requirements. the power on sequencing and timings are shown in figure 12 and table 26 . power down timing requirements are shown in figure 13 , figure 14 , and table 26 . the v cc power plane must not rise too fast. at least 200 s (t r ) must pass from the time that v cc is at 10% of its nominal value until the time that v cc is at 90% of its nominal value. for more details, refer to the intel ? mobile voltage positioning -ii (imvp-ii) design guide (contact your field sales representative). table 6. recommended resistors for ultra-low voltage intel ? celeron ? processor signals recommended resistor value ( ? ) ultra-low voltage intel ? celeron ? processor signal 1, 2 10 pull-down breq0# 3 14 pull-up nctrl 39 pull-up tms 39 pull-down tck 56.2 pull-up prdy#, reset# 4 56.2 pull-down rttimpedp 110 pull-down edgectrlp 150 pull-up picd[1:0], tdo 200-300 pull-up preq#, tdi 500 pull-down trst# 1k pull-up bsel[1:0], testhi, vid[4:0], vttpwrgd 1k pull-down testlo 1.5k pull-up ferr#, ierr#, pwrgood 3k pull-up flush# additional pull-up/pull-down resistor recommendations 6 270 pull-up smi# 680 pull-up stpclk# 1.5k pull-up a20m#, dpslp#, init#, ignne#, lint0/intr, lint1/nmi notes: 1. the recommendations above are only for signals that are being used. these recommendations are maximum values only; stronger pull-ups may be used. pull-ups for the signals driven by the chipset should not violate the chipset specification. refer to section 3.1.4 for the required pull-up or pull-down resistors for signals that are not being used. 2. open-drain signals must never violate the undershoot specification in section 4.3 . use stronger pull-ups if there is too much undershoot. 3. a pull-down on breq0# is an alternative to having the central agent to drive breq0# low at reset. 4. a 56.2 ? 1% terminating resistor connected to v cct is required. 5. the following signals are actively driven high by the ich3-m component and do not need external pull up resistors on ich3-m based platforms: a20m#, dpslp#, init#, ignne#, lint0/intr, lint1/nmi, smi#, stpclk#. 6. these pull up recommendations apply to systems on which these signals are not actively pulled high such as those utilizing the 82443mx chipset. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 21 3.1.2 test access port (tap) connection the tap interface is an implementation of the ieee 1149.1 (?jtag?) standard. due to the voltage levels supported by the tap interface, intel recommends that the ulv intel ? celeron ? processor and the other 1.5-v jtag specification compliant devices be last in the jtag chain after any devices with 3.3-v or 5.0-v jtag interfaces within the system. a translation buffer should be used to reduce the tdo output voltage of the last 3.3/5.0 v device down to the 1.5-v range that the ulv intel celeron processor may tolerate. multiple copies of tms and trst# must be provided, one for each voltage level. a debug port and connector may be placed at the start and end of the jtag chain containing the processor, with tdi to the first component coming from the debug port and tdo from the last component going to the debug port. there are no requirements for placing the ulv intel celeron processor in the jtag chain, except for those that are dictated by voltage requirements of the tap signals. 3.1.3 catastrophic thermal protection the ulv intel celeron processor does not support catastrophic thermal protection or the thermtrip# signal. an external thermal sensor must be used to protect the processor and the system against excessive temperatures. if the external thermal sensor detects a processor junction temperature of 101 c (maximum), both the v cc and v cct supplies to the processor must be reduced to at least 50% of the nominal values within 500 ms and are recommended to be turned off completely within 1 second to prevent damage to the processor. processor temperature must be monitored in all states including low power states. 3.1.4 unused signals all signals named nc must be unconnected. unused agtl inputs, outputs, and bidirectional signals should be unconnected. unused cmos active low inputs should be connected to 1.5 v and unused active high inputs should be connected to v ss . unused open-drain outputs should be unconnected. when tying any signal to power or ground, a resistor will allow for system testability. for unused signals, intel suggests that 1.5-k ? resistors are used for pull-ups and 1.0-k ? resistors are used for pull-downs. picclk must be driven with a clock that meets specification and the picd[1:0] signals must be pulled up separately to 1.5 v with 150- ? resistors, even if the local apic is not used. if the tap signals are not used then the inputs should be pulled to ground with 1-k ? resistors and tdo should be left unconnected. 3.1.5 signal state in low-power states 3.1.5.1 system bus signals all of the system bus signals have agtl input, output, or input/output drivers. except when servicing snoops, the system bus signals are tri-stated and pulled up by the termination resistors. snoops are not permitted in the deep sleep state. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 22 datasheet 3.1.5.2 cmos and open-drain signals the cmos input signals are allowed to be in either the logic high or low state when the processor is in a low-power state. in the auto halt state these signals are allowed to toggle. these input buffers have no internal pull-up or pull-down resistors and system logic may use cmos or open-drain drivers to drive them. the open-drain output signals have open drain drivers and external pull-up resistors are required. one of the two output signals (ierr#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the processor is functioning normally. the ferr# output may be either tri-stated or driven to v ss when the processor is in a low-power state depending on the condition of the floating-point unit. since this signal is a dc current path when it is driven to v ss , intel recommends that the software clears or masks any floating-point error condition before putting the processor into the deep sleep state. 3.1.5.3 other signals the system bus clocks (bclk, bclk#) must be driven in all of the low-power states except the deep sleep state. the apic clock (picclk) must be driven whenever bclk and bclk# are driven. otherwise, it is permitted to turn off picclk by holding it at v ss . bclk and bclk# should be obey the dc levels in table 33 . in the auto halt state, the apic bus data signals (picd[1:0]) may toggle due to apic bus messages. these signals are required to be tri-stated and pulled-up when the processor is in the quick start or deep sleep states. 3.2 power supply requirements 3.2.1 decoupling guidelines the ulv intel ? celeron ? processor in micro fc-bga package has eight 0805idc, 0.68- f surface mount decoupling capacitors. six capacitors are on the v cc supply and two capacitors are on v cct. in addition to the package capacitors, sufficient board level capacitors are also necessary for power supply decoupling. the guidelines are as follows: high and mid frequency v cc decoupling ? place twenty-four 0.22- f 0603 capacitors directly under the package on the solder side of the motherboard using at least two vias per capacitor node. ten 10- f x7 6.3v 1206-size ceramic capacitors should be placed around the package periphery near the balls. trace lengths to the vias should be designed to minimize inductance. avoid bending traces to minimize esl. high and mid frequency v cct decoupling ? place ten 1- f x7r 0603 ceramic capacitors close to the package. via and trace guidelines are the same as above. bulk v cc decoupling ? minimum of 1200- f capacitance with equivalent series resistance (esr) less than or equal to 3.5 m ? . bulk v cct decoupling ? platform dependent but recommendation is minimum of 660- f with esr less than or equal to 7 m ? . refer to the appropriate platform design guidelines for bulk decoupling recommendations. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 23 3.2.2 voltage planes all v cc and v ss pins/balls must be connected to the appropriate voltage plane. all v cct and v ref pins/balls must be connected to the appropriate traces on the system electronics. in addition to the main v cc , v cct , and v ss power supply signals, pll1 and pll2 provide analog decoupling to the pll section. pll1 and pll2 should be connected according to figure 2 . do not connect pll2 directly to v ss . section 3.2.3 contains the rlc filter specification. 3.2.3 pll rlc filter specification 3.2.3.1 introduction all intel ? celeron ? processors have internal pll clock generators, which are analog in nature and require quiet power supplies for minimum jitter. jitter is detrimental to a system; it degrades external i/o timings as well as internal core timings (i.e. maximum frequency). the pll rlc filter specifications for the ulv intel celeron processor are the same as those for the mobile intel pentium ? iii processor-m, and the mobile intel celeron processor. the general desired topology is shown in figure 2 . excluded from the external circuitry are parasitics associated with each component. 3.2.3.2 filter specification the function of the filter is two fold. it protects the pll from external noise through low-pass attenuation. it also protects the pll from internal noise through high-pass filtering. in general, the low-pass description forms an adequate description for the filter. the ac low-pass specification, with input at v cct and output measured across the capacitor, is as follows: < 0.2-db gain in pass band < 0.5-db attenuation in pass band < 1 hz (see dc drop in next set of requirements) 34-db attenuation from 1 mhz to 66 mhz 28-db attenuation from 66 mhz to core frequency the filter specification (ac) is graphically shown in figure 3 . other requirements: use a shielded type inductor to minimize magnetic pickup figure 2. pll rlc filter pll1 pll2 v cct v0027-01 l1 c1 r1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 24 datasheet the filter should support a dc current of at least 30 ma the dc voltage drop from v cct to pll1 should be less than 60 mv, which in practice implies series resistance of less than 2 ? . this also means that the pass band (from dc to 1 hz) attenuation below 0.43 db for v cct = 1.25 v. 3.2.3.3 recommendation for embedded systems the following lc components are recommended. the tables will be updated as other suitable components and specifications are identified. figure 3. pll filter specifications notes: 1. diagram is not to scale 2. no specification for frequencies beyond fcore. 3. fpeak, if it exists, should be less than 0.05 mhz. 0 db -28 db -34 db 0.2 db forbidden zone x db forbidden zone 1 mhz 66 mhz fcore fpeak 1 hz dc passband high frequency band x = 20.log[(vcct-60 mv)/ vcct] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 25 note: minimum damping resistance is calculated from 0.35 ? ? dcr min . from vendor provided data, l1 and l2 dcr min is 0.4 ? and 0.5 ? respectively, qualifying them for zero required trace resistance. dcr min for l3 is not known and is assumed to be 0.15 ? . products with equivalent specifications may also be used. to satisfy damping requirements, total series resistance in the filter (from v cct to the top plate of the capacitor) must be at least 0.35 ? . this resistor may be in the form of a discrete component, or routing, or both. for example, if the picked inductor has minimum dcr of 0.25 ? , then a routing resistance of at least 0.10 ? is required. be careful not to exceed the maximum resistance rule (2 ? ). for example, if using discrete r1, the maximum dcr of the l should be less than 2.0 - 1.1 = 0.9 ? , which precludes using l2 and possibly l1. other routing requirements include: the capacitor should be close to the pll1 and pll2 pins, with less than 0.1 ? per route (these routes do not count towards the minimum damping resistance requirement). the pll2 route should be parallel and next to the pll1 route (minimize loop area). the inductor should be close to the capacitor; any routing resistance should be inserted between v cct and the inductor. any discrete resistor should be inserted between v cct and the inductor. 3.2.3.4 comments a magnetically shielded inductor protects the circuit from picking up external flux noise. this should provide better timing margins than with an unshielded inductor. a discrete or routed resistor is required because the lc filter by nature has an under-damped response, which may cause resonance at the lc pole. noise amplification at this band, although not in the pll-sensitive spectrum, could cause a fatal headroom reduction for analog circuitry. the resistor serves to dampen the response. systems with tight space constraints table 7. pll filter inductor recommendations inductor part number value tol srf rated i dcr min damping r needed l1 tdk mlf2012a4r7kt 4.7 h 10% 35 mhz 30 ma 0.56 ? (1 ? max) 0 ? l2 murata* lqg21n4r7k10 4.7 h 10% 47 mhz 30 ma 0.7 ? (+/-50%) 0 ? l3 murata* lqg21c4r7n00 4.7 h 30% 35 mhz 30 ma 0.3 ? max 0.2 ? (assumed) table 8. pll filter capacitor recommendations capacitor part number value tolerance esl esr c1 kemet* t495d336m016as 33 f 20% 2.5 nh 0.225 ? c2 avx tpsd336m020s0200 33 f 20% unknown 0.2 ? table 9. pll filter resistor recommendations resistor part number value tolerance power r1 various 1 ? 10% 1/16 w www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 26 datasheet should consider a discrete resistor to provide the required damping resistance. too large of a damping resistance may cause a large ir drop, which means less analog headroom and lower frequency. ceramic capacitors have very high self-resonance frequencies, but they are not available in large capacitance values. a high self-resonant frequency coupled with low esl/esr is crucial for sufficient rejection in the pll and high frequency band. the recommended tantalum capacitors have acceptably low esr and esl. the capacitor must be close to the pll1 and pll2 pins; otherwise the value of the low esr tantalum capacitor is wasted. note the distance constraint should be translated from the 0.1- ? requirement. 3.2.4 voltage identification there are five voltage identification balls/pins on the ulv intel ? celeron ? processor. these signals may be used to support automatic selection of v cc voltages. they are needed to cleanly support voltage specification variations on current and future processors. vid[4:0] are defined in table 10 . the vid[4:0] signals are open drain on the processor and need pull-up resistors to 3.3 v on the motherboard. refer to the appropriate vr guidelines provided by intel for additional information. table 10. ultra-low voltage intel ? celeron ? processor vid values vid[4:0] v cc (v) vid[4:0] v cc (v) vid[4:0] v cc (v) vid[4:0] v cc (v) 00000 1.750 01000 1.350 10000 0.975 11000 0.775 00001 1.700 01001 1.300 10001 0.950 11001 0.750 00010 1.650 01010 1.250 10010 0.925 11010 0.725 00011 1.600 01011 1.200 10011 0.900 11011 0.700 00100 1.550 01100 1.150 10100 0.875 11100 0.675 00101 1.500 01101 1.100 10101 0.850 11101 0.650 00110 1.450 01110 1.050 10110 0.825 11110 0.625 00111 1.400 01111 1.000 10111 0.800 11111 0.600 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 27 figure 4 shows the system level connections for the vttpwrgd signal. refer to the appropriate vr and system level guidelines provided by intel for more details. 3.2.5 vttpwrgd signal quality specification the vttpwrgd signal is an input to the processor used to determine that the vtt power is stable and the vid and bsel signals should be driven to their final state by the processor. to ensure the processor correctly reads this signal, it must meet the following requirement while the signal is in its transition region of 300 mv to 900 mv. also, vttpwrgd should only enter the transition region once, after vtt is at nominal values, for the assertion of the signal. in addition, the vttpwrgd signal should have reasonable transition time through the transition region. a sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal. intel recommends the following transition time for the vttpwrgd signal. 3.2.5.1 transition region the transition region covered by this requirement is 300 mv to 900 mv. once the vttpwrgd signal is in that voltage range, the processor is more sensitive to noise, which may be present on the signal. the transition region when the signal first crosses the 300 mv voltage level and continues until the last time it is below 900 mv. figure 4. vttpwrgd system-level connections voltage regulator processor clock generator vcct vttpwrgd (output) vttpwrgd (input) vttpwrgd# (input) vcct 10k vcct 3.3v 100k 1.2v to 3.3v level shifter 1k table 11. vttpwrgd noise specification parameter specification amount of noise (glitch) less than 100 mv table 12. vttpwrgd transition time specification parameter recommendation transition time (300 mv to 900 mv) less than or equal to 100 s www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 28 datasheet 3.2.5.2 transition time the transition time is defined as the time the signal takes to move through the transition region. a 100-s transition time will ensure that the processor receives a good transition edge. 3.2.5.3 noise the signal quality of the vttpwrgd signal is critical to the correct operation of the processor. every effort should be made to ensure this signal is monotonic in the transition region. if noise or glitches are present on this signal, it must be kept to less than 100 mv of a voltage drop from the highest voltage level received to that point. this glitch must remain less than 100 mv until the excursion ends by the voltage returning to the highest voltage previously received. please see figure 5 for an example graph of this situation and requirements. 3.3 system bus clock and processor clocking the bclk and bclk# clock inputs directly control the operating speed of the system bus interface. all system bus timing parameters are specified with respect to the crossing point of the rising edge of the bclk input and falling edge of the bclk# input. the ulv intel ? celeron ? processor core frequency is a multiple of the bclk frequency. the processor core frequency is configured during manufacturing. the configured bus ratio is visible to software in the power-on configuration register. see section 7.2 for details. figure 5. noise estimation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 29 multiplying the bus clock frequency is necessary to increase performance while allowing for easier distribution of signals within the system. clock multiplication within the processor is provided by the internal phase lock loop (pll), which requires constant frequency bclk and bclk# inputs. during reset or on exit from the deep sleep state, the pll requires some amount of time to acquire the phase of bclk and bclk#. this time is called the pll lock latency, which is specified in section 3.6 , ac timing parameters t18 and t47. 3.4 maximum ratings table 13 contains the ulv intel ? celeron ? processor stress ratings. functional operation at the absolute maximum and minimum is neither implied nor ensured. the processor should not receive a clock while subjected to these conditions. functional operating conditions are provided in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. although the processor contains protective circuitry to resist damage from static electric discharge, you should always take precautions to avoid high static voltages or electric fields. table 13. ultra-low voltage intel ? celeron ? processor absolute maximum ratings symbol parameter min max unit notes t storage storage temperature ?40 85 c 1 v cc (abs) supply voltage with respect to v ss ?0.5 1.75 v v cct system bus buffer voltage with respect to v ss ?0.3 1.75 v v in gtl system bus buffer dc input voltage with respect to v ss ?0.3 1.75 v 2 , 3 v in125 1.25 v buffer dc input voltage with respect to v ss ?0.3 1.75 v 4 v in15 1.5 v buffer dc input voltage with respect to v ss ?0.3 2.0 v 5 v in18 1.8 v buffer dc input voltage with respect to v ss ?0.3 2.0 v 6 v in20 2.0 v buffer dc input voltage with respect to v ss ?0.3 2.4 v 7 v in25 2.5 v buffer dc input voltage with respect to v ss ?0.3 3.3 v 9 v invid vid ball/pin dc input voltage with respect to v ss ?3.465v 8 i vid vid current -0.3 3.6 ma 8 notes: 1. the shipping container is only rated for 65 c. 2. parameter applies to the agtl signal groups only. compliance with both v in gtl specifications is required. 3. the voltage on the agtl signals must never be below ?0.3 v or above 1.75 v with respect to ground. 4. parameter applies to clkref, testhi, vttpwrgd signals. 5. parameter applies to cmos, open-drain, apic, testlo and tap bus signal groups only. 6. parameter applies to pwrgood signal. 7. parameter applies to picclk signal. 8. parameter applies to each vid pin/ball individually. 9. parameter applies to bclk signal in single ended clocking mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 30 datasheet 3.5 dc specifications tables 14 through 21 list the dc specifications for the ulv intel ? celeron ? processor. specifications are valid only while meeting specifications for the junction temperature, clock frequency, and input voltages. the junction temperature range for all dc specifications is 0 c to 100 c unless otherwise noted. care should be taken to read all notes associated with each parameter. unlike the mobile intel pentium ? iii processor, the v cc tolerances for the ulv intel celeron processor are not specified as a percentage of nominal. the tolerances are instead specified in the form of load lines for the static and transient cases in tables 15 through 18 . table 14. power specifications for the ultra-low voltage intel ? celeron ? processor symbol parameter min typ max unit notes 1 v cc transient v cc for core logic 1.10 0.95 v v 9 , 10 v cc,dc static v cc for core logic 1.10 0.95 v v 9 , 10 v cct v cc for system bus buffers, transient tolerance 1.138 1.25 1.362 v 9%, 7 , 10 v cct,dc v cc for system bus buffers, static tolerance 1.188 1.25 1.312 v 5%, 2 , 10 i cc current for v cc at core frequency 650 mhz and 1.10 v 400 mhz and 0.95 v 7.58 4.20 a 4 i cct current for v cct 2.7 a 3 , 4 i cc,ah processor auto halt current at 1.10 v 0.95 v 3.09 1.88 a 4 i cc,qs processor quick start current at 1.10 v 0.95 v 2.91 1.82 a 4 i cc,dslp processor deep sleep leakage current at 1.10 v 0.95 v 2.65 1.40 a 4 i lvid vid leakage current 0.5 ma 8 di cc /dt v cc power supply current slew rate 400 a/s 5 , 6 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. processors will comply with the i ccx , max specification for the current mode of operation. 2. static voltage regulation includes: dc output initial voltage set point adjust, output ripple and noise, temperature and warm up. 3. i cct is the current supply for the system bus buffers, including the on-die termination. 4. i ccx , max specifications are specified at v cc static (typical) derived from the tolerances in tables 15 through 18 , v cct , max , t jmax , and under maximum signal loading conditions. 5. based on simulations and averaged over the duration of any change in current. use to compute the maximum inductance and reaction time of the voltage regulator. this parameter is not tested. 6. maximum values specified by design/characterization at nominal v cc and v cct . 7. v ccx must be within this range under all operating conditions, including maximum current transients. v ccx must return to within the static voltage specification, v ccx , dc , within 100 s after a transient event. 8. vid leakage current is < 100 a for vid voltages under 3.0 v. 9. typical v cc indicates the vid encoded voltage. voltage supplied must conform to the load line specification shown in tables 15 through 18 . 10.voltages are measured at the package ball on the micro fc-bga device. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 31 ta ble 1 5. v cc tolerances for the ultra-low voltage intel ? celeron ? processor: vid = 1.1 v i cc (a) v cc (v) static transient typ min max min max 0.0 1.100 1.075 1.125 1.055 1.145 1.0 1.096 1.071 1.121 1.051 1.141 2.0 1.092 1.067 1.117 1.047 1.137 3.0 1.088 1.063 1.113 1.043 1.133 4.0 1.084 1.059 1.109 1.039 1.129 5.0 1.080 1.055 1.105 1.035 1.125 6.0 1.076 1.051 1.101 1.031 1.121 7.0 1.072 1.047 1.097 1.027 1.117 8.0 1.068 1.043 1.093 1.023 1.113 9.0 1.064 1.039 1.089 1.019 1.109 10.0 1.060 1.035 1.085 1.015 1.105 11.0 1.056 1.031 1.081 1.011 1.101 12.0 1.052 1.027 1.077 1.007 1.097 13.0 1.048 1.023 1.073 1.003 1.093 ta ble 1 6. v cc tolerances for the ultra-low voltage intel ? celeron ? processor in the deep sleep state: vid = 1.1 v i cc (a) v cc (v) static transient typ min max min max 0.0 1.068 1.043 1.093 1.023 1.113 1.0 1.064 1.039 1.089 1.019 1.109 2.0 1.060 1.035 1.085 1.015 1.105 3.0 1.056 1.031 1.081 1.011 1.101 4.0 1.052 1.027 1.077 1.007 1.097 5.0 1.048 1.023 1.073 1.003 1.093 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 32 datasheet table 17. v cc tolerances for the ultra-low voltage intel ? celeron ? processor: vid = 0.95 v i cc (a) v cc (v) static transient typ min max min max 0.0 0.938 0.913 0.963 0.893 0.983 1.0 0.934 0.909 0.959 0.889 0.979 2.0 0.930 0.905 0.955 0.885 0.975 3.0 0.926 0.901 0.951 0.881 0.971 4.0 0.922 0.897 0.947 0.877 0.967 5.0 0.918 0.893 0.943 0.873 0.963 6.0 0.914 0.889 0.939 0.869 0.959 7.0 0.910 0.885 0.935 0.865 0.955 8.0 0.906 0.881 0.931 0.861 0.951 table 18. v cc tolerances for the ultra-low voltage intel ? celeron ? processor in the deep sleep state: vid = 0.95 v i cc (a) v cc (v) static transient typ min max min max 0.0 0.922 0.897 0.947 0.865 0.967 1.0 0.918 0.893 0.943 0.861 0.963 2.0 0.914 0.889 0.939 0.857 0.959 3.0 0.910 0.885 0.935 0.853 0.955 4.0 0.906 0.881 0.931 0.849 0.951 table 19. agtl signal group dc specifications symbol parameter min max unit notes v il input low voltage -0.15 v ref -0.2 v v ih input high voltage v ref +0.2 v cct v see v cct,max in table 14 v oh output high voltage ? ? v see v cct,max in table 14 r on output low drive strength 16.67 w 2 i l leakage current for inputs, outputs and i/os 100 a 1 notes: 1. specification applies to leakage high only, for pins with on die r tt , (0 < v in/out v cct ). 2. refer to ibis models for i/v characteristics. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 33 table 20. agtl bus dc specifications symbol parameter min typ max unit notes v cct bus termination voltage 1.25 v 1 v ref input reference voltage 2 / 3 v cct ? 2% 2 / 3 v cct 2 / 3 v cct + 2% v 2%, 2 r tt bus termination strength 50 56 65 w on-die r tt , 3 notes: 1. refer to table 14 for minimum and maximum values. 2. v ref should be created from v cct by a voltage divider. 3. the reset# signal does not have an on-die r tt . it requires an off-die 56.2 ? 1% terminating resistor connected to v cct . table 21. clkref, apic, tap, cmos, and open-drain signal group dc specifications (sheet 1 of 2) symbol parameter min max unit notes v il15 input low voltage, 1.5 v cmos ?0.15 v cmosrefmin ? 300 mv v v il18 input low voltage, 1.8 v cmos ?0.36 0.36 v 1 , 2 v ih15 input high voltage, 1.5 v cmos v cmosrefmax + 250 mv 2.0 v 10 v ih15picd input high voltage, 1.5 v picd[1:0] v cmosrefmax + 200 mv 2.0 v 11 v ih18 input high voltage, 1.8 v cmos 1.44 2.0 v 1 , 2 v oh15 output high voltage, 1.5 v cmos n/a 1.615 v all outputs are open-drain v oh33 output high voltage, 3.3 v signals 2.0 3.465 v 3.3v + 5% v ol33 output low voltage, 3.3 v signals 0.8 v v ol output low voltage 0.3 v 8 v cmosref cmosref voltage 0.90 1.10 v 4 v clkref clkref voltage 1.187 1.312 v 9 notes: 1. parameter applies to the pwrgood signal only. 2. v ilx,min and v ihx,max only apply when bclk, bclk# and picclk are stopped. picclk should be stopped in the low state. see tables 28 and 29 for dc levels when bclk and bclk# are stopped. 3. measured at 9 ma. 4. v cmosref should be created from a stable 1.5-v supply using a voltage divider. it must track the voltage supply to maintain noise immunity. the same 1.5-v supply should be used to power the chipset cmos i/o buffers that drive these signals. 5. (0 vin/out v ihx,max ). 6. specified as the minimum amount of current that the output buffer must be able to sink. however, v ol,max cannot be ensured if this specification is exceeded. 7. parameter applies to vttpwrgd signal only. 8. applies to non-agtl signals except bclk, pwrgood, picclk, bsel[1:0], vid[4:0]. 9. 5% dc tolerance. clkref must be generated from the 2.5-v supply used to generate the bclk signal. ac tolerance must be less than ?40 db @ 1 mhz. 10.applies to all tap and cmos signals (not to apic signals). 11. applies to picd[1:0]. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 34 datasheet 3.6 ac specifications 3.6.1 system bus, clock, apic, tap, cmos, and open-drain ac specifications all system bus ac specifications for the agtl signal group are relative to the crossing point of the rising edge of the bclk input and falling edge of the bclk# input. all agtl timings are referenced to v ref for both 0 and 1 logic levels unless otherwise specified. all apic, tap, cmos, and open-drain signals except pwrgood are referenced to 1.0 v. all minimum and maximum specifications are at points within the power supply ranges shown in tables 15 through 18 and junction temperatures (tj) in the range 0 c to 100 c unless otherwise noted. tj must be less than or equal to 100 c (or the otherwise-noted given value) for all functional processor states. v ilvttpwr input low voltage, vttpwrgd 0.4 v 7 v ihvttpwr input high voltage, vttpwrgd 1.0 v 7 r on 30 w 3 i ol output low current 10 ma 6 i l leakage current for inputs, outputs and i/os 100 a 5 table 21. clkref, apic, tap, cmos, and open-drain signal group dc specifications (sheet 2 of 2) symbol parameter min max unit notes notes: 1. parameter applies to the pwrgood signal only. 2. v ilx,min and v ihx,max only apply when bclk, bclk# and picclk are stopped. picclk should be stopped in the low state. see tables 28 and 29 for dc levels when bclk and bclk# are stopped. 3. measured at 9 ma. 4. v cmosref should be created from a stable 1.5-v supply using a voltage divider. it must track the voltage supply to maintain noise immunity. the same 1.5-v supply should be used to power the chipset cmos i/o buffers that drive these signals. 5. (0 vin/out v ihx,max ). 6. specified as the minimum amount of current that the output buffer must be able to sink. however, v ol,max cannot be ensured if this specification is exceeded. 7. parameter applies to vttpwrgd signal only. 8. applies to non-agtl signals except bclk, pwrgood, picclk, bsel[1:0], vid[4:0]. 9. 5% dc tolerance. clkref must be generated from the 2.5-v supply used to generate the bclk signal. ac tolerance must be less than ?40 db @ 1 mhz. 10.applies to all tap and cmos signals (not to apic signals). 11. applies to picd[1:0]. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 35 table 22. system bus clock ac specifications symbol parameter min typ max unit notes 1 system bus frequency 100 mhz t1s1 bclk period 10 ns 2 t1s1abs bclk period ? instantaneous minimum 9.75 ns 2 t2s1 bclk period stability 250 ps 2 , 3 , 4 t3s1 bclk high time 2.70 ns at >2.0 v t4s1 bclk low time 2.45 ns at <0.5 v t5s1 bclk rise time 0.4 1.6 ns 5 t6s1 bclk fall time 0.4 1.6 ns 5 notes: 1. all ac timings for agtl and cmos signals are referenced to the bclk rising edge at 1.25 v. 2. period, jitter, skew and offset measured at 1.25 v. 3. not 100% tested. specified by design/characterization. 4. measured on the rising edge of adjacent bclks at 1.25 v. the jitter present must be accounted for as a component of bclk skew between devices. 5. measured between 0.5 v and 2.0 v. table 23. valid ultra-low voltage intel ? celeron ? processor frequencies bclk frequency (mhz) frequency multiplier core frequency (mhz) power-on configuration bits [27,25:22] 100 6.5 650 0, 1111 100 4 400 0, 0010 note: while other combinations of bus and core frequencies are defined, operation at frequencies other than those listed above will not be validated by intel and are not ensured. the frequency multiplier is programmed into the processor when it is manufactured, and it cannot be changed. table 24. agtl signal groups ac specifications r tt = 56 ? internally terminated to v cct ; v ref = 2 / 3 v cct ; load = 50 ohms symbol parameter min max unit figure notes 1 t7 agtl output valid delay 0.40 3.25 ns 7 t8 agtl input setup time 1.30 ns 82 , 3 t9 agtl input hold time 1 ns 84 t10 reset# pulse width 1 ms 9 , 10 notes: 1. all ac timings for agtl signals are referenced to the crossing point of the bclk rising edge and the bclk# falling edge for differential clocking and to the bclk rising edge at 1.25 v for single ended clocking. all agtl signals are referenced at v ref . reset# may be asserted (active) asynchronously, but must be deasserted synchronously. 2. specification is for a minimum 0.40-v swing from v ref -200 mv to v ref +200 mv. 3. specification is for a maximum 0.8-v swing from vcct-0.8 v to vcct. 4. after v cc , v cct , and bclk, bclk# become stable and pwrgood is asserted. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 36 datasheet table 25. cmos and open-drain signal groups ac specifications symbol parameter min max unit figure notes 1, 2 t14 1.5v input pulse width, except pwrgood and lint[1:0] 2bclks 7 active and inactive states t14b lint[1:0] input pulse width 6 bclks 73 t15 pwrgood inactive pulse width 2 s 10 4 , 5 notes: 1. all ac timings for cmos and open-drain signals are referenced to the crossing point of the bclk rising edge and bclk# falling edge for differential clocking and to the rising edge of bclk at 1.25 v for single ended clocking. all cmos and open-drain signals are referenced at 1.0 v. 2. minimum output pulse width on cmos outputs is 2 bclks. 3. this specification only applies when the apic is enabled and the lint1 or lint0 signal is configured as an edge triggered interrupt with fixed delivery, otherwise specification t14 applies. 4. when driven inactive, or after v cc , v cct and bclk, bclk# become stable. pwrgood must remain below v il18,max until all the voltage planes meet the voltage tolerance specifications in tables 15 through 18 . and bclk, bclk# have met the bclk, bclk# ac specifications in tables 30 and 31 for at least 2 s. pwrgood must rise error-free and monotonically to 1.8 v. 5. if the bclk settling time specification (t60) may be ensured at power-on reset then the pwrgood inactive pulse width specification (t15) is waived and bclk may start after pwrgood is asserted. pwrgood must still remain below v il25,max until all the voltage planes meet the voltage tolerance specifications. table 26. reset configuration ac specifications and power on/power down timings (sheet 1 of 2) symbol parameter min typ max unit figure notes t16 reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) setup time 4bclks 9 before deassertion of reset# t17 reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) hold time 220bclks 9 after clock that deasserts reset# t18 reset#/pwrgood setup time 1 ms 10 before deassertion of reset# ? t18a v cct to vttpwrgd setup time 1 ms 10 t18b v cc to pwrgood setup time 10 ms 10 t18c bsel, vid valid time before vttpwrgd assertion 1s 10 t18d reset# inactive to valid outputs 1 bclk 9 t18e reset# inactive to drive signals 4 bclks 9 t19a time from v cc (nominal)-12% to pwrgood low 0ns 11 v cc (nominal) is the vid voltage setting t19b all outputs valid after pwrgood low 0ns 11 t19c all inputs required valid after pwrgood low 0ns 11 ? at least 1 ms must pass after pwrgood rises above v ih18min and bclk, bclk# meet their ac timing specification until reset# may be deasserted. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 37 t20a time from v cct -12% to vttpwrgd low 0ns 12 t20b all outputs valid after vttpwrgd low 0ns 12 t20c all inputs required valid after vttpwrgd low 0ns 12 t20d vid, bsel signals valid after vttpwrgd low 0ns 12 t20e vttpwrgd transition time 100 s measurement from 300 mv to 900 mv. amount of noise (glitch) less than 100 mv. see section 4.3.1 for details table 27. apic bus signal ac specifications symbol parameter min max unit figure notes 1 t21 picclk frequency 2 33.3 mhz 2 t22 picclk period 30 500 ns t23 picclk high time 10.5 ns at>1.6 v t24 picclk low time 10.5 ns at<0.4 v t25 picclk rise time 0.25 3.0 ns (0.4 v ? 1.6 v) t26 picclk fall time 0.25 3.0 ns (1.6 v ? 0.4 v) t27 picd[1:0] setup time 8.0 ns 73 t28 picd[1:0] hold time 2.5 ns 73 t29 picd[1:0] valid delay (rising edge) picd[1:0] valid delay (falling edge) 1.5 1.5 8.7 12.0 ns 63 , 4 notes: 1. all ac timings for apic signals are referenced to the picclk rising edge at 1.0 v. all cmos signals are referenced at 1.0 v. 2. the minimum frequency is 2 mhz when picd0 is at 1.5 v at reset referenced to picclk rising edge. 3. for open-drain signals, valid delay is synonymous with float delay. 4. valid delay timings for these signals are specified into 150 ? to 1.5 v and 0 pf of external load. for real system timings these specifications must be derated for external capacitance at 105 ps/pf. table 26. reset configuration ac specifications and power on/power down timings (sheet 2 of 2) symbol parameter min typ max unit figure notes ? at least 1 ms must pass after pwrgood rises above v ih18min and bclk, bclk# meet their ac timing specification until reset# may be deasserted. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 38 datasheet table 28. tap signal ac specifications symbol parameter min max unit figure notes 1 t30 tck frequency ? 16.67 mhz t31 tck period 60 ? ns t32 tck high time 25.0 ns v cmosref +0.2 v, 2 t33 tck low time 25.0 ns v cmosref -0.2 v, 2 t34 tck rise time 5.0 ns (v cmosref -0.2 v) ? (v cmosref +0.2 v), 2 , 3 t35 tck fall time 5.0 ns (v cmosref +0.2 v) ? (v cmosref -0.2 v), 2 , 3 t36 trst# pulse width 40.0 ns 14 asynchronous, 2 t37 tdi, tms setup time 5.0 ns 13 4 t38 tdi, tms hold time 14.0 ns 13 4 t39 tdo valid delay 1.0 10.0 ns 13 5 , 6 t40 tdo float delay 25.0 ns 13 2 , 5 , 6 t41 all non-test outputs valid delay 2.0 25.0 ns 13 5 , 7 , 8 t42 all non-test outputs float delay 25.0 ns 13 2 , 5 , 7 , 8 t43 all non-test inputs setup time 5.0 ns 13 4 , 7 , 8 t44 all non-test inputs hold time 13.0 ns 13 4 , 7 , 8 notes: 1. all ac timings for tap signals are referenced to the tck rising edge at 1.0 v. all tap and cmos signals are referenced at 1.0 v. 2. not 100% tested. specified by design/characterization. 3. 1 ns may be added to the maximum tck rise and fall times for every 1 mhz below 16 mhz. 4. referenced to tck rising edge. 5. referenced to tck falling edge. 6. valid delay timing for this signal is specified into 150 ? terminated to 1.5 v and 0 pf of external load. for real system timings these specifications must be derated for external capacitance at 105 ps/pf. 7. non-test outputs and inputs are the normal output or input signals (except tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 8. during debug port operation use the normal specified timings rather than the tap signal timings. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 39 table 29. quick start/deep sleep ac specifications symbol parameter min max unit figure notes 1 t45 quick start cycle completion to clock stop or dpslp# assertion 100 bclks 15 , 16 t46 quick start cycle completion to input signals stable 0s 15 , 16 t47 deep sleep pll lock latency 0 30 s 15 , 16 2 t48 stpclk# hold time from pll lock 0 ns 15 , 16 t49 input signal hold time from stpclk# deassertion 8bclks 15 , 16 notes: 1. input signals other than reset# and bpri# must be held constant in the quick start state. 2. the bclk, bclk# settling time specification (t60) applies to deep sleep state exit under all conditions. figure 6. bclk (single ended)/picclk/tck generic clock timing waveform figure 7. differential bclk/bclk# waveform (common mode) clk v h v l v trip t h t l t p t r t f d0003-01 bclk bclk# vcross v2,v3 (max) v1,v3 (min) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 40 datasheet figure 8. bclk/bclk# waveform (differential mode) figure 9. valid delay timings notes: 1. tx = t7, t11, t29 (valid delay) 2. tpw = t14, t14b (pulse width) 3. v = v ref for agtl signal group; 1.0v for cmos, open-drain, apic, and tap signal groups 4. vc = crossing point of bclk rising edge and bclk# falling edge for bclk references (differential clock) = 1.25v (single ended clock) figure 10. setup and hold timings notes: 1. ts = t8, t27 (setup time) 2. th =t9, t28 (hold time) 3. v = v ref for agtl signals; 1.0 v for cmos, apic, and tap signals 4. vc = crossing point of bclk rising edge and bclk# falling edge for bclk references (differential clock) = 1.25 v (single ended clock) 0v t6 t5 t1 v4 v5 v ih_diff v il_diff clk signal t x t x t pw v valid valid d0004-00 vc vc clk signal v valid t h ts d0005-0 0 vc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 41 ? figure 11. cold/warm reset and configuration timings notes: 1. tt = t9 (agtl input hold time) 2. tu = t8 (agtl input setup time) 3. tv = t10 (reset# pulse width) 4. tw = t16 (reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) setup time) 5. tx = t17 (reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) hold time) 6. ty = t18d (reset# inactive to valid outputs) 7. tz = t18e (reset# inactive to drive signals) 8. vc = crossing point of bclk rising edge and bclk# falling edge (differential clock) = 1.25 v (single ended clock) bclk reset# t v t x t t t u v c v d0006-02 configuration (a[15:5], breq0#, flush#, init#, picd0) t w valid picd[1:0] agtl/non-agtl outputs non-configuration inputs t y valid t z active www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 42 datasheet figure 12. power-on sequence and reset timings notes: 1. ta = t15 (pwrgood inactive pulse width) 2. tb = t18 (reset#/pw rgood setup time) 3. tc = t18b (setup time from v cc valid until pwrgood assertion) 4. td = t18a (setup time from v cct valid to vttpwrgd assertion) 5. te = t18c(vid, bsel valid time before vttpwrgd assertion) v cct valid vttpwrgd vid[4:0]/ bsel[1:0] cmosref/ clkref/v ref pwrgood reset# bclk/bclk# v ih18,min v il18,max v ihvttpw r,min v ilvttpw r,max t a t c t b v cc v0040-00 t e t d www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 43 figure 13. power down sequencing and timings (v cc leading) notes: 1. ta = t19a (time from v cc (nominal) -12% to pwrgood low) 2. tb = t19b (all outputs valid after pwrgood low) 3. tc = t19c (all inputs required valid after pwrgood low) vttpwrgd bclk/bclk# v0044-00 v cct, v ref v ccmos, cmosref, clkref vid[4:0] bsel[1:0] vcc picclk pwrgood reset# picd[1:0] agtl outputs other cmos outputs all inputs t a t b t c vcc-12% v il18 valid valid valid valid valid www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 44 datasheet figure 14. power down sequencing and timings (v cct leading) notes: 1. ta = t20a (time from v cct -12% to vttpwrgd low) 2. tb = t20b (all outputs valid after vttpwrgd low) 3. tc = t20c (all inputs required valid after vttpwrgd low) 4. td = t20d (vid, bsel signals valid after vttpwrgd low) vttpwrgd bclk/bclk# v0045-00 v cct, v ref v cmos, cmosref, clkref vid[4:0] bsel[1:0] vcc picclk pwrgood reset# picd[1:0] agtl outputs other cmos outputs all inputs t a t b, t c, t d v cct -12% v ilvttpwr valid valid valid valid valid valid www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 45 figure 15. test timings (boundary scan) notes: 1. tr = t43 (all non-test inputs setup time) 2. ts = t44 (all non-test inputs hold time) 3. tu = t40 (tdo float delay) 4. tv = t37 (tdi, tms setup time) 5. tw = t38 (tdi, tms hold time) 6. tx = t39 (tdo valid delay) 7. ty = t41 (all non-test outputs valid delay) 8. tz = t42 (all non-test outputs float delay) figure 16. test reset timings note: tq=t36 (trst# pulse width) tck tdi, tms input signals tdo output signals 0.75v t v t w t r t s t x t u t y t z d0008-01 trst# 0.75v t q d0009-0 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 46 datasheet figure 17. quick start/deep sleep timing (bclk stopping method) notes: 1. tv = t45 (stop grant acknowledge bus cycle completion to clock shut off delay) 2. tw = t46 (setup time to input signal hold requirement) 3. tx = t47 (deep sleep pll lock latency) 4. ty = t48 (pll lock to stpclk# hold time) 5. tz = t49 (input signal hold time) figure 18. quick start/deep sleep timing (dpslp# assertion method) notes: 1. tv = t45 (stop grant acknowledge bus cycle completion to dpslp# assertion) 2. tw = t46 (setup time to input signal hold requirement) 3. tx = t47 (deep sleep pll lock latency) 4. ty = t48 (pll lock to stpclk# hold time) 5. tz = t49 (input signal hold time) t w stpgnt stopped bclk stpclk# cpu bus dpslp# compatibility signals changing normal quick start deep sleep quick start normal frozen t v t y t z t x v00102-00 t w stpgnt bclk stpclk# cpu bus dpslp# compatibility signals changing normal quick start deep sleep quick start normal frozen t v t y t z t x v00103-00 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 47 4.0 system signal simulations systems must be simulated using ibis models to determine if they are compliant with this specification. all references to bclk signal quality also apply to bclk# for differential clocking. 4.1 system bus clock (bclk) and picclk dc specifications and ac signal quality specifications table 30. bclk (differential) dc specifications and ac signal quality specifications symbol parameter min max unit figure notes v1 v il,bclk -0.2 0.35 v 1 v2 v ih,bclk 0.92 1.45 v 1 v3 v in absolute voltage range -0.2 1.45 v undershoot/ overshoot, 2 v4 bclk rising edge ringback 0.35 v 63 v5 bclk falling edge ringback -0.35 v 63 v bclk_dpslp bclk voltage in deep sleep state 0.4 1.45 v 4 v bclk#_dpslp bclk# voltage in deep sleep state 0 v bclk_dpslp - 0.2 v v 4 notes: 1. the clock must rise/fall monotonically between vil,bclk and vih,bclk. 2. these specifications apply only when bclk, bclk# are running. 3. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) voltage the differential waveform may go to after passing the vih_diff (rising) or vil_diff (falling) levels. vil_diff (max) = -0.57 v, vih_diff (min) = 0.57 v. 4. applies when bclk and bclk# are stopped in deep sleep state. table 31. bclk (single ended) dc specifications and ac signal quality specifications symbol parameter min max unit figure notes v1 v il,bclk 0.3 v 18 1 v2 v ih,bclk 2.2 v 18 1 v3 v in absolute voltage range -0.5 3.1 v 18 undershoot/overshoot, 2 v4 bclk rising edge ringback 2.0 v 18 absolute value, 3 v5 bclk falling edge ringback 0.5 v 18 absolute value, 3 notes: 1. the clock must rise/fall monotonically between v il,bclk and v ih,bclk . bclk must be stopped in the low state. 2. these specifications apply only when bclk is running. bclk may not be above v ih,bclk,max or below v il, bclk,min for more than 50% of the clock cycle. 3. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal may go to after passing the v ih,bclk (rising) or v il,bclk (falling) voltage limits. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 48 datasheet 4.2 agtl ac signal quality specifications ringback specifications for the agtl signals are as follows: ringback below v ref,max + 200 mv is not authorized during low to high transitions. ringback above v ref,min ? 200 mv is not authorized during high to low transitions. overshoot and undershoot specifications are documented in table 33 and illustrated in figure 20 . table 32. picclk dc specifications and ac signal quality specifications symbol parameter min max unit figure notes v1 v il20 0.4 v 18 1 v2 v ih20 1.6 v 18 1 v3 v in absolute voltage range -0.5 2.4 v 18 undershoot, overshoot, 2 v4 picclk rising edge ringback 1.6 v 18 absolute value, 3 v5 picclk falling edge ringback 0.4 v 18 absolute value, 3 notes: 1. the clock must rise/fall monotonically between v il20 and v ih20 . 2. these specifications apply only when picclk is running. see the dc specifications for when picclk is stopped. picclk may not be above v ih20,max or below v il20,min for more than 50% of the clock cycle. 3. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the picclk signal may go to after passing the v ih20 (rising) or v il20 (falling) voltage limits. figure 19. bclk (single ended)/picclk generic clock waveform v0012-01 v1 v2 v3 max v4 v3 min v5 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 49 figure 20. maximum acceptable overshoot/undershoot waveform table 33. 100-mhz agtl signal group overshoot/undershoot tolerance at the processor core max v cct + overshoot/ undershoot magnitude (volts) allowed pulse duration (ns) [tj=100c (see note 7)] activity factor = 0.01 activity factor = 0.1 activity factor = 1 1.78 1.6 0.16 0.016 1.73 4.5 0.45 0.045 1.68 9.5 0.95 0.095 1.63 20 2.0 0.2 1.58 20 4.2 0.42 1.53 20 8.5 0.85 1.48 20 19 1.9 notes: 1. under no circumstances should the sum of the max v cct and absolute value of the overshoot/undershoot voltage exceed 1.78 v. 2. activity factor of 1 represents the same toggle rate as the 100-mhz clock. 3. ringbacks below v cct cannot be subtracted from overshoots. lesser undershoot does not allocate longer or larger overshoot. 4. ringbacks above ground cannot be subtracted from undershoots. lesser overshoot does not allocate longer or larger undershoot. 5. system designers are encouraged to follow intel provided agtl layout guidelines. 6. all values are specified by design characterization and are not tested. 7. tj = 85 c for 1.33 ghz. max vss time dependant overshoot time dependant undershoot min www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 50 datasheet 4.3 non-agtl signal quality specifications signals driven to the ulv intel ? celeron ? processor should meet signal quality specifications to ensure that the processor reads data properly and that incoming signals do not affect the long-term reliability of the processor. the overshoot and undershoot specifications for non-agtl signals are shown in table 34 . ringback must not exceed the cmos v ih and v il specification levels in table 21 . 4.3.1 pwrgood, vttpwrgd signal quality specifications the processor requires pwrgood to be a clean indication that clocks and the power supplies (v cc , v cct , etc.) are stable and within their specifications. clean implies that the signal will remain below v il18 and without errors from the time that the power supplies are turned on, until they come within specification. the signal will then transition monotonically to a high (1.8 v) state. the vttpwrgd signal must also transition monotonically. the vttpwrgd signal is an input to the processor used to determine that the vtt power is stable and the vid and bsel signals should be driven to their final state by the processor. to ensure the processor correctly reads this signal, the processor must meet the requirement shown in table 35 while the signal is in its transition region of 300 mv to 900 mv. also, vttpwrgd should only enter the transition region once, after vtt is at nominal values, for the assertion of the signal. table 34. non-agtl signal group overshoot/undershoot tolerance at the processor core max v cmos + overshoot/ undershoot magnitude (volts) allowed pulse duration (ns) [tj=100c (see note 6)] activity factor = 0.01 activity factor = 0.1 activity factor = 1 2.38 6.5 0.65 0.065 2.33 13 1.3 0.13 2.28 29 2.9 0.29 2.23 60 6 0.6 2.18 60 12 1.2 2.13 60 26 2.6 2.08 60 56 5.6 notes: 1. v cmos (nominal) = 1.5 v. 2. under no circumstances should the sum of the max v cmos and absolute value of the overshoot/ undershoot voltage exceed 2.38 v. 3. activity factor of 1 represents a toggle rate of 33 mhz. 4. system designers are encouraged to follow intel provided non-agtl layout guidelines. 5. all values are specified by design characterization, and are not tested. 6. tj = 85 c for 1.33 ghz. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 51 4.3.1.1 vttpwrgd noise parameter specification in addition, the vttpwrgd signal should have reasonable transition time through the transition region. a sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal. intel recommends the following transition time for the vttpwrgd signal. 4.3.1.2 vttpwrgd transition parameter recommendation in addition, the vtt_pwrgd signal should have reasonable transition time through the transition region. a sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal. intel recommends the following transition time for the vtt_pwrgd signal. 4.3.1.2.1 transition region the transition region covered by this requirement is 300 mv to 900 mv. once the vttpwrgd signal is in that voltage range, the processor is more sensitive to noise, which may be present on the signal. the transition region when the signal first crosses the 300-mv voltage level and continues until the last time it is below 900 mv. 4.3.1.2.2 transition time the transition time is defined as the time the signal takes to move through the transition region. a 100-s transition time will ensure that the processor receives a good transition edge. 4.3.1.2.3 noise the signal quality of the vttpwrgd signal is critical to the correct operation of the processor. every effort should be made to ensure this signal is monotonic in the transition region. if noise or glitches are present on this signal, the noise or glitches must be kept to less than 100 mv of a voltage drop from the highest voltage level received to that point. this glitch must remain less than 100 mv until the excursion ends by the voltage returning to the highest voltage previously received. see figure 21 for an example graph of this situation and requirements. table 35. vttpwrgd noise parameter specification parameter specification amount of noise (glitch) less than 100 mv table 36. vttpwrgd transition parameter recommendation parameter recommendation transition time (300 mv to 900 mv) less than or equal to 100 s www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 52 datasheet figure 21. vttpwrgd noise specification www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 53 5.0 mechanical specifications 5.1 surface mount micro fc-bga package the ulv intel ? celeron ? processor is packaged in a surface mount, 479-ball micro fc-bga package. mechanical specifications are shown in table 37 . figure 22 through figure 24 illustrate different views of the package. the micro fc-bga package may have capacitors placed in the area surrounding the die. because the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. doing so may short the capacitors, and possibly damage the device or render it inactive. the use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. table 37. micro fc-bga package mechanical specifications symbol parameter min max unit a overall height, as delivered 1 2.27 2.77 mm a2 die height 0.854 mm b ball diameter 0.78 mm d package substrate length 34.9 35.1 mm e package substrate width 34.9 35.1 mm d1 die length 11. 18 3 10.82 4 mm e1 die width 7.20 3 6.85 4 mm e ball pitch 1.27 mm n ball count 479 each k keep-out outline from edge of package 5 mm k1 keep-out outline at corner of package 7 mm k2 capacitor keep-out height - 0.7 mm s package edge to first ball center 1.625 mm -- solder ball coplanarity 0.2 mm pdie allowable pressure on the die for thermal solution - 689 kpa w package weight 4.5 g notes: 1. all dimensions are subject to change. 2. overall height as delivered. values were based on design specifications and tolerances. final height after surface mount depends on oem motherboard design and smt process. 3. dimension for cpuid = 0x06b1. 4. dimension for cpuid = 0x06b4. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 54 datasheet figure 22. micro fc-bga package ? top and bottom isometric views figure 23. micro fc-bga package ? top and side views note: all dimensions are in millimeters. values shown are for reference only. see table 36 for specific details. top view bottom view label die package keepout capacitor area 35 (e) 35 (d) pin a1 corner e1 d1 a ?0.78 (b) 479 places k2 substrate keepout zone do not contact package inside this line 7 (k1) 8 places 5 (k) 4 places a2 0.20 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 55 5.2 signal listings figure 25 is a top-side view of the ball map of the ulv intel ? celeron ? processor with the voltage balls called out. table 38 lists the signals in ball number order. table 39 lists the signals in signal name order. figure 24. micro fc-bga package ? bottom view note: all dimensions are in millimeters. values shown are for reference only. see table 39 for specific details. 1 2 3 4 6 8 1012141618 20 22 24 26 57911 13 15 17 19 21 23 25 a b c e d f g h j k l m n p r t u v w y aa ab ac ad ae af 25x 1.27 (e) 25x 1.27 (e) 1.625 (s) 4 places 1.625 (s) 4 places www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 56 datasheet figure 25. ball map ? top view note: a2 pin is de-populated on micro-fcpga package. a10# vref nc a31# br eq0# a23# a27# a24# nc a35# a26# a33# a32# d0# d2# d15# d9# d7# vref d8# d10# d11# vss vcct nc vss a25# vss a17# vss a21# vss a20# vss a18# vss a34# vss reset# vss d1# vss d4# vss d17# vss d18# d14# d24# vss nc a16# a28# nc vcct a19# vcct a22# vcct a30# vcct a29# vcct berr# vcct d6# vcct d12# vcct d5# vcct nc vss d20# vss d30# nc vss a13# vss vcct vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc d3# d13# d22# nc nc testhi vcct vcc vcct vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d16# d23# vss d19# nc vss a14# vss vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d21# d36# d27# a9# a5# a15# vcct vcc vss vcc vss vcct d25# vss d32# a12# vss a8# vss vss vcc vss vcc vss d26# d29# vref a4# a7# a11# vcct vcc vss vcc vss vcct d34# vss d38# a3# vss a6# vss vss vcc vss vcc vss d31# d33# d35# req4# bnr# req1# vcct nc vss vcc vss vcct d28# vss d42# vss vss vss rsp# vcc vss vcc vss d39# d45# d48# vref pll2 pll1 nc vcc vss vcc vss vcct nc vss d37# nc vss api# nc nc vcc vss vcc vss d49# d41# nc req0# bpri# vid4 vss vcc vss vcc vss vcct d43# vss d44# req2# vss defer# rp# vss vcc vss vcc vss d47# d57# d51# req3# hit m # rs2# vss vcc vss vcc vss vcct d52# vss d40# rs1# vss lock# vcct vss vcc vss vcc vss d63# d46# d55# trdy# aerr# dbsy # vss vcc vss vcc vss vcct d59# vss d54# drdy# vss rs0# vss vcc vss vcc vss d58# d53# d60# vref hit # ads # vcct vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcct d62# vss d50# vid0 vss ap0# pwr good vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d61# d56# vref bclk vid1 a20m # vcct vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcct dep3# vss dep6# bcl k# / clkref vss smi# nc cmos ref vcct tdi vcct ignne# tck tdo vcct nc vcct lint0 nctrl picd1 vcct picd0 vcct bpm 1# bpm 0# nc dep7# dep1# dep5# vss vid2 vcct stpclk# vss init# vss nc vss nc vss bsel0 vss lint1 vss rtt impedp vss vcct vss bp3# vss prdy# vss dep0# dep2# vss vcct vcct vid3 ierr# flush# ferr# tms dps lp# vref bsel1 testhi cmos ref thrmda thrmdc trst# edge ctrlp nc nc preq# picclk vref bp2# binit# dep4# vss vss a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 vtt pwrgd a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 vcc vss other vcct testlo testlo nc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 57 table 38. signal listing in order by ball number (sheet 1 of 4) no. signal name no. signal name no. signal name no. signal name a3 a10# b18 vss d7 vss e22 vss a4 vref b19 d4# d8 vcc e23 d16# a5 nc b20 vss d9 vss e24 d23# a6 a31# b21 d17# d10 vcc e25 vss a7 breq0# b22 vss d11 vss e26 d19# a8 a23# b23 d18# d12 vcc f1 nc a9 a27# b24 d14# d13 vss f2 vss a10 a24# b25 d24# d14 vcc f3 a14# a11 nc b26 vss d15 vss f4 vss a12 a35# c1 nc d16 vcc f5 vss a13 a26# c2 a16# d17 vss f6 vcc a14 a33# c3 a28# d18 vcc f7 vss a15 a32# c4 nc d19 vss f8 vcc a16 d0# c5 vcct d20 vcc f9 vss a17 d2# c6 a19# d21 vss f10 vcc a18 d15# c7 vcct d22 vcc f11 vss a19 d9# c8 a22# d23 d3# f12 vcc a20 d7# c9 vcct d24 d13# f13 vss a21 vref c10 a30# d25 d22# f14 vcc a22 d8# c11 vcct d26 nc f15 vss a23d10#c12a29# e1 nc f16vcc a24 d11# c13 vcct e2 testhi f17 vss a25 vss c14 berr# e3 vttpwrgd f18 vcc a26 vcct c15 vcct e4 vcct f19 vss b1 nc c16 d6# e5 vcc f20 vcc b2 vss c17 vcct e6 vcct f21 vss b3 a25# c18 d12# e7 vcc f22 vcc b4 vss c19 vcct e8 vss f23 vss b5 a17# c20 d5# e9 vcc f24 d21# b6 vss c21 vcct e10 vss f25 d36# b7 a21# c22 nc e11 vcc f26 d27# b8 vss c23 vss e12 vss g1 a9# b9 a20# c24 d20# e13 vcc g2 a5# b10 vss c25 vss e14 vss g3 a15# b11 a18# c26 d30# e15 vcc g4 vcct b12 vss d1 nc e16 vss g5 vcc b13 a34# d2 vss e17 vcc g6 vss www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 58 datasheet b14 vss d3 a13# e18 vss g21 vcc b15 reset# d4 vss e19 vcc g22 vss b16 vss d5 vcct e20 vss g23 vcct b17 d1# d6 vcc e21 vcc g24 d25# g25 vss l4 vcct p23 vss v2 vss g26 d32# l5 nc p24 d49# v3 lock# h1 a12# l6 vss p25 d41# v4 vcct h2 vss l21 vcc p26 nc v5 vss h2 vss l21 vcc p26 nc v5 vss h3 a8# l22 vss r1 req0# v6 vcc h4 vss l23 vcct r2 bpri# v21 vss h5 vss l24 d28# r3 vid4 v22 vcc h6 vcc l25 vss r4 vss v23 vss h21 vss l26 d42# r5 vcc v24 d63# h22 vcc m1 testlo r6 vss v25 d46# h23 vss m2 vss r21 vcc v26 d55# h24 d26# m3 vss r22 vss w1 trdy# h25 d29# m4 vss r23 vcct w2 aerr# h26 vref m5 rsp# r24 d43# w3 dbsy# j1 a4# m6 vcc r25 vss w4 vss j2 a7# m21 vss r26 d44# w5 vcc j3 a11# m22 vcc t1 req2# w6 vss j4 vcct m23 vss t2 vss w21 vcc j5 vcc m24 d39# t3 defer# w22 vss j6 vss m25 d45# t4 rp# w23 vcct j21 vcc m26 d48# t5 vss w24 d59# j22 vss n1 vref t6 vcc w25 vss j23 vcct n2 pll2 t21 vss w26 d54# j24 d34# n3 pll1 t22 vcc y1 drdy# j25 vss n4 nc t23 vss y2 vss j26 d38# n5 vcc t24 d47# y3 rs0# k1 a3# n6 vss t25 d57# y4 testlo k2 vss n21 vcc t26 d51# y5 vss k3 a6# n22 vss u1 req3# y6 vcc k4 vss n23 vcct u2 hitm# y21 vss k5 vss n24 nc u3 rs2# y22 vcc k6 vcc n25 vss u4 vss y23 vss k21 vss n26 d37# u5 vcc y24 d58# table 38. signal listing in order by ball number (sheet 2 of 4) no. signal name no. signal name no. signal name no. signal name www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 59 k22 vcc p1 nc u6 vss y25 d53# k23 vss p2 vss u21 vcc y26 d60# k24 d31# p3 api# u22 vss aa1 vref k25 d33# p4 nc u23 vcct aa2 hit# k26 d35# p5 nc u24 d52# aa3 ads# l1 req4# p6 vcc u25 vss aa4 vcct l2 bnr# p21 vss u26 d40# aa5 vcc l3 req1# p22 vcc v1 rs1# aa6 vss aa7 vcc ab22 vcc ad11 tdo ae26 vss aa8 vss ab23 vss ad12 vcct af1 vcct aa9 vcc ab24 d61# ad13 nc af2 vcct aa10 vss ab25 d56# ad14 vcct af3 vid3 aa11 vcc ab26 vref ad15 lint0 af4 ierr# aa12 vss ac1 bclk ad16 nctrl af5 flush# aa13 vcc ac2 vid1 ad17 picd1 af6 ferr# aa14 vss ac3 a20m# ad18 vcct af7 tms aa15 vcc ac4 vcct ad19 picd0 af8 dpslp# aa16 vss ac5 vcc ad20 vcct af9 vref aa17 vcc ac6 vss ad21 bpm1# af10 bsel1 aa18 vss ac7 vcc ad22 bpm0# af11 testhi aa19 vcc ac8 vss ad23 nc af12 cmosref aa20 vss ac9 vcc ad24 dep7# af13 thrmda aa21 vcc ac10 vss ad25 dep1# af14 thrmdc aa22 vss ac11 vcc ad26 dep5# af15 trst# aa23 vcct ac12 vss ae1 vss af16 edgectrlp aa24 d62# ac13 vcc ae2 vid2 af17 nc aa25 vss ac14 vss ae3 vcct af18 nc aa26 d50# ac15 vcc ae4 stpclk# af19 preq# ab1 vid0 ac16 vss ae5 vss af20 picclk ab2 vss ac17 vcc ae6 init# af21 vref ab3 ap0# ac18 vss ae7 vss af22 bp2# ab4 pwrgood ac19 vcc ae8 nc af23 binit# ab5 vss ac20 vss ae9 vss af24 dep4# ab6 vcc ac21 vcc ae10 nc af25 vss ab7 vss ac22 vss ae11 vss af26 vss ab8 vcc ac23 vcct ae12 bsel0 ab9 vss ac24 dep3# ae13 vss ab10 vcc ac25 vss ae14 lint1 table 38. signal listing in order by ball number (sheet 3 of 4) no. signal name no. signal name no. signal name no. signal name www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 60 datasheet ab11 vss ac26 dep6# ae15 vss ab12 vcc ad1 bclk#/ clkref ae16 rttimpedp ab13 vss ad2 vss ae17 vss ab14 vcc ad3 smi# ae18 vcct ab15 vss ad4 nc ae19 vss ab16 vcc ad5 cmosref ae20 bp3# ab17 vss ad6 vcct ae21 vss ab18 vcc ad7 tdi ae22 prdy# ab19 vss ad8 vcct ae23 vss ab20 vcc ad9 ignne# ae24 dep0# ab21 vss ad10 tck ae25 dep2# table 39. signal listing in order by signal name (sheet 1 of 3) no. signal name signal buffer type no. signal name signal buffer type k1 a3# agtl i/o af23 binit# agtl i/o j1 a4# agtl i/o l2 bnr# agtl i/o g2 a5# agtl i/o af22 bp2# agtl i/o k3 a6# agtl i/o ae20 bp3# agtl i/o j2 a7# agtl i/o ad22 bpm0# agtl i/o h3 a8# agtl i/o ad21 bpm1# agtl i/o g1 a9# agtl i/o r2 bpri# agtl input a3 a10# agtl i/o a7 breq0# agtl i/o j3 a11# agtl i/o ae12 bsel0 3.3 v cmos output h1 a12# agtl i/o af10 bsel1 3.3 v cmos output d3 a13# agtl i/o ad5 cmosref cmos reference voltage f3 a14# agtl i/o af12 cmosref cmos reference voltage g3 a15# agtl i/o a16 d0# agtl i/o c2 a16# agtl i/o b17 d1# agtl i/o b5 a17# agtl i/o a17 d2# agtl i/o b11 a18# agtl i/o d23 d3# agtl i/o c6 a19# agtl i/o b19 d4# agtl i/o b9 a20# agtl i/o c20 d5# agtl i/o b7 a21# agtl i/o c16 d6# agtl i/o c8 a22# agtl i/o a20 d7# agtl i/o a8 a23# agtl i/o a22 d8# agtl i/o a10 a24# agtl i/o a19 d9# agtl i/o table 38. signal listing in order by ball number (sheet 4 of 4) no. signal name no. signal name no. signal name no. signal name www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 61 b3 a25# agtl i/o a23 d10# agtl i/o a13 a26# agtl i/o a24 d11# agtl i/o a9 a27# agtl i/o c18 d12# agtl i/o c3 a28# agtl i/o d24 d13# agtl i/o c12 a29# agtl i/o b24 d14# agtl i/o c10 a30# agtl i/o a18 d15# agtl i/o a6 a31# agtl i/o e23 d16# agtl i/o a15 a32# agtl i/o b21 d17# agtl i/o a14 a33# agtl i/o b23 d18# agtl i/o b13 a34# agtl i/o e26 d19# agtl i/o a12 a35# agtl i/o c24 d20# agtl i/o ac3 a20m# 1.5v cmos input f24 d21# agtl i/o aa3 ads# agtl i/o d25 d22# agtl i/o w2 aerr# agtl i/o e24 d23# agtl i/o ab3 ap0# agtl i/o b25 d24# agtl i/o p3 ap1# agtl i/o g24 d25# agtl i/o ac1 bclk clock input h24 d26# agtl i/o ad1 bclk#/clkref clock input f26 d27# agtl i/o c14 berr# agtl i/o l24 d28# agtl i/o h25 d29# agtl i/o af24 dep4# agtl i/o c26 d30# agtl i/o ad26 dep5# agtl i/o k24 d31# agtl i/o ac26 dep6# agtl i/o g26 d32# agtl i/o ad24 dep7# agtl i/o k25 d33# agtl i/o y1 drdy# agtl i/o j24 d34# agtl i/o af8 dpslp# 1.5 v cmos input k26 d35# agtl i/o af16 edgectrlp agtl control f25 d36# agtl i/o af6 ferr# 1.5 v open drain output n26 d37# agtl i/o af5 flush# 1.5 v cmos input j26 d38# agtl i/o aa2 hit# agtl i/o m24 d39# agtl i/o u2 hitm# agtl i/o u26 d40# agtl i/o af4 ierr# 1.5 v open drain output p25 d41# agtl i/o ad9 ignne# 1.5 v cmos input l26 d42# agtl i/o ae6 init# 1.5 v cmos input r24 d43# agtl i/o ad15 intr/lint0 1.5 v cmos input r26 d44# agtl i/o v3 lock# agtl i/o m25 d45# agtl i/o ae14 nmi/lint1 1.5 v cmos input v25 d46# agtl i/o ad16 nctrl agtl impedance control t24 d47# agtl i/o af20 picclk 1.8 v apic clock input table 39. signal listing in order by signal name (sheet 2 of 3) no. signal name signal buffer type no. signal name signal buffer type www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 62 datasheet m26 d48# agtl i/o ad19 picd0 1.5 v open drain i/o p24 d49# agtl i/o ad17 picd1 1.5 v open drain i/o aa26 d50# agtl i/o n3 pll1 pll analog voltage t26 d51# agtl i/o n2 pll2 pll analog voltage u24 d52# agtl i/o ae22 prdy# agtl output y25 d53# agtl i/o af19 preq# 1.5 v cmos input w26 d54# agtl i/o ab4 pwrgood 1.8 v cmos input v26 d55# agtl i/o r1 req0# agtl i/o ab25 d56# agtl i/o l3 req1# agtl i/o t25 d57# agtl i/o t1 req2# agtl i/o y24 d58# agtl i/o u1 req3# agtl i/o w24 d59# agtl i/o l1 req4# agtl i/o y26 d60# agtl i/o b15 reset# agtl input ab24 d61# agtl i/o t4 rp# agtl i/o aa24 d62# agtl i/o y3 rs0# agtl i/o v24 d63# agtl i/o v1 rs1# agtl i/o w3 dbsy# agtl i/o u3 rs2# agtl i/o t3 defer# agtl input m5 rsp# agtl input ae24 dep0# agtl i/o ae16 rttimpedp agtl pull-up control ad25 dep1# agtl i/o ad3 smi# 1.5 v cmos input ae25 dep2# agtl i/o ae4 stpclk# 1.5 v cmos input ac24 dep3# agtl i/o ad10 tck 1.5v jtag clock input ac2 vid1 voltage identification ad7 tdi jtag input ae2 vid2 voltage identification ad11 tdo jtag output af3 vid3 voltage identification e2 testhi test use only r3 vid4 voltage identification af11 testhi test use only a4 vref agtl reference voltage m1 testlo test use only a21 vref agtl reference voltage y4 testlo test use only n1 vref agtl reference voltage af13 thermda thermal diode anode af9 vref agtl reference voltage af14 thermdc thermal diode cathode af21 vref agtl reference voltage af7 tms jtag input aa1 vref agtl reference voltage w1 trdy# agtl i/o ab26 vref agtl reference voltage af15 trst# jtag input h26 vref agtl reference voltage ab1 vid0 voltage identification e3 vttpwrgd vcct power good signal table 39. signal listing in order by signal name (sheet 3 of 3) no. signal name signal buffer type no. signal name signal buffer type www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 63 table 40. voltage and no-connect ball locations signal name pin/ball numbers nc a2 , a5, a11, b1, c1, c4, c22, d1, d26, e1, f1, l5, n4, n24, p1, p4, p5, p26, ad4, ad13, ad23, ae8, ae10, af17, af18 vcc d6, d8, d10, d12, d14, d16, d18, d20, d22, e5, e7, e9, e11, e13, e15, e17, e19, e21, f6, f8, f10, f12, f14, f16, f18, f20, f22, g5, g21, h6, h22, j5, j21, k6, k22, l21, m6, m22, n5, n21, p6, p22, r5, r21, t6, t22, u5, u21, v6, v22, w5, w21, y6, y22, aa5, aa7, aa9, aa11, aa13, aa15, aa17, aa19, aa21, ab6, ab8, ab10, ab12, ab14, ab16, ab18, ab20, ab22, ac5, ac7, ac9, ac11, ac13, ac15, ac17, ac19, ac21 vcct a26, c5, c7, c9, c11, c13, c15, c17, c19, c21, d5, e4, e6, g4, g23, j4, j23, l4, l23, n23, r23, u23, v4, w23, aa4, aa23, ac4, ac23, ad6, ad8, ad12, ad14, ad18, ad20, ae3, ae18, af1, af2 vss a25, b2, b4, b6, b8, b10, b12, b14, b16, b18, b20, b22, b26, c23, c25, d2, d4, d7, d9, d11, d13, d15, d17, d19, d21, e8, e10, e12, e14, e16, e18, e20, e22, e25, f2, f4, f5, f7, f9, f11, f13, f15, f17, f19, f21, f23, g6, g22, g25, h2, h4, h5, h21, h23, j6, j22, j25, k2, k4, k5, k21, k23, l6, l22, l25, m2, m3, m4, m21, m23, n6, n22, n25, p2, p21, p23, r4, r6, r22, r25, t2, t5, t21, t23, u4, u6, u22, u25, v2, v5, v21, v23, w4, w6, w22, w25, y2, y5, y21, y23, aa6, aa8, aa10, aa12, aa14, aa16, aa18, aa20, aa22, aa25, ab2, ab5, ab7, ab9, ab11, ab13, ab15, ab17, ab19, ab21, ab23, ac6, ac8, ac10, ac12, ac14, ac16, ac18, ac20, ac22, ac25, ad2, ae1, ae5, ae7, ae9, ae11, ae13, ae15, ae17, ae19, ae21, ae23, ae26, af25, af26 note: a2 pin is de-populated on the micro-fcpga package. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 64 datasheet this page intentionally left blank. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 65 6.0 v cc thermal specifications in order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or other heat transfer system) must make firm contact to the exposed processor die. the processor die must be clean before the thermal solution is attached or the processor may be damaged. table 41 provides the thermal design power (tdp) dissipation and the minimum and maximum t j temperatures for the ulv intel ? celeron ? processor. the thermal solution should be designed to ensure the junction temperature never exceeds the specified value while operating at the thermal design power. additionally, a secondary fail-safe mechanism in hardware should be provided to shutdown the processor at 101 c to prevent permanent damage, as described in section 3.1.3 . tdp is a thermal design power specification based on the worst case power dissipation of the processor while executing publicly available software under normal operating conditions at nominal voltages. contact your intel field sales representative for further information. table 41. power specifications for the ultra-low voltage intel ? celeron ? processor symbol core frequency/voltage thermal design power (typ) thermal design power (max) unit notes tdp 650 mhz and 1.10 v 400 mhz and 0.95 v 7.00 3.40 8.30 4.23 w at 100 c, 1 , 4 symbol parameter min max unit notes p ah auto halt power at 1.10 v 0.95 v 1.9 1.0 wat 50 c, 2 p qs quick start power at 1.10 v 0.95 v 1.7 0.9 wat 50 c, 2 p dslp deep sleep power at 1.10 v 0.95 v 1.6 0.7 wat 35 c, 2 t j junction temperature 0 100 c 3 notes: 1. tdp (typ) is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications. the tdp number shown is a specification based on icc (maximum) and indirectly tested by icc (maximum) testing. the intel tdp specification is a recommended design point and is not representative of the absolute maximum power the processor may dissipate under worst case conditions. 2. not 100% tested. these power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. t j is measured with the on-die thermal diode. 4. tdp (max) is defined as the worst case power dissipated by the processor while executing a worst case instruction mix, operating at typical vcc and under normal operating conditions. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 66 datasheet 6.1 thermal diode the ulv intel ? celeron ? processor has an on-die thermal diode that should be used to monitor the die temperature (t j ). a thermal sensor located on the motherboard, or a stand-alone measurement kit, should monitor the die temperature of the processor for thermal management or instrumentation purposes. tables 42 and 43 provide the diode interface and specifications. note: the reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die. this is due to inaccuracies in the thermal sensor, on- die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. time based variations may occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the t j temperature may change. table 42. thermal diode interface signal name pin/ball number signal description thermda af13 thermal diode anode thermdc af14 thermal diode cathode table 43. thermal diode specifications symbol parameter min typ max unit notes n diode ideality factor (5-150 a) 1.0011 1.0067 1.0122 1 , 2 , 3 , 4 , 6 n diode ideality factor (5-300 a) 1.0003 1.0091 1.0178 1 , 2 , 3 , 5 , 6 notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. characterized at 100 c. 3. not 100% tested. specified by design/characterization. 4. specified for forward bias current = 5 a (min) and 150 a (max). 5. specified for forward bias current = 5 a (min) and 300 a (max). 6. the ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). i fw i s e qv d 1 ? () ? = www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 67 7.0 processor initialization and configuration 7.1 description the ulv intel ? celeron ? processor has some configuration options that are determined by hardware and some that are determined by software. the processor samples its hardware configuration at reset on the active-to-inactive transition of reset#. the p6 family of processors developer?s manual describes these configuration options. some of the configuration options for the ulv intel celeron processor are described in the remainder of this section. 7.1.1 quick start enable quick start enabling is mandatory on the ulv intel celeron processor by strapping a15# low. when the stpclk# signal is asserted it will enter the quick start state when a15# is sampled active on the reset# signal?s active-to-inactive transition. the quick start state supports snoops from the bus priority device but it does not support symmetric master snoops nor is the latching of interrupts supported. a ?1? in bit position 5 of the power-on configuration register indicates that the quick start state has been enabled. 7.1.2 system bus frequency the current generation ulv intel celeron processor will only function with a system bus frequency of 100 mhz. 7.1.3 apic enable the processor apic must be hardware enabled by pulling the picd[1:0] signals separately up to 1.5 v and supplying an active picclk to the processo r. software may be used to disable the apic if it is not being used, after picd[1:0] are sampled high when reset# is deasserted and the processor has started executing instructions. 7.2 clock frequencies and ratios the ulv intel celeron processor uses a clock design in which the bus clock is multiplied by a ratio to produce the processor?s internal (or core) clock. the ratio used is programmed into the processor during manufacturing. the bus ratio programmed into the processor is visible in bit positions 22 to 25 and 27 of the power-on configuration register. table 23 shows the 5-bit codes in the power-on configuration register and their corresponding bus ratios. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
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ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 69 8.0 processor interface 8.1 alphabetical signal reference 8.1.1 a[35:3]# (i/o ? agtl) the a[35:3]# (address) signals define a 2 36 -byte physical memory address space. when ads# is active, these signals transmit the address of a transaction; when ads# is inactive, these signals transmit transaction information. these signals must be connected to the appropriate pins/balls of both agents on the system bus. the a[35:24]# signals are protected with the ap1# parity signal, and the a[23:3]# signals are protected with the ap0# parity signal. on the active-to-inactive transition of reset#, each processor bus agent samples a[35:3]# signals to determine its power-on configuration. see p6 family of processors developer?s manual for details. 8.1.2 a20m# (i - 1.5v tolerant) if the a20m# (address-20 mask) input signal is asse rted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 pr ocessor's address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. 8.1.3 ads# (i/o - agtl) the ads# (address strobe) signal is asserted to indicate the validity of a transaction address on the a[35:3]# signals. both bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop or deferred reply id match operations associated with the new transaction. this signal must be connected to the appropriate pins/balls on both agents on the system bus. 8.1.4 aerr# (i/o - agtl) the aerr# (address parity error) signal is observed and driven by both system bus agents, and if used, must be connected to the appropriate pins/balls of both agents on the system bus. aerr# observation is optionally enabled during power-on configuration; if enabled, a valid assertion of aerr# aborts the current transaction. if aerr# observation is disabled during power-on configuration, a central agent may handle an assertion of aerr# as appropriate to the error handling architecture of the system. 8.1.5 ap[1:0]# (i/o - agtl) the ap[1:0]# (address parity) signals are driven by the request initiator along with ads#, a[35:3]#, req[4:0]# and rp#. ap1# covers a[35:24]#. ap0# covers a[23:3]#. a correct parity signal is high if an even number of covered signals is low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should be connected to the appropriate pins/balls on both agents on the system bus. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 70 datasheet 8.1.6 bclk, bclk# (i) the bclk and bclk# signals determines the system bus frequency. on systems with differential clocking, both system bus agents must receive these signals to drive their outputs and latch their inputs on the bclk rising edge and bclk# falling edge. all external timing parameters are specified with respect to the crossing point of the bclk rising edge and bclk# falling edge. on systems with single ended clocking, both system bus agents must receive the bclk signal to drive their outputs and latch their inputs on the bclk rising edge. all external timing parameters are specified with respect to the bclk signal. the bclk# signal functions as the clkref input. 8.1.7 berr# (i/o - agtl) the berr# (bus error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by either system bus agent and must be connected to the appropriate pins/balls of both agents, if used. however, the ulv intel ? celeron ? processors do not observe assertions of the berr# signal. berr# assertion conditions are defined by the system configuration. configuration options enable the berr# driver as follows: enabled or disabled asserted optionally for internal errors along with ierr# asserted optionally by the request initiator of a bus transaction after it observes an error asserted by any bus agent when it observes an error in a bus transaction 8.1.8 binit# (i/o - agtl) the binit# (bus initialization) signal may be observed and driven by both system bus agents and must be connected to the appropriate pins/balls of both agents, if used. if the binit# driver is enabled during the power-on configuration, binit# is asserted to signal any bus condition that prevents reliable future information. if binit# is enabled during power-on configuration, and binit# is sampled asserted, all bus state machines are reset and any data which was in transit is lost. all agents reset their rotating id for bus arbitration to the state after reset, and internal count information is lost. the l1 and l2 caches are not affected. if binit# is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the machine check architecture (mca) of the system. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 71 8.1.9 bnr# (i/o - agtl) the bnr# (block next request) signal is used to assert a bus stall by any bus agent that is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents may need to request a bus stall simultaneously, bnr# is a wired-or signal that must be connected to the appropriate pins/balls of both agents on the system bus. in order to avoid wire-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is activated on specific clock edges and sampled on specific clock edges. 8.1.10 bp[3:2]# (i/o - agtl) the bp[3:2]# (breakpoint) signals are the system support group breakpoint signals. they are outputs from the processor that indicate the status of breakpoints. 8.1.11 bpm[1:0]# (i/o - agtl) the bpm[1:0]# (breakpoint monitor) signals are breakpoint and performance monitor signals. they are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. 8.1.12 bpri# (i - agtl) the bpri# (bus priority request) signal is used to arbitrate for ownership of the system bus. it must be connected to the appropriate pins/balls on both agents on the system bus. observing bpri# active (as asserted by the priority agent) causes the processor to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed and then releases the bus by deasserting bpri#. 8.1.13 breq0# (i/o - agtl) the breq0# (bus request) signal is a processor arbitration bus signal. the processor indicates that it wants ownership of the system bus by asserting the breq0# signal. during power-up configuration, the central agent must assert the breq0# bus signal. the processor samples breq0# on the active-to-inactive transition of reset#. optionally, this signal may be grounded with a 10- ? resistor. 8.1.14 bsel[1:0] (o ? 3.3v tolerant) the bsel[1:0] (select processor system bus speed) signal is used to configure the processor for the system bus frequency. the chipset and system clock generator also uses the bsel signals. the vttpwrgd signal informs the processor to output the bsel signals. during power up the bsel signals will be indeterminate for a small period of time. the chipset and clock generator should not sample the bsel signals until the vttpwrgd signal is asserted. the assertion of the vttpwrgd signal indicates that the bsel signals are stable and driven to a final state by the processor. refer to figure 12 for the timing relationship between the bsel and vttpwrgd signals. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 72 datasheet table 44 shows the encoding scheme for bsel[1:0]. the only supported system bus frequency for the ulv intel ? celeron ? processor is 100 mhz. if another frequency is used, then the processor is not ensured to function properly. 8.1.15 clkref (analog) the clkref (system bus clock reference) signal provides a reference voltage to define the trip point for the bclk signal on platforms supporting single ended clocking. this signal should be connected to a resistor divider to generate 1.25 v from the 2.5-v supply. a minimum of 1-f decoupling capacitance is recommended on clkref. on systems with differential clocking, the clkref pin functions as the bclk# input. 8.1.16 cmosref (analog) the cmosref (cmos reference voltage) signal provides a dc level reference voltage for the cmos input buffers. cmosref must be generated from a stable 1.5v supply (815 chipset family), 2.5 v (440mx chipset family) and must meet the vcmosref specification. the same 1.5 v (815 chipset family) or 2.5 v (440mx chipset family) supply should be used to power the chipset cmos i/o buffers that drive the cmos signals. the thevenin equivalent impedance of the vcmosref generation circuits must be less than 0.5 k ? /1 k ? (i.e., top resistor 500 ? , bottom resistor 1 k ? ) for the intel 815 chipset family. the thevenin equivalent impedance of the vcmosref generation circuits must be less than 0.75 k ? /0.5 k ? (i.e., top resistor 750 ? , bottom resistor 500 ? ) for the intel 440mx chipset family. 8.1.17 d[63:0]# (i/o - agtl) the d[63:0]# (data) signals are the data signals. these signals provide a 64-bit data path between both system bus agents, and must be connected to the appropriate pins/balls on both agents. the data driver asserts drdy# to indicate a valid data transfer. 8.1.18 dbsy# (i/o - agtl) the dbsy# (data bus busy) signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must be connected to the appropriate pins/balls on both agents on the system bus. 8.1.19 defer# (i - agtl) the defer# (defer) signal is asserted by an agent to indicate that the transaction cannot be ensured in-order completion. assertion of defer# is normally the responsibility of the addressed memory agent or i/o agent. this signal must be connected to the appropriate pins/balls on both agents on the system bus. table 44. bsel[1:0] encoding bsel[1:0] system bus frequency 01 100 mhz www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 73 8.1.20 dep[7:0]# (i/o - agtl) the dep[7:0]# (data bus ecc protection) signals provide optional ecc protection for the data bus. they are driven by the agent responsible for driving d[63:0]#, and must be connected to the appropriate pins/balls on both agents on the system bus if they are used. during power-on configuration, dep[7:0]# signals may be enabled for ecc checking or disabled for no checking. 8.1.21 drdy# (i/o - agtl) the drdy# (data ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-cycle data transfer, drdy# may be deasserted to insert idle clocks. this signal must be connected to the appropriate pins/balls on both agents on the system bus. 8.1.22 dpslp# (i - 1.5 v tolerant) the dpslp# (deep sleep) signal, when asserted in the quick start state, causes the processor to enter the deep sleep state. in order to return to the quick start state bclk, bclk# must be running and the dpslp# pin must be deasserted. 8.1.23 edgctrlp (i-analog) the edgctrlp (edge rate control) signal is used to configure the edge rate of the agtl output buffers. connect the signal to v ss with a 110- ? , 1% resistor. 8.1.24 ferr# (o - 1.5 v tolerant open-drain) the ferr# (floating-point error) signal is asserted when the processor detects an unmasked floating-point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and it is included for compatibility with systems using dos-type floating-point error reporting. 8.1.25 flush# (i - 1.5 v tolerant) when the flush# (flush) input signal is asserted, the processor writes back all internal cache lines in the modified state and invalidates all internal cache lines. at the completion of a flush operation, the processor issues a flush acknowledge transaction. the processor stops caching any new data while the flush# signal remains asserted. on the active-to-inactive transition of reset#, each processor bus agent samples flush# to determine its power-on configuration. 8.1.26 hit# (i/o - agtl), hitm# (i/o - agtl) the hit# (snoop hit) and hitm# (hit modified) signals convey transaction snoop operation results, and must be connected to the appropriate pins/balls on both agents on the system bus. either bus agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which may be continued by reasserting hit# and hitm# together. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 74 datasheet 8.1.27 ierr# (o - 1.5 v tolerant open-drain) the ierr# (internal error) signal is asserted by the processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system logic. the processor will keep ierr# asserted until it is handled in software or with the assertion of reset#, binit, or init#. 8.1.28 ignne# (i - 1.5 v tolerant) the ignne# (ignore numeric error) signal is asserted to force the processor to ignore a numeric error and continue to execute non-control floating- point instructions. if ignne# is deasserted, the processor freezes on a non-control floating-point instruction if a previous instruction caused an error. ignne# has no affect when the ne bit in control register 0 (cr0) is set. 8.1.29 init# (i - 1.5 v tolerant) the init# (initialization) signal is asserted to reset integer registers inside the processor without affecting the internal (l1 or l2) caches or the floating-point registers. the processor begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous input. if init# is sampled active on reset#'s active-to-inactive transition, then the processor executes its built-in self-test (bist). 8.1.30 intr (i - 1.5 v tolerant) the intr (interrupt) signal indicates that an external interrupt has been generated. intr becomes the lint0 signal when the apic is enabled. the interrupt is maskable using the if bit in the eflags register. if the if bit is set, the processor vectors to the interrupt handler after completing the current instruction execution. upon recognizing the interrupt request, the processor issues a single interrupt acknowledge (inta) bus transacti on. intr must remain active until the inta bus transaction to ensure its recognition. 8.1.31 lint[1:0] (i - 1.5 v tolerant) the lint[1:0] (local apic interrupt) signals must be connected to the appropriate pins/balls of all apic bus agents, including the processor and the system logic or i/o apic component. when apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a non-maskable interrupt. intr and nmi are backward compatible with the same signals for the pentium processor. both signals are asynchronous inputs. both of these signals must be software configured by programming the apic register space to be used either as nmi/intr or lint[1:0] in the bios. if the apic is enabled at reset, then lint[1:0] is the default configuration. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 75 8.1.32 lock# (i/o - agtl) the lock# (lock) signal indicates to the system that a sequence of transactions must occur atomically. this signal must be connected to the appropriate pins/balls on both agents on the system bus. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction through the end of the last transaction. when the priority agent asserts bpri# to arbitrate for bus ownership, it waits until it observes lock# deasserted. this enables the processor to retain bus ownership throughout the bus locked operation and ensure the atomicity of lock. 8.1.33 nctrl (i - analog) the nctrl signal provides the agtl pull down impedance control. the processor samples this input to determine the n-channel pull-down device strength when it is the driving agent. an external 14 ? (1% tolerance) pull-up resistor to v cct is required for this signal. refer to platform design guide for implementation details. 8.1.34 nmi (i - 1.5 v tolerant) the nmi (non-maskable interrupt) indicates that an external interrupt has been generated. nmi becomes the lint1 signal when the apic is disabled. asserting nmi causes an interrupt with an internally supplied vector value of two. an external interrupt-acknowledge transaction is not generated. if nmi is asserted during the execution of an nmi service routine, it remains pending and is recognized after the iret is executed by the nmi service routine. at most, one assertion of nmi is held pending. nmi is rising edge sensitive. 8.1.35 picclk (i ? 2.0 v tolerant) the picclk (apic clock) signal is an input clock to the processor and system logic or i/o apic that is required for operation of the processor, system logic, and i/o apic components on the apic bus. 8.1.36 picd[1:0] (i/o - 1.5 v tolerant open-drain) the picd[1:0] (apic data) signals are used for bi-directional serial message passing on the apic bus. they must be connected to the appropriate pins/balls of all apic bus agents, including the processor and the system logic or i/o apic components. if the picd0 signal is sampled low on the active-to-inactive transition of the reset# signal, then the apic is hardware disabled. for the ulv intel ? celeron ? processor, the apic is required to be hardware enabled as described in section 7.1.3 . 8.1.37 pll1, pll2 (analog) the pll1 and pll2 signals provide isolated analog decoupling is required for the internal pll. see section 3.2.2 for a description of the analog decoupling circuit. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 76 datasheet 8.1.38 prdy# (o - agtl) the prdy# (probe ready) signal is a processor output used by debug tools to determine processor debug readiness. 8.1.39 preq# (i - 1.5 v tolerant) the preq# (probe request) signal is used by debug tools to request debug operation of the processor. 8.1.40 pwrgood (i ? 1.8 v tolerant) pwrgood (power good) is a 1.8-v tolerant input. the processor requires this signal to be a clean indication that clocks and the power supplies (v cc , v cct , etc.) are stable and within their specifications. clean implies that the signal will re main low, (capable of sinking leakage current) and without glitches, from the time that the power supplies are turned on, until they come within specification. the signal will then transiti on monotonically to a high (1.8 v) state. figure 12 through figure 14 illustrate the relationship of pwrgood to other system signals. pwrgood may be driven inactive at any time, but clocks and power must again be stable before the rising edge of pwrgood. it must also meet the minimum pulse width specified in table 25 ( section 3.6 ) and be followed by a 1 ms reset# pulse. the pwrgood signal, which must be supplied to the processor, is used to protect internal circuits against voltage sequencing issues. the pwr good signal should be driven high throughout boundary scan operation. 8.1.41 req[4:0]# (i/o - agtl) the req[4:0]# (request command) signals must be connected to the appropriate pins/balls on both agents on the system bus. they are asserted by the current bus owner when it drives a[35:3]# to define the currently active transaction type. 8.1.42 reset# (i - agtl) asserting the reset# signal resets the processor to a known state and invalidates the l1 and l2 caches without writing back modified (m state) lines. for a power-on type reset, reset# must stay active for at least 1 ms after v cc and bclk, bclk# have reached their proper dc and ac specifications and after pwrgood has been asserted. when observing active reset#, all bus agents will deassert their outputs within two clocks. reset# is the only agtl signal that does not have on-die agtl termination. a 56.2 ? 1% terminating resistor connected to v cct is required. a number of bus signals are sampled at the active-to-inactive transition of reset# for the power- on configuration. the configuration options are described in section 4.0 and in the p6 family of processors developer?s manual . unless its outputs are tri-stated during power-on conf iguration, after an active-to-inactive transition of reset#, the processor optionally executes its built-in self-test (bist) and begins program execution at reset-vector 000ffff0h or fffffff0h. reset# must be connected to the appropriate pins/balls on both agents on the system bus. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 77 8.1.43 rp# (i/o - agtl) the rp# (request parity) signal is driven by the request initiator and provides parity protection on ads# and req[4:0]#. rp# should be connected to the appropriate pins/balls on both agents on the system bus. a correct parity signal is high if an even number of covered signals is low and low if an odd number of covered signals are low. this definition allows parity to be high when all covered signals are high. 8.1.44 rs[2:0]# (i/o - agtl) the rs[2:0]# (response status) signals are driven by the response agent (the agent responsible for completion of the current transaction) and must be connected to the appropriate pins/balls on both agents on the system bus. 8.1.45 rsp# (i - agtl) the rsp# (response parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#. rsp# provides parity protection for rs[2:0]#. rsp# should be connected to the appropriate pins/balls on both agents on the system bus. a correct parity signal is high if an even number of covered signals are low, and it is low if an odd number of covered signals are low. during idle state of rs[2:0]# (rs[2:0]#=000), rsp# is also high since it is not driven by any agent ensuring correct parity. 8.1.46 rttimpedp (i-analog) the rttimpedp (r tt impedance/pmos) signal is used to configure the on-die agtl termination. connect the rttimpedp signal to v ss with a 56.2- ? , 1% resistor. 8.1.47 smi# (i - 1.5 v tolerant) the smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current state and enters system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. 8.1.48 stpclk# (i - 1.5 v tolerant) the stpclk# (stop clock) signal, when asserted, causes the processor to enter a low-power quick start state. the processor issues a stop grant acknowledge special transaction and stops providing internal clock signals to all units except the bus and apic units. the processor continues to snoop bus transactions and service interrupts while in the quick start state. when stpclk# is deasserted and other conditions in are met, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no affect on the bus clock. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 78 datasheet 8.1.49 tck (i - 1.5 v tolerant) the tck (test clock) signal provides the clock input for the test bus (also known as the test access port). 8.1.50 tdi (i - 1.5 v tolerant) the tdi (test data in) signal transfers serial test data to the processor. tdi provides the serial input needed for jtag support. 8.1.51 tdo (o - 1.5 v tolerant open-drain) the tdo (test data out) signal transfers serial test data from the processor. tdo provides the serial output needed for jtag support. 8.1.52 testhi[2:1] (i - 1.25 v tolerant) the testhi[2:1] (test input high) signals are used during processor test and need to be pulled high during normal operation. 8.1.53 testlo[2:1] (i - 1.5 v tolerant) the testlo[2:1] (test input low) signals are used during processor test and needs to be pulled to ground during normal operation. 8.1.54 thermda, thermdc (analog) the thermda (thermal diode anode) and thermdc (thermal diode cathode) signals connect to the anode and cathode of the on-die thermal diode. 8.1.55 tms (i - 1.5 v tolerant) the tms (test mode select) signal is a jtag support signal used by debug tools. 8.1.56 trdy# (i/o - agtl) the trdy# (target ready) signal is asserted by the target to indicate that the target is ready to receive write or implicit write-back data transfer. trdy# must be connected to the appropriate pins/balls on both agents on the system bus. 8.1.57 trst# (i - 1.5 v tolerant) the trst# (test reset) signal resets the test access port (tap) logic. the ulv intel celeron processors do not self-reset during power on; therefore, it is necessary to drive this signal low during power-on reset. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 79 8.1.58 vid[4:0] (o ? open-drain) the vid[4:0] (voltage id) pins/balls may be used to support automatic selection of power supply voltages. refer to section 3.2.4 for details. 8.1.59 v ref (analog) the v ref (agtl reference voltage) signal provides a dc level reference voltage for the agtl input buffers. a voltage divider should be used to divide v cct by 2 / 3 . resistor values of 1.00 k ? and 2.00 k ? are recommended. decouple the v ref signal with three 0.1-f high-frequency capacitors close to the processor. 8.1.60 vttpwrgd (i ? 1.25 v) the vttpwrgd signal informs the processor to output the vid signals. during power up, the vid signals will be in an indeterminate state for a small period of time. the voltage regulator should not sample and/or latch the vid signals until the vttpwrgd signal is asserted. the assertion of the vttpwrgd signal indicates that the vid signals are stable and are driven to the final state by the processor. refer to figure 12 for the power up sequence. (also see section 4.3.1 .) 8.2 signal summaries table 45. input signals (sheet 1 of 2) name active level clock signal group qualified a20m# low asynch cmos always bclk high ? system bus always bclk# low ? system bus always bpri# low bclk system bus always defer# low bclk system bus always flush# low asynch cmos always ignne# low asynch cmos always init# low asynch system bus always intr high asynch cmos apic disabled mode lint[1:0] high asynch apic apic enabled mode nmi high asynch cmos apic disabled mode nctrl high asynch picclk high ? apic always preq# low asynch implementation always pwrgood high asynch implementation always reset# low bclk system bus always rsp# low bclk system bus always smi# low asynch cmos always www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz 80 datasheet stpclk# low asynch implementation always tck high ? jtag tdi tck jtag tms tck jtag trst# low asynch jtag vttpwrgd high asynch power/other table 46. output signals name active level clock signal group bsel[1:0] high asynch open-drain ferr# low asynch open-drain ierr# low asynch open-drain prdy# low bclk implementation tdo high tck jtag vid[4:0] high asynch power/other table 47. input/output signals (single driver) name active level clock signal group qualified a[35:3]# low bclk system bus ads#, ads#+1 ads# low bclk system bus always ap[1:0]# low bclk system bus ads#, ads#+1 breq0# low bclk system bus always bp[3:2]# low bclk system bus always bpm[1:0]# low bclk system bus always d[63:0]# low bclk system bus drdy# dbsy# low bclk system bus always dep[7:0]# low bclk system bus drdy# drdy# low bclk system bus always lock# low bclk system bus always req[4:0]# low bclk system bus ads#, ads#+1 rp# low bclk system bus ads#, ads#+1 rs[2:0]# low bclk system bus always trdy# low bclk system bus response phase table 45. input signals (sheet 2 of 2) name active level clock signal group qualified www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ultra-low voltage intel ? celeron ? processor ? 650 mhz and 400 mhz datasheet 81 table 48. input/output signals (multiple driver) name active level clock signal group qualified aerr# low bclk system bus ads#+3 berr# low bclk system bus always binit# low bclk system bus always bnr# low bclk system bus always hit# low bclk system bus always hitm# low bclk system bus always picd[1:0] high picclk apic always www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
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