View PCK9448_1896706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the PCK9448 is a 3.3 v or 2.5 v compatible, 1 : 12 clock fan-out buffer targeted for high performance clock tree applications. with output frequencies up to 350 mhz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. the PCK9448 is speci?cally designed to distribute lvcmos compatible clock signals up to a frequency of 350 mhz. each output provides a precise copy of the input signal with near zero skew. the output buffers support driving of 50 w terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. two selectable independent clock inputs are available, providing support of lvcmos and differential lvpecl clock distribution systems. the PCK9448 clk_st op control is synchronous to the falling edge of the input clock. it allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. applying the oe control will force the outputs into high-impedance mode. all inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from ?oating. the device supports a 2.5 v or 3.3 v power supply and an ambient temperature range of - 40 cto+85 c. 2. features n 12 lvcmos compatible clock outputs n selectable lvcmos and differential lvpecl compatible clock inputs n maximum clock frequency of 350 mhz n maximum clock skew of 150 ps n synchronous output stop in logic low state eliminates output runt pulses n high-impedance output control n 3.3 v or 2.5 v power supply n drives up to 24 series terminated clock lines n t amb = - 40 cto+85 c n available in lqfp32 package n supports clock distribution in networking, telecommunications, and computer applications PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer rev. 01 29 november 2005 product data sheet
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 2 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 3. ordering information 4. functional diagram table 1: ordering information type number package name description version PCK9448bd lqfp32 plastic low pro?le quad ?at package; 32 leads; body 7 7 1.4 mm sot358-1 fig 1. functional diagram of PCK9448 002aaa720 q1 pclk cclk oe 0 1 PCK9448 q2 25 k w q3 q4 q5 q6 q7 q8 clk_stop clk_sel v cc 25 k w sync clk stop v cc 25 k w v cc 25 k w v cc 25 k w q0 q9 q10 q11 pclk
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 3 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 5. pinning information 5.1 pinning 5.2 pin description fig 2. pin con?guration for lqfp32 PCK9448bd clk_sel gnd cclk q4 pclk v cc pclk q5 clk_stop gnd oe q6 v cc v cc gnd q7 q11 gnd v cc q0 q10 v cc gnd q1 q9 gnd v cc q2 q8 gnd q3 002aaa721 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 v cc table 2: pin description symbol pin type description clk_sel 1 i clock input select cclk 2 i alternative clock signal input pclk 3 i clock signal input pclk 4 i clock signal input, active low clk_st op 5 i clock output enable/disable, active low oe 6 i output enable/disable (high-impedance, 3-state) q0 to q11 31, 29, 27, 25, 23, 21, 19, 17, 15, 13, 11, 9 o clock outputs gnd 8, 12, 16, 20, 24, 28, 32 ground negative power supply (gnd) v cc 7, 10, 14, 18, 22, 26, 30 power positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation.
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 4 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 6. functional description refer to figure 1 functional diag r am of PCK9448 . 6.1 function table [1] oe = 0 will high-impedance 3-state all outputs independent of clk_st op. 7. limiting values 8. characteristics 8.1 general characteristics [1] 200 pf capacitor discharged via a 10 w resistor and a 0.75 m h inductor. [2] 100 pf capacitor discharged via a 1.5 k w resistor. table 3: function table control default logic 0 logic 1 clk_sel 1 pecl differential input selected cclk input selected oe 1 outputs disabled (high-impedance state) [1] outputs enabled clk_st op 1 outputs synchronously stopped in logic low state outputs active table 4: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.3 +3.9 v v i input voltage - 0.3 v cc + 0.3 v v o output voltage - 0.3 v cc + 0.3 v i i input current - 20 ma i o output current - 50 ma t stg storage temperature - 65 +125 c table 5: general characteristics symbol parameter conditions min typ max unit v t termination voltage (output) - 0.5v cc -v v esd electrostatic discharge voltage machine model [1] 200 - - v human body model [2] 2000 - - v i latch(prot) latch-up protection current 200 - - ma c pd power dissipation capacitance per output - 10 - pf c i input capacitance inputs - 4.0 - pf
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 5 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 8.2 static characteristics [1] v icr (dc) is the cross point of the differential input signal. functional operation is obtained when the cross point is within the v icr range and the input swing lies within the v i(p-p) (dc) speci?cation. [2] the PCK9448 is capable of driving 50 w transmission lines on the incident edge. each output drives one 50 w parallel terminated transmission line to a termination voltage of v t . alternatively, the device drives up to two 50 w series terminated transmission lines (v cc = 3.3 v) or one 50 w series terminated transmission line (for v cc = 2.5 v). [3] inputs have pull-down or pull-up resistors affecting the input current. [4] i q(max) is the dc current consumption of the device with all outputs open and the input in its default state or open. [1] v icr (dc) is the cross point of the differential input signal. functional operation is obtained when the cross point is within the v icr range and the input swing lies within the v i(p-p) (dc) speci?cation. [2] the PCK9448 is capable of driving 50 w transmission lines on the incident edge. each output drives one 50 w parallel terminated transmission line to a termination voltage of v t . alternatively, the device drives one 50 w series terminated transmission line per output at v cc = 2.5 v. [3] inputs have pull-down or pull-up resistors affecting the input current. [4] i q(max) is the dc current consumption of the device with all outputs open and the input in its default state or open. table 6: static characteristics (3.3 v) t amb = - 40 c to +85 c; v cc = 3.3 v 5 %; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ih high-state input voltage lvcmos 2.0 - v cc + 0.3 v v il low-state input voltage lvcmos - 0.3 - +0.8 v v oh high-state output voltage i oh = - 24 ma [2] 2.4 - - v v ol low-state output voltage i ol =24ma [2] - - 0.55 v i ol = 12 ma - - 0.30 v v i(p-p) peak-to-peak input voltage (pclk) lvpecl 250 - - mv v icr [1] common-mode input voltage range (pclk) lvpecl 1.1 - v cc - 0.6 v z o output impedance - 17 - w i i input current v i =v cc or gnd [3] - - 300 m a i q(max) maximum quiescent current all v cc pins [4] - - 2.0 ma table 7: static characteristics (2.5 v) t amb = - 40 c to +85 c; v cc = 2.5 v 5 %; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ih high-state input voltage lvcmos 1.7 - v cc + 0.3 v v il low-state input voltage lvcmos - 0.3 - +0.7 v v oh high-state output voltage i oh = - 15 ma [2] 1.8 - - v v ol low-state output voltage i ol = 15 ma - - 0.6 v v i(p-p) peak-to-peak input voltage (pclk) lvpecl 250 - - mv v icr [1] common-mode input voltage range (pclk) lvpecl 1.0 - v cc - 0.7 v z o output impedance - 19 - w i i input current v i =v cc or gnd [3] - - 300 m a i q(max) maximum quiescent current all v cc pins [4] - - 2.0 ma
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 6 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 8.3 dynamic characteristics [1] dynamic characteristics apply for parallel output termination of 50 w to v t . [2] v icr (ac) is the cross-point of the differential input signal. normal ac operation is obtained when the cross-point is within the v icr range and the input swing lies within the v i(p-p) (ac) speci?cation. violation of v icr or v i(p-p) impacts static phase offset. [3] setup and hold times are referenced to the falling edge of the selected clock signal input. [4] violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device ske w, reference input pulse width, output duty cycle, and maximum frequency speci?cations. table 8: dynamic characteristics (3.3 v) t amb = - 40 c to +85 c; v cc = 3.3 v 5 %; unless otherwise speci?ed. [1] symbol parameter conditions min typ max unit v i(p-p) input voltage (peak-to-peak value) (pclk, pclk) lvpecl 400 - 1000 mv v icr [2] common-mode input voltage range (pclk, pclk) lvpecl 1.3 - v cc - 0.8 v f o output frequency 0 - 350 mhz f i input frequency 0 - 350 mhz t sk(o) output skew time - - 150 ps t sk(pr) process skew time part-to-part - - 2.0 ns d o output duty cycle f o < 170 mhz; d ref = 50 % 45 50 55 % t plh low-to-high propagation delay pclk to any q 1.6 - 3.6 ns cclk to any q 1.3 - 3.3 ns t phl high-to-low propagation delay pclk to any q 1.6 - 3.6 ns cclk to any q 1.3 - 3.3 ns t plz low to off-state propagation delay oe to any q - - 11 ns t phz high to off-state propagation delay oe to any q - - 11 ns t pzl off-state to low propagation delay oe to any q - - 11 ns t pzh off-state to high propagation delay oe to any q - - 11 ns t su setup time cclk to clk_st op [3] 0.0 - - ns pclk to clk_st op [3] 0.0 - - ns t h hold time cclk to clk_st op [3] 1.0 - - ns pclk to clk_st op [3] 1.5 - - ns t r rise time output; 0.55 v to 2.4 v 0.1 - 1.0 ns cclk input; 0.8 v to 2.0 v - - 1.0 [4] ns t f fall time output; 2.4 v to 0.55 v 0.1 - 1.0 ns cclk input; 2.0 v to 0.8 v - - 1.0 [4] ns
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 7 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer [1] dynamic characteristics apply for parallel output termination of 50 w to v t . [2] v icr (ac) is the cross-point of the differential input signal. normal ac operation is obtained when the cross-point is within the v icr range and the input swing lies within the v i(p-p) (ac) speci?cation. violation of v icr or v i(p-p) impacts static phase offset. [3] see section 9 application inf or mation for part-to-part skew calculation. [4] setup and hold times are referenced to the falling edge of the selected clock signal input. table 9: dynamic characteristics (2.5 v) t amb = - 40 c to +85 c; v cc = 2.5 v 5 %; unless otherwise speci?ed. [1] symbol parameter conditions min typ max unit v i(p-p) input voltage (peak-to-peak value) (pclk, pclk) lvpecl 400 - 1000 mv v icr [2] common-mode input voltage range (pclk, pclk) lvpecl 1.2 v cc - 0.8 v f i input frequency 0 - 350 mhz f o output frequency 0 - 350 mhz t sk(o) output skew time output-to-output [3] - - 150 ps t sk(pr) process skew time part-to-part; pclk or cclk to any q - - 2.7 ns d o output duty cycle d ref = 50 % 45 50 60 % t plh low-to-high propagation delay pclk to any q 1.5 - 4.2 ns cclk to any q 1.7 - 4.4 ns t phl high-to-low propagation delay pclk to any q 1.5 - 4.2 ns cclk to any q 1.7 - 4.4 ns t plz low to off-state propagation delay oe to any q - - 11 ns t phz high to off-state propagation delay oe to any q - - 11 ns t pzl off-state to low propagation delay oe to any q - - 11 ns t pzh off-state to high propagation delay oe to any q - - 11 ns t su setup time cclk to clk_st op [4] 0.0 - - ns pclk to clk_st op [4] 0.0 - - ns t h hold time cclk to clk_st op [4] 1.0 - - ns pclk to clk_st op [4] 1.5 - - ns t r rise time input cclk; 0.8 v to 2.0 v - - 1.0 ns output; 0.6 v to 1.8 v 0.1 - 1.0 ns t f fall time input cclk; 2.0 v to 0.8 v - - 1.0 ns output; 1.8 v to 0.6 v 0.1 - 1.0 ns
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 8 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer fig 3. output clock stop ( clk_st op) timing diagram cclk or pclk clk_stop q0 to q11 002aaa728 the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. fig 4. cycle-to-cycle jitter 002aab293 t n t n+1 t jit(cc) = | t n - t n+1 |
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 9 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer fig 5. propagation delay test reference (pclk/ pclk to qn) fig 6. propagation delay test reference (cclk to qn) fig 7. pulse skew time (t sk(p) ) test reference the pin-to-pin skew is de?ned as the worst-case difference in propagation delay between any similar delay path within a single device. the time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage. fig 8. output skew time (t sk(o) ) fig 9. output duty cycle ( d o ) (1) 2.4 v (v cc = 3.3 v) 1.8 v (v cc = 2.5 v) (2) 0.55 v (v cc = 3.3 v) 0.6 v (v cc = 2.5 v) fig 10. output transition time test reference fig 11. setup and hold time (t su , t h ) 002aaa729 t plh pclk qn v icr v cc 0.5v cc gnd pclk t phl 002aab829 t plh qn v cc 0.5v cc gnd cclk t phl v cc 0.5v cc gnd 002aab290 t plh cclk qn v cc 0.5v cc gnd v cc 0.5v cc gnd t phl t sk(p) = | t plh - t phl | 002aab289 t sk(o) v cc 0.5v cc gnd v cc 0.5v cc gnd t sk(o) 002aab291 t p v cc 0.5v cc gnd t o d o = (t p ? t o 100 %) t o 1 f o ----- = 002aab292 t f (1) (2) t r 002aaa727 t su cclk pclk clk_stop v cc 0.5v cc gnd v cc 0.5v cc gnd t h
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 10 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 9. application information 9.1 driving transmission lines the PCK9448 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum ?exibility to the user, the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of 17 w (v cc = 3.3 v), the outputs can drive either parallel or series terminated transmission lines. in most high performance clock networks, point-to-point distribution of signals is the method of choice. in a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 w resistance to 0.5v cc . this technique draws a fairly high level of dc current, and thus only a single terminated line can be driven by each output of the PCK9448 clock driver. for the series terminated case, however, there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 12 , illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme, the fan-out of the PCK9448 clock driver is effectively doubled due to its capability to drive multiple lines. fig 12. single versus dual transmission lines z o = 50 w 002aaa722 r s = 33 w z o = 50 w r s = 33 w PCK9448 output buffer outb1 outb0 17 w z o = 50 w r s = 33 w PCK9448 output buffer outa 17 w in in r o r o
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 11 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer the waveform plots of figure 13 show simulation results of an output driving a single line versus two lines. in both cases the drive capability of the PCK9448 output buffer is more than suf?cient to drive 50 w transmission lines on the incident edge. note from the delay measurement in the simulations a delta of only 43 ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCK9448. the output waveform in figure 13 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 33 w series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: at the load end the voltage will double, due to the near unity re?ection coef?cient, to 2.5 v. it will then increment towards the quiescent 3.0 v in steps separated by one round trip delay (in this case 4.0 ns). since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted re?ections on the line. to better match the impedances when driving multiple lines, the situation in figure 14 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. fig 13. single versus dual line termination waveforms v l v s z o r s r o z o ++ ------------------------------ ? ?? = z o 50 w 50 w r s 33 w 33 w r o 17 w = || = || = v l 3.0 25 16.5 17 25 ++ ---------------------------------- - ? ?? 1.28 v = = time (ns) 016 12 48 002aaa679 3.0 voltage (v) - 0.5 0 1.0 2.0 in outa t d = 3.8956 ns outb t d = 3.9386 ns
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 12 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 9.2 power consumption of the PCK9448 and thermal management the PCK9448 dynamic electrical (ac) speci?cation is guaranteed for the entire operating frequency range up to 350 mhz. the PCK9448 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating condition such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. this section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCK9448 die junction temperature and the associated device reliability. the long-term device reliability is a function of the die temperature; refer to t ab le 10 . increased power consumption will increase the die junction temperature and impact the device reliability (mtbf). according to the system-de?ned tolerable mtbf, the die junction temperature of the PCK9448 needs to be controlled and the thermal impedance of the board/package should be optimized. the power dissipated in the PCK9448 is represented in equation 1 . (1) where i q(max) is the static current consumption of the PCK9448, c pd is the power dissipation capacitance per output, (m) s c l represents the external capacitive output load, n is the number of active outputs (n is always 12 in the case of the PCK9448). the PCK9448 supports driving transmission lines to maintain high signal integrity and tight timing parameters. any transmission line will hide the limped capacitive load at the end of the board trace, therefore, s c l is zero for controlled transmission line systems and can be eliminated from equation 1 . using parallel termination output termination results in equation 2 for power dissipation. fig 14. optimized dual line termination z o = 50 w 002aaa723 r s = 16 w z o = 50 w r s = 16 w PCK9448 output buffer 17 w in z o = 50 w r o 17 w 16 w 16 w || + 50 w 50 w || = 25 w 25 w = table 10: die junction temperature and mtbf junction temperature ( c) mtbf (years) 100 20.4 110 9.1 120 4.2 130 2.0 p tot i q max () v cc f clk + nc pd c l m ? + ? ?? v c c =
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 13 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer (2) in equation 2 , p stands for the number of outputs with a parallel or thevenin termination; v ol , i ol , v oh and i oh are a function of the output termination technique; d o is the clock signal duty cycle. if transmission lines are used, s c l is zero in equation 2 and can be eliminated. in general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. equation 3 describes the die junction temperature t j as a function of the power consumption. (3) where r th(j-a) is the thermal impedance of the package (junction-to-ambient) and t amb is the ambient temperature. according to t ab le 10 , the junction temperature can be used to estimate the long-term device reliability. further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCK9448 in a series terminated transmission line system, equation 4 . (4) t j(max) should be selected according to the mtbf system requirements and t ab le 10 . r th(j-a) can be derived from t ab le 11 . the r th(j-a) represent data based on 1s2p boards; using 2s2p boards will result in a lower thermal impedance than indicated below. if the calculated maximum frequency is below 350 mhz, it becomes the upper clock speed limit for the given application conditions. the following four derating charts describe the safe frequency operation range for the PCK9448. the charts were calculated for a maximum tolerable die junction temperature of 110 c (120 c), corresponding to an estimated mtbf of 9.1 years (4 years), a supply voltage of 3.3 v and series terminated transmission line or capacitive loading. depending on a given set of these operating conditions and the available device convection, a decision on the maximum operating frequency can be made. table 11: thermal package impedance of the lqfp32 convection (lfpm) r th(j-a) ( c/w) (1p2s board) r th(j-a) ( c/w) (2p2s board) still air 88 61 100 76 56 200 71 54 300 68 53 400 66 52 500 60 49 p tot v cc i qmax () v cc f clk + nc pd c l m ? + ? ?? d o i oh v cc v oh C () 1dc q C () i ol v ol + [] p ? + = t j t amb p tot r th j - a () + = f clk max () 1 c pd n v cc 2 ---------------------------------------- - t jmax () t amb C r th j - a () ------------------------------------ i qmax () v cc () C =
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 14 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 10. test information fig 15. cclk ac test reference for v cc = 3.3 v and v cc = 2.5 v fig 16. pclk ac test reference z o = 50 w 002aaa724 r t = 50 w v t z o = 50 w r t = 50 w v t pulse generator z = 50 w PCK9448 d.u.t. z o = 50 w 002aaa725 r t = 50 w v t z o = 50 w r t = 50 w v t differential pulse generator z = 50 w PCK9448 d.u.t.
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 15 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 11. package outline fig 17. package outline sot358-1 (lqfp32) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.4 0.3 0.18 0.12 7.1 6.9 0.8 9.15 8.85 0.9 0.5 7 0 o o 0.25 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot358 -1 136e03 ms-026 03-02-25 05-11-09 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.9 0.5 d b p e q e a 1 a l p detail x l (a ) 3 b 8 c d h b p e h a 2 v m b d z d a z e e v m a x 1 32 25 24 17 16 9 y pin 1 index w m w m 0 2.5 5 mm scale lqfp32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm sot358-1
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 16 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 12. soldering 12.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 12.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 17 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 12.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 12.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 12: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 18 of 20 philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 13. abbreviations 14. revision history table 13: abbreviations acronym description esd electrostatic discharge hbm human body model mm machine model mtbf mean time between failures lfpm linear feet per minute lvpecl low voltage positive emitter coupled logic lvcmos low voltage complementary metal oxide silicon table 14: revision history document id release date data sheet status change notice doc. number supersedes PCK9448_1 20051129 product data sheet - 9397 750 12534 -
philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 9397 750 12534 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 19 of 20 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 29 november 2005 document number: 9397 750 12534 published in the netherlands philips semiconductors PCK9448 3.3 v/2.5 v lvcmos 1 : 12 clock fan-out buffer 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8.1 general characteristics . . . . . . . . . . . . . . . . . . . 4 8.2 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 8.3 dynamic characteristics . . . . . . . . . . . . . . . . . . 6 9 application information. . . . . . . . . . . . . . . . . . 10 9.1 driving transmission lines . . . . . . . . . . . . . . . . 10 9.2 power consumption of the PCK9448 and thermal management . . . . . . . . . . . . . . . . . . . 12 10 test information . . . . . . . . . . . . . . . . . . . . . . . . 14 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 12 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 12.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 17 12.5 package related soldering information . . . . . . 17 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 contact information . . . . . . . . . . . . . . . . . . . . 19

▲Up To Search▲

Price & Availability of PCK9448

	To Download PCK9448 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .