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intel ? pxa250 and PXA210 applications processors electrical, mechanical, and thermal specification datasheet product features high performance processor intel ? xscale ? microarchitecture 32kb instruction cache 32kb data cache 2kb mini data cache extensive data buffering intel ? media processing technology enhanced 16-bit multiply 40-bit accumulator flexible clocking cpu clock from 66 to 300mhz flexible memory clock ratios frequency change modes rich serial peripheral set ac97 audio port i2s audio port usb client controller high speed uart second uart with flow control fir and sir infrared comm ports low power less than 500mw typical internal dissipation supply voltage may be reduced to 0.85v low power/sleep modes high performance memory controller four banks of sdram - up to 100mhz five static chip selects support for pcmcia or compact flash companion chip interface additional peripherals for system connectivity multimedia card controller (mmc) ssp controller i2c controller two pulse width modulators (pwms) all peripheral pins double as gpios. hardware debug features hardware performance monitoring features order number: 278524-001 february, 2002
2 datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? pxa250 and PXA210 applications processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . copyright ? intel corporation, 2002 *other names and brands may be claimed as the property of others.
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 3 contents 1.0about this document .............................................................................................7 2.0functional overview ..............................................................................................7 3.0package information ..............................................................................................8 3.1package introduction.....................................................................................8 3.1.1functional signal definitions............................................................9 3.1.1.1pxa250 signal pin descriptions......................................9 3.1.1.2PXA210 signal pin descriptions....................................19 3.2package power ratings..............................................................................29 4.0electrical specifications ......................................................................................29 4.1absolute maximum ratings.........................................................................29 4.2operating conditions...................................................................................30 4.3targeted dc specifications.........................................................................31 4.4targeted ac specifications.........................................................................32 4.5oscillator electrical specifications...............................................................33 4.5.132.768khz oscillator specifications..............................................33 4.5.23.6864mhz oscillator specifications.............................................34 4.6reset and power ac timing specifications................................................35 4.6.1power on timing............................................................................35 4.6.2hardware reset timing..................................................................36 4.6.3watchdog reset timing.................................................................37 4.6.4gpio reset timing........................................................................37 4.6.5sleep mode timing........................................................................38 4.7memory bus and pcmcia ac specifications.............................................39 4.8peripheral module ac specifications..........................................................42 4.8.1lcd module ac timing..................................................................43 4.8.2ssp module ac timing..................................................................43 4.8.3boundary scan test signal timings..............................................44 4.9ac test conditions.....................................................................................45
pxa250 and PXA210 electrical, mechanical, and thermal specification 4 datasheet figures 1applications processor block diagram.................................................................8 2pxa250 applications processor.........................................................................16 3PXA210 applications processor.........................................................................26 4power-on reset timing......................................................................................36 5hardware reset timing......................................................................................37 6gpio reset timing.............................................................................................37 7sleep mode timing.............................................................................................38 8lcd ac timing definitions.................................................................................43 9ssp ac timing definitions.................................................................................44 10ac test load......................................................................................................45 tables 1related documentation.........................................................................................7 2pin and signal descriptions for the pxa250 applications processor...................9 3pxa250 256-lead 17x17mm mbga pinout ballpad number order..............17 4pin and signal descriptions for the PXA210 applications processor.................19 5PXA210 225-lead 13x13mm tpbga pinout ballpad number order............27 6 ja and maximum power ratings........................................................................29 7absolute maximum ratings................................................................................29 8voltage, temperature, and frequency electrical specifications.........................30 9standard input, output, and i/o pin dc operating conditions...........................31 10standard input, output, and i/o pin ac operating conditions...........................32 1132.768khz oscillator specifications...................................................................33 123.6864mhz oscillator specifications..................................................................34 13power-on timing specifications.........................................................................36 14hardware reset timing specifications...............................................................37 15gpio reset timing specifications......................................................................38 16sleep mode timing specifications......................................................................39 17sram / rom / flash / synchronous fast flash ac specifications....................39 18variable latency i/o interface ac specifications...............................................40 19card interface (pcmcia or compact flash) ac specifications.........................41 20synchronous memory interface ac specifications 1 ............................................42 21lcd ac timing specifications............................................................................43 22ssp ac timing specifications............................................................................44 23boundary scan test signal timing.....................................................................44
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 5 revision history daterevisiondescription 7/6/010.5first release 2/8/02-001first public release of the emts
pxa250 and PXA210 electrical, mechanical, and thermal specification 6 datasheet
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 7 1.0about this document this is the electrical, mechanical, and thermal specification datasheet for the intel ? pxa250 and PXA210 applications processors. this datasheet contains a functional overview, mechanical data, package signal locations, targeted electrical specifications (simulated), and bus functional waveforms. detailed functional descriptions other than parametric performance is published in the intel ? pxa250 and PXA210 applications processors developer's manual. refer to table1, related documentation for a list of documents that support the pxa250 and PXA210 applications processors. 2.0functional overview the pxa250 and PXA210 applications processors provide high integration, high performance and low power consumption for portable handheld and handset devices. these applications processors incorporate intel s xscale tm microarchitecture based on the arm* v5te architecture. refer to the intel ? xscale tm microarchitecture for the intel ? pxa250 and PXA210 applications processors developer's manual for implementation details, extensions, and options implemented by intel s xscale tm microarchitecture. the applications processor s memory interface supports a variety of memory types that allow flexibility in design requirements. hooks for connection to two companion chips permit glueless connection to external devices. an integrated lcd display controller provides support for displays, and permits 1, 2 and 4 bit grayscale and 8 or 16 bit color pixels. a 256-byte palette ram provides flexibility in color mapping. a rich set of serial devices as well as general system resources provide enough compute and connectivity capability for many applications. for details on the programming model and theory of operation of each of these units, refer to the intel ? pxa250 and PXA210 applications processors developer's manual. for the applications processor s block diagram refer to figure 1, applications processor block diagram on page8 . table 1. related documentation document title order / contact intel ? pxa250 and PXA210 applications processors developer's manual intel order # 278522 intel ? xscale tm microarchitecture for the pxa250 and PXA210 applications processors developer's manual intel order # 278525 intel ? pxa250 and PXA210 applications processors design guide intel order # 278523
pxa250 and PXA210 electrical, mechanical, and thermal specification 8 datasheet 3.0package information 3.1package introduction the applications processor is offered in two packages; ? the pxa250 applications processor, 256-pin mbga (refer to figure 2, pxa250 applications processor on page16) ? the PXA210 applications processor, 225-pin tpbga package (refer to figure 3, PXA210 applications processor on page26) figure 1. applications processor block diagram i 2 s i 2 c ac97 uart1 uart2 slow irda fast irda ssp dma controller and bridge 3.6864 mhz osc 32.768 khz osc system bus color or grayscale lcd controller megacell core memory controller pcmcia & cf control variable control dynamic control static control memory memory latency i/o asic xcvr sdram/ smrom 4 banks rom/ flash/ sram 4 banks rtc os timer pwm(2) int contr. clocks & pwr man. usb mmc client socket 0 socket 1
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 9 3.1.1functional signal definitions 3.1.1.1pxa250 signal pin descriptions signal definitions for the pxa250 applications processor are described in table2, pin and signal descriptions for the pxa250 applications processor on page9. the physical characteristics of the pxa250 applications processor are shown in figure 2, pxa250 applications processor on page16. the pinout for the pxa250 applications processor is described in table3, pxa250 256- lead 17x17mm mbga pinout ballpad number order on page17. table 2. pin and signal descriptions for the pxa250 applications processor (sheet 1 of 7) nametypedescription memory controller pins ma[25:0]ocz memory address bus. this bus signals the address requested for memory accesses. md[15:0]icoczmemory data bus. d[15:0] are used for 16-bit data mode. md[31:16]icocz memory data bus. d[31:16]: these data bits are used for the pxa250 applications processor 32-bit memories and are not pinned out for the PXA210 applications processor, 16-bit package option. noeocz memory output enable. this signal should be connected to the output enables of memory devices to control their data bus drivers. nweocz memory write enable. connect this signal should to the write enables of memory devices. nsdcs[3:0]ocz sdram cs for banks 0 through 3. connect these signals to the chip select (cs) pins for sdram. nsdcs0 is three-stateable nsdcs1-3 are not dqm[3:0]ocz sdram dqm for data bytes 0 through 3. connect these signals to the data output mask enables (dqm) for sdram. nsdrasocz sdram ras. connect this signal should to the row address strobe (ras) pins for all banks of sdram. nsdcasocz sdram cas. connect this signal should to the column address strobe (cas) pins for all banks of sdram. sdcke[0]oc sdram and/or synchronous static memory clock enable. connect sdcke[0] to the cke pins of smrom and sdram-timing synchronous flash. the memory controller provides control register bits for deassertion of each sdcke pin. sdcke[1]oc sdram and/or synchronous static memory clock enable. connect sdcke[1] to the sdram clock enable pins. it is de-asserted (held low) during sleep. sdcke[1] is always deasserted upon reset. the memory controller provides control register bits for deassertion of each sdcke pin.
pxa250 and PXA210 electrical, mechanical, and thermal specification 10 datasheet sdclk[2:0]ocz sdram and/or synchronous static memory clocks. connect sdclk[0] to the clock (clk) pins of smrom and sdram-timing synchronous flash. sdclk[1] and sdclk[2] should be connected to the clock pins of sdram in bank pairs 0/1 and 2/3, respectively. they are driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. at reset, all clock pins are free running at the divide by 2 clock speed and may be turned off via free running control register bits in the memory controller. the memory controller also provides control register bits for clock division and deassertion of each sdclk pin. sdclk[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for smrom or sdram-timing synchronous flash. sdclk[2:1] control register assertion bits are always deasserted upon reset. 0 and 2 are not three-stateable, sdclk1 is three-stateable ncs[5]/ gpio[33] icocz static chip selects. these signals are chip selects for static memory devices such as rom and flash. they are individually programmable in the memory configuration registers. ncs[5:3] may be used with variable data latency variable latency i/o devices. see note [1] ncs[4]/ gpio[80] icoczstatic chip select 4. ncs[3]/ gpio[79] icoczstatic chip select 3. ncs[2]/ gpio[78] icoczstatic chip select 2. ncs[1]/ gpio[15] icoczstatic chip select 1. ncs[0]icocz static chip select 0. this is the boot memory chip select. ncs[0] is a dedicated pin. rd/nwrocz read/write for static interface. intended for use as a steering signal for buffering logic rdy/ gpio[18] icocz variable latency i/o ready pin (input) see note [1] pcmcia/cf control pins npoe/ gpio[48] icocz pcmcia output enable. this pcmcia signal is an output and performs reads from memory and attribute space. see note [1] npwe/ gpio[49] icocz pcmcia write enable. this signal is an output and performs writes to memory and attribute space. see note [1] npiow/ gpio[51] icocz pcmcia i/o write. this signal is an output and performs write transactions to the pcmcia i/o space. see note [1] npior/ gpio[50] icocz pcmcia i/o read. this signal is an output and performs read transactions from the pcmcia i/o space. see note [1] npce[2:1]/ gpio[53, 52] icocz pcmcia card enable. these signals are outputs and select a pcmcia card. bit one enables the high byte lane and bit zero enables the low byte lane. see note [1] table 2. pin and signal descriptions for the pxa250 applications processor (sheet 2 of 7) nametypedescription
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 11 niois16/ gpio[57] icocz i/o select 16. this signal is an input and is an acknowledge from the pcmcia card that the current address is a valid 16 bit wide i/o address. see note [1] npwait/ gpio[56] icocz pcmcia wait. this signal is an input and is driven low by the pcmcia card to extend the length of the transfers to/from applications processor. see note [1] npsktsel/ gpio[54] icocz pcmcia socket select. this signal is an output and is used by external steering logic to route control, address and data signals to one of the two pcmcia sockets. when psktsel is low, socket zero is selected. when psktsel is high, socket one is selected. this signal has the same timing as an address. see note [1] npreg/ gpio[55] icocz pcmcia register select. this signal is an output and indicates that, on a memory transaction, the target address is attribute space. this signal has the same timing as address. see note [1] lcd controller pins l_dd(15:0)/ gpio[73:58] icocz lcd controller display data see note [1] l_fclk/ gpio[74] icocz lcd frame clock see note [1] l_lclk/ gpio[75] icocz lcd line clock see note [1] l_pclk/ gpio[76] icocz lcd pixel clock see note [1] l_bias/ gpio[77] icocz ac bias drive see note [1] full function uart pins ffrxd/ gpio[34] icocz full function uart receive pin see note [1] fftxd/ gpio[39] icocz full function uart transmit pin see note [1] ffcts/ gpio[35] icocz full function uart clear-to-send pin see note [1] ffdcd/ gpio[36] icocz full function uart data-carrier-detect pin see note [1] ffdsr/ gpio[37] icocz full function uart data-set-ready pin: see note [1] ffri/ gpio[38] icocz full function uart ring indicator pin see note [1] ffdtr/ gpio[40] icocz full function uart data-terminal-ready pin see note [1] ffrts/ gpio[41] icocz full function uart ready-to-send pin see note [1] table 2. pin and signal descriptions for the pxa250 applications processor (sheet 3 of 7) nametypedescription
pxa250 and PXA210 electrical, mechanical, and thermal specification 12 datasheet bluetooth uart pins btrxd/ gpio[42] icocz bluetooth uart receive pin see note [1] bttxd/ gpio[43] icocz bluetooth uart transmit pin see note [1] btcts/ gpio[44] icocz bluetooth uart clear-to-send pin see note [1] btrts/ gpio[45] icocz bluetooth uart data-terminal-ready pin see note [1] mmc controller pins mmcmdicoczmultimedia card command pin (i/o) mmdaticoczmultimedia card data pin (i/o) ssp pins sspsclk/ gpio[23] icocz synchronous serial port clock (output) see note [1] sspsfrm/ gpio[24] icocz synchronous serial port frame signal (output) see note [1] ssptxd/ gpio[25] icocz synchronous serial port transmit (output) see note [1] ssprxd/ gpio[26] icocz synchronous serial port receive (input) see note [1] sspextclk/ gpio[27] icocz synchronous serial port external clock (input) see note [1] usb client pins usb_piaoausb client port positive pin of differential pair. usb_niaoausb client port negative pin of differential pair. ac97 controller pins bitclk/ gpio[28] icocz ac97 audio port bit clock (output) see note [1] sdata_in0/ gpio[29] icocz ac97 audio port data in (input) see note [1] sdata_in1/ gpio[32] icocz ac97 audio port data in (input) see note [1] sdata_out/ gpio[30] icocz ac97 audio port data out (output) see note [1] sync/ gpio[31] icocz ac97 audio port sync signal (output) see note [1] nacresetoc ac97 audio port reset signal (output) this pin is a dedicated output. table 2. pin and signal descriptions for the pxa250 applications processor (sheet 4 of 7) nametypedescription
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 13 standard uart and icp pins irrxd/ gpio[46] icocz irda receive signal (input). see note [1] irtxd/ gpio[47] icocz irda transmit signal (output). this pin is the transmit pin for both the sir and fir functions. see note [1] i2c controller pins sclicocz i2c clock (bidirectional) this signal is bidirectional. when it is driving, it functions as an open collector device and requires a pull up resistor. as an input, it expects standard cmos levels. sdaicocz i2c data signal (bidirectional). bidirectional signal. when it is driving, it functions as an open collector device and requires a pull up resistor. as an input, it expects standard cmos levels. pwm pins pwm[1:0]/ gpio[17,16] icocz pulse width modulation channels 0 and 1 (outputs) see note [1] dedicated gpio pins gpio[1:0]icocz general purpose i/o. these two pins are contained in both the pxa250 and PXA210 applications processors. they are preconfigured at a hard reset (nreset) as wakeup sources for both rising and falling edge detects. these gpios do not have alternate functions and are intended to be used as the main external sleep wakeup stimulus. gpio[14:2])icocz general purpose i/o: these pins are not included in the PXA210 applications processor. see note [1] crystal pins pxtaliainput connection for 3.6864mhz crystal pextaloa output connection for 3.6846mhz crystal input connection for external oscillator txtaliainput connection for 32.768khz crystal textaloa output connection for 32.768khz crystal input connection for external oscillator table 2. pin and signal descriptions for the pxa250 applications processor (sheet 5 of 7) nametypedescription
pxa250 and PXA210 electrical, mechanical, and thermal specification 14 datasheet miscellaneous pins boot_sel [2:0] ic boot programming select pins. these pins are sampled to indicate the type of boot device present per the following table; boot_sel[2:0] description 000 asynchronous 32-bit rom 001asynchronous 16-bit rom 010reserved 011reserved 100one 32-bit smrom 101one 16 bit smrom 110two 16 bit smroms (32 bit bus) 111reserved pwr_enocz power enable. active high output. pwr_en enables the external power supply. negating it signals the power supply that the system is going into sleep mode and that the vdd power supply should be removed. nbatt_faul tic battery fault. active low input. signals the applications processor that the main power source is going away (battery is low or is removed from the system.) the assertion of nbatt_fault causes the applications processor to enter sleep mode. the device will not recognize a wakeup event while this signal is asserted. nvdd_faultic vdd fault. active low input. signals the applications processor that the main power source is going out of regulation (i.e. shorted card is inserted). nvdd_fault causes the device to enter sleep mode. nvdd_fault is ignored after a wakeup event until the power supply timer completes (approximately 10 ms). nresetic hard reset. active low input. nreset is a level sensitive input which starts the processor from a known address. a low level causes the current instruction to terminate abnormally, and all on-chip states to be reset. when nreset is driven high, the processor re- starts from address 0. nreset must remain low until the power supply is stable and the internal 3.6864mhz oscillator has come up to speed. while nreset is low the processor performs idle cycles. nreset_outoc reset out. active low output. this signal is asserted when nreset is asserted and deasserts after nreset is negated but before the first instruction fetch. nreset_out is also asserted for soft reset events (sleep, watchdog reset, gpio reset) jtag pins ntrstic jtag test interface reset. if jtag is used, then you must drive ntrst from low to high either before or at the same time as nreset if jtag is not used, then tie ntrst to either nreset or low. tdiicjtag test interface data input. note this pin has an internal pullup resistor. tdoocz jtag test interface data output. note this pin does not have an internal pullup resistor. tmsicjtag test interface mode select. note this pin has an internal pullup resistor. tckic jtag test interface reference clock. tck is the reference clock for all transfers on the jtag test interface. note this pin has an internal pulldown resistor. testictest mode. you must ground this pin. this pin is for manufacturing purposes only. table 2. pin and signal descriptions for the pxa250 applications processor (sheet 6 of 7) nametypedescription
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 15 testclkic test clock. this pin should be used for test purposes only. an end user should ground this pin. power and ground pins vccsup positive supply for the applications processor internal logic. connect this supply to the low voltage (.85 - 1.3v) supply on the pcb. vsssup ground supply for the applications processor internal logic. connect these pins to the common ground plane on the pcb. pll_vccsup positive supply for the plls and oscillators. it is recommended that you connect this pin to the common low voltage supply. pll_vsssupground signal for plls. vccqsup positive supply for all cmos i/o, except memory bus and pcmcia pins. connect these pins to the common 3.3volt supply on the pcb. vssqsup ground supply for all cmos i/o except memory bus and pcmcia pins. connect these pins to the common ground plane on the pcb. vccnsup positive supply for memory bus and pcmcia pins. connect these pins to the common 3.3volt supply on the pcb. vssnsup ground supply for memory bus and pcmcia pins. connect these pins to the common ground plane on the pcb. batt_vccsup backup battery connection. connect this pin to the backup battery supply. if a backup battery is not required, then this pin may be connected to the common 3.3volt supply on the pcb. note: 1. gpio reset operation: configured as gpio inputs by default after any reset. the input buffers for these pins are disabled to prevent current drain. table 2. pin and signal descriptions for the pxa250 applications processor (sheet 7 of 7) nametypedescription
pxa250 and PXA210 electrical, mechanical, and thermal specification 16 datasheet figure 2. pxa250 applications processor
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 17 table 3. pxa250 256-lead 17x17mm mbga pinout ballpad number order (sheet 1 of 3) ball #signalball #signalball #signal a1vccnc10vccqf3nsdcas a2l_dd[13]/gpio[71]c11vssqf4vccn a3l_dd[12]/gpio[70]c12usb_pf5sdclk[1] a4l_dd[11]/gpio[69]c13vccqf6vssq a5l_dd[9]/gpio[67]c14vssqf7gpio[10] a6l_dd[7]/gpio[65]c15irtxd/gpio[47]f8frts/gpio[41] a7gpio[11]c16vssf9sspsclk/gpio[23] a8l_bias/gpio[77]d1sdclk[2]f10ffdtr/gpio[40] a9ssprxd/gpio[26]d2sdclk[0]f11vcc a10sdata_out/gpio[30]d3rdnwrf12gpio[9] a11sdad4vccnf13boot_sel[2] a12ffdcd/gpio[36]d5l_dd[10]/gpio[68]f14gpio[8] a13ffrxd/gpio[34]d6l_dd[5]/gpio[63]f15vssq a14ffcts/gpio[35]d7l_dd[1]/gpio[59]f16vssq a15btcts/gpio[44]d8l_lclk/gpio[75]g1ma[0] a16sdata_in1/gpio[32]d9ssptxd/gpio[25]g2vssn b1dqm[1]d10nacresetg3nsdcs[2] b2dqm[2]d11sclg4nwe b3l_dd[15]/gpio[73]d12pwm[1]/gpio[17]g5noe b4gpio[14]d13bttxd/gpio[43]g6nsdcs[1] b5gpio[13]d14mmcmdg7vcc b6gpio[12]d15vccqg8vssq b7l_dd[3]/gpio[61]d16vssqg9vcc b8l_pclk/gpio[76]e1nsdrasg10vssq b9sspextclk/gpio[27]e2vssng11testclk b10ffri/gpio[38]e3sdcke[1]g12test b11ffdsr/gpio[37]e4sdcke[0]g13boot_sel[1] b12usb_ne5l_dd[6]/gpio[64]g14vccq b13btrxd/gpio[42]e6l_dd[4]/gpio[62]g15gpio[7] b14btrts/gpio[45]e7l_dd[[0]/gpio[58]g16boot_sel[0] b15irrxd/gpio[46]e8l_fclk/gpio[74]h1ma[2] b16mmdate9sspsfrm/gpio[24]h2ma[1] c1rdy/gpio[18]e10sdata_in0/gpio[29]h3md[16] c2vssne11sync/gpio[31]h4vccn c3l_dd[14]/gpio[72]e12pwm[0]/gpio[16]h5md[17] c4vssqe13fftxd/gpio[39]h6ma[3] c5l_dd[8]/gpio[66]e14vccqh7vssq
pxa250 and PXA210 electrical, mechanical, and thermal specification 18 datasheet c6vccqe15vssqh8vss c7l_dd[2]/gpio[60]e16vssqh9vss c8vssqf1nsdcs[0]h10vcc c9bitclk/gpio[28]f2nsdcs[3]h11ntrst h12tckl9vccp6md[24] h13tmsl10gpio[0]p7md26] h14gpio[6]l11pwr_enp8md[27] h15tdil12gpio[1]p9ncs[2]/gpio[78] h16tdol13gpio[2]p10md[29] j1ma[7]l14vssqp11md[12] j2vssnl15textalp12md[31] j3ma[6]l16txtalp13npoe/gpio[48] j4md[18]m1ma[14]p14npce[1]/gpio[52] j5ma[5]m2md[21]p15vssn j6ma[4]m3ma[15]p16npsktsel/gpio[54] j7vccm4vccnr1ma[18] j8vssm5md[1]r2vssn j9vssm6md[6]r3ma[20] j10vssqm7md[7]r4vssn j11gpio[5]m8dqm[0]r5ma[22] j12gpio[4]m9md[8]r6vssn j13nresetm10md[15]r7md[25] j14vssqm11batt_vccr8vssn j15pll_vccm12gpio[22]r9md[10] j16pll_vssm13npreg/gpio[55]r10vssn k1ma[8]m14vccnr11md[30] k2ma[9]m15vssnr12vssn k3md[19]m16niois16/gpio[57]r13ncs[4]/gpio[80] k4vccnn1md[22]r14vssn k5ma[10]n2vssnr15npiow/gpio[51] k6ma[11]n3ma[16]r16npce[2]/gpio[53] k7vssqn4md[0]t1vss k8vccn5vccnt2vccn k9vssqn6md[4]t3md[23] k10vccn7vccnt4ma[21] k11nreset_outn8ncs[0]t5ma[24] k12nbatt_faultn9vccnt6md[3] k13nvdd_faultn10md[13]t7md[5] table 3. pxa250 256-lead 17x17mm mbga pinout ballpad number order (sheet 2 of 3) ball #signalball #signalball #signal
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 19 3.1.1.2PXA210 signal pin descriptions signal definitions for the PXA210 applications processor are described in table 4. the physical characteristics of the PXA210 applications processor are shown in figure 3, PXA210 applications processor on page26. the pinout for the PXA210 applications processor is described in table5, PXA210 225-lead 13x13mm tpbga pinout ballpad number order on page27. k14gpio[3]n11vccnt8ncs[1]/gpio[15] k15pxtaln12dreq[0]/gpio[20]t9ncs[3]/gpio[79] k16pextaln13vccnt10md[9] l1ma[12]n14dreq[1]/gpio[19]t11md[11] l2vssnn15gpio[21]t12md[14] l3ma[13]n16npwait/gpio[56]t13ncs[5]/gpio[33] l4md[20]p1ma[17]t14npwe/gpio[49] l5md[2]p2ma[19]t15npior/gpio[50] l6vccp3vccnt16vccn l7dqm[3]p4ma[25] l8md[28]p5ma[23] table 3. pxa250 256-lead 17x17mm mbga pinout ballpad number order (sheet 3 of 3) ball #signalball #signalball #signal table 4. pin and signal descriptions for the PXA210 applications processor (sheet 1 of 7) pin nametypesignal descriptions memory controller pins ma[25:0]ocz memory address bus. (output) signals the address requested for memory accesses. md[15:0]icocz memory data bus. (input/output) lower 16 bits of the data bus. noeocz memory output enable. (output) connect to the output enables of memory devices to control data bus drivers. nweocz memory write enable. (output) connect to the write enables of memory devices. nsdcs[1:0]ocz sdram cs for banks 1 and 0. (output) connect to the chip select (cs) pins for sdram. for the PXA210 applications processor nsdcs0 can be hi-z, nsdcs1 cannot. dqm[1:0]ocz sdram dqm for data bytes 1 and 0. (output) connect to the data output mask enables (dqm) for sdram. nsdrasocz sdram ras. (output) connect to the row address strobe (ras) pins for all banks of sdram. nsdcasocz sdram cas. (output) connect to the column address strobe (cas) pins for all banks of sdram. sdcke[0]oc sdram and/or synchronous static memory clock enable. (output)connect to the cke pins of smrom and sdram-timing synchronous flash. the memory controller provides control register bits for deassertion.
pxa250 and PXA210 electrical, mechanical, and thermal specification 20 datasheet sdcke[1]oc sdram and/or synchronous static memory clock enable. (output) connect to the clock enable pins of sdram. it is deasserted during sleep. sdcke[1] is always deasserted upon reset. the memory controller provides control register bits for deassertion. sdclk[0]oc sdram and/or synchronous static memory clocks. (output) connect to the clock (clk) pins of smrom and sdram-timing synchronous flash. connect sdclk[1] to the clock pins of sdram in bank pairs 0/1. it is driven by either the internal memory controller clock or the internal memory controller clock divided by 2. at reset, all clock pins are free running at the divide by 2 clock speed and may be turned off via free running control register bits in the memory controller. the memory controller also provides control register bits for clock division and deassertion of each sdclk pin. sdclk[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for smrom or sdram- timing synchronous flash. sdclk[1] control register assertion bit is always deasserted on reset. sdclk[1] can be hi-z, sdclk[0] cannot. sdclk[1]ocz ncs[5]/ gpio[33] icocz static chip selects. (output) chip selects to static memory devices such as rom and flash. individually programmable in the memory configuration registers. ncs[5:3] can be used with variable latency i/o devices. ncs[4]/ gpio[80] icocz ncs[3]/ gpio[79] icocz ncs[2]/ gpio[78] icocz ncs[1]/ gpio[15] icocz npwe/ gpio[49] icocz vlio write enable (output). used as the write enable signal for variable latency i/o. ncs[0]icocz static chip select 0. (output) chip select for the boot memory. ncs[0] is a dedicated pin. rd/nwrocz read/write for static interface. (output) signals that the current transaction is a read or write. rdy/ gpio[18] icocz variable latency i/o ready pin. (input) notifies the memory controller when an external bus device is ready to transfer data. l_dd[8]/ gpio[66] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller alternate bus master request. (input) allows an external device to request the system bus from the memory controller. l_dd[15]/ gpio[73] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller grant. (output) notifies an external device that it has been granted the system bus. lcd controller pins l_dd(7:0)/ gpio[65:58] icocz lcd display data. (outputs) transfers pixel information from the lcd controller to the external lcd panel. l_dd[8]/ gpio[66] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller alternate bus master request. (input) allows an external device to request the system bus from the memory controller. table 4. pin and signal descriptions for the PXA210 applications processor (sheet 2 of 7) pin nametypesignal descriptions
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 21 l_dd[9]/ gpio[67] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 0. (output) chip select 0 for the mmc controller. l_dd[10]/ gpio[68] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 1. (output) chip select 1 for the mmc controller. l_dd[11]/ gpio[69] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc clock. (output) clock for the mmc controller. l_dd[12]/ gpio[70] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. rtc clock. (output) real time clock 1 hz tick. l_dd[13]/ gpio[71] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. 3.6864 mhz clock. (output) output from 3.6864 mhz oscillator. l_dd[14]/ gpio[72] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. 32 khz clock. (output) output from the 32 khz oscillator. l_dd[15]/ gpio[73] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller grant. (output) notifies an external device it has been granted the system bus. l_fclk/ gpio[74] icocz lcd frame clock. (output) indicates the start of a new frame. also referred to as vsync. l_lclk/ gpio[75] icocz lcd line clock. (output) indicates the start of a new line. also referred to as hsync. l_pclk/ gpio[76] icocz lcd pixel clock. (output) clocks valid pixel data into the lcd s line shift buffer. l_bias/ gpio[77] icocz ac bias drive. (output) notifies the panel to change the polarity for some passive lcd panel. for tft panels, this signal indicates valid pixel data. full function uart pins ffrxd/ gpio[34] icocz full function uart receive. (input) mmc chip select 0. (output) chip select 0 for the mmc controller. fftxd/ gpio[39] icocz full function uart transmit. (output) mmc chip select 1. (output) chip select 1 for the mmc controller. bluetooth uart pins btrxd/ gpio[42] icocz bluetooth uart receive. (input) bttxd/ gpio[43] icocz bluetooth uart transmit. (output) btcts/ gpio[44] icocz bluetooth uart clear-to-send. (input) btrts/ gpio[45] icocz bluetooth uart data-terminal-ready. (output) table 4. pin and signal descriptions for the PXA210 applications processor (sheet 3 of 7) pin nametypesignal descriptions
pxa250 and PXA210 electrical, mechanical, and thermal specification 22 datasheet standard uart and icp pins irrxd/ gpio[46] icocz irda receive signal. (input) receive pin for the fir function. standard uart receive. (input) irtxd/ gpio[47] icocz irda transmit signal. (output) transmit pin for the standard uart, sir and fir functions. standard uart transmit. (output) mmc controller pins mmcmdicocz multimedia card command. (bidirectional) mmdaticocz multimedia card data. (bidirectional) gpio[53]icocz mmc clock. (output) clock signal for the mmc controller. l_dd[9]/ gpio[67] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 0. (output) chip select 0 for the mmc controller. l_dd[10]/ gpio[68] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 1. (output) chip select 1 for the mmc controller. l_dd[11]/ gpio[69] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc clock. (output) clock for the mmc controller. ffrxd/ gpio[34] icocz full function uart receive. (input) mmc chip select 0. (output) chip select 0 for the mmc controller. fftxd/ gpio[39] icocz full function uart transmit. (output) mmc chip select 1. (output) chip select 1 for the mmc controller. ssp pins sspsclk/ gpio[23] icocz synchronous serial port clock. (output) sspsfrm/ gpio[24] icocz synchronous serial port frame. (output) ssptxd/ gpio[25] icocz synchronous serial port transmit. (output) ssprxd/ gpio[26] icocz synchronous serial port receive. (input) sspextclk/ gpio[27] icocz synchronous serial port external clock. (input) usb client pins usb_piaoaz usb client positive. (bidirectional) usb_niaoaz usb client negative pin. (bidirectional) table 4. pin and signal descriptions for the PXA210 applications processor (sheet 4 of 7) pin nametypesignal descriptions
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 23 ac97 controller and i 2 s controller pins bitclk/ gpio[28] icocz ac97 audio port bit clock. (input) ac97 clock is generated by codec 0 and fed into the PXA210 applications processor and codec 1. ac97 audio port bit clock. (output) ac97 clock is generated by the PXA210 applications processor. i 2 s bit clock. (input) i 2 s clock is generated externally and fed into PXA210 applications processor. i 2 s bit clock. (output) i 2 s clock is generated by the PXA210 applications processor. sdata_in0/ gpio[29] icocz ac97 audio port data in. (input) input line for codec 0. i 2 s data in. (input) input line for the i 2 s controller. sdata_in1/ gpio[32] icocz ac97 audio port data in. (input) input line for codec 1. i 2 s system clock. (output) system clock from i 2 s controller. sdata_out/ gpio[30] icocz ac97 audio port data out. (output) output from the PXA210 to codecs 0 and 1. i 2 s data out. (output) output line for the i 2 s controller. sync/ gpio[31] icocz ac97 audio port sync signal. (output) frame sync signal for the ac97 controller. i 2 ssync. (output) frame sync signal for the i 2 s controller. nacresetoc ac97 audio port reset signal. (output) i 2 c controller pins sclicocz i 2 c clock. (bidirectional) sdaicocz i 2 c data. (bidirectional). pwm pins pwm[1:0]/ gpio[17:16] icocz pulse width modulation channels 0 and 1. (outputs) gpio pins gpio[1:0]icocz general purpose i/o. wakeup sources on both rising and falling edges on nreset. gpio[57:48]icocz general purpose i/o. wakeup sources on both rising and falling edges on nreset. crystal and clock pins pxtalia 3.6864 mhz crystal input. pextaloa 3.6864 mhz crystal output. txtalia 32.768 khz crystal input. textaloa 32.768 khz crystal output. l_dd[12]/ gpio[70] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. rtc clock. (output) real time clock 1 hz tick. l_dd[13]/ gpio[71] icocz lcd display data. (output) transfers the pixel information from the lcd controller to the external lcd panel. 3.6864 mhz clock. (output) output from 3.6864 mhz oscillator. l_dd[14]/ gpio[72] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. 32 khz clock. (output) output from the 32 khz oscillator. table 4. pin and signal descriptions for the PXA210 applications processor (sheet 5 of 7) pin nametypesignal descriptions
pxa250 and PXA210 electrical, mechanical, and thermal specification 24 datasheet miscellaneous pins boot_sel [2:0] ic boot select pins. (input)indicates type of boot device. pwr_enoc power enable for the power supply. (output) when negated, it signals the power supply to remove power because the system is entering sleep mode. nbatt_faultic main battery fault. (input) signals that main battery is low or removed. assertion causes the PXA210 applications processor to enter sleep mode or force an imprecise data exception, which cannot be masked. the PXA210 applications processor will not recognize a wakeup event while this signal is asserted. nvdd_faultic vdd fault. (input) signals that the main power source is going out of regulation. nvdd_fault causes the PXA210 applications processor to enter sleep mode or force an imprecise data exception, which cannot be masked. nvdd_fault is ignored after a wakeup event until the power supply timer completes (approximately 10 ms). nresetic hard reset. (input) level sensitive input used to start the processor from a known address. assertion causes the current instruction to terminate abnormally and causes a reset. when nreset is driven high, the processor starts execution from address 0. nreset must remain low until the power supply is stable and the internal 3.6864 mhz oscillator has stabilized. nreset_outoc reset out. (output) asserted when nreset is asserted and deasserts after nreset is deasserted but before the first instruction fetch. nreset_out is also asserted for soft reset events: sleep, watchdog reset, or gpio reset. jtag and test pins ntrstic jtag test interface reset. resets the jtag/debug port. if jtag/debug is used, drive ntrst from low to high either before or at the same time as nreset. if jtag is not used, ntrst must be either tied to nreset or tied low. intel recommends that a jtag/debug port be added to all systems for debug and download. see chapter 9 in the intel ? pxa250 and PXA210 applications processor design guide for details. tdiic jtag test data input. (input) data from the jtag controller is sent to the PXA210 using this pin. this pin has an internal pull-up resistor. tdoocz jtag test data output. (output) data from the PXA210 applications processor is returned to the jtag controller using this pin. tmsic jtag test mode select. (input) selects the test mode required from the jtag controller. this pin has an internal pull-up resistor. tckic jtag test clock. (input) clock for all transfers on the jtag test interface. testic test mode. (input) reserved. must be grounded. testclkic test clock. (input) reserved. must be grounded. power and ground pins vccsup positive supply for internal logic. must be connected to the low voltage (.85 - 1.3v) supply on the pcb. vsssup ground supply for internal logic. must be connected to the common ground plane on the pcb. pll_vccsup positive supply for plls and oscillators. must be connected to a separate quiet supply plane on the pcb but may be connected to the common low voltage supply. pll_vsssup ground signal for plls. vccqsup positive supply for all cmos i/o except memory bus. must be connected to the common 3.3v supply on the pcb. table 4. pin and signal descriptions for the PXA210 applications processor (sheet 6 of 7) pin nametypesignal descriptions
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 25 vssqsup ground supply for all cmos i/o except memory bus. must be connected to the common ground plane on the pcb. vccnsup positive supply for memory bus. must be connected to the common 3.3v or 2.5v supply on the pcb. vssnsup ground supply for memory bus and some gpio pins. must be connected to the common ground plane on the pcb. batt_vccsup backup battery supply. connect to the backup battery supply. if a backup battery is not required then this pin may be connected to the common 3.3v supply on the pcb. table 4. pin and signal descriptions for the PXA210 applications processor (sheet 7 of 7) pin nametypesignal descriptions
pxa250 and PXA210 electrical, mechanical, and thermal specification 26 datasheet figure 3. PXA210 applications processor
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 27 table 5. PXA210 225-lead 13x13mm tpbga pinout ballpad number order (sheet 1 of 3) ball #signalball #signalball #signal a1dqm[1]c12bttxd/gpio[43]f8ssprxd/gpio[26] a2l_dd[14]/gpio[72]c13vssqf9vcc a3l_dd[10]/gpio[68]c14vssf10fftxd/gpio[39] a4vssqc15vccqf11vcc a5l_dd[6]/gpio[64]d1vccf12vssq a6l_dd[2]/gpio[60]d2vssqf13testclk a7l_lclk/gpio[75]d3sdclk[1]f14boot_sel[0] a8sspsclk/gpio[23]d4l_dd[15]/gpio[73]f15test a9sspextclk/gpio[27]d5vccg1ma[0] a10nacresetd6l_dd[5]/gpio[63]g2noe a11pwm[1]/gpio[17]d7l_dd[0]/gpio[58]g3nwe a12vssqd8sspsfrm/gpio[24]g4vccn a13ffrxd/gpio[34]d9sdata_out/gpio[30]g5vssn a14btcts/gpio[44]d10sclg6rdnwr a15irrxd/gpio[46]d11sdata_in1/gpio[32]g7vss b1rdy/gpio[18]d12boot_sel[1]g8vss b2vssnd13vssqg9vss b3l_dd[13]/gpio[71]d14vssqg10btrxd/gpio[42] b4l_dd[9]/gpio[67]d15vssqg11ntrst b5vssqe1nsdcasg12tdi b6l_dd[3]/gpio[61]e2vccng13tck b7l_pclk/gpio[76]e3vssng14tms b8vssqe4sdclk[0]g15tdo b9bitclk/gpio[28]e5l_dd[11]/gpio[69]h1vccn b10sdae6l_dd[7]/gpio[65]h2vssn b11vssqe7l_dd[1]/gpio[59]h3ma[2] b12usb_ne8ssptxd/gpio[25]h4ma[1] b13btrts/gpio[45]e9sync/gpio[31]h5vcc b14irtxd/gpio[47]e10vccqh6vssq b15mmdate11mmcmdh7vss c1sdcke[1]e12vccqh8vss c2sdcke[0]e13vssqh9vss c3vccne14vssqh10vssq c4l_dd[12]/gpio[70]e15boot_sel[2]h11vcc c5vccqf1vssnh12vssq c6l_dd[4]/gpio[62]f2nsdcs[0]h13vcc c7l_bias/gpio[77]f3nsdrash14pll_vcc
pxa250 and PXA210 electrical, mechanical, and thermal specification 28 datasheet c8vccqf4nsdcs[1]h15pll_vss c9sdata_in0/gpio[29]f5vccj1ma[5] c10pwm[0]/gpio[16]f6l_dd[8]/gpio[66]j2ma[6] c11usb_pf7l_fclk/gpio[74]j3vssn j4ma[4]l15gpio[0]p11vccn j5ma[3]m1ma[14]p12md[15] j6vssqm2ma[15]p13vccn j7vssm3vccnp14gpio[50] j8vssm4ma[16]p15vssq j9vssm5vccnr1ma[19] j10vssqm6vssnr2ma[20] j11nresetm7md[3]r3ma[21] j12nreset_outm8md[7]r4ma[25] j13pwr_enm9ncs[1]/gpio[15]r5md[1] j14nvdd_faultm10md[10]r6vccn j15nbatt_faultm11md[13]r7md[5] k1ma[8]m12gpio[48]r8ncs[0] k2ma[9]m13gpio[52]r9ncs[3]/gpio[79] k3ma[10]m14vssnr10md[9] k4ma[7]m15gpio[56]r11vssn k5vccnn1vssnr12md[14] k6vccn2ma[18]r13ncs[4]/gpio[80] k7vssqn3vssr14npwe/gpio[49] k8vccn4ma[22]r15gpio[51] k9vssqn5ma[24] k10vccn6vccn k11gpio[1]n7vcc k12textaln8vssn k13txtaln9dqm[0] k14pextaln10vccn k15pxtaln11md[12] l1vssnn12vssn l2vccnn13ncs[5]/gpio[33] l3ma[12]n14gpio[53] l4ma[13]n15vccn l5ma[11]p1ma[17] l6vssqp2vssn l7md[2]p3vccn table 5. PXA210 225-lead 13x13mm tpbga pinout ballpad number order (sheet 2 of 3) ball #signalball #signalball #signal
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 29 3.2package power ratings 4.0electrical specifications 4.1absolute maximum ratings this section provide the absolute maximum ratings for the applications processors. do not exceed these parameters. if you do the part may be permanently damaged. operation at absolute maximum ratings is not guaranteed. l8md[6]p4ma[23] l9vssnp5md[0] l10md[11]p6vssn l11batt_vccp7md[4] l12gpio[54]p8vccn l13gpio[55]p9ncs[2]/gpio[78] l14gpio[57]p10md[8] table 6. ja and maximum power ratings processor ja max power pxa25033 c /w 1.4w PXA21044 c /w 888w table 5. PXA210 225-lead 13x13mm tpbga pinout ballpad number order (sheet 3 of 3) ball #signalball #signalball #signal table 7. absolute maximum ratings (sheet 1 of 2) symbol description min max units ts storage temperature -40 125 deg c vss_o offset voltage between any two vss pins (vss, vssq, vssn) -0.3 0.3 v vcc_o offset voltage between any of the following pins: vccq and vccn -0.3 0.3 v vcc_hv voltage applied to high voltage supplies (vccq, vccn, batt_vcc) vss-0.3 vss+4.0 v vcc_lv voltage applied to low voltage supplies (vcc, pll_vcc) vss-0.3 vss+1.65 v vip voltage applied to non-supply pins except xtal pins vss-0.3 max of vccq+0.3, vss+4.0 v
pxa250 and PXA210 electrical, mechanical, and thermal specification 30 datasheet 4.2operating conditions this section shows voltage, frequency, and temperature specifications for the applications processor for four different ranges (shown in table8, voltage, temperature, and frequency electrical specifications .) the temperature specification for each range is constant; the frequency range is dependent on the operation voltage. note: the parameters in table 8 are preliminary and subject to change. vip_x voltage applied to xtal pins (pxtal, pextal, txtal, textal) vss-0.3 max of vcc+0.3, vss+1.65 v vesd maximum esd stress voltage, human body model; any pin to any supply pin, either polarity, or any pin to all non- supply pins together, either polarity. three stresses maximum. 2000 v ieos maximum dc input current (electrical overstress) for any non-supply pin 5 ma table 7. absolute maximum ratings (sheet 2 of 2) symbol description min max units table 8. voltage, temperature, and frequency electrical specifications (sheet 1 of 2) symbol description min typical max units ta ambient temperature - extended temp -40 - 85 c ta ambient temperature - nominal temp 0 - 70 c vvss vss, vssn, vssq voltage -0.3 0 0.3 v vvccq vccq voltage 3.0 3.3 3.6 v vvccn vccn voltage 2.375 2.5/3.3 3.6 v vbatt batt_vcc voltage 2.2 3.0 3.8 v low voltage range (pxa250 and PXA210) vvcc_l vcc, pll_vcc voltage, low range 0.765 0.85 0.935 v fturbo_l turbo mode frequency, low range 99.5 132.7 mhz fsdram_l external synchronous memory frequency, low range 50 99.5 mhz medium voltage range (pxa250 and PXA210) vvcc_m vcc, pll_vcc voltage, mid range 0.90 1.00 1.10 v fturbo_m turbo mode frequency, mid range 99.5 199.1 mhz fsdram_m external synchronous memory frequency, mid range 50 99.5 mhz high voltage range (pxa250) vvcc_h vcc, pll_vcc voltage, high range 0.99 1.10 1.21 v fturbo_h turbo mode frequency, high range 99.5 298.7 mhz fsdram_h external synchronous memory frequency, high range 50 99.5 mhz
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 31 4.3targeted dc specifications the dc characteristics for each pin include input sense levels and output drive levels and currents. these parameters can be used to determine maximum dc loading, and also to determine maximum transition times for a given load. the dc operating conditions for the high- and low-strength input, output, and i/o pins are shown in table9, standard input, output, and i/o pin dc operating conditions . all dc specification values are valid for the entire temperature range of the device. peak voltage range (pxa250) vvcc_p vcc, pll_vcc voltage, peak range 1.17 1.30 1.43 v fturbo_p turbo mode frequency, peak range 99.5 398.2 mhz fsdram_p external synchronous memory frequency, peak range 50 99.5 mhz table 8. voltage, temperature, and frequency electrical specifications (sheet 2 of 2) symbol description min typical max units table 9. standard input, output, and i/o pin dc operating conditions symbol description min typical max units input dc operating conditions vih input high voltage, all standard input and i/o pins 0.8*vccq vccq v vil input low voltage, all standard input and i/o pins vss 0.2*vccq v iin input leakage, all standard input and io pins 10 a output dc operating conditions voh output high voltage, all standard output and i/o pins vccq-0.6 vccq v vol output low voltage, all standard output and i/o pins vss vss+0.4 v ioh_h output high current, all standard, high- strength output and i/o pins (vo=voh) -10 ma ioh_l output high current, all standard, low- strength output and i/o pins (vo=voh) -3 ma iol_h output low current, all standard, high- strength output and i/o pins (vo=voh) 10 ma iol_l output low current, all standard, low- strength output and i/o pins (vo=voh) 3 ma
pxa250 and PXA210 electrical, mechanical, and thermal specification 32 datasheet 4.4targeted ac specifications all the non-analog input, output, and i/o pins on the applications processor can be divided into one of two categories: 1.high strength input, output, and i/o pins: ? ncs[5:1] (gp 33, 80, 79, 78, 15 respectively), ncs[0] ? md[31:0], ma[25:0] ? dqm[3:0] ? noe, nwe, nsdras, nsdcas, nsdcs[3:0] ? sdclk[2:0], sdcke[1:0] ? rdnwr, rdy (gp[18]) ? npwe, npoe pins (gp[49:48]) ? mmclk (gp[53]), mmcmd, mmdat ? tdo ? nacreset 2.low strength input, output, and i/o pins - all remaining non-supply pins a pin s ac characteristics include input and output capacitance. these determine loading for external drivers or other load analysis. the ac characteristics also include a de-rating factor, which indicates how much faster or slower the ac timings get with different loads. the ac operating conditions for the high- and low-strength input, output, and i/o pins are shown in table10, standard input, output, and i/o pin ac operating conditions . all ac specification values are valid for entire temperature range of the device. table 10. standard input, output, and i/o pin ac operating conditions symbol description min typical max units cin input capacitance, all standard input and io pins 10 pf cout_h output capacitance, all standard high- strength output and io pins 251 501 pf tdf_h output de-rating, falling edge on all standard, high-strength output and i/o pins, from 50pf load. ns/pf tdr_h output de-rating, rising edge on all standard, high-strength output and i/o pins, from 50pf load. ns/pf note: ac specifications guaranteed for loads in this range. all testing is done at 50pf
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 33 4.5oscillator electrical specifications the applications processor contains two oscillators: a 32.768khz oscillator and a 3.6864mhz oscillator. each is for a specific crystal. when choosing a crystal, match the crystal parameters as closely as possible. 4.5.132.768khz oscillator specifications the 32.768khz oscillator is connected between the txtal (amplifier input) and textal (amplified output). the 32.768khz specifications are shown in table11, 32.768khz oscillator specifications . to drive the 32.768khz crystal pins from an external source: ? drive the textal pin with a digital signal that has a low level near 0volts and a high level near vcc. do not exceed vcc or go below vss by more than 100mv. the minimum slew rate is 1volt per 1 s. the maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1ma. ? float the txtal pin or drive it complementary to the textal pin, with the same voltage level, slew rate, and input current restrictions. table 11. 32.768khz oscillator specifications symbol description min typical max units crystal specifications - typical is fox nc38 fxt crystal frequency, txtal/textal 32.768 khz lmt motional inductance, txtal/textal 6827.81 h cmt motional capacitance, txtal/textal 3.455 ff rmt motional resistance, txtal/textal 6 16 35 k cot shunt capacitance txtal to textal 1.6 pf clt load capacitance txtal/textal 12.5 pf amplifier specifications vih_x input high voltage, txtal 0.8*vcc vcc v vil_x input low voltage, txtal vss 0.2*vcc v iin_xt input leakage, txtal 1 a cin_xt input capacitance, txtal/textal 18 25 pf ts_xt stabilization time 2 - 10 s board specifications rp_xt parasitic resistance, txtal/textal to any node 20 m cp_xt parasitic capacitance, txtal/textal, total 5 pf cop_xt parasitic shunt capacitance, txtal to textal 0.4 pf
pxa250 and PXA210 electrical, mechanical, and thermal specification 34 datasheet 4.5.23.6864mhz oscillator specifications the 3.6864mhz oscillator is connected between the pxtal (amplifier input) and pextal (amplified output). the 3.6864mhz specifications are shown in table12, 3.6864mhz oscillator specifications . to drive the 3.6864mhz crystal pins from an external source: ? drive the pextal pin with a digital signal with a low level near 0volts and a high level near vcc. do not exceed vcc or go below vss by more than 100mv. the minimum slew rate is 1volt / 100ns. the maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1ma. ? float the pxtal pin or drive it complementary to the pxtal pin, with the same voltage level, slew rate, and input current restrictions. if floated, some degree of noise susceptibility will be introduced in the system, and it is therefore not recommended. table 12. 3.6864mhz oscillator specifications symbol description min typical max units crystal specifications - typical is fox hc49s fxp crystal frequency, pxtal/pextal 3.6864 mhz lmp motional inductance, pxtal/pextal 0.50593 h cmp motional capacitance, pxtal/pextal 3.68488 ff rmp motional resistance, pxtal/pextal 50 99.3 200 w cop shunt capacitance pxtal to pextal 1.7 pf clp load capacitance pxtal/pextal 20 pf amplifier specifications vih_x input high voltage, pxtal 0.8*vcc vcc v vil_x input low voltage, pxtal vss 0.2*vcc v iin_xp input leakage, pxtal 10 a cin_xp input capacitance, pxtal/pextal 40 50 pf ts_xp stabilization time 17.8 67.8 ms board specifications rp_xp parasitic resistance, pxtal/pextal to any node 20 m cp_xp parasitic capacitance, pxtal/pextal, total 5 pf cop_xp parasitic shunt capacitance, pxtal to pextal 0.4 pf
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 35 4.6reset and power ac timing specifications the applications processor asserts the nreset_out pin in one of several different modes: ? power on ? hardware reset ? watchdog reset ? gpio reset ? sleep mode the following sections give the timing and specifications for the entry and exit of these modes. 4.6.1power on timing the external voltage regulator and other power-on devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. this sequence is shown in figure 4, power-on reset timing on page36, and detailed in table13, power-on timing specifications on page36. on the applications processor, it is important that the power supplies be powered-up in a certain order to avoid high current situations. the required order is: 1.batt_vcc 2.vccq 3.vccn 4.vcc and pll_vcc the supply in step 3 may be powered at the same time as those in step 2, however, vccn should not be powered before vccq.
pxa250 and PXA210 electrical, mechanical, and thermal specification 36 datasheet note: if hardware reset is entered during sleep mode, follow the proper power-supply stabilization times and nreset timing requirements indicated in table 13. 4.6.2hardware reset timing the timing sequences shown in hardware reset timing for hardware reset assumes stable power supplies at the assertion of nreset. if the power supplies are unstable, follow the timings indicated in section 4.6.1, power on timing on page35. figure 4. power-on reset timing table 13. power-on timing specifications symbol description min typical max units tr_batt batt_vcc rise / stabilization time 0.01 100 ms tr_vccq vccq, vccn rise / stabilization time 0.01 100 ms tr_vcc vcc, pll_vcc rise / stabilization time 0.01 10 ms td_vccq delay between batt_vcc at voltage and before vccq and vccn applied 0 ms td_vcc delay from vccq, vccn at voltage and before vcc, pll_vcc applied 0 ms td_ntrst delay between vcc, pll_vcc stable and ntrst deasserted 50 ms td_jtag delay between ntrst deasserted and jtag pins active, with nreset asserted 0.03 ms td_nreset delay between vcc, pll_vcc stable and nreset deasserted 50 ms td_out delay between nreset deasserted and nreset_out deasserted 18.1 18.2 ms batt_vcc vccq vcc ntrst jtag pins nreset t r_batt t r_vccq t r_vcc t d_vccq t d_vcc t d_ntrst t d_jtag t d_nreset t d_out note: nbatt_fault and nvdd_fault must be high before nreset_out is deasserted or the cotulla enters sleep mode vccn t r_vccn t d_vccn note: nbatt_fault and nvdd_fault must be high before nreset_out is deasserted or the pxa250 applications processor enters sleep mode.
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 37 4.6.3watchdog reset timing watchdog reset is an internally generated reset and therefore has no external pin dependencies. the nresetout pin is the only indicator of watchdog reset, and it stays asserted for t dhw_out . refer to figure 5, hardware reset timing on page37. 4.6.4gpio reset timing gpio reset is generated externally, and the source is reconfigured as a standard gpio as soon as the reset propagates internally. the clocks module is not reset by gpio reset, so the timing varies based on the frequency of clock selected and if the clocks and power manager is in the frequency change sequence when gpio reset is asserted (see section 4.5.1, 32.768khz oscillator specifications on page33.) figure 6, gpio reset timing on page37 shows the possible timing of gpio reset. figure 5. hardware reset timing table 14. hardware reset timing specifications symbol description min typical max units tdhw_nreset minimum assertion time of nreset 0.001 ms tdhw_out_a delay between nreset asserted and nreset_out asserted 0 0.001 ms tdhw_out delay between nreset deasserted and nreset_out deasserted 18.1 18.2 ms nreset nreset_out t dhw_nreset t dhw_out note: nbatt_fault and nvdd_fault must be high before nreset is deasserted or the cotulla will enter sleep mode t dhw_out_a note: nbatt_fault and nvdd_fault must be high before nreset is deasserted or the pxa250 applications processor enters sleep mode. figure 6. gpio reset timing gp[1] nreset_out t dhw_out t a_gp[1] t dhw_out_a note: nbatt_fault and nvdd_fault must be high before nreset is deasserted or the application processor will enter sleep mode
pxa250 and PXA210 electrical, mechanical, and thermal specification 38 datasheet 4.6.5sleep mode timing sleep mode is internally asserted, it and asserts the nreset_out and pwr_en signals. the sequence indicated in figure 7, sleep mode timing on page38 and detailed in figure 16, sleep mode timing specifications on page39 is the required timing parameters for sleep mode. table 15. gpio reset timing specifications symbol description min typical max units ta_gp[1] minimum assert time of gp[1]1 in 3.6864mhz input clock cycles 4 - cycles tdhw_out_a delay between gp[1] asserted and nreset_out asserted in 3.6864mhz input clock cycles 6 8 cycles tdhw_out delay between nreset_out asserted and nreset_out deasserted, run or turbo mode2 5 28 s tdhw_out_f delay between nreset_out asserted and nreset_out deasserted, during frequency change sequence3 5 380 s notes: 1.gp[1] is not recognized as a reset source again until configured to do so in software. software should check the state of gp[1] before configuring as a reset to ensure no spurious reset is generated. 2.time is 512*n processor clock cycles plus up to 4 cycles of the 3.6864mhz input clock. 3.time during the frequency change sequence depends on the state of the pll lock detector at the assertion of gpio reset. the lock detector has a maximum time of 350 s plus synchronization. figure 7. sleep mode timing gp[x] pwr_en vcc nvdd_fault nreset_out t dsm_out note: nbatt_fault must be high or cotulla will not exit sleep mode t a_gp[x] t d_pwr_r t d_pwr_f t d_fault t dsm_vcc note: nbatt_fault must be high or the pxa250 applications processor will not exit sleep mode.
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 39 4.7memory bus and pcmcia ac specifications this section gives the timing information for these types of memory: ? sram / rom / flash / synchronous fast flash asynchronous writes (table17, sram / rom / flash / synchronous fast flash ac specifications on page39) ? variable latency i/o (table18, variable latency i/o interface ac specifications on page40) ? card interface (pcmcia or compact flash) (table19, card interface (pcmcia or compact flash) ac specifications on page41) ? synchronous memories (table20, synchronous memory interface ac specifications 1 on page42) table 16. sleep mode timing specifications symbol description min typical max units ta_gp[x} assert time of gpio wake up source (x=[15:0]) 91.6 s td_pwr_f delay from nreset_out asserted to pwr_en deasserted 61 91.6 s td_pwr_r delay between gp[x] asserted to pwr_en asserted 30.5 122.1 s tdsm_vcc delay between pwr_en asserted and vcc stable 10 ms td_fault delay between pwr_en asserted and nvdd_fault deasserted 10 ms tdsm_out delay between pwr_en asserted and nreset_out deasserted, opde set 28.0 80 ms tdsm_out_o delay between pwr_en asserted and nreset_out deasserted, opde clear 10.35 10.5 ms table 17. sram / rom / flash / synchronous fast flash ac specifications (sheet 1 of 2) symbol description memclk frequency (mhz) units, notes 99.5 118.0 132.7 147.5 165.9 tromas ma(25:0) setup to ncs, noe, nsdcas (as nadv) asserted 10 8.5 7.5 6.8 6 ns, 1 tromah ma(25:0) hold after ncs, noe, nsdcas (as nadv) deasserted 10 8.5 7.5 6.8 6 ns, 1 tromasw ma(25:0) setup to nwe asserted 30 25.5 22.5 20.4 18 ns, 3 tromahw ma(25:0) hold after nwe deasserted 10 8.5 7.5 6.8 6 ns, 1 tromces ncs setup to nwe asserted 20 17 15 13.6 12 ns, 2 tromceh ncs hold after nwe deasserted 10 8.5 7.5 6.8 6 ns, 1 tromds md(31:0), dqm(3:0) write data setup to nwe asserted 10 8.5 7.5 6.8 6 ns, 1
pxa250 and PXA210 electrical, mechanical, and thermal specification 40 datasheet tromdswh md(31:0), dqm(3:0) write data setup to nwe deasserted 20 17 15 13.6 12 ns, 2 tromdh md(31:0), dqm(3:0) write data hold after nwe deasserted 10 8.5 7.5 6.8 6 ns, 1 tromnwe nwe high time between beats of write data 20 17 15 13.6 12 ns, 2 notes: 1.this number represents 1 memclk period 2.this number represents 2 memclk periods 3.this number represents 3 memclk periods table 18. variable latency i/o interface ac specifications symbol description memclk frequency (mhz) units, notes 99.5 118.0 132.7 147.5 165.9 tvlioas ma(25:0) setup to ncs asserted 10 8.5 7.5 6.8 6 ns, 1 tvlioasrw ma(25:0) setup to noe or npwe asserted 10 8.5 7.5 6.8 6 ns, 1 tvlioah ma(25:0) hold after noe or npwe deasserted 10 8.5 7.5 6.8 6 ns, 1 tvlioces ncs setup to noe or npwe asserted 20 17 15 13.6 12 ns, 2 tvlioceh ncs hold after noe or npwe deasserted 10 8.5 7.5 6.8 6 ns, 1 tvliodsw md(31:0), dqm(3:0) write data setup to npwe asserted 10 8.5 7.5 6.8 6 ns, 1 tvliodswh md(31:0), dqm(3:0) write data setup to npwe deasserted 20 17 15 13.6 12 ns, 2 tvliodhw md(31:0), dqm(3:0) hold after npwe deasserted 10 8.5 7.5 6.8 6 ns, 1 tvliodhr md(31:0) read data hold after noe deasserted 0 0 0 0 0 ns tvliordyh rdy hold after noe, npwe deasserted 0 0 0 0 0 ns tvlionpwe npwe, noe high time between beats of write or read data 20 17 15 13.6 12 ns, 2 notes: 1.this number represents 1 memclk period 2.this number represents 2 memclk periods table 17. sram / rom / flash / synchronous fast flash ac specifications (sheet 2 of 2) symbol description memclk frequency (mhz) units, notes 99.5 118.0 132.7 147.5 165.9
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 41 table 19. card interface (pcmcia or compact flash) ac specifications symbol description memclk frequency (mhz) units, notes 99.5 118.0 132.7 147.5 165.9 tcardas ma(25:0), npreg, psktsel, npce setup to npwe, npoe, npiow, or npior asserted 20 17 15 13.6 12 ns, 1 tcardah ma(25:0), npreg, psktsel, npce hold after npwe, npoe, npiow, or npior deasserted 10 8.5 7.5 6.8 6 ns, 1 tcardds md(31:0) setup to npwe, npoe, npiow, or npior asserted 10 8.5 7.5 6.8 6 ns, 1 tcarddh md(31:0) hold after npwe, npoe, npiow, or npior deasserted 10 8.5 7.5 6.8 6 ns, 1 tcardcmd npwe, npoe, npiow, or npior command assertion 30 25.5 22.5 20.4 18 ns, 1 note: these numbers are minimums. they can be much longer based on the programmable card interface timing registers.
pxa250 and PXA210 electrical, mechanical, and thermal specification 42 datasheet 4.8peripheral module ac specifications this section describes the ac specifications for these peripheral units: ? lcd ? ssp table 20. synchronous memory interface ac specifications 1 symbol description min max units, notes sdram / smrom / sdram-timing synchronous flash (synchronous) tsynclk sdclk period 10 20 ns, 2 tsyncmd nsdcas, nsdras, nwe, nsdcs assert time 1 sdclk tsynrcd nsdras to nsdcas assert time 1 sdclk tsyncas nsdcas to nsdcas assert time 2 sdclk tsynsdos ma(25:0), md(31:0), dqm(3:0), nsdcs(3:0), nsdras, nsdcas, nwe, noe, sdcke(1:0), rdnwr output setup time to sdclk(2:0) rise 3.8 ns, 3 tsynsdoh ma(25:0), md(31:0), dqm(3:0), nsdcs(3:0), nsdras, nsdcas, nwe, noe, sdcke(1:0), rdnwr output hold time from sdclk(2:0) rise 3.6 ns, 3 tsynsdis md(31:0) read data input setup time from sdclk(2:0) rise 0.5 ns tsyndih md(31:0) read data input hold time from sdclk(2:0) rise 1.5 ns fast flash (synchronous reads only) tffclk sdclk period 15 20 ns, 4 tffas ma(25:0) setup to nsdcas (as nadv) asserted 0.5 sdclk tffces ncs setup to nsdcas (as nadv) asserted 0.5 sdclk tffadv nsdcas (as nadv) pulse width 1 sdclk tffos nsdcas (as nadv) deassertion to noe assertion 3 sdclk tffceh noe deassertion to ncs deassertion 4 sdclk notes: 1.these numbers are for a maximum 99.5mhz memclk and 99.5mhz output sdclk. 2.sdclk for sdram, smrom, and sdram-timing synchronous flash can be at the slowest, divide-by-2 of the 99.5mhz memclk. it can be 99.5mhz at the fastest. 3.this number represents 1/2 sdclk period. 4.sdclk for fast flash can be at the slowest, divide-by-2 of the 99.5mhz memclk. it can be divide-by-2 of the 132.7mhz memclk at its fastest.
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 43 4.8.1lcd module ac timing figure 8 describes the lcd timing parameters. the lcd pin timing specifications are referenced to the pixel clock (l_pclk). values for the parameters are given in table 21. 4.8.2ssp module ac timing figure 9, ssp ac timing definitions on page44 describes the ssp timing parameters. the ssp pin timing specifications are referenced to sclk_c. values for the parameters are given in table22, ssp ac timing specifications on page44. figure 8. lcd ac timing definitions table 21. lcd ac timing specifications symbol description min max units notes tpclkdv l_pclk rise/fall to l_ldd<7:0> driven valid 14 ns 1 tpclklv l_pclk fall to l_lclk driven valid 14 ns 2 tpclkfv l_pclk fall to l_lfclk driven valid 14 ns 2 tpclkbv l_pclk rise to l_bias driven valid 14 ns 2 notes: 1.you can program the lcd data pins to be driven on either the rising or falling edge of the pixel clock (l_pclk). 2.these lcd signals can, at times, transition when l_pclk is not clocking (between frames). at this time, they are clocked with the internal version of the pixel clock before it is driven out onto the l_pclk pin. a4775-01 l_ldd[7:0] (rise) l_ldd[7:0] (fall) l_pclk l_lclk l_bias l_fclk t pclkdv t pclklv t pclkfv t pclkbv t pclkdv
pxa250 and PXA210 electrical, mechanical, and thermal specification 44 datasheet 4.8.3boundary scan test signal timings boundary scan test signal timing is shown in table23, boundary scan test signal timing . figure 9. ssp ac timing definitions table 22. ssp ac timing specifications symbol description min max units notes tsfmv sclk_c rise to sfrm_c driven valid 21 ns trxds rxd_c valid to sclk_c fall (input setup) 11 ns trxdh sclk_c fall to rxd_c invalid (input hold) 0 ns tsfmv sclk_c rise to txd_c valid 22 ns a4774-01 sclk_c sfrm_c txd_c rxd_c t sfmv t sfmv t rxds t rxdh table 23. boundary scan test signal timing (sheet 1 of 2) symbol parameter min max units notes tbsf tck frequency 0.0 33.33 mhz tbsch tck high time 15.0 ns measured at 1.5v tbscl tck low time 15.0 ns measured at 1.5v tbscr tck rise time 5.0 ns 0.8v to 2.0v tbscf tck fall time 5.0 ns 2.0v to 0.8v tbsis1 input setup to tck tdi, tms 4.0 ns tbsih1 input hold from tck tdi, tms 6.0 ns tbsis2 input setup to tck ntrst 25.0 ns tbsih2 input hold from tck ntrst 3.0 ns tbsov1 tdo valid delay 1.5 6.9 ns relative to falling edge of tck tof1 tdo float delay 1.1 5.4 ns relative to falling edge of tck tov12 all outputs (non-test) valid delay 1.5 6.9 ns relative to falling edge of tck
electrical, mechanical, and thermal specification pxa250 and PXA210 datasheet 45 4.9ac test conditions the ac specifications in section 4.4, targeted ac specifications on page32are tested with a 50pf load indicated in figure 10. tof2 all outputs (non-test) float delay 1.1 5.4 ns relative to falling edge of tck tis10 input setup to tck all inputs (non-test) 4.0 ns tih8 input hold from tck all inputs (non-test) 6.0 ns table 23. boundary scan test signal timing (sheet 2 of 2) symbol parameter min max units notes figure 10. ac test load output ball c l c l = 50pf

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