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8 bit microcontroller tlcs-870/c series TMP86FM48
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the qua lity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utiliz ing toshiba products, to comply with the standards of safety in making a safe design for the entire sy stem, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most r ecent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, of fice equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation in struments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infring ements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliabil ity assurance/handling precautions. 030619_s ? 2007 toshiba corporation all rights reserved
TMP86FM48 2007-08-24 86fm48-1 cmos 8-bit microcontroller TMP86FM48ug/fg the TMP86FM48 is the high-speed, high-per formance and low powe r consumption 8-bit microcomputer, including flash, ram, multi-func tion timer/counter, serial interface (uart, sio, i 2 c), a 10-bit ad converter and two clock generators on chip. product no. flash (program area) flash (data area) ram package emulation chip TMP86FM48ug lqfp64-p-1010-0.50e TMP86FM48fg 32256 8 bits 512 8 bits 2.0 k 8 bits qfp64-p-1414-0.80c tmp86c948xb features ? 8-bit single chip microc omputer tlcs-870/c series ? instruction execution time: 0.25 s (at 16 mhz) 122 s (at 32.768 khz) ? 132 types and 731 basic instructions ? 20 interrupt sources (external: 5, internal: 15) ? input/output ports (54 pins) ? 16-bit timer counter: 2 ch ? timer, event counter, pulse width measurement, external trigger timer, window, ppg output modes ? 8-bit timer counter: 2 ch ? timer, event counter, pwm output, programmable divider output, capture modes ? time base timer ? divider output function ? watchdog timer ? interrupt source/internal rese t generate (programmable) lqfp64-p-1010-0.50e TMP86FM48ug qfp64-p-1414-0.80c TMP86FM48fg ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standar ds of safety in making a safe design for the entire system, a nd to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specificati ons. also, please keep in mind the precautions and conditions set forth in the "handlin g guide for semiconductor devices," or "toshiba semiconductor reliability handbook" etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal equipment, office equipment, measuring equipmen t, industrial robotics, domestic applianc es, etc.). these toshiba products are neither intended nor warranted for usage in equipment that require s extraordinarily high quality and/or reliability or a malfun ction or failure of which may cause loss of human life or bodily inju ry ("unintended usage"). unintended usage include atomic energy control instruments, airplane or spaceshi p instruments, transportation instruments, traffic signal instruments, combustion cont rol instruments, medical instruments, all types of safety devices , etc. unintended usage of toshiba products listed in this documen t shall be made at the customer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is pres ented only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by implication or otherwise under any patents or othe r rights of toshiba or the third parties. 070122_c ? the products described in this document are subjec t to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/handling precautions. 030619_s
TMP86FM48 2007-08-24 86fm48-2 ? serial interface ? uart/sio: 1ch ? sio: 1ch ? i 2 c bus: 1ch ? 10-bit successive approximation type ad converter ? analog input: 16 ch ? four key-on wake-up pins ? dual clock operation ? single/dual-clock mode ? nine power saving operating modes ? stop mode: oscillation stops. battery/capacitor back-up. port output hold/high-impedance. ? slow 1, 2 mode: low-power consumption oper ation using low-frequency clock (32.768 khz) ? idle 0 mode: cpu stops, and peripherals operate using high-frequency clock of time-base-timer. release by falling edge of tbtcr < tbtck > setting. ? idle 1 mode: cpu stops, and peripherals operate using high-frequency clock. release by interruputs. ? idle 2 mode: cpu stops, and peripherals operate using high and low-frequency clock. release by interruputs. ? sleep 0 mode: cpu stops, and peripherals operate using low-frequency clock of time-base-timer. release by falling edge of tbtcr < tbtck > setting. ? sleep 1 mode: cpu stops, and peripherals operate using low-frequency clock. release by interrupts. ? sleep 2 mode: cpu stops, and peripherals oper ate using high- and lo w-frequency clock. release by interrupts. ? wide operating voltage: 1.8 to 3.6 v at 8 mhz/32.768 khz 2.7 to 3.6 v at 16 mhz/32.768 khz
TMP86FM48 2007-08-24 86fm48-3 pin assignments (top view) lqfp64-p-1010-0.50e qfp64-p-1414-0.80c 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p80 p81 p82 p83 p84 p85 p86 p87 p30 p31 p32 p33 p34 p35 p36 p37 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p77(ain17) p76 (ain16) p75 (ain15) p74 (ain14) p73 (ain13) p72 (ain12) p71 (ain11) p70 (ain10) p67 (ain07/stop3) p66 (ain06/stop2) p65 (ain05/stop1) p64 (ain04/stop0) p63 (ain03) p62 (ain02) p61 (ain01) p60 (ain00) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a vdd varef a vss/vass boot p52 p51 ( dvo /sda) p50 ( ppg /scl) p07 ( sck1 ) p06 (so1/txd) p05 (si1/rxd) p04 p03 (tc2) p02 (int2) p01 (int1) p00 ( int0 ) p17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss xin xout test vdd (xtin) p21 (xtout) p22 ( stop / int5 ) p20 (so2) p10 (si2) p11 ( sck2 ) p12 ( pwm5 / pdo5 /tc5) p13 (int3/tc3) p14 (tc1) p15 p16 reset
TMP86FM48 2007-08-24 86fm48-4 block diagram analog reference pins xin xout power supply resonator connecting p ins vdd vss address/data bus system control circuit standby control circuit (key-on wake-up) timing generator high frequency low frequency clock generator tlcs-870/c cpu data memory (ram) program memory (flash) interrupt controller i/o ports i/o ports avdd varef avss/vass p67 (ain07) p60 (ain00) p2 10-bit ad converter p6 p0 sio2 uart address/data bus to p3 reset input reset test pin test tc3 8-bit timer/counter tc5 tc1 16-bit timer/counter time base timer watchdog timer p07 to p00 p22 to p20 tc2 p1 p17 to p10 sio1 sio p5 p52 to p50 p37 to p30 i/o ports i2c p8 p87 to p80 p7 p77 (ain17) p70 (ain10) to data memory (flash)
TMP86FM48 2007-08-24 86fm48-5 pin functions (1/2) pin name input/output functions p07 ( sck1 ) i/o (i/o) serial clock input/output 1 p06 (txd, so1) i/o (output) uart data output, serial data output 1 p05 (rxd, si1) i/o (input) uart data input, serial data input 1 p04 i/o p03 (tc2) i/o (input) timer counter 2 input p02 (int2) i/o (input) external interrupt 2 input p01 (int1) i/o (input) external interrupt 1 input p00 ( int0 ) i/o (input) 8-bit input/output port with latch. when used as a serial interface output or uart output, respective output latch (p0dr) should be set to ?1?. when used as an input port, an serial interface input, uart input, timer counter input or an external interrupt input, respective output control (p0outcr) should be cleared to ?0? after setting p0dr to ?1?. external interrupt 0 input p17 i/o p16 i/o p15 (tc1) i/o (input) timer counter 1 input p14 (tc3,int3) i/o (input) timer counter 3 input, external interrupt 3 input p13 ( pwm5 , pdo5 , tc5) i/o (i/o) pwm5 output, pdo5 output, timer/counter 5 input p12 ( sck2 ) i/o (i/o) serial clock input/output 2 p11 (si2) i/o (input) serial data input 2 p10 (so2) i/o (output) 8-bit input/output port with latch. when used as a timer/counter output or serial interface output, respective output latch (p1dr) should be set to ?1?. when used as an input port, a timer counter input, an external interrupt input or serial interface input, respective output control (p1outcr) should be cleared to ?0? after setting p1dr to ?1?. serial data output 2 p22 (xtout) i/o (output) p21 (xtin) i/o (input) resonator connecting pins (32.768 khz) for inputting external clock, xtin is used and xtout is opened. p20 ( int5 , stop ) i/o (input) 3-bit input/output port with latch. when used as an input port or an external interrupt input, respective output control (p2outcr) should be cleared to ?0? after setting output latch (p2dr) to ?1?. external interrupt input 5 or stop mode release signal input p37 to p30 i/o 8-bit input/output port with latch (n-ch high-current output). when used as an input port, respective output control (p3outcr) should be cleared to ?0? after setting output latch (p3dr) to ?1?. p52 i/o p51 ( dvo , sda) i/o (output,i/o) divider output/i 2 c bus serial data input/output p50 ( ppg , scl) i/o (output,i/o) 3-bit input/output port with latch (n-ch high-current output). when used as an input port or i 2 c bus interface input/output, respective output control (p5outcr) should be cleared to ?0? after setting output latch (p5dr) to ?1?. when used as a ppg output or divider output, respective p5dr should be set to ?1?. ppg output/i 2 c bus serial clock input/output p67 (ain07, stop3) i/o (input) stop 3 input p66 (ain06, stop2) i/o (input) stop 2 input p65 (ain05, stop1) i/o (input) stop 1 input p64 (ain04, stop0) i/o (input) stop 0 input p63 (ain03) i/o (input) p62 (ain02) i/o (input) p61 (ain01) i/o (input) p60 (ain00) i/o (input) 8-bit programmable input/output port (tri-state). each bit of this port can be individually configured as an input or an output under software control. when used as an input port, respective input/output control (p6cr1) should be cleared to ?0? after setting input control (p6cr2) to ?1?. when used as an analog input or key on wake up input, respective p6cr1 should be cleared to ?0? after clearing p6cr2 to ?0?. when used as a key on wake up input, stopcr should be set to ?1?. (i = 0 to 3) ad converter analog inputs
TMP86FM48 2007-08-24 86fm48-6 pin functions (2/2) pin name input/output functions pin name p77 (ain17) i/o (input) p76 (ain16) i/o (input) p75 (ain15) i/o (input) p74 (ain14) i/o (input) p73 (ain13) i/o (input) p72 (ain12) i/o (input) p71 (ain11) i/o (input) p70 (ain10) i/o (input) 8-bit programmable input/output port (tri-state). each bit of this port can be individually configured as an input or an output under software control. when used as an input port, respective input/output control (p7cr1) should be cleared to ?0? after setting input control (p7cr2) to ?1?. when used as an analog input, respective p7cr1 should be cleared to ?0? after clearing p7cr2 to ?0?. ad converter analog inputs p87 to p80 i/o 8-bit input/output port with latch (n-ch high-current output). when used as an input port, respective output control (p8outcr) should be cleared to ?0? after setting output latch (p8dr) to ?1?. xin, xout input output resonator connecting pins for high-frequency clock. for inputting external clock, xin is used and xout is opened. reset input reset signal input test input test pin for out-going test. be fixed to low. boot input serial prom mode control input. when wr iting to flash memory, boot pin should be fixed to high level. vdd, vss power supply for operation varef analog reference voltage for ad conversion avdd ad circuit power supply avss/vass power supply ad circuit power supply/analog re ference gnd for ad conversion
TMP86FM48 2007-08-24 86fm48-7 operational description 1. cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 memory address map the TMP86FM48 memory consists of 5 bl ocks: flash memory, boot rom, ram, dbr (data buffer register) and sfr (special function register). they are all mapped in 64-kbyte address space. figure 1.1.1 shows the tmp86f m48 memory address map. the general-purpose registers are not assigned to the ram a ddress space. figure 1.1.1 memory address maps 1.2 program memory (flash) the TMP86FM48 has a 32 k 8 bits (address 8000 h to ffff h ) of program memory (flash). the area of 8000h to 81ffh can be used as a 512 8 bits data memory of flash. flash memory: flash memory includes: program memory (the area of 8000 h to 81ff h can be used as data memory.) vector table boot rom: flash writing program ram: random access memory includes: data memory stack sfr: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers interrupt control registers program status word dbr: data buffer register includes: peripheral control registers peripheral status registers vector table for vector call instructions (16 vectors) vector table for interrupts/reset (16 vectors) vector table for interrupts (8 vectors) 0000 h 64 bytes 2048 bytes 128 bytes sfr ram dbr flash memory (program memory) 32176 bytes 32 bytes 32 b y tes 003f h 0040 h 083f h 1f80 h 1fff h 8000 h ffbf h ffc0 h ffdf h ffe0 h ffff h 16 bytes ffb0 h 2048 bytes boot rom 3800 h 3fff h 512 b y tes 81ff h 8200 h flash memory (data memory)
TMP86FM48 2007-08-24 86fm48-8 1.3 data memory (ram) the TMP86FM48 has 2048 bytes of in ternal ram. the first 192 bytes (0040 h to 00ff h ) of the internal ram are located in the direct area; instructions with shorten operations are available against such an area. the data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. example: clears ram to ?00h?. ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 07ffh ; sramclr: ld (hl), a inc hl dec bc jrs f, sramclr
TMP86FM48 2007-08-24 86fm48-9 1.4 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 1.4.1 system clock control 1.4.1 clock generator the clock generator generates the basic clock which provides the system clocks supplied to the cpu core and peripheral hardware. it co ntains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) and low-frequency (fs) clocks can easily be obtained by connecting a resonator between the xin/xout and xtin/xto ut pins respectively. clock input from an external oscillator is also possible. in th is case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. figure 1.4.2 examples of resonator connection note: the function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and wa tchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. 0036 h timing generator control register 0038 h fc xout xin system clocks timing generator high-frequency clock oscillator standby controller clock generator control system control registers 0039 h syscr2 syscr1 tbtcr clock generator fs xtout xtin low-frequency clock oscillator xout xin (open) xout xin (a) crystal/ceramic resonator (b) external oscillator high-frequency clock xtout xtin (open) xtout xtin (c) crystal (d) external oscillator low-frequency clock
TMP86FM48 2007-08-24 86fm48-10 1.4.2 timing generator the timing generator generates the various system clocks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. a. generation of main system clock b. generation of divider output ( dvo ) pulses c. generation of source cl ocks for time base timer d. generation of source clocks for watchdog timer e. generation of internal source clocks for timer/counters and serial interface f. generation of warm-up cloc ks for releasing stop mode (1) configuration of timing generator the timing generator consists of a 2-stag e prescaler, a 21-stage divider, a main system clock generator, an d machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, tbtcr, that is shown in figure 1.4.4. as reset and stop mode started/canceled, the prescaler and the divider are cleared to ?0?. figure 1.4.3 configurat ion of timing generator multiplexer multi- plexer fc/4 fc or fs low-frequency clock fs high-frequency clock fc watchdog timer machine cycle counters main system clock generator syscr2 tbtcr warm-up controller timer/counters 1 time base timer 1 divider output circuit serial interface 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 s y b a s b0 b1 a 1 y1 a 0 y0 divide r timer/counters 2 timer/counters 3 timer/counters 5
TMP86FM48 2007-08-24 86fm48-11 7 6 5 4 3 2 1 0 tbtcr (0036 h ) (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [h z], fc: low-frequency clock [hz], * : don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal 1/ 2 mode, the dv7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. figure 1.4.4 timing generator control register (2) machine cycle instruction execution and peripheral hardware operation are synchronized with the main system clock. the minimum instruction execution unit is called an ?machine cycle?. there are a total of 10 different types of instructions for the tlcs-870/c series: ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 1.4.5 machine cycle 1/fc or 1/fs [s] main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0
TMP86FM48 2007-08-24 86fm48-12 1.4.3 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. there are two operating modes: single-clock and dual-clock. these modes are controlled by the system control registers (syscr1 and syscr2). figure 1.4.6 shows the operating mode transition diagram and figure 1.4.7 shows the system control registers. (1) single-clock mode only the oscillation circuit for the high-frequency clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports. the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. a. normal1 mode in this mode, both the cpu core and on-chip peripherals operate using the high-frequency clock. the TMP86FM48 is placed in this mode after reset. b. idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chi p peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2, and idle1 mode is released to normal1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. when the imf (interrupt master enable flag) is ?1? (interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. when the imf is ?0? (interrupt disable), the execution will resume with the instruction which follows the idle1 mode start instruction. c. idle0 mode in this mode, all the circuit, except oscillator and the time-base-timer, stops operation. this mode is enabled by setting ?1? on bit tghalt on the system control register 2 (syscr2). when idle0 mode starts, the cpu stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon detecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the cloc k to all peripheral circuits. when returned from idle0 mode, the cpu restarts operating, entering normal1 mode back again. idle0 mode is entered and returned regardless of how tbtcr is set. when imf = ?1?, ef7 (tbt interrupt individual enable flag) = ?1?, and tbtcr = ?1?, interrupt processing is performed. when idle0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to normal1 mode.
TMP86FM48 2007-08-24 86fm48-13 (2) dual-clock mode both the high-frequency and low-frequency oscillation circuits are used in this mode. p21 (xtin) and p22 (xtout) pins cannot be used as input/output ports. the main system clock is obtained from the high-frequency clock in normal2 and idle2 modes, and is obtained from the low-frequency clock in slow and sleep modes. the machine cycle time is 4/fc [s] in the no rmal2 and idle2 modes, and 4/fs [s] (122 s at fs = 32.768 khz) in the slow and sleep modes. the tlcs-870/c is placed in the single-clock mode during reset. to use the dual-clock mode, the low-frequency oscillator should be turned on at the start of a program. a. normal2 mode in this mode, the cpu core operates with the high-frequency clock. on-chip peripherals operate using the high-frequency clock and/or low-frequency clock. b. slow2 mode in this mode, the cpu core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. on-chip peripherals are triggered by the low-frequency clock. as the sysck on syscr2 becomes ?0?, the hardware changes into normal2 mode. as the xen on syscr2 becomes ?0?, the hardware ch anges into slow1 mode. do not clear xten to ?0? during slow2 mode. c. slow1 mode this mode can be used to reduce power- consumption by turning off oscillation of the high-frequency clock. the cpu core and on-chip peripherals operate using the low-frequency clock. switching back and forth between slow1 and slow2 modes are performed by xen bit on the system cont rol register 2 (syscr2). in slow1 and sleep mode, the input clock to the 1st stage of the divide r is stopped; output from the 1st to 6th stages is also stopped. d. idle2 mode in this mode, the internal oscillation circuit remain active. the cpu and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high-frequency clock and/or the low-frequency clock). starting and releasing of idle2 mode are the same as for idle1 mode, except that operation returns to normal2 mode. e. sleep1 mode in this mode, the internal oscillation circuit of the low-frequency clock remains active. the cpu, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (operate using the low-frequency clock). starting and releasing of sleep mode are the same as for idle1 mode, except that operation returns to slow mode. in slow and sleep mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped.
TMP86FM48 2007-08-24 86fm48-14 f. sleep2 mode the sleep2 mode is the idle mode corresponding to the slow2 mode. the status under the sleep2 mode is same as that under the sleep1 mode, except for the oscillation circuit of the high-frequency clock. g. sleep0 mode in this mode, all the circuit, except oscillator and the time-base-timer, stops operation. this mode is enabled by setting ?1? on bit tghalt on the system control register 2 (syscr2). when sleep0 mode starts, the cpu stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon detecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the cloc k to all peripheral circuits. when returned from sleep0 mode, the cpu restarts operating, entering slow1 mode back again. sleep0 mode is entered and returned regardless of how tbtcr is set. when imf = ?1?, ef7 (tbt interrupt individual enable flag) = ?1?, and tbtcr = ?1?, interrupt processing is performed. when sleep0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to slow1 mode. (3) stop mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with a lowest power consumption during stop mode. stop mode is started by the system contro l register 1 (syscr1), and stop mode is released by a inputting (either level-sensit ive or edge-sensitive can be programmably selected) to the stop pin or key on wake up pin input which is enabled by stopcr. after the warm-up period is completed, th e execution resumes with the instruction which follows the stop mode start instruction. note 1: when the idle0/1/2 and sl eep0/1/2 modes are started with the eepcr = ?0?, the cpu wait period for stabilizing of the power supply of flash control circuit is ex ecuted after being released from these mode. note 2: when the stop mode is started with the eepcr = ?1?, the cpu wait period for stablizing of the power supply of flash control circuit is executed after in the stop warm-up time.
TMP86FM48 2007-08-24 86fm48-15 note 1: normal1 and normal2 modes are generically called normal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by falling edge of tbtcr setting. oscillator operating mode high frequency low frequency cpu core tbt other peripherals machine cycle time reset reset reset reset normal1 operate idle1 operate 4/fc [s] idle0 oscillation operate single clock stop stop stop halt halt halt ? normal2 operate with high frequency idle2 halt 4/fc [s] slow2 operate with low frequency sleep2 oscillation halt slow1 operate with low frequency sleep1 operate 4/fs [s] sleep0 oscillation operate dual clock stop stop stop halt halt halt ? figure 1.4.6 operating mode transition diagram (b) dual clock mode idle0 mode normal1 mode idle1 mode stop syscr2 = ?1? stop pin input interrupt (a) single clock mode (note 2) syscr2 = ?1? reset syscr1 = ?1? normal2 mode idle2 mode syscr2 = ?1? stop pin input interrupt syscr2 = ?1? syscr2 = ?0? syscr1 = ?1? slow2 mode sleep2 mode syscr2 = ?1? interrupt syscr2 = ?1? syscr2 = ?0? slow1 mode sleep1 mode syscr2 = ?1? syscr2 = ?0? syscr2 = ?1? syscr1 = ?1? stop pin input interrupt sleep0 mode (note 2) syscr2 = ?1? reset release
TMP86FM48 2007-08-24 86fm48-16 system control register 1 7 6 5 4 3 2 1 0 syscr1 (0038 h ) stop relm retm outen wut (initial value: 0000 00 ** ) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) relm release method for stop pin (p20) 0: edge-sensitive release 1: level-sensitive release retm operating mode after stop mode 0: return to normal1/2 mode 1: return to slow1 mode outen port output during stop mode 0: high impedance 1: output kept return to normal mode return to slow mode wut warm-up time at releasing stop mode (note 8) 00 01 10 11 3 2 16 /fc 2 16 /fc 3 2 14 /fc 2 14 /fc + (2 10 /fc) + (2 10 /fc) + (2 10 /fc) + (2 10 /fc) 3 2 13 /fs 2 13 /fs 3 2 6 /fs 2 6 /fs + (2 3 /fs) + (2 3 /fs) + (2 3 /fs) + (2 3 /fs) r/w note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [h z], fs: low-frequency clock [hz], *: don?t care note 4: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause interrupt request on account of falling edge. note 6: when the key-on wake-up input (stop0 to stop3) is used, relm should be set to ?1?. note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: when the stop mode is started with the eepcr = ?1?, the cpu wait period for stabilizing of the power supply of flash control circuit is executed after in the stop warm-up time. (the cpu wait period for flash is shown in parentheses) system control register 2 7 6 5 4 3 2 1 0 syscr2 (0039 h ) xen xten sysck idle tghalt (initial value: 1000 * 0 ** ) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/main system clock monitor (read) 0: high-frequency clock 1: low-frequency clock idle cpu and watchdog timer control (idle1/2, sleep1/2 mode) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1/2, sleep1/2 mode) tghalt tg control (idle0, sleep0 mode) 0: feeding clock to all peripherals from tg 1: stop feeding clock to peripherals except tbt from tg. (start idle0, sleep0 mode) r/w note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: * : don?t care, tg: timing generator note 3: bits 3, 1and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to norm al1/slow1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr. note 6: when idle1/2 or sleep1/2 mode is rel eased, idle is automatically cleared to ?0?. note 7: when idle0 or sleep0 mode is released, tghalt is automatically cleared to ?0?. note 8: before setting tghalt to ?1?, be sure to stop peripherals. if peripherals are not stopped, the interrupt latch of peripherals may be set after idle0 or sleep0 mode is released. figure 1.4.7 system control registers
TMP86FM48 2007-08-24 86fm48-17 1.4.4 operating mode control (1) stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wake-up input (stop0 to stop3) which is controlled by the stop mode release control register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 to ?1?. during stop mode, the following status is maintained. a. oscillations are turned off, and all internal operations are halted. b. the data memory, registers, the program status word and port output latches are all held in the status in effect before stop mode was entered. c. the prescaler and the divider of the timing generator are cleared to ?0?. d. the program counter holds the address 2 ahead of the instruction (e.g. [set (syscr1).7]) which started stop mode. stop mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the syscr1. do not use any stopx (x: 0 to 3) pin input for releasing stop mode in edge-sensitive mode. when the stop mode is started with the eepcr = ?1?, the cpu wait period for stabilizing of the power supply of flash control circuit is executed after in the stop warming-up time. note 1: the stop mode can be released by either the stop or key-on wake-up pin (stop0 to stop3). however, because the stop pin is different from the key-on wake-up and can not inhibit the release input, the stop pin must be used for releasing stop mode. note 2: during stop period (from start of stop mode to end of warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to ?1? and interrupts may be accepted immediately after stop mode is released. before starting stop mode, therefore, disable interrupts. al so, before enabling interrupts after stop mode is released, clear unnec essary interrupt latches. a. level-sensitive release mode (relm = ?1?) in this mode, stop mode is released by setting the stop pin high or setting the stopx (x: 0 to 3) pin input which is enabled by stopcr. this mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. when the stop pin input is high, executing an instruction which starts stop mode will not place in stop mode but in stead will immediately start the release sequence (warm-up). thus, to start stop mode in the level-sensitive release mode, it is necessary for the program to first confirm that the stop pin input is low. the following two methods can be used for confirmation. a. testing a port p20. b. using an external interrupt input int5 ( int5 is a falling edge-sensitive input).
TMP86FM48 2007-08-24 86fm48-18 example 1: starting stop mode from normal mode by testing a port p20. ld (syscr1), 01010000b ; sets up the level-sensitive release mode sstoph: test (p2prd). 0 ; wait until the stop pin input goes low level jrs f, sstoph set (syscr1).7 ; starts stop mode example 2: starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if port p20 is at high jrs f, sint5 ld (syscr1), 01010000b ; sets up the level-sensitive release mode. set (syscr1). 7 ; starts stop mode sint5: reti note: when the stop mode is started with the eepcr = ?1?, the cpu wait for stabilizing of the power supply of flash control circ uit is executed after in the stop warming-up time. figure 1.4.8 level-sensitive release mode note 1: even if the stop pin input is low after warming up start, the stop mode is not restarted. note 2: in this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. b. edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in applications where a relatively short program is executed repeatedly at periodic intervals. this peri odic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stopx (x: 0 to 3) pin input for releasing stop mode in edge-sensitive release mode. example: starting stop mode from normal mode ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode stop warm-up normal o p eration stop operation stop pin xout pin normal operation stop mode is released by the hardware. a lways released if the stop pin input is high. cpu wait period only when eepcr is ?1?. (the cpu wait period is added.)
TMP86FM48 2007-08-24 86fm48-19 note: when the stop mode is started with the eepcr = ?1?, the cpu wait for stabilizing of the power supply of flash control ci rcuit is executed after in the stop warm-up time. figure 1.4.9 edge-se nsitive release mode stop mode is released by the following sequence. a. in the dual-clock mode, when returning to normal2, both the high-frequency and low-frequency clock oscillators are turned on; when returning to slow1 mode, only the low-frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. b. a stop warm-up period is inserted to allow oscillation time to stabilize. during stop warm-up, all internal operations remain halted. four different stop warm-up times can be selected with the syscr1 in accordance with the resonator characteristics. c. when the eepcr is ?1?, the cpu wait period is inserted to stabilize the power supply of flash control circuit. during cpu wait, though cpu operations remain halted, the peripheral function operation is resumed, and the counting of the timing generator is restarted. after the cpu wait is finished, normal oper ation resumes with the instruction following the stop mode start instruction. d. when the eepcr is ?0?, normal operation resumes with the instruction following the stop mode start instruction after the stop warm-up. note 1: when the stop mode is released, the start is made after the prescaler and the divider of the timing ge nerator are cleared to ?0?. note 2: stop mode can also be released by inputting low level on the reset pin, which immediately performs the normal reset operation. note 3: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be ?h? level, rising together with the power supply voltage. in this case, if an external time constant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply voltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-inverting high-lev el input voltage (hysteresis input). stop mode is released by the hardware at the rising edge of stop pin input. v ih stop warm-up normal operation stop mode started by the program. stop pin xout pin normal operation stop operation stop operation cpu wait period only when eepcr is ?1?. (the cpu wait period is added.)
TMP86FM48 2007-08-24 86fm48-20 table 1.4.1 warm-up time example (at fc = 16.0 mhz, fs = 32.768 khz) warm-up time [ms] (note 2) wut return to normal mode return to slow mode 00 12.288 + (0.064) 750 + (0.244) 01 4.096 + (0.064) 250 + (0.244) 10 3.072 + (0.064) 5.85 + (0.244) 11 1.024 + (0.064) 1.95 + (0.244) note 1: the warm-up time is obtained by dividing the basic clock by the divider: therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when stop mode is released. thus, the warm-up time must be considered an approximate value. note 2: the cpu wait period for flash is shown in parentheses.
TMP86FM48 2007-08-24 86fm48-21 figure 1.4.10 stop mode st art/release (when eepcr = ?0?) oscillator circuit turn on halt a + 3 a + 2 (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) set (syscr1).7 n n + 1 n + 2 n + 3 n + 4 0 turn off main system clock program counte r instruction execution divide r stop warm up (b) stop mode release a + 6 a + 5 a + 4 instruction address a + 2 instruction address a + 3 instruction address a + 4 3 2 1 0 count up 0 halt turn off turn on a + 3 stop pin input oscillator circuit main system clock program counte r instruction execution divider
TMP86FM48 2007-08-24 86fm48-22 figure 1.4.11 stop mode st art/release (when eepcr = ?1?) oscillator circuit turn on halt a + 3 a + 2 (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) set (syscr1).7 n n + 1 n + 2 n + 3 n + 4 0 turn off main system clock program counte r instruction execution divide r stop warm up (b) stop mode release a + 5 a + 4 instruction address a + 2 instruction address a + 3 m + 1 m 1 0 count up 0 halt turn off turn on a + 3 stop pin input oscillator circuit main system clock program counte r instruction execution divide r cpu wait m ? 1 the counting of divider is restarted.
TMP86FM48 2007-08-24 86fm48-23 (2) idle1/2 mode, sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. a. operation of the cpu and watchdog ti mer (wdt) is halted. on-chip peripherals continue to operate. b. the data memory, cpu registers, progra m status word and port output latches are all held in the status in effect before these modes were entered. c. the program counter holds the address 2 ahead of the instruction which starts these modes. note 1: eepcr is a bit1 in eepcr, which is a control bit of the power supply circuit for flash. note 2: during cpu wait, though cpu operations remain halted, the peripheral function operation is resumed. therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the cpu wait is finished. figure 1.4.12 idle1/2, sleep1/2 modes reset no no yes starting idle1/2 and sleep1/2 modes by instruction cpu, wdt are halted interrupt processing execution of the instruction which follows the idle1/2 and sleep1/2 modes start instruction (normal release mode) no yes (interrupt release mode) reset input interru p t re q uest imf = 1 yes eepcr cpu wait ?1? ?0?
TMP86FM48 2007-08-24 86fm48-24 ? start the idle1/2 and sleep1/2 modes when idle1/2 and sleep1/2 modes st art, set syscr2 to ?1?. ? release the idle1/2 and sleep1/2 modes idle1/2 and sleep1/2 modes include a no rmal release mode and an interrupt release mode. these modes are selected by interrupt master enable flag (imf). after releasing idle1/2 and sleep1/2 modes, the syscr2 is automatically cleared to ?0? and the oper ation mode is returned to the mode preceding idle1/2 and sleep1/2 modes. when the idle1/2 and sleep1/2 modes are started with the eepcr = ?0?, the cpu wait period fo r stabilizing of the power supply of flash control circuit is added before the operation mode is returned to the preceding modes. the cpu wait time of idle1/2 is 2 10 /fc [s] and that of sleep1/2 mode is 2 3 /fs [s]. idle1/2 and sleep1/2 modes can also be re leased by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. note: during cpu wait, though cpu operatio ns remain halted, but the peripheral function operation is resumed. theref ore in this time, though the interrupt latch might be set, interrupt operation is not executed until the cpu wait is finished. (a) normal rele ase mode (imf = ?0?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (ef). after the interrupt is generated, the program operation is resumed from the instruction following the idle1/2 and sleep1/2 modes start instruction. normally, the interrupt latches (il) of the interrupt source used for releasing must be cleared to ?0? by load instructions. (b) interrupt release mode (imf = ?1?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (ef). after the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts idle1/2 and sleep1/2 modes. note: when a watchdog timer interrupts is generated immediately before idle1/2 and sleep1/2 mode are started, the watchdog timer interrupt will be processed but idle1/2 and sleep1 /2 mode will not be started.
TMP86FM48 2007-08-24 86fm48-25 figure 1.4.13 idle1/2, sleep1/2 mode start/release main system clock (a) idle1/2, sleep1/2 mode start (example: starting with the set instruction located at address a) a + 2 set (syscr2).4 operate a + 3 halt a + 4 instruction address a + 2 operate a + 3 halt halt halt halt a + 3 operate acceptance of interrupt (1) normal release mode (eepcr = ?1?) (2) interrupt release mode (b) idle1/2, sleep1/2 mode release (eepcr = ?1?) interrupt request program counte r instruction execution watchdog time r main system clock interrupt request program counte r watchdog time r main system clock interrupt request program counte r watchdog time r instruction execution instruction execution
TMP86FM48 2007-08-24 86fm48-26 (3) idle0, sleep0 mode (idle0, sleep0) idle0 and sleep0 modes are controlled by th e system control register 2 (syscr2) and the time base timer control register (tbt cr). the following status is maintained during idle0 and sleep0 modes. a. timing generator stops feeding clock to peripherals except tbt. b. the data memory, cpu registers, progra m status word and port output latches are all held in the status in effect be fore idle0 and sleep0 modes were entered. c. the program counter holds the address 2 ahead of the instruction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 m ode, be sure to stop (disable) periperals. figure 1.4.14 idle0, sleep0 mode reset ?0? no yes starting idle0, sleep0 mode by instruction cpu, wdt are halted interrupt processing execution of the instruction which follows the idle0, sleep0 mode start instruction (normal release mode) no ?1? (interrupt release mode) reset input tbt source clock falling edge yes imf yes ?0? no ?1? tbtcr tbt interrupt enable stopping peripherals by instruction cpu wait eepcr ?0? ?1? note 1: eepcr is a bit1 in eepcr, which is a control bit of the power supply circuit for flash. note 2: during cpu wait, though cpu operations remain halted, but the peripheral function operation is resumed. therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the cpu wait is finished.
TMP86FM48 2007-08-24 86fm48-27 ? start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. when idle0 and sleep0 modes start, set syscr2 to ?1?. ? release the idle0 and sleep modes idle0 and sleep0 modes include a normal release mode and an interrupt release mode. these modes are selected by interrupt master flag (imf), individual interrupt enable-flag (ef7) for inttbt and tbtcr. after releasing idle0 and sleep0 modes, the syscr2 is automatically cleared to ?0? and the oper ation mode is returned to the mode preceding idle0 and sleep0 modes. before starting the idle0 or sleep0 mode, when the tbtcr is set to ?1?, inttbt interrupt latch is set to ?1?. when the idle0 and sleep0 modes are started with the eepcr = ?0?, the cpu wait period for stabilizing of the power supply of flash control circuit is added before the operation mode is returned to the preceding modes. the cpu wait time of idle0 is 2 10 /fc [s] and that of sleep0 mode is 2 3 /fs [s]. idle0 and sleep0 modes can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. note 1: idle0 and sleep0 modes st art/release without reference to tbtcr setting. note 2: during cpu wait, though cpu opera tions remain halted, but the peripheral function operation is resumed. therefore in this time, though the interrupt latch might be set, interrupt operation is not ex ecuted until the cpu wait is finished. a. normal release mode (imf?ef7?tbtcr = ?0?) idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr. after the falling edge is detected, the program operation is resumed from the instruction following the idle0 and sleep0 modes start instruction. b. interrupt release mode (imf?ef7?tbtcr = ?1?) idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr and in ttbt interrupt processing is started. note 1: because returning from idle0, sleep0 to normal1, slow1 is executed by the asynchronous internal clock, the period of idle0, sleep0 mode might be the shorter than the period setting by tbtcr. note 2: when a watchdog timer interrupt is generated immediately before idle0/sleep0 mode is started, th e watchdog timer interrupt will be processed but idle0/sleep0 mode will not be started.
TMP86FM48 2007-08-24 86fm48-28 figure 1.4.15 idle0, sleep0 mode start/release main system clock (a) idle0, sleep0 mode start (example: starting with the set instruction located at address a) a + 2 set (syscr2).2 operate a + 3 halt a + 4 instruction address a + 2 operate a + 3 halt halt halt halt a + 3 operate acceptance of interrupt (1) normal release mode (eepcr = ?1?) (2) interrupt release mode (b) idle0, sleep0 mode release (eepcr = ?1?) interrupt request program counte r instruction execution watchdog time r main system clock tbt clock program counte r instruction execution watchdog time r main system clock tbt clock program counte r instruction execution watchdog time r
TMP86FM48 2007-08-24 86fm48-29 (4) slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter (tc2). a. switching from normal2 mode to slow1 mode first, set syscr2 to switch the main system clock to the low-frequency clock for slow2 mode. next, clear syscr2 to turn off high-frequency oscillation. note: the high-frequency clock oscillation can be continued to return quickly to normal2 mode. but starting stop mode while slow mode, the high-frequency oscillation must be stopped. when the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. the timer/counter 2 (tc2) can conveniently be used to confirm that low-frequency clock oscillation has stabilized. example 1: switching from normal2 mode to slow1 mode. set (syscr2). 5 ; syscr2 1 (switches the main system clock to the low-frequency clock for slow2) clr (syscr2). 7 syscr2 0 (turns off high-frequency oscillation) example2: switching to the slow1 mode a fter low-frequency clock has stabilized. set (syscr2). 6 ; syscr2 1 ld (tc2cr), 14h ; sets mode for tc2 ldw (tc2drl), 8000h ; sets warm-up time (depend on oscillator accompanied) di ; imf 0 set (eire). 4 ; enables inttc2 ei ; imf 1 set (tc2cr). 5 ; starts tc2 pinttc2: clr (tc2cr). 5 ; stops tc2 set (syscr2). 5 ; syscr2 1 (switches the main system clock to the low-frequency clock) clr (syscr2). 7 ; syscr2 0 (turns off high-frequency oscillation) reti vinttc2: dw pinttc2 ; inttc2 vector table
TMP86FM48 2007-08-24 86fm48-30 b. switching from slow1 mode to normal2 mode first, set syscr2 to turn on the high-frequency oscillation. when time for stabilization (warm-up) has been take n by the timer/counter 2 (tc2), clear syscr2 to switch the main system clock to the high-frequency clock. note 1: after sysck is cleared to ?0?, exec uting the instructions is continued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. note 2: slow mode can also be released by inputting low level on the reset pin, which immediately performs the reset operation. after reset, the TMP86FM48 is placed in normal1 mode. example: switching from the slow1 mode to the normal2 mode (fc = 16 mhz, warm-up time is = 4.0 ms). set (syscr2). 7 ; syscr2 1 (starts high-frequency oscillation) ld (tc2cr), 10h ; sets mode for tc2 (timer mode, fc for source) ld (tc2drh), 0f8h ; sets warm-up time (depend on oscillator accompanied) di ; imf 0 set (eire). 4 ; enables inttc2 ei ; imf 1 set (tc2cr). 5 ; starts tc2 pinttc2: clr (tc2cr). 5 ; stops tc2 clr (syscr2). 5 ; syscr2 0 (switches the main system clock to the high-frequency clock) reti vinttc2: dw pinttc2 ; inttc2 vector table high-frequency clock low-frequency clock main system clock sysck
TMP86FM48 2007-08-24 86fm48-31 figure 1.4.16 switching between the normal2 and slow modes high-frequency clock low-frequency clock main system clock sysck xen instruction execution (a) switching to the slow mode clr (syscr2).7 set (syscr2).5 normal2 mode set (syscr2).7 (b) switching to the normal2 mode clr (syscr2).5 normal2 mode slow1 mode slow1 mode turn off slow2 mode warm up during slow2 mode high-frequency clock low-frequency clock main system clock sysck xen instruction execution
TMP86FM48 2007-08-24 86fm48-32 1.5 interrupt control circuit the TMP86FM48 has a total (reset is excluded ) of 20 interrupt source: 5 externals and 15 internals. 4 of the internal sources are non-maskable interrupt s, and the rest of them are maskable interrupts. interrupt sources are provided with interrupt la tches (il), which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by the generation of its interrupt request which requests the cpu to accept its interrupts. interrupts are enabled or disabled by software using the interrupt master enable flag (imf) and interrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. table 1.5.1 interrupt sources interrupt factors enable condition interrupt latch vector address priority internal/external (reset) non-maskable ? fffe h high 1 internal intswi (software interrupt) non-maskable ? fffc h 2 internal intundef (executed the undefined instruction interrupt) non-maskable ? fffc h 2 internal intatrap (address trap interrupt) non-maskable il 2 fffa h 2 internal intwdt (watchdog ti mer interrupt) non-maskable il 3 fff8 h 2 external int0 (external interrupt 0) imf?ef 4 = 1 il 4 fff6 h 5 internal inttc1 (tc1 interrupt) imf?ef 5 = 1 il 5 fff4 h 6 external int1 (external interrupt 1) imf?ef 6 = 1 il 6 fff2 h 7 internal inttbt (time base timer interrupt) imf?ef 7 = 1 il 7 fff0 h 8 external int2 (external interrupt 2) imf?ef 8 = 1 il 8 ffee h 9 internal inttc3 (tc3 interrupt) imf?ef 9 = 1 il 9 ffec h 10 internal intsio1 (serial interface 1 interrupt) imf?ef 10 = 1il 10 ffea h 11 internal intsio2 (serial interface 2 interrupt) imf?ef 11 = 1il 11 ffe8 h 12 internal inttc5 (tc5 interrupt) imf?ef 12 = 1il 12 ffe6 h 13 external int3 (external interrupt 3) imf?ef 13 = 1il 13 ffe4 h 14 internal intadc (ad converter interrupt) imf?ef 14 = 1il 14 ffe2 h 15 reserved imf?ef 15 = 1il 15 ffe0 h 16 reserved imf?ef 16 = 1il 16 ffbe h 17 internal intsbi (serial bus interface interrupt) imf?ef 17 = 1il 17 ffbc h 18 internal intrxd (uart received interrupt) imf?ef 18 = 1il 18 ffba h 19 internal inttxd (uart transmitted interrupt) imf?ef 19 = 1il 19 ffb8 h 20 internal inttc2 (tc2 interrupt) imf?ef 20 = 1il 20 ffb6 h 21 external int5 (external interrupt 5) imf?ef 21 = 1il 21 ffb4 h 22 reserved imf?ef 22 = 1il 22 ffb2 h 23 reserved imf?ef 23 = 1il 23 ffb0 h 24 note 1: to use the watchdog timer interrupt (intwdt) , clear wdtcr1 to ?0? (it is set for the ?reset request? after reset is released). for details, see 2.4 watchdog timer. note 2: to use the address trap interrupt (intatrap) , clear wdtcr1 to ?0? (it is set for the ?reset request? after reset is releas ed). for details, see 2.4.5 address trap.
TMP86FM48 2007-08-24 86fm48-33 figure 1.5.1 interrupt controller block diagram s r instruction which imf to ?0? internal reset write strobe for il 2 imf individual interrupt enable flag priority encoder & vector table address generato r q r s il 23 to il 2 write data interrupt acceptance idle1/2, sleep1/2 mode releease request interrupt request vector table address il 2 s r il 3 q il 4 [di] instru ction ef 23 to ef 4 eintcr external interrupt control re g iste r digital noise reject circuit [reti] instruction during maskable interrupt service [retn] instruction only when imf was set before interrupt was accepted instruction which sets imf to ?1? int5 int3 intadc intsio1 inttc3 intrxd inttc1 edge selction, digital noise reject circuit int2es int2 inttbt edge selction, digital noise reject circuit int1nc, int1es digital noise reject circuit int1 int0 intwdt int0en intswi intundef intatrap q [ei] instruction il 5 il 6 il 7 il 8 il 9 il 10 il 11 il 12 il 13 il 14 il 15 il 16 il 17 il 18 il 19 il 20 il 21 il 22 il 23 intsio2 inttc5 edge selction, digital noise reject circuit int3es inttxd inttc2 22 20 intsbi
TMP86FM48 2007-08-24 86fm48-34 (1) interrupt latches (il 24 to il 2 ) an interrupt latch is provided for each interrupt source, except for a software interrupt. when interrupt request is generated, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. all interrupt latches are initialized to ?0? during reset. the interrupt latches are located on address 002e h, 003c h and 003d h in sfr area. except for il 3 and il 2 , each latch can be cleared to ?0? individually by instruction. (however, the read-modify-write instructions such as bit manipulation or operation instructions cannot be used. interrupt request wo uld be cleared inadequately if interrupt is requested while such instructions are ex ecuted.) thus interrupt request can be canceled/initialized by software. interrupt latches are not set to ?1? by an inst ruction. since interrupt latches can be read, the status for interrupt requests can be monitored by software. note: when manipulating il, clear imf (to disable interrupts) beforehand. example 1: clears interrupt latches di ; imf 0 ld (ile), 11110011b ; il 19 , il 18 0 ldw (ill), 1110100000111111b ; il 12 , il 10 to il 6 0 ei ; imf 1 example 2: reads interrupt latches ld wa, (ill) ; w il h , a il l example 3: tests an interrupt latches test (il).7 ; il 7 = 1 then jump jr f, sset (2) interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). non-maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt master enab le flag (imf) and the individual interrupt enable flags (ef). these registers are located on address 002c h, 003a h and 003b h in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). a. interrupt master enable flag (imf) the interrupt enable register (imf) enables and disables the acceptance of the whole maskable-interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable interrupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrupt acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003a h in sfr), and can be read and written by an instruction. the imf is no rmally set and cleared by [ei] and [di] instruction respectively. during reset, the imf is initialized to ?0?, and maskable interrupts are not accepted until it is set to ?1?.
TMP86FM48 2007-08-24 86fm48-35 b. individual interrupt enable flags (ef 23 to ef 4 ) each of these flags enables and disables the acceptance of its maskable interrupt. setting the corresponding bit of an individu al interrupt enable flag to ?1? enables acceptance of its interrupt, and setting the bit to ?0? disables acceptance. the individual interrupt enable flags (ef 23 to ef 4 ) are located on eire, eirl to eirh (address: 002c h , 003a h to 003b h in sfr), and can be read and written by an instruction. during reset, all the individual interrupt enable flags (ef 23 to ef 4 ) are initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note: before manipulating ef, be sure to clear imf (interrupt disabled). then set imf newly again after operating on the interrupt enables flag (ef). normally, imf is clear to ?0? automatically on service routine. when imf is set to ?1? for using a multiple interrupt on service routine, be sure to process as is the case with ef. example 1: enables interrupts individually and sets imf di ; imf 0 ld (eire), 00001100b ; ef 19 , ef 18 ?1? ldw (eirl), 0110100010100000b ; ef 14 , ef 13 , ef 11 , ef 7 , ef 5 ?1? note: imf is not set. ei ; imf ?1? example 2: c compiler description example unsigned int _io (3ah) eirl; ; / * 3ah shows eirl address * / _di ( ); eirl = 10100000b; _ei ( );
TMP86FM48 2007-08-24 86fm48-36 interrupt latches 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il 15 il 14 il 13 il 12 il 11 il 10 il 9 il 8 il 7 il 6 il 5 il 4 il 3 il 2 il h (003d h ) il l (003c h ) (initial value: 00000000 000000 ** ) 23 22 21 20 19 18 17 16 il 23 il 22 il 21 il 20 il 19 il 18 il 17 il 16 il e (002e h ) (initial value: 00000000) il 23 to il 2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr clears the interrupt request (note 1) (interrupt latch is not set.) r/w note 1: il 2 and il 3 are prohibited from clearing. note 2: when manipulating il, clear im f (to disable interrupts) beforehand. note 3: do not clear il with read-modify-w rite instructions such as bit operations. interrupt enable registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef 15 ef 14 ef 13 ef 12 ef 11 ef 10 ef 9 ef 8 ef 7 ef 6 ef 5 ef 4 imf eir h (003b h ) eir l (003a h ) (initial value: 00000000 00000 *** 0) 23 22 21 20 19 18 17 16 ef 23 ef 22 ef 21 ef 20 ef 19 ef 18 ef 17 ef 16 eir e (002c h ) (initial value: 00000000) ef 23 to ef 4 individual-interrupt enable flag (specified for each bit) 0: disable the acceptance of each maskable interrupt. 1: enable the acceptance of each maskable interrupt. imf interrupt master enable flag 0: disable the acceptance of all maskable interrupts. 1: enable the acceptance of all maskable interrupts. r/w note 1: * : don?t care note 2: when manipulating ef, clear im f (to disable interrupts) beforehand. note 3: do not set imf to 1 simultaneously with ef15 to ef4. figure 1.5.2 interrupt latch (il) , interrupt enable registers (eir) ilh, ill (003c h , 003d h ) eirh, eirl (003a h , 003b h ) ile (002e h ) eire (002c h )
TMP86FM48 2007-08-24 86fm48-37 1.5.1 interrupt sequence an interrupt request, which raised interrupt la tch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruction. interrupt acceptance sequence requires 8-machine cycles (4 s at 8.0 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 1.5.3 shows the timing chart of interrupt acceptance processing. (1) interrupt acceptance proce ssing is packaged as follows. 1. the interrupt master enable flag (imf) is cleared to ?0? in order to disable the acceptance of any following interrupt. 2. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. 3. the contents of the program counter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the stack in sequence of psw + imf, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 3. 4. the entry address (interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. 5. the instruction stored at the entry address of the interrupt service program is executed. note: when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address entry address, b: entry addr ess, c: address which reti instructrion is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s ] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to st art interrupt acceptance processing since its interrupt latch is set. figure 1.5.3 timing chart of interrupt acceptance/return interrupt instruction execute instruction interrupt request interrupt latch (il) imf execute instruction pc sp 1-machine cycle interrupt service task interrupt acceptance execute reti instruction a ? 1 a a + 1 a b b + 1 b + 2 b + 3 c + 2 a a + 1 a + 2 c + 1 n n ? 1 n ? 2 n ? 3 n ? 2 n ? 1 n execute instruction
TMP86FM48 2007-08-24 86fm48-38 example: correspondence between vector table address for inttbt and the entry address of the interrupt service program a maskable interrupt is not accepted until the imf is set to ?1? even if the maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt servic e, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. (2) saving/restoring ge neral-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw, includes imf) are automatically saved on the stack, but the accumulator and others are not. these regi sters are saved by so ftware if necessary. when multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. the following methods are used to save/restore the general-purpose registers. a. using push and pop instructions to save only a specific register, push and pop instructions are available. example: save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return address (example) sp 023a h a 023b sp w sp 023c pc l pc l pc l 023d pc h pc h pc h 023e psw psw psw sp 023f at acceptance of an interrupt at execution of push instructin at execution of pop instructin at execution of an reti instruction 03 h d2 h vector table address fff0 h fff1 h 0f h 06 h entry address d203 h d204 h vecto r interrupt service program
TMP86FM48 2007-08-24 86fm48-39 b. using data transfer instructions to save only a specific register without nested interrupts, data transfer instructions are available. example: save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return figure 1.5.4 saving/restoring general-purpo se registers under interrupt processing (3) interrupt return interrupt return instructions [ reti]/[retn] perform as follows. [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. as for address trap interrupt (intartap), it is required to alter stacked data for program counter (pc) to restarting addr ess, during interrupt service program. otherwise returning interrupt causes inta trap again. when interrupt acceptance processing has complete d, stacked data for pc l and pc h are located on address (sp + 1) and (sp + 2) respectively. note: if [retn] is executed with the abov e data unaltered, the program returns to the address trap area and intatrap occurs again. saving registers restoring registers interrupt service task interrupt acceptance interrupt return main task saving/restoring general-purpose regist ers using push/pop instruction
TMP86FM48 2007-08-24 86fm48-40 example 1: returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return example 2: restarting without returning interrupt (i n this case, psw (includes imf) before interrupt acceptance is discarded.) pintxx inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address note: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return interrupt instruction [r etn] is not utilized during interrupt service program under intatrap (such as example 2). interrupt requests are sampled during th e final cycle of the instruction being executed. thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. note: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task.
TMP86FM48 2007-08-24 86fm48-41 1.5.2 software interrupt (intsw) executing the [swi] instruction generates a software interrupt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the [swi] instruction only for detection of the address error or for debugging. (1) address error detection ff h is read if for some cause such as nois e the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ff h is the swi instruction, so a software interrupt is gene rated and an address error is detected. the address error detection range can be further expanded by writing ff h to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram or sfr areas. (2) debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 1.5.3 undefined instruction interrupt (intundef) taking code which is not defined as authorized instruction for instruction causes intundef. intundef is generated when th e cpu fetches such a code and tries to execute it. intundef is accepted even if non-maskable interrupt is in process. contemporary process is broken and intundef interrupt process starts , soon after it is requested. note: the undefined instruction in terrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 1.5.4 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructions (address trapped area) causes reset-output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary process is broken and intatrap interrupt process starts, soon after it is requested. note: the operating mode under address trappe d, whether to be reset-output or interrupt processing, is selected on watchdog timer control register (wdtcr). 1.5.5 external interrupts the TMP86FM48 has five external interrupt inputs. these inputs are equipped with digital noise reject circuits (p ulse inputs of less than a certain time are eliminated as noise). edge selection is also possible with int1 to int3. int0 /p00 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p00 pin function selection are performed by the external interrupt control register (eintcr).
TMP86FM48 2007-08-24 86fm48-42 table 1.5.2 external interrupts source pin secondary function pin enable conditions edge digital noise reject int0 0 int p00 imf = 1, ef 4 = 1, int0en = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int1 int1 p01 imf?ef 6 = 1 pulses of less than 15/fc or 63/fc [s] are eliminated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 p02 imf?ef 8 = 1 int3 int3 p14/tc3 imf?ef 13 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int5 5 int p20/ stop imf?ef 21 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. note 1: if a noiseless signal is input to the external interrupt pin in the normal 1/2 or idle 1/2 mode, the maximum time from the edge of input signal until the il is set is as follows: (1) int1 pin 55/fc [s] (int1nc = 1), 199/fc [s] (int1nc = 0) (2) int2, int3 pin 31/fc [s] note 2: even if the falling edge of int0 pin input is detected at int0en = 0, the interrupt latch il 4 is not set. note 3: when data changed and did a change of i/o when used external interrupt ports as a normal ports, interrupt request signal occurs incorrectly. handling of prohibition of interrupt enable register (eir) is necessary. note 4: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. external interrupt control register 7 6 5 4 3 2 1 0 eintcr (0037 h ) int1nc int0en int3es int2es int1es (initial value: 00 ** 000 * ) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise int0en p00/ 0 int pin configuration 0: p00 input/output port 1: 0 int pin (port p00 should be set to an input mode) int3es int2es int1es int3 to int1 edge select 0: rising edge 1: falling edge r/w note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched betwe en high and low or when the external interrupt control register (eintcr) is overwritten, the noise cance ller may not operate normally. it is recommended that external interrupts are disabled using the interrupt enable register (eir). figure 1.5.5 external interrupt control register
TMP86FM48 2007-08-24 86fm48-43 1.6 reset circuit the TMP86FM48 has four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock re set. table 1.6.1 shows on-chip hardware initialization by reset action. since the reset circuit has an 11-stage counter fo r generation of flash reset, which is the reset counter for stabilizing of the power suppl y for flash, the reset period is 2 10 /fc [s] (64 s at 16.0 mhz). because the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initia lized when power is turned on, the reset operation occur for the maximum 24/fc [s] (1.5 s at 16.0 mhz). therefore, the maximum reset period is 24/fc [s] + 2 10 /fc [s] (65.5 s at 16.0 mhz). table 1.6.1 shows on-chip hardware initialization by reset action. table 1.6.1 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffe h ) stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized prescaler and divider of timing generator 0 jump status flag (jf) not in itialized watchdog timer enable zero flag (zf) not initialized carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 output latches of i/o ports refer to i/o port circuitry interrupt individual enable flags (ef) 0 interrupt latches (il) 0 control registers refer to each of control register ram not initialized 1.6.1 external reset input the reset pin contains a schmitt trigger (hysteresi s) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. when 2 10 /fc (65.5 s at 16 mhz) period passes after the reset pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses fffe h to ffff h . figure 1.6.1 reset circuit reset input reset vdd malfunction reset output circuit watchdog timer reset adddress trap reset system clock reset flash reset counter
TMP86FM48 2007-08-24 86fm48-44 1.6.2 address-trap-reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (whe n wdtcr1 is set to ?1?) or the sfr area, address-trap-reset and the flash reset will be generated. the reset time is maximum 24/fc [s] + 2 10 /fc [s] (65.5 s at 16.0 mhz). note 1: address ?a? is in the sfr or on-chip ram (wdtcr1 = ?1?) space. note 2: during reset release, reset vector ?r? is read out, and an instruction at address ?r? is fetched and decoded. figure 1.6.2 address-trap-reset note: the operating mode under address trapped is alternative of reset or interrupt. address trap or no address trap can be selected by wdtcr1 for the internal ram. 1.6.3 watchdog timer reset refer to section ?2.4 watchdog timer?. 1.6.4 system-clock-reset if the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the cpu. (the oscillation is continued without stopping.) - in case of clearing syscr2 and syscr2 simultaneously to ?0?. - in case of clearing syscr2 to ?0?, when the syscr2 is ?0?. - in case of clearing sy scr2 to ?0?, when the syscr2 is ?1?. when the system clock reset is generated, th e flash reset is also generated. therefore, the maximum reset period is 24/fc [s] + 2 10 /fc [s] (65.5 s at 16.0 mhz). instruction execution internal reset jp a reset release instruction at address r a ddress trap is occurred max 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] 2 10 /fc [s] for flash reset
TMP86FM48 2007-08-24 86fm48-45 2. on-chip peripherals functions 2.1 special function register (sfr) the TMP86FM48 adopts the memory mapped i/o system, and all peripheral control and data transfers are performed through the special function register (sfr). the sfr is mapped on address 0000 h to 003f h , dbr is mapped on address 1f80 h to 1fff h . figure 2.1.1 to figure 2.1.2 indicate the special function register (sfr) and data buffer register (dbr) for TMP86FM48. address read write address read write 0000 h p0dr (p0 port output latch) 0020 h tc1dral (timer register 1a) 01 p1dr (p1 port output latch) 21 tc1drah (timer register 1a) 02 p2dr (p2 port output latch) 22 tc1drbl (timer register 1b) 03 p3dr (p3 port output latch) 23 tc1drbh (timer register 1b) 04 reserved 24 tc2drl (timer register 2) 05 p5dr (p5 port output latch) 25 tc2drh (timer register 2) 06 p6dr (p6 port output latch) 26 adcdr2 (ad result register 2) ? 07 p7dr (p7 port output latch) 27 adcdr1 (ad result register 1) ? 08 p8dr (p8 port output latch) 28 p6cr2 (p6 port input control) 09 reserved 29 reserved 0a p0outcr (p0 port output control) 2a p3outcr (p3 port output control) 0b p1outcr (p1 port output control) 2b reserved 0c p6cr1 (p6 port input/output control) 2c eir e (interrupt enable register) 0d p5outcr (p5 port output control) 2d reserved 0e adccr1 (ad control register 1) 2e il e (interrupt latch) 0f adccr2 (ad control register 2) 2f reserved 10 tc3dra (timer register 3a) 30 reserved 11 tc3drb (timer register 3b) ? 31 reserved 12 tc3cr (timer counter 3 control) 32 reserved 13 tc2cr (timer counter 2 control) 33 reserved 14 tc5cr (timer counter 5 control) 34 ? wdtcr1 (watchdog timer control) 15 tc5dr (timer register 5) 35 ? wdtcr2 (watchdog timer control) 16 reserved 36 tbtcr (tbt/tg/dvo control) 17 sio1cr (sio1 control) 37 eintcr (external interrupt control) 18 sio1sr (sio1 status) ? 38 syscr1 (system control 1) 19 sio1buf (sio1 data buffer) 39 syscr2 (system control 2) 1a reserved 3a eir l (interrupt enable register) 1b sio2cr (sio2 control) 3b eir h (interrupt enable register) 1c sio2sr (sio2 status) ? 3c il l (interrupt latch) 1d sio2buf (sio2 data buffer) 3d il h (interrupt latch) 1e reserved 3e reserved 1f tc1cr (timer counter 1 control) 3f psw (program status word) note 1: do not access reserved areas by the program. note 2: ? : cannot be accessed. note 3: write-only registers and interrupt latches cannot us e the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical op eration instructions such as and, or, etc.). figure 2.1.1 the special function register (sfr) for TMP86FM48 (1/2)
TMP86FM48 2007-08-24 86fm48-46 address read write 1f80 h reserved d8 reserved d9 ? sbicra (sbi control 1) da sbidbr (sbi data buffer) db ? i2car (i2c address) dc sbisr (sbi status) sbicrb (sbi control 2) dd uartsr (uart status) uartcr1 (uart control 1) de ? uartcr2 (uart control 2) df rdbuf (uart received data buffer) tdbuf (uart transmit data buffer) e0 eepcr (flash control) e1 eepsr (flash status) ? e2 eepeva (flash write emulation time control) e3 reserved e4 p2outcr (p2 port output control) e5 p7cr1 (p7 port input/output control) e6 p7cr2 (p7 port input control) e7 p8cr (p8 port input/output control) e8 reserved e9 reserved ea reserved eb reserved ec reserved ed p0prd (p0 terminal input) ? ee p1prd (p1 terminal input) ? ef p2prd (p2 terminal input) ? f0 p3prd (p3 terminal input) ? f1 reserved f2 p5prd (p5 terminal input) ? f3 reserved f4 reserved f5 reserved f6 reserved f7 reserved f8 reserved f9 reserved fa reserved fb reserved fc reserved fd reserved fe ? stopcr (key-on wake-up control) ff reserved note 1: do not access reserved areas by the program. note 2: ? : cannot be accessed. note 3: write-only registers and interrupt latches cannot us e the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical op eration instructions such as and, or, etc.). figure 2.1.2 the special function register (sfr) for TMP86FM48 (2/2)
TMP86FM48 2007-08-24 86fm48-47 2.2 i/o ports the TMP86FM48 has 8 parallel input/ou tput ports (54 pins) as follows. primary function secondary functions port p0 8-bit i/o port external interrupt input, serial interface input/output, uart input/output and timer/counter input . port p1 8-bit i/o port external interrupt inpu t, serial interface input/output and timer/counter input/output. port p2 3-bit i/o port low-frequency resonator c onnections, external interrupt input, stop mode release signal input. port p3 8-bit i/o port port p5 3-bit i/o port divider output, timer/c ounter output and serial bus interface input/output. port p6 8-bit i/o port analog input and stop mode release signal input. port p7 8-bit i/o port analog input. port p8 8-bit i/o port each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. figure 2.2.1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. output data changes in the s2 state of the write cycle during execution of the instruction which writes to an i/o port. note: the positions of the read and write cy cles may vary, depending on the instruction. figure 2.2.1 input/output timing (example) ex: ld a, (x) fetch cycle read cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle input strobe data input (a) input timing (b) output timing ex: ld (x), a fetch cycle read cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle output strobe data output old new
TMP86FM48 2007-08-24 86fm48-48 2.2.1 port p0 (p07 to p00) port p0 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output, timer/counter input and uart input/output. it can be selected whether output circuit of p0 port is cmos output or a sink open drain individually, by setting the output circuit control (p0out cr). when a corresponding bit of p0outcr is cleared to ?0?, the output circuit is selected to a sink open drain and when a corresponding bit of p0outcr is set to ?1?, the output circuit is selected to a cmos output. when used as an input port or a secondar y function input (external interrupt input, serial interface input, timer/counter input or uart input), the respective output latch (p0dr) should be set to ?1? and its corresponding p0outcr bit should be cleared to ?0?. when used as a secondary function output (serial interface output or uart output), the respective p0dr should be set to ?1?. during reset, the p0dr is initialized to ?1? and p0outcr is initialized to ?0?. p0 port output latch (p0dr) and p0 port terminal input (p0prd) are located on their respective address. when read the output latch data, the p0dr should be read and when read the terminal input data, the p0prd register should be read. 7 6 5 4 3 2 1 0 p0dr (0000 h ) r/w p07 sck1 p06 txd so1 p05 rxd si1 p04 p03 tc2 p02 int2 p01 int1 p00 int0 (initial value: 1111 1111) p0outcr (000a h ) (initial value: 0000 0000) p0outcr port p0 output circuit control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p0prd (1fed h ) p07 p06 p05 p04 p03 p02 p01 p00 read only figure 2.2.2 port 0 d q p0outcri p0i note: i = 7 to 0 d q output latch data input (p0prd) p0outcri input stop outen control output data output (p0dr) control input data input (p0dr)
TMP86FM48 2007-08-24 86fm48-49 2.2.2 port p1 (p17 to p10) port p1 is a 8-bit input/output port which is also used as an external interrupt input, serial interface input/output and timer/counte r input/output. it can be selected whether output circuit of p1 port is cmos output or a sink open drain individually, by setting the output circuit control (p1outcr ). when a corresponding bit of p1outcr is cleared to ?0?, the output circuit is selected to a sink open drain and when a corresponding bit of p1outcr is set to ?1?, the output ci rcuit is selected to a cmos output. when used as an input port or a secondar y function input (external interrupt input, serial interface input, timer/counter input), th e respective output latch (p1dr) should be set to ?1? and its corresponding p1outcr bit should be cleared to ?0?. when used as a secondary function output (serial interface output or timer/counter output), the respective p1dr should be set to ?1?. during reset, the p1dr is initialized to ?1? and p1outcr is initialized to ?0?. p1 port output latch (p1dr) and p1 port terminal input (p1prd) are located on their respective address. when read the output latch data, the p1dr should be read and when read the terminal input data, the p1prd register should be read. 7 6 5 4 3 2 1 0 p1dr (0001 h ) r/w p17 p16 p15 tc1 p14 tc3 int3 p13 tc5 pwm5 pdo5 p12 sck2 p11 si2 p10 so2 (initial value: 1111 1111) p1outcr (000b h ) (initial value: 0000 0000) p1outcr port p1 output circuit control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p17 p16 p15 p14 p13 p12 p11 p10 p1prd (1feeh) read only figure 2.2.3 port 1 dq p1outcri p1i note: i = 7 to 0 dq output latch data input (p1prd) p1outcri input stop outen control output data output (p1dr) control input data input (p1dr)
TMP86FM48 2007-08-24 86fm48-50 2.2.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is al so used as an external interrupt, a stop mode release signal input, and low-frequency crystal oscillator connection pins. it can be selected whether output circuit of p2 port is cmos (p21 and p22 have a pull-up resistor) output or a sink open drain individually, by setting the output circuit control (p2outcr). when a corresponding bit of p2outcr is cl eared to ?0?, the output circuit is selected to a sink open drain and when a corresponding bit of p2outcr is set to ?1?, the output circuit is selected to a cmos output. (in case of p21 and p 22, the pull-up resistor is connected.) when used as an input port or an external interrupt input, the respective output latch (p2dr) should be set to ?1?. during reset, the p2dr initialized to ?1? and p2outcr is initialized to ?0?. a low-frequency crystal oscillator (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual-clock mode. in the single-c lock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that pin p20 should be used as an external interrupt input, a stop mode release signal input, or an input port. if it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. p2 port output latch (p2dr) and p2 port terminal input (p2prd) are located on their respective address. when read the output latch data, the p2dr should be read and when read the terminal input data, the p2prd register should be read. if a read instruction is executed for port p2 dr, p2outcr and p2prd, read data of bits 7 to 3 are unstable. note: when xten is set to ?1?, p21 and p22 become a high impedance state. figure 2.2.4 port 2 (p21 and p22) p21 (xtin) p22 (xtout) stop outen data input (p21prd) d q data input (p21) data output (p21) osc.enable data input (p22prd) d q output latch fs data input (p22) data output (p22) output latch p2outcr p2outcr input d q p2outcr p2outcr input vdd vdd xten d q
TMP86FM48 2007-08-24 86fm48-51 note: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z state. 7 6 5 4 3 2 1 0 p2dr (0002 h ) r/w p22 xtout p21 xtin p20 int5 stop (initial value: **** * 111) * : don?t care p2outcr (1fe4 h ) (initial value: **** * 000) * : don?t care 0: sink open-drain output p20 pin p21, p22 ports p2outcr port p2 output circuit control (set for each bit individually) 1: cmos output cmos output with pull-up resistor r/w p2prd (1fef h ) p22 p21 p20 read only figure 2.2.5 port 2 (p20) data input (p20prd) p20 ( int5 , stop ) dq data input (p20) data output (p20) output latch dq p2outcr p2outcr input int5 , stop input stop
TMP86FM48 2007-08-24 86fm48-52 2.2.4 port p3 (p37 to p30) port p3 is an 8-bit input/output port. it can be selected whether outp ut circuit of p3 port is cmos output or a sink open drain individu ally, by setting p3outcr. (n-ch high current output) when a corresponding bit of p3outcr is cleared to ?0?, the output circuit is selected to a sink open drain and when a corr esponding bit of p3outcr is set to ?1?, the output circuit is selected to a cmos output. when used as an input port, the respective output latch (p3dr) should be set to ?1? and its corresponding p3outcr bit should be cleared to ?0?. during reset, the p3dr is initialized to ?1?, and the p3outcr is initialized to ?0?. p3 port output latch (p3dr) and p3 port terminal input (p3prd) are located on their respective address. when read the output latch data, the p3dr should be read and when read the terminal input data, the p3prd register should be read. 7 6 5 4 3 2 1 0 p3dr (0003 h ) r/w p37 p36 p35 p34 p33 p32 p31 p30 (initial value: 1111 1111) p3outcr (002a h ) (initial value: 0000 0000) p3outcr port p3 output circuit control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p3prd (1ff0 h ) p37 p36 p35 p34 p33 p32 p31 p30 read only figure 2.2.6 port 3 d q p3outcri p3i note: i = 7 to 0 output latch data input (p3prd) p3outcri input stop outen data output (p3dr) data input (p3dr) d q
TMP86FM48 2007-08-24 86fm48-53 2.2.5 port p5 (p52 to p50) port p5 is an 3-bit input/output port which is also used as a timer/counter output, divider output and serial bus interface input/output. (n-ch high current output) it can be selected whether output circuit of p5 port is cmos output or a sink open drain individually, by setting the output circuit control (p5outcr). when a corresponding bit of p5outcr is cleared to ?0?, the output circuit is selected to a sink open drain and when a corresponding bit of p5outcr is set to ?1?, the output circuit is selected to a cmos output. when used as an input port or a serial bus interface input/output, the respective output latch (p5dr) should be set to ?1? and its corresponding p5outcr bit should be cleared to ?0?. when used as a secondary function output (timer/counter output or divider output), the respective p5dr should be set to ?1?. when used as a serial bus interface input/output, p5dr of p50 and p51 should be set to ?1? and p5outcr of p50 and p51 should be cleared to ?0? as a sink open drain output. during reset, the p5dr is initialized to ?1? and p5outcr is initialized to ?0?. p5 port output latch (p5dr) and p5 port terminal input (p5prd) are located on their respective address. when read the output latch data, the p5dr should be read and when read the terminal input data, the p5prd register should be read. if a read instruction is executed for p5dr, p5outcr and p5prd, read data of bits 7 to 3 are unstable. 7 6 5 4 3 2 1 0 p5dr (0005 h ) r/w p52 p51 dvo sda p50 ppg scl (initial value: **** * 111) * : don?t care p5outcr (000d h ) (initial value: **** * 000) * : don?t care p5outcr port p5 output circuit control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p5prd (1ff2 h ) p52 p51 p50 read only figure 2.2.7 port 5 d q p5outcri p5i note: i = 2 to 0 d q output latch data input (p5prd) p5outcri input stop outen control output data output (p5dr) data input (p5dr)
TMP86FM48 2007-08-24 86fm48-54 2.2.6 port p6 (p67 to p60) port p6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. port p6 is also used as an analog input and key-on wake-up input. input/output mode is specified by the p6 co ntrol register (p6cr1). p6 port input is controlled by the input co ntrol register (p6cr2). when used as an output port, respec tive p6cr1 should be set to ?1?. when used as an input port, respective p6cr 1 should be cleared to ?0? and respective p6cr2 should be set to ?1?. when used as an analog input, respective p6cr2 should be cleared to ?0? after respective p6cr1 is cleared to ?0?. when used as a key on wake up input, respective stopken should be set to ?1?. (k = 3 to 0) during reset, the p6cr1 and p6dr are initialized to ?0?, and the p6cr2 is initialized to ?1?. table 2.2.1 and table 2.2.2 show a p6 state. table 2.2.1 p63 to p60 state p6cr1 p6cr2 p6dr p6dr read output remark 0 0 * ?0? high-z ? 0 1 * terminal input high-z input mode 1 * 0 ?0? (output latch) low output mode 1 * 1 ?1? (output latch) high output mode * : don?t care. table 2.2.2 p67 to p64 state stopken p6cr1 p6cr2 p6dr p6 dr read output remark 0 0 0 * ?0? high-z ? 0 0 1 * terminal input high-z input mode 0 1 * 0 ?0? (output latch) low output mode 0 1 * 1 ?1? (output latch) high output mode 1 * * * terminal input high-z key on wake up * : don?t care. note: stopken is bit7 to 4 in stopcr. figure 2.2.8 port 6 (p63 to p60) d q p6cr1i p6cr1i input p6i d q data input (p6dr) data output (p6dr) analog input ainds sain stop outen p6cr2i p6cr2i input d q note 1: i = 3 to 0 note 2: sain is bit0 to 3 in adccr1
TMP86FM48 2007-08-24 86fm48-55 7 6 5 4 3 2 1 0 p6dr (0006 h ) r/w p67 ain07 stop3 p66 ain06 stop2 p65 ain05 stop1 p64 ain04 stop0 p63 ain03 p62 ain02 p61 ain01 p60 ain00 (initial value: 0000 0000) p6cr1 (000c h ) (initial value: 0000 0000) p6cr1 port p6 i/o control (set for each bit individually) 0: input mode or analog input 1: output mode r/w p6cr2 (0028 h ) (initial value: 1111 1111) p6cr2 port p6 input control (set for each bit individually) 0: input disable 1: input enable r/w note 1: do not set output mode to pin which is used for an analog input. note 2: if both p6cr1 and p6cr2 are cleared to ?0?, the read value of p6dr is always ?0?. figure 2.2.9 port 6 (p67 to p64) note 1: j = 7 to 4, k = 3 to 0 note 2: sain is bit0 to 3 in adccr1 note 3: stopken is bit 7 to 4 in stopcr. stopken d q p6cr1j p6cr1j input p6 j d q data input (p6dr) data output (p6dr) analog input stopk input ainds sain stop outen p6cr2j p6cr2j input d q
TMP86FM48 2007-08-24 86fm48-56 2.2.7 port p7 (p77 to p70) port p7 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. port p7 is also used as an analog input. input/output mode is specified by the p7 control register (p7cr1). p7 port input is controlled by the input control register (p7cr2). when used as an output port, respec tive p7cr1 should be set to ?1?. when used as an input port, respective p7cr 1 should be cleared to ?0? and respective p7cr2 should be set to ?1?. when used as an analog input, respective p7cr2 should be cleared to ?0? after respective p7cr1 is cleared to ?0?. during reset, the p7cr1 and p7dr are initialized to ?0?, and the p7cr2 is initialized to ?1?. table 2.2.3 shows a p7 state. table 2.2.3 p7 port state p7cr1 p7cr2 p7dr p7dr read output remark 0 0 * ?0? high-z ? 0 1 * terminal input high-z input mode 1 * 0 ?0? (output latch) low output mode 1 * 1 ?1? (output latch) high output mode * : don?t care.
TMP86FM48 2007-08-24 86fm48-57 7 6 5 4 3 2 1 0 p7dr (0007 h ) r/w p77 ain17 p76 ain16 p75 ain15 p74 ain14 p73 ain13 p72 ain12 p71 ain11 p70 ain10 (initial value: 0000 0000) p7cr1 (1fe5 h ) (initial value: 0000 0000) p7cr1 port p7 i/o control (set for each bit individually) 0: input mode 1: output mode r/w p7cr2 (1fe6 h ) (initial value: 1111 1111) p7cr2 port p7 input control (set for each bit individually) 0: input disable 1: input enable r/w note 1: do not set output mode to pin which is used for an analog input. note 2: if both p7cr1 and p7cr2 are cleared to ?0?, the read value of p7dr is always ?0?. figure 2.2.10 port 7 d q p7cr1i p7cr1i input p7i d q data input (p7dr) data output (p7dr) analog input ainds sain stop outen p7cr2i p7cr2i input d q note 1: i = 7 to 0 note 2: sain is bit0 to 3 in adccr1
TMP86FM48 2007-08-24 86fm48-58 2.2.8 port p8 (p87 to p80) port p8 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. input/output mode is specified by the p8 control register (p8cr). when used as an output port, respec tive p8cr should be set to ?1?. when used as an input port, respective p8cr should be cleared to ?0?. during reset, the p8cr and p8dr are initialized to ?0?. table 2.2.4 shows a p8 state. table 2.2.4 p8 port state p8cr p8dr p8dr re ad output remark 0 * terminal input high-z input mode 1 0 ?0? (output latch) low output mode 1 1 ?1? (output latch) high output mode * : don?t care. 7 6 5 4 3 2 1 0 p8dr (0008 h ) r/w p87 p86 p85 p84 p83 p82 p81 p80 (initial value: 0000 0000) p8cr (1fe7 h ) (initial value: 0000 0000) p8cr port p8 i/o control (set for each bit individually) 0: input mode or analog input 1: output mode r/w figure 2.2.11 port 8 d q p8cri p8cri input p8i d q data input (p8dr) data output (p8dr) stop outen note: i = 7 to 0
TMP86FM48 2007-08-24 86fm48-59 2.3 time base timer (tbt) the time base timer generates time base for key scanning, dynamic displa ying, etc. it also provides a time base timer interrupt (inttbt). an inttbt is generated on the first falling edge of source clock (the divider output of the timing generator) after the time base timer has b een enabled. the divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period (figure 2.3.1 (b)). the interrupt frequency (tbtck) must be selected with the time base timer disabled (the interrupt frequency must not be changed with the disable from the enable state). both frequency selection and enabling can be performed simultaneously. figure 2.3.1 time base timer example: sets the time base timer frequency to fc/2 16 [hz] and enables an inttbt interrupt. ld (tbtcr), 00000010b ; tbtck 010 ld (tbtcr), 00001010b ; tbten 1 di ; imf 0 set (eirl). 6 interrupt period source clock enable tbt tbten inttbt (b) time base timer interrupt 3 tbtcr a b c d e f g h idle0/sleep0 release request fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 time base timer control register tbtck tbten (a) configuration source clock falling edge detector inttbt interrupt request y s mpx: multiplexer mpx
TMP86FM48 2007-08-24 86fm48-60 7 6 5 4 3 2 1 0 tbtcr (0036 h ) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable/disable 0: disable 1: enable normal1/2, idle1/2 mode dv7ck = 0dv7ck = 1 slow, sleep mode tbtck time base timer interrupt frequency select [hz] 000 001 010 011 100 101 110 111 fc/2 23 fc/2 21 fc/2 16 fc/2 14 fc/2 13 fc/2 12 fc/2 11 fc/2 9 fs/2 15 fs/2 13 fs/2 8 fs/2 6 fs/2 5 fs/2 4 fs/2 3 fs/2 fs/2 15 fs/2 13 ? ? ? ? ? ? r/w note: fc: high-frequency clock [hz ], fs: low-frequency clock [hz], * : don?t care figure 2.3.2 time base timer control register table 2.3.1 time base timer interrupt frequency (example: fc = 16 mhz, fs = 32.768 khz) time base timer interrupt frequency [hz] normal1/2, idle1/2 mode tbtck dv7ck = 0 dv7ck = 1 slow, sleep mode 000 1.91 1 1 001 7.63 4 4 010 244.14 128 ? 011 976.56 512 ? 100 1953.13 1024 ? 101 3906.25 2048 ? 110 7812.5 4096 ? 111 31250 16384 ?
TMP86FM48 2007-08-24 86fm48-61 intwdt r s q q fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 clock overflow interrupt request wdtout writing clear code writing disable code wdten wdtt 2 s r 0035 h 0034 h watchdog timer control registers reset release signal from t.g clea r wdt output internal reset a b c d 1 2 binary counters wdtcr2 controller wdtcr1 s y mpx mpx: multiplexer reset request 2.4 watchdog timer (wdt) the watchdog timer is a fail-safe system to rapidly detect the cpu malfunctions such as endless looping caused by noise or the like, or deadlock and resume the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a ?reset request? or a non-maskable ?interrupt request?. however, selection is possible only once after reset. at first the ?reset request? is selected. when the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an inte rrupt at fixed intervals. note: care must be given in system design so as to protect the watchdog timer from disturbing noise. otherwise the watchdog timer may not fully exhibit its functionality. 2.4.1 watchdog timer configuration figure 2.4.1 watchdog timer configuration
TMP86FM48 2007-08-24 86fm48-62 2.4.2 watchdog timer control figure 2.4.2 shows the watchdog timer co ntrol registers (wdt cr1, wdtcr2). the watchdog timer is automati cally enabled after reset. (1) malfunction detection methods using the watchdog timer the cpu malfunction is detected as follows. 1. setting the detection time, selecting ou tput, and clearing the binary counter. 2. repeatedly clearing the binary count er within the setting detection time if the cpu malfunctions such as endless looping or deadlock occur for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters ar e cleared. at this time, when wdtcr1 = ?1?, a reset is generated and the internal hardware is reseted. when wdtcr1 = ?0?, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in stop mode including warm-up or idle mode, and automatically restarts (c ontinues counting) when the stop/idle mode is released. note: the watchdog timer consists of an internal divider and a two-stage binary counter. when clear code 4e h is written, only the binary coun ter is cleared, not the internal divider. depending on the timing at which clear code 4e h is written on the wdtcr2 register, the overflow time of the binary counter may be at minimum 3/4 of the time set in wdtcr1 . thus, write the clear code using a shorter cycle than 3/4 of the time set in wdtcr1 . example: sets the watchdog timer detection time to 2 21 /fc [s] and resets the cpu malfunction. syscr1 ld (wdtcr2), 4eh ; clears the binary counters ld (wdtcr1), 00001101b ; wdtt 10, wdtout 1 ld (wdtcr2), 4eh ; clears the binary counters (always clear immediately before and after changing wdtt) ld (wdtcr2), 4eh ; clears the binary counters ld (wdtcr2), 4eh ; clears the binary counters within 3/4 of wdt detection time within 3/4 of wdt detection time
TMP86FM48 2007-08-24 86fm48-63 watchdog timer register 1 7 6 5 4 3 2 1 0 wdtcr1 (0034 h ) (atas) (atout) wdten wdtt wdtout (initial value: ** 11 1001) wdten watchdog timer enable/disable 0: disable (it is necessary to write the disable code to wdtcr2) 1: enable normal1/2 mode dv7ck = 0dv7ck = 1 slow mode wdtt watchdog timer detection time [s] 00 01 10 11 2 25 /fc 2 23 /fc 2 21 /fc 2 19 /fc 2 17 /fs 2 15 /fs 2 13 /fs 2 11 /fs 2 17 /fs 2 15 /fs 2 13 /fs 2 11 /fs wdtout watchdog timer output select 0: interrupt request 1: reset request write only note 1: wdtout cannot be set to ?1? by program after clearing wdtout to ?0?. note 2: fc: high-frequency clock [h z], fs: low-frequency clock [hz], * : don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. note 4: the watchdog timer must be disabled or the coun ter must be cleared immediately before entering to the stop mode. when the counter is cleared, the counter must be cleared again immediately after releasing the stop mode. note 5: to disable the watchdog timer, always write ?4e h ? (clear code) to wdtcr2 for clearing the binary counter before writing ?0? to wdten, and then write ?b1 h ? (disable code) to wdtcr2. also, immediately before these proc edure, disable the interrupt mater flag (imf) by di instruction. watchdog timer register 2 7 6 5 4 3 2 1 0 wdtcr2 (0035 h ) (initial value: **** **** ) wdtcr2 watchdog timer control code write register 4e h : watchdog timer binary counter clear (clear code) b1 h : watchdog timer dis able (disable code) d2 h : enable assigning address trap area others: invalid write only note 1: the disable code is invali d unless written when wdtcr1 = 0. note 2: * : don?t care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: write clear code 4e h within 3/4 of the time set in wdtcr1. figure 2.4.2 watchdog timer control registers (2) watchdog timer enable the watchdog timer is enabled by setting wdtcr1 to ?1?. wdtcr1 is initialized to ?1? during reset, so the watchdog timer operates immediately after reset is released. (3) watchdog timer disable to disable the watchdog time, write ?4e h ? (clear code) to wdtc r2 for clearing the binary counter before writing ?0? to wdtcr1, and then write ?b1 h ? (disable code) to wdtcr2. the watchdog timer is not disabled if this procedure is reversed and the disable code is written to wdtcr2 before wdtcr1 is cleared to ?0?. also, immediately before these procedure, disable the interrupt master flag (imf) by di instruction. during disabl ing the watchdog timer, the binary counters are cleared to ?0?.
TMP86FM48 2007-08-24 86fm48-64 example: disables watchdog timer di ; imf 0 ld (wdtcr2), 4eh ; clear the binary counter ldw (wdtcr1), 0b101h ; wdten 0, wdtcr2 disable code table 2.4.1 watchdog timer detection time (example: fc = 16 mhz, fs = 32.768 khz) watchdog timer detection time [s] normal1/2 mode wdtt dv7ck = 0 dv7ck = 1 slow mode 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m 4 1 250 m 62.5 m 4 1 250 m 62.5 m 2.4.3 watchdog timer interrupt (intwdt) this is a non-maskable interrupt which can be accepted regardless of the contents of the eir. if a watchdog timer interrupt or a softwa re interrupt is already accepted, however, the new watchdog timer interrupt waits until the pr evious interrupt processing is completed (the end of the [retn] instruction execution). the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source with wdtout. example: watchdog timer interrupt setting up ld sp, 023fh ; sets the stack pointer ld (wdtcr1), 00001000b ;wdtout 0 2.4.4 watchdog timer reset if the watchdog timer reset request occur, a reset is generated and the internal hardware is reseted. when the watchdog timer reset is generated, the flash reset is also generated. therefore, the maximum reset period is 24/fc [s] + 2 10 /fc [s] (65.5 s at 16.0 mhz). note: the high-frequency clock oscillator also immediately turns on when a watchdog timer reset is generated in slow mode. in this case, the reset time may include a certain amount of error if there is any fluctuation of the oscilla tion frequency at starting the high-frequency clock oscillation. therefor e, the reset time must be considered an approximated value. figure 2.4.3 watchdog timer interrupt/reset (wdtt = 11 b ) clock binary counter overflow intwdt interrupt (wdtcr1 = ?0?) 2 17 / fc 2 19 /fc [s] write 4e h to wdtcr2 reset generate 2 1 3 0 1 2 3 0 internal reset (wdtcr1 = ?1?)
TMP86FM48 2007-08-24 86fm48-65 2.5 address trap the watchdog timer control register 1, 2 shares its addresses with the control registers in case of address trap. these control registers for address trap are shown on figure 2.5.1. watchdog timer control register 1 7 6 5 4 3 2 1 0 wdtcr1 (0034 h ) ? ? atas atout (wdten) (wdtt) (wdtout) (initial value: ** 11 1001) atas selection of address trap in internal ram 0: no address trap 1: address trap (after setting atas to ?1?, it is necessary to write the control code d2 h to wdtcr2) atout selection of operation at address trap 0: interrupt request 1: reset request write only watchdog timer control register 2 7 6 5 4 3 2 1 0 wdtcr2 (0035 h ) (initial value: **** **** ) wdtcr2 watchdog timer control code and address trapped area control code d2 h : address trapped area valid to set (atrap control code) 4e h : watchdog timer binary counter clear (wdt clear code) b1 h : watchdog timer disable (wdt disable code) others: invalid write only figure 2.5.1 watchdog timer control registers (1) selection of address trap in internal ram (atas) using wdtcr1, address trap or no address trap can be selected for the internal ram area. to execute an instruction in the internal ram area, set ?0? in wdtcr1. setting in wdtcr1 becomes valid after control code d2h is written in wdtcr2. executing an instruction in the sfr/dbr area generates an address trap unconditionally regardless of the setting in wdtcr1. (2) selection of operation at address trap (atout) as the operation at address trap either interru pt request or reset request can be selected by wdtcr1.
TMP86FM48 2007-08-24 86fm48-66 2.6 divider output (dvo) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from pin p51 ( dvo ). the p51 output latch should be set to ?1?. note: selection of divider output frequency must be made while divider output is disabled. also, in other words, when changing the stat e of the divider output frequency from enabled to disable, do not change the setting of the divider output frequency. 7 6 5 4 3 2 1 0 tbtcr (0036 h ) dvoen dvock (dv7ck) (tbten) (t btck) (initial value: 0000 0000) dvoen divider output enable/disable 0: disable 1: enable normal1/2 mode dv7ck = 0 dv7ck = 1 slow, sleep mode 00 fs/2 5 01 fs/2 4 10 fs/2 3 dvock divider output ( dvo ) frequency selection [hz] 11 fc/2 13 fc/2 12 fc/2 11 fc/2 10 fs/2 5 fs/2 4 fs/2 3 fs/2 2 fs/2 2 r/w note: fc: high-frequency clock [hz ], fs: low-frequency clock [hz], * : don?t care figure 2.6.1 divider output control register example: 1.95 khz pulse output (at fc = 16.0 mhz) set (p5dr).1 ; p51 output latch ?1? ld (tbtcr), 00000000b ; dvock ?00? ld (tbtcr), 10000000b ; dvoen ?1? table 2.6.1 divider output frequency (example: at fc = 16.0 mhz, fs = 32.768 khz) divider output frequency [hz] normal1/2, idle1/2 mode dvock dv7ck = 0 dv7ck = 1 slow, sleep mode 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k 1.024 k 2.048 k 4.096 k 8.192 k 1.024 k 2.048 k 4.096 k 8.192 k figure 2.6.2 divider output data output output latch p51 ( dvo ) mpx d q fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 10 or fs/2 2 a b c d s y 2 dvock dvoen tbtcr divider output control register (a) configuration (b) timing chart p51 output latch dvoen dvo pin output mpx: multiplexer
TMP86FM48 2007-08-24 86fm48-67 2.7 16-bit timer/counter 1 2.7.1 configuration figure 2.7.1 timer/counter 1 (tc1) clear q set toggle 16-bit timer re g ister 1a, b edge detector pulse width measurement mode pulse width measurement mode tc1cr tc1 control registe r mcap1 external trigge r command start external trigger start tc1ck tc1 pin a cap1 mpx source clock mpx risin g falling window mode capture note 1: mpx: multiplexer cmp: comparator note 2: when control input /output is us ed, i/o port setting should be set correctly. for details, refer to ?2.2 i/o ports?. fc/2 11 or fs/2 3 fc/2 7 fc/2 3 mett1 mppg1 cmp tff1 tc1cr write strobe internal reset clea r inttc1 interrupt ppg output mode start match ppg out p ut mode toggle q set clear port (note 2) ppg p in b y a s tc1drb tc1dra b y a s s a y b port (note 2) d a b y c s 16-bit up counter tc1s clea r set clear 2 decoder tc1s mpx 2
TMP86FM48 2007-08-24 86fm48-68 2.7.2 control the timer/counter 1 is controlled by a time r/counter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc1drah (0021h) tc1dral (0020h) (initial value: 1111 1111 1111 1111) tc1drbh (0023h) tc1drbl (0022h) (initial value: 1111 1111 1111 1111) note: tc1drb should not be written except ppg mode. 7 6 5 4 3 2 1 0 tc1cr (001fh) tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m (initial value: 0000 0000) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 slow1/2, sleep1/2 mode fc/2 11 fc/2 7 fc/2 3 fs/2 3 fc/2 7 fc/2 3 fs/2 3 ? ? tc1ck tc1 source clock select [hz] 00 01 10 11 external clock (tc1 pin input) timer extend event window pulse ppg 00: stop and counter clear 01: command start 10: external trigger start at the rising edge tc1s tc1 start control 11: external trigger start at the falling edge acap1 auto capture control 0: auto-capture disable 1: auto-capture enable mcap pulse width measurement mode control 0: double edge capture 1: single edge capture mett1 external trigger timer mode control 0: trigger start 1: trigger start and stop mppg1 ppg output control 0: continuous pulse generation 1: one-shot tff1 time f/f1 control 0: clear 1: set r/w note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of tw o shift registers. a value set in the timer register is put in effect at the rising edge of the first source clock pulse that occurs after the upper data (tc1drah and tc1drbh) are written. therefore, the lower byte must be written before the upper byte (it is recommended that a 16-bit access instruction be used in writing). writing only the lower data (tc1dral and tc1drbl) does not put the setting of the timer register in effect. note 3: set the mode, source clock, ppg control and timer f/f control when tc1 stops (tc1s = 00). note 4: auto-capture can be used in only timer, event counter, and window modes. note 5: values to be loaded to timer registers must satisfy the following condition. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (others) note 6: always write ?0? to tff1 except ppg output mode. note 7: writing to the tc1drb is not possible unless tc1 is set to the ppg output mode. note 8: on entering stop mode, the tc1 start control (tc1 s) is cleared to ?00? automatically. so, the timer stops. once the stop mode has been released, to star t using the timer counter, set tc1s again. note 9: use the auto-capture function in the operative condi tion of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-c apture disable. read the capture value in a capture enabled condition. tc1dra (0021,0020h) r/w tc1drb (0023,0022h) r/w
TMP86FM48 2007-08-24 86fm48-69 note 10: since the up-counter value is captured into tc 1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured val ue, wait at least one cycle of the internal source clock before reading tc1drb for the first time. figure 2.7.2 timer register s and tc1 control register 2.7.3 function timer/counter 1 has six operatin g modes: timer, external tr igger timer, event counter, window, pulse width measurement, programmable pulse generator output mode. (1) timer mode in this mode, counting up is performed us ing the internal clock. the contents of tc1dra are compared with the contents of up counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared to ?0?. counting up resumes after the counter is cleared. the current contents of up counter can be transferred to tc1drb by setting tc1cr to ?1? (auto capture function). use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. table 2.7.1 source clock (internal cloc k) for timer/counter 1 (example: at fc = 16 mhz, fs = 32.768khz) normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 tc1ck resolution [ s] maximum time setting [s] resolution [ s] maximum time setting [s] resolution [ s] maximum time setting [s] 00 01 10 128 8.0 0.5 8.39 0.524 32.77 m 244.14 8.0 0.5 16.0 0.524 32.77 m 244.14 ? ? 16.0 ? ? example 1: sets the timer mode with source clock fc/2 11 [hz] and generates an interrupt 1 second later (at fc = 16 mhz, dv7ck = 0) ldw (tc1dra), 1e84h ; sets the timer register (1 s 2 11 /fc = 1e84h) di ; imf = ?0? set (eirl). 5 ; enable inttc1 ei ; imf = ?1? ld (tc1cr), 00000000b ; tff1 ?0?, tc1ck ?00?, tc1m ?00? ld (tc1cr), 00010000b ; starts tc1 example 2: auto-capture ld (tc1cr), 01010000b ; acap1 ?1? (capture) ld wa, (tc1drb) ; reads the capture value note : since the up-counter value is captured into tc1 drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured val ue, wait at least one cycle of the internal source clock before reading tc1drb for the first time.
TMP86FM48 2007-08-24 86fm48-70 figure 2.7.3 timer mode timing chart source clock up counte r match detect counter clea r (a) timer mode command start 1 2 3 0 n ? ? -2 tc1drb a cap1 m ? 1 m m + + ? + 1 n m ? 1 m m + + ? + 1 n ? ca p ture ca p ture (b) auto capture
TMP86FM48 2007-08-24 86fm48-71 (2) external trigger timer mode in this mode, counting up is started by an external trigger. this trigger is the edge of the tc1 pin input. either the rising or falling edge can be selected with tc1s. source clock is an internal clock. the contents of tc1dra is compared with the contents of up counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared to ?0? and halted. the counter is rest arted by the selected edge of the tc1 pin input. when tc1cr is ?1?, inputting the edge to the reverse direction of the trigger edge to start counting clears the co unter, and the counter is stopped. inputting a constant pulse width can generate interrupts. when tc1cr is ?0?, the reverse directive edge input is ignored. the tc1 pin input edge before a match detection is also ignored. the tc1 pin input has the noise rejection; therefore, pulses of 4/fc [s] or less are rejected as noise. a pulse width of 12/fc [s] or more is required for edge detection in normal1/2 or idle1/2 mode. the noise reje ction circuit is turned off in slow1/2 and sleep1/2 modes. but, a pulse width of one machine cycle or more is required. example 1: detects rising edge in tc1 pin input and generates an interrupt 100 s later. (at fc = 16 mhz, dv7ck = 0) di ; imf = ?0? ldw (tc1dra), 00c8h ; 100 s 2 3 /fc = c8h set (eirl). 5 ; inttc1 interrupt enable ei ; imf = ?1? ld (tc1cr), 00001000b ; tff1 = ?0?, tc1ck = ?10?, tc1m = ?00? ld (tc1cr), 00101000b ; tc1 external trigger start, mett1 = ?0? example 2: generates an interrupt, inputting ?l? level pulse (pulse width: 4 ms or more) to the tc1 pin. (at fc = 16 mhz) di ; imf = ?0? ldw (tc1dra), 1f40h ; 4 ms 2 3 /fc = 1f40h set (eirl). 5 ; inttc1 interrupt enable ei ; imf = ?1? ld (tc1cr), 01001000b ; tff1 = ?0?, tc1ck = ?10?, tc1m = ?00? ld (tc1cr), 01111000b ; tc1 external trigger start, mett1 = 1
TMP86FM48 2007-08-24 86fm48-72 figure 2.7.4 external trigger timer mode timing chart (3) event counter mode in this mode, events are counted at the edge of the tc1 pin input (either the rising or falling edge can be selected with the external trigger tc1cr). the contents of tc1dra are compared with the contents of up counter. if a match is found, an inttc1 interrupt is generated, and the counter is cl eared. after the counter is cleared, the up counter starts counting by tc1 input edge. match detect is executed on other edge of count-up. a match can not be detected and inttc1 is not generated when the pulse is still in same state. two or more machine cycles are required for both the ?h? and ?l? levels of the pulse width. setting tc1cr to ?1? transfers the current contents of up counter to tc1drb (auto-capture function). use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. figure 2.7.5 event counter mode timing chart tc1 pin input up counte r tc1dra inttc1 interru p t 1 2 2 n ? match detect counter clea r count start 0 n ? = = ? = = = ? ?
TMP86FM48 2007-08-24 86fm48-73 table 2.7.2 timer/counter 1 external clock source minimum input pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode ?h? width 2 3 /fc 2 3 /fs ?l? width 2 3 /fc 2 3 /fs (4) window mode in this mode, counting up is performed on the rising edge of the pulse that is the logical and-ed product of the tc1 pin input (window pulse) and an internal clock. the contents of tc1dra are compared with the contents of up counter. if a match is found, an inttc1 interrupt is generated, and the coun ter is cleared. it is possible to select either positive logic or negative logic for the tc1 pin input (by using the tc1 start control tc1cr). the maximum frequency that can be applied to the pin must be such that the related count can be analyzed by program. to put another way, the frequency of the applied pulse must be sufficiently low, compared with that of the internally set source clock. figure 2.7.6 window mode timing chart counter clea r internal clock up counte r match detect counter clea r (a) positive logic (at tc1s = =
TMP86FM48 2007-08-24 86fm48-74 (5) pulse width measurement mode in this mode, counting is started by the exte rnal trigger (set to external trigger start by tc1cr). the trigger can be selected either the rising or falling edge of the tc1 pin input. the source clock is used an in ternal clock. on the next falling (rising) edge, the counter contents are transferred to tc1drb and an inttc1 interrupt is generated. the counter is cleared when th e single edge capture mode (tc1cr = ?1?) is set. when double edge capture (tc1cr = ?0?) is set, the counter continues and, at the next rising (fallin g) edge, the counter contents are again transferred to tc1drb. if a falling (rising) edge capture value is required, it is necessary to read out tc1drb contents unt il a rising (falling) edge is detected. falling or rising edge is selected with the external trigger tc1cr, and single edge or double edge is selected with tc1cr. note 1: be sure to read the captured value from tc1drb before the next trigger edge is detected. if fail to read it, it becomes undefined. it is recommended that a 16-bit access instruction be used to read from tc1drb. note 2: if either the falling or rising edge is us ed in capturing values, the counter stops at ?1? after a value has been captured until the next edge is detected. so, the value captured next will become ?1? larger than the value captured right after capturing starts. note 3: the first captured value after the time r starts may be read incorrectively, therefore, ignore the first captured value. example: duty measurement (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 service switch initial setting ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf = ?0? set (eirl). 5 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 pinttc1: cpl (inttc1sw). 0 ; inverts inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (?h? level pulse width) ld w, (tc1drbh) reti sinttc1: ld l, (tc1drbl) ; reads tc1drb (period) ld h, (tc1drbh) ; duty calculation reti vinttc1: dw pinttc1 tc1 pin inttc1sw hpulse width
TMP86FM48 2007-08-24 86fm48-75 figure 2.7.7 pulse measurement mode timing chart (b) double edge capture (mcap1 = = ? = ? = + + + ? 2 m ? 1 m 0 m capture
TMP86FM48 2007-08-24 86fm48-76 (6) programmable pulse generate (ppg) output mode the ppg output mode is intended to output pulses having an arbitrary duty cycle selected using two timer registers. the timer starts at an edge (rising or falling edge, that is, the same edge type as selected with the external trigger edge select bits (tc1cr) or on a command. its source clock is an internal clock. once the timer starts running, the timer f/f1 is inverted when the counter matches tc1drb, generating the inttc1 interrupt. the counter keeps up-counting, and when counter matches tc1dra, the timer f/f1 is inverted, generating an inttc1 interrupt. if tc1cr was previously set to ?1? (one shot), tc1s is cleared to ?00? automatically, causing the timer to stop. if tc1cr was previously cleared to ?0? (continuous pulse generation), the counter is cleared, resulting in the counter keeping to run and the ppg output being continued. if tc1cr is reset to ?00? (one-shot-based automatic stop is included) during ppg output, the p50 ( ppg ) pin holds the same level that it does just before the counter stops. in ppg output mode, set the output latch of port p50 to ?1?. the timer f/f1 is cleared to ?0? at a reset. in addition, a positive or negative pulse can be output because the output level can be set up at a start, using tc1cr. the p50 ( ppg ) pin outputs an inversion of the timer f/f1 output level. it is impossible to write to tc1drb unless the ppg output mode is set. note 1: to change the content of the timer regi ster when the timer is running, change it to a sufficiently large value, compared with the current count. if the timer register content is changed to a value smaller t han the current count when the timer is running, it is likely that unintended pulses may be output. note 2: do not change tc1cr when the timer is running. tc1cr can be set correctly only at initialization (after a reset). when the timer is stopped during ppg output, if the ppg output is at a logic state opposite to the ppg that when the timer starts, it will become impossible to set tc1cr correctly (an attempt to program tc1cr< tff1> will cause a state opposite to the programmed one to be set in the bit). once the timer has stopped, putting the ppg output securely on an arbitrary level requires in itializing the timer f/f1. to initialize it, put tc1cr in the timer mode again (it is unnecessary to start the timer mode), and then put it in the ppg output mode again. at the same time, set tc1cr. note 3: in the ppg output mode, a value set in the timer register must satisfy: tc1dra > tc1drb example: pulse output ?h? level 800 s, ?l? level 200 s (at fc = 16 mhz, dv7ck = 0) set (p5dr). 0 ; p50 output latch 1 ld (tc1cr), 10001011b ; sets the ppg output mode ldw (tc1dra), 07d0h ; sets the period (1 ms 2 3 /fc = 07d0h) ldw (tc1drb), 0190h ; sets ?l? level pulse width (200 s 2 3 /fc = 0190h) ld (tc1cr), 10011011b ; starts
TMP86FM48 2007-08-24 86fm48-77 figure 2.7.8 ppg output figure 2.7.9 ppg output mode timing chart d q r set clear q toggle tff1 tc1cr write strobe internal reset match with tc1drb match with tc1dra inttc1 interrupt mppg1 tc1s clea r timer f/f1 data output p50 output latch p50 ( ppg ) pin mpx: multiplexe r command start up counte r tc1drb (a) continuous pulse generation (with tc1s = =
TMP86FM48 2007-08-24 86fm48-78 2.8 16-bit timer/counter 2 2.8.1 configuration figure 2.8.1 timer/counter 2 (tc2a) port h a b c d y e f s mpx timer/event counte r b y a s window fc/2 23 or fs/2 15 fc/2 13 or fs/2 5 fc/2 8 fc/2 3 fc fs 3 tc2cr tc2s tc2ck tc2 control re g iste r cmp 16-bit up counter tc2dr 16-bit timer re g ister 2 tc2s clea r match match detect control tc2drh write strobe tc2drl write strobe inttc2 interru p t note 1: mpx: multiplexer cmp: comparator note 2: when control input/output is used, i/o port setting s hould be set correctly. for details, refer to ?2.2 i/o ports?. enable tc2 pin (note 2) tc2m source clock
TMP86FM48 2007-08-24 86fm48-79 2.8.2 control the timer/counter 2 is controlled by a time r/counter 2 control register (tc2cr) and a 16-bit timer register 2 (tc2dr). reset does not affect tc2dr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc2drh (0025h) tc2drl (0024h) 7 6 5 4 3 2 1 0 tc2cr (0013h) tc2s tc2ck tc2m (initial value: ** 00 00 * 0) tc2m tc2 operating mode select 0: timer/event counter mode 1: window mode normal1/2, idle1/2 mode dv7ck = 0dv7ck = 1 slow1/2 mode sleep1/2 mode fc/2 23 fc/2 13 fc/2 8 fc/2 3 ? fs fs/2 15 fs/2 5 fc/2 8 fc/2 3 ? fs fs/2 15 fs/2 5 ? ? fc (note 7) ? fs/2 15 fs/2 5 ? ? ? ? reserved tc2ck tc2 source clock select [hz] 000 001 010 011 100 101 110 111 external clock (tc2 pin input) tc2s tc2 start control 0: stop and counter clear 1: start r/w note 1: fc: high-frequency clock [h z], fs: low-frequency clock [hz], * : don?t care note 2: when writing to the timer register 2 (tc2dr), always write to the lower side (tc2drl) and then the upper side (tc2drh) in that order. writing to only the lo wer side (tc2drl) or the upper side (tc2drh) has no effect. note 3: the timer register 2 (tc2dr) uses the value previ ously set in it for coincidence detection until data is written to the upper side (tc2drh) after writing data to the lower side (tc2drl). note 4: set the mode and source clock when the tc2 stops (tc2s = 0). note 5: values to be loaded to the timer r egister must satisfy the following condition. tc2dr > 1 (tc2dr 15 to tc2dr 11 > 1 at warm up) note 6: if a read instruction is executed for tc2cr, read data of bit 7, 6 and 1 are unstable. note 7: the high-frequency clock(fc) can be selected only when the timer mode at slow2 mode is selected. note 8: on entering stop mode, the tc2 start control (tc2 s) is cleared to ?0? automatically. so, the timer stops. once the stop mode has been released, to star t using the timer counter, set tc2s again. figure 2.8.2 timer register 2 and tc2 control register tc2dr (0025, 0024h) r/w
TMP86FM48 2007-08-24 86fm48-80 2.8.3 function the timer/counter 2 has three operating modes: timer, event counter and window modes. (1) timer mode in this mode, the internal clock is used for counting up. the contents of tc2dr are compared with the contents of up counter . if a match is found, a timer/counter 2 interrupt (inttc2) is generated, and the co unter is cleared. counting up is resumed after the counter is cleared. when fc is selected for source clock at slow2 mode, lower 11-bits of tc2dr are ignored and generated a interrupt by matching upper 5-bits. though, in this situation, it is necessary to set tc2drh only. table 2.8.1 source clock (internal clock) for timer/counter 2 (at fc = 16 mhz) normal1/2, idle1/2 mode slow1/2 mode sleep1/2 mode dv7ck = 0 dv7ck = 1 tc2ck resolution maximum time setting resolution maximum time setting resolution maximum time setting resolution maximum time setting 000 001 010 011 100 101 524.29 ms 512.00 s 16.00 s 0.50 s ? 30.52 s 9.54 h 33.55 s 1.05 s 32.77 ms ? 2.00 s 1.00 s 0.98 ms 16.00 s 0.50 s ? 30.52 s 18.20 h 1.07 min 1.05 s 32.77 ms ? 2.00 s 1.00 s 0.98 ms ? ? 62.5 ns (note) ? 18.20 h 1.07 min ? ? ? ? 1.00 s 0.98 ms ? ? ? ? 18.20 h 1.07 min ? ? ? ? note: when fc is selected as the source clock in ti mer mode, it is used at warm-up for switching from slow2 mode to normal2 mode. example: sets the timer mode with source clock fc/2 3 [hz] and generates an interrupt every 25 ms (at fc = 16 mhz). ldw (tc2dr), 0c350h ; sets tc2dr (25 ms 2 3 /fc = c350h) di ; imf = ?0? set (eire). 4 ; enables inttc2 interrupt ei ; imf = ?1? ld (tc2cr), 00001100b ; tc2ck ?011?, tc2m ?0? ld (tc2cr), 00101100b ; starts tc2
TMP86FM48 2007-08-24 86fm48-81 (2) event counter mode in this mode, events are counted on the rising edge of the tc2 pin input. the contents of tc2dr are compared with the contents of the up counter. if a match is found, an inttc2 interrupt is generated, and the counter is cleared. the minimum input pulse width of tc2 pin is shown in table 2.8.2. two or more machine cycles are required for both the ?h? and ?l? levels of th e pulse width. match detect is executed on the falling edge of the tc2 pin. a match can not be detected and inttc2 is not generated when the pulse is still in a falling state. example: sets the event counter mode and generates an inttc2 interrupt 640 counts later. ldw (tc2dr), 640 ; sets tc2dr di ; imf = ?0? set (eire). 4 ; enables inttc2 interrupt ei ; imf = ?1? ld (tc2cr), 00011100b ; tc2ck ?111?, tc2m ?0? ld (tc2cr), 00111100b ; starts tc2 table 2.8.2 timer/counter 2 external clock source minimum input pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode ?h? width 2 3 /fc 2 3 /fs ?l? width 2 3 /fc 2 3 /fs
TMP86FM48 2007-08-24 86fm48-82 (3) window mode in this mode, counting up performed on the rising edge of an internal clock during tc2 external pin input (window pulse) is ?h? level. the contents of tc2dr are compared with the contents of up counter. if a match found, an inttc2 interrupt is generated, and the up-counter is cleared. the maximum applied frequency (tc2 input) must be considerably slower than the selected internal clock. note: in the window mode, before the slow /sleep mode is entered, the timer should be halted by setting tc2cr to ?0?. example: generates an interrupt, inputting ?h? level pulse width of 120 ms or more. (at fc = 16 mhz, dv7ck = 0) ldw (tc2dr), 00eah ; sets tc2dr (120 ms 2 13 /fc = 00eah) di ; imf = ?0? set (eire). 4 ; enables inttc2 interrupt ei ; imf = ?1? ld (tc2cr), 00000101b ; tc2ck ?001?, tc1m ?1? ld (tc2cr), 00100101b ; starts tc2 figure 2.8.3 window mode timing chart 0 tc2 pin input n ? ? ?
TMP86FM48 2007-08-24 86fm48-83 2.9 8-bit timer/counter 3 2.9.1 configuration note 1: mpx: multiplexer cmp: comparator note 2: when control input/output is used, i/o port setting s hould be set correctly. for details, refer to ?2.2 i/o ports?. figure 2.9.1 timer/counter 3 (tc3) ( note 2 ) overflow tc3 pin clea r tc3s port tc3cr 1 y 0 s fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 10 or fs/2 2 fc/2 9 or fs fc/2 8 fc/2 7 inttc3 interrupt tc3s h a y b c d e f g s edge detector mpx fallin g risin g tc3m tc3s tc3ck 3 tc3 control re g iste r tc3drb acap ca p ture ca p ture cmp tc3dra 8-bit timer re g ister 3a, b match 8-bit up counter source clock
TMP86FM48 2007-08-24 86fm48-84 2.9.2 control the timer/counter 3 is controlled by a time r/counter 3 control register (tc3cr) and two 8-bit timer registers (tc3dra and tc3drb). 7 6 5 4 3 2 1 0 (initial value: 1111 1111) 7 6 5 4 3 2 1 0 (initial value: 1111 1111) 7 6 5 4 3 2 1 0 acap tc3s tc3ck tc3m (initial value: * 0 * 0 0000) tc3m tc3 operation mode set 0: timer/event counter 1: capture normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 slow1/2, sleep1/2 mode fc/2 13 fc/2 12 fc/2 11 fc/2 10 fc/2 9 fc/2 8 fc/2 7 fs/2 5 fs/2 4 fs/2 3 fs/2 2 fs/2 fc/2 8 fc/2 7 fs/2 5 fs/2 4 fs/2 3 fs/2 2 fs/2 ? ? tc3ck tc3 source clock select [hz] 000 001 010 011 100 101 110 111 external clock (tc3 pin input) tc3s tc3 start select 0: stop and clear 1: start acap auto-capture control 0: ? 1: auto capture enable r/w note 1: fc: high-frequency clock [h z], fs: low-frequency clock [hz], * : don?t care note 2: set the mode and the source clock when the tc3 stops (tc3s = 0). note 3: values to be loaded into timer regist er 3a must satisfy the following condition. tc3dra > 1 (in the timer and event counter mode) note 4: auto-capture can be used only in the timer and event counter mode. note 5: if a read instruction is executed for tc 3cr, read data for bits 7 and 5 are unstable. note 6: during tc3 operation, do not change tc3dra. note 7: on entering stop mode, tc3 start control (tc3 s) is cleared to ?0? automatically, so the timer stops. once the stop mode has been released, to star t using the timer counter, set tc3s again. figure 2.9.2 timer register 3 and tc3 control register tc3dra (0010h) r/w tc3drb (0011h) read only tc3cr (0012h)
TMP86FM48 2007-08-24 86fm48-85 2.9.3 function the timer/counter 3 has three operating modes: timer, event counter, and capture mode. (1) timer mode in this mode, the internal clock is used fo r counting up. the contents of tc3dra are compared with the contents of up counter. if a match is found, a timer/counter 3 interrupt (inttc3) is generated, and the up counter is cleared. the current contents of up counter are loaded into tc3drb by setting tc3cr to ?1? (auto-capture function). the contents of up counter can be easily confirmed by executing the read instruction (rd instruction) of tc3drb. loading the contents of up counter is not synchronized with counting up. the contents of over flow (ffh) and 00h can not be loaded correctly. it is necessary to consider the count cycle. table 2.9.1 source clock (internal cloc k) for timer/counter 3 (example: at fc = 16 mhz) normal1/2, idle1/2 mode slow1/2 mode dv7ck = 0 dv7ck = 1 tc3ck resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] 000 001 010 011 100 101 110 512.0 256.0 128.0 64.0 32.0 16.0 8.0 130.6 65.3 32.6 16.3 8.2 4.1 2.0 976.6 488.3 244.1 122.0 61.0 16.0 8.0 249.0 124.5 62.3 31.1 15.6 4.1 2.0 976.6 488.3 244.1 122.0 61.0 ? ? 249.0 124.5 62.3 31.1 15.6 ? ? fe ff clock counte r ff fe tc3drb 01 00 01
TMP86FM48 2007-08-24 86fm48-86 (2) event counter mode in this mode, events are counted on the edge of the tc3 pin input. the counter counts up on the rising edge of the tc3 pin input and when its value matches the tc3dra set value, it is cleared while at the same time generating an inttc3 interrupt. the detection of match is executed at the falling edge of the tc3 pin. therefore, if the tc3 pin keeps high level afte r the rising, the detection of match is not executed and inttc3 is not generated until the level of tc3 pin becomes low. the minimum input pulse width of the tc3 pin is shown in table 2.9.2. one or more machine cycles are required for both the ?h? and ?l? levels of the pulse width. the current contents of up counter are loaded into tc3drb by setting tc3cr to ?1? (auto-capture function). the contents of up counter can be easily confirmed by executing the read instruction (rd instruction) of tc3drb. loading the contents of up counter is not synchronized with counting up. the contents of over flow (ffh) and 00h can not be loaded correctly. it is necessary to consider the count cycle. table 2.9.2 source clock (ext ernal clock) for timer/counter minimum input pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode ?h? width 2 2 /fc 2 2 /fs ?l? width 2 2 /fc 2 2 /fs
TMP86FM48 2007-08-24 86fm48-87 (3) capture mode in this mode, the pulse width, period and duty of the tc3 pin input are measured in this mode, which can be used in decoding the remote control signals or distinguishing ac 50/60 hz, etc. once command operation has started, the counter free-runs on an internal source clock. when the falling edge of the tc3 pin input is detected, the counter value is loaded into tc3drb. when the rising edge is detected, the counter value is loaded into tc3dra, and the counter is cleared, generating an inttc3 interrupt. if the rising edge is detected right after command operation has started, no capture to tc3drb and an inttc3 interrupt occurs only on capture to tc3dra. if a read instruction is executed for tc3drb, the value that exists at the end of the previous capture (immediately after a reset, ?ff?) is read. the minimum acceptable input pulse width is equal to the length of one source clock period selected by tc3cr. table 2.9.3 capture input edges capture into tc3drb capture into tc3dra inttc3 interrupt falling edge rising edge when the overflow occurs before detecting the edge, the inttc3 interrupt is generated, setting ?ffh? to tc3dra and clea ring the counter. it is possible to confirm whether the overflow has occurred or not by reading tc3dra in interrupt routine. after generating of interrupt, the capture function and overflow detection stop until the tc3dra is read, but the counting is continued. because the capture function and overflow detection are restarted by read ing tc3dra, read the tc3drb before the reading tc3dra.
TMP86FM48 2007-08-24 86fm48-88 figure 2.9.3 capture mode timing chart overflow ff (overflow) capture tc3s source clock up counte r tc3 pin input tc3dra tc3drb inttc3 interrupt reading tc3dra command start capture 0 1 i ? 1 i i + 1 k ? 1 1 k 0 m m + 1 n ? 1 m ? 1 n 0 1 2 3 fe ff 1 2 3 k i m n fe
TMP86FM48 2007-08-24 86fm48-89 2.10 8-bit timer/counter 5 2.10.1 configuration note 1: mpx: multiplexer cmp: comparator note 2: when control input/output is used, i/o port setting s hould be set correctly. for details, refer to ?2.2 i/o ports?. figure 2.10.1 timer/counter 5 (tc5) overflow clea r tc5s tc5cr tc5dr ( note 2 ) tc5 pin port tc5 control registe r tc5s tc5m tc5s tc5ck 3 8-bit timer re g ister 5 timer f/f5 inttc5 interrupt match cmp 8-bit up counter source clock ( note 2 ) port toggle clear pdo mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fc/2 2 fc/2 fc a b c d y e f g h s mpx 2 a y b s a b ys pwm output mode pwm5 / pdo5 pin
TMP86FM48 2007-08-24 86fm48-90 2.10.2 control the timer/counter 5 is controlled by a time r/counter 5 control register (tc5cr) and an 8-bit timer register 5 (tc5dr). reset does not affect tc5dr. 7 6 5 4 3 2 1 0 (initial value: 1111 1111) tc5dr (0015h) r/w 7 6 5 4 3 2 1 0 tc5s tc5ck tc5m (initial value: ** 00 0000) tc5cr (0014h) tc5s tc5 start control 0: stop and counter clear 1: start normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 slow1/2, sleep1/2 mode fc/2 11 fc/2 7 fc/2 5 fc/2 3 fc/2 2 fc/2 fc fs/2 3 fc/2 7 fc/2 5 fc/2 3 fc/2 2 fc/2 fc fs/2 3 ? ? ? ? ? ? tc5ck tc5 source clock select [hz] 000 001 010 011 100 101 110 111 external clock (tc5 pin input) tc5m tc5 operating mode select 00: timer/event counter mode 01: reserved 10: programmable divider output (pdo) mode 11: pulse width modulation (pwm) output mode r/w note 1: fc: high-frequency clock [h z], fs: low-frequency clock [hz], * : don?t care note 2: values to be loaded to the timer r egister must satisfy the following condition. 1 tc5dr 255 note 3: when tc5 operation is started (tc5s = ?0? ?1?) or tc5 operation is stopped (tc5s = ?1? ?0?), do not change tc5cr . also, during tc5 operation (tc5s = ?1? ?1?), do not change tc5cr . note 4: available source cloc ks for each operation mode is referred to the following table. timer mode event counter mode pdo mode pwm mode tc5ck 000 001 010 011 100 101 110 111 note 5: the tc5s is automatically cleared to ?0? after starting stop mode. note 6: if a read instruction is executed for tc5cr, read data of bits 7 and 6 are unstable. note 7: during tc5 operation except pwm mode, do not change tc5dr. figure 2.10.2 timer register 5 and tc5 control register
TMP86FM48 2007-08-24 86fm48-91 2.10.3 function the timer/counter 5 has four operating modes: timer, event counter, programmable divider output, and pwm output mode. (1) timer mode in this mode, the internal clock is used for counting up. the contents of tc5dr is compared with the contents of up counter. if a match is found, an inttc5 interrupt is generated and the up-counter is cleared to ?0?. counting up resumes after the up-counter is cleared. table 2.10.1 source clock (internal cloc k) for timer/counter 5 (example: at fc = 16 mhz) normal1/2, idle1/2 mode slow1/2 mode dv7ck = 0 dv7ck = 1 tc5ck resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] 000 001 010 011 128.0 8.0 2.0 0.5 32.6 2.0 0.510 0.128 244.14 8.0 2.0 0.5 62.3 2.0 0.510 0.128 244.14 ? ? ? 62.3 ? ? ? (2) event counter mode in this mode, events are counted on the rising edge of the tc5 pin input (external clock). the contents of the tc5dr is compared with the contents of the up counter. if a match is found, an inttc5 interrupt is generated and the counter is cleared. counting up resumes after the up counter is cleared. the minimum input pulse width of the tc5 pin is shown in table 2.10.2. two or more machine cycles are required for both the ?h? and ?l? levels of the pulse width. match detect is executed on the falling edge of the tc5 pin. a match can not be detected and inttc5 interrupt is not generated when the pulse is still in a falling state. table 2.10.2 timer/counter 5 external clock source minimum input pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode ?h? width 2 3 /fc 2 3 /fs ?l? width 2 3 /fc 2 3 /fs
TMP86FM48 2007-08-24 86fm48-92 (3) programmable divider output (pdo) mode the programmable divider output (pdo) mode is intended to output a pulse having a duty cycle of about 50%. the counter counts up on an internal source clock. if the timer value matches tc5dr, the timer f/f5 is inverted, and the counter is cleared, generating an inttc5 interrupt. the counter keeps counting up, and the timer f/f5 is inverted each time the timer value matches tc5dr. the p13 ( pdo5 ) pin outputs an inversion of the timer f/f5 output level. at a reset or when the timer stops, the timer f/f5 is cleared to ?0?. so, stopping the timer when the pdo output is low may cause the duty cycle to become smaller than the set value. to use the programmable divider output mode, set the output latch of the p13 port to ?1?. example: output a 1024 hz pulse (at fc = 16 mhz) ld (tc5cr), 00000110b ; sets pdo mode (tc5m = 10, tc5ck = 001) set (p1dr). 3 ; p13 output latch 1 ld (tc5dr), 3dh ; 1/1024 2 7 /fc 2 = 3dh ld (tc5cr), 00100110b ; starts tc5 figure 2.10.3 pdo mode timing chart 1 0 1 n 0 internal clock up counter tc5dr timer f/f5 pdo5 pin output inttc5 interrupt 0 n match detect 1 2 n 2 0 n 2 12 1 n 0
TMP86FM48 2007-08-24 86fm48-93 (4) pulse width modulation (pwm) output mode the pulse width modulation (pwm) output mode is intended to output pulses at constant intervals with a resolution of 8 bits. the counter counts up on the internal source clock. if the timer value matches tc5dr, the timer f/f5 is inverted, and the counter keeps-up counting. if an overflow is detected, the timer f/f5 is inverted again, generating an inttc5 interrupt. the p13 ( pwm5 ) pin outputs an inversion of the timer f/f5 output level. at a reset or when the timer stops, the timer f/f5 is cleared to ?0?. so, stopping the timer when the pwm output is low may cause one cycle to become smaller than the set value. to use the pulse width modulation (pwm) output mode, set the output latch of the p13 port to ?1?. tc5dr is configured a 2-stage shift register and, during pulse width, will not switch until one output cycle is completed even if tc5dr is overwritten; therefore, pulse width can be altered continuously. also, the first time, tc5dr is shifted by setting tc5cr to ?1? after data are loaded to tc5dr. note: in pwm mode, writing to the timer register tc5dr should be performed only right after an inttc5 interrupt occurs (usua lly, within the inttc5 interrupt service routine). if writing to the timer register tc5dr occurs at the same timing as the inttc5 interrupt, pulses having a value other than the set value may be output before another inttc5 interrupt occurs, because an unstable value that is being written is shifted. figure 2.10.4 pwm output mode timing chart table 2.10.3 pwm output mode (example: fc = 16 mhz) normal1/2, idle1/2 mode tc5ck resolution [ns] repeat cycle [ s] 000 001 010 011 100 101 110 ? ? ? 500 250 125 62.5 ? ? ? 128 64 32 16 internal clock up counter tc5dr timer f/f5 pwm pin output inttc5 interrupt overwrite 0 n/m n/n m/m match 1 n n + 1 ff 0 1 n n + ? 1 m 1 cycle shift
TMP86FM48 2007-08-24 86fm48-94 2.11 uart (asynchronous serial interface) the TMP86FM48 has 1 channel of uart (asynchronous serial interface). the uart is connected to external devices via rxd and txd. rxd is also used as p05; txd, as p06. to use p05 or p06 as the rxd or tx d pin, set p0 port output latches to ?1?. 2.11.1 configuration figure 2.11.1 uart parity bit intrxd inttxd 2 2 transmit data buffer uart control register 1 receive data buffer 3 rxd txd stop bit uart control register 2 2 uart status register 4 baud rate generator a b c m d p e x f g h s y fc/13 2 transmit/receive clock uartcr1 tdbuf rdbuf shift register counter uartsr shift register receive control circuit noise rejection circuit uartcr2 y m a p b x c s transmit control circuit fc/2 6 fc/2 7 fc/2 8 fc/26 fc/52 fc/104 fc/208 fc/416 inttc5 fc/96 mpx
TMP86FM48 2007-08-24 86fm48-95 2.11.2 control uart is controlled by the uart control registers (uartcr1, uartcr2). the operating status can be monitored usin g the uart status register (uartsr). uart control register 7 6 5 4 3 2 1 0 uartcr1 (1fdd h ) txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: disable 1: enable rxe receive operation 0: disable 1: enable stbt transmit stop bit length 0: 1 bit 1: 2 bits even even-numbered parity 0: odd-numbered parity 1: even-numbered parity pe parity addition 0: no parity 1: parity brg transmit clock select 000: fc/13 [hz] 001: fc/26 010: fc/52 011: fc/104 100: fc/208 101: fc/416 110: tc5 (inttc5) 111: fc/96 write only note 1: when operations are disabled by setting txe and rxe bit to ?0?, the setting becomes valid when data transmit or receive complete. when the transmit data is stored in the transmit data buffer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uartcr1 and uartcr1 should be set to ?0? before uartcr1 is changed 7 6 5 4 3 2 1 0 uartcr2 (1fde h ) rxdnc stopbr (initial value: **** * 000) rxdnc selection of rxd input noise rejection time 00: no noise rejection (hysteresis input) 01: rejects pulses shorter than 31/fc [s] as noise 10: rejects pulses shorter than 63/fc [s] as noise 11: rejects pulses shorter than 127/fc [s] as noise stopbr receive stop bit length 0: 1 bit 1: 2 bits write only note: when uartcr2 = ?01?, pulses longer than 96/fc [s] ar e always regarded as signals; when uartcr2 = ?10?, longer than 192/fc [s]; and when uartcr2 = ?11?, longer than 384/fc [s] figure 2.11.2 uart control register
TMP86FM48 2007-08-24 86fm48-96 7 6 5 4 3 2 1 0 uartsr (1fdd h ) perr ferr oerr rbfl tend tbep (initial value: 0000 11 ** ) perr parity error flag 0: no parity error 1: parity error ferr framing error flag 0: no framing error 1: framing error oerr overrun error flag 0: no overrun error 1: overrun error rbfl receive data buffer full flag 0: receive data buffer empty 1: receive data buffer full tend transmit end flag 0: transmitting 1: transmit end tbep transmit data buffer empty flag 0: transmit data buffer full 1: transmit data buffer empty read only note: when an inttxd is generated tbep is set to ?1? automatically. uart receive data buffer 7 6 5 4 3 2 1 0 rdbuf (1fdf h ) read only (initial value: 0000 0000) uart transmit data buffer 7 6 5 4 3 2 1 0 tdbuf (1fdf h ) write only (initial value: 0000 0000) figure 2.11.3 uart status register and data buffer registers
TMP86FM48 2007-08-24 86fm48-97 2.11.3 transfer data format in uart, a one-bit start bit (low level), stop bit (bit length selectable at high level, by uartcr1), and parity (select parity in uartcr1; even- or odd-numbered parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follow. table 2.11.1 transfer data format note: in order to switch the transmit data form at, perform transmit operations in the following sequence except for the initial setting. without parity/1 stop bit with parity/1 stop bit without parity/2 stop bit with parity/2 stop bit bit6 start pe 0 1 stbt 0 bit0 bit1 bit7 stop 1 bit6 start 0 1 bit0 bit1 bit7 stop 1 stop 2 bit6 start 1 0 bit0 bit1 bit7 parity stop 1 bit6 start 1 1 bit0 bit1 bit7 parity stop 1 stop 2 2 3 8 9 10 11 12 frame length
TMP86FM48 2007-08-24 86fm48-98 2.11.4 transfer rate the baud rate of uart is set of uartcr1. the example of the baud rate shown as follows. table 2.11.2 transfer rate source clock brg 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 when tc5 is used as the uart transfer rate (when uartcr1 = ?110?), the transfer clock and transfer rate are determined as follows: 2.11.5 data sampling the uart receiver keeps sampling input using the clock selected by uartcr1 until a start bit is detected in rxd pin input. rt clock starts detectin g ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bit (s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts). bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 2.11.4 data sampling transfer clock = tc5 source clock ttreg5 set value transfer rate = transfer clock 16 bit 0 start bit a) without noise rejection circuit b) with noise rejection circuit bit 0 start bit bit 0 start bit 1 2 3 4 5678 9 101112 13 14 15 01 23 4 5 6 7 8 9 10 11 rt0 bit 0 start bit 1 2 3 4 5678910111213141501234 5 6 7 8 9 1011 rt0 rxd pin rt clock rxd pin rt clock internal receive data internal receive data
TMP86FM48 2007-08-24 86fm48-99 2.11.6 stop bit length select a transmit stop bit length (1 or 2 bits) by uartcr1. 2.11.7 parity set parity/no parity by uartcr1; set parity type (odd- or even-numbered) by uartcr1. 2.11.8 transmit/receive (1) data transmit set uartcr1 to ?1?. read uartsr to check uartsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-clears uartsr, transfers the data to the transmit shift register and the data are sequentially output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using bits 0 to 2 in uartcr1. when data transmit starts, transmit buffer empt y flag uartsr is set to ?1? and an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, th e txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transmit does not start. (2) data receive set uartcr1 to ?1?. when data ar e received via the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted include a start bit and stop bit (s) and a parity bit if parity addition is specified. when stop bit (s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag uartsr is set and an intrxd interrupt is generated. select the data transfer baud rate using bits 0 to 2 in uartcr1. if an overrun error (oerr) occurs when data are received, the data are not transferred to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note: when a receive operation is disabled by setting uartcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-dis abling setting may not become valid. if a framing error occurs, be sure to perform a re-receive operation.
TMP86FM48 2007-08-24 86fm48-100 2.11.9 status flag/interrupt signal (1) parity error when parity determined using the receive data bits differs from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 2.11.5 generation of parity error (2) framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uart sr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 2.11.6 generation of framing error rxd p in shift register xxxx0 ** parity stop 1pxxxx0 pxxxx0 * uartsr intrxd reading uartsr then rdbuf clears perr. 1xxxx0 xxxx0 * rxd pin shift register xxx0 ** final bit stop uartsr intrxd reading uartsr then rdbuf clears ferr.
TMP86FM48 2007-08-24 86fm48-101 (3) overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 2.11.7 generation of overrun error (4) receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr. the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 2.11.8 generation of receive buffer full reading uartsr then rdbuf clears oerr. xxxx0 * 1xxxx0 rxd pin shift register xxx0 ** final bit stop uartsr intrxd rbfl = ?h? rdbuf yyyy reading uartsr then rdbuf clears rbfl. 1xxxx0 xxxx0 * xxxx rxd pin shift register xxx0 ** final bit stop uartsr intrxd rdbuf yyyy
TMP86FM48 2007-08-24 86fm48-102 (5) transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shift register and data transmit starts, transmit data buffer em pty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. figure 2.11.9 generation of transmit buffer empty (6) transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? the data transmit is stated after writing the tdbuf. figure 2.11.10 generation of transmit buffer empty bit0 * 1yyyy 1yyyy0 **** 1x *** 1xx shift register uartsr uartsr txd pin ***** 1 stop start data writing to tdbuf inttxd transmit clock a fter reading uartsr, writing tdbuf clears tbep. **** 1x ***** 1 final bit * 1xxxx bit0 stop 1yyyy0 zzzz yyyy data write tdbuf shift register xxxx uartsr inttxd txd pin start ***** 1 1xxxx0 data write start
TMP86FM48 2007-08-24 86fm48-103 2.12 serial bus interface (sbi-ver. d) the TMP86FM48 has a 1-channel serial bus interface which employs an i 2 c bus (a bus system by philips). the serial interface is connected to external devices through p51 (sda) and p50 (scl). the serial bus interface pins are also used for the p5 port. when used for se rial bus interface pins, set the p5 output latches of these pins to ?1?. wh en not used as serial bus interface pins, the p5 port is used as a normal i/o port. note 1: when p5 is used as serial bus interface pins, p50 and p51 should be set as a sink open drain output by clearing p5outcr to ?0?. note 2: the serial bus interface can be used on ly in normal1/2 and idle1/2 mode. it can not be used in idle0, slow1/2 and sleep0/1/2 mode. note 3: the i 2 c of TMP86FM48 can be used only in the standard mode of i 2 c. the fast mode and the high-speed mode can not be used. 2.12.1 configuration figure 2.12.1 serial bus interface (sbi) 2.12.2 control the following registers are used for contro l the serial bus interface and monitor the operation status. ? serial bus interface control register a (sbicra) ? serial bus interface control register b (sbicrb) ? serial bus interface data buffer register (sbidbr) ? i 2 c bus address register (i2car) ? serial bus interface status register (sbisr) intsbi interrupt request transfer control circuit i 2 c bus clock sync. + control shift register i 2 c bus data control scl input/ output control sbicrb/ sbisr sbidbr sbicra sbi control register b/ sbi status register i 2 c bus address register sbi data buffer register sbi control register a sda p50 (sda) (scl) p51 divider noise canceller noise canceller i2car fc/4
TMP86FM48 2007-08-24 86fm48-104 2.12.3 software reset a serial bus interface circuit has a software reset function, when a serial bus interface circuit is locked by an external noise, etc. to reset the serial bus interface circuit, write ?01?, ?10? into the swrst (bit1, 0 in sbicrb). 2.12.4 the data format of the i 2 c bus the data format of the i 2 c bus is shown in as below. s: start condition r/ w : direction bit ack: acknowledge bit p: stop condition figure 2.12.2 data format of i 2 c bus 1 1 or more 1 or more 1 or more 1 a c k a c k a c k a c k a c k data 1 1 slave address a c k a c k r / w r / w r / w p p p a c k a c k a c k s s s s (a) addressing format (b) addressing format (with restart) (c) free data format data 8 bits 1 to 8 bits 1 or more 1 data 1 to 8 bits slave address slave address data data data data 8 bits 8 bits 1 to 8 bits 1 to 8 bits 1 to 8 bits 8 bits 1 to 8 bits 1 1 1 1 1 1 1 1 1
TMP86FM48 2007-08-24 86fm48-105 2.12.5 i 2 c bus control the following registers are used to control the serial bus interface (sbi) and monitor the operation status of the i 2 c bus. serial bus interface control register a 7 6 5 4 3 2 1 0 sbicra (1fd9h) bc ack sck (initial value: 0000 * 000) ack = 0 ack = 1 bc number of clock bits number of clock bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 bc number of transferred bits 111 7 7 8 7 write only ack master mode slave mode 0: not generate a clock pulse for an acknowledgement. not count a clock pulse for an acknowledgement. ack acknowledgement mode specification 1: generate a clock pulse for an acknowledgement. count a clock pulse for an acknowledgement. r/w sck n at fc = 16 mhz at fc = 8 mhz at fc = 4 mhz 000: 001: 010: 011: 100: 101: 110: 4 5 6 7 8 9 10 reserved reserved reserved 60.6 khz 30.8 khz 15.5 khz 7.8 khz reserved reserved 58.8 khz 30.3 khz 15.4 khz 7.8 khz 3.9 khz 100.0 khz 55.6 khz 29.4 khz 15.2 khz 7.7 khz 3.9 khz 1.9 khz sck serial clock (fscl) selection (output on scl pin) [fscl = 1/(2 n + 1 /fc + 8/fc)] 111: reserved write only note 1: fc: high-frequency clock [hz], * : don?t care note 2: set the bc to ?000? before switching to 8-bit sio bus mode. note 3: sbicra cannot be used with any of read-modify-w rite instructions such as bit manipulation, etc. note 4: this i 2 c bus circuit does not support the fast mode . it supports the standar d mode only. although the i 2 c bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the i2c specification is not guaranteed in that case. serial bus interface data buffer register 7 6 5 4 3 2 1 0 sbidbr (1fdah) (initial value: **** **** ) r/w note 1: for writing transmitted data, start from the msb (bit7). note 2: the data which was written into sbidbr can not be read, since a write data buffer and a read buffer are independent in sbidbr. therefore, sbidbr cannot be used with any of read-modify-write instructions such as bit manipulation, etc. note 3: * : don?t care i 2 c bus address register 7 6 5 4 3 2 1 0 slave address i2car (1fdbh) sa6 sa5 sa4 sa3 sa2 sa1 sa0 als (initial value: 0000 0000) sa slave address selection als address recognition mode specification 0: slave address recognition 1: non slave address recognition write only note 1: i2car is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. note 2: do not set i2car to ?00h? to avoid the incorrect response of acknowledgment in slave mode. if ?00h? is set to i2car as the slave address and received ?01h ? in slave mode, the device might transmit the acknowledgment incorrectly. figure 2.12.3 serial bus interface control regi ster a, serial bus interface data buffer register and i 2 c bus address register
TMP86FM48 2007-08-24 86fm48-106 serial bus interface control register b 7 6 5 4 3 2 1 0 sbicrb (1fdch) mst trx bb pin sbim swrst1 s wrst0 (initial value: 0001 0000) mst master/slave selection 0: slave 1: master trx transmitter/receiver selection 0: receiver 1: transmitter bb start/stop generation 0: generate a stop condition when mst, trx and pin are ?1? 1: generate a start condition when mst, trx and pin are ?1? pin cancel interrupt service request 0: ? 1: cancel interrupt service request sbim serial bus interface operating mode selection 00: port mode (serial bus interface output disable) 01: reserved 10: i 2 c bus mode 11: reserved swrst1 swrst0 software reset start bit software reset starts by first writing ?10? and next writing ?01? write only note 1: switch a mode to port after confirming that the bus is free. note 2: switch a mode to i 2 c bus mode after confiming that the port is high level. note 3: sbicrb has write-only register and must not be used wi th any of read-modify-write instructions such as bit manipulation, etc. note 4: when the swrst (bit1, 0 in sbicrb) is written to ?01?, ?10? in i 2 c bus mode, software reset is occurred. in this case, the sbicra, i2car and sbisr registers ar e initialized and the bits of sbicrb except the sbim (bit3, 2 in sbicrb) are also initialized. serial bus interface status register 7 6 5 4 3 2 1 0 sbisr (1fdch) mst trx bb pin al aas ad0 lrb (initial value: 0001 0000) mst master/slave selection status monitor 0: slave 1: master trx transmitter/receiver selection status monitor 0: receiver 1: transmitter bb bus status monitor 0: bus free 1: bus busy pin interrupt service requests status monitor 0: requesting interrupt service 1: releasing interrupt service request al arbitration lost detection monitor 0: ? 1: arbitration lost detected aas slave address match detection monitor 0: not detect slave address match or ?general call? 1: detect slave address match or ?general call? ad0 ?general call? detection monitor 0: not detect ?general call? 1: detect ?general call? lrb last received bit monitor 0: last receive bit is ?0? 1: last receiv bit is ?1? read only figure 2.12.4 serial bus interface control regist er b and serial bus interface status register
TMP86FM48 2007-08-24 86fm48-107 (1) acknowledgement mode specification a. acknowledgment mode (ack = ?1?) to set the device as an acknowledgment mode, the ack (bit4 in sbicra) should be set to ?1?. when a serial bus interface circuit is a master mode, an additional clock pulse is generated for an acknowledge signal. in a slave mode, a clock is counted for the acknowledge signal. in the master transmitter mode, the sda pi n is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. in the master receiver mode, the sda pin is set to low level generation an acknowledge signal during additional clock pulse cycle. in a slave mode, when a received slav e address matches to a slave address which is set to the i2car or when a ?general call? is received, the sda pin is set to low level generating an acknowle dge signal. after the matching of slave address or the detection of ?general call?, in the transmitter, the sda pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. in a receiver, the sda pin is set to low level generation an acknowledge signal during additional clock pulse cycle after the matching of slave address or the detection of ?general call? the table 2.12.1 shows the scl and sda pins status in acknowledgment mode. table 2.12.1 scl and sda pins status in acknowledgement mode mode pin transmitter receiver scl an additional clock pulse is generated. master sda released in order to receive an acknowledge signal. set to low level generating an acknowledge signal scl a clock is counted for the acknowledge signal. when slave address matches or a general call is detected ? set to low level generating an acknowledge signal. slave sda after matching of slave address or general call released in order to receive an acknowledge signal. set to low level generating an acknowledge signal. b. non-acknowledgment mode (ack = ?0?) to set the device as a non-acknowledgem ent mode, the ack should be cleared to ?0?. in the master mode, a clock pulse for an acknowledge signal is not generated. in the slave mode, a clock for a acknowledge signal is not counted. (2) number of transfer bits the bc (bits7 to 5 in sbicra) is used to select a number of bits for next transmitting and receiving data. since the bc is cleared to ?000? as a start condition, a slave address and direction bit transmissions are always executed in 8 bits. other than these, the bc retains a specified value. (3) serial clock a. clock source the sck (bits2 to 0 in sbicra) is used to select a maximum transfer frequency output from the scl pin in the master mode. set a communication baud rate that meets the i 2 c bus specification, such as the shortest pulse width of t low , based on the equations shown below.
TMP86FM48 2007-08-24 86fm48-108 four or more machine cycles are required for both high and low levels of pulse width in the external clock which is input from scl pin. note: since the i 2 c of TMP86FM48 can not be used as the fast mode and the high-speed mode, do not set sck as the frequency that is over 100 khz. figure 2.12.5 clock source b. clock synchronization in the i 2 c bus, in order to drive a bus with a wired and, a master device which pulls down a clock pulse to low will, in th e first place, invalidate a clock pulse of another master device which gene rates a high-level clock pulse. the serial bus interface circuit has a clock synchronization function. this function ensures normal transfer even if there are two or more masters on the same bus. the example explains clock synchronization procedures when two masters simultaneously exist on a bus. figure 2.12.6 clock synchronization as master 1 pulls down the scl pin to the low level at point ?a?, the scl line of the bus becomes the low level. after detecting this situation, master 2 resets counting a clock pulse in the high level and sets the scl pin to the low level. master 1 finishes counting a clock pulse in the low level at point ?b? and sets the scl pin to the high level. since master 2 holds the scl line of the bus at the low level, master 1 waits for counting a clock pulse in the high level. after master 2 sets a clock pulse to the high level at po int ?c? and detects the scl line of the bus at the high level, master 1 starts counting a clock pulse in the high level. then, the master, which has finished the counting a clock pulse in the high level, pulls scl pin (master 1) scl pin (master 2) scl (bus) wait count start count reset a b c count restart sck (bits2 to 0 in the sbicra) n 000 001 010 011 100 101 110 4 5 6 7 8 9 10 1/fscl t low = 2 n /fc t high = 2 n /fc + 8/fc fscl = 1/(t low + t high ) fc: high-frequency clock t high t low t sckl t sckh t sckl , t sckh > 4 tcyc note: tcyc = 4/fc (in normal mode, idle mode)
TMP86FM48 2007-08-24 86fm48-109 down the scl pin to the low level. the clock pulse on the bus is determined by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected to the bus. (4) slave address and address re cognition mode specification when the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the als (bit0 in i2car) to ?0?, and set the sa (bits7 to 1 in i2car) to the slave address. when the serial bus interface circuit is used with a free data format not to recognize the slave address, set the als to ?1?. with a free data format, the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (5) master/slave selection to set a master device, the mst (bit7 in sbi crb) should be set to ?1?. to set a slave device, the mst should be cleared to ?0?. when a stop condition on the bus or an arbitration lost is detected, the mst is cleared to ?0? by the hardware. (6) transmitter/receiver selection to set the device as a transmitter, the trx (bit6 in sbicrb) should be set to ?1?. to set the device as a receiver, the trx should be cleared to ?0?. when data with an addressing format is transferred in the slav e mode, the trx is set to ?1? by a hardware if the direction bit (r/ w ) sent from the master device is ?1?, and is cleared to ?0? by a hardware if the bit is ?0?. in the master mo de, after an acknowledge signal is returned from the slave device, the trx is cleared to ?0? by a hardware if a transmitted direction bit is ?1?, and is set to ?1? by a hardware if it is ?0?. when an acknowledge signal is not returned, the current condition is maintained. when a stop condition on the bus or an arbitration lost is detected, the trx is cleared to ?0? by the hardware. table 2.12. 2 shows trx changing conditions in each mode and trx value after changing. table 2.12.2 trx changing conditions in each mode mode direction bit conditions trx after changing ?0? ?0? slave mode ?1? a received slave address is the same value set to i2car ?1? ?0? ?1? master mode ?1? ack signal is returned ?0? when a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not recognized. they are handled as data just after generating a start condition. the trx is not changed by a hardware.
TMP86FM48 2007-08-24 86fm48-110 (7) start/stop condition generation when the bb (bit5 in sbisr) is ?0?, a sl ave address and a direction bit which are set to the sbidbr are output on a bus after gene rating a start condition by writing ?1? to the mst, trx, bb and pin. it is necessary to set transmitted data to the sbidbr and set ack to ?1? beforehand. figure 2.12.7 start condition generation and slave address generation when the bb is ?1?, sequence of generating a stop condition is started by writing ?1? to the mst, trx and pin, and ?0? to the bb. do not modify the contents of mst, trx, bb and pin until a stop condition is generated on a bus. figure 2.12.8 stop condition generation when a stop condition is generated and the scl line on a bus is pulled-down to low level by another device, a stop condition is generated after releasing the scl line. the bus condition can be indicated by reading the contents of the bb (bit5 in sbisr). the bb is set to ?1? when a start condition on a bus is detected and is cleared to ?0? when a stop condition is detected. (8) interrupt service request and cancel when a serial bus interface circuit is in the master mode and transferring a number of clocks set by the bc and the ack is complete, a serial bus interface interrupt request (intsbi) is generated. in the slave mode, the conditions of generating intsbi are follows: ? at the end of acknowledge signal when the received slave address matches to the value set by the i2car ? at the end of acknowledge signal when a ?general call? is received ? at the end of transferring or receiving after matching of slave address or receiving of ?general call? when a serial bus interface interrupt request occurs, the pin (bit4 in sbisr) is cleared to ?0?. during the time that the pi n is ?0?, the scl pin is pulled-down to low level. either writing data to sbidbr or reading data from the sbidbr sets the pin to ?1?. the time from the pin being set to ?1? until the scl pin is released takes t low . although the pin (bit4 in sbicrb) can be set to ?1? by the program, the pin can not be cleared to ?0? by the program. note: if the arbitration lost occurs, when the slave address does not match, the pin is not cleared to ?0? even though intsbi is generated. scl pin sda pin start condition slave address and the direction bit a cknowledge si g nal 1 2 345678 9 a6 a5 a4 a3 a2 a1 a0 r/ w sda pin scl pin stop condition
TMP86FM48 2007-08-24 86fm48-111 (9) setting of i 2 c bus mode the sbim (bit3 and 2 in sbicrb) is used to set i 2 c bus mode. set the sbim to ?10? in order to set i 2 c bus mode. before setting of i 2 c bus mode, confirm serial bus interface pins in a high level, and then, write ?10? to sbim. and switch a port mode after confirming that a bus is free. (10) arbitration lost detection monitor since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data. data on the sda line is used for bus arbitration of the i 2 c bus. the following shows an example of a bus arbitration procedure when two master devices exist simultaneously on a bus. master 1 and master 2 output the same data until point ?a?. after that, when master 1 outputs ?1? and master 2 outputs ?0?, since the sda line of a bus is wired and, the sda line is pulled-down to the low level by master 2. when the scl line of a bus is pulled-up at point ?b?, the slave device reads data on the sda line, that is data in master 2. data transmitted from master 1 becomes invalid. the state in master 1 is called ?arbitration lost?. a master device which loses arbitration releases the sda pin an d the scl pin in order not to effect data transmitted from other masters with arbitration. when more than one master sends the same data at the first word, arbitration occurs continuously after the second word. figure 2.12.9 arbitration lost the serial bus interface circuit compares le vels of a sda line of a bus with its sda pin at the rising edge of the scl line. if the levels are unmatched, arbitration is lost and the al (bit3 in sbisr) is set to ?1?. when the al is set to ?1?, the mst and trx are cleared to ?0? and the mode is switched to a slave receiver mode. thus, the serial bus interface circuit stops output of clock pulses during data transfer after the al is set to ?1?. the al is cleared to ?0? by writing data to the sbidbr, reading data from the sbidbr or writing data to the sbicrb. sda (bus) sda pin becomes ?1? after losing arbitration. a b scl (bus) sda pin (master 2) sda pin (master 1)
TMP86FM48 2007-08-24 86fm48-112 figure 2.12.10 example of when a serial bus interface circuit is a master b (11) slave address match detection monitor in the slave mode, the aas (bit2 in sbisr) is set to ?1? when the received data is ?general call? or the received data ma tches the slave addre ss setting by i2car with an address recognition mode (als = 0). when a serial bus interface circuit operates in the free data format (als = 1), the aas is set to ?1? after receiving the first 1-word of data. the aas is cleared to ?0? by writing data to the sbidbr or reading data from the sbidbr. (12) general call detection monitor the ad0 (bit1 in sbisr) is set to ?1? when all 8-bit received data is ?0? immediately after a start condition in a slave mode. the ad0 is cleared to ?0? when a start or stop condition is detected on a bus. (13) last received bit monitor the sda value stored at the rising edge of the scl is set to the lrb (bit0 in sbisr). in the acknowledge mode, immediately after an intsbi interrupt request is generated, an acknowledge signal is read by reading the contents of the lrb. releasing sda pin and scl pin to hi gh level as losing arbitration. 1 2 3 4 5 6 7 8 9 1 2 3 d7a d6a d5a d4a d3a d2a d1a d0a d7a? d6a? d5a? d7b d6b scl pin sda pin scl pin sda pin a l mst trx a ccessed to sbidbr or sbicrb master a master b 1 2 3 4 56789 stop clock output intsbi
TMP86FM48 2007-08-24 86fm48-113 2.12.6 data transfer of i 2 c bus (1) device initialization for initialization of device, set the ack in sbicra to ?1? and the bc to ?000?. specify the data length to 8 bits to count clocks for an acknowledge signal. set a transfer frequency to the sck in sbicra. next, set the slave address to the sa in i2car and clear the als to ?0? to set an addressing format. after confirming that the serial bus interface pin is high level, for specifying the default setting to a slave receiver mode, cl ear ?0? to the mst, trx and bb in sbicrb, set ?1? to the pin, ?10? to the sbim, and ?00? to bits swrst1 and swrst0. note: the initialization of a serial bus interf ace circuit must be complete within the time from all devices which are connected to a bus have initialized to and device does not generate a start condition. if not, the dat a can not be received correctly because the other device starts transferring before an end of the initialization of a serial bus interface circuit. (2) start condition and slave address generation confirm a bus free status (bb = 0). set the ack to ?1? and specify a slave addre ss and a direction bit to be transmitted to the sbidbr. by writing ?1? to the mst, trx, bb and pin, the start condition is generated on a bus and then, the slave address and the direction bit which are set to the sbidbr are output. an intsbi interrupt request occurs at the 9th falling edge of a scl clock cycle, and the pin is cleared to ?0?. the scl pin is pulled-down to the low level while the pin is ?0?. when an interrupt request occurs, the trx changes by the hardware according to the direction bit only when an acknowledge signal is returned from the slave device. note 1: do not write a slave addr ess to be output to the sbidbr while data is transferred. if data is written to the sbidbr, data to been outputting may be destroyed. note 2: the bus free must be confirmed by software within 98.0 s (the shortest transmitting time according to the i 2 c bus standard) after setting of the slave address to be output. only when the bus free is confirmed, set ?1? to the mst, trx, bb, and pin to generate the start conditi ons. if the writing of slave address and setting of mst, trx, bb and pin doesn?t finish within 98.0 s, the other masters may start the transferring and the slave address data written in sbidbr may be broken. figure 2.12.11 start condition generation and slave address transfer scl pin sda pin start condition slave address + direction bit a cknowledge signal from a slave device 1 2 345678 9 a6 a5 a4 a3 a2 a1 a0 r/ w pin intsbi interrupt request
TMP86FM48 2007-08-24 86fm48-114 (3) 1-word data transfer check the mst by the intsbi interrupt process after an 1-word data transfer is completed, and determine whether the mode is a master or slave. a. when the mst is ?1? (master mode) check the trx and determine whether the mode is a transmitter or receiver. 1. when the trx is ?1? (transmitter mode) test the lrb. when the lrb is ?1?, a receiver does not request data. implement the process to generate a stop condition (described later) and terminate data transfer. when the lrb is ?0?, the receiver requests next data. when the next transmitted data is other than 8 bits, set the bc, set the ack to ?1?, and write the transmitted data to the sbidbr. after writing the data, the pin becomes ?1?, a serial clock pulse is generated fo r transferring a next 1 word of data from the scl pin, and then the 1 word of data is transmitted. after the data is transmitted, and an intsbi interrupt request occurs. the pin become ?0? and the scl pin is set to low level. if the data to be transferred is more than one word in length, repeat the procedure from the lrb test above. figure 2.12.12 example of when bc = ?000?, ack = ?1? 2. when the trx is ?0? (receiver mode) when the next transmitted data is other than of 8 bits, set the bc again. set the ack to ?1? and read the received data from the sbidbr (reading data is undefined immediately after a slave addr ess is sent). after the data is read, the pin becomes ?1?. a serial bus interface circuit outputs a serial clock pulse to the scl to transfer next 1-word of data and sets the sda pin to ?0? at the acknowledge signal timing. an intsbi interrupt request occurs an d the pin becomes ?0?. then a serial bus interface circuit outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that rece ived data is read from the sbidbr. figure 2.12.13 example of when bc = ?000?, ack = ?1? scl pin sda pin a cknowledge signal from a receiver 1 2 3456789 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt request d0 write to sbidbr scl pin sda pin a cknowledge signal to a transmitter 1 2 3456789 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt d0 read sbidbr new d7
TMP86FM48 2007-08-24 86fm48-115 to make the transmitter terminate transmit, clear the ack to ?0? before reading data which is 1-word before the last data to be received. a serial bus interface circuit does not generate a clock pulse for the acknowledge signal by clearing ack. in the interrupt routine of end of transmission, when the bc is set to ?001? and read the data, pin is se t to ?1? and generates a clock pulse for a 1-bit data transfer. in this case, since the master device is a receiver, the sda line on a bus keeps the high-level. the transmitter receives the high-level signal as an ack signal. th e receiver indicates to the transmitter that data transfer is complete. after 1-bit data is received and an interrupt request has occurred, generates the stop condition to terminate transmit, generate the stop condition to terminate data transfer. figure 2.12.14 termination of data transfer in master receiver mode b. when the mst is ?0? (slave mode) in the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode after losing arbitration. in the slave mode, the conditions of generating intsbi are follows: ? when the received slave address matches to the value set by the i2car ? when a ?general call? is received ? at the end of transferring or receiving after matching of slave address or receiving of ?general call? a serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. and an intsbi interrupt request occurs when word data transfer terminates after losing arbitration. the behavior of intsbi and pin after losing arbitration are shown in table 2.12.3. table 2.12.3 the behavior of intsbi and pin after losing arbitration when the arbitration lost occurs during transmission of slave address as a master when the arbitration lost occurs during transmission of data as a master transmit mode intsbi intsbi is generated at the termination of word data. pin when the slave address matches the value set by i2car, the pin is cleared to ?0? by generating of intsbi. when the slave address doesn't match the value set by i2car, the pin keeps ?1?. pin keeps ?1?. scl pin sda pin a cknowledge signal sent to a transmitter 1 2 345678 1 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt request d0 ?0? ack read sbidbr ?001? bc read sbidbr
TMP86FM48 2007-08-24 86fm48-116 check the al (bit3 in the sbisr), the trx (bit6 in the sbisr), the aas (bit2 in the sbisr), and the ad0 (bit1 in the sbisr) and implements processes according to conditions listed in table 2.12.4. table 2.12.4 operation in the slave mode trx al aas ad0 conditions process 1 1 0 a serial bus interfac e circuit loses arbitration when transmitting a slave address. and receives a slave address of which the value of the direction bit sent from another master is ?1?. 1 0 in the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is ?1?. set the number of bits in 1 word to the bc and write transmitted data to the sbidbr. 1 0 0 0 in the slave transmitter mode, 1-word data is transmitted. test the lrb. if the lrb is set to ?1?, set the pin to ?1? since the receiver does not request next data. then, clear the trx to ?0? to release the bus. if the lrb is set to ?0?, set the number of bits in 1 word to the bc and write transmitted data to the sbidbr since the receiver requests next data. 1 1/0 a serial bus interfac e circuit loses arbitration when transmitting a slave address. and receives a slave address of which the value of the direction bit sent from another master is ?0? or receives a ?general call?. read the sbidbr for setting the pin to ?1? (reading dummy data) or write ?1? to the pin. 1 0 0 a serial bus interfac e circuit loses arbitration when transmitting a slave address or data. and terminates transferring word data. a serial bus interface circuit is changed to slave mode. to clear al to ?0?, read the sbidbr or write the data to sbidbr. 1 1/0 in the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is ?0? or receives ?general call?. read the sbidbr for setting the pin to ?1? (reading dummy data) or write ?1? to the pin. 0 0 0 1/0 in the slave receiver mode, a serial bus interface circuit term inates receiving of 1-word data. set the number of bits in 1-word to the bc and read received data from the sbidbr. note: in the slave mode, if the slave address set in i2car is ?00000000b?, the trx changes to ?1? by receiving the start byte data ?00000001b?. (4) stop condition generation when the bb is ?1?, a sequence of generating a stop condition is started by setting ?1? to the mst, trx and pin, and clear ?0? to the bb. do not modify the contents of the mst, trx, bb, pin until a stop condition is generated on a bus. when a scl line on a bus is pulled-down by other devices, a serial bus interface circuit generates a stop conditio n after they release a scl line. figure 2.12.15 stop condition generation ?1? mst ?1? trx ?0? bb ?1? pin scl pin stop condition sda pin bb (read) pin
TMP86FM48 2007-08-24 86fm48-117 (5) restart restart is used to change the direction of data transfer between a master device and a slave device during transferring data. the following explains how to restart a serial bus interface circuit. clear ?0? to the mst, trx and bb and set ?1? to the pin. the sda pin retains the high-level and the scl pin is released. since a stop condition is not generated on a bus, a bus is assumed to be in a busy state from othe r devices. test the bb until it becomes ?0? to check that the scl pin a serial bus interface circuit is released. test the lrb until it becomes ?1? to check that the scl line on a bus is not pulled-down to the low level by other devices. after confirming that a bus stays in a free state, generate a start condition with procedure (2). in order to meet setup time when restarting, take at least 4.7 s of waiting time by software from the time of restarting to confir m that a bus is free until the time to generate a start condition. note: when restarting after receiving in master recever mode, because the device doesn?t send an acknowledgment as a last data, the level of scl line can not be confirmed by reading lrb. therefore, co nfirm the status of scl line by reading p5prd register. figure 2.12.16 timing diagram when restarting start condition sda (pin) scl pin ?0? mst ?0? trx ?0? bb ?1? pin scl (bus) lrb bb pin ?1? mst ?1? trx ?1? bb ?1? pin 4.7 s (min)
TMP86FM48 2007-08-24 86fm48-118 2.13 sio (synchronous serial interface) the TMP86FM48 contains two channels of sio (s ynchronous serial interface). these serial interfaces connect to an external device via si1, si2, so1, so2, sck1 and sck2 pins. the si1, si2, so1, so2, sck1 and sck2 pins respectively are shared wi th p05, p11, p06, p10, p07 and p12. when these pins are used as serial interface, the output latches for each port of p0 and p1 must be set to ?1?. because sio1 and sio2 are the same except that the registers and the function pin for each sio are assigned as different specification, explanation here is made of only sio1. the registers for sio1 and sio2 are listed in table below. table 2.13.1 the registers for sio1 and sio2 sio1 sio2 register address register address sio control register sio1cr 0017h sio2cr 001bh sio status register sio1sr 0018h sio2sr 001ch sio receive buffer register sio1rdb 0019h sio2rdb 001dh sio transmit buffer register sio1tdb 0019h sio2tdb 001dh 2.13.1 configuration note: set the register of port correctly for the port assigned as serial interface pins. for details, see the description of the input/output port control register. figure 2.13.1 synchronous serial interface sck1 pin so1 pin (serial data output) si1 pin (serial data input) port ( note ) shift register on transmitte r shift register on receive r internal data bus shift clock intsio1 interrupt sio1sr sio1cr control circuit sio1tdb sio1rdb msb/lsb selection port ( note ) to bus port ( note ) internal clock input
TMP86FM48 2007-08-24 86fm48-119 2.13.2 control the sio is controlled using the serial interface control register (sio1cr). the operating status of the serial interface can be inspected by reading the status register (sio1sr). serial interface control register 1 7 6 5 4 3 2 1 0 sios sioinh siom siodir sck (initial value: 0000 0000) sios specify start/stop of transfer 0: stop 1: start sioinh forcibly stops transfer (note 1) 0: ? 1: forcibly stop (automatically cleared to ?0? after stopping) siom selects transfer mode 00: transmit mode 01: receive mode 10: transmit/receive mode 11: reserved siodir selects direction of transfer 0: msb (transfer beginning with bit7) 1: lsb (transfer beginning with bit0) normal 1/2 or idle 1/2 mode tbtcr = ?0? tbtcr = ?1? slow/sleep mode 000 fc/2 12 fs/2 4 fs/2 4 001 fc/2 8 fc/2 8 reserved 010 fc/2 7 fc/2 7 reserved 011 fc/2 6 fc/2 6 reserved 100 fc/2 5 fc/2 5 reserved 101 fc/2 4 fc/2 4 reserved 110 fc/2 3 fc/2 3 reserved sck selects serial clock 111 external clock (input from sck1 pin) r/w note 1: when sio1cr is set to ?1?, sio1cr, sio1sr register, sio1rdb register and stotdb register are initialized. note 2: transfer mode, direction of transfer and serial clock must be sele ct during the trans fer is stopping (when sio1sr = ?0?). note 3: fc: high frequency clock [hz], fs: low frequency clock, * : don?t care figure 2.13.2 serial interface control register sio1cr ( 0017h )
TMP86FM48 2007-08-24 86fm48-120 serial interface status register 7 6 5 4 3 2 1 0 siof sef txf rxf txerr rxerr (initial value: 0010 00 ** ) siof serial transfer operation status monitor 0: transfer finished 1: transfer in progress sef number of clocks monitor 0: 8 clocks 1: 1 to 7 clocks txf transmit buffer empty flag 0: data exists in transmit buffer 1: no data exists in transmit buffer rxf receive buffer full flag 0: no data exists in receive buffer 1: data exists in receive buffer read only txerr transfer operation error flag read 0: ? (no error exist) 1: transmit buffer under run occurs in an external clock mode. write 0: clear the flag 1: ? (a write of ?1? to this bit is ignored) rxerr receive operation error flag read 0: ? (no error exist) 1: receive buffer over run occurs in an external clock mode. write 0: clear the flag 1: ? (a write of ?1? to this bit is ignored) r/w note 1: the operation error flag (txerr and rxerr) ar e not automatically cleared by stopping transfer with sio1cr = ?0?. therefore, set these bits to ?0 ? for clearing these error flag. or set sio1cr to ?1?. note 2: * : don?t care figure 2.13.3 serial interface status register receive buffer register 7 6 5 4 3 2 1 0 read only (initial value: 0000 0000) transmit buffer register 7 6 5 4 3 2 1 0 write only (initial value: **** **** ) note 1: sio1tdb is write only register. a bit manipulat ion should not be performed on the transmit buffer register using a read-modify-write instruction. note 2: the sio1tdb should be written after checking sio1sr = ?1?. when sio1sr is ?0?, the writing data can't be transferred to sio1tdb even if write instruction is executed to sio1tdb. note 3: * : don?t care figure 2.13.4 receive buffer register and transmit buffer register sio1sr ( 0018h ) sio1rdb ( 0019h ) sio1tdb ( 0019h )
TMP86FM48 2007-08-24 86fm48-121 2.13.3 functional description (1) serial clock a. clock source the serial clock can be selected by using sio1cr. when the serial clock is changed, the writing instruction to sio1cr should be executed while the transfer is stopped (when sio1sr = ?0?). 1. internal clock setting the sio1cr to other than ?111? outputs the clock (shown in table 2.8.2) as serial clock outputs from sck1 pin. at the before beginning or finishing of a transfer, sck1 pin is kept in high level. when writing (in the transmit mode) or reading (in the receive mode) data can not follow the serial clock rate, an automatic-wait function is executed to stop the serial clock automatically and hold the next shift operation until reading or writing is completed. the maximum time from releasing the automatic-wait function by reading or writing a data is 1 cycle of the selected serial clock until the serial clock comes out from sck1 pin. figure 2.13.5 automatic-wait function (example of transmit mode) table 2.13.2 serial clock rate (fc = 16 mhz, fs = 32.768khz) normal1/2, idle1/2 mode tbtcr = ?0? tbtcr = ?1? slow1/2, sleep1/2 mode serial clock baud rate serial clock baud rate serial clock baud rate 000 fc/2 12 3.906 kbps fs/2 4 2048 bps fs/2 4 2048 bps 001 fc/2 8 62.5 kbps fc/2 8 62.5 kbps reserved ? 010 fc/2 7 125 kbps fc/2 7 125 kbps reserved ? 011 fc/2 6 250 kbps fc/2 6 250 kbps reserved ? 100 fc/2 5 500 kbps fc/2 5 500 kbps reserved ? 101 fc/2 4 1.00 mbps fc/2 4 1.00 mbps reserved ? 110 fc/2 3 2.00 mbps fc/2 3 2.00 mbps reserved ? a utomatic wait is released by writing sio1tdb. a7 sck1 pin output so1 pin sio1tdb a automatic wait a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 b sio1cr
TMP86FM48 2007-08-24 86fm48-122 2. external clock when an external clock is selected by setting sio1cr to ?111?, the clock via the sck1 pin from an external source is used as the serial clock. to ensure shift operation, the serial clock pulse width must be 4/fc or more for both ?h? and ?l? levels. figure 2.13.6 external clock b. shift edges the leading edge is used to transmit data, and the trailing edge is used to receive data. 1. leading edge shift data is shifted on leading edges of the serial clock (falling edges of the sck1 pin input/output). 2. trailing edge shift data is shifted on trailing edges of the serial clock (rising edges of the sck1 pin input/output). figure 2.13.7 shift edge t sckl , t sckh 4/fc t sckl t sckh vil vih (b) trailing edge shift (example of msb transfer) sck1 pin shift registe r bit7 bit6 01234567 bit0 (a) leading edge shift (example of msb transfer) bit5 bit4 bit3 bit2 bit1 sck1 pin si1 pin shift registe r * 0123456 ** 012345 *** 01234 **** 0123 ***** 012 ****** 01 ******* 0 ********* bit7 bit6 ********* bit0 bit5 bit4 bit3 bit2 bit1 7 ******* 67 ****** 567 ***** 4567 **** 34567 *** 234567 ** 1234567 * 01234567 sio1cr sio1cr so1 pin shift out sck1 pin
TMP86FM48 2007-08-24 86fm48-123 (2) transfer bit direction transfer data direction can be selected by using sio1cr. the transfer data direction can?t be set individually for transmit and receive operations. when the data direction is changed, the writing instruction to sio1cr should be executed while the transfer is stopped (when sio1sr = ?0?). figure 2.13.8 transfer bit direct ion (example of transmit mode) a. transmit mode 1. msb transmit mode msb transmit mode is selected by setting sio1cr to ?0?, in which case the data is transferred sequentially beginning with the most significant bit (bit7). 2. lsb transmit mode lsb transmit mode is selected by setting sio1cr to ?1?, in which case the data is transfer red sequentially beginning with the least significant bit (bit0). b. receive mode 1. msb receive mode msb receive mode is selected by setting sio1cr to ?0?, in which case the data is received sequentially beginning with the most significant bit (bit7). 2. lsb receive mode lsb receive mode is selected by setting sio1cr to ?1?, in which case the data is received sequentially beginning with the least significant bit (bit0). c. transmit/receive mode 1. msb transmit/receive mode msb transmit/receive mode are selected by setting sio1cr to ?0? in which case the data is transferred sequentially beginning with the most significant bit (bit7) and the data is received sequentially beginning with the most significant (bit7). sck1 pin sio1tdb a7 a6 a a0 (a) msb transfe r a5 a4 a3 a2 a1 sck1 pin sio1tdb so1 pin (b) lsb transfe r sio1cr sio1cr so1 pin a0 a1 a a7 a2 a3 a4 a5 a6 shift out shift out
TMP86FM48 2007-08-24 86fm48-124 2. lsb transmit/receive mode lsb transmit/receive mode are selected by setting sio1cr to ?1?, in which case the data is transferred sequentially beginning with the least significant bit (bit0) and the data is received sequentially beginning with the least significant (bit0).
TMP86FM48 2007-08-24 86fm48-125 (3) transfer modes transmit, receive and transmit/receive mode are selected by using sio1cr. a. transmit mode transmit mode is selected by writing ?00? to sio1cr. 1. starting the transmit operation transmit mode is selected by setting ?00? to sio1cr. serial clock is selected by using sio1cr. transfer direction is selected by using sio1cr. when a transmit data is written to the transmit buffer register (sio1tdb), sio1sr is cleared to ?0?. after sio1cr is set to ?1?, sio1 sr is set synchronously to ?1? the falling edge of sck1 pin. the data is transferred sequentially st arting from so1 pin with the direction of the bit specified by sbidir, synchronizing with the sck1 pin's falling edge. sio1sr is kept in high level, between the first clock falling edge of sck1 pin and eighth clock falling edge. sio1sr is set to ?1? at the rising edge of sck1 pin after the data written to the sio1tdb is transferred to shift register, then the intsio1 interrupt request is generated, synchronizing with the next falling edge on sck1 pin. note 1: in internal clock operation, when sio1cr is set to ?1?, transfer mode does not start without writing a transmit data to the transmit buffer register (sio1tdb). note 2: in internal clock operation, when the sio1cr is set to ?1?, sio1tdb is transferred to shift regist er after maximum 1-cycle of serial clock frequency, then a serial clock is output from sck1 pin. note 3: in external clock operation, when the falling edge is input from sck1 pin after sio1cr is set to ?1?, sio1 tdb is transferred to shift register immediately. 2. during the transmit operation when data is written to sio1tdb, sio1sr is cleared to ?0?. in internal clock operation, in case a next transmit data is not written to sio1tdb, the serial clock stops to ?h? level by an automatic-wait function when all of the bit set in the sio1tdb has been transmitted. automatic-wait function is released by writing a transmit data to sio1tdb. then, transmit operation is restarted after maximum 1-cycle of serial clock. when the next data is written to the sio1tdb before termination of previous 8-bit data with sio1sr = ?1?, the next data is continuously transferred after transmission of previous data. in external clock operation, after sio1sr is set to ?1?, the transmit data must be written to sio1tdb before the shift operation of the next data begins. if the transmit data is not written to sio1tdb, transmit error occurs immediately after shift operation is started. then, intsio1 interrupt request is generated after sio1sr is set to ?1?.
TMP86FM48 2007-08-24 86fm48-126 3. stopping the transmit operation there are two ways for stopping transmits operation. ? the way of clearing sio1cr. when sio1cr is cleared to ?0?, transmit operation is stopped after all transfer of the data is finished. when transmit operation is finished, sio1sr is cleared to ?0? and so1 pin is kept in high level. in external clock operation, sio1cr must be cleared to ?0? before sio1sr is set to ?1? by beginning next transfer. ? the way of setting sio1cr. transmit operation is stopped immediately after sio1cr is set to ?1?. in this case, sio1cr, sio1sr register, sio1rdb register and sio1tdb register are initialized. figure 2.13.9 example of internal clock and msb transmit mode clearing sios sck1 pin output sio1cr sio1sr so1 pin sio1sr sio1sr a 6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a 7 b0 c6 c5 c4 c3 c2 c1 c0 automatic wait writing transmit data a writing transmit data b writing transmit data c sio1tdb intsio1 interrupt request a b c start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-127 figure 2.13.10 example of external clock and msb transmit mode figure 2.13.11 hold time of the end of transmit mode t sodh sck1 pin sio1sr so1 pin 4/fc t sodh 8/fc clearin g sios sck1 pin input sio1cr sio1sr so1 pin sio1sr sio1sr a 6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a 7 b0 c6 c5 c4 c3 c2 c1 c0 writing transmit data a writing transmit data b writing transmit data c sio1tdb intsio1 interrupt re q uest writing transmit data a b c start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-128 4. transmit error processing transmit errors occur on the following situation. ? shift operation starts before writing next transmit data to sio1tdb in external clock operation. if transmit errors occur during tr ansmit operation, sio1sr is set to ?1? immediately after starting shift operation. synchronizing with the next serial clock falling edge, intsio1 interrupt request is generated. if shift operation starts before writing data to sio1tdb after sio1cr is set to ?1?, sio1sr is set to ?1? immediately after shift operation is started and then intsio1 interrupt request is generated. so1 pin is kept in high level when sio1sr is set to ?1?. when transmit error occurs, transmit operation must be forcibly stop by writing sio1cr to ?1?. in this case, sio1cr, sio1sr register, sio1rdb register and sio1tdb register are initialized. figure 2.13.12 example of transmit error processing sck1 pin input sio1cr sio1sr so1 pin txf sio1sr a 6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 a 7 b0 writing transmit data a writing transmit data b sio1tdb intsio1 interrupt re q uest a b unknown sio1sr sio1cr start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-129 b. receive mode the receive mode is selected by writing ?01? to sio1cr. 1. starting the receive operation receive mode is selected by setting ?01? to sio1cr. serial clock is selected by using sio1cr. transfer direction is selected by using sio1cr. after sio1cr is set to ?1?, sio1 sr is set synchronously to ?1? the falling edge of sck1 pin. synchronizing with the sck1 pin?s rising edge, th e data is received sequentially from si1 pin with the direction of the bit specified by sbidir. sio1sr is kept in high level, between the first clock falling edge of sck1 pin and eighth clock falling edge. when 8-bit data is received, the data is transferred to sio1rdb from shift register. intsio1 interrupt request is generated and sio1sr is set to ?1?. note: in internal clock operation, when the sio1cr is set to ?1?, the serial clock is generated from sck1 pin after maximum 1-cycle of serial clock frequency. 2. during the receive operation the sio1sr is cleared to ?0? by reading a data from sio1rdb. in the internal clock operation, the serial clock stops to ?h? level by an automatic-wait function when the all of the 8-bit data has been received. automatic-wait function is released by reading a received data from sio1rdb. then, receive operation is restarted af ter maximum 1-cycle of serial clock. in external clock operation, after sio1sr is set to ?1?, the received data must be read from sio1rdb before the next data shift-in operation is finished. if received data is not read out from sio1rdb, rece ive error occurs immediately after shift operation is finished. then intsio interrupt request is generated after sio1sr is set to ?1?. 3. stopping the receive operation there are two ways for stopping the receive operation. ? the way of clearing sio1cr. when sio1cr is cleared to ?0?, receive operation is stopped after all of the data is finished to receive. when receive operation is finished, sio1sr is cleared to ?0?. in external clock operation, sio1cr must be cleared to ?0? before sio1sr is set to ?1? by starting the next shift operation. ? the way of setting sio1cr. receive operation is stopped immediately after sio1cr is set to ?1?. in this case, sio1cr , sio1sr register, sio1rdb register and sio1tdb register are initialized.
TMP86FM48 2007-08-24 86fm48-130 figure 2.13.13 example of internal clock and msb receive mode figure 2.13.14 example of exter nal clock and msb receive mode clearin g sios sck1 pin output sio1cr sio1sr si1 pin sio1sr sio1sr a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a7 b0 c6 c5 c4 c3 c2 c1 c0 automatic wait reading received data a reading received data b reading received data c sio1rdb intsio1 interrupt request ab c start shift operation start shift operation start shift operation clearin g sios sck1 pin input sio1cr sio1sr si1 pin sio1sr sio1sr a 6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a 7 b0 c6 c5 c4 c3 c2 c1 c0 reading received data a reading received data b reading received data c sio1rdb intsio1 interrupt request a bc reading received data start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-131 4. receive error processing receive errors occur on the following situation. to protect sio1rdb and the shift register contents, the received data is ignored while the sio1sr is ?1?. ? shift operation is finished before reading out received data from sio1rdb at sio1sr is ?1? in an external clock operation. if receive error occurs, set the siocr1 to ?0? for reading the data that received immediately before er ror occurence. and read the data from sio1rdb. data in shift register (at errors occur) can be read by reading the sio1rdb again. when sio1sr is cleared to ?0? after reading the received data, sio1sr is cleared to ?0?. after clearing sio1cr to ?0?, when 8-bit serial clock is input to sck1 pin, receive operation is stopped. to restart the receive operation, confirm that sio1sr is cleared to ?0?. if the receive error occurs, set the siocr1 to ?1? for stopping the receive operation immediately. in this case, sio1cr, sio1sr register, sio1rdb register and sio1tdb register are initialized. figure 2.13.15 example of receive error processing note: if receive error is not correc ted, an interrupt request does not generate after the error occurs. sck1 pin input sio1cr sio1sr si1 pin sio1sr sio1sr a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a7 b0 c6 c5 c4 c3 c2 c1 c0 reading received data a reading received data b sio1rdb intsio1 interrupt re q uest ab sio1sr write a ?0? after reading the received data when a receive error occurs. start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-132 c. transmit/receive mode the transmit/receive mode are selected by writing ?10? to sio1cr. 1. starting the transmit/receive operation transmit/receive mode is selected by writing ?10? to sio1cr. serial clock is selected by using sio1cr. transfer direction is selected by using sio1cr. when a transmit data is written to the transmit buffer register (sio1tdb), sio1sr is cleared to ?0?. after sio1cr is set to ?1?, sio1sr is set synchronously to the falling edge of sck1 pin. the data is transferred sequentially st arting from so1 pin with the direction of the bit specified by sio1cr, synchronizing with the sck1 pin?s falling edge. and receiving operation also starts with the direction of the bit specified by sio1cr, synchronizing with the sck1 pin's rising edge. sio1sr is kept in high level between the first clock falling edge of sck1 pin and eighth clock falling edge. sio1sr is set to ?1? at the rising edge of sck1 pin after the data written to the sio1tdb is transferred to shift register. when 8-bit data has been received, the received data is transferred to sio1rdb from shift register, then the intsio1 interrupt request occurs, synchronizing with setting sio1sr to ?1?. note 1: in internal clock operation, when the sio1cr is set to ?1?, sio1tdb is transferred to shift regist er after maximum 1-cycle of serial clock frequency, then a serial clock is output from sck1 pin. note 2: in external clock operation, when the falling edge is input from sck1 pin after sio1cr is set to ?1 ?, sio1tdb is transferred to shift register immediately. when the rising edge is input from sck1 pin, receive operation also starts. 2. during the transmit/receive operation when data is written to sio1tdb, sio1sr is cleared to ?0? and when a data is read from sio1rdb, sio1sr is cleared to ?0?. in internal clock operation, in case of the condition described below, the serial clock stops to ?h? level by an automatic-wait function when all of the bit set in the data has been transmitted. ? next transmit data is not written to sio1tdb after reading a received data from sio1rdb ? received data is not read from sio1rdb after writing a next transmit data to sio1tdb ? neither sio1tdb nor sio1rdb is accessed after transmission. the automatic wait function is released by writing the next transmit data to sio1tdb after reading the received data from sio1rdb, or reading the received data from sio1rdb after writing the next data to sio1tdb. then, transmit/receive operation is restarted after maximum 1 cycle of serial clock.
TMP86FM48 2007-08-24 86fm48-133 in external clock operation, reading the received data from sio1rdb and writing the next data to sio1tdb must be finished before the shift operation of the next data begins. if the transmit data is not written to sio1tdb after sio1sr is set to ?1?, transmit error occurs immediat ely after shift operation is started. when the transmit error occurred, sio1sr is set to ?1?. if received data is not read out from sio1rdb before next shift operation starts after setting sio1sr to ?1?, receive error occurs immediately after shift operation is finished. when the receive error has occurred, sio1sr is set to ?1?.
TMP86FM48 2007-08-24 86fm48-134 3. stopping the transmit/receive operation there are two ways for stopping the transmit/receive operation. ? the way of clearing sio1cr. when sio1cr is cleared to ?0?, transmit/receive operation is stopped after all transfer of the data is finished. when transmit/receive operation is finished, sio1sr is cleared to ?0? and so1 pin is kept in high level. in external clock operation, sio1cr must be cleared to ?0? before sio1sr is set to ?1? by beginning next transfer. ? the way of setting sio1cr. transmit/receive operation is stopped immediately after sio1cr is set to ?1?. in this case, sio1cr, sio1sr register, sio1rdb register and sio1tdb register are initialized. figure 2.13.16 example of internal clock and msb transmit/receive mode sck1 pin output sio1cr sio1sr so1 pin txf sio1sr a 6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a 7 b0 c6 c5 c4 c3 c2 c1 c0 writing transmit data a reading received data e sio1rdb intsio1 interrupt re q uest de sio1sr si1 pin d6 d5 d4 d3 d2 d1 d0 e7 e6 e5 e4 e3 e2 e1 f7 d7 e0 f6 f5 f4 f3 f2 f1 f0 a b c writing transmit data b f reading received data f reading received data d writing transmit data c automatic wait clearing sios sio1tdb automatic wait start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-135 figure 2.13.17 example of external clock and msb transmit/receive mode sck1 pin input sio1cr sio1sr so1 pin sio1sr sio1sr a 6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a 7 b0 c6 c5 c4 c3 c2 c1 c0 writing transmit data a reading received data e sio1rdb intsio1 interrupt re q uest de sio1sr si1 pin d6 d5 d4 d3 d2 d1 d0 e7 e6 e5 e4 e3 e2 e1 f7 d7 e0 f6 f5 f4 f3 f2 f1 f0 a b c writing transmit data b f reading received data f reading received data d writing transmit data c clearing sios sio1tdb writing transmit data reading received data start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-136 4. transmit/receive error processing transmit/receive errors occur on the following situation. corrective action is different, which errors occur transmits or receives. transmit errors transmit errors occur on the following situation. ? shift operation starts before writing next transmit data to sio1tdb in external clock operation. if transmit errors occur during tr ansmit operation, sio1sr is set to ?1? immediately after starting shift operation. and intsio1 interrupt request is generated after all of the 8-bit data has been received. if shift operation starts before writing data to sio1tdb after sio1cr is set to ?1?, sio1sr is set immediately after starting shift operation. and intsio1 interrupt request is generated after all of the 8-bit data has been received. so1 pin is kept in high level when sio1sr is set to ?1?. when transmit error occurs, transmit operation must be forcibly stop by writing sio1cr to ?1? after the received data is read from sio1rdb. in this case, sio1cr, sio1sr register, sio1rdb register and sio1tdb register are initialized. figure 2.13.18 example of transmit/r eceive (transmit) error processing sck1 pin input sio1cr sio1sr so1 pin sio1sr sio1sr a 6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 a 7 b0 writing transmit data a reading received data e sio1rdb intsio1 interrupt re q uest de sio1sr si1 pin d6 d5 d4 d3 d2 d1 d0 e7 e6 e5 e4 e3 e2 e1 f7 d7 e0 f6 f5 f4 f3 f2 f1 f0 a b unknown writing transmit data b f reading received data f reading received data d sio1tdb sio1cr sio1sr start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-137 receive errors receive errors occur on the following situation. to protect sio1rdb and the shift register contents, the received data is ignored while the sio1sr is ?1?. ? shift operation is finished before reading out received data from sio1rdb at sio1sr is ?1? in an external clock operation. if receive error occurs, set the sio1cr to ?0? for reading the data that received immediately before er ror occurence. and read the data from sio1rdb. data in shift register (at errors occur) can be read by reading the sio1rdb again. when sio1sr is cleared to ?0? after reading the received data, sio1sr is cleared to ?0?. after clearing sio1cr to ?0?, when 8-bit serial clock is input to sck1 pin, receive operation is stopped. to restart the receive operation, confirm that sio1sr is cleared to ?0?. if the received error occurs, set the sio1cr to ?1? for stopping the receive operation immediately. in this case, sio1cr, sio1sr register, sio1rdb register and sio1tdb register are initialized. figure 2.13.19 example of transmi t/receive (receive) error processing note: if receive error is not correc ted, an interrupt request does not generate after the error occurs. sck1 pin input sio1cr sio1sr so1 pin sio1sr sio1sr a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 a7 b0 writing transmit data a reading received data e sio1rdb intsio1 interrupt re q uest de sio1sr si1 pin d6 d5 d4 d3 d2 d1 d0 e7 e6 e5 e4 e3 e2 e1 f7 d7 e0 f6 f5 f4 f3 f2 f1 f0 a b unknown writing transmit data b ffh reading received data d sio1tdb sio1cr c6 c5 c4 c3 c7 c writing transmit data c sio1sr write a ?0? after reading the received data when a receive mode error occurs. start shift operation start shift operation start shift operation
TMP86FM48 2007-08-24 86fm48-138 figure 2.13.20 hold time of t he end of transmit/receive mode t sodh sck1 pin sio1sr so1 pin 4/fc
TMP86FM48 2007-08-24 86fm48-139 2.14 key-on wake-up (kwu) in the TMP86FM48, the stop mode must be released by not only p20 ( int5 / stop ) pin but also p64 to p67 pins. when the stop mode is released by p64 to p67 pins, the p20 ( int5 / stop ) pin needs to be used. 2.14.1 configuration figure 2.14.1 key-on wake-up circuit note1: stop pin doesn?t have the control register such as stopcr, so when stop mode is relesed by stopx (x: 0 to 3), stop pin should be used as stop function. p67 (ain07/stop3) p66 (ain06/stop2) p65 (ain05/stop1) p64 (ain04/stop0) p20 ( int5 / stop ) stop mode release signal (1: release) stop mode control stop0en stop1en stop2en stop3en stopcr (1ffe h ) int5
TMP86FM48 2007-08-24 86fm48-140 2.14.2 control p64 to p67 (stop0 to stop3) pin can contro lled by key-on wake-up control register (stopcr). it can be configured as enable/disable in 1-bit unit. stop mode can be entered by setting up th e system control register1 (syscr1), and can be exited by detecting low level of stop0 to stop3 pins, which are enabled by stopcr, for releasing stop mode (note 1). also, because each level of the stop0 to stop3 can be confirmed by reading p6dr, ch eck all stop0 to stop3 pins that is enabled by stopcr before the stop mode is started (note 2, 3). note 1: when the stop mode is used by edge-sensitive mode (syscr1 = ?0?), all bit of stopcr (stop3en to stop0en) should be cleared to ?0?. note 2: when the stop pin input is high or stop0 to stop3 pin input which is enabled by stopcr is low, executing an instruction which starts stop mode will not place in stop mode but instead will immediately start the release sequence (warm-up). note 3: when confirms the level of stop0 to stop3 pin which is enabled by stopcr, the corresponding bit of p6cr1 should be cleared to ?0? before reading p6dr. table 2.14.1 input edge (l evel) of stop mode release syscr1 = ?1? syscr1 = ?0? terminal name as both terminal release edge (level) stop p20/ int5 ?h? level (note2) rising edge stop0 p64/ain04 stop1 p65/ain05 stop2 p66/ain06 stop3 p67/ain07 ?l? level (note 2) do not use key on wake up function (note 1) key-on wake-up control register 7 6 5 4 3 2 1 0 stopcr (1ffe h ) stop0en stop1en stop2en stop3en ? ? ? ? (initial value: 0000 **** ) stop0en stop mode released by p64 port 0: disable 1: enable stop1en stop mode released by p65 port 0: disable 1: enable stop2en stop mode released by p66 port 0: disable 1: enable stop3en stop mode released by p67 port 0: disable 1: enable write only figure 2.14.2 key-on wake-up control register
TMP86FM48 2007-08-24 86fm48-141 2.15 10-bit ad converter (adc) the TMP86FM48 has a 10-bit successive approximation type ad converter. 2.15.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 2.15.1. it consists of control registers adccr1 and adccr2, registers adcdr1 and adcdr2, a da converter, a sample-and-hold circuit, a comparator, and a successive comparison circuit. figure 2.15.1 ad converter (adc) ain00 ain01 ain06 ain07 ain10 ain11 ain16 ain17 ack sain ainds adrs 10 varef vss reference voltage analog comparator shift clock analog input multiplexer a b g h i j o p y en 8 ad converter control register1, 2 2 s successive approximate circuit control circuit adccr1 avdd r/2 r r/2 da converter 2 amd adccr2 irefon ad conversion result register adcdr1 adcdr2 4 eocf adbf intadc sample hold circuit 3 ~ ~ ~ ~
TMP86FM48 2007-08-24 86fm48-142 2.15.2 register configuration the ad converter consists of the following four registers: ? ad converter control register 1 (adccr1) ? ad converter control register 2 (adccr2) ? ad conversion result regi ster 1/2 (adcdr1/adcdr2) (1) ad converter contro l register 1 (adccr1) this register selects the an alog channels and operation mode (software start or repeat) in which to perform ad conversion an d controls the ad converter as it starts operating. (2) ad converter contro l register 2 (adccr2) this register selects the ad conversion time and controls the connection of the da converter (ladder resistor network). (3) ad conversion resu lt register (adcdr1) this register is used to store the digital value (bit9 to bit2) after being converted by the ad converter. (4) ad conversion resu lt register (adcdr2) this register is used to store the digital value (bit1 and bit0) after being converted by the ad converter, and then this register is also used to monitor the operating status of the ad converter. the ad converter control register configurations are shown in figure 2.15.2 and figure 2.15.3.
TMP86FM48 2007-08-24 86fm48-143 ad converter control register 1 7 6 5 4 3 2 1 0 adccr1 (000e h ) adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: ? 1: start amd ad operating mode 00: ad operation disable 01: software start mode 10: reserved 11: repeat mode ainds analog input control 0: analog input enable 1: analog input disable sain analog input channel select 0000: selects ain00 1000: selects ain10 0001: selects ain01 1001: selects ain11 0010: selects ain02 1010: selects ain12 0011: selects ain03 1011: selects ain13 0100: selects ain04 1100: selects ain14 0101: selects ain05 1101: selects ain15 0110: selects ain06 1110: selects ain16 0111: selects ain07 1111: selects ain17 r/w note 1: select analog input when ad converter stops (adcdr2 = ?0?). note 2: when the analog input is all use di sabling, the ainds should be set to ?1?. note 3: during conversion, do not perform output instruction to maintain a precision for all of the pins. and port near to analog input, do not input intense signaling of change. note 4: the adrs is automatically cl eared to ?0? after starting conversion. note 5: do not set adrs newly again during ad c onversion. before setting adrs newly again, check adcdr2 to see that the conversion is complet ed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow mode are started, ad conv erter control register 1 (adccr1) is all initialized. therefore, set the adccr1 newly again after exiting these modes. ad converter control register 2 7 6 5 4 3 2 1 0 adccr2 (000f h ) irefon ?1? ack ?0? (initial value: ** 00 0000) irefon da converter (ladder resistor) connection control inputting current to the ladder resistor 0: connected only during ad conversion 1: always connected ack conversion time fc = 16 mhz fc = 8 mhz fc = 4 mhz fc = 1 mhz 000 39/fc ? ? ? 39.0 s 001 reserved 010 78/fc ? ? ? 78.0 s 011 156/fc ? ? 39.0 s 156.0 s 100 312/fc ? 39.0 s 78.0 s ? 101 624/fc 39.0 s 78.0 s 156.0 s ? 110 1248/fc 78.0 s 156.0 s ? ? ack ad conversion time select 111 reserved r/w note 1: settings for ? ? ? in the above table are inhibited. note 2: set conversion time by analog reference voltage (v aref ) as follows. v aref = 2.7 to 3.6 v (31.2 or more) v aref = 1.8 to 3.6 v (124.8 or more) note 3: always set bit0 in adccr2 to ?0? and set bit4 in adccr2 to ?1?. note 4: when a read instruction for adccr2, bit6 to 7 in adccr2 read in as undefined data. note 5: fc: high-frequency clock [hz] note 6: after stop or slow mode are started, ad conv erter control register 2 (adccr2) is all initialized. therefore, set the adccr2 newly again after exiting these modes. figure 2.15.2 ad conver ter control register
TMP86FM48 2007-08-24 86fm48-144 ad conversion result register 7 6 5 4 3 2 1 0 adcdr1 (0027 h ) ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 (initial value: 0000 0000) 7 6 5 4 3 2 1 0 adcdr2 (0026 h ) ad01 ad00 eocf adbf (initial value: 0000 **** ) eocf ad conversion end flag 0: before or during conversion 1: conversion completed adbf ad conversion busy flag 0: during stop of ad conversion 1: during ad conversion read only note 1: the eocf is cleared to ?0? when reading the adcdr1. therefore, the ad conversion result shoul d be read to adcdr2 more first than adcdr1. note 2: adbf is set to ?1? when ad conversion starts and cleared to ?0? when the ad c onversion is finished. it also is cleared upon entering stop or slow mode. note 3: if a read instruction is executed for adcdr2, read data of bit 3 to 0 are unstable. figure 2.15.3 ad converter result register 2.15.3 ad converter operation (1) set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable for analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). (2) set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the conversion time, refer to note 2 for ad converter control register 2. ? choose irefon for da converter control. (3) after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. (4) after an elapse of the specified ad conversion time, the ad converted value is stored in ad conversion result regist er 1 (adcdr1), ad conversion result register (adcdr2) and then the ad conversion end flag (eocf) of ad conversion result register 2 (adcdr2) is set to ?1?, upon which ti me ad conversion interrupt intadc is generated. (5) eocf is cleared to ?0? by a read of th e conversion result. however, if reconverted before a register read, although eocf is cleared the previous conversion result is retained until the next conversion is completed.
TMP86FM48 2007-08-24 86fm48-145 2.15.4 ad converter operation modes there are following two ad converter operation modes: ? software start: ad conver sion is performed once by setting amd to ?01b? and adrs to ?1?. ? repeat mode: ad conversion is performed repeatedly by setting amd to ?11b? and adrs to ?1?. (1) software start mode after setting adccr1 to ?01? (software start mode), set adccr1 to ?1?. ad conversion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad conversion result registers (adcdr1, adcdr2) and at the same time adcdr2 is set to ?1?, the ad conversion finished interrupt (intadc) is generated. adccr1 is automatically cleared to ?0? after ad conversion has started. do not set adccr1 newly again (restart ) during ad conversion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). figure 2.15.4 operation in software start mode indeterminate a dccr1 a dcdr2 a d conversion start a dcdr2 a dcdr1, adcdr2 first conversion result second conversion result intadc request conversion result read reading adcdr1 reading adcdr2 a d conversion start conversion result read
TMP86FM48 2007-08-24 86fm48-146 example: after selecting the conversion time of 39.0 s at 16 mhz and the analog input channel ain3 pin, perform ad conversion once. afte r checking eocf, read the converted value, store the lower 2 bits in address 009eh and store the upper 8 bits in address 009f h on ram. the operation mode is software start mode. ; ain select ld (p6cr1), 00000000b ; p6cr1 bit 3 = 0 ld (p6cr2), 00000000b ; p6cr2 bit 3 = 0 ld (adccr1), 00100011b ; select ain3 ld (adccr2), 11011010b ; select conversion time (624/fc) and operation mode ; ad convert start set (adccr1). 7 ; adrs = 1 sloop: test (adcdr2). 5 ; eocf = 1 ? jrs t, sloop ; result data read ld a, (adcdr2) ld (9eh), a ld a, (adcdr1) ld (9fh), a (2) repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeatedly. in this mode, ad conversion is started by setting adccr1 to ?1? after setting adccr1 to ?11?. after completion of the ad conversion, the conversion result is stored in ad conversion result registers (adcdr1, adcdr2) and at the same time adcdr2 is set to ?1?, the ad conversion finished interrupt (intadc) is generated. in repeat mode, each time one ad conversion is completed, the next ad conversion is started. to stop ad conversion, set adcc r1 to ?00b? (disable mode). the ad convert operation is stopped immediately. the converted value at this time is not stored in the ad conversion result register. figure 2.15.5 operation in repeat mode conversion result read first conversion a dccr1 a dcdr2 a d conversion start a dccr1 convert operation intadc request a d conversion finished indeterminate a dcdr1, a dcdr2 second conversion third conversion first conversion result second conversion result third conversion result a d convert operation suspended. conversion result is not stored. ?00? ?11? reading adcdr1 reading adcdr2 conversion result read conversion result read
TMP86FM48 2007-08-24 86fm48-147 2.15.5 stop and slow modes during ad conversion when the stop or slow mode is entered forcibly during ad conversion, the ad convert operation is suspended and the ad converter is initialized (adccr1 and adccr2 are initialized to initial value). also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering stop or slow mode.) when released from stop or slow mode, ad conversion is not automatically restarted. therefore, when the ad converter is used again, it is necessary to restart ad conversion (set adccr1 to ?1?). note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. 2.15.6 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit digital value converted by the ad as shown in figure 2.15.6. figure 2.15.6 analog input voltage an d ad conversion result (typ.) 0 1 2 3 1021 1022 1023 1024 001 h 002 h 003 h 3fd h 3fe h 3ff h a d conversion result varef ? vass 1024 a nalog input voltage
TMP86FM48 2007-08-24 86fm48-148 2.15.7 precautions about ad converter (1) analog input pin voltage range make sure the analog input pins (ain00 to ain17) are used at voltages within vss below varef. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. (2) analog input shared pins the analog input pins (ain00 to ain17) ar e shared with input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversion from degrading. not only these analog input shared pins, some other pins may also be affected by noise arising from input/output to and from adjacent pins. (3) noise countermeasure the internal equivalent circuit of the anal og input pins is shown in figure 2.15.7. the higher the output impedance of the analog input source, more easily they are susceptible to noise. therefore, make sure the output impedance of the signal source in your design is 5 k ? or less. toshiba also recommends attaching a capacitor external to the chip. figure 2.15.7 analog input equivalent circ uit and example of input pin processing da converter a llowable signal source impedance 5 k ? (max) aini internal capacitance c = 22 pf (typ.) internal resistance r = 5 k ? (typ.) analog comparator note: i = 00 to 17
TMP86FM48 2007-08-24 86fm48-149 2.16 flash memory 2.16.1 outline the TMP86FM48 incorporates 32768 bytes of flash memory (address 8000h to ffffh). of these bytes, 512 bytes (address 8000h to 81ffh) can be used as data memory. when these 512 bytes (address 8000h to 81ffh) are used as data memory, the 32256 bytes (address 8200h to ffffh) can be used as program memory. the writing to flash memory is controlled by flash control regist er (eepcr), flash status register (eepsr) and flash write emulate time control register (eepeva). the flash memory of the TMP86FM48 features: ? the flash memory is constructed of 512 pages flash memory and one page size is 64 bytes (512 pages 64 bytes = 32768 bytes). ? the TMP86FM48 incorporates a 64-byte temporary data buffer. the data written to flash memory is temporarily stored in this data buffer. after 64 bytes data have been written to the temporary data buffer, the writing to flash memory automatically starts by page writing (the 64 bytes data are written to specified page of flash simultaneously). at the same time, page-by-page erasing occurs automatically. so, it is unnecessary to erase individual pages in advance. ? the flash control circuit incorporates an oscillator dedicated to the flash. so flash writing time is independent of the system clock frequency (fc). in addition, because an flash control circuit controls writing time for each flash memory cell, the writing time varies in each page (typically 4 ms per page). ? controlling the power for the flash control circuit (regulator and voltage step-up circuit) achieves low power consumption if the flash is not in use (example: when the program is executed in ram area). 2.16.2 conditions for accessing the flash areas the conditions for accessing the flash area s vary depending on each operation mode. the following tables shows flash are access conditions. table 2.16.1 flash area access conditions operation mode area mcu mode (note 1) serial prom mode (note 2) data memory 8000h to 81ffh write/read/fetch (note3) supported program memory 8200h to ffffh read/fetch only write/read/fetch supported note 1: ?mcu mode? shows normal1/2 and slow1/2 modes. note 2: ?serial prom mode? shows the flash controlling mode. for details, refer to ?2.19 serial prom mode?. note 3: ?fetch? means reading operation of flash data as an instruction by cpu.
TMP86FM48 2007-08-24 86fm48-150 2.16.3 differences among product series the specifications of the flash product (t mp86fm48) are different from those of the emulation chip (tmp86c948) as listed below. see 2.17.2 ?control ? for explanations about the control registers. flash product (TMP86FM48) emulation chip (tmp86c948) it is possible to rewrite the eepcr register only when the program execution area in use is ram/boot-rom. rewriting the eepcr register in the debugger memory window, it is impossible to rewrite the eepcr register. accessing the eepeva register it is possible only to write- and read-access the eepeva register. the writing to this register does not affect the function. the time required to emulate flash writing is put under control. flash write time (the emulation chip is written to emulation memory instead of flash) typically 4 ms (independent of the system clock) the flash write time is set up using the eepeva register (dependent on the system clock). if eepsr = ?1?, executing a read instruction/fetch to the flash area causes ffh to be read regardless of what the current rom data is. fetching ffh results in a software interrupt occurring. executing a read instruction/fetch to the 8000h to ffffh area when eepsr = ?1? the debugger memory window always displays rom data. mcu mode executing a write instruction to the 8000h to 81ffh area when eepcr = ?0011?, eepsr = ?1? and eepsr = ?0?. serial prom mode the eepsr is set to ?1? (write enabled). the eepsr stays at ?0? (write disabled). mcu mode in the debugger memory window, it is possible to rewrite the 8200h to ffffh area (the eepsr remains unchanged). executing a write instruction to the 8200h to ffffh area when eepcr = ?0011?, eepsr = ?1? and eepsr = ?0?. serial prom mode the eepsr is set to ?1? (write enabled). data memory (8000h to 81ffh) 512 bytes of flash are included in the 8000h to 81ffh area. 512 bytes of emulation memory are included in the 8000h to 81ffh area. (turning off the power for the emulation chip erases data in the emulation memory.) boot-rom 2 kbytes are included in the 3800h to 3fffh area. operating voltage vdd = 1.8 to 3.6 v vdd = 1.8 to 3.3 v
TMP86FM48 2007-08-24 86fm48-151 2.16.4 flash memory configuration 64 consecutive bytes in the flash area are tr eated as one group, which is defined as a page. the TMP86FM48 incorporates a one-page temporary data buffer. writing data to flash is temporarily stored in this 64-byte data buffer. after 64 bytes data have been written to the temporary data buffer, these data are written to specif ied page of flash at a time. however, data can be read from any address byte by byte. 2.16.4.1 page configuration the flash area has a page configuration of 64 bytes/page as shown below. the total number of bytes in it is 512 pages 64 bytes ( = 32768 bytes). the writeable area is 8000h to ffffh in serial prom mode. note: the program memory (8200h to ffffh) can be written only in the serial prom mode. for details of the serial prom mode, refer to ?2.19 serial prom mode?. address 0 1 2 3 4 5 6 7 8 9 a b c d e f 8000h 8010h 8020h 8030h 8040h 8050h 8060h 8070h 8080h 8090h 80a0h 80b0h 80c0h 80d0h 80e0h 80f0h ffe0h fff0h figure 2.16.1 page configuration page 0 page 1 page 2 page 3 page 511
TMP86FM48 2007-08-24 86fm48-152 2.17 data memory of flash(address 8000h to 81ffh) the TMP86FM48 incorporates 512 bytes (8000h to 81ffh) of data memory of flash, which features: ? in the mcu mode, user-created programs can rewrite the data memory of flash in page (64 bytes) units. (it can be used to sa ve application last keys and preset data.) ? in the serial prom mode, it is possible to perform serial writing to the data memory of flash in the same manner as for the program memory. so, initial values can be factory-set in the data memory of flash. ? using support programs incorporated in the boot-rom makes it easy to write to the flash. 2.17.1 configuration figure 2.17.1 data memory eepsr rd signal end of write serial prom mode program area chip select signal data area chip select signal ram/boot-rom fetch signal wr signal syscr1 syscr2 syscr2 decoder eepcr temporary data buffer (64 bytes) with write data counter dq r cp write time counter en overflow overflow 512 eepsr request to generate an interrupt vecto r dq r cp dq r cp en flash warm-up counter cpu wait signal flash memory vin data input a ddress input 16 8 data bus a ddress bus 4 eepmd eeprs a tpwdw mnpwdw bfbusy ewupen wint overflow dq r cp regulator clear count up
TMP86FM48 2007-08-24 86fm48-153 2.17.2 control the flash is controlled by flash control re gister (eepcr), flash status register (eepsr) and flash write emulate time control register (eepeva). flash control register 7 6 5 4 3 2 1 0 eepmd eeprs atpwdw mnpwdw (initial value: 1100 * 011) eepcr (1fe0h) program execution area eepmd flash write enable control (write protect) ram/ boot flash 1100: flash write disable 0011: flash write enable other values: reserved eeprs flash write forcible stop 0: ? 1: flash writing is forced to stop. (the write data counter is initialized.) * after writing ?1? to eeprs, it is automatically cleared to ?0?. read only atpwdw automatic power control for the flash control circuit in the idle0/1/2, sleep0/1/2 modes. (this bit is available only when mnpwdw is set to ?1?.) 0: automatic power shut down is executed in idle0/1/2 and sleep0/1/2 modes. 1: automatic power shut down is not executed in idle0/1/2 and sleep0/1/2 modes. (the power is always supplied in these modes.) r/w mnpwdw software-based power control for the flash control circuit 0: the power for the flash control circuit is turned off. 1: the power for the flash control circuit is turned on r/w read only note 1: the eepmd, eeprs, and mnpwdw can be rewritten only when a program fetch is taking place in the ram or boot-rom area. if an attempt is made to rewrite the eepcr register when a program is being executed in the flash area, the eepmd, eeprs, and mnpwdw keep holding the previous data; they are not rewritten. note 2: to write to the flash, set the eepmd with ?0011b ? in advance when a program fetch is taking place in the ram area. however, this processing is not required if a support program in the boot-rom is used. note 3: to forcibly stop writing of flash, set the eeprs to ?1? when a program fetch is taking place in the ram area. note 4: the atpwdw functions only if the mnpwdw is ?1?. if the mnpwdw is ?0?, the power for the flash control circuit is kept turned off regard less of the setting of the atpwdw. note 5: when a stop mode is executed, the power for the flash control circuit is turned off regardless of the setting of the atpwdw. if the mnpwdw is ?0?, entering/exiting t he stop mode allows the power for the flash control circuit to be kept turned off. note 6: executing a read instruction to the eepcr register re sults in bit3 being read as undefined. bit2 is always read as ?0?. note 7: the following attention is necessa ry when the mnpwdw is set or cleared. when the mnpwdw is changed from ?1? to ?0? clear the interrupt master enable flag (i mf) to ?0? in advance to disable an interrupt. after that, do not set imf to ?1? during eepsr = ?0?. if a watchdog timer is used as interrupt request, clear the binary counter for the watchdog timer just before mnpwdw is changed from ?1? to ?0?. when the mnpwdw is changed from ?0? to ?1? when write to or read from the flash memory, make sure that the eepsr is ?1? by software. once the mnpwdw is rewritten from ?0? to ?1? by software, keep performing software-based polling until the eepsr becomes ?1?. figure 2.17.2 flash control register
TMP86FM48 2007-08-24 86fm48-154 flash status register 7 6 5 4 3 2 1 0 wint ewupen bfbusy (initial value: **** * 010) eepsr (1fe1h) wint interrupt detection during a write to the flash 0: not detected 1: detected (interrupt occurred) * wint is automatically cleared to ?0? when read instruction is executed to eepsr. control circuit status operating (power on) halt (power off) or warm-up flash status temporary data buffer empty writing disable ewupen flash control circuit status monitor 1 1 0 bfbusy flash write busy flag 0 1 1 read only note 1: if a nonmaskable interrupt occurs during a write to the flash, the wint is set to "1" and the writing is discontinued, and then warm-up (cpu wait) for the control ci rcuit of flash memory is executed. (the write data counter is initialized.) if wint = ?1? is detected in the nonmaskable inte rrupt service routine, a write is not completed successfully. so, it is necessary to try a write again. the content of the page to which a write is taking place may be changed to an unexpected value dependi ng on the timing when the wint becomes ?1?. note 2: even if a nonmaskable interrupt occurs during an fl ash warm-up, the cpu stays at a halt until the warm-up is finished. note 3: the wint is automatically cleared to ?0? w hen a read instruction is executed to the eepsr register. note 4: when mnpwdw is changed from ?0? to ?1?, ewupen becomes ?1? after taking 2 10 /fc [s] (if sysck = ?0?) or 2 3 /fs [s] (if sysck = ?1?). before accessing the flash, make sure that the ewupen is ?1? in the ram area. note 5: if the bfbusy is ?1?, executing a read instruction or fetch to the flash area causes ffh to be read. fetching ffh results in a software interrupt occurring. figure 2.17.3 flash status register
TMP86FM48 2007-08-24 86fm48-155 flash write emulation time control register (setting of this register functions only in em ulation chip (tmp86c948).) 7 6 5 4 3 2 1 0 eepsucr (initial value: **** * 000) eepeva (1fe2h) emulation chip (tmp86c948) flash product (TMP86FM48) normal1/2 idle1/2 mode slow1/2 sleep1/2 mode all operation modes eepsucr controlling the flash write emulation time [s] for emulation chip 000 001 010 011 100 101 110 111 2 16 /fc 2 15 /fc 2 14 /fc 2 13 /fc 2 12 /fc reserved reserved reserved 2 7 /fs 2 6 /fs 2 5 /fs 2 4 /fs 2 3 /fs reserved reserved reserved typ. 4 ms (regardless of register settings and the system clock) r/w note 1: only in the emulation chip, the eepsucr function s. in the flash product, it is possible only to write- and read-access the register. it does not actually function. because the flash product incorporates a dedicated oscillator, its write time is independent of the system clock. note 2: executing a read instruction to the eepeva r egister results in bit7 to 3 being read as undefined. note 3: the following table lists the write emulation time s pecified by the setting of the eepsucr. select an appropriate value according to the operating frequency used. the shading indicates recommended settings. normal1/2 mode slow1/2 mode eepsucr setting fc = 16 mhz fc = 8 mhz fc = 4 mhz fc = 2 mhz fc = 1 mhz fs = 32.768 khz 000 4.10 8.19 16.38 32.77 65.54 3.91 001 2.05 4.10 8.19 16.38 32.77 1.95 010 1.02 2.05 4.10 8.19 16.38 0.98 011 0.51 1.02 2.05 4.10 8.19 0.49 write time [ms] 100 0.26 0.51 1.02 2.05 4.10 0.24 figure 2.17.4 flash control regi ster and flash status register
TMP86FM48 2007-08-24 86fm48-156 2.17.3 flash write enable control (eepcr) in the flash product, the control register can be used to disable a write to the flash (write protect) in order to prevent a write to the flash from occurring by mistake because of a program error or microcontroller malfunction. to enable a write to the flash, set the eepcr with 0011b. to disable a write to the flash, set the eepcr with 1100b. a reset initializes the eepcr to 1100b to disable a write to the flash. usually, set the eepcr with 1100b, except when it is necessary to write to the flash. note: the eepcr can be rewritten only wh en a program is being executed in the ram area. executing a writ e instruction to the eepcr in the flash area does not change its setting.
TMP86FM48 2007-08-24 86fm48-157 2.17.4 flash write forcible stop (eepcr) to forcibly stop a write to the flash, set the eepcr to ?1?. setting the eepcr to ?1? initializes the write data counter of data buffer and forcibly stops a write, and then a warm-up (cpu wait) for the control circuit of flash memory is executed. after warm-up period, the eepsr is cleared to ?0?. the warm-up period is 2 10 /fc (sysck = ?0?) or 2 3 /fs (sysck = ?1?). after this, if writing to flash starts again, data is stored as the first byte of the temp orary data buffer and sets the eepsr to ?1?. therefore, it is necessary to writ e 64 bytes data to the temporary data buffer. after 1 to 63 bytes are saved to the temporar y data buffer, if the eepcr is set to ?1? the specified page of flash is not written. (it keeps previous data.) note 1: after 64 bytes are written to the te mporary data buffer, the setting the eepcr to ?1? may cause the writing the page of flash to an unexpected value. note 2: the eepcr can be rewritten only when a program is being executed in the ram area. in the flash area, executing a write instruction to the eepcr does not affect its setting. note 3: during the warm-up period for flash me mory (cpu wait), the peripheral circuits continue operating, but the cpu stays at a halt until the warm-up is finished. even if an interrupt latch is set to ?1? by generating of interrupt request, an interrupt sequence doesn?t start till the end of warm-up. if interrupts occur during a warm-up period with imf = ?1?, the interrupt se quence which depends on interrupt pr iority will start after warm-up period. note 4: when the eepcr is set to ?1? with eepsr = ?0?, a warm-up is not executed. note 5: if executed a write or read instruction to the flash area immediately after setting eepcr, insert one or more machi ne cycle instructions after setting eepcr. example: reads the flash memory data imm ediately after setting eepcr to ?1? ld hl,8000h ld (eepcr),3fh ; set eepcr to ?1? nop ; nop (do not execute write or read instruction immediately after setting eepcr.) ld a,(hl) ; reads the data of address 8000h (write or read instruction to the flash memory)
TMP86FM48 2007-08-24 86fm48-158 figure 2.17.5 write data counter initialization and write forcible stop 0 1 20 0 1 2 3 4 5 buffer 0 buffer 1 buffer 2 buffer 63 eepcr write instruction to the flash area write data counte r eepsr eepsr ? ? ? ? data 0 data 1 data 0? data 1? data 2? write to the epcr =
TMP86FM48 2007-08-24 86fm48-159 2.17.5 power control for the flash control circuit for the flash product, it is possible to tu rn off the power for flash control circuit (such as a regulator) to suppress power consum ption if the flash area is not accessed. for the emulation chip (tmp86c948), the register setting and the cpu wait functions behave in the same manner as for the flash product to maintain compatibility; however, power consumption is not suppressed. the eepcr and eepcr are used to control the power for the flash control circuit. if the power for the flash control circuit is turned off according to the setting of these registers, starting to use the circuits again needs to allow warm-up time for the power supply. table 2.17.1 power supply warm-up time (cpu wait) for the flash control circuit stop mode (when eepcr = ?1?) normal1/2 idle0/1/2 mode slow1/2 sleep0/1/2 mode to return to a normal mode to return to a slow mode 2 10 /fc [s] (64 s @16 mhz) 2 3 /fs [s] (244 s @32.768 khz) stop warm-up time + 2 10 /fc [s] stop warm-up time + 2 3 /fs [s] 2.17.5.1 software-based power control for t he flash control circ uit (eepcr) the eepcr is a software-based power control bit for the flash control circuit. when a program is being executed in the ram area, setting this bit enables software-based po wer control. clearing th e eepcr to ?0? immediately turns off the power for the flash control circuit. once the eepcr is switched from ?0? to ?1?, before attempting a read or fetch from the flash area, it is necessary to insert a warm up period by software until the power supply is stabilized. in this case, because the cpu wait is not executed, any other instructions except accessing to fl ash (write or read) are available. when mnpwdw is changed from ?0? to ?1?, ewupen becomes ?1? after taking 2 10 /fc [s] (sysck = ?0?) or 2 3 /fs [s] (sysck = ?1?). usually software-based polling should be performed until the eepsr becomes ?1?. an example of setting is given below. (1) example of controlling the eepcr 1. transfer a program for controlling the eepcr to the ram area. 2. release an address trap in the ram area (setup the wdtcr1 and wdtcr2 registers). 3. jump to the control program transferred to the ram area. 4. clear the interrupt master enable flag (imf ?0?). 5. clear the binary counter if the watchdog timer is in use. 6. to turn off the power for the flash control circuit, clear the eepcr to ?0?. 7. perform cpu processing as required. 8. to access the flash area again, set the eepcr to ?1?. 9. keep program polling until the eepsr becomes ?1?. (upon completion of an flash warming-up, the eepsr is set to ?1?. it takes 2 10 /fc (sysck = ?0?) or 2 3 /fs (sysck = ?1?) until ewupen becomes ?1?.) this procedure enables the flash area to be accessed.
TMP86FM48 2007-08-24 86fm48-160 if the eepcr is ?1?, entering a stop mode forcibly turns off the power for the flash control circuit. when th e stop mode is released, a stop mode oscillation warm-up is carried out, and then the cpu wait period (warm-up for stabilizing of flash power supply circuit) is automatically performed. if the eepcr is ?0?, entering/exiting the stop mode keeps the power for the flash control circuit turned off. note 1: if the eepsr is ?0?, do not access (fetch, read, or write) the flash area. executing a read instruction or fetc h to the flash area causes ffh to be read. fetching ffh results in a software interrupt occurring. note 2: to clear the eepcr to ?0?, clear the interrupt master enable flag (imf) to ?0? in advance to disable an interrupt. after that, do not set imf to ?1? during eepsr = ?0?. note 3: if the eepcr is ?0 ?, generating a nonmaskable interrupt automatically rewrites the mnpwdw to ?1 ? to warm up the flash control circuit (cpu wait). that time, the peripheral circ uits continue operating, but the cpu stays at a halt until the warm-up is finished. note 4: the eepcr can be rewritt en only when a program is being executed in the ram area. in the flash area, executing a write instruction to the eepcr does not affect its setting. note 5: if a watchdog timer is used as inte rrupt request, clear the binary counter for the watchdog timer just before mnpwdw is changed from ?1? to ?0?. note 6: during the warm-up period with a software polling of eepsr, if a nonmaskable interrupt occurs, the cpu stays at a halt until the warm-up is finished. figure 2.17.6 software-based power control fo r the flash control circuit (eepcr) eepcr eepsr eepsr flash warm-up counte r flash control circuit status program execution area specify mnpwdw = 0 specify mnpwdw = 1 normal operation powe r -off state warm-up in progress normal operation flash area ram area flash area 0 2 10 /fc or 2 3 /fs [s] overflow 0 software polling (cpu is operating)
TMP86FM48 2007-08-24 86fm48-161 example: performing software-based power control for the flash control circuit sramarea: di ; disable an interrupt (imf ?0?) ld (wdtcr2),4eh ; clear the binary counter if the watchdog timer is in use clr (eepcr).0 ; clear the eepcr to ?0?. set (eepcr).0 ; set the eepcr to ?1? sloop1: test (eepsr).1 ; monito r the eepsr register. jrs t,sloop1 ; jump to sloop1 if eepsr = ?0?. jp main ; jump to the flash area.
TMP86FM48 2007-08-24 86fm48-162 2.17.5.2 automatic power control for the flash control circuit (eepcr) the eepcr is an automatic power control bit for the flash control circuit. it is possible to suppress power co nsumption by automatically shutting down the power for the flash control circuit wh en an operation mode is changed to idle0/1/2 and sleep0/1/2 modes. this bit ca n be specified regardless of the area in which a program is being executed. after the eepcr is cleared to ?0?, entering an operation mode (idle0/1/2 or sleep0/1/2) where the cpu is at a halt automatically turns off the power for the flash control circuit. once the operation mode is released, the warm-up time (cpu wait) is automatically counted to resume no rmal processing. the cpu wait period is either 2 10 /fc (sysck = ?0?) or 2 3 /fs (sysck = ?1?). if the eepcr is ?1?, releasing the operation mode does not cause the cpu wait. if eepcr = ?1?, executing a stop mode forcibly turns off the power for the flash control circuit regardless of the setting of the eepcr. when the stop mode is released, a stop mode oscillation warm -up is carried out, and then an flash control circuit warm-up (c pu wait) is automatically performed. if the eepcr is ?0?, entering/exiti ng a stop mode allows the power for the flash control circuit to be kept turned off. note 1: the eepcr functions onl y if the eepcr is ?1?. if the eepcr is ?0?, the power for the flash control circuit is kept turned off when an operation mode is executed or released. note 2: during an flash warm-up (cpu wait), the peripheral circuits continue operating, but the cpu stays at a halt. even if an interru pt latch is set under this condition, no interrupt process occurs unt il the cpu wait is completed. if the imf is ?1? when the interrupt latch is set, interrupt process take s place according to the interrupt priority after the cpu has started operating. figure 2.17.7 automatic power control for the flash control circuit (eepcr) eepcr eepcr eepsr flash warm-up counter flash control circuit status program execution area specify atpwdw = mode idle or sleep mode cpu wait normal or slow mode
TMP86FM48 2007-08-24 86fm48-163 2.17.6 accessing the flash data memory area during the writing to the data memory of flash area, neither a read nor fetch can be performed for the 8000h to ffffh area. therefore, to write the data memory of flash, the program being executed should be jumped to ram area or should be jumped to the support program in boot-rom. for details about the support program in boot-rom, refer to ?2.17.6.2 method of using support programs in the boot-rom?. an ld instruction can be used to read data from the data memory of flash area byte by byte. the support program incorporated in the boot-rom can also be used to read data from the data memory of flash area. if a nonmaskable interrupt occurs during a write to the flash (eepsr = ?1?), the wint is set to ?1? and the writing is discontinued, and then the warm-up (cpu wait) for control circuit of flash memory is executed (the write data counter is also initialized). if wint = ?1? is detected in the nonmaskable interrupt service routine, a write is not completed successfully. so, it is necessary to try a write again. the warm-up period is 2 10 /fc (sysck = ?0?) or 2 3 /fs (sysck = ?1?). after 1 to 63 bytes are saved to the temporary data buffer, if an interrupt generates, the spec ified page of flash is not written. (it keeps previous data.) note 1: after 64 bytes are written to the tempor ary data buffer, the generating of an interrupt may cause the writing the page of flash to an unexpected value. note 2: during the warm-up period for flash me mory (cpu wait), the peripheral circuits continue operating, but the cpu stays at a halt until the warm-up is finished. even if an interrupt latch is set to ?1? by generating of interrupt request, an interrupt sequence doesn?t start till the end of warm-up. if interrupts occur during a warm-up period with imf = ?1?, the interrupt se quence which depends on interrupt pr iority will start after warm-up period. note 3: when write the data to flash memory from ram area, disable all the nonmaskable interrupt by clearing interrupt master enabl e flag (imf) to ?0? beforehand. however, in support program of boot-rom, there is no need to clear the imf because boot-rom already has a di (disable interrupt) instruction.
TMP86FM48 2007-08-24 86fm48-164 2.17.6.1 method of developing the control program in the ram area to develop the program in ram, the write control program should be stored in flash beforehand or should load from external device by using peripheral function (example: uart, sio etc). given below is an example of developing the control program in the ram area. (1) example of developing and writing the control program to the ram area 1. for the emulation chip, set the eepeva register with an optimum time value according to the operating frequency. 2. transfer the write control program to the ram area. 3. release an address trap in the ram area (set up the wdtcr1 and wdtcr2 registers). 4. jump to the ram area. 5. monitor the eepsr. if it is ?0?, set the eepcr to ?1?, and then start and keep poll ing until the eepsr becomes ?1?. 6. clear the interrupt master enable flag (imf ?0?). 7. set the eepcr with ?3bh? (to enable a write to the flash). 8. execute a write instruction for 64 bytes to the flash area. 9. start and keep polling by software until the eepsr becomes ?0?. (upon completion of an erase and write to the flash cells, the eepsr is set to ?1?. for the flash product, the required write time is typically 4 ms. for the emulation chip, it is the value specified in the eepeva register.) 10. set the eepcr with ?cbh? (to disable a write to the flash). 11. jump to the flash area (main program). note: see (2), ?method of specifying an ad dress for a write to the flash,? for a description about the flash address to be specified at step 8 above.
TMP86FM48 2007-08-24 86fm48-165 (2) method of specifying an address for a write to the flash the flash page to be written is specified by the 10 high-order bits of the address of the first-byte data. the first-byte data is stored at the first address of the temporary data buffer. if the data to be written is, for example, 8040h, page 1 is selected, and the data is stored at the first address of the temporary data buffer. even if the 6 low-order bits of the specified address is not 000000b, the first-byte data is always stored at the first address of the data buffer. any address can be specified as the second and subsequent address within flash area (for the mcu mode, 8000 to 81 ffh and, for the serial prom mode, 8000h to ffffh). the write data bytes are stored in the temporary data buffer in the sequence they are written, regardless of what address is specified. usually, the address that is the same as the first- byte is specified for the second and subsequent address. a 16-bit transfer instruction (ldw) can also be used for writing to the temporary data buffer. example: data bytes 00h to 3fh are written to page 1. (figure 2.17.8 shows the example of data buffer and pages.) di ; disable an interrupt (imf ?0?) ld c,00h ld hl,eepcr ; specify the eepcr register address. ld ix,8040h ; specify a write address. ld (hl),3bh ; specify the eepcr sloop1: ld (ix),c ; store data to the temporary data buffer. (a write page is selected when the first byte is written.) inc c ; c = c + 1 cmp c,40h ; jump to sloop1 if c is not 40h jr nz,sloop1 sloop2: test (eepsr).0 jrs f,sloop2 ; jump to sloop2 if eepsr = ?1?. ld (hl),0cbh ; specify the eepcr note: if the bfbusy is ?1?, executing a read instruction or fetch to the flash area causes ?ffh? to be read. fetching ?ffh? results in a software interrupt occurring. 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh address 0 1 2 3 4 5 6 7 8 9 a b c d e f 8030h 8040h 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 8050h 10h 11h 12h 13h 14h 15h 16h 19h 1ah 1bh 1ch 1dh 1eh 1fh 8060h 20h 21h 22h 23h 24h 25h 26h 29h 2ah 2bh 2ch 2dh 2eh 2fh 8070h 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh figure 2.17.9 data buffer and write page (example) temporary data buffer page 1
TMP86FM48 2007-08-24 86fm48-166 figure 2.17.10 write to the flash data memory area (in case of flash product) figure 2.17.11 write to the flash data memory area (in case of emulation chip) note 1: the emulation chip is written to emulation memory instead of flash cell. note 2: in case of emulation chip, the data stacked to data buffer is written to emulation memory just before eepsr is chan ged from ?1? to ?0?. therefore, if the writing of flash is stopped forcibly after the write data counter becomes overflow, the memory value on the page subjected to a write may be different from flash product. data 2 0 1 2 3 63 0 buffer 0 buffer 1 buffer 2 buffer 63 flash cell write instruction to the flash area write data counte r eepsr eepsr ? ? ? ? data 0 data 1 erasing writing write completed write time (typically 4 ms) data 63 64 bytes are written at a time. overflow data before writeing data after writing data 2 0 1 2 3 63 0 buffer 0 buffer 1 buffer 2 buffer 63 emulation memor y write instruction to the flash area write data counte r eepsr eepsr ? ? ? ? data 0 data 1 data before writing write completed write time data 63 64 bytes are written at a time. overflow (set by eepeva register) data after writing
TMP86FM48 2007-08-24 86fm48-167 2.17.6.2 method of using support programs in the boot-rom the boot-rom of tmp86fm4 8 has support program to simplify writing/reading of flash. this program su pports three subroutines. 1. writing to data flash from ram 2. reading from data flash to ram 3. reading from program flash to ram in addition to a program for controlling a write in the serial prom mode, the boot-rom incorporates support programs for simplifying a write to the data memory of flash in the mcu mode. the support programs take the form of a subroutine. after setting general-purpose registers with the necessary data, just execute a call instruction for a support program. it enables a write to and a read from the flash. there are two subroutines in boot-rom. the table 2.17.2 shows the function of these subroutines. table 2.17.2 support program (subroutines) in boot-rom program call address function support program 1 3e00h writing to data memory of flash (8000h to 81ffh) from ram area is available. 64-byte data can be written at a time. support program 2 3e2ch reading from flash memory (8000h to ffffh) into ram area is available. 64-byte data can be read at a time. when using the support program, it is unnecessary to prepare an flash write program in advance or develop it in the ram area. support program 1 enables 64 consecutive data bytes to be transferred from the ram area to any data memory of flash page in block. (only data memory of flash is available.) support program 2 enables data to be transferred from any flash memory page (both data memory of flash and program memory are available.) to a specified 64-byte consecutive ram area in block. how to use the support programs in the boot-rom is explained below. see (3), ?support program 1,? and (4), ?support prog ram 2,? for the source code of the support programs. (1) example of using support program 1 to write data to the flash data area (block transfer from the ram area to the flash data area) 1. for the emulation chip, set the eepe va register with the optimum time according to the operating frequency. 2. set data in the transfer-source ram area. 3. set the ram area start address (t ransfer source) in the hl register. 4. set the flash data area start address (transfer destination) in the de register. 5. set ?1fh? in the b register. (be sure to set 1fh (half of the number of bytes to be written.)) 6. clear the binary counter if the watchdog timer is in use. 7. execute a call instruction to ?3e00h?. 8. data is transferred from the ram area to the flash data area in block. after several milliseconds, prog ram control is returned to the main routine.
TMP86FM48 2007-08-24 86fm48-168 note 1: steps 1 to 6 above are executed in the flash area. note 2: support program 1 rewrites the hl , de, b, and wa registers. if the existing data in them are necessary, save it in advance. note 3: if the eepcr is ?0?, exec uting support program 1 rewrites it to ?1? before performing a block transfer. note 4: executing a call instruction for support program 1 consumes two bytes of stack. note 5: if the watchdog timer is in use, be su re to clear the binary counter for it before executing a call instruction to 3e00h. note 6: do not specify the address from 8200h to ffffh as a transfer destination address in mcu mode. example) setting up hl = 0050h, de = 8100h, and b = 1fh, and executing a call instruction for support program 1 (3e00h) figure 2.17.12 example of using support progr am 1 to write data to the flash data area (2) using support program 2 to read data from the flash area (block transfer from the flash area to the ram area) 1. set the ram area start address (trans fer destination) in the hl register. 2. set the flash area start address (t ransfer source) in the de register. 3. set ?1fh? in the b register. (be sure to set 1fh (half of the number of bytes to be read.)) 4. execute a call instruction to ?3e2ch?. 5. data is transferred from the flash area to the ram area in block. upon completion of processing, program control is returned to the main routine. note 1: a ld instruction can be used to read data from the flash area in byte units without using support program 2. note 2: steps 1 to 4 above are executed in the flash area. note 3: support program 2 rewrites the hl , de, b, and wa registers. if the existing data in them are necessary, save it in advance. note 4: executing a call instruction for support program 2 consumes two bytes of stack. 55h 0050h 0ah 50h 12h 40h ram area 0051h 0052h 0053h 008fh : 55h 8100h 0ah 50h 12h 40h flash data area 8101h 8102h 8103h 813fh : write block transfe r
TMP86FM48 2007-08-24 86fm48-169 example) setting up hl = 0050h, de = 8100h, and b = 1fh, and executing a call instruction for support program 2 (3e2ch) figure 2.17.13 example of using support pr ogram 2 to read data from the flash area (3) support program 1 (block transfer from the ram area to the flash data area) shown below is the support program source code for writing data to the flash. user_sub_write section code abs = 3e00h suser_main1: test (eepsr).1 jrs f,sram_to_eep ; jump sram_to_eep if the eepsr is ?1? seep_warmingup: set (eepcr).0 ; set the eepcr to ?1?. test (eepsr).1 ; wait until a warm-up is completed. jrs t,seep_warmingup sram_to_eep: di ; disable an interrupt. and de,0ffc0h ; mask the 6 low-order bits. ld (eepcr),3bh ; enable a write to the flash. sbfbusy_loop: ld wa,(hl) ; read data from the ram. ld (de),wa ; write data to the flash. inc hl inc hl dec b jrs f,sbfbusy_loop seep_write_end: test (eepsr).0 ; perform polling on the bfbusy flag. jrs f,seep_write_end ld (eepcr),0cbh ; disable a write to the flash. ret r a m area flash area 55h 0050h 0ah 50h 12h 40h 0051h 0052h 0053h 008fh 55h 8100h 0ah 50h 12h 40h 8101h 8102h 8103h 813fh : : read block transfe r : :
TMP86FM48 2007-08-24 86fm48-170 (4) support program 2 (block transfer from the flash area to the ram area) shown below is the support program sou rce code for reading data from the flash. user_sub_read section code abs = 3e2ch suser_main2: and de,0ffc0 ; mask the 6 low-order bits. ld (eepcr),0cbh ; disable a write to the flash. seep_read_loop: ld wa,(de) ld (hl),wa inc hl inc hl inc de inc de dec b jrs f,seep_read_loop ret
TMP86FM48 2007-08-24 86fm48-171 2.18 flash program memory the TMP86FM48 incorporates 32256 bytes ( 8200h to ffffh) of program memory. if the data memory of flash is not in use, the TMP86FM48 can be used as an flash product with 32768 full bytes. to write data to the progra m memory (data memory of flash), execute the serial prom mode. 2.18.1 configuration the program memory has the same configuration as for the data memory of flash. see section 2.17.1 ?configuration?. 2.18.2 control the program memory is controlled in the same manner as for the data memory of flash. see section 2.17.2 ?control?. 2.18.3 flash write enable control (eepcr) the flash write enable control register for the program memory behaves in the same manner as for the data memory of flash. see section 2.17.3 ?flash write enable control (eepcr)?. 2.18.4 flash write forcible stop (eepcr) the flash write forcible stop register for the program memory behaves in the same manner as for the data memory of flash. se e section 2.17.4 ?flash write forcible stop (eepcr)?. 2.18.5 power control for the flash control circuit the power for the program memory control circu it is controlled in the same manner as for the data memory of flash. see section 2.17.5 ?power control for the flash control circuit?. 2.18.6 accessing the flash program memory area basically, a write to the program memory ar ea is carried out using uart communication after the serial prom mode is entered. for explanations about what control is performed in the serial prom mode, see the following descriptions.
TMP86FM48 2007-08-24 86fm48-172 2.19 serial prom mode 2.19.1 outline the TMP86FM48 has a 2 kbytes boot-rom for programming to flash memory. this boot-rom is a mask rom that contains a program to write the flash memory on-board. the boot-rom is available in a serial prom mode and it is controlled by boot pin and reset pin, and is communicated via txd (p06) and rxd (p05) pins. there are four operation modes in a serial prom mode: flash memory writing mode, ram loader mode, flash memory sum output mode and product discrimination code output mode. operating area of serial prom mode differs from that of mcu mode. the operating area of serial prom mode shows in table 2.19.1. table 2.19.1 operating area of serial prom mode parameter min max unit operating voltage 2.7 3.6 v high frequency (note) 2 16 mhz temperature 25 5 c note: even though included in above operati ng area, part of frequency can not be supported in serial prom mode. for details, refer to. 2.19.2 memory mapping the boot-rom is mapped in address 3800 h to 3fff h . the figure 2.19.1 shows a memory mapping. figure 2.19.1 memory address maps 2.19.3 serial prom mode setting 2.19.3.1 serial prom mode control pins to execute on-board programming, start the TMP86FM48 in serial prom mode. setting of a serial prom mode is shown in table 2.19.2. table 2.19.2 serial prom mode setting pin setting boot pin high reset pin 0000 h 64 bytes 2048 bytes 128 bytes sfr ram dbr flash memory 32768 bytes 003f h 0040 h 083f h 1f80 h 1fff h ffff h 2048 bytes boot rom 3800 h 3fff h 8000 h
TMP86FM48 2007-08-24 86fm48-173 2.19.3.2 pin function in the serial prom mode, txd (p06) and rxd (p05) pins are used as a serial interface pin. pin name (serial prom mode) input/ output function pin name (mcu mode) txd output serial data output p06 rxd input serial data input p05 boot input serial prom mode control boot reset input serial prom mode control (note 1) reset test input 0v test vdd, avdd 2.7 v to 3.6 v vss, avss/vass 0v varef power supply open or equal with vdd p00 to p04,p07 p10 to p17 p20 to p22 p30 to p37 p50 to p52 p60 to p67 p70 to p77 p80 to p87 i/o placed in high-z state during serial prom mode. xin input xout output resonator connecting pins for high-frequency clock. for inputting external clock, xin is used and xout is opened. (note 2) note 1: when the device is used as on-board writing and other parts are already mounted in place, be careful no to affect these communication control pins. note 2: operating area of high frequency in serial prom mode is from 2 mhz to 16 mhz. to set a serial prom mode, connect de vice pins as shown in figure 2.19.2. figure 2.19.2 serial prom mode port setting external control vdd ( 2.7 v to 3.6 v ) gnd xout gnd vdd avdd varef boot rxd(p05) txd(p06) reset test avss/vass mcu mode xin TMP86FM48 serial prom mode
TMP86FM48 2007-08-24 86fm48-174 2.19.3.3 activating serial prom mode the following is a procedure of setting of serial prom mode. figure 2.19.3 shows a serial prom mode timing. (1) turn on the power to the vdd pin. (2) set the reset and test pins to low level. (3) set the boot pin to high level. (4) wait until the power supply and clock sufficiently stabilize. (5) release the reset . (set to high level) (6) input a matching data (5ah) to rxd pin after waiting for setup sequence. for details of the setup timing, re fer to ?2.19.14 uart timing? figure 2.19.3 serial prom mode timing 2.19.4 interface specifications for uart the following shows the uart communication format used in serial prom mode. before on-board programming can be executed, the communication format on the external controller side must also be set up in the same way as for this product. note that although the default baud rate is 9600 bps, it can be changed to other values as shown in table 2.19.3. the table 2.19.4 show s an operating frequency and baud rate in serial prom mode. except frequency which is not described in table 2.19.4 can not use in serial prom mode. baud rate (default): 9600 bps data length: 8 bits parity addition: none stop bit length: 1 bit table 2.19.3 baud rate modification data baud rate modification data 04h 05h 06h 07h 0ah 18h 28h baud rate (bps) 76800 62500 57600 38400 31250 19200 9600 vdd boot(input) test(input) reset (input) program rxd (input) matching data input serial prom mode reset mode indeterminate setu p time for serial prom mode ( rxsu p) warm-up
TMP86FM48 2007-08-24 86fm48-175 table 2.19.4 operating frequency and baud rate in serial prom mode reference baud rate (bps) 76800 62500 57600 38400 31250 19200 9600 baud rate modification data 04h 05h 06h 07h 0ah 18h 28h (note 3) ref. frequency (mhz) area (mhz) baud rate (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) 1 2 1.91~2.10 ? ? ? ? ? ? ? ? ? ? ? ? 9615 + 0.16 4 3.82~4.19 ? ? ? ? ? ? ? ? 31250 0.00 19231 + 0.16 9615 + 0.16 2 4.19 3.82~4.19 ? ? ? ? ? ? ? ? 32734 + 4.75 20144 + 4.92 10072 + 4.92 4.9152 4.70~5.16 ? ? ? ? ? ? 38400 0.00 ? ? 19200 0.00 9600 0.00 3 5 4.70~5.16 ? ? ? ? ? ? 39063 + 1.73 ? ? 19531 + 1.73 9766 + 1.73 6 5.87~6.45 ? ? ? ? ? ? - ? ? ? ? ? 9375 ? 2.34 4 6.144 5.87~6.45 ? ? ? ? ? ? - ? ? ? ? ? 9600 0.00 5 7.3728 7.05~7.74 ? ? ? 57600 0.00 - ? ? ? 19200 0.00 9600 0.00 6 8 7.64~8.39 ? ? 62500 0.00 - ? 38462 + 0.16 31250 0.00 19231 + 0.16 9615 + 0.16 9.8304 9.40~10.32 76800 0.00 ? ? - ? 38400 0.00 ? ? 19200 0.00 9600 0.00 7 10 9.40~10.32 78125 + 1.73 ? ? - ? 39063 + 1.73 ? ? 19531 + 1.73 9766 + 1.73 12 11.75~12.90 ? ? ? ? 57692 + 0.16 - ? 31250 0.00 18750 ? 2.34 9375 ? 2.34 12.288 11.75~12.90 ? ? ? ? 59077 + 2.56 - ? 32000 + 2.40 19200 0.00 9600 0.00 8 12.5 11.75~12.90 ? ? 60096 ? 3.85 60096 + 4.33 - ? 30048 ? 3.85 19531 + 1.73 9766 + 1.73 9 14.7456 14.10~15.48 ? ? ? ? 57600 0.00 38400 0.00 ? ? 19200 0.00 9600 0.00 10 16 15.27~16.77 76923 + 0.16 62500 0.00 ? ? 38462 + 0.16 31250 0.00 19231 + 0.16 9615 + 0.16 note 1: ?ref.frequency? and ?area? show the high frequency area supported in serial prom mode. except the above frequency can not be supported in serial prom mode even though the high frequency is included in area from 2 mhz to 16 mhz. note 2: the total error of frequency must be kept within + / ? 3% so that the auto-detection of frequency is executed correctly. note 3: an external controller should tr ansmit a matching data repeatedly till the TMP86FM48 transmit an echo back data. above number indicates a transmission number of times of matc hing data till transmis sion of echo back data. 2.19.5 command there are five commands in serial prom mode. after reset release, the TMP86FM48 waits a matching data (5ah). table 2.19.5 command in serial prom mode command data operation mode remarks 5ah setup matching data. always start wi th this command after reset release. 30h flash memory writing writing to area from 8000h to ffffh is enable. 60h ram loader writing to area from 0050h to 082fh is enable. 90h flash memory sum output the checksum of entire flash area (from 8000h to ffffh) is output in order of the upper byte and the lower byte. c0h product discrimination code output product discrimination code, that is expressed by 13 bytes data, is output.
TMP86FM48 2007-08-24 86fm48-176 2.19.6 operation mode there are four operating modes in serial prom mode: flash memory writing mode, ram loader mode, flash memory sum output mode and product discrimination code output mode. for details about these modes, refer to ?(1) flash memory writing mode? through ?(4) product discrimination code output mode?. (1) flash memory writing mode the data are written to the specified flash memory addresses. the controller should send the write data in the intel hex format (binary). for details of writing data format, refer to ?2.19.7 flash memory writing data format?. if no errors are encountered till the end record, the sum of 32 kbytes of flash memory is calculated and the result is returned to the controller. to execute the flash memory writing mode, the TMP86FM48 checks the passwords except a blank product. if the passwords did not match, the program is not executed. (2) ram loader mode the ram loader transfers the data into the internal ram that has been sent from the controller in intel hex format. when th e transfer has terminated normally, the ram loader calculates the sum and sends the result to the controller before it starts executing the user program. after sending of sum, the program jumps to the start address of ram in which the first transferred data has been written. this ram loader function provides the user?s own way to control on-board programming. to execute the ram loader mode, the TMP86FM48 checks the passwords except a blank product. if the passwords did not match, the program is not executed. (3) flash memory sum output mode the sum of 32 kbytes of flash memory is calculated and the result is returned to the controller. the boot rom does not support the reading function of the flash memory. instead, it has this sum command to use. by reading the sum, it is possible to manage revisions of application programs. (4) product discrimination code output mode the product discrimination code is output as a 13-byte data, that includes the start address and the end address of rom (in case of TMP86FM48, the start address is 8000h and the end address is ffffh). theref ore, the controller can recognize the device information by using this function.
TMP86FM48 2007-08-24 86fm48-177 2.19.6.1 flash writing mode (operation command: 30h) table 2.19.6 shows flash memory writing mode process. table 2.19.6 flash writing mode process number of bytes transferred transfer data from external controller to TMP86FM48 baud rate transfer data from TMP86FM48 to external controller 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.19.3) ? 9600 bps 9600 bps ? ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (30h) ? changed new baud rate changed new baud rate ? ok: echo back data (30h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte address 15 to 08 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 9th byte 10th byte address 07 to 00 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 11th byte 12th byte address 15 to 08 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 13th byte 14th byte address 07 to 00 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 15th byte : m?th byte password string (note 5) ? changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) m?th + 1 byte : n?th ? 2 byte intel hex format (binary) (note 2) changed new baud rate ? n?th ? 1 byte ? changed new baud rate ok: sum (high) (note 3) error: nothing transmitted n?th byte ? changed new baud rate ok: sum (low) (note 3) error: nothing transmitted boot rom n?th + 1 byte (wait for the next operation) (command data) changed new baud rate ? note 1: ?xxh 3? denotes that operation stops afte r sending 3 bytes of xxh. for details, refer to ?2.19.8 error code?. note 2: refer to ?2.19.10 in tel hex format (binary)?. note 3: refer to ?2.19.9 checksum (sum)?. note 4: refer to ?2.19.11 passwords?. note 5: if all data of addresses from ffe0h to ffffh are ?00h? or ?ffh?, the passwords comparison is not executed because the device is considered as blank product. however, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. if a password error occurs, the uart function of TMP86FM48 stops without returning error code to the controller. therefore, when a password error occurs, the TMP86FM48 should be reset by reset pin input.
TMP86FM48 2007-08-24 86fm48-178 description of flash memory writing mode 1. the receive data in the 1st byte is the matching data. when the boot program starts in serial prom mode, TMP86FM48 (mentioned as ?device? hereafter) waits for the matching data (5ah) to receive. upon receiving the matching data, it automatically adjusts the uart?s initial baud rate to 9,600bps. 2. when the device has received the matching data, the device transmits the data ?5ah? as an echo back to the controller. if the device can not receive the matching data, the device does not transmit the echo back data and waits for the matching data again with changing baud rate. therefore, the controller should send the matching data continuously until the device transmits the echo back data. an external controller should transmit a ma tching data repeatedly till the device transmit an echo back data. the transmi ssion number of times of matching data varies by the frequency of device. for details, refer to table 2.19.4. 3. the receive data in the 3rd byte is the baud rate modification data. the seven kinds of baud rate modification data show n in table 2.19.3 are available. even if baud rate changing is no need, be sure to send the initial baud rate data (28h: 9,600 bps). 4. when the 3rd byte data is one of the baud rate modification data corresponding to the device's operating frequency, the device sends the echo back data which is the same as received baud rate modification data. then the baud rate is changed. if the 3rd byte data does not correspond to the baud rate modification data, the device stops uart function after sending 3 bytes of baud rate modification error code: (62h). the changing of baud rate is executed after transmitting the echo back data. 5. the receive data in the 5th byte is the command data (30h) to write the flash memory. 6. when the 5th byte is one of the oper ation command data shown in table 2.19.5, the device sends the echo back data which is the same as received operation command data (in this case, 30h). if the 5th byte data does not correspond to the operation command data, the device stops uart function after sending 3 bytes of operation command error code: (63h). 7. the 7th byte is used as an upper bit ( bit15 to bit8) of the password count storage address. when the receiving is executed correctly (no error), the device does not send any data. if the receiving error occu rs, the device stops uart function after sending 3 bytes of receiving error code: (a1h or a3h). 8. the 9th byte is used as a lower bit (b it7 to bit0) of the password count storage address. when the receiving is executed correctly (no error), the device does not send any data. if the receiving error occu rs, the device stops uart function after sending 3 bytes of receiving error code: (a1h or a3h). 9. the 11th byte is used as an upper bit (bit15 to bit8) of the password comparison start address. when the receiving is executed correctly (no error), the device does not send any data. if the receiving error occurs, the device stops uart function after sending 3 bytes of receiv ing error code: (a1h or a3h). 10. the 13th byte is used as a lower bit (bit7 to bit0) of the password comparison start address. when the receiving is executed correctly (no error), the device does not send any data. if the receiving error occu rs, the device stops uart function after sending 3 bytes of receiving error code: (a1h or a3h).
TMP86FM48 2007-08-24 86fm48-179 11. the 15th through the m?th bytes are the password data. the number of passwords is the data (n) indicated by the password count storage address. the password data are compared for n entries beginning with the password comparison start address. the controller should send n bytes of password data to the device. if the passwords do not match, the device stop s uart function without returning error code to the controller. if the data of addresses from ffe0h to ffffh are all ?ffh?, the comparison of passwords is not executed because the device is considered as a blank product. 12. the receive data in the m?th + 1 through n?th ? 2 byte are received as binary data in intel hex format. no received data are echoed back to the controller. the data which is not the start mark (3ah for ?:?) in intel hex format is ignored and does not send an error code to the controller until the device receives the start mark. after receiving the start mark, the device receives the data record, that consists of length of data, address, record type, writing data and checksum. after receiving the checksum of data record, the device waits the start mark data (3ah) again. the data of data record is temporarily stored to ram and then, is written to specified flash memory by page (64 bytes) writing. for details of an organization of flash, refer to ?2.19.7 serial prom mode?. since after receiving an end record, the device starts to calculate the sum, the controller should wait the sum after sending the end record. if receive error or intel hex format error occurs, the device stops uart function without returning error code to the controller. 13. the n?th ? 1 and the n?th bytes are the sum value that is sent to the controller in order of the upper byte and the lower byte. for details on how to calculate the sum, refer to ?2.19.9 checksum (sum)?. the sum calculation is performed after detecting the end record, but the calculation is not executed when receive error or intel hex format error has occurred. the time required to calculate the sum of the 32 kbytes of flash memory area is approximately 100 ms at fc = 16 mhz. after the sum calculation, the device sends the sum data to the controller. after sending the end record, the controller can judge that the transmission has been terminated correctly by receiving the checksum. 14. after sending the sum, the device waits for the next operation command data.
TMP86FM48 2007-08-24 86fm48-180 2.19.6.2 ram loader mode (operation command: 60h) table 2.19.7 shows ram loader mode process. table 2.19.7 ram loader mode process number of bytes transferred transfer data from external controller to TMP86FM48 baud rate transfer data from TMP86FM48 to external controller 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.19.3) ? 9600 bps 9600 bps ? ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (60h) ? changed new baud rate changed new baud rate ? ok: echo back data (60h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte address 15 to 08 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 9th byte 10th byte address 07 to 00 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 11th byte 12th byte address 15 to 08 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 13th byte 14th byte address 07 to 00 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) 15th byte : m?th byte password string (note 5) ? changed new baud rate changed new baud rate ? ok: nothing transmitted error: a1h 3, a3h 3 (note 1) m?th + 1 byte : n?th ? 2 byte intel hex format (binary) (note 2) changed new baud rate ? n?th ? 1 byte ? changed new baud rate ok: sum (high) (note 3) error: nothing transmitted boot rom n?th byte ? changed new baud rate ok: sum (low) (note 3) error: nothing transmitted ram ? the program jumps to the start address of ram in which the first transferred data has been written. note 1: ?xxh 3? denotes that operation stops after sending 3 bytes of xxh. for details, refer to 2.19.8 ?error code?. note 2: refer to 2.19.10 ?int el hex format (binary)?. note 3: refer to 2.19.9 ?checksum (sum)?. note 4: refer to 2.19.11 ?passwords?. note 5: if all data of addresses from ffe 0h to ffffh are ?00h? or ?ffh?, the passwords comparison is not executed because the device is considered as blank product. however, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. if a password error occurs, the uart function of TMP86FM48 stops without returning error code to the controller. therefore, when a password error
TMP86FM48 2007-08-24 86fm48-181 occurs, the TMP86FM48 should be reset by reset pin input. note 6: do not send only end record after transferring of password string. if the TMP86FM48 receives the end record only af ter reception of password string, it does not operate correctly. note 7: when the flash power supply is turned off in user?s program by setting eepcr, be sure to disable t he watchdog timer (wdt) or to clear the binary counter of wdt immediately before. description of ram loader mode 1. the process of the 1st byte through the 4th byte are the same as flash memory writing mode. 2. the receive data in the 5th byte is the ram loader command data (60h) to write the user?s program to ram. 3. when the 5th byte is one of the oper ation command data shown in table 2.19.5, the device sends the echo back data which is the same as received operation command data (in this case, 60h). if the 5th byte data does not correspond to the operation command data, the device stops uart function after sending 3 bytes of operation command error code: (63h). 4. the process of the 7th byte through the m?th byte are the same as flash memory writing mode. 5. the receive data in the m?th + 1 through n'th ? 2byte are received as binary data in intel hex format. no received data are echoed back to the controller. the data which is not the start mark (3ah for ?:?) in intel hex format is ignored and does not send an error code to the cont roller until the device receives the start mark. after receiving the start mark, the device receives the data record, that consists of length of data, address, reco rd type, writing data and checksum. after receiving the checksum of data record, th e device waits the start mark data (3ah) again. the data of data record is written to specified ram by the receiving data. since after receiving an end record, the de vice starts to calculate the sum, the controller should wait the sum after sending the end record. if receive error or intel hex format error occurs, the uart function of TMP86FM48 stops without returning error code to the controller. 6. the n?th ? 1 and the n?th bytes are the sum value that is sent to the controller in order of the upper byte and the lower byte. for details on how to calculate the sum, refer to 2.19.9 ?checksum (sum)?. the sum calculation is performed after detecting the end record, but the calculation is not executed when receive error or intel hex format error has occurred. the sum is calculated by the data written to ram, but the length of data, address, record type and checksum in intel hex format are not included in sum. 7. the boot program jumps to the first addre ss that is received as data in intel hex format after sending the sum to the controller.
TMP86FM48 2007-08-24 86fm48-182 2.19.6.3 flash memory sum output mode (operation command: 90h) table 2.19.8 shows flash memory sum output mode process. table 2.19.8 flash memory sum output process number of bytes transferred transfer data from external controller to TMP86FM48 baud rate transfer data from TMP86FM48 to external controller 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.19.3) ? 9600 bps 9600 bps ? ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (90h) ? changed new baud rate changed new baud rate ? ok: echo back data (90h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte ? changed new baud rate ok: sum (high) (note 2) error: nothing transmitted 8th byte ? changed new baud rate ok: sum (low) (note 2) error: nothing transmitted boot rom 9th byte (wait for the next operation) (command data) changed new baud rate ? note 1: ?xxh 3? denotes that operation stops after sending 3 bytes of xxh. for details, refer to ?2.19.8 error code?. note 2: refer to ?2.19.9 checksum (sum)? description of flash memory sum output mode 1. the process of the 1st byte through the 4th byte are the same as flash memory writing mode. 2. the receive data in the 5th byte is the flash memory sum command data (90h) to calculate the entire flash memory. 3. when the 5th byte is one of the oper ation command data shown in table 2.19.5, the device sends the echo back data which is the same as received operation command data (in this case, 90h). if the 5th byte data does not correspond to the operation command data, the device stops uart function after sending 3 bytes of operation command error code: (63h). 4. the 7th and the 8th bytes are the sum value that is sent to the controller in order of the upper byte and the lower byte. for details on how to calculate the sum, refer to ?2.19.9 checksum (sum)?. 5. after sending the sum, the device waits for the next operation command data.
TMP86FM48 2007-08-24 86fm48-183 2.19.6.4 product discrimination code ou tput mode (operation command: c0h) table 2.19.9 shows product discrimination code output mode process. table 2.19.9 product discrimi nation code output process number of bytes transferred transfer data from external controller to TMP86FM48 baud rate transfer data from TMP86FM48 to external controller 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.19.3) ? 9600 bps 9600 bps ? ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (c0h) ? changed new baud rate changed new baud rate ? ok: echo back data (c0h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte changed new baud rate 3ah start mark 8th byte changed new baud rate 0ah the number of transfer data (from 9th to 18th byte) 9th byte changed new baud rate 02h length of address (2 bytes) 10th byte changed new baud rate 00h reserved data 11th byte changed new baud rate 00h reserved data 12th byte changed new baud rate 00h reserved data 13th byte changed new baud rate 00h reserved data 14th byte changed new baud rate 01h the number of rom block (1 block) 15th byte changed new baud rate 80h first address of rom 16th byte changed new baud rate 00h 17th byte changed new baud rate ffh end address of rom 18th byte changed new baud rate ffh 19th byte changed new baud rate 7fh checksum of transferred data (from 9th to 18th byte) boot rom 20th byte (wait for the next operation) (command data) changed new baud rate ? note: ?xxh 3? denotes that operation stops after sending 3 bytes of xxh. for details, refer to ?2.19.8 error code?. description of product discrimination code output mode 1. the process of the 1st byte through the 4th byte are the same as flash memory writing mode. 2. the receive data in the 5th byte is the product discrimination code output command data (c0h). 3. when the 5th byte is one of the oper ation command data shown in table 2.19.5, the device sends the echo back data which is the same as received operation command data (in this case, c0h). if the 5th byte data does not correspond to the operation command data, the device stops uart function after sending 3 bytes of operation command error code: (63h). 4. the 7th and the 19th bytes are the product discrimination code. for details, refer to 2.19.12 ?product di scrimination code?. 5. after sending the sum, the device waits for the next operation command data.
TMP86FM48 2007-08-24 86fm48-184 2.19.7 flash memory writing data format flash area of TMP86FM48 consists of 512 pages and one page size is 64 bytes. writing to flash is executed by page writing. therefore, it is necessary to send 64 bytes data (for one page) even though only a few bytes data are written. figure 2.19.4 shows an organization of flash area. when the controller sends the writing data to the device, be sure to keep the form at described below. 1. the address of data after receiving the flash writing command should be the first address of page. for example, in case of page 2, the first address should be 8080h. 2. if the last data?s address of data record is not end address of page, the address of the next data record should be the address + 1. for example, if the last data?s address is 802fh (page 0), the address of the next data record should be 8030h (page 0). ex) :10802000202122232425262728292a2b2c2d2e2fd8 ' 8020h to 802fh data :10803000303132333435363738393a3b3c3d3e3fc8 ' 8030h to 803fh data 3. the last data?s address of data record immediately before sending the end record should be the last address of page. for example, in case of page 1, the last data?s address of data record should be 807fh. ex) :10807000303132333435363738393a3b3c3d3e3f88 ' 8070h to 807fh data :00000001ff ' end record note: do not write only the addresses from ffe0h to ffffh when all data of flash memory are the same data. if these area are only written, the next operation can not be executed because of password error. address 0 1 2 3 4 5 6 7 8 9 a b c d e f 8000h f 8010h 8020h page 0 8030h e 8040h f 8050h 8060h page 1 8070h e 8080h f 8090h 80a0h page 2 80b0h e 80c0h : : ff70h e ff80h f ff90h ffa0h page 510 ffb0h e ffc0h f ffd0h ffe0h page 511 fff0h e note: ?f? shows the first address of each page and ?e? shows the last address of each page. figure 2.19.4 organization of flash area
TMP86FM48 2007-08-24 86fm48-185 2.19.8 error code when the device detects an error, the error codes are sent to the controller. table 2.19.10 error code transmit data meaning of transmit data 62h, 62h, 62h baud rate modification error occurred. 63h, 63h, 63h operating command error occurred. a1h, a1h, a1h framing error in received data occurred. a3h, a3h, a3h overrun error in received data occurred. note1: if password error occurs, the TMP86FM48 doesn?t send error codes. 2.19.9 checksum (sum) (1) calculation method sum consists of byte + byte... + byte, the checksum of which is returned in word as the result. namely, data is read out in byte and checksum of which is calculated, with the result returned in word. example: a1h if the data to be calculated consists of the four bytes shown to the left, sum of the data is b2h c3h d4h a1h + b2h + c3h + d4h = 02eah sum (high) = 02h sum (low) = eah the sum returned when executing the flash memory write command, ram loader command, or flash memory sum command is calculated in the manner shown above. (2) calculation data the data from which sum is calculated are listed in table 2.19.11 below. table 2.19.11 checksum calculation data operating mode calculation data remarks flash memory writing mode flash memory sum output mode data in the entire area (32 kbytes) of flash memory even when written to part of the flash area, data in the entire memory area (32 kbytes) is calculated. the length of data, address, record type and checksum in intel hex format are not included in sum. ram loader mode data written to ram the length of data, address, record type and checksum in intel hex format are not included in sum. product discrimination code output mode checksum of transferred data (from 9th to 18th byte) for details, refer to 2.19.12 product discrimination code.
TMP86FM48 2007-08-24 86fm48-186 2.19.10 intel hex format (binary) 1. after receiving the checksum of a record, th e device waits for the start mark data (3ah for ?:?) of the next record. therefore, the device ignores the data, which does not match the start mark data after receiving the checksum of a record. 2. make sure that once the controller program has finished sending the checksum of the end record, it does not send anything and wa its for two bytes of data to be received (upper and lower bytes of checksum). this is because after receiving the checksum of the end record, the boot program calculates the checksum and returns the calculated checksum in two bytes to the controller. 3. if a receive error or intel hex format e rror occurs, the uart fu nction of TMP86FM48 stops without returning error code to the cont roller. in the following cases, an intel hex format error occurs: ? when the record type is not 00h, 01h, or 02h ? when a sum error occurred ? when the data length of an extended record (type = 02h) is not 02h ? when the address of an extended record (type = 02h) is larger than 1000h and after that, receives the data record ? when the data length of the end record (type = 01h) is not 00h 2.19.11 passwords the eight or more bytes consecutive data in flash memory area can be used as password. in password check, TMP86FM48 compares thes e data with data which are transmitted from the external controller. the area in which passwords can be specified is located at addresses 8000h to ff9fh. the area from ffa0h to ffffh can not be specified as passwords area. the device compares the stored passwords with the passwords, which are received from the controller. if all data of addresses from ffe0h to ffffh are ?00h? or ?ffh?, the passwords comparison is not executed because the device is considered as blank product. it is necessary to specify the pa ssword count storage addresses and the password comparison start address even though it is a blank product. table 2.19.12 shows the password setting in the blank product and non blank product.
TMP86FM48 2007-08-24 86fm48-187 table 2.19.12 password setting in t he blank product and non blank product password blank product (note 1) non blank product pnsa (password count storage addresses) 8000h pnsa ff9fh 8000h pnsa ff9fh pcsa (password comparison start address) 8000h pcsa ff9fh 8000h pcsa ffa0 ? n n (password count) * 8 n setting of password no need need (note 2) note 1: when all data of addresses from ffe 0h to ffffh area are ?00h? or ?ffh?, the device is judged as blank product. note 2: the same three or more bytes consecutive data can not be used as password. when the password includes the same co nsecutive data (three or more bytes), the password error occurs. if the passwor d error occurred, the uart function of device stops without returning error code. note 3: *: don?t care. note 4: when the password doesn't matc h the above condition, the password error occurs. if the password error occurred , the uart function of device stops without returning error code. 2.19.11.1 confirmation method of the blank product and non blank product the external controller can confirm whether the device is the blank product or not, by transmission of data described below. (1) executes flash memory writing mode or ram loader mode. (2) transmits the pnsa and pcsa. (3) transmits the end record. (4) in case of the blank product, the device sends checksum of fl ash memory. in case of the non blank product, the device does n?t send checksum of flash memory but the uart function stops without sending any data. the external controller can confirm the blank product and non blank product by receiving checksum. note: when the uart function stops in non blank product, the TMP86FM48 should be reset by pin reset input for restarting the serial prom mode.
TMP86FM48 2007-08-24 86fm48-188 2.19.11.2 password string a string of passwords in the received data are compared with the data in the flash memory. in the following case s, a password error occurs: ? when the received data does not match the data in the flash memory 2.19.11.3 handling of password error if a password error occurs, the uart function of TMP86FM48 stops without returning error code to the controller. ther efore, when a password error occurs, the TMP86FM48 should be reset by reset pin input. 08h 8012h 01h 8107h 02h 8108h 03h 8109h 04h 810ah flash memory 05h 810bh 06h 810ch 07h 810dh 08h 810eh 80h 12h 81h 07h 01h 02h 03h 04h 05h 06h 07h 08h uart pnsa pcsa password string 8 bytes rxd pin comparison ?08h? is treated as the number of password. example pnsa = 8012h pcsa = 8107h password string = 01h, 02h, 03h, 04h, 05h, 06h, 07h, 08h
TMP86FM48 2007-08-24 86fm48-189 2.19.12 product discrimination code the product discrimination code is a 13-byte data, that includes the start address and the end address of rom. table 2.19.13 shows the product discrimination code format. table 2.19.13 product discrimination code format data the meaning of data in case of TMP86FM48 1st start mark (3ah) 3ah 2nd the number of transfer data (from 3rd to 12th byte) 0ah 3rd length of address 02h 4th reserved data 00h 5th reserved data 00h 6th reserved data 00h 7th reserved data 00h 8th the number of rom block 01h 9th the upper byte of the first address of rom 80h 10th the lower byte of the first address of rom 00h 11th the upper byte of the end address of rom ffh 12th the lower byte of the end address of rom ffh 13th checksum of transferred data (from 3rd to 12th byte) 7fh
TMP86FM48 2007-08-24 86fm48-190 2.19.13 flowchart start setup uart data receive receive data = ?5ah? change baud rate (adjust to 9600 baud source clock) no yes uart data transmit (transmit data = ?5ah?) uart data receive change baud rate by receive data receive data = 30h (flash memory writing mode) receive data = 60h (ram loader mode) receive data = 90h (flash sum output mode) uart data receive (intel hex format) uart data transmit (check-sum) uart data receive uart data transmit (transmit data = 30h) uart data transmit (transmit data = 60h) password certification (compare receive data and flash data) uart data receive (intel hex format) uart data transmit (check sum) jumps to start address of user program uart data transmit (transmit data = 90h) uart data transmit (check sum) receive data = c0h (product discrimination code output mode) uart data transmit (transmit data = c0h) password certification (compare receive data and flash data) flash write process ram write process uart data transmit (product discrimination code) uart data transmit ( echoed back the baud rate modification data )
TMP86FM48 2007-08-24 86fm48-191 2.19.14 uart timing table 2.19.14 uart timing-1 (vdd = 2.7 v to 3.6 v, fc = 2 mhz to 16 mhz, ta = 25c) required minimum time parameter symbol the number of clock (fc) at fc = 2 mhz at fc = 16 mhz time from the reception of a matching data until the output of an echo back cmeb1 approx. 600 300 s 37.5 s time from the reception of a baud rate modification data until the output of an echo back cmeb2 approx. 700 350 s 43.7 s time from the reception of an operation command until the output of an echo back cmeb3 approx. 600 300 s 37.5 s calculation time of checksum ck sm approx. 1573000 786.5 ms 98.3 ms table 2.19.15 uart timing-2 (vdd = 2.7 v to 3.6 v, fc = 2 mhz to 16 mhz, ta = 25c) required minimum time parameter symbol the number of clock (fc) at fc = 2 mhz at fc = 16 mhz time from reset release until acceptance of start bit of rxd pin rxsup 110000 55 ms 6.9 ms time between a matching data and the next matching data cmtr1 28500 14.3 ms 1.8 ms time from the echo back of matching data until the acceptance of baud rate modification data cmtr2 600 300 s 37.5 s time from the output of echo back of baud rate modification data until the acceptance of an operation command cmtr3 750 375 s 46.9 s time from the output of echo back of operation command until the acceptance of password count storage addresses cmtr4 950 475 s 59.4 s rxsu p cmtr2 cmtr3 cmtr4 reset pin (TMP86FM48) ( 5ah ) ( 28h ) ( 30h ) rxd p in ( TMP86FM48 ) ( 5ah ) ( 28h ) ( 30h ) txd p in ( TMP86FM48 ) cmeb1 cmeb2 cmeb3 ( 5ah ) ( 5ah ) ( 5ah ) cmtr1 rxd p in ( TMP86FM48 ) txd p in ( TMP86FM48 )
TMP86FM48 2007-08-24 86fm48-192 input/output circuitry (1) control pins the input/output circuitries of the TMP86FM48 control pins are shown below. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins (high frequency) r f = 3 m ? (typ.) r o = 0.5 k ? (typ.) normal1 mode normal2 mode xtin xtout input output refer to port p2 resonator connecting pins (low frequency) r f = 20 m ? (typ.) r o = 220 k ? (typ.) reset input hysteresis input pull-up resistor r in = 220 k ? (typ.) r = 100 ? (typ.) test input pull-down resistor r in = 70 k ? (typ.) r = 100 ? (typ.) boot input pull-down resistor r in = 70 k ? (typ.) r = 100 ? (typ.) osc. enable fc vdd vdd xin xout r f r o r in vdd r r in vdd r osc. enable fc vdd vdd xin xout r f r o xten r a ddress-trap-reset watchdog-timer system-clock-reset r in vdd r
TMP86FM48 2007-08-24 86fm48-193 (2) input/output ports port i/o input/output circuitry remarks p0 p1 i/o initial ?high-z? sink open drain output or cmos output hysteresis input r = 100 ? (typ.) p20 i/o initial ?high-z? sink open drain output or cmos output hysteresis input r = 100 ? (typ.) p21 p22 i/o initial ?high-z? sink open drain output or cmos output hysteresis input programmable pull-up resistor r in3 = 220 k ? (typ.) p3 i/o initial ?high-z? sink open drain or cmos output hysteresis input high current output (nch) r = 100 ? (typ.) p5 i/o initial ?high-z? sink open drain output or cmos output hysteresis input high current output (nch) r = 100 ? (typ.) r vdd pch control input from output latch pin input (control input) data output disable (control output) r vdd resistor control input from output latch pin input disable data output r in3 pull-up resistor r vdd pch control input from output latch pin input disable data output r vdd pch control input from output latch pin input data output disable (control output) r vdd pch control input from output latch pin input (control input) disable data output
TMP86FM48 2007-08-24 86fm48-194 port i/o input/output circuitry remarks p6 p7 i/o initial ?high-z? tri-state i/o hysteresis input r = 100 ? (typ.) p8 i/o initial ?high-z? tri-state i/o hysteresis input r = 100 ? (typ.) r vdd i/o control input from output latch analog input data output disable input control pin input r vdd i/o control input from output latch data output disable pin input
TMP86FM48 2007-08-24 86fm48-195 electrical characteristics absolute maximum ratings (v ss = 0 v) parameter symbol pins rating unit supply voltage v dd ? 0.3 to 4.0 input voltage v in ? 0.3 to v dd + 0.3 output voltage v out1 ? 0.3 to v dd + 0.3 v i out1 p0, p1, p20, p3, p5, p6, p7, p8 ports ? 2 i out2 p0, p1, p2, p4, p6, p7, p8 ports 2 output current (per 1 pin) i out3 p3, p5 ports 10 i out1 p0, p1, p20, p3, p5, p6, p7, p8 ports ? 30 i out2 p0, p1, p2, p4, p6, p7, p8 ports 80 output current (total) i out3 p3, p5 ports 30 ma power dissipation [topr = 85c] pd 350 mw soldering temperature (time) tsld 260 (10 s) storage temperature tstg ? 55 to 125 operating temperature topr ? 40 to 85 c note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performanc e may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
TMP86FM48 2007-08-24 86fm48-196 recommended operating condition-1 (mcu mode) (v ss = 0 v, topr = ? 40 to 85c) parameter symbol pins condition min max unit normal1, 2 mode fc = 16 mhz idle0, 1, 2 mode 2.7 normal1, 2 mode fc = 8 mhz (in case of connecting the resonator) idle0, 1, 2 mode normal1, 2 mode fc = 4.2 mhz (in case of external clock input) idle0, 1, 2 mode 1.8 slow1, 2 mode fs = 32.768 khz sleep0, 1, 2 mode supply voltage v dd stop mode 1.8 3.6 v ih1 except hysteresis input v dd 0.70 v ih2 hysteresis input v dd 2.7 v v dd 0.75 input high level v ih3 v dd < 2.7 v v dd 0.90 v dd v il1 except hysteresis input v dd 0.30 v il2 hysteresis input v dd 2.7 v v dd 0.25 input low level v il3 v dd < 2.7 v 0 v dd 0.10 v v dd = 1.8 to 3.6 v 8.0 fc xin, xout v dd = 2.7 to 3.6 v 1.0 16.0 mhz clock frequency (in case of connecting the resonator) fs xtin, xtout v dd = 1.8 to 3.6 v 30.0 34.0 khz v dd = 1.8 to 3.6 v 4.2 fc xin, xout v dd = 2.7 to 3.6 v 1.0 16.0 mhz clock frequency (in case of external clock input) fs xtin, xtout v dd = 1.8 to 3.6 v 30.0 34.0 khz note: the recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), ma lfunction may occur. thus, when designing products which include this device, ensure that the re commended operating conditions for the device are always adhered to. recommended operating condition-2 (serial prom mode) (v ss = 0 v, topr = 25c 5c) parameter symbol pins condition min max unit supply voltage vdd 2 mhz fc 16 mhz 2.7 3.6 v clock frequency fc xin, xout vdd = 2.7 to 3.6 v 2.0 16.0 mhz note: the operating temperature area of serial prom mode is 25c 5c and the operating area of high frequency of serial prom mode is different from mcu mode.
TMP86FM48 2007-08-24 86fm48-197 dc characteristics (v ss = 0 v, topr = ? 40 to 85c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input v dd = 3.3 v ? 0.4 ? v i in1 test v dd = 3.6 v, v in = 0 v ? ? ? 5 i in2 sink open drain, tri-state v dd = 3.6 v, v in = 3.6 v/0 v ? ? 5 input current i in3 reset v dd = 3.6 v, v in = 3.6 v ? ? + 5 a r in1 test pull down v dd = 3.6 v, v in = 3.6 v ? 70 ? r in2 boot pull down v dd = 3.6 v, v in = 3.6 v ? 70 ? input resistance r in3 reset pull up p21, p22 ports v dd = 3.6 v, v in = 0 v 100 220 450 k ? high frequency feedback resistor r fb xout v dd = 3.6 v ? 3 ? low frequency feedback resistor r fbt xtout v dd = 3.6 v ? 20 ? m ? output leakage current i lo sink open drain, tri-state v dd = 3.6 v v out = 3.4v/0.2 v ? ? 10 a output high voltage v oh cmos, tri-state v dd = 3.6 v, l oh = ? 0.6 ma 3.2 ? ? output low voltage v ol except xout, p3 and p5 ports v dd = 3.6 v, i ol = 0.9 ma ? ? 0.4 v output low current i ol p3, p5 ports v dd = 3.6 v, v ol = 1.0 v ? 6 ? ma flash area mnp = ?1? ? 5.0 6.0 supply current in normal 1, 2 mode fetch area ram area mnp = ?0? ? 3.5 4.8 mnp?atp = ?1? ? 3.5 4.5 supply current in idle 0, 1, 2 mode v dd = 3.6 v v in = 3.4 v/0.2 v fc = 16 mhz fs = 32.768 khz mnp?atp = ?0? ? 2.5 3.7 ma flash area mnp = ?1? ? 800 1400 supply current in slow 1 mode fetch area ram area mnp = ?0? ? 6 20 mnp?atp = ?1? ? 800 1400 supply current in sleep 1 mode mnp?atp = ?0? ? 5 18 mnp?atp = ?1? ? 800 1400 supply current in sleep 0 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz mnp?atp = ?0? ? 5 18 supply current in stop mode i dd v dd = 3.6 v v in = 3.4 v/0.2 v ? 0.5 10 a note 1: typical values show those at topr = 25c. note 2: input current (i in1 , i in2 ): the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref current. note 4: the supply currents of slow2 and sleep2 m odes are equivalent to idle0, idle1, idle2. note 5: mnp (mnpwdw) shows bit0 in eepcr register and atp (atpwdw) shows bit1 in eepcr register. note 6: ?fetch? means reading operation of flash data as an instruction by cpu.
TMP86FM48 2007-08-24 86fm48-198 ad conversion characteristics (v ss = 0.0 v, 2.7 v v dd 3.6 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 2.5 ? ? analog input voltage v ain v ss ? v aref v power supply current of analog reference voltage i ref v dd = a vdd = v aref = 3.6 v v ss = 0.0 v ? 0.35 0.61 ma non linearity error ? ? 2 zero point error ? ? 2 full scale error ? ? 2 total error v dd = a vdd = 2.7 v v ss = 0.0 v v aref = 2.7 v ? ? 2 lsb (v ss = 0.0 v, 2.0 v v dd < 2.7 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 0.6 ? a vdd power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 2.0 ? ? analog input voltage v ain v ss ? v aref v power supply current of analog reference voltage i ref v dd = a vdd = v aref = 2.0v v ss = 0.0 v ? 0.20 0.34 ma non linearity error ? ? 4 zero point error ? ? 4 full scale error ? ? 4 total error v dd = a vdd = 2.0 v v ss = 0.0 v v aref = 2.0 v ? ? 4 lsb (v ss = 0.0 v, 1.8 v v dd < 2.0 v, topr = ? 10 to 85c) (note 5) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 0.1 ? a vdd power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 1.8 ? ? analog input voltage v ain v ss ? v aref v power supply current of analog reference voltage i ref v dd = a vdd = v aref = 1.8 v v ss = 0.0 v ? 0.18 0.31 ma non linearity error ? ? 4 zero point error ? ? 4 full scale error ? ? 4 total error v dd = a vdd = 1.8 v v ss = 0.0 v v aref = 1.8 v ? ? 4 lsb note 1: the total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please refer to ?2.15.2 register configration?. note 3: please use input voltage to ain input pin in limit of varef ? vss. when voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. note 4: analog reference voltage range: ? varef = varef ? vss note 5: when ad is used with vdd < 2.0 v, the gua ranteed temperature range va ries with the operating voltage. note 6: when ad converter is not used, fix the avdd pin and varefpin on the v dd level.
TMP86FM48 2007-08-24 86fm48-199 ac characteristics (v ss = 0 v, v dd = 2.7 to 3.6 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit normal1, 2 mode idle1, 2 mode 0.25 ? 4 slow1, 2 mode machine cycle time tcy sleep1, 2 mode 117.6 ? 133.3 s high level clock pulse width twch low level clock pulse width twcl for external clock operation (xin input), fc = 16 mhz ? 31.25 ? ns high level clock pulse width twch low level clock pulse width twcl for external clock operation (xtin input), fs = 32.768 khz ? 15.26 ? s (v ss = 0 v, v dd = 1.8 to 3.6 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit normal1, 2 mode idle1, 2 mode 0.5 ? 4 slow1, 2 mode machine cycle time tcy sleep1, 2 mode 117.6 ? 133.3 s high level clock pulse width twch low level clock pulse width twcl for external clock operation (xin input), fc = 4.2 mhz ? 119.04 ? ns high level clock pulse width twch low level clock pulse width twcl for external clock operation (xtin input), fs = 32.768 khz ? 15.26 ? s flash characteristics (v ss = 0 v) parameter condition min typ. max unit number of guaranteed writes (page writing) to flash memory in serial prom mode v dd = 2.7 to 3.6 v, 2 mhz fc 16 mhz (topr = 25c 5c) ? ? 10 5 number of guaranteed writes (page writing) to flash data memory in mcu mode ? ? 10 5 times writing time to flash data memory for one page (64 bytes) in mcu mode v dd = 1.8 to 3.6 v at fc = 8 mhz v dd = 2.7 to 3.6 v at fc = 16 mhz (topr = ? 40 to 85c) ? 4 6 ms recommended oscillating conditions note 1: an electrical shield by metal shield plate on the surface of ic package is recommended in order to protect the device from the high electric field stress applied from crt (cathodic ray tube) for continuous reliable operation. note 2: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following http://www.murata.com/
TMP86FM48 2007-08-24 86fm48-200 handling precaution ? the solderability test conditions for lead-free products (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245c dipping time = 5 seconds number of times = once r-type flux used note : the pass criteron of the above test is as follows: solderability rate until forming 95% ? when using the device (oscillator) in places expose d to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition.
TMP86FM48 2007-08-24 86fm48-201 package dimensions lqfp64-p-1010-0.50e unit: mm 1.25 typ 1.25typ 0.5 m 0.08 0.2 +0.07 - 0.03 0.125 +0.075 - 0.035 49 64 32 48 33 1 16 17 10.0 0.1 12.0 0.2 10.0 0.1 12.0 0.2 1.4 0.05 0.1 0.05 1.6 max 0.08 0.25 0~10 0.45~0.75 (0.5)
TMP86FM48 2007-08-24 86fm48-202 qfp64-p-1414-0.80c unit: mm + 0.08 ? 0.04
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