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? 2000 mos integrated circuit pd16770b 420-output tft-lcd source driver (compatible with 64-gray scales) document no. s14773ej1v0ds00 (1st edition) date published may 2001 ns cp(k) printed in japan data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. description the pd16770b is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 + 0.1 v to v dd2 ? 0.1 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a clock frequency of 45 mhz when driving at 2.3 v, this driver is applicable to sxga + standard tft-lcd panels. features ? cmos level input (2.3 to 3.6 v) ? 420 outputs ? input of 6 bits (gray-scale data) by 6 dots ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter ? logic power supply voltage (v dd1 ): 2.3 to 3.6 v ? driver power supply voltage (v dd2 ): 8.5 0.5 v ? output dynamic range v ss2 + 0.1 v to v dd2 ? 0.1 v ? high-speed data transfer: f clk = 45 mhz (internal data transfer speed when operating at v dd1 = 2.3 v) ? apply for dot-line inversion, n-line inversion and column line inversion ? output voltage polarity inversion function (pol) ? display data inversion function (capable of controlling by each input port) (pol21, pol22) ? current consumption control function (lpc, hpc, bcont) ? slim chip ordering information part number package pd16770bn - tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, please contact one of our sales representatives. the mark shows major revised points.
data sheet s14773ej1v0ds 2 pd16770b 1. block diagram sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 - v 9 pol d 00 - d 05 c 1 c 2 c 69 c 70 stb clk 70-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 - d 15 d 20 - d 25 s 3 s 420 pol21, pol22 d 30 - d 35 d 40 - d 45 d 50 - d 55 bcont hpc lpc remark /xxx indicates active low signal. 2. relationship between output circuit and d/a converter s 1 s 2 s 419 6-bit d/a converter s 420 v 4 5 5 pol multi- plexer v 9 v 0 v 5
data sheet s14773ej1v0ds 3 pd16770b 3. pin configuration ( pd16770bn-xxx: copper foil surface, face-up) s 420 s 419 sthl s 418 d 55 s 417 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 v dd1 r , /l v 9 v 8 v 7 v 6 v 5 v dd2 v ss2 bcont v 4 v 3 v 2 v 1 v 0 hpc v ss1 lpc clk stb pol pol21 pol22 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 s 4 d 02 s 3 d 01 s 2 d 00 s 1 sthr c o pp er f oil surface remark this figure does not specify the tcp package.
data sheet s14773ej1v0ds 4 pd16770b 4. pin functions (1/2) pin symbol pin name description s 1 to s 420 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input these refer to the start pulse input/output pins when driver ics are connected in cascade. the shift directions of the shift registers are as follows. r,/l = h: sthr input, s 1 s 420 , sthl output r,/l = l: sthl input, s 420 s 1 , sthr output sthr right shift start pulse input/output sthl left shift start pulse input/output these refer to the start pulse i/o pins when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. r,/l = h (right shift): sthr input, sthl output r,/l = l (left shift): sthl input, sthr output the start pulse width (h level) for next-level drivers is 1 clk. clk shift clock input refers to the shift register?s shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 70 th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. if 72 clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stb?s rising edge. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l: the s 2n?1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2n?1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n-1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stb?s rising edge. pol21, pol22 data inversion data inversion can invert when display data is loaded. pol21, pol22 = h: data inversion loads display data after inverting it. pol21, pol22 = l: data inversion does not invert input data. pol21: d 00 to d 05 , d 10 to d 15 , d 20 to d 25 pol22: d 30 to d 35 , d 40 to d 45 , d 50 to d 55 lpc low power control input hpc high power control input controls the write function of the driver section by digitally controlling the bypass current of the output amplifier. this pin is pulled up to the v dd1 power supply inside the ic. refer to 9. current consumption control function.
data sheet s14773ej1v0ds 5 pd16770b (2/2) pin symbol pin name description bcont bias control this pin can be used to finely control the bias current inside the output amplifier. when this fine-control function is not required, leave this pin open. refer to 9. current consumption control function. v 0 to v 9 -corrected power supplies input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > 0.5 v dd2 > v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v v dd1 logic power supply 2.3 to 3.6 v v dd2 driver power supply 8.5 v 0.5 v v ss1 logic ground grounding v ss2 driver ground grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down. 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also recommended between the -corrected power supply terminals (v 0 , v 1 , v 2 , , v 9 ) and v ss2 .
data sheet s14773ej1v0ds 6 pd16770b 5. relationship between input data and output voltage value the pd16770b incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd?s counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors (r0 to r62) are designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ? to v 63 ? is almost equivalent. for the 2 sets of five -compensated power supplies, v 0 to v 4 and v 5 to v 9 , respectively, input gray scale voltages of the same polarity with respect to the common voltage. when fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the -compensated power supplies v 1 to v 3 and v 6 to v 8 . figure 5 ? 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships as follows. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > 0.5 v dd2 > v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v. figures 5 ? 2 and 5 ? 3 show the relationship between the input data and the output data and the resistance values of the resistor strings. figure 5 ? ? ? ? 1. relationship between input data and - corrected power supplies 0.1 v 0.1 v v dd2 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 0.5 v dd2 v com v 9 v ss2 00 10 20 30 3f input data (hex) 15 15 16 16 16 16 16 16 split interval
data sheet s14773ej1v0ds 7 pd16770b figure 5 ? ? ? ? 2. relationship between input data and output voltage v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > 0.5 v dd2 , pol21, pol22 = l data d x5 d x4 d x3 d x2 d x1 d x0 rn ( ? ) 00h 000000 v 0 'v 0 r0 1766 01h 000001 v 1 'v 1 +(v 0 -v 1 ) 4585 / 6351 r1 736 02h 000010 v 2 'v 1 +(v 0 -v 1 ) 3849 / 6351 r2 566 03h 000011 v 3 'v 1 +(v 0 -v 1 ) 3283 / 6351 r3 509 04h 000100 v 4 'v 1 +(v 0 -v 1 ) 2774 / 6351 r4 396 05h 000101 v 5 'v 1 +(v 0 -v 1 ) 2378 / 6351 r5 340 06h 000110 v 6 'v 1 +(v 0 -v 1 ) 2038 / 6351 r6 283 07h 000111 v 7 'v 1 +(v 0 -v 1 ) 1755 / 6351 r7 283 08h 001000 v 8 'v 1 +(v 0 -v 1 ) 1472 / 6351 r8 226 09h 001001 v 9 'v 1 +(v 0 -v 1 ) 1246 / 6351 r9 226 0ah 001010 v 10 'v 1 +(v 0 -v 1 ) 1020 / 6351 r10 170 0bh 001011 v 11 'v 1 +(v 0 -v 1 ) 850 / 6351 r11 170 0ch 001100 v 12 'v 1 +(v 0 -v 1 ) 680 / 6351 r12 170 0dh 001101 v 13 'v 1 +(v 0 -v 1 ) 510 / 6351 r13 170 0eh 001110 v 14 'v 1 +(v 0 -v 1 ) 340 / 6351 r14 170 0fh 001111 v 15 'v 1 +(v 0 -v 1 ) 170 / 6351 r15 170 10h 010000 v 16 'v 1 r16 152 11h 010001 v 17 'v 2 +(v 1 -v 2 ) 2280 / 2432 r17 152 12h 010010 v 18 'v 2 +(v 1 -v 2 ) 2128 / 2432 r18 152 13h 010011 v 19 'v 2 +(v 1 -v 2 ) 1976 / 2432 r19 152 14h 010100 v 20 'v 2 +(v 1 -v 2 ) 1824 / 2432 r20 152 15h 010101 v 21 'v 2 +(v 1 -v 2 ) 1672 / 2432 r21 152 16h 010110 v 22 'v 2 +(v 1 -v 2 ) 1520 / 2432 r22 152 17h 010111 v 23 'v 2 +(v 1 -v 2 ) 1368 / 2432 r23 152 18h 011000 v 24 'v 2 +(v 1 -v 2 ) 1216 / 2432 r24 152 19h 011001 v 25 'v 2 +(v 1 -v 2 ) 1064 / 2432 r25 152 1ah 011010 v 26 'v 2 +(v 1 -v 2 ) 912 / 2432 r26 152 1bh 011011 v 27 'v 2 +(v 1 -v 2 ) 760 / 2432 r27 152 1ch 011100 v 28 'v 2 +(v 1 -v 2 ) 608 / 2432 r28 152 1dh 011101 v 29 'v 2 +(v 1 -v 2 ) 456 / 2432 r29 152 1eh 011110 v 30 'v 2 +(v 1 -v 2 ) 304 / 2432 r30 152 1fh 011111 v 31 'v 2 +(v 1 -v 2 ) 152 / 2432 r31 152 20h 100000 v 32 'v 2 r32 156 21h 100001 v 33 'v 3 +(v 2 -v 3 ) 2340 / 2496 r33 156 22h 100010 v 34 'v 3 +(v 2 -v 3 ) 2184 / 2496 r34 156 23h 100011 v 35 'v 3 +(v 2 -v 3 ) 2028 / 2496 r35 156 24h 100100 v 36 'v 3 +(v 2 -v 3 ) 1872 / 2496 r36 156 25h 100101 v 37 'v 3 +(v 2 -v 3 ) 1716 / 2496 r37 156 26h 100110 v 38 'v 3 +(v 2 -v 3 ) 1560 / 2496 r38 156 27h 100111 v 39 'v 3 +(v 2 -v 3 ) 1404 / 2496 r39 156 28h 101000 v 40 'v 3 +(v 2 -v 3 ) 1248 / 2496 r40 156 29h 101001 v 41 'v 3 +(v 2 -v 3 ) 1092 / 2496 r41 156 2ah 101010 v 42 'v 3 +(v 2 -v 3 ) 936 / 2496 r42 156 2bh 101011 v 43 'v 3 +(v 2 -v 3 ) 780 / 2496 r43 156 2ch 101100 v 44 'v 3 +(v 2 -v 3 ) 624 / 2496 r44 156 2dh 101101 v 45 'v 3 +(v 2 -v 3 ) 468 / 2496 r45 156 2eh 101110 v 46 'v 3 +(v 2 -v 3 ) 312 / 2496 r46 156 2fh 101111 v 47 'v 3 +(v 2 -v 3 ) 156 / 2496 r47 156 30h 110000 v 48 'v 3 r48 175 31h 110001 v 49 'v 4 +(v 3 -v 4 ) 4397 / 4572 r49 175 32h 110010 v 50 'v 4 +(v 3 -v 4 ) 4222 / 4572 r50 175 33h 110011 v 51 'v 4 +(v 3 -v 4 ) 4047 / 4572 r51 175 34h 110100 v 52 'v 4 +(v 3 -v 4 ) 3872 / 4572 r52 175 35h 110101 v 53 'v 4 +(v 3 -v 4 ) 3697 / 4572 r53 232 36h 110110 v 54 'v 4 +(v 3 -v 4 ) 3465 / 4572 r54 232 37h 110111 v 55 'v 4 +(v 3 -v 4 ) 3233 / 4572 r55 232 38h 111000 v 56 'v 4 +(v 3 -v 4 ) 3001 / 4572 r56 232 39h 111001 v 57 'v 4 +(v 3 -v 4 ) 2769 / 4572 r57 289 3ah 111010 v 58 'v 4 +(v 3 -v 4 ) 2480 / 4572 r58 345 3bh 111011 v 59 'v 4 +(v 3 -v 4 ) 2135 / 4572 r59 402 3ch 111100 v 60 'v 4 +(v 3 -v 4 ) 1733 / 4572 r60 402 3dh 111101 v 61 'v 4 +(v 3 -v 4 ) 1331 / 4572 r61 459 3eh 111110 v 62 'v 4 +(v 3 -v 4 ) 872 / 4572 r62 872 3fh 111111 v 63 'v 4 rtotal 15851 out p ut volta g e caution there is no connection between v 4 and v 5 terminal in the chip. v 0 ' v 17 ' v 1 ' v 47 ' v 2 ' v 48 ' v 3 ' v 49 ' v 15 ' v 16 ' v 63 ' v 61 ' v 62 ' r 0 r 17 r 1 r 47 r 46 r 2 r 48 r 3 r49 r 14 r 15 r 16 r 60 r 61 r 62 v 4 v 3 v 1 v 0
data sheet s14773ej1v0ds 8 pd16770b figure 5 ? ? ? ? 3. relationship between input data and output voltage 0.5 v dd2 > v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v, pol21, pol22 = l data d x5 d x4 d x3 d x2 d x1 d x0 rn ( ? ) 00h 000000 v 0 '' v 9 r0 1766 01h 000001 v 1 '' v 9 +(v 8 -v 9 ) 1766 / 6351 r1 736 02h 000010 v 2 '' v 9 +(v 8 -v 9 ) 2502 / 6351 r2 566 03h 000011 v 3 '' v 9 +(v 8 -v 9 ) 3068 / 6351 r3 509 04h 000100 v 4 '' v 9 +(v 8 -v 9 ) 3577 / 6351 r4 396 05h 000101 v 5 '' v 9 +(v 8 -v 9 ) 3973 / 6351 r5 340 06h 000110 v 6 '' v 9 +(v 8 -v 9 ) 4313 / 6351 r6 283 07h 000111 v 7 '' v 9 +(v 8 -v 9 ) 4596 / 6351 r7 283 08h 001000 v 8 '' v 9 +(v 8 -v 9 ) 4879 / 6351 r8 226 09h 001001 v 9 '' v 9 +(v 8 -v 9 ) 5105 / 6351 r9 226 0ah 001010 v 10 '' v 9 +(v 8 -v 9 ) 5331 / 6351 r10 170 0bh 001011 v 11 '' v 9 +(v 8 -v 9 ) 5501 / 6351 r11 170 0ch 001100 v 12 '' v 9 +(v 8 -v 9 ) 5671 / 6351 r12 170 0dh 001101 v 13 '' v 9 +(v 8 -v 9 ) 5841 / 6351 r13 170 0eh 001110 v 14 '' v 9 +(v 8 -v 9 ) 6011 / 6351 r14 170 0fh 001111 v 15 '' v 9 +(v 8 -v 9 ) 6181 / 6351 r15 170 10h 010000 v 16 '' v 8 r16 152 11h 010001 v 17 '' v 8 +(v 7 -v 8 ) 152 / 2432 r17 152 12h 010010 v 18 '' v 8 +(v 7 -v 8 ) 304 / 2432 r18 152 13h 010011 v 19 '' v 8 +(v 7 -v 8 ) 456 / 2432 r19 152 14h 010100 v 20 '' v 8 +(v 7 -v 8 ) 608 / 2432 r20 152 15h 010101 v 21 '' v 8 +(v 7 -v 8 ) 760 / 2432 r21 152 16h 010110 v 22 '' v 8 +(v 7 -v 8 ) 912 / 2432 r22 152 17h 010111 v 23 '' v 8 +(v 7 -v 8 ) 1064 / 2432 r23 152 18h 011000 v 24 '' v 8 +(v 7 -v 8 ) 1216 / 2432 r24 152 19h 011001 v 25 '' v 8 +(v 7 -v 8 ) 1368 / 2432 r25 152 1ah 011010 v 26 '' v 8 +(v 7 -v 8 ) 1520 / 2432 r26 152 1bh 011011 v 27 '' v 8 +(v 7 -v 8 ) 1672 / 2432 r27 152 1ch 011100 v 28 '' v 8 +(v 7 -v 8 ) 1824 / 2432 r28 152 1dh 011101 v 29 '' v 8 +(v 7 -v 8 ) 1976 / 2432 r29 152 1eh 011110 v 30 '' v 8 +(v 7 -v 8 ) 2128 / 2432 r30 152 1fh 011111 v 31 '' v 8 +(v 7 -v 8 ) 2280 / 2432 r31 152 20h 100000 v 32 '' v 7 r32 156 21h 100001 v 33 '' v 7 +(v 6 -v 7 ) 156 / 2496 r33 156 22h 100010 v 34 '' v 7 +(v 6 -v 7 ) 312 / 2496 r34 156 23h 100011 v 35 '' v 7 +(v 6 -v 7 ) 468 / 2496 r35 156 24h 100100 v 36 '' v 7 +(v 6 -v 7 ) 624 / 2496 r36 156 25h 100101 v 37 '' v 7 +(v 6 -v 7 ) 780 / 2496 r37 156 26h 100110 v 38 '' v 7 +(v 6 -v 7 ) 936 / 2496 r38 156 27h 100111 v 39 '' v 7 +(v 6 -v 7 ) 1092 / 2496 r39 156 28h 101000 v 40 '' v 7 +(v 6 -v 7 ) 1248 / 2496 r40 156 29h 101001 v 41 '' v 7 +(v 6 -v 7 ) 1404 / 2496 r41 156 2ah 101010 v 42 '' v 7 +(v 6 -v 7 ) 1560 / 2496 r42 156 2bh 101011 v 43 '' v 7 +(v 6 -v 7 ) 1716 / 2496 r43 156 2ch 101100 v 44 '' v 7 +(v 6 -v 7 ) 1872 / 2496 r44 156 2dh 101101 v 45 '' v 7 +(v 6 -v 7 ) 2028 / 2496 r45 156 2eh 101110 v 46 '' v 7 +(v 6 -v 7 ) 2184 / 2496 r46 156 2fh 101111 v 47 '' v 7 +(v 6 -v 7 ) 2340 / 2496 r47 156 30h 110000 v 48 '' v 6 r48 175 31h 110001 v 49 '' v 6 +(v 5 -v 6 ) 175 / 4572 r49 175 32h 110010 v 50 '' v 6 +(v 5 -v 6 ) 350 / 4572 r50 175 33h 110011 v 51 '' v 6 +(v 5 -v 6 ) 525 / 4572 r51 175 34h 110100 v 52 '' v 6 +(v 5 -v 6 ) 700 / 4572 r52 175 35h 110101 v 53 '' v 6 +(v 5 -v 6 ) 875 / 4572 r53 232 36h 110110 v 54 '' v 6 +(v 5 -v 6 ) 1107 / 4572 r54 232 37h 110111 v 55 '' v 6 +(v 5 -v 6 ) 1339 / 4572 r55 232 38h 111000 v 56 '' v 6 +(v 5 -v 6 ) 1571 / 4572 r56 232 39h 111001 v 57 '' v 6 +(v 5 -v 6 ) 1803 / 4572 r57 289 3ah 111010 v 58 '' v 6 +(v 5 -v 6 ) 2092 / 4572 r58 345 3bh 111011 v 59 '' v 6 +(v 5 -v 6 ) 2437 / 4572 r59 402 3ch 111100 v 60 '' v 6 +(v 5 -v 6 ) 2839 / 4572 r60 402 3dh 111101 v 61 '' v 6 +(v 5 -v 6 ) 3241 / 4572 r61 459 3eh 111110 v 62 '' v 6 +(v 5 -v 6 ) 3700 / 4572 r62 872 3fh 111111 v 63 '' v 5 rtotal 15851 out p ut volta g e caution there is no connection between v 4 and v 5 terminal in the chip. v 17 '' v 0 '' v 16 '' v 15 '' v 2 '' v 1 '' v 63 '' v 62 '' v 61 '' v 49 '' v 48 '' v 47 '' r 61 r 60 r 59 r 49 r 48 r 47 r 46 v 6 r 62 v 5 r 17 r 0 r 16 r 15 r 14 r 2 r 1 v 9 v 8 v 60 ''
data sheet s14773ej1v0ds 9 pd16770b 6. relationship between input data and output pin data format: 6 bits 2 rgbs (6 dots) input width: 36 bits (2-pixel data) r,/l = h (right shift) output s 1 s 2 s 3 s 4 xxx s 419 s 420 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 r,/l = l (left shift) output s 1 s 2 s 3 s 4 xxx s 419 s 420 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 pol s 2n?1 note s 2n note lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 note s 2n-1 (odd output), s 2n (even output) 7. relationship between stb, pol and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. selected voltage v 0 to v 4 hi-z stb pol s 2n s 2n-1 hi-z hi-z selected voltage v 5 to v 9 selected voltage v 0 to v 4 selected voltage v 0 to v 4 selected voltage v 5 to v 9 selected voltage v 5 to v 9
data sheet s14773ej1v0ds 10 pd16770b 8. relationship between stb, clk, and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. figure8 ? ? ? ? 1. output circuit block diagram dac + sw1 s n (v out ) v amp(in) output amp figure8 ? ? ? ? 2. output circuit timing waveform stb (external input) (v out : external output) clk (external input) v amp(in) hi-z sw1 : on sw1 : off sw1 : on [1] [2] output output s n remarks 1. stb = l: sw1 = on, stb = h: sw1 = off 2. stb = ?h? is acknowledged at timing [1]. 3. the display data latch is completed at timing [2] and the input voltage (v amp(in) : gray-scale level voltage) of the output amplifier changes.
data sheet s14773ej1v0ds 11 pd16770b 9. current consumption control function the pd16770b has a power control function which can switch the bias current of the output amplifier between four levels and a bias control function (bcont) which can be used to finely control the bias current. the bias current of the output amplifier can be switched between four levels using lpc (low power control) pins and hpc (high power control) pins. power mode lpc hpc high l l middle h or open l normal l h or open low h or open h or open following graph shows the relationship between each power modes and bias current. high mid nomal low 6.00 8.00 7.00 9.00 v dd2 i dd2 remark this relationship is founded on results of simulation and don?t assuring a characteristics of this product.
data sheet s14773ej1v0ds 12 pd16770b it is possible to fine-control the current consumption by using the bias current control function (bcont pin). when using this function, connect this pin to the stabilized ground potential (v ss2 ) via an external resistor (r ext ). when not using this function, leave this pin open. figure9 ? ? ? ? 1. bias current control function (bcont) pd16770b b cont lpc hpc r ext h/l h/l refer to the table below for the percentage of current regulation when using the bias current control function. table9 ? ? ? ? 1. current consumption regulation percentage compared to normal mode current consumption regulation percentage r ext lpc = l, hpc = h/open lpc = h/open, hpc = h/open (open) 100% 65% 50 k ? 110% 70% 20 k ? 115% 80% 10 k ? 120% 85% remark the above current consumption regulation percentages are founded on results of simulation and don?t assuring a characteristics of this product. caution because the power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver ic, when this occurs, the characteristics of the output amplifier will simultaneously change. therefore, when using these functions, be sure to sufficiently evaluate the picture quality. v dd1 = 3.3 v v dd2 = 8.7 v
data sheet s14773ej1v0ds 13 pd16770b 10. electrical specifications absolute maximum ratings (t a = 25c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +4.0 v driver part supply voltage v dd2 ?0.5 to +10.0 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v driver part input voltage v i2 ?0.5 to v dd2 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v operating ambient temperature t a ?10 to +75 c storage temperature t stg ?55 to +125 c caution product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter/ that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?10 to +75c, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic part supply voltage v dd1 2.3 3.6 v driver part supply voltage v dd2 8.0 8.5 9.0 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 00.3 v dd1 v -corrected voltage v 0 to v 9 v ss2 + 0.1 v dd2 ? 0.1 v driver part output voltage v o v ss2 + 0.1 v dd2 ? 0.1 v maximum clock frequency f clk v dd1 = 2.3 v 45 mhz
data sheet s14773ej1v0ds 14 pd16770b electrical characteristics (t a = ?10 to +75c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v, unless otherwise specified, power mode: normal, bcont = open) parameter symbol conditions min. typ. max. unit input leak current i il 1.0 a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v v 0 pin, v 5 pin 126 252 504 a -corrected supply current i v dd2 = 8.5 v v 0 to v 4 = v 5 to v 9 = 4.0 v v 4 pin, v 9 pin ? 504 ? 252 ? 126 a i voh v x = 7.0 v, v out = 6.5 v note ? 30 a driver output current i vol v x = 1.0 v, v out = 1.5 v note 30 a output voltage deviation ? v o 7 20 mv output swing difference deviation ? v p?p t a = 25c v dd1 = 3.3 v, v dd2 = 8.5 v, v out = 2.0 v, 4.25 v, 6.5 v 2 15 mv logic part dynamic current consumption i dd1 v dd1 1.0 6.5 ma driver part dynamic current consumption i dd2 v dd2 , with no load 3.0 6.5 ma note v x refers to the output voltage of analog output pins s 1 to s 420 . v out refers to the voltage applied to analog output pins s 1 to s 420 . cautions 1. f stb = 64 khz, f clk = 40 mhz. 2. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 3. refers to the current consumption per driver when cascades are connected under the assumption of sxga+ single-sided mounting (10 units). switching characteristics (t a = ?10 to +75c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v, unless otherwise specified, power mode: normal, bcont = open) parameter symbol conditions min. typ. max. unit t plh1 10 20 ns start pulse delay time t phl1 c l = 10 pf 10 20 ns t plh2 2.5 5 s t plh3 58 s t phl2 2.5 5 s driver output delay time t phl3 c l = 75 pf, r l = 5 k ? 58 s c i1 sthr (sthl) excluded, t a = 25c 10 pf input capacitance c i2 sthr (sthl),t a = 25c 10 pf
data sheet s14773ej1v0ds 15 pd16770b timing requirement (t a = ?10 to +75c, v dd1 = 2.3 to 3.6 v, v ss1 = 0 v, t r = t f = 5.0 ns) parameter symbol conditions min. typ. max. unit clock pulse width pw clk 22 ns clock pulse high period pw clk(h) 4ns clock pulse low period pw clk(l) 4ns data setup time t setup1 4ns data hold time t hold1 0ns start pulse setup time t setup2 4ns start pulse hold time t hold2 0ns pol21, pol22 setup time t setup3 4ns pol21, pol22 hold time t hold3 0ns start pulse low period t spl 1clk stb pulse width pw stb 2clk last data timing t ldt 2clk clk-stb time t clk-stb clk stb 6ns stb-clk time t stb-clk stb clk 9ns time between stb and start pulse t stb-sth stb sthr(sthl) 2clk pol-stb time t pol-stb pol or stb ?5 ns stb-pol time t stb-pol stb pol or 6ns remark unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 .
data sheet s14773ej1v0ds 16 pd16770b switching characteristics waveform (r,/l = h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol (v out ) stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3707172 701 702 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t phl1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage +0.1 v dd2 6-bit accuracy t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 409 to d 414 d 415 to d 420 d 421 to d 426 d 4195 to d 4200 invalid invalid v dd1 v ss1 t spl t setup3 t hold3 pol21, pol22 (1st dr.) (1st dr.) invalid s n
data sheet s14773ej1v0ds 17 pd16770b 11. recommended soldering conditions the following conditions must be met for soldering conditions of the pd16770b. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. pd16770bn- : tcp (tab package) mounting condition mounting method condition soldering heating tool 300 to 350c: heating for 2 to 3 seconds: pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c: pressure 3 to 8 kg/cm 2 : time 3 to 5 seconds. real bonding 165 to 180c: pressure 25 to 45 kg/cm 2 : time 30 to 40 seconds. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time.
data sheet s14773ej1v0ds 18 pd16770b [memo]
data sheet s14773ej1v0ds 19 pd16770b notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16770b reference documents nec semiconductor device reliability/quality control system (c10983e) semiconductor device mounting technology (c10535e) m8e 00. 4 the information in this document is current as of may, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the po ssibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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