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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998 mos integrated circuit m m m m pd16780 288/300 output tft-lcd source driver data sheet document no. s12608ej1v0ds00 (1st edition) date published may 1999 ns cp(k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd16780 is a source driver for tft-lcds. the m pd16780 corresponds only to lcd of stripe array color filter. the m pd16780 is constitute a shift register which generates the sampling time, and a sample-and-hold circuit which samples the analog voltage. there are two sample-and-hold circuits which perform sampling holding alternately. the application with high free degree is possible from driver operation system to lcd-tv because a high picture quality is realized. features ? 5.0 v drive (dynamic range 4.6 v p-p , v dd2 = 5.0 v) ? 288/300 output channel ? f max. = 20 mhz (v dd1 = 3.0 v) ? corresponds only to lcd of stripe array color filter ? two on-chip sample-and-hold circuits ? small output deviation between pins (deviation between chip pins: 20 mv max.) ? switch between right and left shift using the r,/l pin ordering information part number package m pd16780n-xxx tcp (tab package) remark the tcps external shape is custom-order item. users are requested to consult wiht a nec sales representative.
data sheet s12608ej1v0ds00 2 m m m m pd16780 1. block diagram s 1 s 2 s 299 s 300 c 1 c 2 c 99 c 100 100-bit shift register level shifter sample and hold sthr sthl v dd1 (3.3/5.0 v) v ss1 v dd2 (5.0 v) v ss2 v ss3 r,/l clk o sel c 1 c 2 c 3 cx remark /xxx indicates active low signal. 2. sample-and hold circuit and output circuit C + C + sw sw s n c h1 v ss3 c h1 v ss3 sw s&h 1 sw s&h 2 video line (c n ) shpn cx
data sheet s12608ej1v0ds00 3 m m m m pd16780 3. pin configuration ( m m m m pd16780n-xxx) s 300 s 299 s 298 sthl c 1 c 2 c 3 v dd2 v dd1 copper foil clk surface r,/l cx test v ss1 o sel v ss3 v ss2 sthr s 3 s 2 s 1 remark this figure does not specify the tcp package.
data sheet s12608ej1v0ds00 4 m m m m pd16780 4. pin functions pin symbol pin name description c 1 ,c 2 ,c 3 video signal input these pins are input video signals r,g, and b. s 1 -s 300 video signal input these pins are output video signals, which have been sampled and hold. c 1 : s 3n-2 (n = 1, 2, 96/100) c 2 : s 3n-1 c 3 : s 3n sthr, sthl cascade i/o these pins are inputs/outputs for the start pulse for sample and hold timing. high level of sthr/sthl is read at rising edge of clk and start sampling video signal. sthr serves as the input pin and sthl serves as output pin for the right shift. for left shift, sthl serves as the input pins and sthr serves as the output pin. r,/l shift direction switching input the shift directions of the shift registers are as follows. r,/l = h: sthr input, s 1 ? s 300 , sthl output. r,/l = l: sthl input, s 300 ? s 1 , sthr output. o sel selection of number of outputs switching input selects number of outputs. o sel = l: 288 output mode o sel = h: 300 output mode output pins s 145 through s 156 are invalid in 288 output mode. the signal which is with s 157 to s 168 (r,/l = h) or s 133 to s 144 (r,/l = l) is output identically. clk shift clock input the start pulse is read at rising edge of clk. the sampling pulse shpn is generated at rising edge of clk. m pd16780 corresponds only to lcd of stripe array color filter and only simultaneous sampling. for details, refer to 6. timing chart . cx hold capacitance control input two sample & hold circuits are switched. cx = h s&h1: sampling, s&h2: output cx = l s&h1: output, s&h2: sampling test test pin fix this pin to the l level. v dd1 logic power supply 3.3 v 0.3 v, or 5.0 v 0.5 v v dd2 driver power supply 5.0 v 0.5 v v ss1 logic ground grounding v ss2 driver ground grounding v ss3 sample & hold ground it is ground of sample & hold capacitance. supply this terminal with the stable gnd. ?
data sheet s12608ej1v0ds00 5 m m m m pd16780 cautions 1. to prevent latch-up-breakdown, the power should be turned on in order v dd1 , logic input v dd2 , video signal input. it should be turned off in the opposite order. this relationship should be followed during transition periods as well. 2. the sampling of the video signal of this ic is only the simultaneous 3 output sampling of c 1 , c 2 , c 3 . incidentally, it is designing abound of the input of the video signal in 10 mhz max. if a video signal with a higher frequency is input, the data may not be correctly displayed. 3. insert a capacitor of 0.1 m m m m f between v dd1 and v ss1 , and v dd2 and v ss2 . unless the power supply is reinforced, the supply voltage may fluctuate, making the sampling voltage abnormal. 4. if noise is superimposed on the start pulse pin, the data may not be displayed. for this reason, be sure to input cx signal during the vertical blanking period. 5. if the start pulse width is extended by half the clock or longer, the sampling start timing shp1 does not change from normal timing; therefore, the sampling operation is performed normally.
data sheet s12608ej1v0ds00 6 m m m m pd16780 5. function description 5.1 switching of sample & hold circuits two sample-and-hold circuits are switched. cx output sample & hold operation l sample & hold circuit 1 (s&h1) sample & hold circuit 2 (s&h2) h sample & hold circuit 2 (s&h2) sample & hold circuit 1 (s&h1) 5.2 sample & hold and output relation between video signals c 1 , c 2 and c 3 and output pins and two sample & hold circuits. 5.2.1 300 output cx s 1 (s 300 )s 2 (s 299 )s 3 (s 298 )s 4 (s 297 ) s 299 (s 2 )s 300 (s 1 ) l sampling c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 )c 1-2 (c 3-2 ) c 2-2 (c 2-2 )c 3-2 (c 1-2 ) output c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 )c 1-1 (c 3-1 ) c 2-1 (c 2-1 )c 3-1 (c 1-1 ) h sampling c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 )c 1-1 (c 3-1 ) c 2-1 (c 2-1 )c 3-1 (c 1-1 ) output c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 )c 1-2 (c 3-2 ) c 2-2 (c 2-2 )c 3-2 (c 1-2 ) remark c m-n = m: video input, n: sample & hold 5.2.2 288 output cx s 1 (s 288 )s 2 (s 287 )s 3 (s 286 )s 4 (s 285 ) s 287 (s 2 )s 288 (s 1 ) l sampling c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 )c 1-2 (c 3-2 ) c 2-2 (c 2-2 )c 3-2 (c 1-2 ) output c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 )c 1-1 (c 3-1 ) c 2-1 (c 2-1 )c 3-1 (c 1-1 ) h sampling c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 )c 1-1 (c 3-1 ) c 2-1 (c 2-1 )c 3-1 (c 1-1 ) output c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 )c 1-2 (c 3-2 ) c 2-2 (c 2-2 )c 3-2 (c 1-2 ) remark c m-n = m: video input, n: sample & hold
data sheet s12608ej1v0ds00 7 m m m m pd16780 6. timing chart (right shift, 300 output) clk sthr (sthl) sthr (sthl) shp 1 -shp 3 (shp 300 -shp 298 ) s 1 -s 3 (s 300 -s 298 ) s 1 -s 3 (s 300 -s 298 ) s 4 -s 6 (s 297 -s 295 ) s 295 -s 297 (s 6 -s 4 ) s 298 -s 300 (s 3 -s 1 ) s 4 -s 6 (s 297 -s 295 ) s 7 -s 9 (s 294 -s 292 ) shp 4 -shp 6 (shp 297 -shp 295 ) shp 1 -shp 3 (shp 300 -shp 298 ) shp 4 -shp 6 (shp 297 -shp 295 ) shp 295 -shp 297 (shp 6 -shp 4 ) shp 298 -shp 300 (shp 3 -shp 1 ) shp 7 -shp 9 (shp 294 -shp 292 ) 1 2 3 (1) (2) (3) 99 100
data sheet s12608ej1v0ds00 8 m m m m pd16780 7. electrical specifications absolute maximum ratings (t a = +25 c, v ss1 =v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 - 0.3 to +7.0 v driver part supply voltage v dd2 - 0.3 to +7.0 v input voltage v i - 0.3 to v dd1/2 + 0.3 v output voltage v o - 0.3 to v dd1/2 + 0.3 v operating ambient temperature t a - 30 to +85 c storage temperature t stg - 55 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = - - - - 30 to +85 c, v dd2 3 3 3 3 v dd1 , v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic part supply voltage v dd1 3.0 5.5 v driver part supply voltage v dd2 4.5 5.0 5.5 v video input voltage v vi v ss2 + 0.2 v dd2 - 0.2 v driver part output voltage v o2 v ss2 + 0.2 v dd2 - 0.2 v maximum clock frequency f max. clk 20 mhz output load capacitance c l 1 output 50 pf ?
data sheet s12608ej1v0ds00 9 m m m m pd16780 electrical characteristics (t a = C30 to +85 c, v dd1 = 3.0 v to 5.5 v, v dd2 = 5.0 v 0.5 v, v dd2 3 3 3 3 v dd1 , v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit low-level driver part output voltage v vol s 1 to s 300 v ss2 + 0.2 v high-level driver part output voltage v voh v dd2 C 0.2 v high-level input voltage v ih clk, sthr (l), r,/l, o sel , cx 0.7 v dd1 v dd1 v low-level input voltage v il v ss1 0.3 v dd1 v input leak current i il all inputs C1.0 +1.0 m a high-level output voltage v loh sthr (sthl), i oh = C1.0 ma 0.85 v dd1 v low-level output voltage v loh sthr (sthl), i ol = +1.0 ma 0.15 v dd1 v reference voltage v ref1 v dd2 = 5.0 v, v vi = 0.5 v, t a = 25c 0.5 v v ref2 v dd2 = 5.0 v, v vi = 2.5 v, t a = 25c 2.5 v v ref3 v dd2 = 5.0 v, v vi = 4.5 v, t a = 25c 4.5 v output voltage deviation d v vo1 v dd2 = 5.0 v, v vi = 0.5 v, t a = 25c 20 mv d v vo2 v dd2 = 5.0 v, v vi = 2.5 v, t a = 25c 20 mv d v vo3 v dd2 = 5.0 v, v vi = 4.5 v, t a = 25c 20 mv logic dynamic current consumption i dd1 v dd1 = 5.0 v with no load note 1.0 3.5 ma driver dynamic current consumption i dd2 v dd2 = 5.0 v with no load note 5.6 8.5 ma note f clk = 15 mhz, f cx = 17 khz. ?
data sheet s12608ej1v0ds00 10 m m m m pd16780 switching characteristics (t a = C 30 to +85 c, v dd1 = 3.0 v to 5.5 v, v dd2 = 5.0 v 0.5 v, v dd2 3 3 3 3 v dd1 , v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t phl1 c l = 20 pf 7 43 ns t plh1 clk ? sthl(sthr) 7 43 ns driver output delay time t plh2 v dd2 = 5.0 v 8 m s t plh3 r l = 2 k w 16 m s t phl2 c l = 25 pf x 2 8 m s t phl3 16 m s input capacitance c i1 sthr(sthl), t a =25 c1020pf c i2 c 1 ,c 2 ,c 3 , t a =25 c4060pf c i3 sthr(sthl),c 1 ,c 2 ,c 3 excluded input, t a =25 c 715pf timing requirement (t a = C 30 to +85 c, v dd1 = 3.0 v to 5.5 v, v dd2 = 5.0 v 0.5 v, v dd2 3 3 3 3 v dd1 , v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit clock pulse width pw clk 50 ns clock pulse high period pw clk(h) 15 ns clock pulse low period pw clk(l) 15 ns start pulse setup time t setup 7ns start pulse setup time t hold 7ns start pulse C cx time t sth-cx 50 ns cx setup time t cxsetup 1.0 m s cx hold time t cxhold 50 ns clk stop period note t clkstop refer to 8. swithing characteristics waveform. note this shows the period where it is possible for clk stop. ? ? ?
data sheet s12608ej1v0ds00 11 m m m m pd16780 8. switching characteristics waveform (r,/l=h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . ? y ? t v dd1 2 1 0 401 400 399 102 101 100 3 2 1 0 t clkstop : it is possible for the clock among this to stop. v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 t plh3 t cxsetup invalid invalid t phl1 t plh1 t hold t setup pw clk pw clk(l) pw clk(h) t plh1 t phl1 s 1 to s 3 s 301 to s 303 s 298 to s 300 s 295 to s 297 s 7 to s 9 s 4 to s 6 s 1 to s 3 s 1198 to s 1200 s 1195 to s 1197 t cxhold t plh2 t phl2 target voltage 0.1 v dd1 target voltage 20 mv t phl3 clk sthr (1st dr.) c 1 to c 3 sthl (1st dr.) sthl (4th dr.) cx v out t sth-cx ?
data sheet s12608ej1v0ds00 12 m m m m pd16780 9. recommended mounting conditions the following conditions must be met for mounting conditions of the m pd16780. for more details, refer to the semiconductor device mounting technology manual(c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. m pd16780n-xxx : tcp(tab package) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 sec ; pressure 100g(per solder) acf (adhesive conductive film) temporary bonding 70 to 100 c ; pressure 3 to 8 kg/cm2; time 3 to 5 sec. real bonding 165 to 180 c pressure 25 to 45 kg/cm2 time 30 to 40secs(when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s12608ej1v0ds00 13 m m m m pd16780 [memo]
data sheet s12608ej1v0ds00 14 m m m m pd16780 [memo]
data sheet s12608ej1v0ds00 15 m m m m pd16780 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16780 reference documents nec semiconductor device reliability/quality control system(c10983e) quality grades to necs semiconductor devices(c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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