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hy57v561620t 4banks x 4m x 16bit synchronous dram this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. revision 0.1/ apr.01 description the hynix hy57v561620 is a 268,435,456bit cmos synchronous dram, ideally suited for the mobile applications which require low power consumption and extended temperature range. hy57v561620 is organized as 4 banks of 4,194,304x16. hy57v561620 is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline ( cas latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? single 3.3v 0.3v power supply ? all device pins are compatible with lvttl interface ? jedec standard 400mil 54pin tsop-ii with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by udqm and ldqm ? internal four banks operation ? auto refresh and self refresh ? 8192 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 and full page for sequential burst - 1, 2, 4 and 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency power organization interface package HY57V561620T-HI 133mhz normal power 4banks x 4mbits x16 lvttl 400mil 54pin tsop ii hy57v561620t-si 100mhz hy57v561620lt-hi 133mhz low power hy57v561620lt-si 100mhz
hy57v561620t revision 0.1 / apr.01 2 pin configuration v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss nc udqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm / we / cas / ras / cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd 54 pin tsop ii 400 mil x 875mil 0.8 mm pin pitch pin description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke, udqm and ldqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a12 address row address : ra0 ~ ra12, column address : ca0 ~ ca8 auto-precharge flag : a10 ras , cas , we row address strobe, col- umn address strobe, write enable ras , cas and we define the operation refer function truth table for details udqm, ldqm data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq15 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection
hy57v561620t revision 0.1 / apr.01 3 functional block diagram 4mbit x 4banks x16 i/o synchronous dram x decoders state machine a0 a1 a12 ba0 ba1 address buffers address register mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq14 dq15 self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we udqm ldqm 4 mx16 bank 3 x decoders memory cell array y decoders x decoders 4 mx16 bank 0 4 mx16 bank 1 4 mx16 bank 2
hy57v561620t revision 0.1 / apr.01 4 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating condition (ta= -40 to 85 c ) note : 1. all voltages are referenced to v ss = 0v 2. v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration 3. v il (max) is acceptable -2.0v ac pulse width with 3ns of duration ac operating condition (ta= -40 to 85 c , v dd =3.3 0.3v, v ss =0v) note : 1. output load to measure access time is equivalent to two ttl gates and one capacitor (50pf) for details, refer to ac/dc output circuit parameter symbol rating unit ambient temperature t a -40 ~ 85 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 c sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 2.0 v 1,2 input low voltage v il vssq-2.0 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 50 pf 1
hy57v561620t revision 0.1 / apr.01 5 output vtt =1.4v rt=250 w 50 pf 50 pf output dc output load circuit ac output load circuit capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta= -40 to 85 c , v dd =3.3 0.3v) note : 1. v in = 0 to 3.6v, all other pins are not under test = 0v 2. d out is disabled, v out =0 to 3.6v parameter pin symbol -hi -si unit min max min max input capacitance clk c i1 2.5 3.5 2.5 4.0 pf a0 ~ a12, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm ci 2 2.5 3.8 2.5 5.0 pf data input / output capacitance dq0 ~ dq15 c i/o 4.0 6.5 4.0 6.5 pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol - 0.4 v i ol =+4ma
hy57v561620t revision 0.1 / apr.01 6 dc characteristics ii (ta= -40 c to 85 c , v dd =3.3v 0.3v, v ss =0v) note : 1. i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open. 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3. HY57V561620T-HI/si 4.hy57v561620lt-hi/si parameter symbol test condition speed unit note -hi -si operating current i dd1 burst length=1, one bank active tras 3 tras(min),trp 3 trp(min), io=0ma 120 100 ma 1 precharge standby current in power down mode i dd2p cke vil(max), tck = min. 2 ma i dd2ps cke vil(max), tck = 2 precharge standby current in non power down mode i dd2n cke 3 vih(min), cs 3 vih(min), tck = min input signals are changed one time during 2clks. all other pins 3 vdd-0.2v or 0.2v 20 ma i dd2ns cke 3 vih(min), tck = input signals are stable. 10 active standby current in power down mode i dd3p cke vil(max), tck = min 3 ma i dd3ps cke vil(max), tck = 3 active standby current in non power down mode i dd3n cke 3 vih(min), cs 3 vih(min), tck = min input signals are changed one time during 2clks. all other pins 3 vdd-0.2v or 0.2v 25 ma i dd3ns cke 3 vih(min), tck = input signals are stable 15 burst mode operating current idd4 tck 3 tck(min), tras 3 tras(min), io=0ma all banks active 150 120 ma 1 auto refresh current i dd5 trrc 3 trrc(min), all banks active 260 250 ma 2 self refresh current i dd6 cke 0.2v 4 ma 3 2 ma 4
hy57v561620t revision 0.1 / apr.01 7 ac characteristics i note : 1. assume tr / tf (input rise and fall time ) is 1ns. 2. access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v parameter symbol -hi -si unit note min max min max system clock cycle time cas latency = 3 tck3 7.5 1000 10 1000 ns cas latency = 2 tck2 12 12 ns clock high pulse width tchw 2.5 - 3 - ns 1 clock low pulse width tclw 2.5 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 5.4 6 ns 2 cas latency = 2 tac2 - 6 6 ns data-out hold time toh 2.5 - 2.5 - ns data-input setup time tds 1.5 - 2 - ns 1 data-input hold time tdh 0.8 - 1 - ns 1 address setup time tas 1.5 - 2 - ns 1 address hold time tah 0.8 - 1 - ns 1 cke setup time tcks 1.5 - 2 - ns 1 cke hold time tckh 0.8 - 1 - ns 1 command setup time tcs 1.5 - 2 - ns 1 command hold time tch 0.8 - 1 - ns 1 clk to data output in low z-time tolz 1 - 1 - ns clk to data output in high z-time cas latency = 3 tohz3 2.7 5.4 3 6 ns cas latency = 2 tohz2 3 6 3 6 ns
hy57v561620t revision 0.1 / apr.01 8 ac characteristics ii note : 1. a new command can be given trrc after self refresh exit. parameter symbol -hi -si unit note min max min max ras cycle time operation trc 65 - 70 - ns auto refresh trrc 65 - 70 - ns ras to cas delay trcd 20 - 20 - ns ras active time tras 45 100k 50 100k ns ras precharge time trp 20 - 20 - ns ras to ras bank active delay trrd 15 - 20 - ns cas to cas delay tccd 1 - 1 - clk write command to data-in delay twtl 0 - 0 - clk data-in to precharge command tdpl 2 - 2 - clk data-in to active command tdal 5 - 4 - clk dqm to data-out hi-z tdqz 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - clk mrs to new command tmrd 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - 3 - clk cas latency = 2 tproz2 - - 2 - clk power down exit time tpde 1 - 1 - clk self refresh exit time tsre 1 - 1 - clk 1 refresh time tref - 64 - 64 ms
hy57v561620t revision 0.1 / apr.01 9 device operating option table hy57v561620(l)t-hi hy57v561620(l)t-si cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.5ns 100mhz(10ns) 3clks 3clks 6clks 9clks 3clks 6ns 2.5ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 2.5ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns
hy57v561620t revision 0.1 / apr.01 10 command truth table note : 1. op code : operand code 2. v = valid, x = don?t care, h = logic high, l= logic low, ra = row address, ca = column address. command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code 1 no operation h x h x x x x x l h h h bank active h x l l h h x ra v read h x l h l h x ca l v read with autoprecharge h write h x l h l l x ca l v write with autoprecharge h precharge all banks h x l l h l x x h x precharge selected bank l v burst stop h x l h h l x x udqm, ldqm h x v x auto refresh h h l l l h x x self refresh entry h l l l l h x x exit l h h x x x x l h h h precharge power down entry h l h x x x x x l h h h exit l h h x x x x l h h h clock suspend entry h l h x x x x x l v v v exit l h x x
hy57v561620t revision 0.1 / apr.01 11 package information 400mil 54pin thin small outline package unit : mm(inch)

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