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4-bit single-chip microcomputer m pd75516 mos integrated circuit data sheet ? nec corporation 1989 document no. ic-2471d (o. d. no. ic-7580d) date published november 1993 p printed in japan the mark h shows major revised points. the information in this document is subject to change without notice. description the m pd75516 is a product in the 75x series(of 4-bit single-chip microcomputers). the 75x series has an architecture which is comparable to that of 8-bit microcomputers. the m pd75516 possesses high class processing capacities as a 4-bit single-chip microcomputer with built-in a/d converter and serial interface, including the capability to process data in lengths of 1, 4 and 8 bits in addition to its high speed operation. details of functions are described in the user's manual shown below. be sure to read in design. m pd75516 user's manual: iemC5049 features l a large number of i/o lines: 64 lines (internal pull-up/pull- down resistor specifiable: 47) l built-in 8-bit serial interface: 2 channels built-in nec standard serial bus interface (sbi) l built-in 8-bit ad converter: 8 channels l high speed operation and a instruction execution time variation function which is effective for saving power. ? 0.95 m s/1.91 m s/15.3 m s (at 4.19 mhz operation), 122 m s (at 32.768 khz operation) l program memory (rom) capacity: 16256 8 bits l data memory (ram) capacity: 512 4 bits l powerful timer function: 4 channels ? 8-bit timer/event counter ? watch timer ? 8-bit basic interval timer ? timer/pulse generator: 14-bit pwm with variable output l ultra low power consumption clock operation is possible (5 m a typ.: during operation at 3 v) l devices with built-in prom are available ( m pd75p516) uses vcrs and cd players, telephones, cameras, etc.
2 m pd75516 ordering information ordering code package quality grade m pd75516gf- -3b9 80-pin plastic qfp (14 20 mm) standard remarks " " means the specified rom code. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. item on-chip memory general registers instruction cycle a/d converter timer/counters serial interface vectored interrupt test input instruction set system clock oscillator operating voltage package list of m pd75516 functions function (4 bits 8 or 8 bits 4) 4 banks ? 0.95 m s/1.91 m s/15.3 m s (main system clock: 4.19 mhz operation) ? 122 m s (subsystem clock: 32.768 khz operation) 8-bit resolution 8 channels (successive approximation type) ? operating voltage: v dd = 3.5 to 6.0 v ?timer/event counter ? basic interval timer ? timer/pulse generator (14-bit pwm output capability) ? watch timer ? nec standard serial bus interface (sbi)/3-wire sio: 1 channel ? normal clocked serial interface (3-wire sio): 1 channel external: 3, internal: 4 external: 1, internal: 1 ? bit data set/reset/test/boolean operations ? 4-bit data transfer, operation, increment/ decrement, compare ? 8-bit data transfer, operation, increment/ decrement, compare ? ceramic/crystal oscillator for main system clock oscillation: 4.19 mhz ? crystal oscillator for subsystem clock oscillation: 32.768 khz v dd = 2.7 to 6.0 v 80-pin plastic qfp (14 20 mm) rom 16256 8 bits ram 512 4bits n-ch open-drain input/output input/ output ports total 64 cmos input 16 (dual function and analog input as int, sio, ppo, software pull-up capability: 7) cmos input/output 28 (led drive: 4) ? software pull-up capability : 16 ? mask option pull-down capability: 4 2 channels 4 channels 20 (led drive: 8; 10 v withstand voltage, mask option pull-up capability: 20)
3 m pd75516 contents 1. pin configuration ................................................................................................................................ 4 2. example of system configuration ..............................................................................................5 3. internal block diagram .................................................................................................................... 6 4. pin functions ......................................................................................................................................... 7 4.1 port pins ........................................................................................................................................................... 7 4.2 non-port pins .................................................................................................................................................. 9 4.3 pin input/output circuit list ................................................................................................................. 10 4.4 recommended connections of unused pins .................................................................................. 13 4.5 mask option selection ............................................................................................................................. 14 5. memory configuration ................................................................................................................... 15 6. peripheral hardware functions ................................................................................................. 18 6.1 ports ................................................................................................................................................................. 18 6.2 clock generator ......................................................................................................................................... 19 6.3 clock output circuit ................................................................................................................................. 20 6.4 basic interval timer .................................................................................................................................. 21 6.5 watch timer ................................................................................................................................................... 22 6.6 timer/event counter ................................................................................................................................. 22 6.7 timer/pulse generator ............................................................................................................................ 24 6.8 serial interface ........................................................................................................................................... 25 6.9 a/d converter .............................................................................................................................................. 29 6.10 bit sequential buffer ............................................................................................................................... 30 7. interrupt functions ......................................................................................................................... 31 8. standby functions ............................................................................................................................ 33 9. reset functions .................................................................................................................................. 34 10. instruction set ................................................................................................................................... 36 11. electrical specifications ............................................................................................................... 45 12. characteristic curves ..................................................................................................................... 59 13. package information ....................................................................................................................... 65 14. recommended soldering conditions ....................................................................................... 66 appendix a. development tools ........................................................................................................ 67 appendix b. related documents ....................................................................................................... 68
4 m pd75516 1. pin configuration * be sure to supply power to both v dd pins. ic: internally connected (connect to v ss directly.) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 av0 av ref v dd v dd p113 p112 p111 p110 p103 p102 p101 p100 p93 p92 p91 p90 si1/p83 so1/p82 sck1/p81 ppo/p80 kr7/p73 kr6/p72 kr5/p71 kr4/p70 p140 p141 p142 p143 reset x2 x1 ic xt2 xt1 v ss p00/int4 p01/sck0 p02/so0/sb0 p03/si0/sb1 p10/int0 p11/int1 p12/int2 p13/ti0 p20/pto0 p21 p22/pcl p23/buz p30 an1 an2 an3 an4/p150 an5/p151 an6/p152 an7/p153 av ss p120 p121 p122 p123 p130 p131 p132 p133 kr3/p63 kr2/p62 kr1/p61 kr0/p60 p53 p52 p51 p50 v ss p43 p42 p41 p40 p33 p32 p31 * m pd75516gf- -3b9
5 m pd75516 2. example of system configuration vtr (voltage synthesizer tuner) m pd75516 int0 input port output port port4, 5 kr0?r7 system clock watch clock sio analog input ppo sio osd lpf fip driver fip remote control ic key matrix servo ic mechanism mechanism control tuner mechanism computer/ timer
6 m pd75516 3. internal block diagram port0 port1 port2 port3 port4 port5 port6 port7 port8 port9 4 4 4 4 4 4 4 4 4 p00-p03 p90-p93 p10-p13 p20-p23 p30-p33 p40-p43 * p50-p53 * p60-p63 p70-p73 p80-p83 basic interval timer intbt timer/event counter #0 watch timer intt0 intw timer pulse generator inttpg serial interface0 intcsi serial interface1 interrupt control a/d converter bit seq. buffer(16) ti0/p13 pto0/p20 buz/p23 ppo/p80 si0/sb1/p03 so0/sb0/p02 sck0/p01 si1/p83 so1/p82 sck1/p81 int0/p10 int1/p11 int2/p12 int4/p00 an0-an3 an4/p150-an7/p15 av ref av ss program counter (14) alu cy sp (8) bank general reg. ram data memory 512 4 bits decode and control rom program memory 16256 8 bits cpu clock stand by control clock generator sub main clock divider xt1 xt2 x1 x2 clock output control pcl/p22 v ss v dd reset fx/ n 2 f port10 p100-p103 port11 p120-p123 * port12 port13 p140-p143 * port14 p150-p153 port15 4 p130-p133 * p110-p113 4 4 4 4 4 4 kr0/p60- kr7/p73 8 * ports 4 , 5 and 12 to 14 are 10 v middle-high voltage n-ch open-drain input/output ports.
7 m pd75516 int4 sck0 so0/sb0 si0/sb1 int0 int1 int2 ti0 pto0 pcl buz kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 4. pin functions 4.1 port pins (1/2) p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 p31 p32 p33 p40 to p43 p50 to p53 p60 p61 p62 p63 p70 p71 p72 p73 pin name i/o after reset input/ output *2 4-bit input port (port0). internal pull-up resistor can be specified in 3-bit units by software for p01 to p03. 4-bit input port (port1). internal pull-up resistor can be specified in 4-bit units by software. noise removing function available 4-bit input/ output port (port2). internal pull-up resistor can be specified in 4-bit units by software. b f C a f C b m C c b C c e C b input input input input input input/ output programmable 4-bit input/ output port (port3). input/ output specifiable in 1-bit units. internal pull-up resistor can be specified in 4-bit units by software. input/ output input/ output n-ch open-drain 4-bit input/output port (port4). pull-up resistor can be incorporated in 1-bit units (mask option). 10 v withstand voltage with open-drain. n-ch open-drain 4-bit input/ output port (port5). pull-up resistor can be incorporated in 1-bit units (mask option). 10 v withstand voltage with open-drain. l l input e C c m m function dual- function pin *2 *2 *2 *2 *2 l l input/ output input/ output 4-bit input/output port (port7). internal pull-up resistor can be specified in 4-bit units by software. input f C c f C a programmable 4-bit input/output port (port6). input/output specifiable in 1-bit units. internal pull-up resistor can be specified in 4-bit units by software. input / output circuit type *1 8-bit i/o high level (when a pull- up resistor is incorporated) or high im- pedance high level (when a pull- up resistor is incorporated) or high im- pedance input *1. schmitt trigger inputs are circled. 2. can drive led directly.
8 m pd75516 4.1 port pins (2/2) pin name i/o function dual- function pin after reset ppo sck1 so1 si1 an4 to an7 input / output circuit type * 8-bit i/o p80 p81 p82 p83 p90 to p93 p120 to p123 p130 to p133 p140 to p143 p150 to p153 input 4-bit input port (port8). input e f e b v e e m m m y-a 4-bit input/output port (port9) pull-up resistor can be incorporated in 1-bit units (mask option). n-ch open-drain 4-bit input/ output port (port12). pull-up resistor can be incorporated in 1-bit units (mask option). 10 v withstand voltage with open-drain. input/ output input/ output input/ output 4-bit input/output port (port10). input input 4-bit input/output port (port11). high level (when a pull- up resistor is incorporated) or high im- pedance input/ output n-ch open-drain 4-bit input/ output port (port13). pull-up resistor can be incorporated in 1-bit units (mask option). 10 v withstand voltage with open-drain. n-ch open-drain 4-bit input/ output port (port14). pull-up resistor can be incorporated in 1-bit units (mask option). 10 v withstand voltage with open-drain. input/ output high level (when a pull- up resistor is incorporated) or high im- pedance high level (when a pull- up resistor is incorporated) or high im- pedance 4-bit input/output port (port15). input input * schmitt trigger inputs are circled. input/ output p100 to p103 p110 to p113 low level (when a pull down resistor is incorpo- rated) or high impedance
9 m pd75516 4.2 non-port pins dual- function pin pin name i/o after reset input / output circuit type * function ti0 pto0 pcl buz sck0 so0/sb0 si0/sb1 int4 int0 int1 int2 kr0 to kr3 kr4 to kr7 sck1 so1 si1 an0 to an3 an4 to an7 av ref av ss x1, x2 xt1 xt2 reset ppo ic v dd v ss input output output external event pulse input pin to the timer/event counter. timer/event counter output pin. b C c e C b e C b e C b f C a f C b m C c b b C c b C c f C c f C a f e b y y-a z b e clock output pin. fixed frequency output pin (for buzzer or system clock trimming). output input/ output serial clock input/output pin. input/ output serial data output pin. serial bus input/output pin. input/ output p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60 to p63 p70 to p73 p81 p82 p83 p150 to p153 serial data input pin. serial bus input/output pin. edge-detected vectored interrupt input pin (valid for detection of rising and falling edges). input clocked asynchronous asynchronous input input input serial falling edge detection testable input pin. input serial falling edge detection testable input pin. input/ output serial clock input/output pin. output serial data output pin. input serial data input pin. input a/d converter analog input pin. input a/d converter reference voltage input pin. a/d converter reference gnd potential pin. main system clock oscillation crystal/ceramic connection pin. an external clock is input to x1 and an antiphase clock is input to x2. input input subsystem clock oscillation crystal connection pin. an external clock is input to xt1 and xt2 is leave open. input input input input input input input input input input input input output p80 system reset input pin. timer/pulse generator pulse output pin. input edge-detected vectored interrupt input pin (detected edge selection possible). edge-detected testable input pin (rising edge detection). * schmitt trigger inputs are circled. gnd potential pin. positive power supply pin. internally connected. connect to v ss directly.
10 m pd75516 4.3 pin input/output circuit list use of simplified forms of the input/output circuit for each pin of the m pd75516 are shown as follows. fig. 4C1 pin input/output circuit list (1/3) v dd in p-ch n-ch type a v dd p-ch n-ch output disable data out in output disable data type a in/out output disable data type a in/out v dd p-ch type d type d v dd in type d type b type e type b-c type b p.u.r. p.u.r. : pull-up resistor p.u.r. : pull-up resistor p-ch p.u.r. p.u.r. enable p.u.r. enable cmos specified input buffer schmitt trigger input having hysteresis characteristics schmitt trigger input having hysteresis characteristics push-pull output which can be set to output high impedance (with both p-ch and n-ch set to off) input/output circuit consisting of type d push-pull output and type a input buffer
11 m pd75516 fig. 4C1 pin input/output circuit list (2/3) type e-c v dd p-ch n-ch output disable data output disable data type b in/out output disable data type b in/out v dd p-ch type d type d type f-b type f type f-c type f-a type m p.u.r. p.u.r. : pull-up resistor output disable data type b in/out p-ch type d p.u.r. p.u.r. : pull-up resistor v dd output disable data type a in/out p-ch type d p.u.r. p.u.r. : pull-up resistor v dd p.u.r. enable p.u.r. enable p.u.r. enable p-ch p.u.r. v dd type b in/out p-ch p.u.r. v dd output disable (n-ch) output disable (p-ch) p.u.r. : pull-up resistor v dd in/out output disable data p.u.r. (mask option) p.u.r. : pull-up resistor input/output circuit consisting of type d push-pull output and type b schmitt trigger input n-ch (+10 v withstand voltage) middle-high voltage input buffer (+10 v withstand voltage)
12 m pd75516 fig. 4C1 pin input/output circuit list (3/3) type m-c output disable data type a in/out type d type y-a type v type z type y output disable data in/out p-ch p.u.r. p.u.r. : pull-up resistor v dd p.u.r. enable p.d.r. (mask option) n-ch v dd v dd p-ch n-ch in av ss av ss input enable v dd v dd p-ch n-ch in av ss av ss input enable sampl- ing c reference voltage (from the series resistance string voltage tap) sampl- ing c reference voltage (from the series resistance string voltage tap) reference voltage av ss av ref in instruction p.d.r.: pull-down resistor + - + -
13 m pd75516 4.4 recommended connections of unused pins p00/int4 p01/sck0 p02/so0/sb0 p03/si1/sb1 p10/int0 to p12/int2 p13/ti0 p20/pto0 p21 p22/pcl p23/buz p30 to p33 p40 to p43 p50 to p53 p60/kr0 to p63/kr3 p70/kr4 to p73/kr7 p80/ppo p81/sck1 p82/so1 p83/si1 p90 to p93 p100 to p103 p110 to p113 p120 to p123 p130 to p133 p140 to p143 p150/an4 to p153/an7 an0 to an3 xt1 xt2 av ref av ss ic pin recommended connection connect to v ss connect to v ss connect to v ss or v dd connect to v ss connect to v ss or v dd input state : connect to v ss or v dd ouput state : leave open connect to v ss table 4-1 recommended connection of unused pins input state : connect to v ss or v dd ouput state : leave open leave open connect to v ss or v dd
14 m pd75516 4.5 mask option selection the following mask options are available for the pins. (1) specification of internal pull-up/pull-down resistor table 4-2 pull-up/pull-down resistor selection pins p40 to p43, p50 to p53, p120 to p123, p130 to p133, p140 to p143 p90 to p93 mask option (2) specification of internal feedback resistor for subsystem clock oscillation table 4-3 feedback resistor selection pins mask option with feedback resistor (subsystem clock used) without feedback resistor (subsystem clock not used) xt1, xt2 with pull-up resistor (specifiable bit-wise) with pull-down resistor (specifiable bit-wise) without pull-down resistor (specifiable bit-wise) without pull-up resistor (specifiable bit-wise) note when the subsystem clock is not used, operation is not affected if a feedback resistor is incorporated, but the supply current i dd is increased.
15 m pd75516 5. memory configuration program memory (rom) ...... 12160 8 bits (0000h to 2f7fh) 0000h, 0001h : vector table in which the program start addresses by reset are written. 0002h to 000dh : vector table in which the program start addresses by interrupt are written. 0020h to 007fh : table area referred by the geti instruction. data memory data area ... 512 4 bits (000h to 1ffh) peripheral hardware area ... 128 4 bits (f80h to fffh)
16 m pd75516 fig. 5C1 program memory map remarks in cases other than above, the program can branch to an address for which only the lower 8Cbit of the pc have been changed, by a br pcde or br pcxa instruction. br $addr instruction relative branch address (-15 to -1, +2 to +16) ? ? ? ? ? ? ? mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 7 6 0 address internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) int0 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi0 start address (high-order 6 bits) intcsi0 start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address call !addr instruction subroutine entry address rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe 1fffh 2000h 3f7fh ? ? ? ? br !addr instruction branch address branch destination address and subroutine entry address by geti instruction brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 2fffh 3000h inttpg start address (high-order 6 bits) inttpg start address (low-order 8 bits) mbe rbe ? 000ch
17 m pd75516 fig. 5C2 data memory map 256 4 (32 4) 0 1 15 000h 01fh 008h 0ffh 100h 1ffh f80h fffh general register area stack area data area static ram (512 4) peripheral hardware area data memory memory bank 256 4 not on-chip 128 4
18 m pd75516 6. peripheral hardware functions 6.1 ports there are the following 3 types of i/o ports. cmos input (port0, 1, 8, 15) : 16 cmos input/output (port2, 3, 6, 7, 9, 10, 11) : 28 n-ch open-drain input/output (port4, 5, 12, 13, 14) : 20 total 64 table 6C1 port functions port (pin name) function operation/features remarks can be set in the input or output mode as a 4-bit unit. shares the use of the pin with int4, sck0, so0/sb0, si0/sb1. can always be read or tested regardless of the operating mode of the dual function pin. 4-bit input port 1 shares the use of the pin with int0 to int2 and ti0. shares the use of the pin with pto0, pcl, buz can be set in the input or the output mode in 1/4-bit units port 2 port 3 * 4-bit input/output with ports 4 and 5 as a pair, data can be input and output in 8-bit units. with a mask option, the internal pull-up resistance can be speci- fied in 1-bit units. port 4 * port 5 * 4-bit input/output (n-ch open-drain 10 v withstand voltage) can be set in input or output mode in 4-bit units can be set in input or output mode in 1/4-bit units with ports 6 and 7 as a pair, data can be input and output in 8-bit units. can be set in input or output mode in 4-bit units 4-bit input/output port 7 port 6 shares the use of the pin with kr0 to kr3. shares the use of the pin with kr4 to kr7. shares the use of the pin with ppo, sck1, so1 and si1. can always be read or tested regardless of the operating mode of the dual function pin. port 8 with a mask option, the internal pull-up resistance can be speci- fied in 1-bit units. port 10 port 11 4-bit input/output 4-bit input port 12 port 13 port 14 4-bit input/output (n-ch open-drain 10 v withstand voltage) with a mask option, the internal pull-up resistance can be speci- fied in 1-bit units. can always be read or tested regardless of the operating mode of the dual function pin. shares the use of the pin with an4 to an7. 4-bit input port 15 * can drive a led directly. port 0 can be set in input or output mode in 4-bit units. port 9 4-bit input/output can be set in input or output mode in 4-bit units. can be set in input or output mode in 4-bit units.
19 m pd75516 6.2 clock generator the clock generator operation is determined by the processor clock control register (pcc) and the system clock control register (scc). 2 kinds of clocks such as a main system clock and a subsystem clock are available. in addition, the instruction execution time can be changed. 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz operation) 122 m s (subsystem clock: 32.768 khz operation) fig. 6C1 clock generator block diagram * instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) of f is 1 machine cycle of the instruction. with t cy , refer to "ac character- istics" in 11. "electrical specifications" . h xt1 xt2 x1 x2 f xt f x scc pcc halt * stop * halt f/f stop f/f 4 q s r s r 1/ 4 1/ 1/ 1/8~1/4096 2 16 scc3 scc0 pcc0 pcc1 pcc2 pcc3 q basic interval timer (bt) timer/event counter serial interface watch timer clock output circuit a/d converter frequency divider watch timer timer/pulse generator subsystem clock oscillation circuit main system clock oscillation circuit internal bus oscillation stop frequency divider f wait release signal from bt reset signal standby release signal from interrupt control circuit pcc2 and pcc3 clear selector selector int0 noise eliminator cpu clock output circuit int0 noise eliminator
20 m pd75516 6.3 clock output circuit the clock output circuit is a circuit which outputs a clock pulse from p22/pcl pin and is used to supply clock pulses to remote control outputs or peripheral lsi's. clock output (pcl) : f , 524, 262, 65.5 khz (4.19 mhz operation) buzzer output (buz) : 2 khz (4.19 mhz, or 32.768 khz operation) fig. 6C2 clock output circuit configuration clom 3 clom 1 clom 0 clom port2.2 pcl/p22 f x /2 3 f x /2 4 f x /2 6 4 clom 2 output buffer internal bus form clock generator f selector p22 output latch port 2 input/ output mode specification bit bit 2 of pmgb remarks consideration is given so that a low amplitude pulse is not output when switching between clock output enable and disable.
21 m pd75516 6.4 basic interval timer the basic interval timer includes the following functions. it operates as an interval timer which generates reference time interrupts. it can be applied as a watchdog timer which detects when a program is out of control. selects and counts wait times when the standby mode is released. it reads count contents. fig. 6C3 basic interval timer configuration * instruction execution. internal bus f x /2 5 f x /2 7 f x /2 12 from clock generator 4 btm3 btm2 btm1 btm0 btm mpx bt irqbt set bt interrupt request flag clear clear basic interval timer (8-bit frequency divider) wait release signal during standby release 8 3 vectored interrupt request signal f x /2 9 set1 *
22 m pd75516 6.5 watch timer the m pd75516 incorporates one channel of watch timer which has the following functions. sets test flags (irqw) at 0.5-second intervals. the standby mode can be released with irqw. 0.5-second time intervals can be created in either the main system clock or the subsystem clock. in the rapid feed mode, time intervals which are 128 times normal (3.91 ms) can be set, making this function convenient for program debugging and testing. a fixed frequency (2.048 khz) can be output to the p23/buz pin for use in generating buzzer sounds and trimming system clock oscillator frequencies. the frequency divider can be cleared, so this watch can be started at 0 second. fig. 6C4 watch timer block diagram 8 internal bus wm7 0 0 0 wm2 wm1 wm0 bit test instruction p23 output latch port 2 input/output mode port2.3 bit 2 of pmgb p23/buz output buffer selector frequency divider clear (2.048 khz) 2 14 f w 2 7 f w (256 hz : 3.91 ms) f w (32.768 khz) selector wm from clock generator 16 f w 128 f w (32.768 khz) f xt (32.768 khz) intw irqw set signal 2hz 0.5 sec 0 remarks values in parentheses are when fx = 4.194304 mhz and fxt = 32.768 khz. 6.6 timer/evnet counter the m pd75516 incorporates one channel of timer/event counter which has the following functions. operates as a programmable interval timer. outputs square waves in the desired frequency to the pto0 pin. operates as an event counter. divides the ti0 pin input into n divisions and outputs it to the pto0 pin (frequency divider operation). supplies a serial shift clock to the serial interface circuit. count status read function.
23 m pd75516 p13/ti0 port1.3 input buffer from clock generator mpx tm06 tm05 tm04 tm03 tm02 set1 tm0 timer operation start cp count register (8) clear 8 comparator (8) 8 8 modulo register (8) 8 8 internal bus tmod0 match reset tout f/f toe0 to enable flag p20 output latch port2.0 bit 2 of pgmb port 2 input/ output mode to serial interface p20/pto0 output buffer intt0 irqt0 set signal reset irqt0 clear signal t0 tm07 tm01 tm00 * * instruction execution fig. 6C5 timer/event counter block diagram
24 m pd75516 6.7 timer/pulse generator the m pd75516 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. the timer/pulse generator has the following functions. (a) functions available in the timer mode ? 8-bit interval timer operation (irqtpg generation) enabling the clock source to be varied at 5 levels ? square wave output to ppo pin (b) functions available in the pwm pulse generate mode ? 14-bit accuracy pwm pulse output to the ppo pin (used as a digital-to analog converter and applicable to tuning) ? interrupt generation of fixed time interval if pulse output is not necessary, the ppo pin can be used as a 1-bit output port. note if the stop mode is set while the timer/pulse generator is in operation, miss-operation may result. to prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. fig. 6C6 block diagram of timer/pulse generator (timer mode) 8 8 modl modh tpgm3 (set to "1") 8 8 1/2 f x tpgm1 cp tpgm4 tpgm5 tpgm7 ppo inttpg irqtpg set signal internal bus modulo register l (8) modulo register h (8) modulo lach h (8) comparator (8) count register (8) clear clear prescalar select latch (5) frequency divider match set t f/f selec- tor output buffer
25 m pd75516 fig. 6C7 timer/pulse generator block diagram (pwm pulse generator mode) f x tpgm1 tpgm3 8 8 modh modl modh (8) ppo tpgm5 tpgm7 inttpg 1/2 modl 7-2 (6) internal bus modulo register h (8) modulo register l (8) frequency divider modulo latch (14) pwm pulse generator selector output buffer (irqtpg set signal) 6.8 serial interface the m pd75516 has two serial interface channels on chip. the differences between channel 0 and channel 1 are shown in table 6C2. table 6C2 differences between channels 0 and 1 channel 1 channel 0 3-wire serial i/o clock selection transfer mode transfer end flag serial transfer end flag (eot) f x /2 4 , f x /2 3 , tout f/f, external clock f x /2 4 , f x /2 3 , external clock msb first/lsb first switchable msb first serial transfer end interrupt request flag (irqcsi0) use enabled none serial transfer mode and function 2-wire serial i/o serial bus interface (sbi) (1) serial interface (channel 0) functions the following 4 modes are available to the m pd75516 serial interface (channel 0). ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode (serial bus interface mode) ( = 7.81 ms : fx = 4.19 mhz operation) 2 15 f x
26 m pd75516 fig. 6C8 serial interface (channel 0) block diagram f x /2 3 (from timer/ event counter) intcsi0 irqcsi0 set signal mpx i ntcsi0 control circuit reld serial clock counter serial clock control circuit p01/sck0 p03/si/sb1 p02/so/sb0 selector 8/4 csim0 bit test 8 8 internal bus 8 slave address register (sva) addres comparator shift register (sio0) match signal relt bit manipulation cmdt so0 latch set clr q d sbic bit test busy/ acknowledge output circuit ackt (8) (8) (8) cmdd ackd acke bsye bus release/ command/ acknowledge detection circuit selector f x /2 4 f x /2 6 tout f/f external sck0 p01 output latch ? ? ? ?
27 m pd75516 (2) serial interface (channel 1) functions the following 2 modes are available to the m pd75516 serial interface (channel 1). operation stop mode 3-wire serial i/o mode
28 m pd75516 fig. 6C9 serial interface (channel 1) block diagram 8 8 0 csim1 fx/2 3 fx/2 4 r s q p83/si1 p82/so1 p81/sck1 bit0 7 sio1 bit7 internal bus sio1 write signal (serial start signal) bit mani- pulation serial operating mode register 1 (8) bit mani- pulation serial transfer end flag (eot) mpx set clear clear serial clock counter (3) overflow shift register 1 (8)
29 m pd75516 6.9 a/d converter the m pd75516 incorporates an 8Cbit resolution a/d converter with 8Cchannel analog inputs (an0 to an7). the a/d converter employs successive approximation. fig. 6C10 a/d converter block diagram an0 an1 an2 an3 an4 an5 an6 an7 av ss av ref r/2 r r r r/2 + C 8 8 0 adm6 adm5 adm4 soc eoc adm1 0 8 internal bus control circuit sa register (8) comparator simple & hold circuit tap decoder multiplexer adm
30 m pd75516 6.10 bit sequential buffer: 16 bits the bit sequential buffer is a special data memory for bit manipulation. in particular it facilitates bit manipulation switch the address and bit specifications sequentially modified, and is thus useful for bitCwise processing of data comprising many bits. fig. 6C11 bit sequential buffer format fc3h address bit 3 fc2h fc1h fc0h 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 bsb3 bsb2 bsb1 bsb0 symbol l register l = f l = c l = b l = 8 l = 7 l = 4 l = 3 l = 0 decs l incs l remarks in pmem.@l addressing, the specified bit shifts in accordance with the l register.
31 m pd75516 7. interrupt functions the m pd75516 has nine types of interrupt sources and can generate multiple interrupts with priority order. 2 kind of test sources are also available. int2 of these test sources is an edge detection testable input. the m pd75516 interrupt control circuit has the following functions: hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (ie ) and the interrupt master enable flag (ime). function of setting any interrupt start address. multiple interrupt function which can specify priority order with the interrupt priority select register (ips). interrupt request flag (irq ) test function (interrupt generation can be checked by software). standby mode release function (interrupt to be released by interrupt enable flag can be selected).
32 m pd75516 fig. 7-1 interrupt control circuit block diagram 4 2 (ime) ips ist decoder 2 2 2 im2 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 irq4 irq0 irq1 irqcsi0 irqt0 irqtpg irq2 int bt intcsi0 intt0 inttpg vrqn internal bus vector table address generator circuit priority control circuit standby release signal interrupt enable flag (ie xxx ) edge detection circuit edge detection circuit both edges detection circuit int2 /p12 kr0/p60 kr7/p73 im2 rising edge detection circuit falling edge detection circuit selector intw irqw noise eliminator
33 m pd75516 8. standby functions two standby modes (stop mode and halt mode) are available for the m pd75516 to decrease power consumption in the program standby mode. table 8-1 operation status in standby mode set instruction system clock when set clock generator basic interval timer serial interface (channel 0) serial interface (channel 1) timer/event counter watch timer a/d converter timer/pulse generator external interrupt cpu stop mode stop instruction setting enabled only with main system clock. oscillator stops only with main system clock. operation stopped. operation enabled only when external sck0 input is selected for serial clock. operation enabled only when external sck1 input is selected for serial clock. operation enabled only when ti0 pin input is specified for count clock. operation enabled only f xt is selected for count clock. operation stopped. operation stopped. halt mode halt instruction setting enabled with either main system clock or subsystem clock. stops only with cpu clock f (oscillation continued). operation (irqbt set at reference time intervals). operation enabled when the main system clock oscillates or with external sck0. operation enabled only when the main system clock oscillates. operation enabled only when the main system clock oscillates. operation enabled. operation enabled only when the main system clock oscillates. operation enabled only when the main system clock oscillates. operating state int1, 2, and 4 operation enabled. int0 operation disabled. operation stopped. interrupt request signal or reset input from operational hardware enabled by interrupt enable flag. release signal
34 m pd75516 9. reset function the m pd75516 is reset and the hardware is initialized as shown in table 9-1 by reset input. the reset operation timing is shown in fig. 9-1. fig. 9-1 reset operation by reset input wait (31.3 ms/4.19 mhz) halt mode operating mode internal reset operation operating mode or standby mode reset input table 9-1 status of each hardware after resetting (1/2) carry flag (cy) skip flag (sk0 to 2) interrupt status flag (ist0, 1) bank enable flag (mbe, rbe) stack pointer (sp) data memory (ram) general register (x, a, h, l, d, e, b, c) bank selection register (mbs, rbs) program counter (pc) reset input during operation same as the left undefined 0 0 same as the left undefined undefined undefined 0, 0 reset input in standby mode low-order 6 bits of program memory address 0000h are set in pc13 to 8 and the contents of address 0001h are set in pc7 to 0. held 0 0 bit 6 of program memory address 0000h is set in rbe, and bit 7 is set in mbe. undefined held * held 0, 0 hardware psw counter (bt) mode register (btm) counter (t0) modulo register (tmod0) mode register (tm0) toe0, tout f/f modulo register mode register mode register (wm) basic interval timer undefined 0 0 ffh 0 0, 0 held 0 0 undefined 0 0 ffh 0 0, 0 held 0 0 timer/event counter timer/pulse generator watch timer * data of data memory addresses 0f8h to 0fdh becomes undefined by reset input.
35 m pd75516 table 9-1 hardware statuses after reset (2/2) reset input during operation undefined 0 0 undefined 1 04h (eoc = 1) 7fh 0 0 0 undefined 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 undefined reset input in standby mode held 0 0 held 1 04h (eoc = 1) 7fh 0 0 0 held 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 held hardware serial interface (channel 0) shift register (sio0) operating mode register 0 (csim0) sbi control register (sbic) slave address register (sva) p01/sck0 output latch mode register (adm), eoc sa register processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) shift register (sio1) operating mode register 1 (csim1) serial transfer end flag (eot) interrupt request flag (irq ) interrupt enable flag (ie ) interrupt master enable flag (ime) int0, 1, and 2 mode registers (im0, 1, 2) output buffer output latch input/output mode register (pmga, b, c) pull-up resistor specify register (poga) a/d converter clock generator and clock output circuit serial interface (channel 1) interrupt function digital port bit sequential buffer (bsb0 to bsb3)
36 m pd75516 10. instruction set (1) operand identifier and description enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (for details, refer to "ra75x assembler package user's manual C language volume" (eeuC730) ). if more than one description method is available, select one. capital alphabetic letters, plus and minus signs are keywords. describe them as they are. in the case of immediate data, describe appropriate numerical values or labels. identifier description method reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hl-, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label * bit 2-bit immediate data or label fmem fb0h to fbfh and ff0h to fffh immediate data or labels pmem fc0h to fffh immediate data or labels addr 0000h to 3f7fh immediate data or labels caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (bit0 = 0) or label portn port0 to port15 ie iebt, iecsi0, iet0, ie0, ie1, ie2, ie4, iew, ietpg rbn rb0 to rb3 mbn mb0, mb1, mb2, mb15 * for 8-bit data processing, only even addresses can be specified.
m pd75516 37 (2) legend for operation description a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expanded register pair (xa) bc : expanded register pair (bc) de : expanded register pair (de) hl : expanded register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 15) ime : interrupt master enable flag ips : interrupt priority select register ie : interrupt enable flag rbs : register bank select register mbs : memory bank select register pcc : processor clock control register . : address and bit delimiter ( ) : contents addressed by h : hexadecimal data
38 m pd75516 (3) description of symbols in the addressing area column remarks 1. mb indicates accessible memory bank. 2. in *2, mb = 0 irrespective of mbe and mbs. 3. in *4 and *5, mb = 15 irrespective of mbe and mbs. 4. *6 to *10 indicate addressable areas. (4) description of the machine cycle column s indicates the number of machine cycles required for skip operation by an instruction having skip function. the s value varies as follows: ? when not skipped ...................................................................................................... s = 0 ? when 1-byte or 2-byte instructions are skipped .................................................... s = 1 ? when 3-byte instructions are skipped (br !adder, call !adder instruction) ... s = 2 note geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle (= t cy ) of cpu clock f and three time periods are available according to pcc setting. mb = mbe ? mbs (mbs = 0, 1, 15) * 2 mb = 0 mbe = 0 : mb = 0 (00h to 7fh) mb = 15 (80h to ffh) mbe = 1 : mb = mbs (mbs = 0, 1, 15) mb = 15, fmem = fb0h to fbfh, ff0h to fffh * 5 mb = 15, pmem = fc0h to fffh * 6 addr = 0000h to 3f7fh addr = (current pc) C 15 to (current pc) C 1, (current pc) + 2 to (current pc) + 16 caddr = 0000h to 0fffh (pc 13, 12 = 00b) or 1000h to 1fffh (pc 13, 12 = 01b) or 2000h to 2fffh (pc 13, 12 = 10b) or 3000h to 3f7fh (pc 13, 12 = 11b) * 9 faddr = 0000h to 07ffh *10 taddr = 0020h to 007fh data memory addressing program memory addressing *3 *1 *4 *7 *8
m pd75516 39 a, #n4 1 1 a ? n4 stack a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 stack a hl, #n8 2 2 hl ? n8 stack b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg 2 2 a ? reg xa, rp' 2 2 xa ? rp' reg1, a 2 2 reg1 ? a rp'1, xa 2 2 rp'1 ? xa a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp' xa, @pcde 1 3 xa ? (pc 13C8 +de) rom xa, @pcxa 1 3 xa ? (pc 13C8 +xa) rom machine cycle skip condition addressing area no. of bytes mov transfer movt xch note 1. instruction group 2. table reference mnemonic operands operation note 1 note 2
40 m pd75516 machine cycle skip condition addressing area no. of bytes cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) ? cy *1 a, #n4 1 1 + s a ? a+n4 carry xa, #n8 2 2 + s xa ? xa+n8 carry a, @hl 1 1 + s a ? a+(hl) *1 carry xa, rp' 2 2 + s xa ? xa+rp' carry rp'1, xa 2 2 + s rp'1 ? rp'1+xa carry a, @hl 1 1 a, cy ? a+(hl)+cy *1 xa, rp' 2 2 xa, cy ? xa+rp'+cy rp'1, xa 2 2 rp'1, cy ? rp'1+xa+cy a, @hl 1 1 + s a ? aC(hl) *1 borrow xa, rp' 2 2 + s xa ? xaCrp' borrow rp'1, xa 2 2 + s rp'1 ? rp'1Cxa borrow a, @hl 1 1 a, cy ? aC(hl)Ccy *1 xa, rp' 2 2 xa, cy ? xaCrp'Ccy rp'1, xa 2 2 rp'1, cy ? rp'1CxaCcy a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa bit transfer operation mov1 adds addc subs subc and or xor note instruction group mnemonic operand operation note
m pd75516 41 a11cy ? a 0 , a 3 ? cy, a nC1 ? a n a22a ? a reg 1 1 + s reg ? reg+1 reg = 0 rp1 1 1 + s rp1 ? rp1+1 rp1 = 00h @hl 2 2 + s (hl) ? (hl)+1 *1 (hl) = 0 mem 2 2 + s (mem) ? (mem)+1 *3 (mem) = 0 reg 1 1 + s reg ? regC1 reg = fh rp' 2 2 + s rp' ? rp'C1 rp' = ffh reg, #n4 2 2 + s skip if reg = n4 reg = n4 @hl, #n4 2 2 + s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1 + s skip if a = (hl) *1 a = (hl) xa, @hl 2 2 + s skip if xa = (hl) *1 xa = (hl) a, reg 2 2 + s skip if a = reg a = reg xa.rp' 2 2 + s skip if xa = rp' xa = rp' cy 1 1 cy ? 1 cy 1 1 cy ? 0 cy 1 1 + s skip if cy = 1 cy = 1 cy 1 1 cy ? cy machine cycle skip condition addressing area no. of bytes rorc not note 2 increment/decrement decs incs compare ske set1 clr1 skt not1 carry flag manipulation note 1. instruction group 2. accumulator manipulation operands mnemonic operation note 1
42 m pd75516 mem.bit 2 2 (mem.bit) ? 1*3 fmem.bit 2 2 (fmem.bit) ? 1*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 1*5 @h + mem.bit 2 2 (h+mem 3C0 .bit) ? 1*1 mem.bit 2 2 (mem.bit) ? 0*3 fmem.bit 2 2 (fmem.bit) ? 0*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 0*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) ? 0*1 mem.bit 2 2 + s skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2 + s skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit) = 1 *1 (@h+mem.bit) = 1 mem.bit 2 2 + s skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2 + s skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit) = 0 *1 (@h+mem.bit) = 0 fmem.bit 2 2 + s skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 and clear *5 (pmem.@l) = 1 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit)=1 and clear *1 (@h+mem.bit)=1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 pc 13C0 ? addr (optimum instruction is addr selected from among br !addr, *6 brcb !caddr and br $addr by an assembler.) !addr 3 3 pc 13C0 ? addr *6 $addr 1 2 pc 13C0 ? addr *7 !caddr 2 2 pc 13C0 ? pc 13,12 +caddr 11C0 *8 pcde 2 3 pc 13C0 ? pc 13C8 +de pcxa 2 3 pc 13C0 ? pc 13C8 +xa machine cycle skip condition addressing area no. of bytes set1 clr1 skt skf sktclr and1 or1 xor1 memory bit manipulation br brcb br branch note instruction group mnemonic operands operation note
m pd75516 43 (spC4) (spC1) (spC2) ? pc 11C0 !addr 3 3 (spC3) ? mbe, rbe, pc 13, 12 *6 pc 13C0 ? addr, sp ? spC4 (spC4) (spC1) (spC2) ? pc 11C0 !faddr 2 2 (spC3) ? mbe, rbe, pc 13, 12 *9 pc 13C0 ? 00, faddr, sp ? spC4 mbe, rbe, pc 13, 12 ? (sp+1) 13pc 11C0 ? (sp) (sp+3) (sp+2) sp ? sp+4 mbe, rbe, pc 13, 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) sp ? sp+4 then skip unconditionally pc 13, 12 ? (sp+1) 13pc 11C0 ? (sp) (sp+3) (sp+2) psw ? (sp+4) (sp+5), sp ? sp+6 rp 1 1 (spC1) (spC2) ? rp, sp ? spC2 bs 2 2 (spC1) ? mbs, (spC2) ? rbs, sp ? spC2 rp 1 1 rp ? (sp+1) (sp), sp ? sp+2 bs 2 2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 2 2 ime(ips.3) ? 1 ie 22ie ? 1 2 2 ime(ips.3) ? 0 ie 22ie ? 0 a, portn 2 2 a ? portn (n = 0 to 15) xa, portn 2 2 xa ? portn+1, portn (n = 4, 6) portn, a 2 2 portn ? a (n = 2 to 7, 9 to 14) portn, xa 2 2 portn+1, portn ? xa (n = 4, 6) 2 2 set halt mode (pcc.2 ? 1) 2 2 set stop mode (pcc.3 ? 1) 1 1 no operation rbn 2 2 rbs ? n (n = 0 to 3) mbn 2 2 mbs ? n (n = 0, 1, 15) machine cycle skip condition addressing area no. of bytes call subroutine stack control callf ret rets 13 + s unconditional reti push pop ei di in * interrupt control input/output cpu control out * halt stop nop sel * mbe = 0 or mbe = 1 and mbe = 15 must be set for execution of in/out instruction note instruction group special mnemonic operands operation note
44 m pd75516 ? tbr instruction pc 13C0 ? (taddr) 4C0 +(taddr+1) ? tcall instruction (spC4)(spC1)(spC2) ? pc 11C0 (spC3) ? mbe, rbe, pc 13, 12 3pc 13C0 ? (taddr) 5C0 +(taddr+1) sp ? spC4 ? (taddr) (taddr+1) instruction depends on executed in the case of instructions instruction except tbr and referred to. tcall instructions machine cycle skip condition addressing area no. of bytes special ---------------------------------------------------- ------------------------ ------------------------ ---------------------------------------------------- 1 geti * taddr *10 * tbr and tcall instructions are assembled pseudo-instructions to define the geti instruction table. note instruction group mnemonic operands operation note
45 m pd75516 v v ma ma ma ma ma ma ma ma ma ma c c C0.3 to +7.0 C0.3 to v dd +0.3 C0.3 to v dd +0.3 peak value effective value peak value effective value peak value effective value peak value effective value ports 4, 5 and 12 to 14 11. electrical specifications unit rating symbol test conditions absolute maximum ratings (ta = 25 c) except ports 4, 5 and 12 to 14 power supply voltage internal pull-up resistor open-drain input voltage v dd v i1 v i2 1 pin all pins 1 pin total of ports 0, 2, 3 and 4 total of ports 5 to 11 total of ports 12 to 14 output voltage output current high operating temperature storage temperature output current low v o i oh v ol * t opt t stg C0.3 to +11 C0.3 to v dd +0.3 C15 C30 30 15 100 60 100 60 40 25 C40 to +85 C65 to +150 v v v * calculate the effective value with the formula [effective value] = [peak value] ? duty. operating voltage power supply voltage ambient temperature power supply voltage ambient temperature power supply voltage ambient temperature v c v c v c a/d converter timer/pulse generator other circuits v dd ta v dd ta v dd ta symbol parameter unit min. max. 3.5 C10 4.5 C40 2.7 C40 6.0 +70 6.0 +85 6.0 +85 test conditions parameter input capacitance output capacitance input /output capacitance 15 15 15 pf pf pf c i c o c io capacitance (ta = 25 c, v dd = 0 v) f = 1 mhz unmeasured pin returned to 0 v symbol test conditions parameter min. typ. max. unit
46 m pd75516 main system clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) v dd = oscillation voltage range after v dd reaches the minimum value in the oscillation voltage range v dd = 4.5 to 6.0 v oscillator frequency (f x ) *1 oscillation stabilization time *2 oscillator frequency (f x ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 high and low level widths (t xh , t xl ) 1.0 1.0 1.0 100 ceramic resonator crystal resonator external clock 4.19 mhz ms mhz ms ms mhz ns 5.0 *3 4 5.0 *3 10 30 5.0 *3 500 resonator recommended circuit parameter test conditions min. typ. max. unit subsystem clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) oscillator frequency (f xt ) *1 oscillation stabilization time *2 xt1 input frequency (f xt ) *1 xt1 high and low level widths (t xth , t xtl ) crystal resonator external clock v dd = 4.5 to 6.0 v 32 32 5 32.768 1.0 35 2 10 100 15 khz s s khz m s resonator recommended circuit parameter test conditions min. typ. max. unit *1. oscillator characteristics only. refer to the description of ac characteristics for details of instruction execution time. 2. time required for oscillation to become stabilized after v dd reaches min. of the oscillation voltage range or after stop mode release. 3. when the oscillator frequency is 4.19 mhz < f x 5.0 mhz, ppc = 0011 should not be selected as the instruction execution time. if pcc = 0011 is selected, one machine cycle is less than 0.95 m s, and the specification min. value of 0.95 m s will not be achieved. x1 x2 c1 c2 x1 x2 c1 c2 x1 x2 m pd74hcu04 xt1 xt2 c3 c4 r xt1 xt2 leave open
47 m pd75516 note when the system clock oscillator is used, the following points should be noted concerning wiring in the section enclosed by dots, in order to prevent the effects of wiring capacitance, etc. keep the wiring as short as possible. do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. ensure that oscillator capacitor connection points are always at the same potential as vdd. do not connect in a power supply pattern in which a high current flows. do not take a signal from the oscillator. the subsystem clock oscillator is designed to be a circuit with the low amplification factor to achieve low consumption current, with the result that it is more prone to misoperation due to noise than the main system clock oscillator. therefore, when using the subsystem clock, special care is required for the wiring method. 2.7 kbrC1000h kbrC2.0ms kbrC4.0ms csa 2.00mg csa 4.00mgu csa 4.19mg093 csa 4.91mgu csa 4.91mg cst 2.00mg cst 4.00mgu cst 4.19mg093 cst 4.91mgu cst 4.91mg crhf 3.00 crhf 4.19 c1 c2 min. max. kyocera corp. murata mfg. co., ltd. toko, inc. 100 47 33 30 30 on-chip on-chip 27 100 47 33 30 on-chip on-chip 27 2.7 30 3.0 2.7 3.0 3.0 6.0 6.0 6.0 external capacitance (pf) oscillation voltage range (v) manufacturer product name remarks recommended oscillator constants main system clock : ceramic resonator (ta = C40 to +85 c) main system clock : crystal resonator (ta = C20 to +70 c) c1 c2 min. max. 27 27 external capacitance (pf) oscillation voltage range (v) manufacturer product name remarks 2.7 6.0 hcC49/u kinseki h
48 m pd75516 ports 2 to 5, 9 to 14, p80, p82 ports 0, 1, 6, 7, 15, p81, p83, reset x1, x2, xt1 except below x1, x2, xt1 except below x1, x2, xt1 ports 4, 5, 12 to 14 (when open-drain) v dd = 4.5 to 6.0 v, i oh = C1 ma i oh = 100 m a dc characteristics (ta = C40 to 85 c, v dd = 2.7 to 6.0 v) v ih1 v ih2 ports 2, 3, 9 to 11, p80, p82 ports 0, 1, 6, 7, 15, p81, p83, reset port 4, 5, 12 to 14 v ih3 x1, x2, xt1 v ih4 input voltage high v il1 v il2 v il3 input voltage low output voltage high ports 3, 4, 5 v dd = 4.5 to 6.0v, i ol = 15 ma v dd = 4.5 to 6.0 v, i ol = 1.6 ma i ol = 400 m a sb0, 1 open-drain pull-up resistance 3 1k w v oh v ol output voltage low i lih1 v i = v dd v i = 9 v i lih2 i lih3 input leakage current high input leakage current low i lil1 i lil2 v i = 0 v except below ports 4, 5, 12 to 14 (when open-drain) v o = v dd i loh1 v o = 9 v i loh2 output leakage current high v dd = 5.0 v 10% ports 0, 1, 2, 3, 6, 7 (except p00) v i = 0 v v dd = 3.0 v 10% ports 4, 5, 12 to 14 v o = v dd C2.0 v v dd = 5.0 v 10% v dd = 3.0 v 10% r u2 r u1 internal pull-down resistor output leakage current low i lol v o = 0 v 0.7 v dd v dd v 0.8 v dd v dd v 0.7 v dd v dd v 0.7 v dd 10 v v dd C0.5 v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.4 v internal pull-up resistor open-drain v dd C1.0 v v dd C0.5 v 0.4 2.0 v 0.4 v 0.5 v 0.2 v dd v 3 m a 20 m a 20 m a C3 m a C20 m a 3 m a 20 m a C3 m a 15 40 80 k w 30 300 k w 15 40 70 k w 10 60 k w r d v o = 2 v port 9 20 70 140 k w internal pull-up resistor symbol parameter test conditions min. typ. max. unit
49 m pd75516 600 1800 m a dc characteristics (ta = C40 to 85 c, v dd = 2.7 to 6.0 v) i dd3 i dd1 32.768 khz crystal oscillation *5 v dd = 5 v 10% *3 v dd = 3 v 10% *4 v dd = 5 v 10% v dd = 3 v 10% v dd = 3 v 10% v dd = 3 v 10% ta = 25 c i dd2 operating mode halt mode halt mode operating mode v dd = 5 v 10% v dd = 3 v 10% i dd4 i dd5 xt1 = 0 v stop mode 39ma 0.55 1.5 ma 200 600 m a 40 120 m a 515 m a 0.5 20 m a 0.3 10 m a 5 m a supply current *1 *1. current flowing to the internal pull-up resistor excluded. 2. subsystem clock oscillation also included. 3. when operated in the high speed mode with the processor clock control register (pcc) set to 0011. 4. when operated in the low speed mode with pcc = 0000. 5. when operated on the subsystem clock after the main system clock oscillation stop with the system clock control register (scc) set to 1001. parameter symbol test conditions min. typ. max. unit 4.19 mhz crystal oscillation c1 = c2 = 22 pf *2
50 m pd75516 v dd = 4.5 to 6.0 v 0.95 64 m s 3.8 64 m s operation with subsystem clock 114 122 125 m s v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz v dd = 4.5 to 6.0 v 0.48 m s 1.8 m s int0 *2 m s int1, 2, 4 10 m s kr0C7 10 m s 10 m s ac characteristics (ta = C40 to +85 c , v dd = 2.7 to 6.0 v) (1) basic operation f ti t cy t tih , t til operation with main system clock ti0 input frequency ti0 input high and low- level widths reset low-level width t rsl cycle time t cy [ m s] *1. the cpu clock ( f ) cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (scc) and the processor clock control register (pcc). the cycle time t cy characteristics for power supply voltage v dd when the main system clock is in operation is shown below. 2. 2t cy or 128/f x is set by interrupt mode register (im0) setting. 70 64 60 6 5 4 3 2 1 0.5 0 1 2 3 4 5 6 operation guaranteed range t cy vs v dd (main system clock in operation) power supply voltage v dd [v] parameter symbol test conditions min. typ. max. unit t inth , t intl interrupt input high and low-level widths cpu clock cycle time (minimum instruction execution time = 1 machine cycle ) *1
51 m pd75516 so output delay time from sck 1600 ns 3800 ns v dd = 4.5 to 6.0 v (t kcy1 /2)C50 ns (t kcy1 /2) C150 ns 150 ns 400 ns v dd = 4.5 to 6.0 v 250 ns 1000 ns (2) serial transfer operation (a) 2-wire and 3-wire serial i/o mode (sck...internal clock output) sck cycle time t kcy1 r l = 1 k w c l = 100 pf * t kso1 si setup time (to sck - ) si hold time (from sck - ) t ksi1 t sik1 t kl1 t kh1 sck high and low level widths v dd = 4.5 to 6.0 v * r l and c l are so output line load resistance and load capacitance, respectively. (b) 2-wire and 3-wire serial i/o mode (sck...external clock input) v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns 400 ns v dd = 4.5 to 6.0 v 300 ns 1000 ns r l = 1 k w c l = 100 pf * sck cycle time t kcy2 t kl2 t kh2 si setup time (to sck - ) t sik2 t ksi2 si hold time (from sck - ) t kso2 so output delay time from sck * r l and c l are so output line load resistance and load capacitance, respectively. sck high and low level widths parameter symbol test conditions min. typ. max. unit parameter symbol test conditions min. typ. max. unit
52 m pd75516 (c) sbi mode (sck...internal clock output (master)) v dd = 4.5 to 6.0 v 1600 ns 3800 ns v dd = 4.5 to 6.0 v t kcy3 /2C50 ns t kcy3 /2C150 ns 150 ns t kcy3 /2 ns v dd = 4.5 to 6.0 v 0 250 ns 0 1000 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 ns r l = 1 k w c l = 100 pf * t kcy3 t kl3 t kh3 t sik3 t ksi3 t kso3 sck cycle time sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high and low level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh * r l and c l are so output line load resistance and load capacitance, respectively. (d) sbi mode (sck...external clock input (slave)) v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns t kcy4 /2 ns v dd = 4.5 to 6.0 v 0 300 ns 0 1000 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 ns r l = 1 k w c l = 100 pf * t kcy4 t kl4 t kh4 t sik4 t ksi4 t kso4 sck cycle time sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high and low level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh * r l and c l are so output line load resistance and load capacitance, respectively. parameter symbol test conditions min. typ. max. unit parameter symbol test conditions min. typ. max. unit
53 m pd75516 888bit 2.5 v av ref v dd *2 1.5 lsb 168/f x m s 44/f x m s av ss av ref v 1000 m w 1.0 2.0 ma (3) a/d converter (ta = C10 to +70 c, v dd = 3.5 to 6.0 v, av ss = v ss = 0v) absolute accuracy *1 resolution conversion time *3 sampling time *4 analog input voltage analog input impedance av ref current t conv t samp v ian r an i ref *1. absolute accuracy with the quantization error ( 1/2 lsb) excluded. 2. adm1 is set as shown below with regard to the a/d converter reference voltage (av ref ). when 0.6 v dd av ref 0.65 v dd , the adm1 can be set either to 0 or 1. 3. this is the time form the execution of the conversion start instruction to the conversion end (eoc = 1) (operating at 40.1 m s : f x = 4.19 mhz). 4. this is the time from the execution of the conversion start instruction to the sampling end (operating at 10.5 m s : f x = 4.19 mhz). parameter symbol test conditions min. typ. max. unit 2.5 v 0.6 v dd 0.65 v dd v dd (3.5 to 6.0v) adm1 = 0 adm1 = 1 av ref
54 m pd75516 ac timing test points (except x1 and xt1 inputs) clock timing ti0 timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 1/f x t xl t xh v dd - 0.5 v 0.4 v x1 input 1/f xt t xtl t xth v dd - 0.5 v 0.4 v xt1 input 1/f ti t til t tih ti0
55 m pd75516 serial transfer timing 3-wire serial i/o mode: 2-wire serial i/o mode: t kcy2 t kl2 t kh2 t sik2 t kso2 t ksi2 sck sb0,1 t kh1 t kcy1 t kl1 t sik1 t ksi1 t kso1 sck si so input data output data
56 m pd75516 serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing t ksb sck sb0,1 t sbl t sbh t sbk t kl3,4 t kh3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sck t ksb sb0,1 t sbk t kl3,4 t kh3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 int0,1,2,4 kr0-7 t intl t inth reset t rsl
57 m pd75516 data memory stop mode low power supply voltage data retention characteristics (ta = C40 to +85 c) 2.0 6.0 v v dddr = 2.0 v 0.1 10 m a 0 m s release by reset 2 17 /f x ms release by interrupt request *3 ms *1. current to the internal pull-up resistor is not included. 2. oscillation stabilization wait time is time to stop cpu operation to prevent unstable operation upon oscillation start. 3. according to the setting of the basic interval timer mode register (btm) (see below). 0 00 2 20 /f x (approx. 250 ms) 0 11 2 17 /f x (approx. 31.3 ms) 1 01 2 15 /f x (approx. 7.82 ms) 1 11 2 13 /f x (approx. 1.95 ms) wait time (values at f x = 4.19 mhz in parentheses) btm3 btm2 btm1 btm0 data retention timing (stop mode release by reset) parameter symbol test conditions min. typ. max. unit release signal set time oscillation stabilization wait time *2 t wait data retention power supply voltage data retention power supply current *1 v dddr i dddr t srel stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation
58 m pd75516 data retention timing (standby release signal: stop mode release by interrupt signal) stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel
m pd75516 59 12. characteristic curves i dd vs v dd (main system clock : crystal oscillation) power supply voltage vdd [v] 5000 1000 500 100 50 10 5 1 0 1 2 3 4 5 6 7 c4 r (ta=25 c) main system clock halt mode subsystem clock operating mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode c1 c2 c3 4.19 mhz 32.768 khz x1 x2 xt1 xt2 crystal resonator crystal resonator high-speed mode pcc=0011 medium-speed mode pcc=0010 low-speed mode pcc=0000 power supply current i dd [ m a]
m pd75516 60 * this is larger than the crystal oscillation by about 10%. 5000 1000 500 100 50 10 5 1 0 1 2 3 4 5 6 7 c4 r (ta=25 c) main system clock halt mode * subsystem clock operating mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode c1 c2 c3 4.19 mhz 32.768 khz x1 x2 xt1 xt2 ceramic oscillator crystal resonator high-speed mode pcc=0011 medium-speed mode pcc=0010 low-speed mode pcc=0000 i dd vs v dd (main system clock : crystal oscillation) power supply voltage vdd [v] power supply current i dd [ m a]
m pd75516 61 5000 1000 500 100 50 10 5 1 0 1 2 3 4 5 6 7 c4 r (ta=25 c) main system clock halt mode subsystem clock operating mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode c1 c2 c3 2.0 mhz 32.768 khz x1 x2 xt1 xt2 ceramic oscillator crystal resonator high-speed mode pcc=0011 medium-speed mode pcc=0010 low-speed mode pcc=0000 power supply voltage vdd [v] ii dd vs v dd (main system clock : crystal oscillation) power supply current i dd [ m a]
m pd75516 62 i dd vs v dd (main system clock : crystal oscillation) power supply current i dd [ m a] power supply voltage vdd [v] 5000 1000 500 100 50 10 5 1 0 1 2 3 4 5 6 7 c4 r (ta=25 c) subsystem clock operating mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode c1 c2 c3 1.0 mhz 32.768 khz x1 x2 xt1 xt2 ceramic oscillator crystal resonator high-speed mode pcc=0011 medium-speed mode pcc=0010 low-speed mode pcc=0000 main system clock halt mode
m pd75516 63 x1 x2 3 2 1 0 1 2 3 4 5 i dd [ma] 40 30 10 0 i ol [ma] 20 1 2 3 4 5 f x [mhz] v ol [v] 0.5 0.2 i dd [ma] 0.4 0.3 0 1 2 3 4 5 f x [mhz] 0.1 40 10 i ol [ma] 30 20 0 1 2 3 4 5 v ol [v] high-speed mode pcc = 0011 medium-speed mode pcc = 0010 low-speed mode pcc = 0000 main system clock halt mode v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v x1 x2 low-speed mode pcc = 0000 main system clock halt mode medium- speed mode pcc = 0010 high-speed mode pcc = 0011 v ol vs i ol (port 3, 4 ,5) (ta = 25 c) i dd vs f x (v dd = 5v, ta = 25 c) v ol vs i ol (port 0, 2, 6, 7) (ta = 25 c) i dd vs f x (v dd = 3v, ta = 25 c)
m pd75516 64 20 15 10 5 0 1 2 3 4 5 i oh [ma] v dd C v oh [v] v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v oh vs i oh (ta = 25 c) v dd = 2.7 v
m pd75516 65 13. package information n a m f b 64 65 40 k l 80 pin plastic qfp (14 20) 80 1 25 24 41 g d c p detail of lead end s q 55? m i h j p80gf-80-3b9-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.8 0.35 0.10 0.15 20.0 0.2 0.929 0.016 0.039 0.031 0.006 0.031 (t.p.) 0.795 note m n 0.15 0.15 1.8 0.2 0.8 (t.p.) 0.006 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.014 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009
m pd75516 66 14. recommeded soldering conditions the m pd75516 should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions for the surface mounting type, refer to the document semiconductor device mount technology (iei-1207) . for soldering methods and conditions other than those recommended below, contact our salesman. table 4C1 surface mount type soldering conditions m pd75516gfC C3b9: 80Cpin plastic qfp (14 20 mm) note use of more than one soldering method should be avoided (except in the case of pin part heating). for your information products to improve the recommended soldering conditions are available. (improvements: extension of the infrared reflow peak temperature to 235oc, doubled frequency, increased life, etc.) for further details, consult our sales personnel. ws60-00-1 soldering conditions package peak temperature: 230 c duration: 30 sec. max. (at 210 c or above) number of times: once package peak temperature: 215 c duration: 40 sec. max. (at 200 c or above) number of times: once solder bath temperature: 260 c or less duration: 10 sec. max. number of times: once preheating temperature: 120 c max. (package surface temperature) pin part temperature: 300 c or less duration: 3 sec. max. (per device side) soldering method pin part heating recommended condition symbol infrared reflow vps ir30-00-1 vp15-00-1 wave soldering h -
m pd75516 67 appendix a. development tools the following development tools are available for the development of systems using the m pd75516. ieC75000Cr *1 inCcircuit emulator for use with the 75x series ieC75001Cr ieC75000CrCem *2 emulation board for use with the ieC75000Cr and the ieC75001Cr epC75516gfCr emulation probe for use with the m pd75516. 80Cpin conversion socket evC9200gC80 included evC9200gC80 pgC1500 prom programmer paC75p516gf connect to pgC1500 with prom programmer adapter for use with the m pd75p516gf ie control program host machine pgC1500 controller pcC9800 series (msCdos? ver. 3.30 to ver. 5.00a *3 ) ibm pc/at? (pc dos? ver. 3.1) ra75x relocatable assembler *1. maintenance product 2. not a builtCin component in the ieC75001Cr 3. ver. 5.00/5.00a has a task swapping function, which cannot be used with this software. remarks refer to the "75x series selection guide" (ifC151) for thirdCparty development tools. software hardware
m pd75516 68 appendix b. related documents device related documents document name document number user's manual iemC5049 instruction application table iemC5036 basic volume iemC5104 application note a/d converter volume ieaC630 75x series selection guide ifC151 development tools documents document name document number ieC75000Cr/ieC75000Cr user's manual eeuC846 ieC75000CrCem user's manual eeuC673 epC75516gfCr user's manual eeuC703 pgC1500 user's manual eeuC651 operation volume eeuC731 ra75x assembler package user's manual language volume eeuC730 pgC1500 controller user's manual eeuC704 other documents document name document number package manual ieiC635 surface mount technology manual ieiC1207 quality grade on nec semiconductor devices ieiC1209 nec semiconductor device reliability & quality control iemC5068 electrostatic discharge (esd) test memC539 semiconductor device quality guide guarantee guide meiC603 microcomputer related products guide meiC604 C other manufacturers volume note the information in these related documents is subject to change without notice. for design purpose, etc., be sure to use the latest ones. h hardware software
m pd75516 69
[memo] m4 92.6 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m pd75516 ms-dos is a trademark of microsoft corporation. pc dos and pc/at are trademarks of ibm corporation.

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