View X25650Z-25_1767129.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

not recommended for new design rev 1.1 9/8/00 characteristics subject to change without notice. 1 of 15 www.xicor.com recommended system management alternative: x5643 64k x25650 8k x 8 bit 5mhz spi serial eeprom with block lock protection features 5mhz clock rate low power cmos <1? standby current <5ma active current 2.5v to 5.5v power supply spi modes (0,0 & 1,1) 8k x 8 bits 32 byte page mode block lock protection protect 1/4, 1/2 or all of eeprom array programmable hardware write protection in-circuit programmable rom mode built-in inadvertent write protection power-up/down protection circuitry write enable latch write protect pin self-timed write cycle 5ms write cycle time (typical) high reliability endurance: 1,000,000 cycles data retention: 100 years esd protection: 2000v on all pins packages 8-lead soic 14-lead soic description the x25650 is a cmos 65,536-bit serial eeprom, internally organized as 8k x 8. the x25650 features a serial peripheral interface (spi) and software protocol, allowing operation on a simple three-wire bus. the bus signals are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input, allowing any number of devices to share the same bus. the x25650 also features two additional inputs that pro- vide the end user with added ?xibility. by asserting the hold input, the x25650 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. the wp input can be used as a hardwire input to the x25650 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. the x25650 utilizes xicors proprietary direct write cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. block diagram command decode and control logic write control and timing logic write protect logic x decode logic 8kbyte array 64 x 256 y decode data register so si sck cs hold wp 64 128 8 32 status register 64 128 x 256 64 x 256 direct write and block lock protection is a trademark of xicor, inc.
not recommended for new design x25650 characteristics subject to change without notice. 2 of 15 rev 1.1 9/8/00 www.xicor.com pin descriptions serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. chip select (cs ) when cs is high, the x25650 is deselected and the so output pin is at high impedance and unless an internal write operation is underway, the x25650 will be in the standby power mode. cs low enables the x25650, placing it in the active power mode. it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. write protect (wp ) when wp is low and the nonvolatile bit wpen is ?? nonvolatile writes to the x25650 status register are dis- abled, but the part otherwise functions normally. when wp is held high, all functions, including nonvolatile writes operate normally. wp going low while cs is still low will interrupt a write to the x25650 status reg- ister. if the internal write cycle has already been initi- ated, wp going low will have no affect on a write. the wp pin function is blocked when the wpen bit in the status register is ?? this allows the user to install the x25650 in a system with wp pin grounded and still be able to write to the status register. the wp pin func- tions will be enabled when the wpen bit is set ?? pin names pin configuration hold (hold ) hold is used in conjunction with the cs pin to pause the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume com- munication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage hold hold input nc no connect cs so wp v ss 1 2 3 4 8 7 6 5 v cc hold sck si soic 14-lead soic nc 1 nc 2 cs 3 so 4 wp 5 v ss 6 nc 7 14 nc 13 nc 12 v cc 11 hold 10 sck 9si 8nc * pin 3 and pin 4 are internally connected.
not recommended for new design x25650 characteristics subject to change without notice. 3 of 15 rev 1.1 9/8/00 www.xicor.com principles of operation the x25650 is a 8k x 8 eeprom designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the x25650 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising sck. cs must be low and the hold and wp inputs must be high during the entire operation. table 1 contains a list of the instructions and their opcodes. all instructions, addresses and data are transferred msb ?st. data input is sampled on the ?st rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock and then resume operations. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input to place the x25650 into a ?ause condition. after releasing hold , the x25650 will resume operation from the point when hold was ?st asserted. write enable latch the x25650 contains a ?rite enable latch. this latch must be set before a write operation will be com- pleted internally. the wren instruction will set the latch and the wrdi instruction will reset the latch. this latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status reg- ister write cycle. status register the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is format- ted as follows: wpen, bl0 and bl1 are set by the wrsr instruction. wel and wip are read-only and automatically set by other operations. the write-in-process (wip) bit indicates whether the x25650 is busy with a write operation. when set to a ?? a write is in progress, when set to a ?? no write is in progress. during a write, all other bits are ?on? care? the write enable latch (wel) bit indicates the status of the ?rite enable latch. when set to a ?? the latch is set, when set to a ?? the latch is reset. the block lock (bl0 and bl1) bits are nonvolatile and allow the user to select one of four levels of protection. the x25650 is divided into four 16384-bit segments. one, two, or all four of the segments may be protected. that is, the user may read the segments but will be unable to alter (write) data within the selected seg- ments. the partitioning is controlled as illustrated below. 76543210 wpen x x x bl1 bl0 wel wip status register bits array addresses protected bl1 bl0 0 0 none 0 1 $1800?1fff 1 0 $1000?1fff 1 1 $0000?1fff table 1. instruction set note: *instructions are shown msb in leftmost position. instructions are transferred msb ?st. instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address (1 to 32 bytes)
not recommended for new design x25650 characteristics subject to change without notice. 4 of 15 rev 1.1 9/8/00 www.xicor.com the write-protect-enable (wpen) bit is available for the x25650 as a nonvolatile enable bit for the wp pin. wpen wp wel protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable programmable hardware write protection the write protect (wp ) pin and the nonvolatile write protect enable (wpen) bit in the status register con- trol the programmable hardware write protect feature. hardware write protection is enabled when wp pin is low, and the wpen bit is ?? hardware write protec- tion is disabled when either the wp pin is high or the wpen bit is ?? when the chip is hardware write pro- tected, nonvolatile writes are disabled to the status register, including the block lock bits and the wpen bit itself, as well as the block-protected sections in the memory array. only the sections of the memory array that are not block-protected can be written. in circuit programmable rom mode note that since the wpen bit is write protected, it can- not be changed back to a low state; so write protec- tion is enabled as long as the wp pin is held low. thus an in circuit programmable rom function can be implemented by hardwiring the wp pin to vss, writing to and block locking the desired portion of the array to be rom, and then programming the wpen bit high. the table above de?es the program protect status for each combination of wpen and wp . clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the eeprom memory array, cs is ?st pulled low to select the device. the 8-bit read instruction is transmitted to the x25650, followed by the 16-bit address of which the last 13 are used. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached ($1fff) the address counter rolls over to address $0000 allowing the read cycle to be continued inde?itely. the read operation is terminated by taking cs high. refer to the read eeprom array operation sequence illustrated in figure 1. to read the status register the cs line is ?st pulled low to select the device followed by the 8-bit rdsr instruction. after the rdsr opcode is sent, the con- tents of the status register are shifted out on the so line. figure 2 illustrates the read status register sequence. write sequence prior to any attempt to write data into the x25650, the ?rite enable latch must ?st be set by issuing the wren instruction (see figure 3). cs is ?st taken low, then the wren instruction is clocked into the x25650. after all eight bits of the instruction are trans- mitted, cs must then be taken high. if the user con- tinues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the eeprom memory array, the user issues the write instruction, followed by the address and then the data to be written. this is minimally a thirty- two clock operation. cs must go low and remain low for the duration of the operation. the host may continue to write up to 32 bytes of data to the x25650. the only restriction is the 32 bytes must reside on the same page. if the address counter reaches the end of the page and the clock continues, the counter will ?oll over to the ?st address of the page and overwrite any data that may have been written.
not recommended for new design x25650 characteristics subject to change without notice. 5 of 15 rev 1.1 9/8/00 www.xicor.com for the write operation (byte or page write) to be com- pleted, cs can only be brought high after bit 0 of data byte n is clocked in. if it is brought high at any other time the write operation will not be completed. refer to figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which cs going high are valid. to write to the status register, the wrsr instruction is followed by the data to be written. data bits 0, 1, 4, 5 and 6 must be ?? figure 6 illustrates this sequence. while the write is in progress following a status register or eeprom write sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. hold operation the hold input should be high (at v ih ) under normal operation. if a data transfer is to be interrupted hold can be pulled low to suspend the transfer until it can be resumed. the only restriction is the sck input must be low when hold is ?st pulled low and sck must also be low when hold is released. the hold input may be tied high either directly to v cc or tied to v cc through a resistor. operational notes the x25650 powers-up in the following state: the device is in the low power standby state. a high to low transition on cs is required to enter an active state and receive an instruction. so pin is high impedance. the ?rite enable?latch is reset. data protection the following circuitry has been included to prevent in- advertent writes: the ?rite enable?latch is reset upon power-up. a wren instruction must be issued to set the ?rite enable?latch. ?s must come high at the proper clock count in or- der to start a write cycle. figure 1. read eeprom array operation sequence 0 1 2 3 4 5 6 7 8 9 10 2021222324 2526272829 30 7654 32 10 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0
not recommended for new design x25650 characteristics subject to change without notice. 6 of 15 rev 1.1 9/8/00 www.xicor.com figure 2. read status register operation sequence figure 3. write enable latch sequence figure 4. byte write operation sequence 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 01234567 cs si sck high impedance so 012345678910 cs sck si so high impedance instruction 16 bit address data byte 76543210 151413 3210 20 21 22 23 24 25 26 27 28 29 30 31
not recommended for new design x25650 characteristics subject to change without notice. 7 of 15 rev 1.1 9/8/00 www.xicor.com figure 5. page write operation sequence figure 6. write status register operation sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 6543210 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15
not recommended for new design x25650 characteristics subject to change without notice. 8 of 15 rev 1.1 9/8/00 www.xicor.com absolute maximum ratings temperature under bias ....................?5? to +135? storage temperature .........................?5? to +150? voltage on any pin with respect to v ss ....... ?v to +7v d.c. output current ............................................... 5ma (soldering, 10 seconds)......................................300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indi- cated in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0? +70? industrial ?0? +85? supply voltage limits x25650-2.5 2.5v to 5.5v d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d.) power-up timing capacitance t a = +25?, f = 1mhz, v cc = 5v notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. (3) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. max. i cc v cc supply current (active) 5 ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open, cs = v ss i sb v cc supply current (standby) 1 a cs = v cc , v in = v ss or v cc ?0.3v i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v il (1) input low voltage ? v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v i ol = 3ma, v cc = 5v v oh1 output high voltage v cc ?0.8 v i oh = ?.6ma, v cc = 5v v ol2 output low voltage 0.4 v i ol = 1.5ma, v cc = 3v v oh2 output high voltage v cc ?0.3 v i oh = ?.4ma, v cc = 3v symbol parameter min. max. unit t pur (3) power-up to read operation 1 ms t puw (3) power-up to write operation 1 ms symbol parameter max. unit test conditions c i/o (3) output capacitance (so) 8 pf v i/o = 0v c in (3) input capacitance (sck, si, cs , wp , hold ) 6 pf v in = 0v
not recommended for new design x25650 characteristics subject to change without notice. 9 of 15 rev 1.1 9/8/00 www.xicor.com equivalent a.c. load circuit a.c. conditions of test output 5v 1.44k ? 1.95k ? 100pf output 3v 1.64k ? 4.63k ? 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 a.c. operating characteristics data input timing data output timing notes: (4) this parameter is periodically sampled and not 100% tested. (5) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. symbol parameter min. max. unit f sck clock frequency 0 5 mhz t cyc cycle time 200 ns t lead cs lead time 100 ns t lag cs lag time 100 ns t wh clock high time 80 ns t wl clock low time 80 ns t su data setup time 20 ns t h data hold time 20 ns t ri (4) data in rise time 2 s t fi (4) data in fall time 2 s t hd hold setup time 40 ns t cd hold hold time 40 ns t cs cs deselect time 100 ns t wc (5) write cycle time 10 ms symbol parameter min. max. unit f sck clock frequency 0 5 mhz t dis output disable time 100 ns t v output valid from clock low 80 ns t ho output hold time 0 ns t ro (4) output rise time 50 ns t fo (4) output fall time 50 ns t lz (4) hold high to output in low z 50 ns t hz (4) hold low to output in high z 50 ns
not recommended for new design x25650 characteristics subject to change without notice. 10 of 15 rev 1.1 9/8/00 www.xicor.com serial output timing serial input timing sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance
not recommended for new design x25650 characteristics subject to change without notice. 11 of 15 rev 1.1 9/8/00 www.xicor.com hold timing sck cs si so t hd t lz hold t hz t cd t hd t cd
not recommended for new design x25650 characteristics subject to change without notice. 12 of 15 rev 1.1 9/8/00 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
not recommended for new design x25650 characteristics subject to change without notice. 13 of 15 rev 1.1 9/8/00 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14-lead plastic small outline gullwing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050"typical 0.030"typical 14 places footprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0??8 x 45
not recommended for new design x25650 characteristics subject to change without notice. 14 of 15 rev 1.1 9/8/00 www.xicor.com packaging information note: all dimensions in ? (to convert into inches, 1? = 3.94 x 10 -5 inch) all dimensions are typical values 8-lead xbga complete part number top mark xaas x25650z - 2.5 xaat x25650zi - 2.5 8-lead xbga: top view v cc s1 sck v ss wp hold so cs 1 2 3 4 8 7 6 5 .083 in. .159 in.
not recommended for new design x25650 characteristics subject to change without notice. 15 of 15 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.1 9/8/00 www.xicor.com ordering information part mark convention x25650 p-v device v cc limits 2.5 = 2.5 to 5.5v temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? package s8 = 8-lead soic t s14 = 14-lead soic other packages x blank = 8-lead soic ae = 2.5v to 5.5v, 0? to 70? af = 2.5v to 5.5v, ?0? to +85? s = 14-lead soic x x25650

▲Up To Search▲

Price & Availability of X25650Z-25

	To Download X25650Z-25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .