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ADJD-S312-CR999 miniature surface-mount rgb digital color sensor data sheet features ? fully integrated rgb digital color sensor ? digital i/o via 2-wire serial interface ? industrys smallest form factor C csp 3x3x0.77mm ? adjustable sensitivity for diferent levels of illumina - tion ? uniformly distributed rgb photodiode array ? 7 bit resolution per channel output ? built in internal oscillator ? sleep function when not in use ? no external components ? low supply voltage (vdd) 2.6v ? 0c to 70c operating temperature ? lead free package applications ? general color detection and measurement ? mobile appliances such as mobile phones, pdas, mp3 players,etc ? consumer appliances ? portable medical equipments ? portable color detector/reader description the ADJD-S312-CR999 is a cost efective, cmos digital output rgb color sensor in miniature surface-mount package with a mere size of 3x3x0.77mm. the ic comes with integrated rgb flters, an analog-to-digital converter and a digital core for communication and sensitivity con - trol. the output allows direct interface to micro-controller or other logic control for further signal processing with - out the need of any additional components. this device is designed to cater for wide dynamic range of illumination level and is ideal for applications like por - table or mobile devices which demand higher integra - tion, smaller size and low power consumption. sensitivity control is performed by the serial interface and can be optimized individually for the diferent color channel. the sensor can also be used in conjunction with a white led for refective color management. avago technologies products and software are not specifically designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. customer is solely responsible, and waives all rights to make claims against avago technologies or its suppliers, for all loss, damage, expense or liability in connection with such use. esd warning: standard cmos handling precautions should be observed to avoid static discharge.
general specifcations block diagram feature value interface 100khz serial interface supply 2.6v digital (nominal), 2.6v analog (nominal) photocurrent to voltag e conversi on green photocurrent to voltag e conversi on blue sdaslv sclslv xrst rgb photosenso r arra y sleep gain selectio n control core analog t o digital conversi on photocurrent to voltag e conversi on re d 0v t vdd_ramp v ddd / v dda no voltage must be applied to io's during power-up and power-down ramp time esd protection diode turn-on during power-up and power-down a particular power-up and power-down sequence must be used to prevent any esd diode from turning on inad - vertently. the fgure above describes the sequence. in general, avdd and dvdd should power-up and power - down together to prevent esd diodes from turning on inadvertently. during this period, no voltage should be applied to the ios for the same reason. powering the device ground connection agnd and dgnd must both be set to 0v and preferably star-connected to a central power source as shown in the application diagram. a potential diference between agnd and dgnd may cause the esd diodes to turn on inadvertently.
electrical specifcations absolute maximum ratings (notes 1 & 2) recommended operating conditions dc electrical specifcations over recommended operating conditions (unless otherwise specifed) ac electrical specifcations parameter symbol minimum maximum units notes storage temperature t stg_abs -40 85 c digital supply voltage, dvdd to dvss v ddd_abs -0.5 3.7 v analog supply voltage, avdd to avss v dda_abs -0.5 3.7 v input voltage vi n_abs -0.5 v ddd +0.5 v all i/o pins solder refow peak temperature t l_abs 245 c human body model esd rating esd hbm_ abs 2 kv all pins, human body model per jesd22-a114-b parameter symbol minimum maximum units notes free air operating temperature ta 0 25 70 c digital supply voltage, dvdd to dvss v ddd 2.5 2.6 3.6 v analog supply voltage, avdd to avss v dda 2.5 2.6 3.6 v output current load high i oh 3 ma output current load low i ol 3 ma input voltage high level (note 4) v ih 0.7 v ddd v ddd v input voltage low level (note 4) v il 0 0.3 v ddd v parameter symbol conditions minimum typical (note 3) maximum units output voltage high level (note 5) v oh i oh = 3ma v ddd -0.8 v ddd -0.4 v output voltage low level (note 6) v ol i ol = 3ma 0.2 0.4 v dynamic supply current (note 7,8) i dd_dyn (note 9) 9.4 14 ma static supply current (note 8) i dd_static (note 9) 2.7 ma sleep-mode supply current (note 8) i dd_slp (note 9) 0.2 15 ua input leakage current i leak -10 10 ua parameter symbol conditions minimum typical (note 3) maximum units internal clock frequency f clk 16 26 38 mhz
optical specifcation minimum sensitivity (note 3) maximum sensitivity (note 3) parameter symbol conditions minimum typical (note 3) maximum units dark ofset* v d ee = 0 65 lsb *code is from dark code to (dark code + 128lsb) parameter symbol conditions minimum typical (note 3) maximum units irradiance responsivity re l p = 460 nm refer note 10 b 36 lsb/ (mwcm -2 ) l p = 542 nm refer note 11 g 52 l p = 645 nm refer note 12 r 79 parameter symbol conditions minimum typical (note 3) maximum units irradiance responsivity re l p = 460 nm refer note 10 b 1150 lsb/ (mwcm -2 ) l p = 542 nm refer note 11 g 1640 l p = 645 nm refer note 12 r 2310
notes: 1. the absolute maximum ratings are those values beyond which damage to the device may occur. the device should not be operated at these limits. the parametric values defned in the electrical specifcations table are not guaranteed at the absolute maximum ratings. the recom - mended operating conditions table will defne the conditions for actual device operation. 2. unless otherwise specifed, all voltages are referenced to ground. 3. specifed at room temperature (25c) and vddd = vdda = 2.6v. 4. applies to all di pins. 5. applies to all do pins. sdaslv go tri-state when output logic high. minimum voh depends on the pull-up resistor value. 6. applies to all do and dio pins. 7. dynamic testing is performed with the ic operating in a mode representative of typical operation. 8. refers to total device current consumption. 9. output and bidirectional pins are not loaded. 10. test condition is blue light of peak wavelength ( l p ) 460 nm and spectral half width ( ?l ?) 25 nm. 11. test condition is green light of peak wavelength ( l p ) 542 nm and spectral half width ( ?l ?) 35 nm 12. test condition is red light of peak wavelength ( l p ) 645 nm and spectral half width ( ?l ?) 20 nm 13. saturation irradiance = (msb)/(irradiance responsivity) minimum sensitivity (note 13) maximum sensitivity (note 13) parameter symbol conditions minimum typical (note 3) maximum units saturation irradiance l p = 460 nm refer note 10 b 4.17 mwcm -2 l p = 542 nm refer note 11 g 2.88 l p = 645 nm refer note 12 r 1.90 parameter symbol conditions minimum typical (note 3) maximum units saturation irradiance l p = 460 nm refer note 10 b 0.13 mwcm -2 l p = 542 nm refer note 11 g 0.09 l p = 645 nm refer note 12 r 0.06
typical spectral response when the gains for all the color channels are set at equal. spectral response 0 0.2 0.4 0.6 0.8 1 400 500 600 700 wavelength (nm ) relative sensitivity serial interface timing information figure 1. serial interface bus timing waveforms parameter symbol minimum maximum units scl clock frequency f scl 0 100 khz (repeated) start condition hold time t hd:st a s data hold time t hd:da t 0 . s scl clock low period t lo w . - s scl clock high period t high .0 - s repeated start condition setup time t su:st a . - s data setup time t su:da t 0 - n s stop condition setup time t su:st o .0 - s bus free time between start and stop conditions t buf . - s - sda scl t hd:sta t low t high t su:dat t hd:dat t su:sto t buf s p s t su:sta t hd:sta sr
sensor gain optimization fowchart sensor operation fowchart * please refer to application note for more detailed information. high level description the sensor needs to be confgured before it can be used. the gain selection needs to be set for optimum perfor - mance depending on light levels. the fowcharts below describe the diferent procedures required. step 5 acquire adc readings step 1 hardware reset step 3 - 4 select sensor gain settings adc readings optimum? sensor gain optimization step 2 device initialization stop n o yes st ep 6 ac qu ir e adc r ea di n g s st ep 1 ha rd wa re r es et st ep 3 - 4 se le ct s en so r ga in s e tti n g s st ep 5 ac qu ir e da rk o ffs et a n d st or e cu rre n t o ffs et v al ue s se ns or op er at io n st ep 2 de vic e in it ia li za ti on st op st ep 7 co m put e se n s or v al ue s
setup value for photodiode size the following value can be written to each of the photo - diode size registers to adjust the gain of the sensor. the default value after reset for these registers is 07h. setup value for integration time the following value can be written to each of the integra - tion time registers to adjust the gain of the sensor. the default value after reset for these registers is 07h. sensor adc output registers to obtain sensor adc value, 02 hex must be written to acq register before reading the sensor adc output registers. sensor gain settings the sensor gain can be adjusted by varying the photo - diode size and integration time of the sensor manually through the following registers. sensor sensitivity ~ photodiode size x integration time slot detail description a hardware reset (by asserting xrst) should be per - formed before starting any operation. the user controls and confgures the device by program - ming a set of internal registers through a serial interface. at the start of application, the following setup data must be written to the setup registers: address (hex) register setup data (hex) 03 setup0 01 04 setup1 01 0c setup2 01 0d setup3 01 0e setup4 01 address (hex) register description 0b pdasr red channel photodiode size 0a pdasg green channel photodiode size 09 pdasb blue channel photodiode size 11 tintr red channel integration time 10 tintg green channel integration time 0f tintb blue channel integration time value (hex) photodiode size 01 ? 03 ? 07 ? 0f full value (hex) integration time slot 00 1 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0a 11 0b 12 0c 13 0d 14 0e 15 0f 16 address (hex) register description 02 acq acquire sensor analog to digital converter (adc) values when 02h is written. reset to 00h when sensor acquisition is completed 44 adcr sensor red channel adc value. 43 adcg sensor green channel adc value. 42 adcb sensor blue channel adc value.
serial interface reference description the programming interface to the adjd-s312 is a 2-wire serial bus. the bus consists of a serial clock (scl) and a serial data (sda) line. the sda line is bi-directional on adjd-s312 and must be connected through a pull-up resistor to the positive power supply. when the bus is free, both lines are high. the 2-wire serial bus on adjd-s312 requires one device to act as a master while all other devices must be slaves. a master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer while a device addressed by the master is called a slave. slaves are identifed by unique device addresses. both master and slave can act as a transmitter or a receiv - er but the master controls the direction for data transfer. a transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus. the adjd-s312 serial bus interface always operates as a slave transceiver with a data transfer rate of up to 100kbit/s. start/stop condition the master initiates and terminates all serial data trans - fers. to begin a serial data transfer, the master must send a unique signal to the bus called a start condition. this is defned as a high to low transition on the sda line while scl is high. the master terminates the serial data transfer by sending another unique signal to the bus called a stop condition. this is defned as a low to high transition on the sda line while scl is high. the bus is considered to be busy after a start (s) condi - tion. it will be considered free a certain time after the stop (p) condition. the bus stays busy if a repeated start (sr) is sent instead of a stop condition. the start and repeated start conditions are function - ally identical. figure 1: start/stop condition s star t condition p stop condition sd a sc l data transfer the master initiates data transfer after a start condition. data is transferred in bits with the master generating one clock pulse for each bit sent. for a data bit to be valid, the sda data line must be stable during the high period of the scl clock line. only during the low period of the scl clock line can the sda data line change state to either high or low. figure 2: data bit transfer the scl clock line synchronizes the serial data transmis - sion on the sda data line. it is always generated by the master. the frequency of the scl clock line may vary throughout the transmission as long as it still meets the minimum timing requirements. the master by default drives the sda data line. the slave drives the sda data line only when sending an acknowl - edge bit after the master writes data to the slave or when the master requests the slave to send data. the sda data line driven by the master may be imple - mented on the negative edge of the scl clock line. the master may sample data driven by the slave on the posi - tive edge of the scl clock line. figure shows an example of a master implementation and how the scl clock line and sda data line can be synchronized. figure 3: data bit synchronization sda scl data valid data change sda scl sda data sampled on the positive edge of scl sda data driven on the negative edge of scl
10 figure 4: data byte transfer figure 5: slave-receiver acknowledge figure 6: master-receiver acknowledge sd a sc l ms b l sb 1 2 8 9 ac k 1 2 8 9 no ac k s or sr sr or p p sr star t or repeated star t conditio n stop or repeated star t conditio n ms b l sb a complete data transfer is 8-bits long or 1-byte. each byte is sent most signifcant bit (msb) frst followed by an acknowledge or not acknowledge bit. each data transfer can send an unlimited number of bytes (depending on the data format). see figure 4. acknowledge/not acknowledge the receiver must always acknowledge each byte sent in a data transfer. in the case of the slave-receiver and master-transmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either stop sc l (master ) 8 9 sd a ( slave- re ce iver ) sd a (master-transmi tter) ls b acknow ledge acknow ledge clo ck pul se sd a left h ig h by trans mi tte r sd a pulled lo w by rec eive r sc l (master ) 8 9 sd a ( slave-tr an sm itter) sd a (master-recei ver ) acknow ledge clo ck pul se ls b sd a left h ig h by trans mi tte r no t acknow ledge sd a left h ig h by rec eive r p sr stop or repeated star t condition the transfer or generate a repeated start to start a new transfer. see figure 5. in the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. the mas - ter can then send a stop or repeated start condition to begin a new data transfer. in all cases, the master generates the acknowledge or not acknowledge scl clock pulse. see figure 6.
11 addressing each slave device on the serial bus needs to have a unique address. this is the frst byte that is sent by the master-transmitter after the start condition. the address is defned as the frst seven bits of the frst byte. the eighth bit or least signifcant bit (lsb) determines the direction of data transfer. a one in the lsb of the frst byte indicates that the master will read data from the addressed slave (master-receiver and slave-transmit - ter). a zero in this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver). a device whose address matches the address sent by the master will respond with an acknowledge for the frst byte and set itself up as a slave-transmitter or slave-re - ceiver depending on the lsb of the frst byte. the slave address on adjd-s312 is 0x58 (7-bits). figure 7: slave addressing ms b l sb r/ w a1 a6 a5 a4 a3 a2 a0 slav e addres s 1 0 1 1 0 0 0 data format adjd-s312 uses a register-based programming architec - ture. each register has a unique address and controls a specifc function inside the chip. to write to a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then writes the new register data. once the slave acknowl - edges, the master generates a stop condition to end the data transfer. see fgure 8. to read from a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then generates a repeated start condition and resends the slave address sent previously. the least signifcant bit (lsb) of the slave address must indicate that the master wants to read from the slave. the addressed device will then acknowledge the master. the master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. the master then generates a stop condition to end the data transfer. see fgure 9. figure 8: register byte write protocol figure 9: register byte read protocol a6 a5 a4 a3 a2 a1 a0 w a s a p d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ma st er s ends sl ave addres s ma st er w ri te s register addres s ma st er w ri te s register dat a ma st er w ill wr ite dat a start condition stop condition slav e a ck now ledge a slav e a ck now ledge slav e a ck now ledge a6 a5 a4 a3 a2 a1 a0 w a s d7 d6 d5 d4 d3 d2 d1 d0 ma st er w ill wr ite dat a start condition slav e a ck now ledge a p d7 d6 d5 d4 d3 d2 d1 d0 stop condition a6 a5 a4 a3 a2 a1 a0 r sr ma st er w ill read dat a repeat ed st ar t condition slav e a ck now ledge a ma st er not acknow ledge a slav e a ck now ledge ma st er s ends sl ave addres s ma st er w ri te s register addres s ma st er s ends sl ave addres s ma st er reads register dat a
1 avdd dgnd dvdd agnd xrst sdaslv sclslv voltage regulator voltage regulator host system xrst sda scl star-connected ground sleep 10 k host system 10 k 10 k 10 k dvdd a4 d4 c4 c3 a1 a2, a3, d2 c2 d1 pin name type description a1 avdd power analog power pin. a2 agnd ground tie to analog ground. a3 agnd ground tie to analog ground. a4 sleep input when sleep=1, the device goes into sleep mode. in sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. b1 nc no connect no connect. leave foating. b2 nc no connect no connect. leave foating. b3 nc no connect no connect. leave foating. b4 nc no connect no connect. leave foating. c1 nc no connect no connect. leave foating c2 dgnd ground tie to digital ground. c3 sclslv input sdaslv and sclslv are the serial interface communications pins. sdaslv is the bidi - rectional data pin and sclslv is the interface clock. a pull-up resistor should be tied to sdaslv because it goes tri-state to output logic 1. c4 sdaslv input/ output(tri-state high) d1 dvdd power digital power pin. d2 agnd ground tie to analog ground. d3 nc no connect no connect. leave foating. d4 xrst input global, asynchronous, active-low system reset. when asserted low, xrst resets all regis - ters. minimum reset pulse low is 1 us and must be provided by external circuitry. application diagrams powering the device ground connection agnd and dgnd must both be set to 0v and preferably star-connected to a central power source as shown in the application diagram. a potential diference between agnd and dgnd may cause the esd diodes to turn on inadvertently. pin information
1 pin confguration package dimensions 1 2 3 4 a avdd agnd agnd sleep b nc nc nc nc c nc dgnd sclslv sdaslv d dvdd agnd nc xrst note: 1. dimensions are in milimeters (mm) 2. standard tolerances (unless otherwise specifed) a. linear tolerance = +/-0.1mm b. angular tolerance = +/-1
1 recommended underfll type and characteristic ? low moisture absorption type ? total height of underfll from pcb plane to cover up 70 C 85 % ? underfll to cover all 4 side of the package height 70 ~ 85% underfill pcb height 70 ~ 85% underfill pcb delta-flux max. 2 c/sec. t- m in. t- m ax. t -reflow t -peak t-reflo w t-pre 100 ~ 140 sec. 90 ~ 120 sec. 160 c 180 c 217~220 c 240 5 c time tempera ture delta-cooling max. 2 c/sec. delta-ramp max. 1 c/sec. t-comp recommended refow profle it is recommended that henkel pb-free solder paste lf310 be used for soldering ADJD-S312-CR999. below is the recommended refow profle.
1 recommended stencil design ? stencil thickness 5 mils ? stencil type ni electroforming ? stencil aperture type square ? stencil aperture 310 um ? additional feature rounded square edge nsmd 310 um 560 um after soldering or mounting precaution please ensure that all soldered or refowed csp package that is mounted on the pcb is not exposed to compres - sion or loading force directly perpendicular to the fat top surface. precaution: excessive loading force directly perpendicular to the fat top surface may cause pre-mature failure. pcb loading force recommended pcb land pad design ? niau fash over copper pad ? pad diameter (c)= 0.20 mm ? nsmd diameter (d)= 0.25 ~ 0.30 mm
1 recommendations for handling and storage of adjd-s312 this product is qualifed as moisture sensitive level 3 per jedec j-std-020. precautions when handling this moisture sensitive product is important to ensure the reliability of the product. do refer to avago application note an5305 handling of moisture sensitive surface mount devices for details. a. storage before use ? unopened moisture barrier bag (mbb) can be stored at 30c and 90%rh or less for maximum 1 year ? it is not recommended to open the mbb prior to assembly (e.g. for iqc) ? it should also be sealed with a moisture absorbent material (silica gel) and an indicator card (cobalt chloride) to indicate the moisture within the bag b. control after opening the mbb ? the humidity indicator card (hic) shall be read immediately upon opening of mbb ? the components must be kept at <30c/60%rh at all time and all high temperature related process including soldering, curing or rework need to be completed within 168hrs c. control for unfnished reel ? for any unused components, they need to be stored in sealed mbb with desiccant or desiccator at <5%rh d. control of assembled boards ? if the pcb soldered with the components is to be subjected to other high temperature processes, the pcb need to be stored in sealed mbb with desiccant or desiccator at <5%rh to ensure no components have exceeded their foor life of 168hrs e. baking is required if: ? 10% or 15% hic indicator turns pink ? the components are exposed to condition of >30c/60%rh at any time. ? the components foor life exceeded 168hrs ? recommended baking condition (in component form): 125c for 24hrs
package tape and reel dimensions carrier tape dimensions k o b o section b- b section a- a a o 0.30 0.05 b b a a 1.75 0.10 5.50 0.0 5 12.00 0.10 r 0.50 typ . 1.55 0.05 8.00 0.10 1.50 (min.) 4.00 0.10 see note #2 2.00 0.05 see note #2 a o : b o : k o : pitch: width: 3.30 3.30 1.10 8.00 12.00 notes : 1. a o and b o measured at 0.3 mm 2. 10 pitches cumulativ e 3. dimensions are in above base of pocket. tolerance is 0.2 mm. millimeters (mm) .
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limted. all rights reserved. obsoletes av01-0687en av02-0637en - july 30, 2007 reel dimensions 18.0 max.* 178.0 0.5 12.4 45 45 65 r10.65 r5.2 +1.5* - 0.0 55.0 0.5 176.0 512 embossed ribs raised: 0.25 mm width: 1.25 mm back view notes: 1. *measured at hub area. 2. all flange edges to be rounded.

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