spread aware?, eight output zero delay buffer w152 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07148 rev. ** revised september 24, 2001 features ? spread aware??designed to work with ssftg reference signals two banks of four outputs each configuration options to halve, double, or quadruple the reference frequency refer to table 1 to determine the specific option which meets your multiplication needs outputs may be three-stated available in 16-pin soic package extra strength output drive available (-11/-12 versions) contact factory for availability information on 16-pin tssop key specifications operating voltage: ............................................... 3.3v10% operating range: ................... 15 mhz < f outqa < 140 mhz cycle-to-cycle jitter: (refer to figure 3 ) .................... 225 ps cycle-to-cycle jitter: frequency range 25 to140 mhz ......................................................... 125 ps output to output skew: between banks .....................215 ps output to output skew: within banks (refer to figure 4 ) ...................................................100 ps total timing budget impact: ........................................555 ps max. phase error variation:.......................................225 ps tracking skew: ..........................................................130 ps table 1. configuration options device feedback signal qa0:3 qb0:3 w152-1/11 [1] qa0:3 or qb0:3 refx1 refx1 w152-2/12 [2] qa0:3 refx1 ref/2 w152-2/12 [2] qb0:3 refx2 refx1 w152-3 qa0:3 refx2 refx1 w152-3 qb0:3 refx4 refx2 w152-4 qa0:3 or qb0:3 refx2 refx2 notes: 1. w152-11 has stronger output drive than the w152-1. 2. w152-12 has stronger output drive than the w152-2. spread aware is a trademark of cypress semiconductor corporation. block diagram pin configuration qa0 pll ref mux qa1 qa2 qa3 qb0 qb1 2 sel0 fbin qb2 qb3 sel1 2 (present on the -3 and -4 only) (present on the -2, -12, and -3 only) fbin qa3 qa2 vdd gnd qb3 qb2 sel0 16 15 14 13 12 11 10 9 ref qa0 qa1 vdd gnd qb0 qb1 sel1 1 2 3 4 5 6 7 8
w152 document #: 38-07148 rev. ** page 2 of 8 overview the w152 products are eight-output zero delay buffers. a phase-locked loop (pll) is used to take a time-varying signal and provide eight copies of that same signal out. the external feedback to the pll provides outputs in phase with the refer- ence inputs. internal dividers exist in some options allowing the user to get a simple multiple (/2, x2, x4) of the reference input, for details see table 1 . because the outputs are separated into two banks, it is possible to provide some combination of these mul- tiples at the same time. spread aware many systems being designed now utilize a technology called spread spectrum frequency timing generation. cypress has been one of the pioneers of ssftg development, and we de- signed this product so as not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the ss feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchroniza- tion. for more details on spread spectrum timing technology, please see the cypress application note titled, ? emi suppres- sion techniques with spread spectrum frequency timing generator (ssftg) ics. ? functional description logic inputs provide the user the ability to turn off one or both banks of clocks when not in use, as described in table 2 . dis- abling a bank of unused outputs will reduce jitter and power consumption, and will also reduce the amount of emi gener- ated by the w152. these same inputs allow the user to bypass the pll entirely if so desired. when this is done, the device no longer acts as a zero delay buffer, it simply reverts to a standard eight-output clock driver. the w152 pll enters an auto power-down mode when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off. pin definitions pin name pin no. pin type pin description ref 1 i reference input: the output signals qa0:3 through qb0:3 will be synchronized to this signal unless the device is programmed to bypass the pll. fbin 16 i feedback input: when programmed to zero delay buffer mode, this input must be fed by one of the outputs (qa0:3 or qb0:3) to ensure proper functionality. if the trace between fbin and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the ref signal input. qa0:3 2, 3, 14, 15 o outputs from bank a: the frequency of the signals provided by these pins is deter- mined by the feedback signal connected to fbin, and the specific w152 option being used. see table 2 . qb0:3 6, 7, 10, 11 o outputs from bank b: the frequency of the signals provided by these pins is deter- mined by the feedback signal connected to fbin, and the specific w152 option being used. see table 2 . vdd 4, 13 p power connections: connect to 3.3v. use ferrite beads to help reduce noise for optimal jitter performance. gnd 5, 12 g ground connections: connect all grounds to the common system ground plane. sel0:1 9, 8 i function select inputs: tie to v dd (high, 1) or gnd (low, 0) as desired per table 2 . table 2. input logic sel1 sel0 qa0:3 qb0:3 pll 0 0 three-state three-state shutdown 0 1 active three-state active, utilized 1 0 active active shutdown, bypassed 1 1 active active active, utilized
w152 document #: 38-07148 rev. ** page 3 of 8 how to implement zero delay typically, zero delay buffers (zdbs) are used because a de- signer wants to provide multiple copies of a clock signal in phase with each other. the whole concept behind zdbs is that the signals at the destination chips are all going high at the same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described below. external feedback is the trait that allows for this compensation. the pll on the zdb will cause the feedback signal to be in phase with the reference signal. when laying out the board, match the trace lengths between the output being used for feedback and the fbin input to the pll. if it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the fbin pin a little shorter or a little longer than the traces to the devices being clocked. inserting other devices in feedback path another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. this implementation can be applied to any device (asic, multiple output clock buffer/driver, etc.) which is put into the feedback path. referring to figure 2 , if the traces between the asic/buffer and the destination of the clock signal(s) (a) are equal in length to the trace between the buffer and the fbin pin, the signals at the destination(s) device will be driven high at the same time the reference clock provided to the zdb goes high. synchronizing the other outputs of the zdb to the outputs form the asic/buffer is more complex however, as any propagation delay in the asic/buffer must be accounted for. 9 2 3 1 4 7 6 8 5 16 13 14 15 10 11 12 3.3v supply vdd 0.1 f 0.1 f 10 f ferrite bead see note 3 vdd or gnd (for desired operation mo vdd or gnd (for desired operation mode) qa0 qa2 qa1 qa3 ground power power fb in ref in qb1 qb0 qb2 qb3 sel1 sel0 ground vdd figure 1. schematic [3] note: 3. pin 16 needs to be connected to one of the outputs from either bank a or bank b, it should not be connected to both. pins 2 a nd 10 are shown here as examples. none of the outputs should be considered as preferred for the feedback path. reference signal feedback input asic/ buffer zero delay buffer a figure 2. 6 output buffer in the feedback path
w152 document #: 38-07148 rev. ** page 4 of 8 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : t a =0 c to 70 c, v dd = 3.3v 10% parameter description test condition min. typ. max. unit i dd supply current unloaded, 100 mhz 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 12 ma (-11, -12) i ol = 8 ma (-1, -2, -3, -4) 0.4 v v oh output high voltage i oh = 12 ma (-11, -12) i oh = 8 ma (-1, -2, -3, -4) 2.4 v i il input low current v in = 0v 50 a i ih input high current v in = v dd 50 a ac electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v 10% parameter description test condition min. typ. max. unit f in input frequency note 3 15 140 mhz f out output frequency 15-pf load [8] 15 140 mhz t r output rise time (-1, -2, -3, -4) 0.8v to 0.8v, 15-pf load 2 2.5 ns output rise time (-11, -12) 0.8v to 0.8v, 15-pf load 1.5 ns t f output fall time (-1, -2, -3, -4) 2.0v to 0.8v, 15-pf load 2 2.5 ns output rise time (-11, -12) 2.0v to 0.8v, 20-pf load 1.5 ns t iclkr input clock rise time [4] 4.5 ns t iclkf input clock fall time [4] 4.5 ns t pd fbin to ref skew [5, 6] 350 ps t sk output to output skew all outputs loaded equally [10] 215 ps t d duty cycle 15-pf load [7, 8] 45 50 55 % t lock pll lock time power supply stable 1.0 ms t jc jitter, cycle-to-cycle note 9 225 ps notes: 3. input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). see table 1 . 4. longer input rise and fall time will degrade skew and jitter performance. 5. all ac specifications are measured with a 50 ? transmission line. 6. skew is measured at v dd /2 on rising edges. 7. duty cycle is measured at v dd /2. 8. for the higher drive -11 and -12, the load is 20 pf. 9. for frequencies above 25 mhz cy - cy = 125 ps. 10. measured across all outputs. maximum skew between outputs in the same bank is 100 ps.
w152 document #: 38-07148 rev. ** page 5 of 8 ordering information ordering code option package name package type w152 -1, -11, -2, -12, -3, -4 g x 16-pin soic (150 mil) 16-pin tssop (4.4 mm) figure 3. cycle to cycle jitter at 15 pf w152 -01 cycle - cycle jitter @ 15 pf 0 100 200 300 400 500 600 700 800 900 1000 0 20 40 60 80 100 120 140 160 frequency in mhz 07/21/99 w152-a1 ps figure 4. pin to pin skew at 15 pf w152 -01 pin- pin skew @ 15 pf -200 -100 0 100 200 300 a1 a2 a3 a4 b1 b2 b3 b4 output # pin a 1 = ref o7/21/99 a3 ps
w152 document #: 38-07148 rev. ** page 6 of 8 package diagrams 16-pin small outline integrated circuit (soic, 150 mils)
w152 document #: 38-07148 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 16-pin thin shrink small outline package (tssop, 4.4 mm)
w152 document #: 38-07148 rev. ** page 8 of 8 document title: w152 spread aware ? , eight output zero delay buffer document number: 38-07148 rev. ecn no. issue date orig. of change description of change ** 110257 12/15/01 szv change from spec number: 38-00786 to 38-07148
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