spread aware?, zero delay buffer w162 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07150 rev. ** revised november 14, 2001 features ? spread aware??designed to work with ssftg reference signals two banks of four outputs, plus the fed back output outputs may be three-stated available in 16-pin soic or ssop package extra strength output drive available (-19 version) internal feedback key specifications operating voltage: ............................................... 3.3v10% operating range: ................................15 < f out < 133 mhz cycle-to-cycle jitter: .................................................. 250 ps output to output skew: ............................................. 150 ps propagation delay: ..................................................... 150 ps table 1. input logic sel1 sel0 qa0:3 qb0:3 pll qfb 00three- state three- state shutdown active 01activethree- state active, utilized active 1 0 active active shutdown, bypassed active 1 1 active active active, utilized active spread aware is a trademark of cypress semiconductor corporation. block diagram pin configuration pll ref mux qa1 qa2 qa3 qb0 qb1 sel0 qb2 qb3 sel1 qfb qa3 qa2 vdd gnd qb3 qb2 sel0 16 15 14 13 12 11 10 9 ref qa0 qa1 vdd gnd qb0 qb1 sel1 1 2 3 4 5 6 7 8 qfb qa0
w162 document #: 38-07150 rev. ** page 2 of 7 overview the w162 products are nine-output zero delay buffers. a phase-locked loop (pll) is used to take a time-varying signal and provide eight copies of that same signal out. internal feedback is used to maximize the number of output signals provided in the 16-pin package. spread aware many systems being designed now utilize a technology called spread spectrum frequency timing generation. cypress has been one of the pioneers of ssftg development, and we de- signed this product so as not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the ss feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. for more details on spread spectrum timing technology, please see the cypress application note titled, ? emi suppres- sion techniques with spread spectrum frequency timing generator (ssftg) ics. ? functional description logic inputs provide the user the ability to turn off one or both banks of clocks when not in use, as described in table 1 . dis- abling a bank of unused outputs will reduce jitter and power consumption, and will also reduce the amount of emi generat- ed by the w162. these same inputs allow the user to bypass the pll entirely if so desired. when this is done, the device no longer acts as a zero delay buffer, it simply reverts to a standard nine-output clock driver. pin definitions pin name pin no. pin type pin description ref 1 i reference input: the output signals qa0:3 through qb0:3 will be synchro- nized to this signal unless the device is programmed to bypass the pll. qfb 16 o feedback output: this signal is used as the feedback internally to establish the propagation delay of nearly 0. qa0:3 2, 3, 14, 15 o outputs from bank a: the frequency of the signals provided by these pins is equal to the signal connected to ref. qb0:3 6, 7, 10, 11 o outputs from bank b: the frequency of the signals provided by these pins is equal to the signal connected to ref. vdd 4, 13 p power connections: connect to 3.3v. use ferrite beads to help reduce noise for optimal jitter performance. gnd 5, 12 p ground connections: connect all grounds to the common system ground plane. sel0:1 9, 8 i function select inputs: tie to v dd (high, 1) or gnd (low, 0) as desired per table 1 .
w162 document #: 38-07150 rev. ** page 3 of 7 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : t a =0 c to 70 c, v dd = 3.3v 10% parameter description test condition min typ max unit i dd supply current unloaded, 100 mhz 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 12 ma (-19) i ol = 8 ma (-9) 0.4 v v oh output high voltage i ol = 12 ma (-19) i ol = 8 ma (-9) 2.4 v i il input low current v in = 0v ? 500 a i ih input high current v in = v dd 10 a ac electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v 10% parameter description test condition min typ max unit f in input frequency 15 133 mhz f out output frequency 15-pf load [5] 15 133 mhz t r output rise time (-09) [1] 2.0 to 0.8v, 15-pf load 2 2.5 ns output rise time (-19) [1] 2.0 to 0.8v, 20-pf load 1.5 ns t f output fall time (-09) [1] 2.0 to 0.8v, 15-pf load 2 2.5 ns output rise time (-19) [1] 2.0 to 0.8v, 20-pf load 1.5 ns t pd fbin to ref skew [2, 3] measured at v dd /2 150 ps t sk output to output skew all outputs loaded equally 150 ps t d duty cycle 15-pf load [4] 45 50 55 % t lock pll lock time power supply stable 1.0 ms t jc jitter, cycle-to-cycle 250 ps notes: 1. long input rise and fall time will degrade skew and jitter performance. 2. all ac specifications are measured with a 50 ? transmission line, load terminated with 50 ? to 1.4v. 3. skew is measured at v dd /2 on rising edges. 4. duty cycle is measured at v dd /2 5. for the higher drive -19, the load is 20 pf.
w162 document #: 38-07150 rev. ** page 4 of 7 schematic ordering information ordering code option package name package type w162 -09, -19 g h 16-pin plastic soic (150-mil) 16-pin plastic ssop (150-mil) 9 2 3 1 4 7 6 8 5 16 13 14 15 10 11 12 v dd v dd 10 f 0.1 f ferrite bead ferrite bead v dd or gnd (for desired operation mode) v dd or gnd (for desired operation mode) output output output output ground power power output ref in output output output output logic in logic in ground 10 f 0.1 f
w162 document #: 38-07150 rev. ** page 5 of 7 package diagrams 16-pin ssop small shrunk outline package (ssop, 150-mil)
w162 document #: 38-07150 rev. ** page 6 of 7 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 16-pin small outlined integrated circuit (soic, 150-mil)
w162 document #: 38-07150 rev. ** page 7 of 7 document title: w162 spread aware ? . zero delay buffer document number: 38-07150 rev. ecn no. issue date orig. of change description of change ** 110590 12/19/01 dsg change from spec number: 38-00788 to 38-07150
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