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dl138/d rev. 5, dec-2002 f act device data
f act device data dl138/d rev. 5, dec?2002 ? scillc, 2002 previous edition ? 2001 ?all rights reserved?
http://onsemi.com 2 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. f act is a trademark of national semiconductor corporation. mosaic is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p .o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 to ll free usa/canada email : onlit@hibbertco.com n. american technical support : 800?282?9855 toll free usa/canada
http://onsemi.com 3 t able of contents numeric data sheet listing and selection guide page numeric data sheet listing 5 . . . . . . . . . . . . . . . . . . . . . . . . . selection guide 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . inverters 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and gates 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nand gates 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or gates 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nor gates 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . exclusive or (xor) gate 7 . . . . . . . . . . . . . . . . . . . . . . . schmitt triggers 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flip?flops 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multiplexers 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . decoders/demultiplexers 7 . . . . . . . . . . . . . . . . . . . . . . . . latches 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . shift registers 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous counter, negative edge?triggered 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . buffers/line drivers 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t ransceivers 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cascade synchronous counters, positive edge?triggered 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . msi flip?flops/registers 8 . . . . . . . . . . . . . . . . . . . . . . . . chapter 1: description and family characteristics f act family description ? section 1 10 . . . . . . . . . . . . . . . . circuit characteristics ? section 2 15 . . . . . . . . . . . . . . . . . . ratings, specifications and waveforms ? section 3 20 . . . design considerations ? section 4 27 . . . . . . . . . . . . . . . . . . chapter 2: fact data sheets page data sheets 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ch ap te r 3: case outlines and package dimensions device nomenclatures 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . case outlines and package dimensions 321 . . . . . . . . . . . chapter 4: index alphanumeric index 330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sales office listing 331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . document type definitions 332 . . . . . . . . . . . . . . . . . . . . . . .
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http://onsemi.com 5 numeric data sheet listing device number function page mc74ac00, mc74act00 . . . . . . . quad 2?input nand gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 mc74ac02, mc74act02 . . . . . . . quad 2?input nor gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 mc74ac04, mc74act04 . . . . . . . hex inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 mc74ac05, mc74act05 . . . . . . . hex inverter with opne?drain ouptuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 mc74ac08, mc74act08 . . . . . . . quad 2?input and gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mc74ac10, mc74act10 . . . . . . . triple 3?input nand gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 mc74ac11, mc74act11 . . . . . . . triple 3?input and gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 mc74ac14, mc74act14 . . . . . . . hex inverter schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 mc74ac20, mc74act20 . . . . . . . dual 4?input nand gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 mc74ac32, mc74act32 . . . . . . . quad 2?input or gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 mc74ac74, mc74act74 . . . . . . . dual d?type positive edge?triggered flip?flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 mc74ac86, mc74act86 . . . . . . . quad 2?input exclusive or gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 mc74ac109, mc74act109 . . . . . dual jk positive edge?triggered flip?flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 mc74ac125, mc74act125 . . . . . quad buffer with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 mc74ac132, mc74act132 . . . . . quad 2?input nand schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 mc74ac138, mc74act138 . . . . . 1?of?8 decoder/demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 mc74ac139, mc74act139 . . . . . dual 1?of?4 decoder/demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mc74ac151, mc74act151 . . . . . 1?of?8 decoder/demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 mc74ac153, mc74act153 . . . . . dual 4?input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 mc74ac157, mc74act157 . . . . . quad 2?input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 mc74ac161, mc74act161 . . . . . synchronous presettable binary counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 mc74ac163, mc74act163 . . . . . synchronous presettable binary counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 mc74ac174, mc74act174 . . . . . hex d flip?flop with master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 mc74ac175, mc74act175 . . . . . quad d flip?flop with master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 mc74ac240, mc74act240 . . . . . octal buffer/line driver with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 mc74ac244, mc74act244 . . . . . octal buffer/line driver with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 mc74ac245, mc74act245 . . . . . octal bidirectional transceiver with 3?state inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 187 mc74ac253, mc74act253 . . . . . dual 4?input multiplexer with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 mc74ac257, mc74act257 . . . . . quad 2?input multiplexer with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mc74ac259, mc74act259 . . . . . 8?bit addressable latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 mc74ac273, mc74act273 . . . . . octal d flip?flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 mc74ac299, mc74act299 . . . . . 8?input universal shift/storage register with common parallel i/o pins . . . . . . . . . . . . . . . 222 mc74ac373, mc74act373 . . . . . octal transparent latch with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 mc74ac374, mc74act374 . . . . . octal d?type flip?flop with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 mc74ac377, mc74act377 . . . . . octal d flip?flop with clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 mc74ac540, mc74act540 . . . . . octal buffer/line driver with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 mc74ac541, mc74act541 . . . . . octal buffer/line driver with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 mc74ac573, mc74act573 . . . . . octal buffer/line driver with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 mc74ac574, mc74act574 . . . . . octal d flip?flop with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 mc74ac646, mc74act646 . . . . . octal transceiver/register with 3?state outputs, non?inverting . . . . . . . . . . . . . . . . . . . . . . 279 mc74ac652, mc74act652 . . . . . octal transceiver/register with 3?state outputs, non?inverting . . . . . . . . . . . . . . . . . . . . . . 287 mc74ac4040 . . . . . . . . . . . . . . . . . . 12?stage binary ripple counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 mc74act241 . . . . . . . . . . . . . . . . . octal buffer/line driver with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 mc74act323 . . . . . . . . . . . . . . . . . 8?input universal shift/storage register with synchronous reset and common i/o pins . 303 mc74act564 . . . . . . . . . . . . . . . . . octal d?type flip?flop with 3?state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 mc74act640 . . . . . . . . . . . . . . . . . octal 3?state inverting transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
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http://onsemi.com 7 selection guide inverters function t ype of output device page hex 2s mc74ac04, mc74act04 54 hex with open? drain outputs 2s mc74ac05, mc74act05 59 and gates function t ype of output device page quad 2?input 2s mc74ac08, mc74act08 64 t riple 3?input 2s mc74ac11, mc74act11 74 nand gates function t ype of output device page dual 4?input 2s mc74ac20, mc74act20 84 quad 2?input 2s mc74ac00, mc74act00 44 t riple 3?input 2s mc74ac10, mc74act10 69 or gate function t ype of output device page quad 2?input 2s mc74ac32, mc74act32 89 nor gate function t ype of output device page quad 2?input 2s mc74ac02, mc74act02 49 exclusive or gate function t ype of output device page quad 2?input xor 2s mc74ac86, mc74act86 101 schmitt triggers function t ype of output device page hex, inverting 2s mc74ac14, mc74act14 79 quad 2?input nand 2s mc74ac132, mc74act132 117 flip?flops function clock edge device page dual d with set & clear positive mc74ac74, mc74act74 94 dual jk positive mc74ac109, mc74act109 106 multiplexers function t ype of output device page 8?to?1 2s mc74ac151, mc74act151 134 dual 4?to?1, non? inverting 2s mc74ac153, mc74act153 141 dual 4?to?1, non? inverting 3s mc74ac253, mc74act253 193 quad 2?to?1, non?inverting 2s mc74ac157, mc74act157 147 quad 2?to?1, non?inverting 3s mc74ac257, mc74act257 200 decoders/demultiplexers function t ype of output device page dual 1?of?4 2s mc74ac139, mc74act139 128 1?of?8 2s mc74ac138, mc74act138 122 latches function t ype of output device page addressable, 8?bit 2s mc74ac259, mc74act259 207 octal, 8?bit, non? inverting 3s mc74ac573, mc74act573 263 t ransparent, 8?bit, non?inverting 3s mc74ac373, mc74act373 231
http://onsemi.com 8 selection guide (continued) shift registers t ype of mode* function t ype o f output sr sl hold reset device page parallel?in/parallel?out, bidirectional, 8?bit 3s x x x a mc74ac299, mc74act299 222 parallel?in/parallel?out, bidirectional, 8?bit 3s x x x s mc74act323 303 asynchronous counter, negative edge?triggered function device page 12?stage binary with reset mc74ac4040 294 buffers/line drivers function t ype of output device page quad 3s mc74ac125, mc74act125 112 octal, non? inverting 3s mc74act241 298 octal, non? inverting 3s mc74ac244, mc74act244 182 octal, non?invert- ing, bus pinout 2s mc74ac541, mc74act541 254 octal, inverting 3s mc74ac240, mc74act240 177 octal, inverting, bus pinout 2s mc74ac540, mc74act540 254 t ransceivers function t ype of output device page octal, non? inverting 3s mc74ac245, mc74act245 187 octal, non? inverting 3s mc74act640 314 octal, non?inver- ting, with register 3s mc74ac646, mc74act646 279 octal, non?inver- ting, mux latch 3s mc74ac652, mc74act652 287 cascade synchronous counters, positive edge?triggered function load reset device page 4?bit binary, 2s s a mc74ac161, mc74act161 153 4?bit binary, 2s s s mc74ac163, mc74act163 153 msi flip?flops/registers function bits s/r ce device page d?type, non?inv, 2s 4 ? x mc74ac377, mc74act377 246 d?type, non?inv, 2s 6a ? mc74ac174, mc74act174 165 d?type, non?inv, 2s 8 a ? mc74ac273, mc74act273 215 d?type, non?inv, 3s 8? ? mc74ac574, mc74act574 271 d?type, invert, 3s 8 ? ? mc74act564 309
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http://onsemi.com 10 section 1 ? descriptions and family characteristics f act ? logic on semiconductor fact logic offers a unique combination of high speed, low power dissipation, high noise immunity, wide fan-out capability, extended power supply range and high reliability. this data book describes the product line with device specifications as well as material discussing design considerations and comparing the fact family to predecessor technologies. the sub two-micron silicon gate cmos process utilized in this family has been proven in the field. it has been further enhanced to meet and exceed the jedec standards for 74acxx logic. for direct replacement of ls, als and other ttl devices, the ?act circuits with ttl-type input thresholds are included in the fact family. these include the more popular bus drivers/transceivers as well as many other 74actxxx devices. characteristics ? full logic product line ? industry standard functions and pinouts for ssi, msi and lsi ? meets or exceeds jedec standards for 74acxx family ? ttl inputs on selected circuits ? high performance outputs common output structure for standard and buffer drivers output sink/source current of 24 ma t ransmission line driving 50 ohm (commercial) guaranteed ? operation from 2?6 volts guaranteed ? t emperature range ?40 c to +85 c (commercial) ? improved esd protection network ? high current latch-up immunity interfacing f act devices have a wide operating voltage range (v cc = 2 to 6 vdc) and sufficient current drive to interface with most other logic families available today. device designators are as follows: ?ac ? this is a high-speed cmos device with cmos input switching levels and buffered cmos outputs that can drive 24 ma of i oh and i ol current. industry standard ac nomenclature and pinouts are used. ?act ? this is a high-speed cmos device with a ttl-to- cmos input buffer stage. these device inputs are designed to interface with ttl outputs operating with a v cc = 5 v 0.5 v with v oh = 2.4 v and v ol = 0.4 v. these devices have buffered outputs that will drive cmos or ttl devices with no additional interface circuitry. ?act devices have the same output structures as ?ac devices. low power cmos operation if there is one single characteristic that justifies the existence of cmos, it is low power dissipation. in the quiescent state, fact draws three orders of magnitude less power than the equivalent ls or als ttl device. this enhances system reliability; because costly regulated high current power supplies, heat sinks and fans are eliminated, f act logic devices are ideal for portable systems such as laptop computers and backpack communications systems. operating power is also very low for fact logic. power consumption of various technologies with a clock frequency of 1 mhz is shown below. f act = 0.1 mw/gate als = 1.2 mw/gate ls = 2.0 mw/gate hc = 0.1 mw/gate figure 1?1. i cc versus v cc figure 1?1 illustrates the effects of i cc versus power supply voltage (v cc ) for two load capacitance values: 50 pf and stray capacitance. the clock frequency was 1 mhz for the measurements. ac performance in comparison to ls, als and hc families, fact devices have faster internal gate delays. additionally, as the level of integration increases, fact logic leads the way to very high- speed systems.
http://onsemi.com 11 the example below describes typical values for a 74xx138, 3-to-8 line decoder. f act = 6.0 ns @ c l = 50 pf als = 12.0 ns @ c l = 50 pf ls = 22.0 ns @ c l = 15 pf hc = 17.5 ns @ c l = 50 pf ac performance specifications are guaranteed at 5 v 0.5 v and 3.3 v 0.3 v. for worst case design at 2 v v cc on all device types, the formula below can be used to determine ac performance. ac performance at 2 v v cc = 1.9 ac sp ecification at 3.3 v. multiple output switching propagation delay is affected by the number of outputs switching simultaneously. t ypically, devices with more than one output will follow the rule: for each output switching, derate the databook specification by 250 ps. this effect typically is not significant on an octal device unless more than four outputs are switching simultaneously. this derating is valid for the entire temperature range and 5 v 10% v cc . noise immunity the noise immunity of a logic family is also an important equipment cost factor in terms of decoupling components, power supply dynamic resistance and regulation as well as layout rules for pc boards and signal cables. the comparisons shown describe the difference between the input threshold of a device and the output voltage, ? v il ? v ol ? / ? v ih ? v oh ? at 4.5 v v cc . f act = 1.25/1.25 v als = 0.4/0.7 v ls = 0.3/0.7 v @ 4.75 v v cc hc = 0.8/1.25 v output characteristics all f act outputs are buffered to ensure consistent output voltage and current specifications across the family. both ?ac and ?act device types have the same output structures. tw o clamp diodes are internally connected to the output pin to suppress voltage overshoot and undershoot in noisy system applications which can result from impedance mismatching. the balanced output design allows for controlled edge rates and equal rise and fall times. all devices (?ac or ?act) are guaranteed to source and sink 24 ma. commercial devices, 74ac/actxxx, are capable of driving 50 ohm transmission lines. i ol /i oh characteristics f act = 24/?24 ma als = 24/?15 ma ls = 8/?0.4 ma @ 4.75 v v cc hc = 4/?4 ma dynamic output drive t raditionally, in order to predict what incident wave voltages would occur in a system, the designer was required to do an output analysis using a bergeron diagram. not only is this a long and time consuming operation, but the designer needed to depend upon the accuracy and reliability of the manufacturer-supplied ?typical? output i/v curve. additionally, there was no way to guarantee that any supplied device would meet these ?typical? performance values across the operating voltage and temperature limits. fortunately for the system designers, on semiconductor has taken the necessary steps to guarantee incident wave switching on transmission lines with impedances as low as 50 ohms for the commercial temperature range. figure 1?2 shows a bergeron diagram for switching both high-to-low and low-to-high. on the right side of the graph ( i out > 0), are the v oh and i ih curves for fact logic while on the left side (i out < 0), are the curves for v ol and i il . although we will only discuss here the low-to-high transition, the information presented may be applied to a high-to-low transition. ? figure 1?2. gate driving 50 ohm line reflection diagram ? begin analysis at the v ol (quiescent) point. this is the intersection of the v ol /i ol curve for the output and the v in /i in curve for the input. for cmos inputs and outputs, this point will be approximately 100 mv. then draw a 50 ohm load line from this intersection to the v oh /i oh curve as shown by line 1. this intersection is the voltage that the incident wave will have. here it occurs at approximately 3.95 v. then draw a line with a slope of ?50 ohms from this first inte rsection point to the v in /i in curve as shown by line
http://onsemi.com 12 2. this second intersection will be the first reflection back from the input gate. continue this process of drawing the load lines from each intersection to the next. lines terminating on the v oh /i oh curve should have positive slopes while lines terminating on the v in /i in curve should have negative slopes. figure 1?3a. resultant waveforms driving 50 ohm line ? theoretical figure 1?3b. resultant waveforms driving 50 ohm line ? actual figure 1?3c. resultant waveforms driving 50 ohm line ? theoretical each intersection point predicts the voltage of each reflected wave on the transmission line. intersection points on the v oh /i oh curve will be waves travelling from the driver to the receiver while intersection points on the v in /i in curve will be waves travelling from the receiver to the driver. figures 1?3a, 1?3b, 1?3c and 1?3d show the resultant wave- forms. e ach division on the time scale represents the propagation delay of the transmission line. while this exercise can be done for fact, it is no longer necessary. fact is guaranteed to drive an incident wave of enough voltage to switch another fact input. we can calculate what current is required by looking at the bergeron di agram. the quiescent voltage on the line will be within 100 mv of either rail. we know what voltage is required to guarantee a valid voltage at the receiver. this is either 70% or 30% of v cc . the formula for calculating the current and voltage required is ? (v oq ? v i )/z o ? at v i . for v oq = 100 mv, v ih = 3.85 v, v cc = 5.5 v and z o = 50 ohms, the required i oh at 3.85 v is 75 ma. for the high-to-low transition, v oq = 5.4 v, v il = 1.35 v and z o = 50 ohms, i ol is 75 ma at 1.65 v. f act?s i/o specifications include these limits. for transmission lines with impedances greater than 50 ohms, the current requirements are less and switching is still guaranteed. it is important to note that the typical 24 ma drive sp eci fi ca tio n is not adequate to guarantee incident wave switching. the only way to guarantee this is to guarantee the current required to switch a transmission line from the output quiescent point to the valid v in level.
http://onsemi.com 13 figure 1?3d. resultant waveforms driving 50 ohm line ? actual the following performance charts are provided in order to aid the designer in determining dynamic output current drive of fact devices with various power supply voltages. figure 1?4. output characteristics v oh /i oh , mc74ac00 figure 1?5. output characteristics v ol /i ol , mc74ac00 figure 1?6. input characteristics v in /i in choice of voltage specifications to obtain better performance and higher density, semiconductor technologies are reducing the vertical and horizontal dimensions of integrated device structures. due to a number of electrical limitations in the manufacture of vlsi devices and the need for low voltage operation in memory cards, it was decided by the jedec committee to establish interface standards for devices operating at 3.3 v 0.3 v. to this end, on semiconductor guarantees all of its devices operational at 3.3 v 0.3 v. note also that ac and dc specifications are guaranteed between 3 and 5.5 v. operation of f act logic is also guaranteed from 2 to 6 v on v cc . operating voltage ranges f act = 2 to 6 v als = 5 v 10% ls = 5 v 5% hc = 2 to 6 v figure 1?7. internal gate delays
http://onsemi.com 14 general characteristics (all max ratings) symbol parameter ls als hcmos f act unit symbol parameter ls als hcmos ac act unit v cc/ee/dd operating voltage 5 5% 5 10% 2to6 2to6 2to6 v v cc/ee/dd operating v oltage range 5 5 % 5 10% 2 to 6 2 to 6 2 to 6 v t a 74 series operating 0to+70 0to+70 ?40 to +85 ?40 to +85 ?40 to +85 c t a 7 4 s er i es operating t emperature range 0 to +7 0 0 to +7 0 ? 40 to + 8 5 ? 40 to + 8 5 ? 40 to + 8 5 c v ih (min) input voltage (limits) 2 2 3.15 3.15 2 v v il (max) input voltage (limits) 0.8 0.8 0.9 1.35 0.8 v v oh (min) output voltage (limits) 2.7 2.7 v cc ?0.1 v cc ?0.1 v cc ?0.1 v v ol (max) output voltage (limits) 0.5 0.5 0.1 0.1 0.1 v i ih input current 20 20 +1 +1 +1 a i il input current ?400 ?200 ?1 ?1 ?1 a i oh out p ut current at ?0.4 ?0.4 ?4 @ v cc ?0.8 ?24 @ v cc ?0.8 ?24 @ v cc ?0.8 ma i ol output current at v 0 (limit) 8 8 4 @ 0.4 v 24 @ 0.4 v 24 @ 0.4 v ma dcm dc noise margin 0 3/0 7 0 4/0 7 0 8/1 25 1 25/1 25 0 7/2 4 v dcm dc noise margin low/high 0 . 3/0 .7 0 . 4/0 .7 0 . 8/1 . 2 5 1 . 2 5 /1 . 2 5 0 .7 /2 . 4 v note: all dc parameters are specified over the commercial temperature range. figure 1?8. logic family comparisons f act replaces ls, als, hcmos on semiconductor?s advanced cmos family is specifically designed to outperform the ls, als and hcmos families. figure 1?7 shows the relative position of various logic families in speed/power performance. fact exhibits 1 ns internal propagation delays while consuming 1 w of power. the logic family comparisons table below summarizes the key performance specifications for various competitive technology logic families. speed/power characteristics (all typical ratings) symbol parameter ls als hcmos f act unit i g quiescent supply current/gate 0.4 0.2 0.0005 0.0005 ma p g power/gate (quiescent) 2 1.2 0.0025 0.0025 mw t p propagation delay 7 5 8 5 ns ? speed power product 14 6 0.02 0.01 pj f max clock frequency d/ff 33 50 50 160 mhz propagation delay (commercial temperature range) product ls als hcmos f act unit t/t 74xx00 typ 10 5 8 5 ns t plh /t phl 74xx00 max 15 11 23 8.5 ns t plh /t phl 74xx74 typ 25 12 23 8 ns t plh /t phl (clock to q) 74xx74 max 40 18 44 10.5 ns t plh /t phl 74xx163 typ 18 10 20 5 ns t plh /t phl (clock to q) 74xx163 max 27 17 52 10 ns conditions: (ls) v cc = 5 v, c l = 15 pf, 25 c; (als/hc/fact) v cc = 5 v, 10%, c l = 50 pf, typ values at 25 c, max values at 0 to 70 c for als, ?40 to +85 c for hc/fact. figure 1?8. logic family comparisons, cont?d
http://onsemi.com 15 section 2 ? circuit characteristics power dissipation one advantage to using cmos logic is its extremely low power consumption. during quiescent conditions, fact will consume several orders of magnitude less current than its bipolar counterparts. but dc power consumption is not the whole picture. any circuit will have ac power consumption, whether it is built with cmos or bipolar technologies. power consumption of a circuit can be calculated using the formula: p d = [(c l + c pd ) ? v cc ? v s ? f] + [i q ? v cc ] where p d = power dissipation (w) c l = load capacitance (farad) c pd = device power capacitance (farad) v cc = power supply (volt) v s = output voltage swing (volt) f= frequency of operation (hz) i q = quiescent current (amp) power consumption for f act is dependent on the supply voltage, frequency of operation, internal capacitance and load. v s will be v cc and i q can be considered negligible for cmos. therefore, the simplified formula for cmos is: p d = (c l + c pd ) v cc 2 f c pd values for cmos devices are calculated by measuring the power consumption of a device at two different frequencies. c pd is calculated in the following manner: 1. the power supply voltage is set to v cc = 5 vdc. 2. signal inputs are set up so that as many outputs as possible are switching, giving a worst-case situation per jedec c pd conditions (see section 3). 3. the power supply current is measured and recorded at input frequencies of 200 khz and 1 mhz. 4. the power dissipation capacitance is calculated by solving the two simultaneous equations p 1 = (c pd ? v cc 2 ? f 1 ) + (i cc ? v cc ) p 2 = (c pd ? v cc 2 ? f 2 ) + (i cc ? v cc ) giving c pd = (p 1 ? p 2 )/v cc 2 (f 1 ? f 2 ) or c pd = (i 1 ? i 2 )/v cc (f 1 ? f 2 ) where i 1 = supply current at f 1 = 200 khz. i 2 = supply current at f 2 = 1 mhz. on f act device data sheets, c pd is a typical value and is given either for the package or for the individual device function, if there is more than one (i.e., gates, flip-flops, etc.), within the package. mc74ac74 mc74ac74 mc74ac74 figure 1?9. power demonstration circuit schematic
http://onsemi.com 16 the circuit shown in figure 1?9 was used to compare the power consumption of fact versus als devices. tw o identical circuits were built on the same board and driven from the same input. in the circuit, the input signal was driven into four d-type flip-flops which act as divide-by-2 frequency dividers. the outputs from the flip-flops were connected to the inputs of a mc74ac38 figure 1?10. fact versus als circuit power decoder. this generated eight non-overlapping clock pulses on the outputs of the mc74ac38, which were then connected to an mc74ac04 inverter. the input frequency was then varied and the power consumption was measured. figure 1?10 illustrates the results of these measurements. below 40 mhz, the fact circuit dissipates much less power than the als version. it is interesting to note that when the frequency went to zero, the fact circuit?s power consumption also went to near zero; the als circuit continued to dissipate almost 100 mw. another advantage of f act is its capabilities above 40 mhz. at this frequency, the first 74als74 d-type flip-flop ceased to operate. once this occurred, the entire circuit stopped working and the power consumption fell to its quiescent value. the fact device, however, continued functioning beyond the limit of the frequency generator, which was 100 mhz. this graph shows two advantages of fact circuits (power and speed). fact logic delivers increased performance in addition to offering the power savings of cmos. refer to section 3 for test philosophies regarding power dissipation. specification derivation at first glance, the specifications for fact logic might appear to be widely spread, possibly indicating wide design margins are required. however, several effects are reflected in each specification. figures 1?1 1a through 1?11e illustrate how the data from the characterization of actual devices is transformed into the specifications that appear on the data sheet. this data is taken from the ?ac245. figure 1?11a shows the data taken (from one part) on a typical, single path, t phl from an to bn, over temperature at 5 v; there is negligible variation in the value of t phl . the next graph, figure 1?11b, depicts data taken on the same device; this set of curves represents the data on all paths a to b and b to a. the data on this plot indicates only a small variation for t phl . the graphs in figures 1?11a and 1?11b include data at 5 v; figure 1?11c shows the variation of delay times over the standard 5 0.5 v voltage range. note there is only a 6% variation in delay time due to voltage effects. now refer to figure 1?11d which illustrates the process effects on delay time. this graph indicates that the process effects contribute to the spread in specifications more than any other factor in that the effects of the theoretical process spread can increase or decrease specification times by 30%. because this 30% spread represents considerably more than 3 standard deviations, this guarantees an increase in the manufacturability and the quality level of f act product. to further ensure parts within specification will pass on testers at the limits of calibration, tester guardbands are incorporated. figure 1?11a. t phl , an to bn, single path
http://onsemi.com 17 figure 1?11b. t phl , a to b, all paths w ith voltage and process effects added (figure 1?11e), the full range of the specification can be seen. for reference, the data sheet values are shown on the graph. volts figure 1?11c. voltage effects on delay times figure 1?11d. fact process effects on delay times figure 1?11e. t phl , a to b, with voltage and process variation this linear behavior with temperature and voltage is typical of cmos. although the graphs are drawn for a specific device, other part types have very similar graphical representations. therefore, for performance-critical applications, where not all variables need to be taken into account at once, the user can narrow the specifications. for example, all parts in a critically timed subcircuit are together on a board, so it may be assumed the devices are at the same supply and temperature. the same reasoning can be applied to setup and hold times. consider the ?ac74. the setup time is 3 ns while the hold time is 0 ns. theoretically, if these numbers were violated, the device would malfunction; however, in actuality, the device probably will not malfunction. looking at the typical setup and hold times gives a better understanding of the device operation. at 25 c and 5 v, the setup time is 1.5 ns while the hold time is ?1.5 ns. they are the same; a positive setup time means the control signal to be valid before the clock edge, a positive hold time indicates the control signal will be held valid after the clock edge for the specified time, and a negative hold time means the control signal can transition before the clock edge. fact devices were designed to be as
http://onsemi.com 18 immune to metastability as possible. this is reflected in the typical specifications. the true ?critical? time where the input is actually sampled is extremely short: less than 50 ps. by applying the same reasoning as we did to the propagation delays to the setup and hold times, it becomes obvious that the spread from setup to hold time (3 ns worst-case) really covers devices across the entire process/ temperature/voltage spread. the real dif ference between the setup and hold times for any single device, at a specified temperature and voltage, is negligible. capacitive loading effects in addition to temperature and power supply effects, capacitive loading effects for loads greater than 50 pf should be taken into account for propagation delays of fact devices. minimum delay numbers may be determined from the table below. propagation delays are measured to the 50% point of the output waveform. parameter v oltage (v) unit parameter 3 4.5 5.5 unit t rise 31 22 19 ps/pf t fall 18 13 12.5 ps/pf t a = 25 c the two graphs following, figures 1?12 and 1?13, describe pr opagation delays on f act devices as affected by variations in power supply voltage (v cc ) and lumped load capacitance (c l ). figures 1?14 and 1?15 show the ef fects of lumped load capacitance on rise and fall times for fact devices. latch-up a major problem with cmos has been its sensitivity to latch-up, usually attributed to high parasitic gains and high input impedance. fact logic is guaranteed not to latch-up with dynamic currents of 100 ma forced into or out of the inputs or the outputs under worst case conditions (t a = 125 c and v cc = 5.5 vdc). at room temperature the parts can typically withstand dynamic currents of over 450 ma. for most designs, latch-up will not be a problem, but the designer should be aware of its causes and how to prevent it. figure 1?12. propagation delay versus v cc (?ac00) figure 1?13. propagation delay versus c l (?ac00) f act devices have been specifically designed to reduce the possibility of latch-up occurring; on semiconductor accomplished this by lowering the gain of the parasitic transistors, reducing substrate and p-well resistivity to increase external drive current required to cause a parasitic to turn on, and careful design and layout to minimize the substrate-injected current coupling to other circuit areas. figure 1?14. t rise versus capacitance
http://onsemi.com 19 figure 1?15. t fall versus capacitance figure 1?16. cmos inverter cross section with latch-up circuit schematic electrostatic discharge (esd) sensitivity f act circuits show excellent resistance to esd-type damage. fact logic is guaranteed to have 2000 v esd immunity on all inputs and outputs using human body model (1500 ohms, 100 pf). fact parts do not require any special handling procedures. however, normal handling precautions should be observed as in the case of any semi-conductor device. figure 1?17 shows the esd test circuit used in the sensitivity analysis for this specification. figure 1?18 is the pulse waveform required to perform the sensitivity test. the test procedure is as follows: five pulses, each of 2000 v, are applied to every combination of pins with a five second cool-down period between each pulse. the polarity is then reversed and the same procedure, pulse and pin combination used for an additional five discharges. continue until all pins have been tested. the voltage is increased and the testing procedure is again performed; this entire process is re p eat ed un til failure is detected. this is done to thoroughly evaluate all pins. ? figure 1?17. esd pulse waveform figure 1?18. esd test circuit ? ? ? ?
http://onsemi.com 20 section 3 ? ratings, specifications and waveforms specifying fact devices t raditionally, when a semiconductor manufacturer completed a new device for introduction, specifications were based on the characterization of just a few parts. while these specifications were appealing to the designer, they were often too tight and, over time, the ic manufacturers had difficulty producing devices to the original specs. this forced the manufacturer to relax circuit specifications to reflect the actual performance of the device. as a result, designers were required to review system designs to ensure the system would remain reliable with the new specifications. on semiconductor realized and understood the problems associated with characterizing devices too aggressively. to provide more realistic and manufacturable specs, on semiconductor devised a systematic and thorough process to generate specifications. devices are selected from multiple wafer lots to ensure process variations are taken into account. in addition, the process parameters are measured and compared to the known process limits. this method of characterizing parts more accurately represents the product across time, voltage, temperature and process rather than portraying the fastest possible device. f act circuits are therefore guaranteed to be manufacturable over time without the need to respecify timing. these specification guidelines allow designers to design systems more efficiently since the devices used will behave as documented. unspecified guardbands no longer need to be added by the designer to ensure system reliability. power dissipation ? test philosophy in an effort to reduce confusion about measuring c pd , a jedec standard test procedure (per jedec, appendix e) has been adopted which specifies the test setup for each type of device. this allows a device to be exercised in a consistent manner for the purpose of specification comparison. all device measurements are made with v cc = 5 v at 25 c, with 3-state outputs both enabled and disabled. gates ? switch one input. bias the remaining inputs such that the output switches. latches ? switch the enable and d inputs such that the latch toggles. flip-flops ? switch the clock pin while changing d (or bias j and k) such that the output(s) change each clock cycle. for parts with a common clock, exercise only one flip-flop. decoders ? switch one address pin which changes two outputs. multiplexers ? switch one address pin with the corresponding data inputs at opposite logic levels so that the output switches. counters ? switch the clock pin with other inputs biased such that the device counts. shift registers ? switch the clock pin with other inputs biased such that the device counts. t ransceivers ? switch one data input. for bidirectional devices enable only one direction. parity generator ? switch one input. priority encoders ? switch the lowest priority input. load capacitance ? each output which is switching should be loaded with the standard 50 pf. if the device is tested at a high enough frequency, the static supply current can be ignored. thus at 1 mhz, the following formula can be used to calculate c pd : c pd = i cc /(v cc ) (1 10 6 ) ? equivalent load capacitance ratings and specifications symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output source/sink current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c 1 absolute maximum ratings are those values beyond which damage to the device may occur. obviously the databook specifications sh ould be met, without exception to ensure that the system design is reliable over its power supply, temperature, output/input loading variables. on semiconductor does not recommend operation of fact circuits outside databook specifications.
http://onsemi.com 21 figure 1?19. absolute maximum ratings 1 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v v cc @ 3.0 v 150 t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v 40 ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v 25 tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v 10 ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v 8.0 ns/v t j junction temperature (pdip) 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ?24 ma i ol output current ? low 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. figure 1?20. recommended operating conditions
http://onsemi.com 22 dc characteristics for ?ac family devices 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 2.56 2.46 v ?12 ma 4.5 3.86 3.76 v i oh ?24 ma 5.5 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 0.36 0.44 v 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 24 ma i in maximum input 55 01 10 a v i =v cc gnd p leakage current 5.5 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 a v in =v cc or gnd q supply current 5.5 8 . 0 80 a v in = v cc or gnd * all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . dc characteristics for ?act family devices 74act 74act symbol parameter v cc (v) t a = 25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 3.86 3.76 v i oh ?24 ma 5.5 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih * all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
http://onsemi.com 23 dc characteristics for ?act family devices (continued) symbol conditions unit 74act 74act v cc (v) parameter symbol conditions unit t a = ?40 c to +85 c t a = 25 c v cc (v) parameter symbol conditions unit guaranteed limits typ v cc (v) parameter 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma i in maximum input 55 01 10 a v i =v cc gnd p leakage current 5.5 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1v i old ?minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 a v in =v cc or gnd q supply current 5.5 8 . 0 80 a v in = v cc or gnd * all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ? ? ? figure 1?21. ac tri-state loading circuit ac loading and waveforms loading circuit figure 1?21 shows the ac loading circuit used in characterizing and specifying propagation delays of all f act devices (?ac and ?act) unless otherwise specified in the data sheet of a specific device. the use of this load, differs somewhat from previous (hcmos) practice, provides more meaningful information and minimizes problems of instrumentation and customer correlation. in the past, +25 c propagation delays for ttl devices were specified with a load of 15 pf to ground; this required great care in building test jigs to minimize stray capacitance and implied the use of high impedance, high frequency scope probes. fast circuits changed to 50 pf of capacitance allowing more leeway in stray capacitance and also loading the device during rising or falling output transitions. this more closely resembles the inloading to be expected in average applications and thus gives the designer more useful delay figures. we have incorporated this scheme into the fact product line. the net effect of the change in ac load is to increase the average observed propagation delay by about 1 ns. the 500 ohm resistor to ground can be a high frequency passive probe for a sampling oscilloscope, which costs much less than the equivalent high impedance probe. alternately, the 500 ohm resistor to ground can simply be a 450 ohm resistor feeding into a 50 ohm coaxial cable leading to a sampling scope input connector, with the internal 50 ohm termination of the scope completing the path to ground. this is the preferred scheme for correlation. (see figure 1?21.) w ith this scheme there should be a matching cable from the device input pin to the other input of the sampling scope; this also serves as a 50 ohm termination for the pulse generator that supplies the input signal. shown in figure 1?21 is a second 500 ohm resistor from the device output to a switch. for most measurements this switch is open; it is closed for measuring one set of the enable/disable parameters (low-to-off and off-to-low) of a 3-state output. with the switch closed, the pair of 500 ohm resistors and the 2 v cc supply voltage establish a quiescent high level.
http://onsemi.com 24 ?acxx devices ?actxx devices figure 1?22a. test input signal levels figure 1?22b. test input signal levels t est conditions figure 1?22a and 1?22b describe the input signal voltage levels to be used when testing fact circuits. the ac test conditions follow industry convention requiring v in to range from 0 v for a logic low to 3 v for a logic high for ?act devices and 0 v to v cc for ?ac devices. the dc parameters are normally tested with v in at guaranteed input levels, that is v ih to v il (see data tables for details). care must be taken to adequately decouple these high performance parts and to protect the test signals from electrical noise. in an electrically noisy environment, (e.g., a tester and handler not specifically designed for high speed work), dc input levels may need to be adjusted to increase the noise margin to allow for the extra noise in the tester which would not be seen in a system. noise immunity testing is performed by raising v in to the nominal supply voltage of 5 v then dropping to a level corresponding to v ih characteristics, and then raising again to the 5 v level. noise tests can also be performed on the v il characteristics by raising v in from 0 v to v il , then returning to 0 v. both v ih and v il noise immunity tests
http://onsemi.com 25 should not induce a switch condition on the appropriate outputs of the fact device. good high frequency wiring practices should be used in constructing test jigs. leads on the load capacitor should be as short as possible to minimize ripples on the output wave form transitions and to minimize undershoot. generous ground me tal (preferably a ground plane) should be used for the same reasons. a v cc bypass capacitor should be provided at the test socket, also with minimum lead lengths. rise and fall times input signals should have rise and fall times of 3 ns and signal swing of 0 v to 3.0 v v cc for ?act devices or 0 v to v cc for ?ac devices. rise and fall times less than or equal to 1 ns should be used for testing f max or pulse widths. cmos devices, including 4000 series cmos, hc, hct and f act families, tend to oscillate when the input rise and fall times become lengthy. as a direct result of its increased performance, fact devices can be more sensitive to slow input rise and fall times than other lower performance technologies. it is important to understand why this oscillation occurs. consider the outputs, where the problem is initiated. usually, cmos outputs drive capacitive loads with low dc leakage. when the output changes from a high level to a low level, or from a low level to a high level, this capacitance has to be charged or discharged. with the present high performance technologies, this charging or discharging takes place in a very short time, typically 2?3 ns. the requirement to charge or discharge the capacitive loads quickly creates a condition where the instantaneous current change through the output structure is quite high. a voltage is generated across the v cc or ground leads inside the package due to the inductance of these leads. the internal ground of the chip will change in reference to the outside world because of this induced voltage. consider the input. if the internal ground changes, the input volt age level appears to change to the dut. if the input rise time is slow enough, its level might still be in the device threshold region, or very close to it, when the output switches. if the internally-induced voltage is large enough, it is possible to shift the threshold region enough so that it re-crosses the input level. if the gain of the device is sufficient and the input rise or fall time is slow enough, then the device may go into oscillation. as device propagation delays become shorter , the inputs will have less time to rise or fall through the threshold region. as device gains increase, the outputs will swing more, creating more induced voltage. instantaneous current change will be greater as outputs become quicker, generating more induced voltage. package-related causes of output oscillation are not entirely to blame for problems with input rise and fall time measurements. all testers have v cc and ground leads with a finite inductance. this inductance needs to be added to the inductance in the package to determine the overall voltage which will be induced when the outputs change. as the reference for the input signals moves further away from the pin under test, the test will be more susceptible to problems caused by the inductance of the leads and stray noise. any noise on the input signal will also cause problems. with f act logic having gains as high as 100, it merely takes a 50 mv change in the input to generate a full 5 v swing on the output. *v mi = 50% v cc for ?ac devices; 1.5 v for ?act devices v mo = 50% for ?ac/?act devices figure 1?23. waveform for inverting and non-inverting functions figure 1?24. propagational delay, pulse width and t rec waveforms
http://onsemi.com 26 enable and disable times figure 1?25 and 1?26 show that the disable times are measured at the point where the output voltage has risen or fallen by 10% from the voltage rail level (i.e., ground for t plz or v cc for t phz ). this change enhances the repeatability of measurements, reduces test times, and gives the system designer more realistic delay times to use in calculating mini mum cycle times. since the high impedance state rising or falling waveform is rc-controlled, the first 10% of change is more linear and is less susceptible to external influences. more importantly, perhaps from the system designer?s point of view, a change in voltage of 10% is adequate to ensure that a device output has turned off. measuring to a larger change in voltage merely exaggerates the apparent disable time and thus penalizes system performance since the designer must use the enable and disable times to devise worst case timing signals to ensure that the output of one device is disabled before that of another device is enabled. propagation delay, f max , set, hold, and recovery times a 1 mhz square wave is recommended for most propagation delay tests. the repetition rate must necessarily be increased for testing f max . a 50% duty cycle should always be used when testing f max . t wo pulse generators are usually required for testing such parameters as setup time (t s ), hold time (t h ), recovery time (t rec ) shown in figure 1?27. electrostatic discharge precautions should be taken to prevent damage to devices by electrostatic discharge. static charge tends to accumulate on insulated surfaces such as synthetic fabrics or carpeting, plastic sh eets, trays, foam, tubes or bags, and on ungrounded electrical tools or appliances. the problem is much worse in a dry atmosphere. in general, it is recommended that individuals take the precaution of touching a known ground before handling devices. to effectively avoid electrostatic damage to fact devices, it is recommended that individuals wear a grounded wrist strap when handling devices. more often, handling equipment, which is not properly grounded, causes damage to parts. ensure that all plastic parts of the tester, which are near the device, are conductive and connected to ground. figure 1?25. setup time, hold time and recovery t ime figure 1?26. 3-state output high enable and disable times figure 1?27. 3-state output low enable and disable times *v mi = 50% v cc for ?ac devices; 1.5 v for ?act devices v mo = 50% v cc for ?ac/?act devices
http://onsemi.com 27 section 4 ? design considerations t oday?s system designer is faced with the problem of keeping ahead when addressing system performance and reliability. on semiconductor?s advanced cmos helps designers achieve these goals. f act logic was designed to alleviate many of the drawbacks that are common to current technology logic circuits. fact logic combines the low static power consumption and the high noise margins of cmos with a high fan-out, low input loading and a 50 ohm transmission line drive capability (comparable to on semiconductor?s f ast bipolar technology family) to offer a complete family of sub 2-micron ssi and msi devices. performance features such as advanced schottky speeds at cmos power levels, advanced schottky drive, excellent noise, esd and latch-up immunity are characteristics that designers of state-of-the-art systems require. fact logic answers all of these concerns in one family of products. to fully utilize the advantages provided by fact, the system designer should have an understanding of the flexibility as well as the trade-offs of cmos design. the following section discusses common design concerns relative to the performance and requirements of fact. there are six items of interest which need to be evaluated when implementing fact devices in new designs: ? thermal management ? circuit performance and long- term circuit reliability are affected by die temperature. ? interfacing ? interboard and technology interfaces, battery backup and power down or live insert/extract systems require some special thought. ? t ransmission line driving ? fact has line driving capabilities superior to all cmos families and most ttl families. ? noise effects ? as edge rates increase, the probability of crosstalk and ground bounce problems increases. the enhanced noise immunity and high threshold levels improve fact?s resistance to crosstalk problems. ? board layout ? prudent board layout will ensure that most noise effects are minimized. ? power supplies and decoupling ? maximize ground and v cc traces to keep v cc /ground impedance as low as possible; full ground/v cc planes are best. decouple any device driving a transmission line; otherwise add one capacitor for every package. thermal management circuit performance and long-term circuit reliability are affected by die t emperature. nor mally, both are improved by keeping the ic junction temperatures low. electrical power dissipated in any integrated circuit is a source of heat. this heat source increases the temperature of the die relative to some reference point, normally the ambient temperature of 25 c in still air. the temperature increase, then, depends on the amount of power dissipated in the circuit and on the net thermal resistance between the heat source and the reference point. see section 2 for calculation of fact power consumption. the temperature at the junction is a function of the packaging and mounting system?s ability to remove heat generated in the circuit ? from the junction region to the ambient environment. the basic formula for converting power dissipation to estimated junction temperature is: t j = t a + p d ( jc + ca ) (1) or t j = t a + p d ( ja ) (2) where t j = maximum junction temperature t a = maximum ambient temperature p d = calculated maximum power dissipation including effects of external loads (see power dissipation in section iii). jc = average thermal resistance, junction to case ca = average thermal resistance, case to ambient ja = average thermal resistance, junction to ambient this on semiconductor recommended formula has been approved by radc and desc for calculating a ?practical? maximum operating junction temperature for mil-m-38510 (jan) devices. only two terms on the right side of equation (1) can be varied by the user ? the ambient temperature, and the device case-to-ambient thermal resistance, ca . (to some extent the device power dissipation can also be controlled, but under recommended use the v cc supply and loading dictate a fixed power dissipation.) both system air flow and the package mounting technique affect the ca thermal resistance term. jc is essentially independent of air flow and external mounting method, but is sensitive to package material, die bonding method, and die area.
http://onsemi.com 28 thermal resistance in still air package description no body body body die die area flag area jc ( c/watt) n o. leads b o d y style b o d y material b o d y w l di e bonds di e a rea (sq. mils) fl ag a rea (sg. mils) a vg. max. 14 dil epoxy 1/4 3/4 epoxy 4096 6,400 38 61 16 dil epoxy 1/4 3/4 epoxy 4096 12,100 34 54 20 dil epoxy 0.35 0.35 epoxy 4096 14,400 n/a n/a notes: 1. all plastic packages use copper lead frames. 2. body style dil is ?dual-in-line.? 3. standard mounting method: dual-in-line socket or p/c board with no contact between bottom of package and socket or p/c board . figure 1?28. thermal resistance values for standard i/c packages for applications where the case is held at essentially a fixed temperature by mounting on a large or temperature- controlled heat sink, the estimated junction temperature is calculated by: t j = t c + p d ( jc ) (3) where t c = maximum case temperature and the other parameters are as previously defined. the maximum and average jc resistance values for standard ic packages are given in figure 1?28. in figure 1?29, this basic data is converted into graphs showing the maximum power dissipation allowable at various ambient temperatures (still air) for circuits mounted in the different packages, taking into account the maximum permissible operating junction temperature for long term life ( 100,000 hours for ceramic packages). figure 1?29. ambient temperature derating curves (plastic dual-in-line package test environment) air flow the effect of air flow over the packages on ja (due to a decrease in ca ) reduces the temperature rise of the package, therefore permitting a corresponding increase in power dissipation without exceeding the maximum permissible operating junction temperature. even though different device types mounted on a printed circuit board may each have dif ferent power dissipations, all will have the same input and output levels provided that each is subject to identical air flow and the same ambient air temperature. this eases design, since the only change in levels between devices is due to the increase in ambient temperatures as the air passes over the devices, or differences in ambient temperature between two devices. the majority of users employ some form of air-flow cooling. as air passes over each device on a printed circuit board, it absorbs heat from each package. this heat gradient from the first package to the last package is a function of the air flow rate and individual package dissipations. figure 1?30 provides gradient data at power levels of 200 mw, 250 mw, 300 mw, and 400 mw with an air flow rate of 500 ifpm. these figures show the proportionate increase in the junction temperature of each dual in-line package as the air passes over each device. for higher rates of air flow the change in junction temperature from package to package down the airstream will be lower due to greater cooling. power dissipation (mw) junction temperature gradient ( c/package) 200 0.4 250 0.5 300 0.63 400 0.88 devices mounted on 0.062 pc board with z axis spacing of 0.5 . air flow is 500 lfpm along the z axis. figure 1?30. thermal gradient of junction t emperature (16-pin dual-in-line package) optimizing the long term reliability of plastic packages t odays plastic integrated circuit packages are as reliable as ceramic packages under most environmental conditions. however when the ultimate in system reliability is required, thermal management must be considered as a prime system design goal. modern plastic package assembly technology utilizes gold wire bonded to aluminum bonding pads throughout the electronics industry. when exposed to high temperatures for protracted periods of time an intermetallic compound can
http://onsemi.com 29 form in the bond area resulting in high impedance contacts and degradation of device performance. since the formation of intermetallic compounds is directly related to device junction temperature, it is incumbent on the designer to determine that the device junction temperatures are consistent with system reliability goals. predicting bond failure time based on the results of almost ten (10) years of +125 c operating life testi ng, a special arrhenius equation has been developed to show the relationship between junction temperature and reliability. (1) t = (6.376 10 ? 9 )e 1 1554.267 273.15 + t j where: t = time in hours to 0.1% bond failure (1 failure per 1,000 bonds). t j = device junction temperature, c. and: (2) t j = t a + p d ja = t a + ? t j where: t j = device junction temperature, c. t a = ambient temperature, c. p d = device power dissipation in watts. ja = device thermal resistance, junction to air, c/watt. ? t j = increase in junction temperature due to on-chip power dissipation. figure 1?31 shows the relationship between junction temperature, and continuous operating time to 0.1% bond failure, (1 failure per 1,000 bonds). junction t emperature c t ime, hours t ime, years 80 1,032,200 1 17.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 figure 1?31. device junction temperature versus ti me to 0.1% bond failures figure 1?31 is graphically illustrated in figure 1?32 which shows that the reliability for plastic and ceramic devices is the same until elevated junction temperatures induce intermetallic failures in plastic devices. early and mid-life failure rates of plastic devices are not effected by this intermetallic mechanism. figure 1?32. failure rate versus time junction temperature procedure after the desired system failure rate has been established for failure mechanisms other than intermetallics, each device in the system should be evaluated for maximum junction temperature. knowing the maximum junction temperature, refer to figure 1?31 or equation 1 to determine the continuous operating time required to 0.1% bond failures due to intermetallic formation. at this time, system reliability departs from the desired value as indicated in figure 1?32. air flow is one method of thermal management which should be considered for system l ongevity. other commonly used methods include heat sinks for higher powered devices, refrigerated air flow and lower density board stuffing. since ca is entirely dependent on the application, it is the responsibility of the designer to determine its value. this can be achieved by various techniques including simulation, modeling, actual measurement, etc. the material presented here emphasizes the need to consider thermal management as an integral part of system design and also the tools to determine if the management methods being considered are adequate to produce the desired system reliability. interfacing f act devices have outputs which combine balanced cmos outputs with high current line driving capability. each standard output is guaranteed to source or sink 24 ma of current at worst case conditions. this allows fact circuits to drive more loads than standard advanced schottky parts; fact can directly drive als, as, ls, hc and hct devices.
http://onsemi.com 30 figure 1?33. interfacing fact to nmos, cmos and ttl f act devices can be directly driven by both nmos and cmos families, as shown in figure 1?33, operating at the same rail potential without special considerations. this is possible due to the low input loading of fact product, guaranteed to be less than 1 a per input. some older technologies, including all existing ttl families, will not be able to drive f act circuits directly; this is due to inadequate high level capability, which is guaranteed to 2.4 v. there are two simple approaches to the ttl-to-fact interface problem. a ttl-to-cmos converter can be constr ucted employi ng a resistor pull-up to v cc of approximately 4.7 k ohms, which is depicted in figure 1?34. the correct high level is seen by the cmos device while not loading down the ttl driver. figure 1?34. v ih pull-up on ttl outputs unfortunately, there will be designs where including a pull-up resistor will not be acceptable. in these cases, such as a terminated ttl bus, on semiconductor has designed devices which offer thresholds that are ttl-compatible (figure 1?35). these interfaces tend to be slightly slower than their cmos-level counterparts due to an extra buffer stage required for level conversion. figure 1?35. ttl interfacing to ?act ecl devices cannot directly drive fact devices. in te rf aci ng f act-to-ecl can be accomplished by using ttl-to-ecl translators and 10125 ecl-to-ttl translators in addition to following the same rules on the ttl outputs to cmos inputs (i.e., a resistor pull-up to v cc of approximately 4.7 k ohms). the translation can also be accomplished by a resistive network. a three-resistor interface between fact and ecl logic is illustrated in figure 1?36a. figure 1?36b and 1?36c show the translation from ecl-to-fact, which is somewhat more complicated. these two examples offer some possible interfaces between ecl and fact logic. ? ? ? figure 1?36a. resistive fact-to-ecl translation figure 1-36b. single-ended ecl-to-?ac circuit figure 1-36c. differential output ecl-to-?ac circuit it should be understood that for fact, as with other cmos technologies, input levels that are between specified input values will cause both transistors in the cmos structure to be conducting. this will cause a low resistive path from the supply rail to ground, increasing the power consumption by several orders of magnitude. it is important
http://onsemi.com 31 that cmos inputs are always driven as close as possible to the rail. figure 1?37. crystal oscillator circuit implemented with fact ?ac00 line driving w ith the available high-speed logic families, designers can reach new heights in system performance. yet, these faster devices require a closer look at transmission line effects. although all circuit conductors have transmission line properties, these characteristics become significant when the edge rates of the drivers are equal to or less than three times the propagation delay of the line. significant transmission line properties may be exhibited in an example where devices have edge rates of 3 ns and lines of 8 inches or greater, assuming propagation delays of 1.7 ns/ft for an unloaded printed circuit trace. of the many properties of transmission lines, two are of major interest to the system designer: z oe , the effective equivalent impedance of the line, and t pde , the effective propagation delay down the line. it should be noted that the intrinsic values of line impedance and propagation delay, z o and t pd , are geometry-dependent. once the intrinsic values are known, the effects of gate loading can be calculated. the loaded values for z oe and t pde can be calculated with: z oe z o 1 c t c l t pde t pd 1 c t c l where c i = intrinsic line capacitance and c t = additional capacitance due to gate loading. the formulas indicate that the loading of lines decreases the effective impedance of the line and increases the propagation delay. lines that have a propagation delay greater than one third the rise time of the signal driver should be evaluated for transmission line ef fects. when performing transmission line analysis on a bus, only the longest, most heavily loaded and the shortest, least loaded lines need to be analyzed. a ll lines in a bus should be terminated equally; if one line requires termination, all lines in the bus should be terminated. this will ensure similar signals on all of the lines. there are several termination schemes which may be used. included are series, parallel, ac parallel and thevenin terminations. ac parallel and series terminations are the most useful for low power applications since they do not consume any dc power. parallel and thevenin terminations experience high dc power consumption. t ermination schemes a: no termination b: series termination c: parallel termination figure 1?38. termination schemes d: ac parallel termination e: thevenin termination series terminations series terminations are most useful in high-speed applications where most of the loads are at the far end of the line. loads that are between the driver and the end of the line will receive a two-step waveform. the first wave will be the incident wave. the amplitude is dependent upon the output
http://onsemi.com 32 impedance of the driver, the value of the series resistor and the impedance of the line according to the formula v w = v cc ? z oe /(z oe + r s + z s ) the amplitude will be one-half the voltage swing if r s (the series resistor) plus the output impedance (z s ) of the driver is equal to the line impedance. the second step of the waveform is the reflection from the end of the line and will have an amplitude equal to that of the first step. all devices on the line will receive a valid level only after the wave has propagated down the line and returned to the driver. therefore, all inputs will see the full voltage swing within two times the delay of the line. parallel termination parallel terminations are not generally recommended for cmos circuits due to their power consumption, which can exceed the power consumption of the logic itself. the power consumption of parallel terminations is a function of the resistor value and the duty cycle of the signal. in addition, parallel termination tends to bias the output levels of the driver towards either v cc or ground. while this feature is not desirable for driving cmos inputs, it can be useful for driving ttl inputs. ac parallel termination ac parallel terminations work well for applications where the delays caused by series terminations are unacceptable. the effects of ac parallel terminations are similar to the effects of standard parallel terminations. the major dif ference is that the capacitor blocks any dc current path and helps to reduce power consumption. thevenin termination thevenin terminations are also not generally r eco mme nde d due to their power consumption. like parallel termination, a dc path to ground is created by the terminating resistors. the power consumption of a thevenin termination, though, will generally not be a function of the signal duty cycle. thevenin terminations are more applicable for driving cmos inputs because they do not bias the output levels as paralleled terminations do. it should be noted that lines with thevenin terminations should not be left floating since this will cause the input levels to float between v cc or ground, increasing power consumption. f act circuits have been designed to drive 50 ohm transmission lines over the full commercial temperature range. this is guaranteed by the fact family?s specified dynamic drive capability of 86 ma sink and 75 ma source current. this ensures incident wave switching on 50 ohm transmission lines and is consistent with the 3 ns rated edge transition time. f act devices also feature balanced output totem pole structures to allow equal source and sink current capability. this gives rise to balanced edge rates and equal rise and fall times. balanced drive capability and transition times eliminate both the need to calculate two dif ferent delay times for each signal path and the requirement to correct signal polarity for the shortest delay time. f act product inputs have been created to take full advantage of high output levels to deliver the maximum noise immunity to the system designer. v ih and v il are specified at 70% and 30% of v cc respectively. the corresponding ou tput levels, v oh and v ol , are specified to be within 0.1 v of the rails, of which the output sourcing or sinking 20 a or less. these noise margins are outlined in figure 1?39. figure 1?39. input threshold cmos bus loading cmos logic devices have clamp diodes from all inputs and outputs to v cc and ground. w hile these diodes increase system reliability by damping out undershoot and overshoot noise, they can cause problems if power is lost. figure 1?40 exemplifies the situation when power is removed. any input driven above the v cc pin will forward-bias the clamp diode. current can then flow into the device, and out v cc or any output that is high. depending upon the system, this current, i in , can be quite high, and may not allow the bus voltage to reach a valid high state. one possible solution to eliminate this problem is to place a series resistor in the line. figure 1?40. noise effects ?? ?? ?? ?? noise effects f act offers the best noise immunity of any competing technology available today. with input thresholds specified at 30% and 70% of v cc and outputs that drive to within 100 mv of the rails, fact devices offer noise margins approaching 30% of v cc . at 5 v v cc , fact?s specified input and output levels give almost 1.5 v of noise margin for both ground- and v cc -born noise. with realistic input thresholds closer to 50% of v cc , the actual margins approach 2.5 v. however, even the most advanced technology cannot alone eliminate noise problems. good circuit board layout techniques are essential to take full advantage of the superior performance of fact circuits.
http://onsemi.com 33 w ell-designed circuit boards also help eliminate manufacturing and testing problems. another recommended practice is to segment the board into a high-speed area, a medium-speed area and a low- speed area. the circuit areas with high current requirements (i.e., buffer circu its and high-speed logic) should be as close to the power supplies as possible; low-speed circuit areas can be furthest away. decoupling capacitors should be adjacent to all buffer chips; they should be distributed throughout the logic: one capacitor per chip. t ransmission lines need to be terminated to keep reflections minimal. to minimize crosstalk, long signal lines should not be close together. crosstalk the problem of crosstalk and how to deal with it is becoming more important as system performance and board densities increase. crosstalk is the capacitive coupling of signals from one line to another. the amplitude of the noise generated on the inactive line is directly related to the edge rates of the signal on the active line, the proximity of the two lines and the distance that the two lines are adjacent. crosstalk has two basic causes. forward crosstalk, figure 1?41a, is caused by the wavefront propagating down the printed circuit trace at two different velocities. this difference in velocities is due to the difference in the dielectric constants of air ( r = 1) and epoxy glass ( r = 4.7). as the wave propagates down the trace, this difference in velocities will cause one edge to reach the end before the other. this delay is the cause of forward crosstalk; it increases with longer trace length, so consequently the magnitude of forward crosstalk will increase with distance. reverse crosstalk, figure 1?41b, is caused by the mutual inductance and capacitance between the lines which is a transformer action. reverse crosstalk increases linearly with distance up to a critical length. this critical length is the distance that the signal can travel during its rise or fall time. although crosstalk cannot be totally eliminated, there are some design techniques that can reduce system problems resulting from crosstalk. fact?s industry-leading noise margins make systems immune to crosstalk-related problems easier to design. fact?s ac noise margins, shown in figure 1?42a and 1?42b, exemplify the outstanding immunity to everyday noise which can affect system reliability. figure 1?41a. forward crosstalk on pcb traces voltage (v) key vertical scale horizontal scale active driver 1.0 v/div 50 ns/div fwd crosstalk 0.2 v/div 5.0 ns/div active receiver 1.0 v/div 5.0 ns/div this figure shows traces taken on a test fixture designed to exaggerate the amplitude of crosstalk pulses. voltage (v) figure 1-41b. reverse crosstalk on pcb traces key vertical scale horizontal scale active driver 1.0 v/div 50 ns/div fwd crosstalk 0.2 v/div 5.0 ns/div active receiver 1.0 v/div 5.0 ns/div this figure shows traces taken on a test fixture designed to exaggerate the amplitude of crosstalk pulses.
http://onsemi.com 34 figure 1?42a. high noise margin figure 1-42b. low noise margin w ith over 2 v of noise margins, the fact family offers better noise rejection than any other comparable technology. in any design, the distance that lines run adjacent to each other should be kept as short as possible. the best situation is when the lines are perpendicular to each other. for those situations where lines must run parallel, the effects of crosstalk can be minimized by line termination. t erminating a line in its characteristic impedance reduces the amplitude of an initial crosstalk pulse by 50%. t erminating the line will also reduce the amount of ringing. crosstalk problems can also be reduced by moving lines further apart or by inserting ground lines or planes between them. figure 1?43. effects of termination on crosstalk ground bounce ground bounce occurs as a result of the intrinsic characteristics of the leadframes and bondwires of the packages used to house cmos devices. as edge rates and drive capability increase in advanced logic families, the effects of these intrinsic electrical characteristics become more pronounced. figure 1?44a shows a simple circuit model for a device in a leadframe driving a standard test load. the inductor l1 represents the parasitic inductance in the ground lead of the package; inductor l2 represents the parasitic inductance in the power lead of the package; inductor l3 represents the parasitic inductance in the output lead of the package; the resistor r1 represents the output impedance of the device output, and the capacitor and resistor c l and r l represent the standard test load on the output of the device. figure 1?44a. output model i figure 1-44b. output voltage figure 1-44c. output current figure 1-44d. inductor voltage
http://onsemi.com 35 the three waveforms shown in figure 1?44b, c and d, depict how ground bounce is generated. the first waveform shows the voltage (v) across the load as it is switched from a logic high to a logic low. the output slew rate is dependent upon the characteristics of the output transistor, the inductors l1 and l3, and c l , the load capacitance. the second waveform shows the current that is generated as the capacitor discharges [i = c l ? dv/dt]. the third waveform shows the voltage that is induced across the inductance in the ground lead due to the changing currents [v gb = ?l ? (di/dt)]. there are many factors which affect the amplitude of the ground bounce. included are: ? number of outputs switching simultaneously: more outputs results in more ground bounce. ? t ype of output load: capacitive loads generate two to three times more ground bounce than typical system traces. increasing the capacitive load to approximately 60?70 pf increases ground bounce. beyond 70 pf, ground bounce drops off due to the filtering effect of the load. moving the load away from the output reduces the ground bounce. ? location of the output pin: outputs closer to the ground pin exhibit less ground bounce than those further away. ? v oltage: lowering v cc reduces ground bounce. ? t est fixtures: standard test fixtures generate 30 to 50% more ground bounce than a typical system since they use capacitive loads which both increase the ac load and form lcr tank circuits that oscillate. ground bounce produces several symptoms: ? altered device states. fact logic does not exhibit this symptom. ? propagation delay degradation. fact devices are characterized not to degrade more than 250 ps per additional output switching. ? undershoot on active outputs. the worst-case undershoot will be approximately equal to the worst-case quiet output noise. ? quiet output noise. fact logic?s worst-case quiet output noise has been measured to be approximately 500-1100 mv in actual system applications. observing either one of the following rules is sufficient to avoid running into any of the problems associated with ground bounce: first , use caution when driving asynchronous ttl-level inputs from cmos octal outputs, or second , use caution when running control lines (set, reset, load, clock, chip select) which are glitch-sensitive through the same devices that drive data or address lines. when it is not possible to avoid the above conditions, there are simple precautions available which can minimize ground bounce noise. these are: ? locate these outputs as close to the ground pin as possible. ? use the lowest v cc possible or separate the power supplies. ? use board design practices which reduce any additive noise sources, such as crosstalk, reflections, etc. design rules the set of design rules listed below are recommended to ensure reliable system operation by providing the optimum power supply connection to the devices. most designers will recognize t hese guidelines as those they have employed with advanced bipolar logic families. ? use multi-layer boards with v cc and ground planes, with the device power pins soldered directly to the planes to insure the lowest power line impedances possible. ? use decoupling capacitors for every device, usually 0. 1 f should be adequate. these capacitors should be located as close to the ground pin as possible. ? do not use sockets or wirewrap boards whenever possible. ? do not connect capacitors from the outputs directly to ground. figure 1?45. power distribution impedances ? ? ? ? ?
http://onsemi.com 36 decoupling requirements on semiconductor advanced cmos, as with other high- performance, high-drive logic families, has special decoupling and printed circuit board layout requirements. adhering to these requirements will ensure the maximum advantages are gained with fact products. local high frequency decoupling is required to supply power to the chip when it is transitioning from a low to a high value. this power is necessary to charge the load capacitance or drive a line impedance. figure 1?45 displays various v cc and ground layout schemes along with associated impedances. for most power distribution networks, the typical im pe da nc e is between 50 and 100 ohms. this impedance appears in series with the load impedance and will cause a droop in the v cc at the part. this limits the available voltage swing at the local node, unless some form of decoupling is used. this drooping of rails will cause the rise and fall times to become elongated. consider the example described in figure 1?46 to calculate the amount of decoupling necessary. this circuit utilizes an ?ac240 driving a 100 ohm bus from a point somewhere in the middle. ? w orst-case octal drain = 8 94 ma = 0.75 amp. figure 1?46. octal buffer driving a 100 ohm bus buffer output sees net 50 ? load. 50 ? load line on i oh ?v oh characteristic shows low-to-high step of approx. 4.8 v being in the middle of the bus, the driver will see two 100 ohm loads in parallel, or an effective impedance of 50 ohms. to switch the line from rail to rail, a drive of 94 ma is needed; more than 750 ma will be required if all eight lines switch at once. this instantaneou s current requirement will generate a voltage across the impedance of the power lines, causing the actual v cc at the chip to droop. this droop limits the voltage swing available to the driver . the net effect of the voltage droop will lengthen device rise and fall times and slow system operation. a local decoupling capacitor is required to act as a low impedance supply for the driver chip during high current conditions. it will maintain the voltage within acceptable limits and keep rise and fall times to a minimum. the necessary values for decoupling capacitors can be calculated with the formula given in figure 1?47. in this example, if the v cc droop is to be kept below 0.1 v and the edge rate equals 4 ns, a 0.03 f capacitor is needed. it is good practice to distribute decoupling capacitors evenly through the logic, placing one capacitor for every package. capacitor types decoupling capacitors need to be of the high k ceramic type wi th low equivalent series resistance (esr), consisting primarily of series inductance and series resistance. capacitors using 5zu dielectric have suitable properties and make a good choice for decoupling capacitors; they offer minimum cost and effective performance. figure 1?47. formula for calculating decoupling capacitors ? ? ? ? ?
http://onsemi.com 37 ttl-compatible cmos designs require delta i cc consideration the fact product line is comprised of two types of advanced cmos circuits: ?ac and ?act devices. ?act indicates an advanced cmos device with ttl-type input thresholds for direct replacement of ls and als circuits. as this ?act series is used to replace ttl, the delta i cct specification must be considered; this spec may be confusing and misleading to the engineer unfamiliar with cmos. it is important to understand the concept of delta i cct and how to use it with a design. first, consider where delta i cct initiates. most cmos input structures are of the totem pole type with an n-channel transistor in a series with a p-channel transistor as illustrated below. figure 1?48. cmos input structure ??? ??? ??? these two transistors can be modeled as variable resistors with resi stances varying according to the input voltage. the resistance of an on transistor is approximately 50 ohms while the resistance of an off transistor is generally greater than 5 mohm. when the input to this structure is at either ground or v cc , one transistor will be on and one will be off. the total series resistance of this pair will be the combination of the two individual resistances, greater than 1 a. when the input is between ground and v cc , the resistance of the on transistor will increase while the resistance of the off transistor will decrease. the net resistance will drop due to the much larger value of the off resistance. the total series resistance can be as low as 600 ohms. this reduction in series resistance of the input structure will cause a corresponding increase in i cc as current flows through the input structure. the following graph d epicts typical i cc variance with input voltage for an ?act device. figure 1?49. i cc versus input voltage for ?act devices the delta i cc specification is the increase in i cc . for each input at v cc ?2.1 v, the delta i cc value should be added to the quiescent supply current to arrive at the circuit?s worst-case static i cc value. fortunately, there are several factors which tend to reduce the increase in i cc per input. most ttl devices will be able to drive fact inputs well beyond the ttl output specification due to fact?s low input loading in a typical system. fast logic outputs can drive ?act-type inputs down to 200 mv and up to 3.5 v. additionally, the typical i cc increase per input will be less than the specified limit. as shown in the graph above, the i cc increase at v cc ?2.1 v is less than 200 a in the typical system. experiments have shown that the i cc of an ?act240 series device typically increases onl y 200 a when all of the inputs are connected to a fast device instead of ground or v cc . it is important when designing with fact, as with any ttl-compatible cmos technology, that the delta i cc specification be considered. designers should be aware of the spec?s significance and that the data book specification is a worst-case value; most systems will see values that are much less.
http://onsemi.com 38 t esting advanced cmos devices with i/o pins there are more and more cmos families becoming available which can replace ttl circuits. although testing these new cmos units with programs and fixtures which were developed for bipolar devices will yield acceptable results most of the time, there are some cases where this approach will cause the test engineer problems. such is the case with parts that have a bidirectional pin, exemplified by the ?245 octal transceiver. if the proper testing methods are not followed, these types of parts may not pass those tests for i cc and input leakage currents, even when there is no fault with the devices. cmos circuits, unlike their bipolar counterparts, have static i cc specification orders of magnitude less than standard load currents. most cmos i cc specifications are usually less than 100 a. when conducting an i cc test, greater care must be taken so that other currents will not mask the actual i cc of the device. these currents are usually sourced from the inputs and outputs. since the static i cc requirements of cmos devices are so low, output load currents must be prevented from masking the current load of the device during an i cc test. even a standard 500 ohm load resistor will sink 10 ma at 5 v, which is more than twice the i cc level being tested. thus, most manufacturers will specify that all outputs must be unloaded during i cc tests. another area of concern is identified when considering the inputs of the device. when the input is in the transition region, i cc can be several orders of magnitude greater than the specification. when the input voltage is in the transition region, both the n-channel and the p-channel transistors in the input totem-pole structure will be slightly on, and a conduction is created from v cc to ground. this conduction path leads to the increased i cc current seen in the i cc vs. v in curve. when the input is at either rail, the input structure no longer conducts. most i cc testing is done with all of the inputs tied to either v cc or ground. if the inputs are allowed to float, they will typically float to the middle of the transition region, and the input structure will conduct an order of magnitude more current than the actual i cc of the device under test which is being measured by the tester. figure 1?50. i cc versus i in when testing the i cc of a cmos ?245, problems can arise depending upon how the test is conducted. note the structure of the ?245?s i/o pins illustrated below. figure 1?51. ?245 i/o structure each i/o pin is connected to both an input device and an output device. the pin can be viewed as having three states: input, output and output disabled. however, only two states actually exist.
http://onsemi.com 39 figure 1?52. i/o pin internal structure the pin is either an input or an output. when testing the i cc of the device, the pins selected as outputs by the t/r signal must either be enabled and left open or be disabled and tied to either rail. if the output device is disabled and allowed to float, the input device will also float, and an excessive amount of current will flow from v cc to ground. a simple rule to follow is to treat any output which is disabled as an input. this will help insure the integrity of an i cc test. another area which might precipitate problems is the measurement of the leakages on i/o pins. the i/o pin internal structure is depicted below. the pin is internally connected to both an input device and an output device; the limit for a leakage test must be the combined i in specification of the input and the i oz specification of the output. for fact devices, i in is specified at 1 a while i oz is specified at 5 a. combining these gives a limit of 6 a for i/o pins. usually, i/o pins will show leakages that are less than the i oz specification of the output alone. t esting cmos circuits is no more difficult than testing their bipolar counterparts. however, there are some areas of concern that will be new to many test engineers beginning to work with cmos. becoming familiar with and understanding these areas of concern prior to creating a test philosophy will avert many problems that might otherwise arise later.
http://onsemi.com 40 t esting disable times of 3-state outputs in a t ransmission line environment t raditionally, the disable time of a 3-state buffer has been measured from the 50% point on the disable input, to the 10% or 90% point on the output. on a bench test site, the output waveform is generated by a load capacitor and a pull-up/pull-down resistor. this circuit gives an rc charge/discharge curve as shown below. figure 1?53. typical bench 3-state waveform at e test sites generally are unable to duplicate the bench test structure. ate test loads dif fer because they are usually programmable and are situated away from the actual device. a commonly used test load is a wheatstone bridge. the following figure illustrates the wheatstone bridge test structure when used on the mct 2000 test-system to duplicate the bench load. figure 1?54. mct wheatstone bridge test load + the voltage source provides a pull-up/pull-down voltage while the current sources provide i oh and i ol . when devices with slow output slew rates are tested with the ate load, the resultant waveforms closely approximate the bench waveform, and a high degree of correlation can be achieved. however, when devices with high output slew rates are tested, different results are observed that make correlating tester results with bench results more difficult. this difference is due to the transmission line properties of the test equipment. most disable tests are preceded by establishing a current flow through the output structure. t ypically, these currents will be between 5 ma and 20 ma. the device is then disabled, and a comparator detects when the output has risen to the 10% or 90% level. consider the situation where the connection between the device under test (dut) and the comparator is a transmission line. visualize the device output as a switch; the effect is easier to see. there is current flowing through the line, and then the switch is opened. at the device end, the reflection coefficient changes from 0 to 1. this generates a current edge flowing back down the line equal to the current flowing in the line prior to the opening of the switch. this current wave will propagate down the line where it will encounter the high impedance tester load. this will cause the wave to be reflected back down the line toward the dut. the current wave will continue to reflect in the transmission line until it reaches the voltage applied to the tester load. at this point, the current source impedance decreases and it will dissipate the current. a typical waveshape on a modern ate is depicted in figure 1?51. figure 1?55. typical ate 3-state waveform
http://onsemi.com 41 t ransmission line theory states the voltage level of this current wave is equal to the current in the line times the impedance of the line. with typical currents as low as 5 ma and impedances of 50 to 60 ohms, this voltage step can be as minimal has 250 mv . if the comparator was programmed to the 10% point, it would be looking for a step of 550 mv at 5.5 v v cc . three reflections of the current pulse would be required before the comparator would detect the level. it is this added delay time caused by the transmission line environment of the ate that may cause parts to fail customers? incoming tests, even though the device meets specifications. the figure below graphically shows this stepout. figure 1?56. measurement stepout point a represents the typical 50% measurement point on tester driven waveforms. point b represents the point at which the delay time would be measured on a bench test fixture. point c represents where the delay time could be measured on at e fixtures. the delay time measured on the at e fixture can vary from the bench measured delay time to some greater value, depending upon the voltage level that the tester is set. if the voltage level of the tester is close to voltage levels of the plateaus, the results may become non-repeatable.
http://onsemi.com 42
http://onsemi.com 43 chapter 2 f act device data sheets
? semiconductor components industries, llc, 2002 may, 2002 ? rev. 6 44 publication order number: mc74ac00/d high?performance silicon?gate cmos ? output drive capability: 24 ma ? operating voltage range: 2 to 6 v ac00; 4.5 to 5.5 act00 ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with the jedec standard no. 7a requirements ? chip complexity: 32 fets figure 1. logic diagram figure 2. pinout: 14?lead packages (top view) l l h h l h l h function table inputs output ab h h h l y marking diagrams a= assembly location wl or l = wafer lot yy or y = year ww or w = work week tssop?14 dt suffix case 948g xxx 00 alyw 1 14 1 14 pdip?14 n suffix case 646 mc74xxx00n aw l yyww soic?14 d suffix case 751a 1 14 xxx00 awl yww http://onsemi.com eiaj?14 m suffix case 965 1 14 74xxx00 awl yww 1 14 1 14 1 14 1 14 see detailed ordering and shipping information in the package dimensions section on page 48 of this data sheet. ordering information
mc74ac00, mc74act00 http://onsemi.com 45 maximum ratings (note 1) symbol parameter v alue unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 v i v cc 0.5 v v o dc output voltage (note 2) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 78 125 170 c/w p d power dissipation in still air at 85 c pdip soic tssop 78 125 170 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 > 1000 v i latch?up latch?up performance above v cc and below gnd at 85 c (note 6) 100 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not implied. 2. i o absolute maximum rating must be observed. 3. tested to eia/jesd22?a114?a. 4. tested to eia/jesd22?a115?a. 5. tested to jesd22?c101?a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc supply voltage mc74ac00 mc74act00 2.0 4.5 5.0 5.0 6.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v t r , t f input rise and fall time (note 7) v cc @ 3.0 v mc74ac00 v cc @ 4.5 v v cc @ 5.5 v ? ? ? 150 40 25 ? ? ? ns/v t r , t f input rise and fall time (note 8) v cc @ 4.5 v mc74act00 v cc @ 5.5 v ? ? 10 8.0 ? ? ns/v t j junction temperature ? ? 150 c t a operating ambient temperature range ?55 25 125 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 7. v in from 30% to 70% v cc . 8. v in from 0.8 v to 2.0 v.
mc74ac00, mc74act00 http://onsemi.com 46 dc characteristics mc74ac00 v cc t a = +25 c t a = ?40 c to +85 c t a = ?55 c + 125 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level input voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 2.1 3.15 3.85 v v out = 0.1 v or v cc ? 0.1 v v il maximum low level input voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 0.9 1.35 1.65 v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 2.9 4.4 5.4 v i out = ?50 a 3.0 4.5 5.5 ? ? ? 2.56 3.86 4.86 2.46 3.76 4.76 2.4 3.7 4.7 v *v in = v il or v ih ?12 ma i oh ?24 ma ?24 ma v ol maximum low level output voltage 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v i out = 50 a 3.0 4.5 5.5 ? ? ? 0.36 0.36 0.36 0.44 0.44 0.44 0.5 0.5 0.5 v *v in = v il or v ih 12 ma i ol 24 ma 24 ma i in maximum input leakage current 5.5 ? 0. 1 1.0 1.0 a v i = v cc , gnd i old ?minimum dynamic output current 5.5 ? ? 75 50 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ?50 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 4.0 40 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics (t r = t f = 3.0 ns; c l = 50 pf; see figures 3 and 4 for waveforms) mc74ac00 v cc * t a = +25 c t a = ?40 c to +85 c t a = ?55 c to + 125 c symbol parameter v cc * (v) min typ max min max min max unit t plh propagation delay 3.3 5.0 2.0 1.5 7.0 6.0 9.5 8.0 2.0 1.5 10.0 8.5 1.0 1.0 1 1.0 8.5 ns t phl propagation delay 3.3 5.0 1.5 1.5 5.5 4.5 8.0 6.5 1.0 1.0 8.5 7.0 1.0 1.0 9.0 7.0 ns *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac00, mc74act00 http://onsemi.com 47 dc characteristics mc74act00 v cc t a = +25 c t a = ?40 c to +85 c t a = ?55 c to + 125 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level input voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 v v out = 0.1 v or v cc ? 0.1 v v il maximum low level input voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 0.8 0.8 v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 4.4 5.4 v i out = ?50 a 4.5 5.5 ? ? 3.86 4.86 3.76 4.76 3.7 4.7 v *v in = v il or v ih i oh ?24 ma ?24 ma v ol maximum low level output voltage 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 v i out = 50 a 4.5 5.5 ? ? 0.36 0.36 0.44 0.44 0.5 0.5 v *v in = v il or v ih i ol 24 ma 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 1.0 a v i = v cc , gnd i cct additional m ax. i cc /input 5.5 0.6 ? 1.5 1.6 ma v i = v cc ? 2.1 v i old ?minimum dynamic output current 5.5 ? ? 75 50 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ?50 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 4.0 40 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (t r = t f = 3.0 ns; c l = 50 pf; see figures 3 and 4 for waveforms) mc74act00 v cc * t a = +25 c t a = ?40 c to +85 c t a = ?55 c to +125 c symbol parameter v cc * (v) min typ max min max min max unit t plh propagation delay 5.0 1.5 5.5 9.0 1.0 9.5 1.0 9.5 ns t phl propagation delay 5.0 1.5 4.0 7.0 1.0 8.0 1.0 8.0 ns *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ t est conditions unit c in input capacitance 4.5 v cc = 5.0 v pf c pd power dissipation capacitance 30 v cc = 5.0 v pf
mc74ac00, mc74act00 http://onsemi.com 48 figure 3. switching waveforms gnd v cc output y input a or b c l * *includes all probe and jig capacitance 50% device under test output figure 4. test circuit 90% v mi 10% t plh t phl t f t r 50 scope t est point 450 input v mi = 50% for mc74ac00 = 1.5 v for mc74act00 order information device package shipping mc74ac00n pdip?14 2000/box mc74act00n pdip?14 2000/box mc74ac00dr2 soic?14 2500/reel mc74act00dr2 soic?14 2500/reel mc74ac00dtr2 tssop?14 2500/reel mc74act00dtr2 tssop?14 2500/reel mc74ac00mel eiaj?14 2000 tape and reel mc74act00mel eiaj?14 2000 tape and reel
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 49 publication order number: mc74ac02/d ? outputs source/sink 24 ma ? act02 has ttl compatible inputs figure 1. pinout: 14?lead packages conductors (top view) maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage temperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac02dt tssop?14 96 units/rail mc74ac02dtr2 tssop?14 2500 tape & reel mc74act02dt tssop?14 96 units/rail mc74act02dtr2 tssop?14 2500 tape & reel mc74ac02n pdip?14 25 units/rail mc74ac02d soic?14 55 units/rail mc74act02n pdip?14 25 units/rail mc 74a c02dr2 soic?14 2500 tape & reel mc74act02d soic?14 55 units/rail mc 74a c t02dr2 soic?14 2500 tape & reel mc74ac02m eiaj?14 50 units/rail mc74ac02mel eiaj?14 2000 tape & reel mc74act02m eiaj?14 50 units/rail mc74act02mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 53 of this data sheet. device marking information
mc74ac02, mc74act02 http://onsemi.com 50 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac02, mc74act02 http://onsemi.com 51 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 5.0 7.5 1.0 8.0 ns 3?5 t plh p ropagat i on d e l ay 5.0 1.5 4.0 6.0 1.0 6.5 ns 3 ?5 t phl propagation delay 3.3 1.5 5.0 7.5 1.0 8.0 ns 3?5 t phl p ropagat i on d e l ay 5.0 1.5 4.5 6.5 1.0 7.0 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac02, mc74act02 http://onsemi.com 52 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 1.5 ? 8.5 1.0 9.0 ns 3?6 t phl propagation delay 5.0 1.5 ? 9.5 1.0 10 ns 3?6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 30 pf v cc = 5.0 v
mc74ac02, mc74act02 http://onsemi.com 53 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac02n aw l yyww ac02 awl yww ac 02 alyw act 02 alyw act02 awl yww mc74act02n aw l yyww 74ac02 alyw eiaj?14 74act02 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 54 publication order number: mc74ac04/d ? outputs source/sink 24 ma ? act04 has ttl compatible inputs figure 1. pinout: 14?lead packages conductors (top view) maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage temperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac04dt tssop?14 96 units/rail mc74ac04dtr2 tssop?14 2500 tape & reel mc74act04dt tssop?14 96 units/rail mc74act04dtr2 tssop?14 2500 tape & reel mc74ac04n pdip?14 25 units/rail mc74ac04d soic?14 55 units/rail mc74act04n pdip?14 25 units/rail mc 74a c04dr2 soic?14 2500 tape & reel mc74act04d soic?14 55 units/rail mc 74a c t04dr2 soic?14 2500 tape & reel mc74ac04m eiaj?14 50 units/rail mc74ac04mel eiaj?14 2000 tape & reel mc74act04m eiaj?14 50 units/rail mc74act04mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 58 of this data sheet. device marking information
mc74ac04, mc74act04 http://onsemi.com 55 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac04, mc74act04 http://onsemi.com 56 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 4.5 9.0 1.0 10 ns 3?5 t plh p ropagat i on d e l ay 5.0 1.5 4.0 7.0 1.0 7.5 ns 3 ?5 t phl propagation delay 3.3 1.5 4.5 8.5 1.0 9.5 ns 3?5 t phl p ropagat i on d e l ay 5.0 1.5 3.5 6.5 1.0 7.0 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac04, mc74act04 http://onsemi.com 57 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 1.5 8.5 1.0 9.0 ns 3?6 t phl propagation delay 5.0 1.5 8.0 1.0 8.5 ns 3?6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 30 pf v cc = 5.0 v
mc74ac04, mc74act04 http://onsemi.com 58 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac04n aw l yyww ac04 awl yww ac 04 alyw act 04 alyw act04 awl yww mc74act04n aw l yyww 74ac04 alyw eiaj?14 74act04 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 59 publication order number: mc74ac05/d the mc74ac/act05 is identical in pinout to the ls05. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ttl outputs. ? outputs source/sink 24 ma ? act05 has ttl compatible inputs figure 1. pinout: 14-lead packages (top view) function table input a output y l h z l note: z = high impedance figure 2. logic diagram tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac05dt tssop?14 96 units/rail mc74ac05dtr2 tssop?14 2500 tape & reel mc74act05dt tssop?14 96 units/rail mc74act05dtr2 tssop?14 2500 tape & reel mc74ac05n pdip?14 25 units/rail mc74ac05d soic?14 55 units/rail mc74act05n pdip?14 25 units/rail mc 74a c05dr2 soic?14 2500 tape & reel mc74act05d soic?14 55 units/rail mc 74a c t05dr2 soic?14 2500 tape & reel mc74ac05m eiaj?14 50 units/rail mc74ac05mel eiaj?14 2000 tape & reel mc74act05m eiaj?14 50 units/rail mc74act05mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 63 of this data sheet. device marking information
mc74ac05, mc74act05 http://onsemi.com 60 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ min unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v vreg dc regulated power voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac05, mc74act05 http://onsemi.com 61 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in = v cc or gnd q supply current 5.5 ? 4 . 0 40 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v. ac characteristics 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min typ max min max t pzl propagation delay 3.3 1.5 ? 8.0 1.0 9.0 ns t pzl pg y output enable 5.0 1.5 ? 6.0 1.0 6.5 ns t plz propagation delay 3.3 1.5 ? 8.0 1.0 9.0 ns t plz pg y output enable 5.0 1.5 ? 6.0 1.0 6.5 ns *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac05, mc74act05 http://onsemi.com 62 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i oh 24 ma 5.5 ? 0.36 0.44 i oh 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in = v cc or gnd q supply current 5.5 ? 4 . 0 40 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min typ max min max t pzl propagation delay 50 15 ? 80 10 85 ns t pzl propagation delay output enable 5. 0 1 .5 ? 8 . 0 1 . 0 8 .5 ns t plz propagation delay 50 15 ? 85 10 90 ns t plz propagation delay output enable 5. 0 1 .5 ? 8 .5 1 . 0 9 . 0 ns *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 30 pf v cc = 5.0 v
mc74ac05, mc74act05 http://onsemi.com 63 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac05n aw l yyww ac05 awl yww ac 05 alyw act 05 alyw act05 awl yww mc74act05n aw l yyww 74ac05 alyw eiaj?14 74act05 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 64 publication order number: mc74ac08/d ? outputs source/sink 24 ma ? act08 has ttl compatible inputs figure 1. pinout: 14?lead packages conductors (top view) maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage temperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac08dt tssop?14 96 units/rail mc74ac08dtr2 tssop?14 2500 tape & reel mc74act08dt tssop?14 96 units/rail mc74act08dtr2 tssop?14 2500 tape & reel mc74ac08n pdip?14 25 units/rail mc74ac08d soic?14 55 units/rail mc74act08n pdip?14 25 units/rail mc 74a c08dr2 soic?14 2500 tape & reel mc74act08d soic?14 55 units/rail mc 74a c t08dr2 soic?14 2500 tape & reel mc74ac08m eiaj?14 50 units/rail mc74ac08mel eiaj?14 2000 tape & reel mc74act08m eiaj?14 50 units/rail mc74act08mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 68 of this data sheet. device marking information
mc74ac08, mc74act08 http://onsemi.com 65 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac08, mc74act08 http://onsemi.com 66 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 7.5 9.5 1.0 10.0 ns 3?5 t plh p ropagat i on d e l ay 5.0 1.5 5.5 7.5 1.0 8.5 ns 3 ?5 t phl propagation delay 3.3 1.5 7.0 8.5 1.0 9.0 ns 3?5 t phl p ropagat i on d e l ay 5.0 1.5 5.5 7.0 1.0 7.5 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac08, mc74act08 http://onsemi.com 67 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 1.0 ? 9.0 1.0 10.0 ns 3?5 t phl propagation delay 5.0 1.0 ? 9.0 1.0 10.0 ns 3?5 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 20 pf v cc = 5.0 v
mc74ac08, mc74act08 http://onsemi.com 68 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac08n aw l yyww ac08 awl yww ac 08 alyw act 08 alyw act08 awl yww mc74act08n aw l yyww 74ac08 alyw eiaj?14 74act08 alyw
? semiconductor components industries, llc, 2002 june, 2002 ? rev. 6 69 publication order number: mc74ac10/d ? outputs source/sink 24 ma ? act10 has ttl compatible inputs figure 1. pinout: 14?lead packages conductors (top view) maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage temperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac10dt tssop?14 96 units/rail mc74ac10dtr2 tssop?14 2500 tape & reel mc74act10dt tssop?14 96 units/rail mc74act10dtr2 tssop?14 2500 tape & reel mc74ac10n pdip?14 25 units/rail mc74ac10d soic?14 55 units/rail mc74act10n pdip?14 25 units/rail mc 74a c10dr2 soic?14 2500 tape & reel mc74act10d soic?14 55 units/rail mc 74a c t10dr2 soic?14 2500 tape & reel mc74ac10m eiaj?14 50 units/rail mc74act10m eiaj?14 50 units/rail mc74act10mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 73 of this data sheet. device marking information http://onsemi.com
mc74ac10, mc74act10 http://onsemi.com 70 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac10, mc74act10 http://onsemi.com 71 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 6.0 9.5 1.0 10.5 ns 3?5 t plh p ropagat i on d e l ay 5.0 1.5 4.5 7.0 1.0 8.0 ns 3 ?5 t phl propagation delay 3.3 1.5 5.5 8.5 1.0 10.0 ns 3?5 t phl p ropagat i on d e l ay 5.0 1.5 4.0 6.0 1.0 6.5 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac10, mc74act10 http://onsemi.com 72 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 1.0 ? 9.0 1.0 10.0 ns 3?5 t phl propagation delay 5.0 1.0 ? 9.0 1.0 9.5 ns 3?5 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 25 pf v cc = 5.0 v
mc74ac10, mc74act10 http://onsemi.com 73 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac10n aw l yyww ac10 awl yww ac 10 alyw act 10 alyw act10 awl yww mc74act10n aw l yyww 74ac10 alyw eiaj?14 74act10 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 74 publication order number: mc74ac11/d ? outputs source/sink 24 ma ? act11 has ttl compatible inputs figure 1. pinout: 14?lead packages conductors (top view) maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage temperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac11dt tssop?14 96 units/rail mc74ac11dtr2 tssop?14 2500 tape & reel mc74act11dt tssop?14 96 units/rail mc74act11dtr2 tssop?14 2500 tape & reel mc74ac11n pdip?14 25 units/rail mc74ac11d soic?14 55 units/rail mc74act11n pdip?14 25 units/rail mc 74a c11dr2 soic?14 2500 tape & reel mc74act11d soic?14 55 units/rail mc 74a ct 11 dr2 soic?14 2500 tape & reel mc74ac11m eiaj?14 50 units/rail mc74ac11mel eiaj?14 2000 tape & reel mc74act11m eiaj?14 50 units/rail mc74act11mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 78 of this data sheet. device marking information
mc74ac11, mc74act11 http://onsemi.com 75 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac11, mc74act11 http://onsemi.com 76 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 5.5 9.5 1.0 10.0 ns 3?5 t plh p ropagat i on d e l ay 5.0 1.5 4.0 8.0 1.0 8.5 ns 3 ?5 t phl propagation delay 3.3 1.5 5.5 8.5 1.0 9.5 ns 3?5 t phl p ropagat i on d e l ay 5.0 1.5 4.0 7.0 1.0 7.5 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac11, mc74act11 http://onsemi.com 77 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 1.5 ? 9.5 1.0 10.5 ns 3?5 t phl propagation delay 5.0 1.5 ? 9.5 1.0 10.5 ns 3?5 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 20 pf v cc = 5.0 v
mc74ac11, mc74act11 http://onsemi.com 78 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac11n aw l yyww ac11 awl yww ac 11 alyw act 11 alyw act11 awl yww mc74act11n aw l yyww 74ac11 alyw eiaj?14 74act1 1 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 79 publication order number: mc74ac14/d the mc74ac14/74act14 contains six logic inverters which accept standard cmos input signals (ttl levels for mc74act14) and provide standard cmos output levels. they are capable of transforming slowly changing input signals into sharply defined, jitter?free output signals. in addition, they have a greater noise margin then conventional inverters. the mc74ac14/74act14 has hysteresis between the positive?going and negative?going input thresholds (typically 1.0 v) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations. ? schmitt trigger inputs ? outputs source/sink 24 ma ? act14 has ttl compatible inputs figure 1. pinout; 14?lead packages conductors (top view) function table input output a o l h h l tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac14dt tssop?14 96 units/rail mc74ac14dtr2 tssop?14 2500 tape & reel mc74act14dt tssop?14 96 units/rail mc74act14dtr2 tssop?14 2500 tape & reel mc74ac14n pdip?14 25 units/rail mc74ac14d soic?14 55 units/rail mc74act14n pdip?14 25 units/rail mc 74a c14dr2 soic?14 2500 tape & reel mc74act14d soic?14 55 units/rail mc 74a c t14dr2 soic?14 2500 tape & reel mc74ac14m eiaj?14 50 units/rail mc74ac14mel eiaj?14 2000 tape & reel mc74act14m eiaj?14 50 units/rail mc74act14mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 83 of this data sheet. device marking information
mc74ac14, mc74act14 http://onsemi.com 80 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac14, mc74act14 http://onsemi.com 81 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 9.5 13.5 1.5 15.0 ns 3?5 t plh p ropagat i on d e l ay 5.0 1.5 7.0 10.0 1.5 1 1.0 ns 3 ?5 t phl propagation delay 3.3 1.5 7.5 1 1.5 1.5 13.0 ns 3?5 t phl p ropagat i on d e l ay 5.0 1.5 6.0 8.5 1.5 9.5 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac14, mc74act14 http://onsemi.com 82 input characteristics (unless otherwise specified) symbol parameter v cc 74ac 74act t est conditions symbol parameter v cc (v) 74ac 74act t est conditions maximum positive 3.0 2.2 v t + m ax i mum p os i t i ve threshold 4.5 3.2 2.0 v t a = worst case threshold 5.5 3.9 minimum negative 3.0 0.5 v t ? mi n i mum n egat i ve threshold 4.5 0.9 0.8 v t a = worst case threshold 5.5 1.1 3.0 1.2 v h(max) maximum hysteresis 4.5 1.4 1.2 v t a = worst case 5.5 1.6 3.0 0.3 v h(min) minimum hysteresis 4.5 0.4 0.4 v t a = worst case 5.5 0.5 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac14, mc74act14 http://onsemi.com 83 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 1.5 ? 1 1.5 1.0 12.5 ns 3?5 t phl propagation delay 5.0 1.5 ? 10.0 1.0 1 1.0 ns 3?5 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 25 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac14n aw l yyww ac14 awl yww ac 14 alyw act 14 alyw act14 awl yww mc74act14n aw l yyww 74ac14 alyw eiaj?14 74act14 alyw
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 84 publication order number: mc74ac20/d ? outputs source/sink 24 ma ? act20 has ttl compatible inputs figure 1. pinout: 14-lead packages (top view) pin assignment pin function a n , b n , c n , d n inputs o n outputs maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc + 0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc + 0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage temperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended oper- ating conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac20dt tssop?14 96 units/rail mc74ac20dtr2 tssop?14 2500 tape & reel mc74act20dt tssop?14 96 units/rail mc74act20dtr2 tssop?14 2500 tape & reel mc74ac20n pdip?14 25 units/rail mc74ac20d soic?14 55 units/rail mc74act20n pdip?14 25 units/rail mc 74a c20dr2 soic?14 2500 tape & reel mc74act20d soic?14 55 units/rail mc 74a c t20dr2 soic?14 2500 tape & reel mc74ac20m eiaj?14 50 units/rail mc74ac20mel eiaj?14 2000 tape & reel mc74act20mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 88 of this data sheet. device marking information http://onsemi.com
mc74ac20, mc74act20 http://onsemi.com 85 recommended operating conditions symbol parameter min typ min unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v vreg dc regulated power voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum low level 3.0 2.99 2.9 2.9 i out = ? 50 a output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ? 12 ma 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 ? 24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in = v cc or gnd q supply current 5.5 ? 4 . 0 40 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v.
mc74ac20, mc74act20 http://onsemi.com 86 ac characteristics 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min typ max min max t plh propagation delay 3.3 2.0 6.0 8.5 1.5 10.0 ns plh pg y 5.0 1.5 5.0 7.0 1.0 8.0 ns t phl propagation delay 3.3 1.5 5.0 7.0 1.0 9.0 ns phl pg y 5.0 1.5 4.0 6.0 1.0 7.0 ns *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ? 50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 i oh ? 24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i oh 24 ma 5.5 ? 0.36 0.44 i oh 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in = v cc or gnd q supply current 5.5 ? 4 . 0 40 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac20, mc74act20 http://onsemi.com 87 ac characteristics 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min typ max min max t plh propagation delay 50 20 65 90 15 10 5 ns t plh propagation delay 5. 0 2 . 0 6 .5 9 . 0 1 .5 10 .5 ns t phl propagation delay 50 20 55 90 15 10 5 ns t phl propagation delay 5. 0 2 . 0 5.5 9 . 0 1 .5 10 .5 ns *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 40 pf v cc = 5.0 v
mc74ac20, mc74act20 http://onsemi.com 88 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac20n aw l yyww ac20 awl yww ac 20 alyw act 20 alyw act20 awl yww mc74act20n aw l yyww 74ac20 alyw eiaj?14 74act20 alyw
? semiconductor components industries, llc, 2001 may , 2001 ? rev. 5 89 publication order number: mc74ac32/d ? outputs source/sink 24 ma ? act32 has ttl compatible inputs
figure 1. pinout: 14?lead packages conductors (top view) maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage t emperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operat- ing conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac32dt tssop?14 96 units/rail mc74ac32dtr2 tssop?14 2500 tape & reel mc74act32dt tssop?14 96 units/rail mc74act32dtr2 tssop?14 2500 tape & reel mc74ac32n pdip?14 25 units/rail mc74ac32d soic?14 55 units/rail mc74act32n pdip?14 25 units/rail mc 74a c32dr2 soic?14 2500 tape & reel mc74act32d soic?14 55 units/rail mc 74a c t32dr2 soic?14 2500 tape & reel mc74ac32m eiaj?14 50 units/rail mc74ac32mel eiaj?14 2000 tape & reel mc74act32m eiaj?14 50 units/rail mc74act32mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 93 of this data sheet. device marking information
mc74ac32, mc74act32 http://onsemi.com 90 recommended o perating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply v oltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v rf ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f input rise and fall time (note 2) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input v oltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input v oltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output v oltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output v oltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac32, mc74act32 http://onsemi.com 91 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 7.0 9.0 1.5 10.0 ns 3 ? 5 t plh p ropagat i on d e l ay 5.0 1.5 5.5 7.5 1.0 8.5 ns 3 ?5 t phl propagation delay 3.3 1.5 7.0 8.5 1.0 9.0 ns 3 ? 5 t phl p ropagat i on d e l ay 5.0 1.5 5.0 7.0 1.0 7.5 ns 3 ?5 *v oltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input v oltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input v oltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output v oltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output v oltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac32, mc74act32 http://onsemi.com 92 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 1.0 ? 9.0 1.0 10.0 ns 3?6 t phl propagation delay 5.0 1.0 ? 9.0 1.0 10.0 ns 3?6 *v oltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 20 pf v cc = 5.0 v
mc74ac32, mc74act32 http://onsemi.com 93 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww , w = work week pdip?14 so?14 tssop?14 mc74ac32n aw l yyww ac32 awl yww ac 32 alyw act 32 alyw act32 awl yww mc74act32n aw l yyww 74ac32 alyw eiaj?14 74act32 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 94 publication order number: mc74ac74/d the mc74ac74/74act74 is a dual d?type flip?flop with asynchronous clear and set inputs and complementary (q,q ) outputs. information at the input is transferred to the outputs on the positive edge of the clock pulse. clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. after the clock pulse input threshold voltage has been passed, the data input is locked out and information present will not be transferred to the outputs until the next rising edge of the clock pulse input. asynchronous inputs: low input to s d (set) sets q to high level low input to c d (clear) sets q to low level clear and set are independent of clock simultaneous low on c d and s d makes both q and q high ? outputs source/sink 24 ma ? act74 has ttl compatible inputs figure 1. pinout: 14?lead packages conductors (top view) pin assignment pin function d 1 , d 2 data inputs cp 1 , cp 2 clock pulse inputs c d1 , c d2 direct clear inputs s d1 , s d2 direct set inputs q 1 , q 1 , q 2 , q 2 outputs tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac74dt tssop?14 96 units/rail mc74ac74dtr2 tssop?14 2500 tape & reel mc74act74dt tssop?14 96 units/rail mc74act74dtr2 tssop?14 2500 tape & reel mc74ac74n pdip?14 25 units/rail mc74ac74d soic?14 55 units/rail mc74act74n pdip?14 25 units/rail mc 74a c74dr2 soic?14 2500 tape & reel mc74act74d soic?14 55 units/rail mc 74a c t74dr2 soic?14 2500 tape & reel mc74ac74m eiaj?14 50 units/rail mc74ac74mel eiaj?14 2000 tape & reel mc74act74m eiaj?14 50 units/rail mc74act74mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 100 of this data sheet. device marking information
mc74ac74, mc74act74 http://onsemi.com 95 truth table (each half) inputs outputs s d c d cp d q q l h x x h l h l x x l h l l x x h h h h h h l h h l l h h h l x q 0 q 0 note: h = high voltage level l = low voltage level x = immaterial; = low-to-high clock transition q 0 (q 0 ) = previous q(q ) before low-to-high t ransition of clock figure 2. logic symbol figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions.
mc74ac74, mc74act74 http://onsemi.com 96 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note ) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note ) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac74, mc74act74 http://onsemi.com 97 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 100 125 ? 95 ? mhz 3?3 f max frequency 5.0 140 160 ? 125 ? mh z 3 ? 3 t plh propagation delay 3.3 5.0 8.0 12.5 4.0 13.0 ns 3?6 t plh pg y c dn or s dn to q n or q n 5.0 3.5 6.0 9.0 3.0 10.0 ns 3 ? 6 t phl propagation delay 3.3 4.0 10.5 12.0 3.5 13.5 ns 3?6 t phl pg y c dn or s dn to q n or q n 5.0 3.0 8.0 9.5 2.5 10.5 ns 3 ? 6 t plh propagation delay 3.3 4.5 8.0 13.5 4.0 16.0 ns 3?6 t plh pg y c pn to q n or q n 5.0 3.5 6.0 10.0 3.0 10.5 ns 3 ? 6 t phl propagation delay 3.3 3.5 8.0 14.0 3.5 14.5 ns 3?6 t phl pg y c pn to q n or q n 5.0 2.5 6.0 10.0 2.5 10.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s set-up time, high or low 3.3 1.5 4.0 4.5 ns 3?9 t s d n to cp n 5.0 1.0 3.0 3.0 ns 3 ? 9 t h hold time, high or low 3.3 ?2.0 0.5 0.5 ns 3?9 t h d n to cp n 5.0 ?1.5 0.5 0.5 ns 3 ? 9 t c pn or c dn or s dn 3.3 3.0 5.5 7.0 ns 3?6 t w pulse width 5.0 2.5 4.5 5.0 ns 3 ? 6 t rec recovery time 3.3 ?2.5 0 0 ns 3?9 t rec c dn or s dn to cp 5.0 ?2.0 0 0 ns 3 ? 9 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac74, mc74act74 http://onsemi.com 98 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 50 145 210 ? 125 ? mhz 3?3 f max maximum clock frequency 5. 0 14 5 210 ? 12 5 ? mh z 3 ? 3 t plh propagation delay 50 30 55 95 25 10 5 ns 3?6 t plh propagation delay c dn or s dn to q n or q n 5. 0 3 . 0 5.5 9 .5 2 .5 10 .5 ns 3 ? 6 t phl propagation delay 50 30 60 10 0 30 11 5 ns 3?6 t phl propagation delay c dn or s dn to q n or q n 5. 0 3 . 0 6 . 0 10 . 0 3 . 0 11 .5 ns 3 ? 6 t plh propagation delay 50 40 75 11 0 40 13 0 ns 3?6 t plh propagation delay c pn to q n or q n 5. 0 4 . 0 7.5 11 . 0 4 . 0 13 . 0 ns 3 ? 6 t phl propagation delay 50 35 60 10 0 30 11 5 ns 3?6 t phl propagation delay c pn to q n or q n 5. 0 3 .5 6 . 0 10 . 0 3 . 0 11 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac74, mc74act74 http://onsemi.com 99 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s set-up time, high or low 50 10 30 35 ns 3?9 t s d n to cp n 5. 0 1 . 0 3 . 0 3 .5 ns 3 ? 9 t h hold time, high or low 50 ?0 5 10 10 ns 3?9 t h d n to cp n 5. 0 ? 0 .5 1 . 0 1 . 0 ns 3 ? 9 t c pn or c dn or s dn 50 30 50 60 ns 3?6 t w pulse width 5. 0 3 . 0 5. 0 6 . 0 ns 3 ? 6 t rec recovery time 50 ?2 5 0 0 ns 3?9 t rec c dn or s dn to cp 5. 0 ? 2 .5 0 0 ns 3 ? 9 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 35 pf v cc = 5.0 v
mc74ac74, mc74act74 http://onsemi.com 100 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac74n aw l yyww ac74 awl yww ac 74 alyw act 74 alyw act74 awl yww mc74act74n aw l yyww 74ac74 alyw eiaj?14 74act74 alyw
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 101 publication order number: mc74ac86/d ? outputs source/sink 24 ma figure 1. pinout: 14?lead packages conductors (top view) maximum ratings* rating symbol v alue unit dc supply voltage (referenced to gnd) v cc ?0.5 to +7.0 v dc input voltage (referenced to gnd) v in ?0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out ?0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output sink/source current, per pin i out 50 ma dc v cc or gnd current per output pin i cc 50 ma storage temperature t stg ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac86dt tssop?14 96 units/rail mc74ac86dtr2 tssop?14 2500 tape & reel mc74act86dt tssop?14 96 units/rail mc74act86dtr2 tssop?14 2500 tape & reel mc74ac86n pdip?14 25 units/rail mc74ac86d soic?14 55 units/rail mc74act86n pdip?14 25 units/rail mc 74a c86dr2 soic?14 2500 tape & reel mc74act86d soic?14 55 units/rail mc 74a c t86dr2 soic?14 2500 tape & reel mc74ac86m eiaj?14 50 units/rail mc74act86m eiaj?14 50 units/rail mc74act86mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 105 of this data sheet. device marking information http://onsemi.com
mc74ac86, mc74act86 http://onsemi.com 102 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac v cc t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac86, mc74act86 http://onsemi.com 103 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac v cc * t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf fig symbol parameter v cc * (v) min typ max min max unit fi g. no. t plh propagation delay 3.3 2.0 6.0 1 1.5 1.5 12.5 ns 3?5 t plh pg y inputs to outputs 5.0 1.5 4.5 8.5 1.0 9.0 ns 3 ?5 t phl propagation delay 3.3 2.0 6.5 1 1.5 1.5 12.5 ns 3?5 t phl pg y inputs to outputs 5.0 1.5 4.5 8.5 1.0 9.5 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act v cc t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 01 10 a v i =v cc gnd p leakage current 5.5 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac86, mc74act86 http://onsemi.com 104 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act v cc * t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf fig symbol parameter v cc * (v) min typ max min max unit fi g. no. t plh propagation delay 5.0 1.5 8.5 9.5 1.0 10.0 ns 3?5 t phl propagation delay 5.0 1.5 7.0 9.5 1.0 10.5 ns 3?5 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 35 pf v cc = 5.0 v
mc74ac86, mc74act86 http://onsemi.com 105 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac86n aw l yyww ac86 awl yww ac 86 alyw act 86 alyw act86 awl yww mc74act86n aw l yyww 74ac86 alyw eiaj?14 74act86 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 106 publication order number: mc74ac109/d the mc74ac109/74act109 consists of two high?speed completely independent transition clocked jk flip?flops. the clocking operation is independent of rise and fall times of the clock waveform. the jk design allows operation as a d flip?flop (refer to mc74ac74/74act74 data sheet) by connecting the j and k inputs together. asynchronous inputs: low input to s d (set) sets q to high level low input to c d (clear) sets q to low level clear and set are independent of clock simultaneous low on c d and s d makes both q and q high ? outputs source/sink 24 ma ? act109 has ttl compatible inputs figure 1. pinout; 16?lead packages conductors (top view) pin assignment pin function j 1 , j 2 , k 1 , k 2 data inputs cp 1 , cp 2 clock pulse inputs c d1 , c d2 direct clear inputs s d1 , s d2 direct set inputs q 1 , q 2 , q 1 , q 2 outputs http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac109n pdip?16 25 units/rail mc74ac109d soic?16 48 units/rail mc74ac109dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac109dt tssop?16 96 units/rail mc74ac109dtr2 tssop?16 soic?16 2500 tape & reel mc74act109n pdip?16 25 units/rail mc74act109d soic?16 48 units/rail mc74act109dr2 2500 tape & reel mc74act109dt tssop?16 96 units/rail mc74act109dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 11 1 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac109m eiaj?16 mc74ac109mel eiaj?16 2000 tape & reel mc74act109m eiaj?16 mc74act109mel eiaj?16 2000 tape & reel 50 units/rail 50 units/rail
mc74ac109, mc74act109 http://onsemi.com 107 truth table inputs outputs s d c d cp j k q q l h x x x h l h lxx x l h l lxx x h h h h lll h h h hl t oggle h h lhq 0 q 0 ? h h hhh l h h l x x q 0 q 0 ? h = high voltage level l = low voltage level = low?to?high clock transition x = immaterial q 0 (q 0 ) = previous q 0 (q 0 ) before low?to?high transition of clock figure 2. logic symbol note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram (one half shown) maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions.
mc74ac109, mc74act109 http://onsemi.com 108 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac109, mc74act109 http://onsemi.com 109 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 125 ? ? 100 ? mhz 3?3 f max frequency 5.0 150 ? ? 125 ? mh z 3 ? 3 t plh propagation delay 3.3 4.0 ? 13.5 3.5 16.0 ns 3?6 t plh pg y cp n to q n or q n 5.0 2.5 ? 10.0 2.0 10.5 ns 3 ? 6 t phl propagation delay 3.3 3.0 ? 14.0 3.0 14.5 ns 3?6 t phl pg y cp n to q n or q n 5.0 2.0 ? 10.0 1.5 10.5 ns 3 ? 6 t plh propagation delay 3.3 3.0 ? 12.0 2.5 13.0 ns 3?6 t plh pg y c dn or s dn to q n or q n 5.0 2.5 ? 9.0 2.0 10.0 ns 3 ? 6 t phl propagation delay 3.3 3.0 ? 12.0 3.0 13.5 ns 3?6 t phl pg y c d n or s dn to q n or q n 5.0 2.0 ? 9.5 2.0 10.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s set?up time, high or low 3.3 ? 6.5 7.5 ns 3?9 t s set up t ime, high or low j n or k n to cp n 3.3 5.0 ? 6.5 4.5 7.5 5.0 ns 3 ? 9 t h hold time, high or low 3.3 ? 0 0 ns 3?9 t h hold t ime, high or low j n or k n to cp n 3.3 5.0 ? 0 0.5 0 0.5 ns 3 ? 9 t pulse width 3.3 ? 4.0 4.5 ns 3?6 t w pulse width cp n or c dn or s dn 3.3 5.0 ? 4.0 3.5 4.5 3.5 ns 3 ? 6 t rec recovery time 3.3 ? 0 0 ns 3?9 t rec recovery time c dn or s dn to cp 3.3 5.0 ? 0 0 0 0 ns 3 ? 9 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac109, mc74act109 http://onsemi.com 110 dc characteristics (continued) symbol conditions unit 74act 74act v cc (v) parameter symbol conditions unit t a = ?40 c to +85 c t a = +25 c v cc (v) parameter symbol conditions unit guaranteed limits typ v cc (v) parameter v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 50 145 ? ? 125 ? mhz 3?3 f max maximum clock frequency 5. 0 14 5 ? ? 12 5 ? mh z 3 ? 3 t plh propagation delay 50 40 ? 11 0 35 13 0 ns 3?6 t plh propagation delay cp n to q n or q n 5. 0 4 . 0 ? 11 . 0 3 .5 13 . 0 ns 3 ? 6 t phl propagation delay 50 30 ? 10 0 25 11 5 ns 3?6 t phl propagation delay cp n to q n or q n 5. 0 3 . 0 ? 10 . 0 2 .5 11 .5 ns 3 ? 6 t plh propagation delay 50 25 ? 95 20 10 5 ns 3?6 t plh propagation delay c dn or s dn to q n or q n 5. 0 2 .5 ? 9 .5 2 . 0 10 .5 ns 3 ? 6 t phl propagation delay 50 25 ? 10 0 20 11 5 ns 3?6 t phl propagation delay c dn or s dn to q n or q n 5. 0 2 .5 ? 10 . 0 2 . 0 11 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s set?up time, high or low 50 ? 20 25 ns 3?9 t s set up t ime, high or low j n or k n to cp n 5. 0 ? 2 . 0 2 .5 ns 3 ? 9 t h hold time, high or low 50 ? 20 20 ns 3?9 t h hold t ime, high or low j n or k n to cp n 5. 0 ? 2 . 0 2 . 0 ns 3 ? 9 t pulse width 50 ? 50 60 ns 3?6 t w pulse width cp n or c dn or s dn 5. 0 ? 5. 0 6 . 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac109, mc74act109 http://onsemi.com 111 ac operating requirements (continued) symbol fig. no. unit 74act 74act v cc * (v) parameter symbol fig. no. unit t a = ?40 c to +85 c c l = 50 pf t a = +25 c c l = 50 pf v cc * (v) parameter symbol fig. no. unit guaranteed minimum typ v cc * (v) parameter t rec recovery time 50 ? 0 0 ns 3?9 t rec recovery time c dn or s dn to cp 5. 0 ? 0 0 ns 3 ? 9 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 35 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac109 awl yww mc74ac109n aw l yyww ac 109 alyw act109 awl yww act 109 alyw mc74act109n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac109 alyw 74act109 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 112 publication order number: mc74ac125/d ? outputs source/sink ? act125 has ttl compatible inputs figure 1. pinout: 14?lead packages conductors (top view) pin assignment pin function a n , b n inputs o n outputs function table inputs output a n b n o n l l l h l h h x z note: h = high voltage level; l = low voltage level; z = high impedance; x = immaterial tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac125dt tssop?14 96 units/rail mc74ac125dtr2 tssop?14 2500 tape & reel mc74act125dt tssop?14 96 units/rail mc74act125dtr2 tssop?14 2500 tape & reel mc74ac125n pdip?14 25 units/rail mc74ac125d soic?14 55 units/rail mc74act125n pdip?14 25 units/rail mc 74a c125dr2 soic?14 2500 tape & reel mc74act125d soic?14 55 units/rail mc 74a c t125dr2 soic?14 2500 tape & reel mc74ac125m eiaj?14 50 units/rail mc74ac125mel eiaj?14 2000 tape & reel mc74act125m eiaj?14 50 units/rail mc74act125mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 1 16 of this data sheet. device marking information
mc74ac125, mc74act125 http://onsemi.com 113 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac125, mc74act125 http://onsemi.com 114 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ? 50 a g output voltage 4.5 4.46 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 ? 24 ma v ol minimum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i oz v i (oe) = v il , v ih v i (oe) = v il , v ih i () il , ih v i = v cc , gnd 5.5 ? 0.5 5.0 a v i = v cc , gnd v o = v cc , gnd a v in = v cc or gnd q supply current 5.5 ? 8 . 0 80 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one input loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v.
mc74ac125, mc74act125 http://onsemi.com 115 ac characteristics 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min max min max t plh propagation delay 3.3 1.0 9.0 1.0 10 ns t plh pg y data to output 5.0 1.0 7.0 1.0 7.5 ns t phl propagation delay 3.3 1.0 9.0 1.0 10 ns t phl pg y data to output 5.0 1.0 7.0 1.0 7.5 ns t pzh output enable 3.3 1.0 10.5 1.0 11 ns t pzh p t ime 5.0 1.0 7.0 1.0 8.0 ns t pzl output enable 3.3 1.0 10 1.0 11 ns t pzl p t ime 5.0 1.0 8.0 1.0 8.5 ns t phz output disable 3.3 1.0 10 1.0 10.5 ns t phz p t ime 5.0 1.0 9.0 1.0 9.5 ns t plz output disable 3.3 1.0 10.5 1.0 1 1.5 ns t plz p t ime 5.0 1.0 9.0 1.0 9.5 ns *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.2 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ? 50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 i oh ? 24 ma v ol minimum low level 4.5 0.001 0.1 0.1 v i out = ? 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i oh ? 24 ma 5.5 ? 0.36 0.44 ? 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i oz v i (oe) = v il , v ih v i (oe) = v il , v ih i () il , ih v i = v cc , gnd 5.5 ? 0.5 5.0 a v i = v cc , gnd v o = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one input loaded at a time.
mc74ac125, mc74act125 http://onsemi.com 116 ac characteristics 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min max min max t plh propagation delay 50 10 90 10 10 ns t plh propagation delay data to output 5. 0 1 . 0 9 . 0 1 . 0 10 ns t phl propagation delay 50 10 90 10 10 ns t phl propagation delay data to output 5. 0 1 . 0 9 . 0 1 . 0 10 ns t pzh output enable 50 10 85 10 95 ns t pzh output enable t ime 5. 0 1 . 0 8 .5 1 . 0 9 .5 ns t pzl output enable 50 10 95 10 10 5 ns t pzl output enable t ime 5. 0 1 . 0 9 .5 1 . 0 10 .5 ns t phz output disable 50 10 95 10 10 5 ns t phz output disable t ime 5. 0 1 . 0 9 .5 1 . 0 10 .5 ns t plz output disable 50 10 10 10 10 5 ns t plz output disable t ime 5. 0 1 . 0 10 1 . 0 10 .5 ns *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac125n aw l yyww ac125 awl yww ac 125 alyw act 125 alyw act125 awl yww mc74act125n aw l yyww 74ac12 5 alyw eiaj?14 74act12 5 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 117 publication order number: mc74ac132/d the mc74ac/74act132 contains four 2?input nand gates which are capable of transforming slowly changing input signals into sharply defined, jitter?free output signals. in addition, they have greater noise margin than conventional nand gates. each circuit contains a 2?input schmitt trigger. the schmitt trigger uses positive feedback to effectively speed?up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. this hysteresis between the positive?going and negative?going input threshold is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations. ? schmitt trigger inputs ? outputs source/sink 24 ma ? act132 has ttl compatible inputs figure 1. pinout; 14?lead packages conductors (top view) function table inputs output a b y l l h l h h h l h h h l h = high voltage level l = low voltage level tssop?14 dt suffix case 948g 1 14 eiaj?14 m suffix case 965 1 14 so?14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip?14 n suffix case 646 device package shipping ordering information mc74ac132dt tssop?14 96 units/rail mc74ac132dtr2 tssop?14 2500 tape & reel mc74act132dt tssop?14 96 units/rail mc74act132dtr2 tssop?14 2500 tape & reel mc74ac132n pdip?14 25 units/rail mc74ac132d soic?14 55 units/rail mc74act132n pdip?14 25 units/rail mc 74a c132dr2 soic?14 2500 tape & reel mc74act132d soic?14 55 units/rail mc 74a c t132dr2 soic?14 2500 tape & reel mc74ac132m eiaj?14 50 units/rail mc74ac132mel eiaj?14 2000 tape & reel mc74act132m eiaj?14 50 units/rail mc74act132mel eiaj?14 2000 tape & reel see general marking information in the device marking section on page 121 of this data sheet. device marking information
mc74ac132, mc74act132 http://onsemi.com 118 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac132, mc74act132 http://onsemi.com 119 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 2.0 ? 13.0 1.5 14.0 ns 3?5 t plh p ropagat i on d e l ay 5.0 2.0 ? 9.0 1.5 10.0 ns 3 ?5 t phl propagation delay 3.3 2.0 ? 13.5 1.5 15.0 ns 3?5 t phl p ropagat i on d e l ay 5.0 2.0 ? 9.0 1.5 10.0 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 40 40 a v in =v cc or gnd q supply current 5.5 ? 4 . 0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 5.0 3.0 ? 1 1.5 2.5 13.0 ns 3?6 t phl propagation delay 5.0 3.0 ? 1 1.0 2.5 12.5 ns 3?5 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac132, mc74act132 http://onsemi.com 120 input characteristics (unless otherwise specified) symbol parameter v cc (v) 74ac 74act unit t est conditions maximum positive 3.0 2.2 v t + m ax i mum p os i t i ve threshold 4.5 3.2 2.0 v t a = worst case threshold 5.5 3.9 minimum negative 3.0 0.5 v t ? mi n i mum n egat i ve threshold 4.5 0.9 0.8 v t a = worst case threshold 5.5 1.1 3.0 1.2 v h(max) maximum hysteresis 4.5 1.4 1.2 v t a = worst case 5.5 1.6 3.0 0.3 v h(min) minimum hysteresis 4.5 0.4 0.4 v t a = worst case 5.5 0.5 capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 30 pf v cc = 5.0 v
mc74ac132, mc74act132 http://onsemi.com 121 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 so?14 tssop?14 mc74ac132n aw l yyww ac132 awl yww ac 132 alyw act 132 alyw act132 awl yww mc74act132n aw l yyww 74ac13 2 alyw eiaj?14 74act13 2 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 122 publication order number: mc74ac138/d the mc74ac138/74act138 is a high?speed 1?of?8 decoder/demultiplexer. this device is ideally suited for high?speed bipolar memory chip select address decoding. the multiple input enables allow parallel expansion to a 1?of?24 decoder using just three mc74ac138/74act138 devices or a 1?of?32 decoder using four mc74ac138/74act138 devices and one inverter. ? demultiplexing capability ? multiple input enable for easy expansion ? active low mutually exclusive outputs ? outputs source/sink 24 ma ? act138 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) figure 2. logic symbol pin assignment pin function a 0 ?a 2 address inputs e 1 ?e 2 enable inputs e 3 enable input o 0 ?o 7 outputs http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac138n pdip?16 25 units/rail mc74ac138d soic?16 48 units/rail mc74ac138dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac138dt tssop?16 96 units/rail mc74ac138dtr2 tssop?16 soic?16 2500 tape & reel mc74act138n pdip?16 25 units/rail mc74act138d soic?16 48 units/rail mc74act138dr2 2500 tape & reel mc74act138dt tssop?16 96 units/rail mc74act138dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 127 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac138m eiaj?16 mc74ac138mel eiaj?16 2000 tape & reel mc74act138m eiaj?16 mc74act138mel eiaj?16 2000 tape & reel 50 units/rail 50 units/rail
mc74ac138, mc74act138 http://onsemi.com 123 functional description the mc74ac138/74act138 high?speed 1?of?8 decoder/demultiplexer accepts three binary weighted inputs (a 0 , a 1 , a 2 ) and, when enabled, provides eight mutually exclusive active?low outputs (o 0 ?o 7 ). the mc74ac138/74act138 features three enable inputs, two active?low (e 1 , e 2 ) and one active?high (e 3 ). all outputs will be high unless e 1 and e 2 are low and e 3 is high. this multiple enabled function allows easy parallel expansion of the device to a 1?of?32 (5 lines to 32 lines) decoder with just four mc74ac138/74act138 devices and one inverter (see figure 4). the mc74ac138/74act138 can be used as an 8?output demultiplexer by using one of the active low enable inputs as the data input and the other enable inputs as strobes. the enable inputs which are not used must be permanently tied to their appropriate active?high or active?low state. truth table inputs outputs e 1 e 2 e 3 a 0 a 1 a 2 o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 h x x x x x h h h h h h h h x h x x x x h h h h h h h h x x l x x x h h h h h h h h l l h l l l l h h h h h h h l l h h l l h l h h h h h h l l h l h l h h l h h h h h l l h h h l h h h l h h h h l l h l l h h h h h l h h h l l h h l h h h h h h l h h l l h l h h h h h h h h l h l l h h h h h h h h h h h l h = high voltage level l = low voltage level x = immaterial note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram
mc74ac138, mc74act138 http://onsemi.com 124 figure 4. expansion to 1?of?32 decoding maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac138, mc74act138 http://onsemi.com 125 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac138, mc74act138 http://onsemi.com 126 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 8.5 13.0 1.5 15.0 ns 3?6 t plh pg y a n to o n 5.0 1.5 6.5 9.5 1.5 10.5 ns 3 ? 6 t phl propagation delay 3.3 1.5 8.0 12.5 1.5 14.0 ns 3?6 t phl pg y a n to o n 5.0 1.5 6.0 9.0 1.5 10.5 ns 3 ? 6 t plh propagation delay 3.3 1.5 1 1.0 15.0 1.5 16.0 ns 3?6 t plh pg y e 1 or e 2 to o n 5.0 1.5 8.0 1 1.0 1.5 12.0 ns 3 ? 6 t phl propagation delay 3.3 1.5 9.5 13.5 1.5 15.0 ns 3?6 t phl pg y e 1 or e 2 to o n 5.0 1.5 7.0 9.5 1.5 10.5 ns 3 ? 6 t plh propagation delay 3.3 1.5 1 1.0 15.5 1.5 16.5 ns 3?6 t plh pg y e 3 to o n 5.0 1.5 8.0 1 1.0 1.5 12.5 ns 3 ? 6 t phl propagation delay 3.3 1.5 8.5 13.0 1.5 14.0 ns 3?6 t phl pg y e 3 to o n 5.0 1.5 6.0 8.0 1.0 9.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac138, mc74act138 http://onsemi.com 127 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 15 10 .5 1 .5 11 .5 ns 3 ? 6 t phl propagation delay 50 15 65 10 5 15 11 5 ns 3?6 t phl propagation delay a n to o n 5. 0 1 .5 6 .5 10 .5 1 .5 11 .5 ns 3 ? 6 t plh propagation delay 50 25 80 11 5 20 12 5 ns 3?6 t plh propagation delay e 1 or e 2 to o n 5. 0 2 .5 8 . 0 11 .5 2 . 0 12 .5 ns 3 ? 6 t phl propagation delay 50 20 75 11 5 20 12 5 ns 3?6 t phl propagation delay e 1 or e 2 to o n 5. 0 2 . 0 7.5 11 .5 2 . 0 12 .5 ns 3 ? 6 t plh propagation delay 50 25 80 12 0 20 13 0 ns 3?6 t plh propagation delay e 3 to o n 5. 0 2 .5 8 . 0 12 . 0 2 . 0 13 . 0 ns 3 ? 6 t phl propagation delay 50 20 65 10 5 15 11 5 ns 3?6 t phl propagation delay e 3 to o n 5. 0 2 . 0 6 .5 10 .5 1 .5 11 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 60 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac138 awl yww mc74ac138n aw l yyww ac 138 alyw act138 awl yww act 138 alyw mc74act138n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac138 alyw 74act138 alyw
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 128 publication order number: mc74ac139/d the mc74ac139/74act139 is a high?speed, dual 1?of?4 decoder/demultiplexer. the device has two independent decoders, each accepting two inputs and providing four mutually?exclusive active?low outputs. each decoder has an active?low enable input which can be used as a data input for a 4?output demultiplexer. each half of the mc74ac139/74act139 can be used as a function generator providing four minterms of two variables. ? multifunctional capability ? t wo completely independent 1?of?4 decoders ? active low mutually exclusive outputs ? outputs source/sink 24 ma ? act139 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin assignment pin function a 0 , a 1 address inputs e enable inputs o 0 ?o 3 outputs truth table inputs outputs e a 0 a 1 o 0 o 1 o 2 o 3 h x x h h h h l l l l h h h l h l h l h h l l h h h l h l h h h h h l h = high voltage level l = low voltage level x = immaterial http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac139n pdip?16 25 units/rail mc74ac139d soic?16 48 units/rail mc74ac139dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac139dt tssop?16 96 units/rail mc74ac139dtr2 tssop?16 soic?16 2500 tape & reel mc74act139n pdip?16 25 units/rail mc74act139d soic?16 48 units/rail mc74act139dr2 2500 tape & reel mc74act139dt tssop?16 96 units/rail soic?16 1 16 see general marking information in the device marking section on page 133 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac139m eiaj?16 mc74ac139mel eiaj?16 2000 tape & reel mc74act139m eiaj?16 mc74act139mel eiaj?16 2000 tape & reel 50 units/rail 50 units/rail
mc74ac139, mc74act139 http://onsemi.com 129 figure 2. logic symbol e note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram functional description the mc74ac139/74act139 is a high?speed dual 1?of?4 decoder/demultiplexer. the device has two independent decoders, each of which accepts two binary weighted inputs (a 0 ?a 1 ) and provides four mutually exclusive active?low outputs (o 0 ?o 3 ). each decoder has an active?low enable (e ). when e is high all outputs are forced high. the enable can be used as the data input for a 4?output demultiplexer application. each half of the mc74ac139/74act139 generates all four minterms of two variables. these four minterms are useful in some applications, replacing multiple gate functions as shown in figure 4, and thereby reducing the number of packages required in a logic network. e a 0 a 1 e a 0 a 1 e a 0 a 1 e a 0 a 1 e a 0 a 1 e a 0 a 1 e a 0 a 1 e a 0 a 1 o 0 o 0 o 1 o 1 o 2 o 2 o 3 o 3 figure 4. gate functions (each half)
mc74ac139, mc74act139 http://onsemi.com 130 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac139, mc74act139 http://onsemi.com 131 dc characteristics 74ac 74ac v cc t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v ih g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v pg 5.5 2.75 3.85 3.85 cc v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v il input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v pg 5.5 2.75 1.65 1.65 cc v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a oh g output voltage 4.5 4.49 4.4 4.4 v out pg 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a ol output voltage 4.5 0.001 0.1 0.1 v out pg 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd i in maximum input leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd i cc maximum quiescent supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac v cc * t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf fig symbol parameter v cc * (v) min typ max min max unit fi g. no. t plh propagation delay 3.3 4.0 8.0 1 1.5 3.5 13 ns 3?6 t plh pg y a n to o n 5.0 3.0 6.5 8.5 2.5 9.5 ns 3 ? 6 t phl propagation delay 3.3 3.0 7.0 10 2.5 11 ns 3?6 t phl pg y a n to o n 5.0 2.5 5.5 7.5 2.0 8.5 ns 3 ? 6 t plh propagation delay 3.3 4.5 9.5 12 3.5 13 ns 3?6 t plh pg y e n to o n 5.0 3.5 7.0 8.5 3.0 10 ns 3 ? 6 t phl propagation delay 3.3 4.0 8.0 10 3.0 11 ns 3?6 t phl pg y e n to o n 5.0 2.5 6.0 7.5 2.5 8.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac139, mc74act139 http://onsemi.com 132 dc characteristics 74act 74act v cc t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v ih g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v il input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a oh g output voltage 5.5 5.49 5.4 5.4 v out g *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a ol output voltage 5.5 0.001 0.1 0.1 v out g *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd i in maximum input leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd i cc maximum quiescent supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act v cc * t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf fig symbol parameter v cc * (v) min typ max min max unit fi g. no. t plh propagation delay 50 15 60 85 15 95 ns 3?6 t plh propagation delay a n to o n 5. 0 1 .5 6 . 0 8 .5 1 .5 9 .5 ns 3 ? 6 t phl propagation delay 50 15 60 95 15 10 5 ns 3?6 t phl propagation delay a n to o n 5. 0 1 .5 6 . 0 9 .5 1 .5 10 .5 ns 3 ? 6 t plh propagation delay 50 25 70 10 0 20 11 0 ns 3?6 t plh propagation delay e n to o n 5. 0 2 .5 7. 0 10 . 0 2 . 0 11 . 0 ns 3 ? 6 t phl propagation delay 50 20 70 95 15 10 5 ns 3?6 t phl propagation delay e n to o n 5. 0 2 . 0 7. 0 9 .5 1 .5 10 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 40 pf v cc = 5.0 v
mc74ac139, mc74act139 http://onsemi.com 133 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac139 awl yww mc74ac139n aw l yyww ac 139 alyw act139 awl yww act 139 alyw mc74act139n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac139 alyw 74act139 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 134 publication order number: mc74ac151/d the mc74ac151/74act151 is a high?speed 8?input digital multiplexer. it provides, in one package, the ability to select one line of data from up to eight sources. the mc74ac151/74act151 can be used as a universal function generator to generate any logic function of four variables. both true and complementary outputs are provided. ? outputs source/sink 24 ma ? act151 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin assignment pin function i 0 ?i 7 data inputs s 0 ?s 2 select inputs e enable input z data output z inverted data output truth table inputs outputs e s 2 s 1 s 0 z z h x x x h l l l l l i 0 i 0 l l l h i 1 i 1 l l h l i 2 i 2 l l h h i 3 i 3 l h l l i 4 i 4 l h l h i 5 i 5 l h h l i 6 i 6 l h h h i 7 i 7 h = high voltage level l = low voltage level x = immaterial http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac151n pdip?16 25 units/rail mc74ac151d soic?16 48 units/rail mc74ac151dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac151dt tssop?16 96 units/rail mc74ac151dtr2 tssop?16 soic?16 2500 tape & reel mc74act151n pdip?16 25 units/rail mc74act151d soic?16 48 units/rail mc74act151dr2 2500 tape & reel mc74act151dt tssop?16 96 units/rail mc74act151dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 140 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac151m eiaj?16 mc74act151m eiaj?16 50 units/rail 50 units/rail
mc74ac151, mc74act151 http://onsemi.com 135 figure 2. logic symbol functional description the mc74ac151/74act151 is a logic implementation of a single pole, 8?position switch with the switch position controlled by the state of three select inputs, s 0 , s 1 , s 2 . both true and complementary outputs are provided. the enable input (e ) is active low. when it is not activated, the complementary output is high and the true output is low regardless of all other inputs. the logic function provided at the output is: z = e ? (i 0 ? s 0 ? s 1 ? s 2 +i 1 ? s 0 ? s 1 ? s 2 + i 2 ? s 0 ? s 1 ? s 2 +i 3 ? s 0 ? s 1 ? s 2 + i 4 ? s 0 ? s 1 ? s 2 +i 5 ? s 0 ? s 1 ? s 2 + i 6 ? s 0 ? s 1 ? s 2 +i 7 ? s 0 ? s 1 ? s 2 ) the mc74ac151/74act151 provides the ability, in one package, to select from eight sources of data or control information. by proper manipulation of the inputs, the mc74ac151/74act151 can provide any logic function of four variables and its complement. figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
mc74ac151, mc74act151 http://onsemi.com 136 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac151, mc74act151 http://onsemi.com 137 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac151, mc74act151 http://onsemi.com 138 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 3.0 1 1.5 18.0 3.0 20.0 ns 3?6 t plh pg y s n to z or z 5.0 2.5 8.5 13.0 2.0 15.0 ns 3 ? 6 t phl propagation delay 3.3 2.5 12 18.0 2.5 20.0 ns 3?6 t phl pg y s n to z or z 5.0 2.0 8.5 13.0 1.5 15.0 ns 3 ? 6 t plh propagation delay 3.3 2.5 8.0 13.0 2.0 14.0 ns 3?6 t plh pg y e to z or z 5.0 2.0 6.0 10.0 1.5 1 1.0 ns 3 ? 6 t phl propagation delay 3.3 1.5 8.5 13.0 1.5 14.0 ns 3?6 t phl pg y e to z or z 5.0 1.5 6.5 10.0 1.5 1 1.0 ns 3 ? 6 t plh propagation delay 3.3 2.5 9.5 14.0 2.0 15.5 ns 3?5 t plh pg y i n to z or z 5.0 1.5 7.0 10.5 1.5 1 1.0 ns 3 ?5 t phl propagation delay 3.3 2.5 9.5 15.0 2.0 16.0 ns 3?5 t phl pg y i n to z or z 5.0 1.5 7.0 1 1.0 1.5 12.0 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v *voltage range 5.0 v is 5.0 v 0.5 v dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac151, mc74act151 http://onsemi.com 139 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 35 ? 15 5 30 17 0 ns 3?6 t plh propagation delay s n to z 5. 0 3 .5 ? 1 5.5 3 . 0 1 7. 0 ns 3 ? 6 t phl propagation delay 50 35 ? 15 5 30 16 5 ns 3?6 t phl propagation delay s n to z 5. 0 3 .5 ? 1 5.5 3 . 0 16 .5 ns 3 ? 6 t plh propagation delay 50 35 ? 15 30 16 5 ns 3?6 t plh propagation delay s n to z 5. 0 3 .5 ? 1 5 3 . 0 16 .5 ns 3 ? 6 t phl propagation delay 50 40 ? 16 5 35 18 5 ns 3?6 t phl propagation delay s n to z 5. 0 4 . 0 ? 16 .5 3 .5 18 .5 ns 3 ? 6 t plh propagation delay 50 25 ? 95 25 10 0 ns 3?6 t plh propagation delay e to z 5. 0 2 .5 ? 9 .5 2 .5 10 . 0 ns 3 ? 6 t phl propagation delay 50 25 ? 90 25 10 0 ns 3?6 t phl propagation delay e to z 5. 0 2 .5 ? 9 . 0 2 .5 10 . 0 ns 3 ? 6 t plh propagation delay 50 25 ? 85 25 95 ns 3?6 t plh propagation delay e to z 5. 0 2 .5 ? 8 .5 2 .5 9 .5 ns 3 ? 6 t phl propagation delay 50 30 ? 10 0 25 10 5 ns 3?6 t phl propagation delay e to z 5. 0 3 . 0 ? 10 . 0 2 .5 10 .5 ns 3 ? 6 t plh propagation delay 50 35 ? 11 5 30 12 5 ns 3?6 t plh propagation delay i n to z 5. 0 3 .5 ? 11 .5 3 . 0 12 .5 ns 3 ? 6 t phl propagation delay 50 35 ? 12 0 30 13 5 ns 3?6 t phl propagation delay i n to z 5. 0 3 .5 ? 12 . 0 3 . 0 13 .5 ns 3 ? 6 t plh propagation delay 50 35 ? 12 0 30 13 0 ns 3?6 t plh propagation delay i n to z 5. 0 3 .5 ? 12 . 0 3 . 0 13 . 0 ns 3 ? 6 t phl propagation delay 50 40 ? 12 5 30 14 0 ns 3?6 t phl propagation delay i n to z 5. 0 4 . 0 ? 12 .5 3 . 0 14 . 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 70 pf v cc = 5.0 v
mc74ac151, mc74act151 http://onsemi.com 140 marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac151 awl yww mc74ac151n aw l yyww ac 151 alyw act151 awl yww act 151 alyw mc74act151n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac151 alyw 74act151 alyw
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 141 publication order number: mc74ac153/d the mc74ac153/74act153 is a high?speed dual 4?input multiplexer with common select inputs and individual enable inputs for each section. it can select two lines of data from four sources. the two buffered outputs present data in the true (non?inverted) form. in addition to multiplexer operation, the mc74ac153/74act153 can act as a function generator and generate any two functions of three variables. ? outputs source/sink 24 ma ? act153 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin assignment pin function i 0a ?i 3a side a data inputs i 0b ?i 3b side b data inputs s 0 , s 1 common select inputs e a side a enable input e b side b enable input z a side a output z b side b output truth table select inputs inputs (a or b) output s 0 s 1 e i 0 i 1 i 2 i 3 z x x h x x x x l l l l l x x x l l l l h x x x h h l l x l x x l h l l x h x x h l h l x x l x l l h l x x h x h h h l x x x l l h h l x x x h h h = high voltage level l = low voltage level x = immaterial http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac153n pdip?16 25 units/rail mc74ac153d soic?16 48 units/rail mc74ac153dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac153dt tssop?16 96 units/rail mc74ac153dtr2 tssop?16 soic?16 2500 tape & reel mc74act153n pdip?16 25 units/rail mc74act153d soic?16 48 units/rail mc74act153dr2 2500 tape & reel mc74act153dt tssop?16 96 units/rail soic?16 1 16 see general marking information in the device marking section on page 146 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac153m eiaj?16 mc74ac153mel eiaj?16 2000 tape & reel mc74act153m eiaj?16 mc74act153mel eiaj?16 2000 tape & reel 50 units/rail 50 units/rail
mc74ac153, mc74act153 http://onsemi.com 142 figure 2. logic symbol functional description the mc74ac153/74act153 is a dual 4?input multiplexer. it can select two bits of data from up to four sources under the control of the common select inputs (s 0 , s 1 ). the two 4?input multiplexer circuits have individual active?low enables (e a ,e b ) which can be used to strobe the outputs independently. when the enables (e a , e b ) are high, the corresponding outputs (z a , z b ) are forced low. the mc74ac153/74act153 is the logic implementation of a 2?pole, 4?position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. the logic equations for the outputs are shown below. z a = e a ? (i 0a ? s 1 ? s 0 +i 1a ? s 1 ? s 0 +i 2a ? s 1 ? s 0 +i 3a ? s 1 ? s 0 ) z b = e b ? (i 0b ? s 1 ? s 0 +i 1b ? s 1 ? s 0 +i 2b ? s 1 ? s 0 +i 3b ? s 1 ? s 0 ) figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
mc74ac153, mc74act153 http://onsemi.com 143 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac153, mc74act153 http://onsemi.com 144 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac153, mc74act153 http://onsemi.com 145 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 2.5 9.5 15.0 2.5 17.5 ns 3?6 t plh pg y s n to z n 5.0 2.0 6.5 1 1.0 2.0 12.5 ns 3 ? 6 t phl propagation delay 3.3 3.0 8.5 14.5 2.5 16.5 ns 3?6 t phl pg y s n to z n 5.0 2.5 6.5 1 1.0 2.0 12.0 ns 3 ? 6 t plh propagation delay 3.3 2.5 8.0 13.5 2.0 16.0 ns 3?6 t plh pg y e n to z n 5.0 1.5 5.5 9.5 1.5 1 1.0 ns 3 ? 6 t phl propagation delay 3.3 2.5 7.0 1 1.0 2.0 12.5 ns 3?6 t phl pg y e n to z n 5.0 2.0 5.0 8.0 1.5 9.0 ns 3 ? 6 t plh propagation delay 3.3 2.5 7.5 12.5 2.0 14.5 ns 3?5 t plh pg y i n to z n 5.0 1.5 5.5 9.0 1.5 10.5 ns 3 ?5 t phl propagation delay 3.3 1.5 7.0 1 1.5 1.5 13.0 ns 3?5 t phl pg y i n to z n 5.0 1.5 5.0 8.5 1.5 10.0 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac153, mc74act153 http://onsemi.com 146 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 30 70 11 5 20 13 5 ns 3?6 t plh propagation delay s n to z n 5. 0 3 . 0 7. 0 11 .5 2 . 0 13 .5 ns 3 ? 6 t phl propagation delay 50 30 70 11 5 25 13 5 ns 3?6 t phl propagation delay s n to z n 5. 0 3 . 0 7. 0 11 .5 2 .5 13 .5 ns 3 ? 6 t plh propagation delay 50 20 65 10 5 20 12 5 ns 3?6 t plh propagation delay e n to z n 5. 0 2 . 0 6 .5 10 .5 2 . 0 12 .5 ns 3 ? 6 t phl propagation delay 50 30 60 95 25 11 0 ns 3?6 t phl propagation delay e n to z n 5. 0 3 . 0 6 . 0 9 .5 2 .5 11 . 0 ns 3 ? 6 t plh propagation delay 50 25 55 95 20 11 0 ns 3?5 t plh propagation delay i n to z n 5. 0 2 .5 5.5 9 .5 2 . 0 11 . 0 ns 3 ?5 t phl propagation delay 50 20 55 95 20 11 0 ns 3?5 t phl propagation delay i n to z n 5. 0 2 . 0 5.5 9 .5 2 . 0 11 . 0 ns 3 ?5 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 65 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac153 awl yww mc74ac153n aw l yyww ac 153 alyw act153 awl yww act 153 alyw mc74act153n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac153 alyw 74act153 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 147 publication order number: mc74ac157/d the mc74ac157/74act157 is a high?speed quad 2?input multiplexer. four bits of data from two sources can be selected using the common select and enable inputs. the four outputs present the selected data in the true (noninverted) form. the mc74ac157/74act157 can also be used as a function generator. ? outputs source/sink 24 ma ? act157 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin name pin function i 0a ?i 0d source 0 data inputs i 1a ?i 1d source 1 data inputs e enable input s select input z a ?z d outputs truth table inputs outputs e s i 0 i 1 z h x x x l l h x l l l h x h h l l l x l l l h x h h = high voltage level l = low voltage level x = immaterial http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac157n pdip?16 25 units/rail mc74ac157d soic?16 48 units/rail mc74ac157dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac157dt tssop?16 96 units/rail mc74ac157dtr2 tssop?16 soic?16 2500 tape & reel mc74act157n pdip?16 25 units/rail mc74act157d soic?16 48 units/rail mc74act157dr2 2500 tape & reel mc74act157dt tssop?16 96 units/rail mc74act157dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 152 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac157m eiaj?16 mc74ac157mel eiaj?16 2000 tape & reel mc74act157m eiaj?16 mc74act157mel eiaj?16 2000 tape & reel 50 units/rail 50 units/rail
mc74ac157, mc74act157 http://onsemi.com 148 figure 2. logic symbol functional description the mc74ac157/74act157 is a quad 2?input multiplexer. it selects four bits of data from two sources under the control of a common select input (s). the enable input (e ) is active?low. when e is high, all of the outputs (z) are forced low regardless of all other inputs. the mc74ac157/74act157 is the logic implementation of a 4?pole, 2?position switch where the position of the switch is determined by the logic levels supplied to the select input. the logic equations for the outputs are shown below: z a = e ? (i 1a ? s+i 0a ? s ) z b = e ? (i 1b ? s+i 0b ? s ) z c = e ? (i 1c ? s+i 0c ? s ) z d = e ? (i 1d ? s+i 0d ? s ) a common use of the mc74ac157/74act157 is the moving of data from two groups of registers to four common output busses. the particular register from which the data comes is determined by the state of the select input. a less obvious use is as a function generator. the mc74ac157/74act157 can generate any four of the sixteen different functions of two variables with one variable common. this is useful for implementing gating functions. figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
mc74ac157, mc74act157 http://onsemi.com 149 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac157, mc74act157 http://onsemi.com 150 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac157, mc74act157 http://onsemi.com 151 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 7.0 1 1.5 1.5 13.0 ns 3?6 t plh pg y s to z n 5.0 1.5 5.5 9.0 1.5 10.0 ns 3 ? 6 t phl propagation delay 3.3 1.5 6.5 1 1.0 1.5 12.0 ns 3?6 t phl pg y s to z n 5.0 1.5 5.0 8.5 1.0 9.5 ns 3 ? 6 t plh propagation delay 3.3 1.5 7.0 1 1.5 1.5 13.0 ns 3?6 t plh pg y e to z n 5.0 1.5 5.5 9.0 1.5 10.0 ns 3 ? 6 t phl propagation delay 3.3 1.5 6.5 1 1.0 1.5 12 ns 3?6 t phl pg y e n to z n 5.0 1.5 5.5 9.0 1.0 9.5 ns 3 ? 6 t plh propagation delay 3.3 1.5 5.0 8.5 1.0 9.0 ns 3?5 t plh pg y i n to z n 5.0 1.5 4.0 6.5 1.0 7.0 ns 3 ?5 t phl propagation delay 3.3 1.5 5.0 8.0 1.0 9.0 ns 3?5 t phl pg y i n to z n 5.0 1.5 4.0 6.5 1.0 7.0 ns 3 ?5 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac157, mc74act157 http://onsemi.com 152 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 20 ? 90 15 10 0 ns 3?6 t plh propagation delay s to z n 5. 0 2 . 0 ? 9 . 0 1 .5 10 . 0 ns 3 ? 6 t phl propagation delay 50 20 ? 95 20 10 5 ns 3?6 t phl propagation delay s to z n 5. 0 2 . 0 ? 9 .5 2 . 0 10 .5 ns 3 ? 6 t plh propagation delay 50 15 ? 10 15 11 5 ns 3?6 t plh propagation delay e n to z n 5. 0 1 .5 ? 10 1 .5 11 .5 ns 3 ? 6 t phl propagation delay 50 15 ? 85 10 90 ns 3?6 t phl propagation delay e n to z n 5. 0 1 .5 ? 8 .5 1 . 0 9 . 0 ns 3 ? 6 t plh propagation delay 50 15 ? 70 10 85 ns 3?5 t plh propagation delay i n to z n 5. 0 1 .5 ? 7. 0 1 . 0 8 .5 ns 3 ?5 t phl propagation delay 50 15 ? 75 10 85 ns 3?5 t phl propagation delay i n to z n 5. 0 1 .5 ? 7.5 1 . 0 8 .5 ns 3 ?5 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac157 awl yww mc74ac157n aw l yyww ac 157 alyw act157 awl yww act 157 alyw mc74act157n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac157 alyw 74act157 alyw
? semiconductor components industries, llc, 2002 august, 2002 ? rev. 6 153 publication order number: mc74ac161/d the mc74ac161/74act161 and mc74ac163/74act163 are high?speed synchronous modulo?16 binary counters. they are synchronously presettable for application in programmable dividers and have two types of count enable inputs plus a terminal count output for versatility in forming synchronous multistage counters. the mc74ac161/74act161 has an asynchronous master reset input that overrides all other inputs and forces the outputs low. the mc74ac163/74act163 has a synchronous reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. ? synchronous counting and loading ? high?speed synchronous expansion ? t ypical count rate of 125 mhz ? outputs source/sink 24 ma ? act161 and act163 have ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin assignment pin function cep count enable parallel input cet count enable trickle input cp clock pulse input mr ( 161) asynchronous master reset input sr ( 163) synchronous reset input p 0 ?p 3 parallel data inputs pe parallel enable input q 0 ?q 3 flip?flop outputs tc t erminal count output http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 see general marking information in the device marking section on page 163 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 see detailed ordering and shipping information in the package dimensions section on page 164 of this data sheet. ordering information
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 154 figure 2. logic symbol *mr for 161 *sr for 163 functional description the mc74ac161/act161 and mc74ac163/act163 count modulo?16 binary sequence. from state 15 (hhhh) they increment to state 0 (llll). the clock inputs of all flip?flops are driven in parallel through a clock buffer. thus all changes of the q outputs (except due to master reset of the 161) occur as a result of, and synchronous with, the low?to?high transition of the cp input signal. the circuits have four fundamental modes of operation, in order of precedence: asynchronous reset ( 161), synchronous reset ( 163), parallel load, count?up and hold. five control inputs ? master reset (mr , 161), synchronous reset (sr , 163), parallel enable (pe ), count enable parallel (cep) and count enable trickle (cet) ? determine the mode of operation, as shown in the mode select table. a low signal on mr overrides all other inputs and asynchronously forces all outputs low. a low signal on sr overrides counting and parallel loading and allows all outputs to go low on the next rising edge of cp. a low signal on pe overrides counting and allows information on the parallel data (p n ) inputs to be loaded into the flip?flops on the next rising edge of cp. with pe and mr ( 161) or sr ( 163) high, cep and cet permit counting when both are high. conversely, a low signal on either cep or cet inhibits counting. the mc74ac161/act161 and mc74ac163/act163 use d?type edge?triggered flip?flops and changing the sr , pe , cep and cet inputs when the cp is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of cp, are observed. the terminal count (tc) output is high when cet is high and counter is in state 15. to implement synchronous multistage counters, the tc outputs can be used with the cep and cet inputs in two different ways. please refer to the mc74ac568 data sheet. the tc output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip?flops, counters or registers. logic equations: count enable = cep ? cet ? pe tc = q 0 ? q 1 ? q 2 ? q 3 ? cet mode select table *sr pe cet cep action on the rising clock edge ( ) l x x x reset (clear) h lx x load (p n q n ) h hhh count (increment) h hl x no change (hold) h h x l no change (hold) *for 163 only h = high voltage level l = low voltage level x = immaterial figure 3. state diagram
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 155 p 0 p 1 p 2 p 3 163 figure 4. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 161 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 156 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 157 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac161 74ac161 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum count 3.3 70 111 ? 60 ? mhz 3?3 f max frequency 5.0 110 167 ? 95 ? mh z 3 ? 3 t plh propagation delay 3.3 2.0 7.0 12.0 1.5 13.5 ns 3?6 t plh cp to q n (pe input high or low) 5.0 1.5 5.0 9.0 1.0 9.5 ns 3 ? 6 t phl propagation delay 3.3 1.5 7.0 12.0 1.5 13.0 ns 3?6 t phl cp to q n (pe input high or low) 5.0 1.5 5.0 9.5 1.5 10.0 ns 3 ? 6 t plh propagation delay 3.3 3.0 9.0 15.0 2.5 16.5 ns 3?6 t plh cp to tc 5.0 2.0 6.0 10.5 1.5 1 1.5 ns 3 ? 6 t phl propagation delay 3.3 3.5 8.5 14.0 2.5 15.5 ns 3?6 t phl cp to tc 5.0 2.0 6.5 1 1.0 2.0 1 1.5 ns 3 ? 6 t plh propagation delay 3.3 2.0 5.5 9.5 1.5 1 1.0 ns 3?6 t plh cet to tc 5.0 1.5 3.5 6.5 1.0 7.5 ns 3 ? 6 t phl propagation delay 3.3 2.5 6.5 1 1.0 2.0 12.5 ns 3?6 t phl cet to tc 5.0 2.0 5.0 8.5 1.5 9.5 ns 3 ? 6 t phl propagation delay 3.3 2.0 6.0 12.0 1.5 13.5 ns 3?6 t phl mr to q n 5.0 1.5 5.5 9.5 1.5 10.0 ns 3 ? 6 t phl propagation delay 3.3 3.5 10.0 15.0 3.0 17.5 ns 3?6 t phl mr to tc 5.0 2.5 8.5 13.0 2.5 13.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac163 74ac163 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum count 3.3 70 95 ? 60 ? mhz 3?3 f max frequency 5.0 110 140 ? 95 ? mh z 3 ? 3 t plh propagation delay 3.3 2.0 7.5 12.5 1.5 13.5 ns 3?6 t plh cp to q n (pe input high or low) 5.0 1.5 5.5 9.0 1.0 9.5 ns 3 ? 6 t phl propagation delay 3.3 1.5 8.5 12.0 1.5 13.0 ns 3?6 t phl cp to q n (pe input high or low) 5.0 1.5 6.0 9.5 1.5 10.0 ns 3 ? 6 t plh propagation delay 3.3 3.0 9.5 15.0 2.5 16.5 ns 3?6 t plh cp to tc 5.0 2.0 7.0 10.5 1.5 1 1.5 ns 3 ? 6 t phl propagation delay 3.3 3.5 1 1.0 14.0 2.5 15.5 ns 3?6 t phl cp to tc 5.0 2.0 8.0 1 1.0 2.0 1 1.5 ns 3 ? 6 t plh propagation delay 3.3 2.0 7.5 9.5 1.5 1 1.0 ns 3?6 t plh cet to tc 5.0 1.5 5.5 6.5 1.0 7.5 ns 3 ? 6 t phl propagation delay 3.3 2.5 8.5 1 1.0 2.0 12.5 ns 3?6 t phl cet to tc 5.0 2.0 6.0 8.5 1.5 9.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 158 ac operating requirements 74ac161 74ac161 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 6.0 13.5 16.0 ns 3?9 t s p n to cp 5.0 3.5 8.5 10.5 ns 3 ? 9 t h hold time, high or low 3.3 ?7.0 ?1.0 ?0.5 ns 3?9 t h p n to cp 5.0 ?4.0 0 0 ns 3 ? 9 t s setup time, high or low 3.3 6.5 1 1.5 14.0 ns 3?9 t s pe to cp 5.0 4.0 7.5 8.5 ns 3 ? 9 t h hold time, high or low 3.3 ?6.0 0 0 ns 3?9 t h pe to cp 5.0 ?3.5 0.5 1.0 ns 3 ? 9 t s setup time, high or low 3.3 3.0 6.0 7.0 ns 3?9 t s cep or cet to cp 5.0 2.0 4.5 5.0 ns 3 ? 9 t h hold time, high or low 3.3 ?3.5 0 0 ns 3?9 t h cep or cet to cp 5.0 ?2.0 0 0.5 ns 3 ? 9 t clock pulse width (load) 3.3 2.0 3.5 4.0 ns 3?6 t w high or low 5.0 2.0 2.5 3.0 ns 3 ? 6 t clock pulse width (count) 3.3 2.0 4.0 4.5 ns 3?6 t w high or low 5.0 2.0 3.0 3.5 ns 3 ? 6 t mr pulse width low 3.3 3.0 5.5 7.5 ns 3?6 t w mr p u l se width , low 5.0 2.5 4.5 6.0 ns 3 ? 6 t rec recovery time 3.3 ?2.0 ?0.5 0 ns 3?9 t rec mr to cp 5.0 ?1.0 0 0.5 ns 3 ? 9 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 159 ac operating requirements 74ac163 74ac163 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 5.5 13.5 16.0 ns 3?9 t s p n to cp 5.0 4.0 8.5 10.5 ns 3 ? 9 t h hold time, high or low 3.3 ?7.0 ?1.0 ?0.5 ns 3?9 t h p n to cp 5.0 ?5.0 0 0 ns 3 ? 9 t s setup time, high or low 3.3 5.5 14 16.5 ns 3?9 t s sr to cp 5.0 4.0 9.5 1 1.0 ns 3 ? 9 t h hold time, high or low 3.3 ?7.5 ?1.0 ?0.5 ns 3?9 t h sr to cp 5.0 ?5.5 ?0.5 0 ns 3 ? 9 t s setup time, high or low 3.3 5.5 1 1.5 14.0 ns 3?9 t s pe to cp 5.0 4.0 7.5 8.5 ns 3 ? 9 t h hold time, high or low 3.3 ?7.5 ?1.0 ?0.5 ns 3?9 t h pe to cp 5.0 ?5.0 ?0.5 0 ns 3 ? 9 t s setup time, high or low 3.3 3.5 6.0 7.0 ns 3?9 t s cep or cet to cp 5.0 2.5 4.5 5.0 ns 3 ? 9 t h hold time, high or low 3.3 ?4.5 0 0 ns 3?9 t h cep or cet to cp 5.0 ?3.0 0 0.5 ns 3 ? 9 t clock pulse width (load) 3.3 3.0 3.5 4.0 ns 3?6 t w high or low 5.0 2.0 2.5 3.0 ns 3 ? 6 t clock pulse width (count) 3.3 3.0 4.0 4.5 ns 3?6 t w high or low 5.0 2.0 3.0 3.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 160 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 161 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act161 74act161 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum count 50 115 125 ? 100 ? mhz 3?3 f max maximum count frequency 5. 0 11 5 12 5 ? 100 ? mh z 3 ? 3 t plh propagation delay 50 15 80 95 15 10 5 ns 3?6 t plh propagation delay cp to q n (pe input high or low) 5. 0 1 .5 8 . 0 9 .5 1 .5 10 .5 ns 3 ? 6 t phl propagation delay 50 15 80 10 5 15 11 5 ns 3?6 t phl propagation delay cp or q n (pe input high or low) 5. 0 1 .5 8 . 0 10 .5 1 .5 11 .5 ns 3 ? 6 t plh propagation delay 50 20 11 0 11 0 15 12 5 ns 3?6 t plh propagation delay cp to tc 5. 0 2 . 0 11 . 0 11 . 0 1 .5 12 .5 ns 3 ? 6 t phl propagation delay 50 15 11 0 12 5 15 13 5 ns 3?6 t phl propagation delay cp to tc 5. 0 1 .5 11 . 0 12 .5 1 .5 13 .5 ns 3 ? 6 t plh propagation delay 50 15 75 85 15 10 0 ns 3?6 t plh propagation delay cet to tc 5. 0 1 .5 7.5 8 .5 1 .5 10 . 0 ns 3 ? 6 t phl propagation delay 50 15 80 95 15 10 5 ns 3?6 t phl propagation delay cet to tc 5. 0 1 .5 8 . 0 9 .5 1 .5 10 .5 ns 3 ? 6 t phl propagation delay 50 15 80 10 0 15 11 0 ns 3?6 t phl propagation delay mr to q n 5. 0 1 .5 8 . 0 10 . 0 1 .5 11 . 0 ns 3 ? 6 t phl propagation delay 50 25 10 0 13 5 20 14 5 ns 3?6 t phl propagation delay mr to tc 5. 0 2 .5 10 . 0 13 .5 2 . 0 14 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act163 74act163 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum count 50 120 140 ? 105 ? mhz 3?3 f max maximum count frequency 5. 0 120 140 ? 10 5 ? mh z 3 ? 3 t plh propagation delay 50 15 55 10 0 15 11 0 ns 3?6 t plh propagation delay cp to q n (pe input high or low) 5. 0 1 .5 5.5 10 . 0 1 .5 11 . 0 ns 3 ? 6 t phl propagation delay 50 15 60 11 0 15 12 0 ns 3?6 t phl propagation delay cp to q n (pe input high or low) 5. 0 1 .5 6 . 0 11 . 0 1 .5 12 . 0 ns 3 ? 6 t plh propagation delay 50 25 70 11 5 20 13 5 ns 3?6 t plh propagation delay cp to tc 5. 0 2 .5 7. 0 11 .5 2 . 0 13 .5 ns 3 ? 6 t phl propagation delay 50 30 80 13 5 20 15 0 ns 3?6 t phl propagation delay cp to tc 5. 0 3 . 0 8 . 0 13 .5 2 . 0 1 5. 0 ns 3 ? 6 t plh propagation delay 50 20 55 90 15 10 5 ns 3?6 t plh propagation delay cet to tc 5. 0 2 . 0 5.5 9 . 0 1 .5 10 .5 ns 3 ? 6 t phl propagation delay 50 20 60 10 0 20 11 0 ns 3?6 t phl propagation delay cet to tc 5. 0 2 . 0 6 . 0 10 . 0 2 . 0 11 . 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 162 ac operating requirements 74act161 74act161 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 70 95 11 5 ns 3?9 t s setup t ime, high or low p n to cp 5. 0 7. 0 9 .5 11 .5 ns 3 ? 9 t h hold time, high or low 50 ?3 0 0 0 ns 3?9 t h hold t ime, high or low p n to cp 5. 0 ? 3 . 0 0 0 ns 3 ? 9 t s setup time, high or low 50 60 85 95 ns 3?9 t s setup t ime, high or low pe to cp 5. 0 6 . 0 8 .5 9 .5 ns 3 ? 9 t h hold time, high or low 50 ?3 5 ?05 ?05 ns 3?9 t h hold t ime, high or low pe to cp 5. 0 ? 3 .5 ? 0 .5 ? 0 .5 ns 3 ? 9 t s setup time, high or low 50 40 55 65 ns 3?9 t s setup t ime, high or low cep or cet to cp 5. 0 4 . 0 5.5 6 .5 ns 3 ? 9 t h hold time, high or low 50 ?2 0 0 0 ns 3?9 t h hold t ime, high or low cep or cet to cp 5. 0 ? 2 . 0 0 0 ns 3 ? 9 t clock pulse width (load) 50 20 30 35 ns 3?6 t w clock pulse width (load) high or low 5. 0 2 . 0 3 . 0 3 .5 ns 3 ? 6 t clock pulse width (count) 50 20 30 35 ns 3?6 t w clock pulse width (count) high or low 5. 0 2 . 0 3 . 0 3 .5 ns 3 ? 6 t mr pulse width low 50 30 30 75 ns 3?6 t w mr p u l se width , low 5. 0 3 . 0 3 . 0 7.5 ns 3 ? 6 t rec recovery time 50 0 0 05 ns 3?9 t rec recovery t ime mr to cp 5. 0 0 0 0 .5 ns 3 ? 9 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 163 ac operating requirements 74act163 74act163 symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 40 10 0 12 0 ns 3?9 t s setup t ime, high or low p n to cp 5. 0 4 . 0 10 . 0 12 . 0 ns 3 ? 9 t h hold time, high or low 50 ?5 0 05 05 ns 3?9 t h hold t ime, high or low p n to cp 5. 0 ?5. 0 0 .5 0 .5 ns 3 ? 9 t s setup time, high or low 50 40 10 0 11 5 ns 3?9 t s setup t ime, high or low sr to cp 5. 0 4 . 0 10 . 0 11 .5 ns 3 ? 9 t h hold time, high or low 50 ?5 5 ?0 5 ?0 5 ns 3?9 t h hold t ime, high or low sr to cp 5. 0 ?5.5 ? 0 .5 ? 0 .5 ns 3 ? 9 t s setup time, high or low 50 40 85 10 5 ns 3?9 t s setup t ime, high or low pe to cp 5. 0 4 . 0 8 .5 10 .5 ns 3 ? 9 t h hold time, high or low 50 ?5 5 ?0 5 0 ns 3?9 t h hold t ime, high or low pe to cp 5. 0 ?5.5 ? 0 .5 0 ns 3 ? 9 t s setup time, high or low 50 25 55 65 ns 3?9 t s setup t ime, high or low cep or cet to cp 5. 0 2 .5 5.5 6 .5 ns 3 ? 9 t h hold time, high or low 50 ?3 0 0 05 ns 3?9 t h hold t ime, high or low cep or cet to cp 5. 0 ? 3 . 0 0 0 .5 ns 3 ? 9 t clock pulse width 50 20 35 35 ns 3?6 t w clock pulse width high or low 5. 0 2 . 0 3 .5 3 .5 ns 3 ? 6 t clock pulse width (count) 50 20 35 35 ns 3?6 t w clock pulse width (count) high or low 5. 0 2 . 0 3 .5 3 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v marking diagrams x= 1 or 3 a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac16x awl yww mc74ac16xn aw l yyww act16x awl yww mc74act16xn aw l yyww dip?16 so?16 eiaj?16 74ac16x alyw 74act16x alyw
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 164 ordering information device package shipping mc74ac161n pdip?16 25 units/rail mc74act161n pdip?16 25 units/rail mc74ac161d soic?16 48 units/rail mc74ac161dr2 soic?16 2500 tape & reel mc74act161d soic?16 48 units/rail mc74act161dr2 soic?16 2500 tape & reel mc74ac161m eiaj?16 50 units/rail mc74act161mel eiaj?16 2000 tape & reel mc74ac163n pdip?16 25 units/rail mc74act163n pdip?16 25 units/rail mc74ac163d soic?16 48 units/rail mc74ac163dr2 soic?16 2500 tape & reel mc74act163d soic?16 48 units/rail mc74act163dr2 soic?16 2500 tape & reel mc74ac163mel eiaj?16 2000 tape & reel mc74act163mel eiaj?16 2000 tape & reel
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 165 publication order number: mc74ac174/d the mc74ac174/74act174 is a high?speed hex d flip?flop. the device is used primarily as a 6?bit edge?triggered storage register. the information on the d inputs is transferred to storage during the low?to?high clock transition. the device has a master reset to simultaneously clear all flip?flops. ? outputs source/sink 24 ma ? act174 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin assignment pin function d 0 ?d 5 data inputs cp clock pulse input mr master reset input q 0 ?q 5 outputs truth table inputs output mr cp d q l x x l h h h h l l h l x q h = high voltage level l = low voltage level x = immaterial = low?to?high transition of clock http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac174n pdip?16 25 units/rail mc74ac174d soic?16 48 units/rail mc74ac174dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac174dt tssop?16 96 units/rail mc74ac174dtr2 tssop?16 soic?16 2500 tape & reel mc74act174n pdip?16 25 units/rail mc74act174d soic?16 48 units/rail mc74act174dr2 2500 tape & reel mc74act174dt tssop?16 96 units/rail soic?16 1 16 see general marking information in the device marking section on page 170 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac174m eiaj?16 mc74ac174mel eiaj?16 2000 tape & reel mc74act174m eiaj?16 mc74act174mel eiaj?16 2000 tape & reel 50 units/rail 50 units/rail
mc74ac174, mc74act174 http://onsemi.com 166 figure 2. logic symbol functional description the mc74ac174/74act174 consists of six e dge ?t ri gge re d d flip?flops with individual d inputs and q outputs. the clock (cp) and master reset (mr ) are common to all flip?flops. each d input?s state is transferred to the corresponding flip?flop?s output following the low?to?high clock (cp) transition. a low input to the master reset (mr ) will force all outputs low independent of clock or data inputs. the mc74ac174/ 74act174 is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions.
mc74ac174, mc74act174 http://onsemi.com 167 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac174, mc74act174 http://onsemi.com 168 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 90 100 ? 70 ? mhz 3?3 f max frequency 5.0 100 125 ? 100 ? mh z 3 ? 3 t plh propagation delay 3.3 2.0 9.0 1 1.5 1.5 12.5 ns 3?6 t plh cp to q n 5.0 1.5 6.0 8.5 1.0 9.5 ns 3 ? 6 t phl propagation delay 3.3 2.0 8.5 1 1.0 1.5 12.0 ns 3?6 t phl cp to q n 5.0 1.5 6.0 8.0 1.0 9.0 ns 3 ? 6 t phl propagation delay 3.3 2.5 9.0 1 1.5 2.0 12.5 ns 3?6 t phl mr to q n 5.0 1.5 7.0 9.0 1.5 10.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 2.5 6.5 7.0 ns 3?9 t s d n to cp 5.0 2.0 5.0 5.5 ns 3 ? 9 t h hold time, high or low 3.3 1.0 3.0 3.0 ns 3?9 t h d n to cp 5.0 0.5 3.0 3.0 ns 3 ? 9 t mr pulse width low 3.3 1.0 5.5 7.0 ns 3?6 t w mr p u l se width , low 5.0 1.0 5.0 5.0 ns 3 ? 6 t cp pulse width 3.3 1.0 5.5 7.0 ns 3?6 t w cp p u l se width 5.0 1.0 5.0 5.0 ns 3 ? 6 t rec recovery time 3.3 0 2.5 2.5 ns 3?6 t rec mr to cp 5.0 0 2.0 2.0 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac174, mc74act174 http://onsemi.com 169 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 50 165 ? ? 140 ? mhz 3?3 f max maximum clock frequency 5. 0 16 5 ? ? 140 ? mh z 3 ? 3 t plh propagation delay 50 15 ? 10 5 15 11 5 ns 3?6 t plh propagation delay cp to q n 5. 0 1 .5 ? 10 .5 1 .5 11 .5 ns 3 ? 6 t phl propagation delay 50 15 ? 10 5 15 11 5 ns 3?6 t phl propagation delay cp to q n 5. 0 1 .5 ? 10 .5 1 .5 11 .5 ns 3 ? 6 t phl propagation delay 50 15 ? 95 15 11 0 ns 3?6 t phl propagation delay mr to q n 5. 0 1 .5 ? 9 .5 1 .5 11 . 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac174, mc74act174 http://onsemi.com 170 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 ? 15 15 ns 3?9 t s setup t ime, high or low d n to cp 5. 0 ? 1 .5 1 .5 ns 3 ? 9 t h hold time, high or low 50 ? 20 20 ns 3?9 t h hold t ime, high or low d n to cp 5. 0 ? 2 . 0 2 . 0 ns 3 ? 9 t mr pulse width low 50 ? 30 35 ns 3?6 t w mr p u l se width , low 5. 0 ? 3 . 0 3 .5 ns 3 ? 6 t cp pulse width 50 ? 30 35 ns 3?6 t w cp pulse width high or low 5. 0 ? 3 . 0 3 .5 ns 3 ? 6 t rec recovery time 50 ? 05 05 ns 3?6 t rec recovery t ime mr to cp 5. 0 ? 0 .5 0 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 85 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac174 awl yww mc74ac174n aw l yyww ac 174 alyw act174 awl yww act 174 alyw mc74act174n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac174 alyw 74act174 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 171 publication order number: mc74ac175/d the mc74ac/act175 is a high?speed quad d flip?flop. the device is useful for general flip?flop requirements where clock and clear inputs are common. the information on the d inputs is transferred to storage during the low?to?high clock transition. the device has a master reset to simultaneously clear all flip?flops, when mr is low. the mc74ac/act175 consists of four edge?triggered d flip?flops with individual d inputs and q and q outputs. the clock (cp) and master reset (mr ) are common to all flip?flops. each d input?s state is transferred to the corresponding flip?flop?s output following the low?to?high clock (cp) transition. a low input to the master reset (mr ) will force all q outputs low and q outputs high independent of clock or data inputs. the mc74ac/act175 is useful for applications where the clock and master reset are common to all storage elements. ? outputs source/sink 24 ma ? act175 has ttl compatible inputs figure 1. pinout: 16?lead packages (top view) pin assignment pin function d 0 ? d 3 data inputs cp clock pulse input mr master reset input q 0 ? q 3 outputs q 0 ? q 3 outputs http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac175n pdip?16 25 units/rail mc74ac175d soic?16 48 units/rail mc74ac175dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac175dt tssop?16 96 units/rail mc74ac175dtr2 tssop?16 soic?16 2500 tape & reel mc74act175n pdip?16 25 units/rail mc74act175d soic?16 48 units/rail mc74act175dr2 2500 tape & reel mc74act175dt tssop?16 96 units/rail mc74act175dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 176 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac175m eiaj?16 50 units/rail
mc74ac175, mc74act175 http://onsemi.com 172 truth table inputs outputs mr cp d qn qn l x x l h h h h l h l l h h l x qn qn note: h = high voltage level, l = low voltage level x = immaterial = low?to?high transition of clock figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. figure 2. logic symbol
mc74ac175, mc74act175 http://onsemi.com 173 recommended operating conditions symbol parameter min typ min unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ? 50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ? 12 ma 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 ? 24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i oh 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac175, mc74act175 http://onsemi.com 174 dc characteristics (continued) symbol conditions unit 74ac 74ac v cc (v) parameter symbol conditions unit t a = ?40 c to +85 c t a = +25 c v cc (v) parameter symbol conditions unit guaranteed limits typ v cc (v) parameter i cc maximum quiescent 55 ? 80 80 a v in = v cc or gnd q supply current 5.5 ? 8 . 0 80 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 149 ? ? 139 ? mhz 3?3 f max frequency 5.0 187 ? ? 187 ? mh z 3 ? 3 t plh propagation delay 3.3 2.0 ? 12.0 2.0 13.5 ns 3?6 t plh pg y cp to q n or q n 5.0 1.5 ? 9.0 1.0 9.5 ns 3 ? 6 t phl propagation delay 3.3 2.5 ? 13.0 2.0 14.5 ns 3?6 t phl pg y cp to q n or q n 5.0 1.5 ? 9.5 1.5 10.5 ns 3 ? 6 t plh propagation delay 3.3 3.0 ? 12.5 2.5 13.5 ns 3?6 t plh pg y mr to q n 5.0 2.0 ? 9.0 1.5 10.0 ns 3 ? 6 t phl propagation delay 3.3 3.0 ? 1 1.0 2.5 12.5 ns 3?6 t phl pg y mr to q n 5.0 2.0 ? 8.5 1.5 9.0 ns 3 ? 6 ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s set?up time, high or low 3.3 ? 4.5 4.5 ns 3?9 t s d n to cp 5.0 ? 3.0 3.0 ns 3 ? 9 t h hold time, high or low 3.3 ? 1.0 1.0 ns 3?9 t h d n to cp 5.0 ? 1.0 1.0 ns 3 ? 9 t mr pulse width low 3.3 ? 4.5 4.5 ns 3?6 t w 5.0 ? 3.5 3.5 ns 3 ? 6 t cp pulse width 3.3 ? 4.5 5.0 ns 3?6 t w 5.0 ? 3.5 3.5 ns 3 ? 6 t rec recovery time 3.3 ? 0 0 ns 3?6 t rec mr to cp 5.0 ? 0 0 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac175, mc74act175 http://onsemi.com 175 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ? 50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 i oh ? 24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i oh 24 ma 5.5 ? 0.36 0.44 i oh 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in = v cc or gnd q supply current 5.5 ? 8 . 0 80 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 50 175 ? ? 145 ? mhz 3?3 f max maximum clock frequency 5. 0 1 75 ? ? 14 5 ? mh z 3 ? 3 t plh propagation delay 50 20 ? 10 0 15 11 0 ns 3?6 t plh propagation delay cp to q n 5. 0 2 . 0 ? 10 . 0 1 .5 11 . 0 ns 3 ? 6 t phl propagation delay 50 20 ? 11 0 15 12 0 ns 3?6 t phl propagation delay cp to q n 5. 0 2 . 0 ? 11 . 0 1 .5 12 . 0 ns 3 ? 6 t phl propagation delay 50 20 ? 95 15 10 5 ns 3?6 t phl propagation delay mr to q n or q n 5. 0 2 . 0 ? 9 .5 1 .5 10 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac175, mc74act175 http://onsemi.com 176 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s (h) set?up time, high or low 50 ? 2.0 2.0 ns 3?9 s (l) d n to cp 5. 0 ? 2.5 2.5 ns 3 ? 9 t h hold time, high or low 50 ? 10 10 ns 3?9 t h d n to cp 5. 0 ? 1 . 0 1 . 0 ns 3 ? 9 t mr pulse width, low 50 ? 30 40 ns 3?6 t w 5. 0 ? 3 . 0 4 . 0 ns 3 ? 6 t cp pulse width, 50 ? 30 35 ns 3?6 t w high or low 5. 0 ? 3 . 0 3 .5 ns 3 ? 6 t rec recovery time 50 ? 0 0 ns 3?6 t rec mr to cp 5. 0 ? 0 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 45.0 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac175 awl yww mc74ac175n aw l yyww ac 175 alyw act175 awl yww act 175 alyw mc74act175n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac175 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 177 publication order number: mc74ac240/d the mc74ac240/74act240 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved pc board density. ? 3?state outputs drive bus lines or buffer memory address registers ? outputs source/sink 24 ma ? act240 has ttl compatible inputs figure 1. pinout: 20?lead packages conductors (top view) truth table inputs outputs oe 1 d (pins 12, 14, 16, 18) l l h l h l h x z note: h = high voltage level l = low voltage level x = immaterial z = high impedance truth table inputs outputs oe 2 d (pins 3, 5, 7, 9) l l h l h l h x z note: h = high voltage level l = low voltage level x = immaterial z = high impedance http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac240n pdip?20 18 units/rail mc74act240n pdip?20 18 units/rail mc74ac240dw soic?20 38 units/rail mc74ac240dwr2 soic?20 1000 tape & reel mc74act240dw soic?20 38 units/rail mc 74a c t240dwr2 soic?20 1000 tape & reel mc74ac240dt tssop?20 75 units/rail mc74ac240dtr2 tssop?20 2500 tape & reel mc74act240dt tssop?20 75 units/rail mc 74a c t240dtr2 tssop?20 2500 tape & reel mc74ac240m eiaj?20 40 units/rail mc74ac240mel eiaj?20 2000 tape & reel mc74act240m eiaj?20 40 units/rail mc74act240mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 181 of this data sheet. device marking information
mc74ac240, mc74act240 http://onsemi.com 178 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac240, mc74act240 http://onsemi.com 179 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac240, mc74act240 http://onsemi.com 180 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 6.0 8.0 1.0 9.0 ns 3?5 t plh data to output 5.0 1.5 4.5 6.5 1.0 7.0 ns 3 ?5 t phl propagation delay 3.3 1.5 5.5 8.0 1.0 8.5 ns 3?5 t phl data to output 5.0 1.5 4.5 6.0 1.0 6.5 ns 3 ?5 t pzh output enable time 3.3 1.5 6.0 10.5 1.0 1 1.0 ns 3?7 t pzh o utput e na bl e ti me 5.0 1.5 5.0 7.0 1.0 8.0 ns 3 ?7 t pzl output enable time 3.3 1.5 7.0 10.0 1.0 1 1.0 ns 3?8 t pzl o utput e na bl e ti me 5.0 1.5 5.5 8.0 1.0 8.5 ns 3 ? 8 t phz output disable time 3.3 1.5 7.0 10.0 1.0 10.5 ns 3?7 t phz o utput di sa bl e ti me 5.0 1.5 6.5 9.0 1.0 9.5 ns 3 ?7 t plz output disable time 3.3 1.5 7.5 10.5 1.0 1 1.5 ns 3?8 t plz o utput di sa bl e ti me 5.0 1.5 6.5 9.0 1.0 9.5 ns 3 ? 8 *v oltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac240, mc74act240 http://onsemi.com 181 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 15 60 85 15 95 ns 3?5 t plh propagation delay data to output 5. 0 1 .5 6 . 0 8 .5 1 .5 9 .5 ns 3 ?5 t phl propagation delay 50 15 55 75 15 85 ns 3?5 t phl propagation delay data to output 5. 0 1 .5 5.5 7.5 1 .5 8 .5 ns 3 ?5 t pzh output enable time 5.0 1.5 7.0 8.5 1.0 9.5 ns 3?7 t pzl output enable time 5.0 2.0 7.0 9.5 1.5 10.5 ns 3?8 t phz output disable time 5.0 2.0 8.0 9.5 2.0 10.5 ns 3?7 t plz output disable time 5.0 2.5 6.5 10.0 2.0 10.5 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v ac 240 alyw ac240 aw l yyww mc74ac240n aw l yyww 74ac240 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 240 alyw act240 aw l yyww mc74act240n aw l yyww 74act240 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 182 publication order number: mc74ac244/d the mc74ac244/74act244 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved pc board density. ? 3?state outputs drive bus lines or buffer memory address registers ? outputs source/sink 24 ma ? act244 has ttl compatible inputs figure 1. pinout: 20?lead packages conductors (top view) truth table inputs outputs oe 1 d (pins 12, 14, 16, 18) l l l l h h h x z note: h = high voltage level l = low voltage level x = immaterial z = high impedance truth table inputs outputs oe 2 d (pins 3, 5, 7, 9) l l l l h h h x z note: h = high voltage level l = low voltage level x = immaterial z = high impedance http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac244n pdip?20 18 units/rail mc74act244n pdip?20 18 units/rail mc74ac244dw soic?20 38 units/rail mc74ac244dwr2 soic?20 1000 tape & reel mc74act244dw soic?20 38 units/rail mc74act244dwr2 soic?20 1000 tape & reel mc74ac244dt tssop?20 75 units/rail mc74ac244dtr2 tssop?20 2500 tape & reel mc74act244dt tssop?20 75 units/rail mc74act244dtr2 tssop?20 2500 tape & reel mc74ac244m eiaj?20 40 units/rail mc74ac244mel eiaj?20 2000 tape & reel mc74act244m eiaj?20 40 units/rail mc74act244mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 186 of this data sheet. device marking information
mc74ac244, mc74act244 http://onsemi.com 183 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac244, mc74act244 http://onsemi.com 184 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac244, mc74act244 http://onsemi.com 185 ac characteristics (for figures and waveforms ? see section 3) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 2.0 6.5 9.0 1.5 10.0 ns 3?5 t plh data to output 5.0 1.5 5.0 7.0 1.0 7.5 ns 3 ?5 t phl propagation delay 3.3 2.0 6.5 9.0 2.0 10.0 ns 3?5 t phl data to output 5.0 1.5 5.0 7.0 1.0 7.5 ns 3 ?5 t pzh output enable time 3.3 2.0 6.0 10.5 1.5 1 1.0 ns 3?7 t pzh o utput e na bl e ti me 5.0 1.5 5.0 7.0 1.5 8.0 ns 3 ?7 t pzl output enable time 3.3 2.5 7.5 10.0 2.0 1 1.0 ns 3?8 t pzl o utput e na bl e ti me 5.0 1.5 5.5 8.0 1.5 8.5 ns 3 ? 8 t phz output disable time 3.3 3.0 7.0 10.0 1.5 10.5 ns 3?7 t phz o utput di sa bl e ti me 5.0 2.5 6.5 9.0 1.0 9.5 ns 3 ?7 t plz output disable time 3.3 2.5 7.5 10.5 2.5 1 1.5 ns 3?8 t plz o utput di sa bl e ti me 5.0 2.0 6.5 9.0 2.0 9.5 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac244, mc74act244 http://onsemi.com 186 ac characteristics (for figures and waveforms ? see section 3) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 20 65 90 15 10 0 ns 3?5 t plh propagation delay data to output 5. 0 2 . 0 6 .5 9 . 0 1 .5 10 . 0 ns 3 ?5 t phl propagation delay 50 20 70 90 15 10 0 ns 3?5 t phl propagation delay data to output 5. 0 2 . 0 7. 0 9 . 0 1 .5 10 . 0 ns 3 ?5 t pzh output enable time 5.0 1.5 6.0 8.5 1.0 9.5 ns 3?7 t pzl output enable time 5.0 2.0 7.0 9.5 1.5 10.5 ns 3?8 t phz output disable time 5.0 2.0 7.0 9.5 1.5 10.5 ns 3?7 t plz output disable time 5.0 2.5 7.5 10.0 2.0 10.5 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v ac 244 alyw ac244 aw l yyww mc74ac244n aw l yyww 74ac244 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 244 alyw act244 aw l yyww mc74act244n aw l yyww 74act244 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 187 publication order number: mc74ac245/d the mc74ac245/74act245 contains eight non?inverting bidirectional buffers with 3?state outputs and is intended for bus?oriented applications. current sinking capability is 24 ma at both the a and b ports. the transmit/receive (t/r ) input determines the direction of data flow through the bidirectional transceiver. transmit (active?high) enables data from a ports to b ports; receive (active?low) enables data from b ports to a ports. the output enable input, when high, disables both a and b ports by placing them in a high z condition. ? noninverting buffers ? bidirectional data path ? a and b outputs source/sink 24 ma ? act245 has ttl compatible inputs figure 1. pin assignment pin function oe output enable input t/r t ransmit/receive input a 0 ?a 7 side a 3?state inputs or 3?state outputs b 0 ?b 7 side b 3?state inputs or 3?state outputs truth tables inputs outputs oe t/r outputs l l bus b data to bus a l h bus a data to bus b h x high z state h = high voltage level l = low voltage level x = immaterial http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac245n pdip?20 18 units/rail mc74act245n pdip?20 18 units/rail mc74ac245dw soic?20 38 units/rail mc74ac245dwr2 soic?20 1000 tape & reel mc74act245dw soic?20 38 units/rail mc74act245dwr2 soic?20 1000 tape & reel mc74ac245dt tssop?20 75 units/rail mc74ac245dtr2 tssop?20 2500 tape & reel mc74act245dt tssop?20 75 units/rail mc74act245dtr2 tssop?20 2500 tape & reel mc74ac245m eiaj?20 40 units/rail mc74ac245mel eiaj?20 2000 tape & reel mc74act245m eiaj?20 40 units/rail mc74act245mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 192 of this data sheet. device marking information
mc74ac245, mc74act245 http://onsemi.com 188 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac245, mc74act245 http://onsemi.com 189 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i ozt maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.6 6.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 0 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 . 0 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac245, mc74act245 http://onsemi.com 190 ac characteristics (for figures and waveforms ? see section 3) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 5.0 8.5 1.0 9.0 ns 3?5 t plh a n to b n or b n to a n 5.0 1.5 3.5 6.5 1.0 7.0 ns 3 ?5 t phl propagation delay 3.3 1.5 5.0 8.5 1.0 9.0 ns 3?5 t phl a n to b n or b n to a n 5.0 1.5 3.5 6.0 1.0 7.0 ns 3 ?5 t pzh output enable time 3.3 2.5 7.0 1 1.5 2.0 12.5 ns 3?7 t pzh o utput e na bl e ti me 5.0 1.5 5.0 8.5 1.0 9.0 ns 3 ?7 t pzl output enable time 3.3 2.5 7.5 12.0 2.0 13.5 ns 3?8 t pzl o utput e na bl e ti me 5.0 1.5 5.5 9.0 1.0 9.5 ns 3 ? 8 t phz output disable time 3.3 2.0 6.5 12.0 1.0 12.5 ns 3?7 t phz o utput di sa bl e ti me 5.0 1.5 5.5 9.0 1.0 10.0 ns 3 ?7 t plz output disable time 3.3 2.0 7.0 1 1.5 1.5 13.0 ns 3?8 t plz o utput di sa bl e ti me 5.0 1.5 5.5 9.0 1.0 10.0 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i ozt maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.6 6.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 0 a v in v cc or gnd i cc maximum quiescent supply current 5.5 ? 8.0 80.0 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac245, mc74act245 http://onsemi.com 191 ac characteristics (for figures and waveforms ? see section 3) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 15 40 75 15 80 ns 3?5 t plh propagation delay a n to b n or b n to a n 5. 0 1 .5 4 . 0 7.5 1 .5 8 . 0 ns 3 ?5 t phl propagation delay 50 15 40 80 10 90 ns 3?5 t phl propagation delay a n to b n or b n to a n 5. 0 1 .5 4 . 0 8 . 0 1 . 0 9 . 0 ns 3 ?5 t pzh output enable time 5.0 1.5 5.0 10 1.5 1 1.0 ns 3?7 t pzl output enable time 5.0 1.5 5.5 10 1.5 12.0 ns 3?8 t phz output disable time 5.0 1.5 5.5 10 1.0 1 1.0 ns 3?7 t plz output disable time 5.0 2.0 5.0 10 1.5 1 1.0 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c i/o input/output capacitance 15 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v
mc74ac245, mc74act245 http://onsemi.com 192 ac 245 alyw ac245 aw l yyww mc74ac245n aw l yyww 74ac245 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 245 alyw act245 aw l yyww mc74act245n aw l yyww 74act245 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 193 publication order number: mc74ac253/d the mc74ac253/74act253 is a dual 4?input multiplexer with 3?state outputs. it can select two bits of data from four sources using common select inputs. the outputs may be individually switched to a high impedance state with a high on the respective output enable (oe ) inputs, allowing the outputs to interface directly with bus oriented systems. ? multifunctional capability ? noninverting 3?state outputs ? outputs source/sink 24 ma ? act253 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin name pin function i 0a ?i 3a side a data inputs i 0b ?i 3b side b data inputs s 0 , s 1 common select inputs oe a side a output enable input oe b side b output enable input z a, z b 3?state outputs http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac253n pdip?16 25 units/rail mc74ac253d soic?16 48 units/rail mc74ac253dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac253dt tssop?16 96 units/rail mc74ac253dtr2 tssop?16 soic?16 2500 tape & reel mc74act253n pdip?16 25 units/rail mc74act253d soic?16 48 units/rail mc74act253dr2 2500 tape & reel mc74act253dt tssop?16 96 units/rail mc74act253dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 199 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac253m eiaj?16 mc74ac253mel eiaj?16 2000 tape & reel mc74act253m eiaj?16 mc74act253mel eiaj?16 2000 tape & reel 50 units/rail 50 units/rail
mc74ac253, mc74act253 http://onsemi.com 194 truth table select inputs data inputs output enable outputs s 0 s 1 i 0 i 1 i 2 i 3 oe z x x x x x x h z l l l x x x l l l l h x x x l h h l x l x x l l h l x h x x l h l h x x l x l l l h x x h x l h h h x x x l l l h h x x x h l h address inputs s 0 and s 1 are common to both sections. h = high voltage level l = low voltage level x = immaterial z = high impedance functional description the mc74ac253/74act253 contains two identical 4?input multiplexers with 3?state outputs. they select two bits from four sources selected by common select inputs (s 0 , s 1 ). the 4?input multiplexers have individual output enable (oe a , oe b ) inputs which, when high, force the outputs to a high impedance (high z) state. this device is the logic implementation of a 2?pole, 4?position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. the logic equations for the outputs are shown: z a = oe a ? (i 0a ? s 1 ? s 0 +i 1a ? s 1 ? s 0 + i 2a ? s 1 ? s 0 +i 3a ? s 1 ? s 0 ) z b = oe b ? (i 0b ? s 1 ? s 0 +i 1b ? s 1 ? s 0 + i 2b ? s 1 ? s 0 +i 3b ? s 1 ? s 0 ) if the outputs of 3?state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. designers should ensure that output enable signals to 3?state devices whose outputs are tied together are designed so that there is no overlap. note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram figure 2. logic symbol
mc74ac253, mc74act253 http://onsemi.com 195 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac253, mc74act253 http://onsemi.com 196 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac253, mc74act253 http://onsemi.com 197 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 2.0 ? 15.5 2.0 17.5 ns 3?6 t plh s n to z n 5.0 2.0 ? 1 1.0 1.5 12.5 ns 3 ? 6 t phl propagation delay 3.3 2.5 ? 16.0 2.0 18.0 ns 3?6 t phl s n to z n 5.0 2.0 ? 1 1.5 1.5 13.0 ns 3 ? 6 t plh propagation delay 3.3 1.5 ? 14.5 1.5 17.0 ns 3?5 t plh i n to z n 5.0 1.5 ? 10.0 1.5 1 1.5 ns 3 ?5 t phl propagation delay 3.3 2.0 ? 13.0 1.5 15.0 ns 3?5 t phl i n to z n 5.0 1.5 ? 9.5 1.5 1 1.0 ns 3 ?5 t pzh output enable time 3.3 1.5 ? 8.0 1.0 8.5 ns 3?7 t pzh o utput e na bl e ti me 5.0 1.5 ? 6.0 1.0 6.5 ns 3 ?7 t pzl output enable time 3.3 1.5 ? 8.0 1.0 9.0 ns 3?8 t pzl o utput e na bl e ti me 5.0 1.5 ? 6.0 1.0 7.0 ns 3 ? 8 t phz output disable time 3.3 2.0 ? 9.5 1.5 10.0 ns 3?7 t phz o utput di sa bl e ti me 5.0 2.0 ? 8.0 1.5 8.5 ns 3 ?7 t plz output disable time 3.3 1.5 ? 8.0 1.0 9.0 ns 3?8 t plz o utput di sa bl e ti me 5.0 1.5 ? 7.0 1.0 7.5 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac253, mc74act253 http://onsemi.com 198 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac253, mc74act253 http://onsemi.com 199 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 20 ? 11 5 20 13 0 ns 3?6 t plh propagation delay s n to z n 5. 0 2 . 0 ? 11 .5 2 . 0 13 . 0 ns 3 ? 6 t phl propagation delay 50 30 ? 13 0 25 14 5 ns 3?6 t phl propagation delay s n to z n 5. 0 3 . 0 ? 13 . 0 2 .5 14 .5 ns 3 ? 6 t plh propagation delay 50 25 ? 10 0 20 11 0 ns 3?5 t plh propagation delay i n to z n 5. 0 2 .5 ? 10 . 0 2 . 0 11 . 0 ns 3 ?5 t phl propagation delay 50 35 ? 11 0 30 12 5 ns 3?5 t phl propagation delay i n to z n 5. 0 3 .5 ? 11 . 0 3 . 0 12 .5 ns 3 ?5 t pzh output enable time 5.0 2.0 ? 7.5 1.5 8.5 ns 3?7 t pzl output enable time 5.0 2.0 ? 8.0 1.5 9.0 ns 3?8 t phz output disable time 5.0 3.0 ? 9.5 2.5 10.0 ns 3?7 t plz output disable time 5.0 2.5 ? 7.5 2.0 8.5 ns 3?8 *v oltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac157 awl yww mc74ac157n aw l yyww ac 157 alyw act157 awl yww act 157 alyw mc74act157n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac157 alyw 74act157 alyw
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 200 publication order number: mc74ac257/d the mc74ac257/74act257 is a quad 2?input multiplexer with 3?state outputs. four bits of data from two sources can be selected using a common data select input. the four outputs present the selected data in true (noninverted) form. the outputs may be switched to a high impedance state by placing a logic high on the common output enable (oe ) input, allowing the outputs to interface directly with bus?oriented systems. ? multiplexer expansion by tying outputs together ? noninverting 3?state outputs ? outputs source/sink 24 ma ? act257 has ttl compatible inputs figure 1. pinout: 16?lead packages conductors (top view) pin name pin function s common data select input oe 3?state output enable input i 0a ?i 0d data inputs from source 0 i 1a ?i 1d data inputs from source 1 z a ?z d 3?state multiplexer outputs truth table output enable select input data inputs outputs oe s i 0 i 1 z h x x x z l h x ll l h x hh l l l xl l l h x h h = high voltage level l = low voltage level x = immaterial z = high impedance http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac257n pdip?16 25 units/rail mc74ac257d soic?16 48 units/rail mc74ac257dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac257dt tssop?16 96 units/rail mc74ac257dtr2 tssop?16 soic?16 2500 tape & reel mc74act257n pdip?16 25 units/rail mc74act257d soic?16 48 units/rail mc74act257dr2 2500 tape & reel mc74act257dt tssop?16 96 units/rail mc74act257dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 206 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac257mel eiaj?16 2000 tape & reel mc74act257m eiaj?16 mc74act257mel eiaj?16 2000 tape & reel 50 units/rail
mc74ac257, mc74act257 http://onsemi.com 201 figure 2. logic symbol functional description the mc74ac257/74act257 is a quad 2?input multiplexer with 3?state outputs. it selects four bits of data from two sources under control of a common data select input. when the select input is low, the i 0x inputs are selected and when select is high, the i 1x inputs are selected. the data on the selected inputs appears at the outputs in true (noninverted) form. the device is the logic implementation of a 4?pole, 2?position switch where the position of the switch is determined by the logic levels supplied to the select input. the logic equations for the outputs are shown below: z a = oe ? (i 1a ? s+i 0a ? s ) z b = oe ? (i 1b ? s+i 0b ? s ) z c = oe ? (i 1c ? s+i 0c ? s ) z d = oe ? (i 1d ? s+i 0d ? s ) when the output enable input (oe ) is high, the outputs are forced to a high impedance state. if the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. designers should ensure the output enable signals to 3?state devices whose outputs are tied together are designed so there is no overlap. note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram
mc74ac257, mc74act257 http://onsemi.com 202 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac257, mc74act257 http://onsemi.com 203 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac257, mc74act257 http://onsemi.com 204 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 5.0 8.5 1.0 9.0 ns 3?5 t plh i n to z n 5.0 1.5 4.0 6.0 1.0 7.0 ns 3 ?5 t phl propagation delay 3.3 1.5 6.0 8.5 1.0 9.0 ns 3?5 t phl i n to z n 5.0 1.5 4.5 6.0 1.0 7.0 ns 3 ?5 t plh propagation delay 3.3 1.5 7.0 10.5 1.5 1 1.5 ns 3?6 t plh s to z n 5.0 1.5 5.0 7.5 1.0 8.5 ns 3 ? 6 t phl propagation delay 3.3 1.5 7.5 10.5 1.5 1 1.5 ns 3?6 t phl s to z n 5.0 1.5 5.5 7.5 1.0 8.5 ns 3 ? 6 t pzh output enable time 3.3 1.5 6.5 9.5 1.0 10.5 ns 3?7 t pzh o utput e na bl e ti me 5.0 1.5 5.0 7.5 1.0 8.5 ns 3 ?7 t pzl output enable time 3.3 1.5 5.5 9.0 1.0 10.0 ns 3?8 t pzl o utput e na bl e ti me 5.0 1.5 5.0 8.5 1.0 9.5 ns 3 ? 8 t phz output disable time 3.3 1.5 5.5 10.0 1.0 1 1.0 ns 3?7 t phz o utput di sa bl e ti me 5.0 1.5 5.0 9.0 1.0 10.0 ns 3 ?7 t plz output disable time 3.3 1.5 5.5 9.0 1.0 10.0 ns 3?8 t plz o utput di sa bl e ti me 5.0 1.5 5.0 8.0 1.0 9.0 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac257, mc74act257 http://onsemi.com 205 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac257, mc74act257 http://onsemi.com 206 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 15 50 70 10 75 ns 3?6 t plh propagation delay i n to z n 5. 0 1 .5 5. 0 7. 0 1 . 0 7.5 ns 3 ? 6 t phl propagation delay 50 20 60 75 15 85 ns 3?6 t phl propagation delay i n to z n 5. 0 2 . 0 6 . 0 7.5 1 .5 8 .5 ns 3 ? 6 t plh propagation delay 50 20 70 95 15 10 5 ns 3?6 t plh propagation delay s to z n 5. 0 2 . 0 7. 0 9 .5 1 .5 10 .5 ns 3 ? 6 t phl propagation delay 50 25 70 10 5 20 11 5 ns 3?6 t phl propagation delay s to z n 5. 0 2 .5 7. 0 10 .5 2 . 0 11 .5 ns 3 ? 6 t pzh output enable time 5.0 2.0 6.0 8.0 1.5 9.0 ns 3?7 t pzl output enable time 5.0 2.0 6.0 8.0 1.5 9.0 ns 3?8 t phz output disable time 5.0 2.5 6.5 9.0 1.5 10.0 ns 3?7 t plz output disable time 5.0 2.0 6.0 7.5 1.5 8.5 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac257 awl yww mc74ac257n aw l yyww ac 257 alyw act257 awl yww act 257 alyw mc74act257n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac257 alyw 74act257 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 207 publication order number: mc74ac259/d the mc74ac259/74act259 is a high?speed 8?bit addressable latch designed for general purpose storage applications in digital systems. it is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1?of?8 decoder and demultiplexer w ith active high outputs. the device also incorporates an active low common clear for resetting all latches, as well as an active low enable. it is functionally identical to the als259 8?bit addressable latch. ? serial?to?parallel conversion ? eight bits of storage with output of each bit available ? random (addressable) data entry ? active high demultiplexing or decoding capability ? easily expandable ? common clear figure 1. pinout: 16?lead packages conductors (top view) figure 2. logic symbol mode select table e mr mode l h addressable latch h h memory l l active high 8?channel demultiplexer h l clear h = high voltage level l = low voltage level http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 device package shipping ordering information mc74ac259n pdip?16 25 units/rail mc74ac259d soic?16 48 units/rail mc74ac259dr2 2500 tape & reel tssop?16 dt suffix case 948f mc74ac259dt tssop?16 96 units/rail mc74ac259dtr2 tssop?16 soic?16 2500 tape & reel mc74act259n pdip?16 25 units/rail mc74act259d soic?16 48 units/rail mc74act259dr2 2500 tape & reel mc74act259dt tssop?16 96 units/rail mc74act259dtr2 tssop?16 soic?16 2500 tape & reel 1 16 see general marking information in the device marking section on page 214 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 mc74ac259m eiaj?16 50 units/rail
mc74ac259, mc74act259 http://onsemi.com 208 mode select?function table o p eratin g inputs outputs operating mode mr e d a 0 a 1 a 2 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 master reset l h x x x x l l l l l l l l l l d l l l q = d l l l l l l l demultiplex l ldhll l q = d l l l l l l demultiplex (active high l ldlhl l lq = d l llll (active high decoder when ? ????? ? ??????? d eco d er w h en d = h ) ? ????? ? ??????? d = h) ? ????? ? ??????? l ldhhh l llllllq = d store h h x x x x q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 store (do nothing) h h x x x x q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 h l d l l l q = d q 1 q 2 q 3 q 4 q 5 q 6 q 7 h ldhll q 0 q = d q 2 q 3 q 4 q 5 q 6 q 7 addressable h ldlhl q 0 q 1 q = d q 3 q 4 q 5 q 6 q 7 add ressa bl e latch ? ????? ? ??????? latch ? ????? ? ??????? ? ????? ? ??????? h l d h h h q 0 q 1 q 2 q 3 q 4 q 5 q 6 q = d h = high voltage level l = low voltage level x = immaterial d = high or low data one setup time prior to the low?to?high enable transition q = lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. functional description the mc74ac259/74act259 has four modes of operation as shown in the mode selection table. in the addressable latch mode, data on the data line (d) is written into the addressed latch. the addressed latch will follow the data input with all non?addressed latches remaining in their previous states in the memory mode. all latches remain in their previous state and are unaffected by the data or address inputs. in the one?of?eight decoding or demultiplexing mode, the addressed output will follow the state of the d input with all other outputs in the low state. in the clear mode all outputs are low and unaffected by the address and data inputs. when operating the mc74ac/act259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. therefore, this should only be done while in the memory mode. the mode select function table summarizes the operations of the mc74ac/act259.
mc74ac259, mc74act259 http://onsemi.com 209 note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram
mc74ac259, mc74act259 http://onsemi.com 210 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac259, mc74act259 http://onsemi.com 211 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac259, mc74act259 http://onsemi.com 212 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 2.0 9.0 14.5 1.5 17.0 ns 3?5 t plh d n to q n 5.0 2.0 6.5 10.0 1.5 1 1.5 ns 3 ?5 t phl propagation delay 3.3 2.0 9.0 13.5 1.5 16.0 ns 3?5 t phl d n to q n 5.0 2.0 6.0 9.5 1.5 1 1.0 ns 3 ?5 t plh propagation delay 3.3 2.0 10.5 15.0 1.5 17.5 ns 3?6 t plh e to q n 5.0 2.0 7.0 10.5 1.5 12.5 ns 3 ? 6 t phl propagation delay 3.3 2.0 8.0 12.5 1.5 15.0 ns 3?6 t phl e to q n 5.0 2.0 7.5 9.0 1.5 1 1.0 ns 3 ? 6 t plh propagation delay 3.3 2.0 12.0 19.0 1.5 22.5 ns 3?6 t plh address to q n 5.0 2.0 8.0 13.0 1.5 15.5 ns 3 ? 6 t phl propagation delay 3.3 2.0 10.0 16.0 1.5 19.0 ns 3?6 t phl address to q n 5.0 2.0 7.0 1 1.0 1.5 13.0 ns 3 ? 6 t phl propagation delay 3.3 2.0 8.0 12.0 1.5 13.5 ns 3?7 t phl mr to q 5.0 2.0 6.0 9.0 1.5 10.0 ns 3 ?7 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 ? 3.5 4.5 ns 3?9 t s d n to e 5.0 ? 2.5 3.5 ns 3 ? 9 t h hold time, high or low 3.3 ? 2.5 2.5 ns 3?9 t h d n to e 5.0 ? 2.0 2.0 ns 3 ? 9 t s setup time 3.3 ? 7.0 9.0 ns 3?6 t s address to e 5.0 ? 4.0 6.0 ns 3 ? 6 t h hold time 3.3 ? 2.0 2.0 ns 3?6 t h address to e 5.0 ? 2.0 2.0 ns 3 ? 6 t minimum pulse 3.3 ? 6.0 6.5 ns 3?6 t w width m r 5.0 ? 5.5 6.0 ns 3 ? 6 t minimum pulse 3.3 ? 6.5 7.0 ns 3?6 t w width e 5.0 ? 5.5 6.0 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac259, mc74act259 http://onsemi.com 213 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 20 65 11 0 15 12 5 ns 3?5 t plh propagation delay d n to q n 5. 0 2 . 0 6 .5 11 . 0 1 .5 12 .5 ns 3 ?5 t phl propagation delay 50 20 70 10 5 15 12 0 ns 3?5 t phl propagation delay d n or q n 5. 0 2 . 0 7. 0 10 .5 1 .5 12 . 0 ns 3 ?5 t plh propagation delay 50 20 10 5 14 0 15 16 5 ns 3?6 t plh propagation delay e to q n 5. 0 2 . 0 10 .5 14 . 0 1 .5 16 .5 ns 3 ? 6 t phl propagation delay 50 20 90 12 0 15 14 0 ns 3?6 t phl propagation delay e or q n 5. 0 2 . 0 9 . 0 12 . 0 1 .5 14 . 0 ns 3 ? 6 t plh propagation delay 50 20 80 11 5 15 13 5 ns 3?6 t plh propagation delay address to q n 5. 0 2 . 0 8 . 0 11 .5 1 .5 13 .5 ns 3 ? 6 t phl propagation delay 50 20 60 10 0 15 12 0 ns 3?6 t phl propagation delay address to q n 5. 0 2 . 0 6 . 0 10 . 0 1 .5 12 . 0 ns 3 ? 6 t phl propagation delay 50 20 10 0 15 11 0 ns 3?7 t phl propagation delay mr to q 5. 0 2 . 0 10 . 0 1 .5 11 . 0 ns 3 ?7 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac259, mc74act259 http://onsemi.com 214 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 ? 30 40 ns 3?9 t s setup t ime, high or low d n to e 5. 0 ? 3 . 0 4 . 0 ns 3 ? 9 t h hold time, high or low 50 ? 25 25 ns 3?9 t h hold t ime, high or low d n to e 5. 0 ? 2 .5 2 .5 ns 3 ? 9 t s setup time 50 ? 45 65 ns 3?6 t s setup t ime address to e 5. 0 ? 4 .5 6 .5 ns 3 ? 6 t h hold time 50 ? 25 25 ns 3?6 t h hold t ime address to e 5. 0 ? 2 .5 2 .5 ns 3 ? 6 t minimum pulse 50 ? 70 75 ns 3?6 t w width mr 5. 0 ? 7. 0 7.5 ns 3 ? 6 t minimum pulse 50 ? 70 75 ns 3?6 t w width e 5. 0 ? 7. 0 7.5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50.0 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac259 awl yww mc74ac259n aw l yyww ac 259 alyw act259 awl yww act 259 alyw mc74act259n aw l yyww dip?16 so?16 tssop?16 eiaj?16 74ac259 alyw
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 215 publication order number: mc74ac273/d the mc74ac273/74act273 has eight edge-triggered d?type flip?flops with individual d inputs and q outputs. the common buffered clock (cp) and master reset (mr ) inputs load and reset (clear) all flip?flops simultaneously. the register is fully edge-triggered. the state of each d input, one setup time before the low?to?high clock transition, is transferred to the corresponding flip?flop?s q output. all outputs will be forced low independently of clock or data inputs by a low voltage level on the mr input. the device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. ? ideal buffer for mos microprocessor or memory ? eight edge-triggered d flip?flops ? buffered common clock ? buffered, asynchronous master reset ? see mc74ac377 for clock enable version ? see mc74ac373 for transparent latch version ? see mc74ac374 for 3-state version ? outputs source/sink 24 ma ? act273 has ttl compatible inputs figure 1. pinout: 20?lead packages conductors (top view) pin assignment pin function d 0 ?d 7 data inputs mr master reset cp clock pulse input q 0 ?q 7 data outputs http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac273n pdip?20 18 units/rail mc74act273n pdip?20 18 units/rail mc74ac273dw soic?20 38 units/rail mc74ac273dwr2 soic?20 1000 tape & reel mc74act273dw soic?20 38 units/rail mc74act273dwr2 soic?20 1000 tape & reel mc74ac273dt tssop?20 75 units/rail mc74ac273dtr2 tssop?20 2500 tape & reel mc74act273dt tssop?20 75 units/rail mc74act273dtr2 tssop?20 2500 tape & reel mc74ac273m eiaj?20 40 units/rail mc74ac273mel eiaj?20 2000 tape & reel mc74act273m eiaj?20 40 units/rail mc74act273mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 221 of this data sheet. device marking information
mc74ac273, mc74act273 http://onsemi.com 216 figure 2. logic symbol mode select-function table operating mode inputs outputs operating mode mr cp d n q n reset (clear) l x x l load 1 h h h load 0 h l l h = high voltage level l = low voltage level x = immaterial = low-to-high clock transition figure 3. logic diagram note: that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions.
mc74ac273, mc74act273 http://onsemi.com 217 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac273, mc74act273 http://onsemi.com 218 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 90 125 ? 75 ? mhz 3?3 f max frequency 5.0 140 175 ? 125 ? mh z 3 ? 3 t plh propagation delay 3.3 4.0 7.0 12.5 3.0 14.0 ns 3?6 t plh clock to output 5.0 3.0 5.5 9.0 2.5 10.0 ns 3 ? 6 t phl propagation delay 3.3 4.0 7.0 13.0 3.5 14.5 ns 3?6 t phl clock to output 5.0 3.0 5.0 10.0 2.5 1 1.0 ns 3 ? 6 t phl propagation delay 3.3 4.0 7.0 13.0 3.5 14.0 ns 3?6 t phl mr to output 5.0 3.0 5.0 10.0 2.5 10.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 3.5 5.5 6.0 ns 3?9 t s data to cp 5.0 2.5 4.0 4.5 ns 3 ? 9 t h hold time, high or low 3.3 ?2.0 0 0 ns 3?9 t h data to cp 5.0 ?1.0 1.0 1.0 ns 3 ? 9 t clock pulse width 3.3 3.5 5.5 6.0 ns 3?6 t w high or low 5.0 2.5 4.0 4.5 ns 3 ? 6 t mr pulse width 3.3 2.0 5.5 6.0 ns 3?6 t w high or low 5.0 1.5 4.0 4.5 ns 3 ? 6 t rec recovery time 3.3 1.5 3.5 4.5 ns 3?9 t rec mr to cp 5.0 1.0 2.0 3.0 ns 3 ? 9 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac273, mc74act273 http://onsemi.com 219 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 50 125 200 ? 125 ? mhz 3?3 f max maximum clock frequency 5. 0 12 5 200 ? 12 5 ? mh z 3 ? 3 t phl propagation delay 50 30 60 10 25 11 0 ns 3?6 t phl propagation delay clock to output 5. 0 3 . 0 6 . 0 10 2 .5 11 . 0 ns 3 ? 6 t plh propagation delay 50 30 65 11 25 12 0 ns 3?6 t plh propagation delay clock to output 5. 0 3 . 0 6 .5 11 2 .5 12 . 0 ns 3 ? 6 t phl propagation delay 50 30 70 11 25 11 5 ns 3?6 t phl propagation delay mr to output 5. 0 3 . 0 7. 0 11 2 .5 11 .5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac273, mc74act273 http://onsemi.com 220 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 30 45 50 ns 3?9 t s setup t ime, high or low data to cp 5. 0 3 . 0 4 .5 5. 0 ns 3 ? 9 t h hold time, high or low 50 ?2 5 20 20 ns 3?9 t h hold t ime, high or low data to cp 5. 0 ? 2 .5 2 . 0 2 . 0 ns 3 ? 9 t clock pulse width 50 25 40 45 ns 3?6 t w clock pulse width high or low 5. 0 2 .5 4 . 0 4 .5 ns 3 ? 6 t mr pulse width 50 25 40 45 ns 3?6 t w high or low 5. 0 2 .5 4 . 0 4 .5 ns 3 ? 6 t rec recovery time 50 ?1 0 20 30 ns 3?6 t rec recovery t ime mr to cp 5. 0 ? 1 . 0 2 . 0 3 . 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v
mc74ac273, mc74act273 http://onsemi.com 221 ac 273 alyw ac273 aw l yyww mc74ac273n aw l yyww 74ac273 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 273 alyw act273 aw l yyww mc74act273n aw l yyww 74act273 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 222 publication order number: mc74ac299/d the mc74ac299/74act299 is an 8?bit universal shift/storage register with 3?state outputs. four modes of operation are possible: hold (store), shift left, shift right and load data. the parallel load inputs and flip?flop outputs are multiplexed to reduce the total number of package pins. additional outputs are provided for flip?flops q 0 , q 7 to allow easy serial cascading. a separate active low master reset is used to reset the register. ? common parallel i/o for reduced pin count ? additional serial inputs and outputs for expansion ? four operating modes: shift left, shift right, load and store ? 3?state outputs for bus?oriented applications ? outputs source/sink 24 ma ? act299 has ttl compatible inputs figure 1. pinout: 20?lead packages conductors (top view) pin assignment pin function cp clock pulse input ds 0 serial data input for right shift ds 7 serial data input for left shift s 0 , s 1 mode select inputs mr asynchronous master reset oe 1 , oe 2 3?state output enable inputs i/o 0 ?i/o 7 parallel data inputs or 3?state parallel outputs q 0 , q 7 serial outputs http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e device package shipping ordering information mc74ac299n pdip?20 18 units/rail mc74act299n pdip?20 18 units/rail mc74ac299dw soic?20 38 units/rail mc74ac299dwr2 soic?20 1000 tape & reel mc74act299dw soic?20 38 units/rail mc74act299dwr2 soic?20 1000 tape & reel mc74ac299dt tssop?20 75 units/rail mc74ac299dtr2 tssop?20 2500 tape & reel mc74act299dt tssop?20 75 units/rail mc74act299dtr2 tssop?20 2500 tape & reel see general marking information in the device marking section on page 230 of this data sheet. device marking information
figure 3. logic diagram note: that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. mc74ac299, mc74act299 http://onsemi.com 223 figure 2. logic symbol
mc74ac299, mc74act299 http://onsemi.com 224 functional description the mc74ac299/74act299 contains eight edge?triggered d?type flip?flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. the type of operation is determined by s 0 and s 1 , as shown in the t ruth t able. all flip?flop outputs are brought out through 3?state buffers to separate i/o pins that also serve as data inputs in the parallel load mode. q 0 and q 7 are also brought out on other pins for expansion in serial shifting of longer words. a low signal on mr overrides the select and cp inputs and resets the flip?flops. all other state changes are initiated by the rising edge of the clock. inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of cp, are observed. a high signal on either oe 1 or oe 2 disables the 3 - state buf fers and puts the i/o pins in the high impedance state. in this condition the shift, hold, load and reset operations can still occur. the 3?state buffers are also disabled by high signals on both s 0 and s 1 in preparation for a parallel load operation. truth table inputs response mr s 1 s 0 cp response l x x x asynchronous reset; q 0 ?q 7 = low h h h parallel load; i/o n q n h l h shift rights; ds 0 q 0 , q 0 q 1 , etc. h h l shift left; ds 7 q 7 , q 7 q 6 , etc. h l l x hold h = high voltage level l = low voltage level x = immaterial = low-to-high transition maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac299, mc74act299 http://onsemi.com 225 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i ozt maximum 3?state current 55 ? 06 60 a v i (oe) = v il , v ih v i =v cc gnd current 5.5 ? 0 . 6 6 . 0 a v i = v cc , gnd v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum input 3.3 90 ? ? 80 ? mhz 3?3 f max frequency 5.0 130 ? ? 105 ? mh z 3 ? 3 t plh propagation delay 3.3 8.5 ? 20.5 7.0 22 ns 3?6 t plh cp to q 0 or q 7 5.0 5.5 ? 14 4.5 15 ns 3 ? 6 t phl propagation delay 3.3 8.5 ? 21.5 7.0 23 ns 3?6 t phl cp to q 0 or q 7 5.0 5.5 ? 14.5 5.0 16 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac299, mc74act299 http://onsemi.com 226 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) symbol fig. no. unit 74ac 74ac v cc * (v) parameter symbol fig. no. unit t a = ?40 c to +85 c c l = 50 pf t a = +25 c c l = 50 pf v cc * (v) parameter symbol fig. no. unit max min max typ min v cc * (v) parameter t plh propagation delay 3.3 9.0 ? 20.5 7.5 22.5 ns 3?6 t plh cp to i/o n 5.0 6.0 ? 14.5 5.0 16 ns 3 ? 6 t phl propagation delay 3.3 10 ? 23 8.5 24.5 ns 3?6 t phl cp to i/o n 5.0 6.5 ? 16 6.0 17.5 ns 3 ? 6 t phl propagation delay 3.3 9.0 ? 22.5 7.5 25.0 ns 3?6 t phl mr to q 0 or q 7 5.0 5.5 ? 15.5 5.0 17.0 ns 3 ? 6 t phl propagation delay 3.3 9.0 ? 21.5 7.5 24.0 ns 3?6 t phl mr to i/o n 5.0 5.5 ? 15.0 5.0 16.5 ns 3 ? 6 t pzh output enable time 3.3 7.0 ? 18 6.0 19.5 ns 3?7 t pzh oe to i/o n 5.0 4.5 ? 12.5 4.0 13.5 ns 3 ?7 t pzl output enable time 3.3 7.0 ? 18 6.0 20.5 ns 3?8 t pzl oe to i/o n 5.0 5.0 ? 12.5 4.0 14 ns 3 ? 8 t phz output disable time 3.3 6.5 ? 18.5 5.5 19.5 ns 3?7 t phz oe to i/o n 5.0 3.5 ? 14 3.0 15 ns 3 ?7 t plz output disable time 3.3 5.5 ? 17 4.5 19 ns 3?8 t plz oe to i/o n 5.0 3.5 ? 12.5 2.0 13.5 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 ? 8.0 8.5 ns 3?9 t s s 0 or s 1 to cp 5.0 ? 5.0 5.5 ns 3 ? 9 t h hold time, high or low 3.3 ? 0.5 0.5 ns 3?9 t h s 0 or s 1 to cp 5.0 ? 1.0 1.0 ns 3 ? 9 t s setup time, high or low 3.3 ? 5.5 6.0 ns 3?9 t s i/o n to cp 5.0 ? 3.5 4.0 ns 3 ? 9 t h hold time, high or low 3.3 ? 0 0 ns 3?9 t h i/o n to cp 5.0 ? 1.0 1.0 ns 3 ? 9 t s setup time, high or low 3.3 ? 6.5 7.0 ns 3?6 t s ds 0 or ds 7 to cp 5.0 ? 4.0 4.5 ns 3 ? 6 t h hold time, high or low 3.3 ? 0 0.5 ns 3?6 t h ds 0 or ds 7 to cp 5.0 ? 1.0 1.0 ns 3 ? 6 t cp pulse width low 3.3 ? 4.5 5.0 ns 3?6 t w cp p u l se wid t h , low 5.0 ? 3.5 3.5 ns 3 ? 6 t mr pulse width low 3.3 ? 4.5 5.0 ns 3?9 t w mr p u l se width , low 5.0 ? 3.5 3.5 ns 3 ? 9 t rec recovery time 3.3 ? 1.5 1.5 ns 3?9 t rec mr to cp 5.0 ? 1.5 1.5 ns 3 ? 9 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac299, mc74act299 http://onsemi.com 227 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i ozt maximum 3-state current 55 ? 06 60 a v i (oe) = v il , v ih v i =v cc gnd current 5.5 ? 0 . 6 6 . 0 a v i = v cc , gnd v o = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac299, mc74act299 http://onsemi.com 228 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum input 50 120 ? ? 110 ? mhz 3?3 f max maximum input frequency 5. 0 120 ? ? 110 ? mh z 3 ? 3 t plh propagation delay 50 40 ? 12 5 30 14 ns 3?6 t plh propagation delay cp to q 0 or q 7 5. 0 4 . 0 ? 12 .5 3 . 0 14 ns 3 ? 6 t phl propagation delay 50 40 ? 13 5 35 15 ns 3?6 t phl propagation delay cp to q 0 or q 7 5. 0 4 . 0 ? 13 .5 3 .5 1 5 ns 3 ? 6 t plh propagation delay 50 45 ? 12 5 45 13 5 ns 3?6 t plh propagation delay cp to i/o n 5. 0 4 .5 ? 12 .5 4 .5 13 .5 ns 3 ? 6 t phl propagation delay 50 50 ? 15 45 16 5 ns 3?6 t phl propagation delay cp to i/o n 5. 0 5. 0 ? 1 5 4 .5 16 .5 ns 3 ? 6 t phl propagation delay 50 40 ? 15 40 18 ns 3?6 t phl propagation delay mr to q 0 or q 7 5. 0 4 . 0 ? 1 5 4 . 0 18 ns 3 ? 6 t phl propagation delay 50 40 ? 14 5 35 17 5 ns 3?6 t phl propagation delay mr to i/o n 5. 0 4 . 0 ? 14 .5 3 .5 1 7.5 ns 3 ? 6 t pzh output enable time 50 25 ? 12 15 13 ns 3?7 t pzh output enable t ime oe to i/o n 5. 0 2 .5 ? 12 1 .5 13 ns 3 ?7 t pzl output enable time 50 20 ? 12 15 13 5 ns 3?8 t pzl output enable t ime oe to i/o n 5. 0 2 . 0 ? 12 1 .5 13 .5 ns 3 ? 8 t phz output disable time 50 20 ? 12 5 20 13 5 ns 3?7 t phz output disable t ime oe to i/o n 5. 0 2 . 0 ? 12 .5 2 . 0 13 .5 ns 3 ?7 t plz output disable time 50 25 ? 11 5 20 12 5 ns 3?8 t plz output disable t ime oe to i/o n 5. 0 2 .5 ? 11 .5 2 . 0 12 .5 ns 3 ? 8 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac299, mc74act299 http://onsemi.com 229 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 ? 50 55 ns 3?9 t s setup t ime, high or low s 0 or s 1 to cp 5. 0 ? 5. 0 5.5 ns 3 ? 9 t h hold time, high or low 50 ? 10 10 ns 3?9 t h hold t ime, high or low s 0 or s 1 to cp 5. 0 ? 1 . 0 1 . 0 ns 3 ? 9 t s setup time, high or low 50 ? 40 45 ns 3?9 t s setup t ime, high or low i/o n to cp 5. 0 ? 4 . 0 4 .5 ns 3 ? 9 t h hold time, high or low 50 ? 10 10 ns 3?9 t h hold t ime, high or low i/o n to cp 5. 0 ? 1 . 0 1 . 0 ns 3 ? 9 t s setup time, high or low 50 ? 45 50 ns 3?6 t s setup t ime, high or low ds 0 or ds 7 to cp 5. 0 ? 4 .5 5. 0 ns 3 ? 6 t h hold time, high or low 50 ? 10 10 ns 3?6 t h hold t ime, high or low ds 0 or ds 7 to cp 5. 0 ? 1 . 0 1 . 0 ns 3 ? 6 t cp pulse width 50 ? 40 45 ns 3?9 t w cp pulse width high or low 5. 0 ? 4 . 0 4 .5 ns 3 ? 9 t mr pulse width low 50 ? 35 35 ns 3?9 t w mr p u l se width , low 5. 0 ? 3 .5 3 .5 ns 3 ? 9 t rec recovery time 50 ? 15 15 ns 3?9 t rec recovery t ime mr to cp 5. 0 ? 1 .5 1 .5 ns 3 ? 9 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 170 pf v cc = 5.0 v
mc74ac299, mc74act299 http://onsemi.com 230 ac 299 alyw ac299 aw l yyww mc74ac299n aw l yyww marking diagrams pdip?20 so?20 tssop?20 act 299 alyw act299 aw l yyww mc74act299n aw l yyww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 6 231 publication order number: mc74ac373/d the mc74ac373/74act373 consists of eight latches with 3?state outputs for bus organized system applications. the flip?flops appear transparent to the data when latch enable (le) is high. when le is low , the data that meets the setup time is latched. data appears on the bus when the output enable (oe ) is low. when oe is high, the bus output is in the high impedance state. ? eight latches in a single package ? 3?state outputs for bus interfacing ? outputs source/sink 24 ma ? act373 has ttl compatible inputs figure 1. pinout: 20?lead packages conductors (top view) pin assignment pin function d 0 ?d 7 data inputs le latch enable input oe output enable input o 0 ?o 7 3?state latch outputs figure 2. logic symbol http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac373n pdip?20 18 units/rail mc74act373n pdip?20 18 units/rail mc74ac373dw soic?20 38 units/rail mc74ac373dwr2 soic?20 1000 tape & reel mc74act373dw soic?20 38 units/rail mc74act373dwr2 soic?20 1000 tape & reel mc74ac373dt tssop?20 75 units/rail mc74ac373dtr2 tssop?20 2500 tape & reel mc74act373dt tssop?20 75 units/rail mc74act373dtr2 tssop?20 2500 tape & reel mc74ac373m eiaj?20 40 units/rail mc74ac373mel eiaj?20 2000 tape & reel mc74act373m eiaj?20 40 units/rail mc74act373mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 238 of this data sheet. device marking information
mc74ac373, mc74act373 http://onsemi.com 232 truth table inputs outputs oe le d n o n h x x z l h l l l h h h l l x o 0 h = high voltage level l = low voltage level z = high impedance x = immaterial o 0 = previous o 0 before low-to-high transition of clock functional description the mc74ac373/74act373 contains eight d?type la tc he s with 3?state standard outputs. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d input changes. when le is low, the latches store the information that was present on the d inputs a setup time preceding the high?to?low transition of le. the 3-state standard outputs are controlled by the output enable (oe ) input. when oe is low, the standard outputs are in the 2?state mode. when oe is high, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
mc74ac373, mc74act373 http://onsemi.com 233 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac373, mc74act373 http://onsemi.com 234 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac373, mc74act373 http://onsemi.com 235 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 1.5 10 13.5 1.5 15 ns 3?5 t plh d n to o n 5.0 1.5 7.0 9.5 1.5 10.5 ns 3 ?5 t phl propagation delay 3.3 1.5 9.5 13 1.5 14.5 ns 3?5 t phl d n to o n 5.0 1.5 7.0 9.5 1.5 10.5 ns 3 ?5 t plh propagation delay 3.3 1.5 10 13.5 1.5 15 ns 3?6 t plh le to o n 5.0 1.5 7.5 9.5 1.5 10.5 ns 3 ? 6 t phl propagation delay 3.3 1.5 9.5 12.5 1.5 14 ns 3?6 t phl le to o n 5.0 1.5 7.0 9.5 1.5 10.5 ns 3 ? 6 t pzh output enable time 3.3 1.5 9.0 1 1.5 1.0 13 ns 3?7 t pzh o utput e na bl e ti me 5.0 1.5 7.0 8.5 1.0 9.5 ns 3 ?7 t pzl output enable time 3.3 1.5 8.5 1 1.5 1.0 13 ns 3?8 t pzl o utput e na bl e ti me 5.0 1.5 6.5 8.5 1.0 9.5 ns 3 ? 8 t phz output disable time 3.3 1.5 10 12.5 1.0 14.5 ns 3?7 t phz o utput di sa bl e ti me 5.0 1.5 8.0 11 1.0 12.5 ns 3 ?7 t plz output disable time 3.3 1.5 8.0 1 1.5 1.0 12.5 ns 3?8 t plz o utput di sa bl e ti me 5.0 1.5 6.5 8.5 1.0 10 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 3.5 5.5 6.0 ns 3?9 t s d n to le 5.0 2.0 4.0 4.5 ns 3 ? 9 t h hold time, high or low 3.3 ?3.0 1.0 1.0 ns 3?9 t h d n to le 5.0 ?1.5 1.0 1.0 ns 3 ? 9 t le pulse width high 3.3 4.0 5.5 6.0 ns 3?6 t w le p u l se wid t h , high 5.0 2.0 4.0 4.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac373, mc74act373 http://onsemi.com 236 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac373, mc74act373 http://onsemi.com 237 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 25 85 10 15 11 5 ns 3?5 t plh propagation delay d n to o n 5. 0 2 .5 8 .5 10 1 .5 11 .5 ns 3 ?5 t phl propagation delay 50 20 80 10 15 11 5 ns 3?5 t phl propagation delay d n to o n 5. 0 2 . 0 8 . 0 10 1 .5 11 .5 ns 3 ?5 t plh propagation delay 50 25 85 11 20 11 5 ns 3?6 t plh propagation delay le to o n 5. 0 2 .5 8 .5 11 2 . 0 11 .5 ns 3 ? 6 t phl propagation delay 50 20 80 10 15 11 5 ns 3?6 t phl propagation delay le to o n 5. 0 2 . 0 8 . 0 10 1 .5 11 .5 ns 3 ? 6 t pzh output enable time 5.0 2.0 8.0 9.5 1.5 10.5 ns 3?7 t pzl output enable time 5.0 2.0 7.5 9.0 1.5 10.5 ns 3?8 t phz output disable time 5.0 2.5 9.0 11 2.5 12.5 ns 3?7 t plz output disable time 5.0 1.5 7.5 8.5 1.0 10 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 30 70 80 ns 3?9 t s setup t ime, high or low d n to le 5. 0 3 . 0 7. 0 8 . 0 ns 3 ? 9 t h hold time, high or low 50 0 0 10 ns 3?9 t h hold t ime, high or low d n to le 5. 0 0 0 1 . 0 ns 3 ? 9 t le pulse width high 50 20 70 80 ns 3?6 t w le p u l se wid t h , high 5.0 2.0 7.0 8.0 ns 3?6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 40 pf v cc = 5.0 v
mc74ac373, mc74act373 http://onsemi.com 238 ac 373 alyw ac373 aw l yyww mc74ac373n aw l yyww 74ac373 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 373 alyw act373 aw l yyww mc74act373n aw l yyww 74act373 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 239 publication order number: mc74ac374/d the mc74ac374/74act374 is a high?speed, low?power octal d?type flip?flop featuring separate d?type inputs for each flip?flop and 3?state outputs for bus?oriented applications. a buffered clock (cp) and output enable (oe ) are common to all flip?flops. ? buffered positive edge?triggered clock ? 3?state outputs for bus?oriented applications ? outputs source/sink 24 ma ? see mc74ac273 for reset version ? see mc74ac377 for clock enable version ? see mc74ac373 for transparent latch version ? see mc74ac574 for broadside pinout version ? see mc74ac564 for broadside pinout version with inverted outputs ? act374 has ttl compatible inputs figure 1. pinout: 20 lead packages conductors (top view) pin assignment pin function d 0 ?d 7 data inputs cp clock pulse input oe 3?state output enable input o 0 ?o 7 3?state outputs figure 2. logic symbol 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac374n pdip?20 18 units/rail mc74act374n pdip?20 18 units/rail mc74ac374dw soic?20 38 units/rail mc74ac374dwr2 soic?20 1000 tape & reel mc74act374dw soic?20 38 units/rail mc74act374dwr2 soic?20 1000 tape & reel mc74ac374dt tssop?20 75 units/rail mc74act374dt tssop?20 75 units/rail mc74act374dtr2 tssop?20 2500 tape & reel mc74ac374m eiaj?20 40 units/rail mc74ac374mel eiaj?20 2000 tape & reel mc74act374m eiaj?20 40 units/rail mc74act374mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 245 of this data sheet. device marking information http://onsemi.com
mc74ac374, mc74act374 http://onsemi.com 240 truth table inputs outputs d n cp oe o n h l h l l l x x h z h = high voltage level l = low voltage level x = immaterial z = high impedance = low-to-high transition functional description the mc74ac374/74act374 consists of eight edge? triggered flip?flops with individual d?type inputs and 3?state true outputs. the buffered clock and buf fered output enable are common to all flip?flops. the eight flip?flops will store the state of their individual d inputs that meet the setup and hold time requirements on the low?to?high clock (cp) transition. with the output enable (oe ) low, the contents of the eight flip?flops are available at the outputs. when the oe is high, the outputs go to the high impedance state. operation of the oe input does not affect the state of the flip?flops. figure 3. logic diagram note: that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions.
mc74ac374, mc74act374 http://onsemi.com 241 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions y (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac374, mc74act374 http://onsemi.com 242 dc characteristics (continued) symbol conditions unit 74ac 74ac v cc (v) parameter symbol conditions unit t a = ?40 c to +85 c t a = +25 c v cc (v) parameter symbol conditions unit guaranteed limits typ v cc (v) parameter i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 60 110 ? 60 ? mhz 3?3 f max frequency 5.0 100 155 ? 100 ? mh z 3 ? 3 t plh propagation delay 3.3 3.0 11 13.5 1.5 15.5 ns 3?6 t plh cp to o n 5.0 2.5 8.0 9.5 1.5 10.5 ns 3 ? 6 t phl propagation delay 3.3 2.5 10 12.5 2.0 14 ns 3?6 t phl cp to o n 5.0 2.0 7.0 9.0 1.5 10 ns 3 ? 6 t pzh output enable time 3.3 3.0 9.5 1 1.5 1.5 13 ns 3?7 t pzh o utput e na bl e ti me 5.0 2.0 7.0 8.5 1.0 9.5 ns 3 ?7 t pzl output enable time 3.3 2.5 9.0 1 1.5 1.5 13 ns 3?8 t pzl o utput e na bl e ti me 5.0 2.0 6.5 8.5 1.0 9.5 ns 3 ? 8 t phz output disable time 3.3 3.0 10.5 12.5 2.0 14.5 ns 3?7 t phz o utput di sa bl e ti me 5.0 2.0 8.0 11 2.0 12.5 ns 3 ?7 t plz output disable time 3.3 2.0 8.0 1 1.5 1.0 12.5 ns 3?8 t plz o utput di sa bl e ti me 5.0 1.5 6.5 8.5 1.0 10 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 2.0 5.5 6.0 ns 3?9 t s d n to cp 5.0 1.0 4.0 4.5 ns 3 ? 9 t h hold time, high or low 3.3 ?1.0 1.0 1.0 ns 3?9 t h d n to cp 5.0 0 1.5 1.5 ns 3 ? 9 t cp pulse width 3.3 4.0 5.5 6.0 ns 3?6 t w high or low 5.0 2.5 4.0 4.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac374, mc74act374 http://onsemi.com 243 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 50 100 160 ? 90 ? mhz 3?3 f max maximum clock frequency 5. 0 100 160 ? 90 ? mh z 3 ? 3 t plh propagation delay 50 20 85 10 20 11 5 ns 3?6 t plh propagation delay cp to o n 5. 0 2 . 0 8 .5 10 2 . 0 11 .5 ns 3 ? 6 t phl propagation delay 50 20 80 95 15 11 ns 3?6 t phl propagation delay cp to o n 5. 0 2 . 0 8 . 0 9 .5 1 .5 11 ns 3 ? 6 t pzh output enable time 5.0 2.0 8.0 9.5 1.5 10.5 ns 3?7 t pzl output enable time 5.0 1.5 8.0 9.0 1.5 10.5 ns 3?8 t phz output disable time 5.0 1.5 8.5 1 1.5 1.0 12.5 ns 3?7 t plz output disable time 5.0 1.5 7.0 8.5 1.0 10 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac374, mc74act374 http://onsemi.com 244 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 10 50 55 ns 3?9 t s setup t ime, high or low d n to cp 5. 0 1 . 0 5. 0 5.5 ns 3 ? 9 t h hold time, high or low 50 0 15 15 ns 3?9 t h hold t ime, high or low d n to cp 5. 0 0 1 .5 1 .5 ns 3 ? 9 t cp pulse width 50 25 50 50 ns 3?6 t w cp pulse width high or low 5. 0 2 .5 5. 0 5. 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 80 pf v cc = 5.0 v
mc74ac374, mc74act374 http://onsemi.com 245 ac 374 alyw ac374 aw l yyww mc74ac374n aw l yyww 74ac374 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 374 alyw act374 aw l yyww mc74act374n aw l yyww 74act374 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 7 246 publication order number: mc74ac377/d the mc74ac377/74act377 has eight edge-triggered, d-type flip-flops with individual d inputs and q outputs. the common buffered clock (cp) input loads all flip-flops simultaneously, when the clock enable (ce ) is low. the register is fully edge-triggered. the state of each d input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop?s q output. the ce input must be stable only one setup time prior to the low-to-high clock transition for predictable operation. ? ideal for addressable register applications ? clock enable for address and data synchronization applications ? eight edge-triggered d flip-flops ? buffered common clock ? outputs source/sink 24 ma ? see mc74ac273 for master reset version ? see mc74ac373 for transparent latch version ? see mc74ac374 for 3-state version ? act377 has ttl compatible inputs ? msl = 1 for all surface mount ? chip complexity: 292 fets or 73 gates 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 see general marking information in the device marking section on page 253 of this data sheet. device marking information see detailed ordering and shipping information in the package dimensions section on page 252 of this data sheet. ordering information http://onsemi.com
mc74ac377, mc74act377 http://onsemi.com 247 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 o 7 d 7 d 6 o 6 o 5 d 5 d 4 o 4 cp ce o 0 d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd figure 1. pinout: 20?lead packages conductors (top view) figure 2. logic symbol o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 cp ce pin names pin function d 0 ?d 7 data inputs ce clock enable (active low) q 0 ?q 7 data outputs cp clock pulse input mode select-function table operating mode inputs outputs operating mode cp ce d n q n load 1 l h h load 0 l l l hold (do nothing) h x no change h o ld (d o n ot hi ng ) x h x no change h = high voltage level l = low voltage level x = immaterial = low-to-high clock transition please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram dq cp dq cp dq cp dq cp dq cp dq cp dq cp dq cp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 ce cp
mc74ac377, mc74act377 http://onsemi.com 248 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c ja thermal resistance (junction to ambient) soic, dw tssop, dt pdip, n 97 129 69 c/w v esd esd withstand voltage human body model (note 1) machine model (note 2) charged device model (note 3) > 2000 > 200 > 1000 v i latch?up latch?up performance v cc = 5.5 v; ta = 125 c (note 4) > 100 ma *m aximum ratings are those values beyond which damage to the devi ce may occur. functional operation should be restricted to the recommended operating conditions. 1. tested to eia/jesd22?a114?a 2. tested to eia/jesd22?a115?a 3. tested to jesd22?c101?a 4. tested to eia/jesd78 recommended operating conditions symbol parameter min typ max unit v cc supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v itri df ll ti (n t 5) v cc @ 3.0 v 150 t r , t f input rise and fall time (note 5) ac devices exce p t schmitt in p uts v cc @ 4.5 v 40 ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v 25 tt f input rise and fall time (note 6) v cc @ 4.5 v 10 ns/v t r , t f input rise and fall t ime (note 6) act devices except schmitt inputs v cc @ 5.5 v 8.0 ns/v t j junction temperature (pdip) 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ?24 ma i ol output current ? low 24 ma 5. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 6. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac377, mc74act377 http://onsemi.com 249 74ac ? dc characteristics t a = +25 c t a = t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level input voltage 3.0 4.5 5.5 1.50 2.25 2.75 2.10 3.15 3.85 2.10 3.15 3.85 v v v v out = 0.1 v or v cc ? 0.1 v v il maximum low level input voltage 3.0 4.5 5.5 1.50 2.25 2.75 0.90 1.35 1.65 0.90 1.35 1.65 v v v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 v v v i out = ?50 a 3.0 4.5 5.5 2.56 3.86 4.86 2.46 3.76 4.76 v v v *v in = v il or v ih ?12 ma i oh ?24 ma ?24 ma v ol maximum low level output voltage 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 v v v i out = 50 a 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 v v v *v in = v il or v ih ?12 ma i oh ?24 ma ?24 ma i in maximum input leakage current 5.5 0.1 1.0 a v i = v cc , gnd i old i ohd maximum input leakage current 5.5 5.5 75 ?75 ma ma v old = 1.65 v max v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . 74ac ? ac characteristics for figures and waveforms, see figures 4, 5, and 6. t a = +25 c t a = ?40 c to +85 c t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf symbol parameter v cc * (v) min typ max min max unit f max maximum clock frequency 3.3 5.0 90 140 75 125 mhz t plh propagation delay cp to q n 3.3 5.0 3.0 2.0 13.0 9.0 1.5 1.5 14.0 10.0 ns t phl propagation delay cp to q n 3.3 5.0 3.5 2.5 13.0 10.0 2.0 1.5 14.5 1 1.0 ns *v oltage range 3.3 v is 3.3 v 0.3 v; voltage range 5.0 v is 5.0 v 0.5 v. 74ac ? ac operating requirements t a = +25 c t a = ?40 c to +85 c t a = +25 c c l = 50 pf t a = 40 c to +85 c symbol parameter v cc * (v) typ guaranteed minimum unit t s setup time, high or low d n to cp 3.3 5.0 5.5 4.0 6.0 4.5 ns t h hold time, high or low d n to cp 3.3 5.0 0 1.0 0 1.0 ns t s setup time, high or low ce to cp 3.3 5.0 6.0 4.0 7.5 4.5 ns t h hold time, high or low ce to cp 3.3 5.0 0 1.0 0 1.0 ns t w cp pulse width high or low 3.3 5.0 5.5 4.0 6.0 4.5 ns *v oltage range 3.3 v is 3.3 v 0.3 v; voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac377, mc74act377 http://onsemi.com 250 74act ? dc characteristics t a = t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level input voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 v v out = 0.1 v or v cc ? 0.1 v v il maximum low level input voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 v i out = ?50 a 4.5 5.5 3.86 4.86 3.76 4.76 v *v in = v il or v ih ?24 ma i oh ?24 ma v ol maximum low level output voltage 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 v i out = 50 a 4.5 5.5 0.36 0.36 0.44 0.44 v *v in = v il or v ih ?24 ma i oh ?24 ma i in maximum input leakage current 5.5 0.1 1.0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1 v i old i ohd ?minimum dynamic output current 5.5 75 ?75 ma v old = 1.65 v max v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. 74act ? ac characteristics for figures and waveforms ? see figures 4, 5, and 6. t a = +25 c t a = ?40 c to +85 c t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf symbol parameter v cc * (v) min typ max min max unit f max maximum clock frequency 5.0 140 125 mhz t plh propagation delay cp to q n 5.0 3.0 9.0 2.5 10 ns t phl propagation delay cp to q n 5.0 3.5 10 2.5 11 ns *voltage range 5.0 v is 5.0 v 0.5 v. 74act ? ac operating requirements t a = +25 c t a = ?40 c to +85 c t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf symbol parameter v cc * (v) typ guaranteed minimum unit t s setup time, high or low d n to cp 5.0 4.5 5.5 ns t h hold time, high or low d n to cp 5.0 1.0 1.0 ns t s setup time, high or low ce to cp 5.0 4.5 5.5 ns t h hold time, high or low ce to cp 5.0 1.0 1.0 ns t w cp pulse width high or low 5.0 4.0 4.5 ns *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac377, mc74act377 http://onsemi.com 251 capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 90 pf v cc = 5.0 v switching waveforms figure 4. clock q t r t f v cc gnd 50% 50% t plh t phl 50% data clock v cc figure 5. v alid gnd *includes all probe and jig capacitance c l * 50 scope test point device under test output figure 6. t w 1/f max v cc gnd t su t h 50% figure 7. test circuit 450 50% ce clock v cc v cc gnd t su t h 50%
mc74ac377, mc74act377 http://onsemi.com 252 ordering information device package shipping mc74ac377n pdip?20 18 units/rail mc74act377n pdip?20 18 units/rail mc74ac377dw soic?20 38 units/rail mc74ac377dwr2 soic?20 1000 tape & reel mc74act377dw soic?20 38 units/rail mc74act377dwr2 soic?20 1000 tape & reel mc74ac377dt tssop?20 75 units/rail mc74ac377dtr2 tssop?20 2500 tape & reel mc74act377dt tssop?20 75 units/rail mc74ac377m eiaj?20 40 units/rail mc74act377m eiaj?20 40 units/rail mc74act377mel eiaj?20 2000 tape & reel
mc74ac377, mc74act377 http://onsemi.com 253 ac 377 alyw ac377 aw l yyww mc74ac377n aw l yyww 74ac377 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 377 alyw act377 aw l yyww mc74act377n aw l yyww 74act377 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2002 july, 2002 ? rev. 6 254 publication order number: mc74ac540/d the mc74ac540/74act540 and mc74ac541/74act541 are octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. the mc74ac541/74act541 is a noninverting option of the mc74ac540/74act540. these devices are similar in function to the mc74ac240/74act240 and mc74ac244/74act244 while providing flow?through architecture (inputs on opposite side from outputs). this pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater pc board density. ? 3?state outputs ? inputs and outputs opposite side of package, allowing easier interface to microprocessors ? outputs source/sink 24 ma ? mc74ac540/74act540 provides inverted outputs ? mc74ac541/74act541 provides noninverted outputs ? act540 and act541 have ttl compatible inputs truth table inputs outputs oe 1 oe 2 d 540 541 l h x l l x h l h x x l l z z h h z z l h = high voltage level l = low voltage level x = immaterial z = high impedance 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 see general marking information in the device marking section on page 262 of this data sheet. device marking information see detailed ordering and shipping information in the package dimensions section on page 261 of this data sheet. ordering information http://onsemi.com
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 255 figure 1. mc74ac540/74act540 figure 2. mc74ac541/74act541 maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions.
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 256 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1.) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2. ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2 . ) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 257 dc characteristics 74ac 74ac v cc t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v ih g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v pg 5.5 2.75 3.85 3.85 cc v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v il input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 cc v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a oh g output voltage 4.5 4.49 4.4 4.4 v out pg 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a ol output voltage 4.5 0.001 0.1 0.1 v pg 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd i in maximum input leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih oz 3-state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd i cc maximum quiescent supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 258 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac v cc * t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf fig symbol parameter v cc * (v) min typ max min max unit fi g. no. t plh propagation delay 3.3 1.5 5.5 7.5 1.0 8.0 ns 3?5 t plh data to output ( ac540) 5.0 1.5 4.0 6.0 1.0 6.5 ns 3 ?5 t phl propagation delay 3.3 1.5 5.0 7.0 1.0 7.5 ns 3?5 t phl data to output ( ac540) 5.0 1.5 4.0 5.5 1.0 6.0 ns 3 ?5 t pzh output enable time 3.3 3.0 8.5 11 2.5 12 ns 3?7 t pzh ( ac540) 5.0 2.0 6.5 8.5 2.0 9.5 ns 3 ?7 t pzl output enable time 3.3 2.5 7.5 10 2.0 11 ns 3?8 t pzl ( ac540) 5.0 2.0 6.0 7.5 1.5 8.5 ns 3 ? 8 t phz output disable time 3.3 2.5 8.5 13 1.5 14 ns 3?7 t phz ( ac540) 5.0 1.5 7.5 10.5 1.0 11 ns 3 ?7 t plz output disable time 3.3 2.0 7.0 10 2.0 11 ns 3?8 t plz p ( ac540) 5.0 1.5 6.0 8.0 1.5 9.0 ns 3 ? 8 t plh propagation delay 3.3 2.0 5.5 8.0 1.5 9.0 ns 3?5 t plh pg y data to output ( ac541) 5.0 1.5 4.0 6.0 1.0 6.5 ns 3 ?5 t phl propagation delay 3.3 2.0 5.5 8.0 1.5 8.5 ns 3?5 t phl pg y data to output ( ac541) 5.0 1.5 4.0 6.0 1.0 6.5 ns 3 ?5 t pzh output enable time 3.3 3.0 8.0 1 1.5 3.0 12.5 ns 3?7 t pzh p ( ac541) 5.0 2.0 6.0 8.5 1.5 9.5 ns 3 ?7 t pzl output enable time 3.3 2.5 7.0 10 2.5 1 1.5 ns 3?8 t pzl p ( ac541) 5.0 1.5 5.5 7.5 1.0 8.5 ns 3 ? 8 t phz output disable time 3.3 3.5 9.0 12.5 2.5 14 ns 3?7 t phz p ( ac541) 5.0 2.0 7.0 9.5 1.0 10.5 ns 3 ?7 t plz output disable time 3.3 2.5 6.5 9.5 2.0 10.5 ns 3?8 t plz p ( ac541) 5.0 2.0 5.5 7.5 1.0 8.5 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 259 dc characteristics 74act 74act v cc t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v ih g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v il input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a oh g output voltage 5.5 5.49 5.4 5.4 v g *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a ol output voltage 5.5 0.001 0.1 0.1 v g *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd i in maximum input leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih oz 3-state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd i cc maximum quiescent supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 260 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 10 ? 70 10 75 ns 3?5 t plh propagation delay data to output ( act540) 5. 0 1 . 0 ? 7. 0 1 . 0 7.5 ns 3 ?5 t phl propagation delay 50 10 ? 80 10 85 ns 3?5 t phl propagation delay data to output ( act540) 5. 0 1 . 0 ? 8 . 0 1 . 0 8 .5 ns 3 ?5 t pzh output enable time 50 10 ? 10 5 10 11 5 ns 3?7 t pzh output enable t ime ( act540) 5. 0 1 . 0 ? 10 .5 1 . 0 11 .5 ns 3 ?7 t pzl output enable time 50 10 ? 95 10 10 5 ns 3?8 t pzl output enable t ime ( act540) 5. 0 1 . 0 ? 9 .5 1 . 0 10 .5 ns 3 ? 8 t phz output disable time 50 10 ? 12 0 10 12 5 ns 3?7 t phz output disable t ime ( act540) 5. 0 1 . 0 ? 12 . 0 1 . 0 12 .5 ns 3 ?7 t plz output disable time 50 15 ? 90 10 10 ns 3?8 t plz output disable t ime ( act540) 5. 0 1 .5 ? 9 . 0 1 . 0 10 ns 3 ? 8 t plh propagation delay 50 15 ? 75 10 80 ns 3?5 t plh propagation delay data to output ( act541) 5. 0 1 .5 ? 7.5 1 . 0 8 . 0 ns 3 ?5 t phl propagation delay 50 15 ? 75 10 80 ns 3?5 t phl propagation delay data to output ( act541) 5. 0 1 .5 ? 7.5 1 . 0 8 . 0 ns 3 ?5 t pzh output enable time 50 20 ? 10 0 10 11 0 ns 3?7 t pzh output enable t ime ( act541) 5. 0 2 . 0 ? 10 . 0 1 . 0 11 . 0 ns 3 ?7 t pzl output enable time 50 15 ? 95 10 10 5 ns 3?8 t pzl output enable t ime ( act541) 5. 0 1 .5 ? 9 .5 1 . 0 10 .5 ns 3 ? 8 t phz output disable time 50 20 ? 11 0 10 12 0 ns 3?7 t phz output disable t ime ( act541) 5. 0 2 . 0 ? 11 . 0 1 . 0 12 . 0 ns 3 ?7 t plz output disable time 50 20 ? 90 10 10 ns 3?8 t plz output disable t ime ( act541) 5. 0 2 . 0 ? 9 . 0 1 . 0 10 ns 3 ? 8 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 30 pf v cc = 5.0 v
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 261 ordering information device package shipping mc74ac540n pdip?20 18 units/rail mc74act540n pdip?20 18 units/rail mc74ac540dw soic?20 38 units/rail mc74ac540dwr2 soic?20 1000 tape & reel mc74act540dw soic?20 38 units/rail mc74act540dwr2 soic?20 1000 tape & reel mc74ac540dt tssop?20 75 units/rail mc74ac540dtr2 tssop?20 2500 tape & reel mc74act540dt tssop?20 75 units/rail mc74act540dtr2 tssop?20 2500 tape & reel mc74ac540m eiaj?20 40 units/rail mc74act540m eiaj?20 40 units/rail mc74act540mel eiaj?20 2000 tape & reel mc74ac541n pdip?20 18 units/rail mc74act541n pdip?20 18 units/rail mc74ac541dw soic?20 38 units/rail mc74ac541dwr2 soic?20 1000 tape & reel mc74act541dw soic?20 38 units/rail mc74act541dwr2 soic?20 1000 tape & reel mc74ac541dt tssop?20 75 units/rail mc74ac541dtr2 tssop?20 2500 tape & reel mc74act541dt tssop?20 75 units/rail mc74act541dtr2 tssop?20 2500 tape & reel mc74ac541m eiaj?20 40 units/rail mc74ac541mel eiaj?20 2000 tape & reel mc74act541m eiaj?20 40 units/rail mc74act541mel eiaj?20 2000 tape & reel
mc74ac540, mc74act540, mc74ac541, mc74act541 http://onsemi.com 262 ac 54x alyw ac54x aw l yyww mc74ac54xn aw l yyww 74ac54x awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 54x alyw act54x aw l yyww mc74act54xn aw l yyww 74act54x awl yww x= 0 or 1 a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 263 publication order number: mc74ac573/d the mc74ac573/74act573 is a high?speed octal latch with buffered common latch enable (le) and buffered common output enable (oe ) inputs. the mc74ac573/74act573 is func tionally identical to the mc74ac373/74act373 but has inputs and outputs on opposite sides. ? inputs and outputs on opposite sides of package allowing easy interface with microprocessors ? useful as input or output port for microprocessors ? functionally identical to mc74ac373/74act373 ? 3?state outputs for bus interfacing ? outputs source/sink 24 ma ? act573 has ttl compatible inputs figure 1. pinout 20?lead packages conductors (top view) pin assignment pin function d 0 ?d 7 data inputs le latch enable input oe 3?state output enable input o 0 ?o 7 3?state latch outputs figure 2. logic symbol http://onsemi.com pdip?20 n suffix case 738 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac573n pdip?20 18 units/rail mc74act573n pdip?20 18 units/rail mc74ac573dw soic?20 38 units/rail mc74ac573dwr2 soic?20 1000 tape & reel mc74act573dw soic?20 38 units/rail mc74act573dwr2 soic?20 1000 tape & reel mc74ac573dt tssop?20 75 units/rail mc74ac573dtr2 tssop?20 2500 tape & reel mc74act573dt tssop?20 75 units/rail mc74act573dtr2 tssop?20 2500 tape & reel mc74ac573m eiaj?20 40 units/rail mc74ac573mel eiaj?20 2000 tape & reel mc74act573m eiaj?20 40 units/rail mc74act573mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 270 of this data sheet. device marking information
mc74ac573, mc74act573 http://onsemi.com 264 truth table inputs outputs oe le d n o n l h h h l h l h l l x o 0 h x x z h = high voltage level l = low voltage level z = high impedance x = immaterial o 0 = prev ious o 0 before low?to?high transition of clock functional description the mc74ac573/74act574 contains eight d?type la tc he s with 3?state output buffers. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d input changes. when le is low the latches store the information that was present on the d inputs a setup time preceding the high?to?low transition of le. the 3?state buffers are controlled by the output enable (oe ) input. when oe is low , the buf fers are enabled. when oe is high the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. figure 3. logic diagram note: that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions.
mc74ac573, mc74act573 http://onsemi.com 265 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac573, mc74act573 http://onsemi.com 266 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i oz maximum v i (oe) = v il , v ih 3?state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac573, mc74act573 http://onsemi.com 267 ac characteristics (for figures and waveforms ? see section 3) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 2.5 ? 13.0 2.0 15.0 ns 3?5 t plh d n to o n 5.0 2.5 ? 10.0 2.0 1 1.5 ns 3 ?5 t phl propagation delay 3.3 2.5 ? 12.0 2.0 14.0 ns 3?5 t phl d n to o n 5.0 2.5 ? 9.5 2.0 1 1.0 ns 3 ?5 t plh propagation delay 3.3 2.5 ? 13.0 2.0 15.0 ns 3?6 t plh le to o n 5.0 2.5 ? 9.5 2.0 1 1.0 ns 3 ? 6 t phl propagation delay 3.3 2.5 ? 12.0 2.0 14.0 ns 3?6 t phl le to o n 5.0 2.5 ? 8.5 2.0 10.0 ns 3 ? 6 t pzh output enable time 3.3 2.5 ? 1 1.0 2.0 12.0 ns 3?7 t pzh o utput e na bl e ti me 5.0 2.5 ? 9.0 2.0 10.0 ns 3 ?7 t pzl output enable time 3.3 2.5 ? 1 1.0 2.0 12.5 ns 3?8 t pzl o utput e na bl e ti me 5.0 2.5 ? 8.5 2.0 9.5 ns 3 ? 8 t phz output disable time 3.3 2.5 ? 12.5 2.0 13.5 ns 3?7 t phz o utput di sa bl e ti me 5.0 2.5 ? 1 1.0 2.0 12.0 ns 3 ?7 t plz output disable time 3.3 2.5 ? 9.5 2.0 10.5 ns 3?8 t plz o utput di sa bl e ti me 5.0 2.5 ? 8.0 2.0 9.0 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 ? 3.5 4.0 ns 3?9 t s d n to le 5.0 ? 3.0 3.5 ns 3 ? 9 t h hold time, high or low 3.3 ? 2.0 2.0 ns 3?9 t h d n to le 5.0 ? 2.0 2.0 ns 3 ? 9 t le pulse width high 3.3 ? 6.0 7.0 ns 3?6 t w le p u l se wid t h , high 5.0 ? 4.0 5.0 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac573, mc74act573 http://onsemi.com 268 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 25 ? 10 5 20 12 ns 3?5 t plh propagation delay d n to o n 5. 0 2 .5 ? 10 .5 2 . 0 12 ns 3 ?5 t phl propagation delay 50 25 ? 10 5 20 12 ns 3?5 t phl propagation delay d n to o n 5. 0 2 .5 ? 10 .5 2 . 0 12 ns 3 ?5 t plh propagation delay 50 30 ? 10 5 25 12 ns 3?6 t plh propagation delay le to o n 5. 0 3 . 0 ? 10 .5 2 .5 12 ns 3 ? 6 t phl propagation delay 50 25 ? 95 20 10 5 ns 3?6 t phl propagation delay le to o n 5. 0 2 .5 ? 9 .5 2 . 0 10 .5 ns 3 ? 6 t pzh output enable time 5.0 2.0 ? 10 1.5 11 ns 3?7 t pzl output enable time 5.0 1.5 ? 9.5 1.5 10.5 ns 3?8 t phz output disable time 5.0 2.5 ? 11 1.5 12.5 ns 3?7 t plz output disable time 5.0 1.5 ? 8.5 1.0 9.5 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac573, mc74act573 http://onsemi.com 269 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 ? 30 35 ns 3?9 t s setup t ime, high or low d n to le 5. 0 ? 3 . 0 3 .5 ns 3 ? 9 t h hold time, high or low 50 ? 0 0 ns 3?9 t h hold t ime, high or low d n to le 5. 0 ? 0 0 ns 3 ? 9 t le pulse width high 50 ? 35 40 ns 3?6 t w le p u l se wid t h , high 5.0 ? 3.5 4.0 ns 3?6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 5.0 pf v cc = 5.0 v c pd power dissipation capacitance 25 pf v cc = 5.0 v
mc74ac573, mc74act573 http://onsemi.com 270 ac 573 alyw ac573 aw l yyww mc74ac573n aw l yyww 74ac573 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 573 alyw act573 aw l yyww mc74act573n aw l yyww 74act573 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 6 271 publication order number: mc74ac574/d the mc74ac574/74act574 is a high?speed, low power octal flip?flop with a buffered common clock (cp) and a buffered common output enable (oe ). the information presented to the d inputs is stored in the flip?flops on the low?to?high clock (cp) transition. the mc74ac574/74act574 is func tionally identical to the mc74ac374/74act374 except for the pinouts. ? inputs and outputs on opposite sides of package allowing easy interface with microprocessors ? useful as input or output port for microprocessors ? functionally identical to mc74ac374/74act374 ? 3-state outputs for bus-oriented applications ? outputs source/sink 24 ma ? act574 has ttl compatible inputs figure 1. pinout: 20?lead packages conductors (top view) pin assignment pin function d 0 ?d 7 data inputs cp clock pulse input oe 3?state output enable input o 0 ?o 7 3?state outputs http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74ac574n pdip?20 18 units/rail mc74act574n pdip?20 18 units/rail mc74ac574dw soic?20 38 units/rail mc74ac574dwr2 soic?20 1000 tape & reel mc74act574dw soic?20 38 units/rail mc74act574dwr2 soic?20 1000 tape & reel mc74ac574dt tssop?20 75 units/rail mc74ac574dtr2 tssop?20 2500 tape & reel mc74act574dt tssop?20 75 units/rail mc74act574dtr2 tssop?20 2500 tape & reel mc74ac574m eiaj?20 40 units/rail mc74ac574mel eiaj?20 2000 tape & reel mc74act574m eiaj?20 40 units/rail mc74act574mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 278 of this data sheet. device marking information
mc74ac574, mc74act574 http://onsemi.com 272 figure 2. logic symbol functional description the mc74ac574/74act574 consists of eight edge- triggered flip?flops with individual d?type inputs and 3?state true outputs. the buffered clock and buf fered output enable are common to all flip?flops. the eight flip?flops will store the state of their individual d inputs that meet the setup and hold time requirements on the low?to?high clock (cp) transition. with the output enable (oe ) low, the contents of the eight flip?flops are available at the outputs. when oe is high, the outputs go to the high impedance state. operation of the oe input does not affect the state of the flip?flops. function table inputs internal outputs function oe cp d q o n function h h l nc z hold h hh nc z hold h ll z load h hh z load l ll l data available l hh h data available l hl nc nc no change in data l h h nc nc no change in data h = high voltage level l = low voltage level x = immaterial z = high impedance = low-to-high clock transition nc = no change figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions.
mc74ac574, mc74act574 http://onsemi.com 273 recommended operating conditions symbol parameter min typ max unit v cc supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac574, mc74act574 http://onsemi.com 274 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level ivl 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level ivl 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level ovl 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level ovl 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 01 10 a v i v cc gnd in p leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i old ?minimum dynamic 5.5 ? ? 75 ma v old = 1.65 v max i ohd ?y output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 a v in v cc or gnd cc q supply current 5.5 ? 8.0 80 a v in = v cc or gnd * all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac574, mc74act574 http://onsemi.com 275 ac characteristics (for figures and waveforms ? see section 3) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 75 ? ? 60 ? mhz 3?3 f max frequency 5.0 95 ? ? 85 ? mh z 3 ? 3 t plh propagation delay 3.3 3.5 ? 13.5 3.5 15 ns 3?6 t plh cp to o n 5.0 2.0 ? 9.5 2.0 11 ns 3 ? 6 t phl propagation delay 3.3 3.5 ? 12 3.5 13.5 ns 3?6 t phl cp to o n 5.0 2.0 ? 8.5 2.0 9.5 ns 3 ? 6 t pzh output enable time 3.3 2.5 ? 11 2.5 12 ns 3?7 t pzh o utput e na bl e ti me 5.0 2.0 ? 8.5 2.0 9.0 ns 3 ?7 t pzl output enable time 3.3 3.0 ? 10.5 3.5 1 1.5 ns 3?8 t pzl o utput e na bl e ti me 5.0 1.5 ? 8.0 2.0 9.0 ns 3 ? 8 t phz output disable time 3.3 4.0 ? 12 4.5 13 ns 3?7 t phz o utput di sa bl e ti me 5.0 2.0 ? 9.5 2.0 10.5 ns 3 ?7 t plz output disable time 3.3 2.0 ? 9.0 2.5 10 ns 3?8 t plz o utput di sa bl e ti me 5.0 1.5 ? 7.5 1.5 8.5 ns 3 ? 8 *v oltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 ? 2.5 3.0 ns 3?9 t s d n to cp 5.0 ? 1.5 2.0 ns 3 ? 9 t h hold time, high or low 3.3 ? 1.5 1.5 ns 3?9 t h d n to cp 5.0 ? 1.5 1.5 ns 3 ? 9 t cp pulse width 3.3 ? 6.0 7.0 ns 3?6 t w high or low 5.0 ? 4.0 5.0 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac574, mc74act574 http://onsemi.com 276 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1 v i oz maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.5 5.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms ? see section 3) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 50 100 ? ? 85 ? ns 3?3 f max maximum clock frequency 5. 0 100 ? ? 8 5 ? ns 3 ? 3 t plh propagation delay 50 25 ? 11 20 12 ns 3?6 t plh propagation delay cp to o n 5. 0 2 .5 ? 11 2 . 0 12 ns 3 ? 6 t phl propagation delay 50 20 ? 10 15 11 ns 3?6 t phl propagation delay cp to o n 5. 0 2 . 0 ? 10 1 .5 11 ns 3 ? 6 t pzh output enable time 5.0 2.0 ? 9.5 1.5 10 ns 3?7 t pzl output enable time 5.0 2.0 ? 9.0 1.5 10 ns 3?8 t phz output disable time 5.0 2.0 ? 10.5 1.5 1 1.5 ns 3?7 t plz output disable time 5.0 2.0 ? 8.5 1.5 9.0 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac574, mc74act574 http://onsemi.com 277 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 ? 25 25 ns 3?9 t s setup t ime, high or low d n to cp 5. 0 ? 2 .5 2 .5 ns 3 ? 9 t h hold time, high or low 50 ? 10 10 ns 3?9 t h hold t ime, high or low d n to cp 5. 0 ? 1 . 0 1 . 0 ns 3 ? 9 t cp pulse width 50 ? 30 40 ns 3?6 t w cp pulse width high or low 5. 0 ? 3 . 0 4 . 0 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 40 pf v cc = 5.0 v
mc74ac574, mc74act574 http://onsemi.com 278 ac 574 alyw ac574 aw l yyww mc74ac574n aw l yyww 74ac574 awl yww marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 574 alyw act574 aw l yyww mc74act574n aw l yyww 74act574 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 279 publication order number: mc74ac646/d the mc74ac646/74act646 consist of registered bus transceiver circuits, with outputs, d?type flip?flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. data on the a or b bus will be loaded into the respective registers on the low?to?high transition of the appropriate clock pin (cab or cba). the four fundamental data handling functions available are illustrated figures 1 to 4. ? independent registers for a and b buses ? multiplexed real?time and stored data transfers ? choice of true and inverting data paths ? 3?state outputs ? 300 mil slim dual in?line package ? outputs source/sink 24 ma ? act646 has ttl compatible inputs figure 1. figure 2. figure 3. figure 4. http://onsemi.com marking diagrams device package shipping ordering information mc74ac646n pdip?24 15 units/rail mc74ac646dw soic?24 30 units/rail mc74act646n pdip?24 15 units/rail mc 74a c646dwr 2 soic?24 1000 tape & reel mc74act646dw soic?24 30 units/rail mc 74a c t646dwr2 soic?24 1000 tape & reel a= assembly location l, wl = wafer lot y, yy = year w, ww = work week pdip?24 n suffix case 724 so?24 dw suffix case 751e act646 aw l yyww 1 24 mc74act646n aw l yyww 1 24 pdip?24 so?24 mc74ac646n aw l yyww ac646 aw l yyww
mc74ac646, mc74act646 http://onsemi.com 280 pin assignment pin function a 0 ?a 7 data register inputs data register a outputs b 0 ?b 7 data register b inputs data register b outputs cab, cba clock pulse inputs sab, sba t ransmit/receive inputs dir, g output enable inputs figure 6. logic symbol note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 7. logic diagram figure 5. pinout: 24?lead packages conductors (top view)
mc74ac646, mc74act646 http://onsemi.com 281 function table inputs data i/o* operation or function g dir cab cba sab sba a 0 ?a 7 b 0 ?b 7 operation or function h h x x h or l h or l x x x x input input isolation store a and b data l l l l x x x x x x l h output input real time b data to a bus stored b data to a bus l l h h x h or l x x l h x x input output real time a data to b bus stored a data to b bus *the data output functions may be enabled or disabled by various signals at the g and dir inputs. data input functions are always enabled; i.e., data at the bus pins will be stored on every low?to?high transition of the appropriate clock inputs. note: h = high voltage level; l = low voltage level; x = immaterial; = low?to?high transition maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v s ppl voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac646, mc74act646 http://onsemi.com 282 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i ozt maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.6 6.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac646, mc74act646 http://onsemi.com 283 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 4.0 10.5 16.5 3.0 18.5 ns 3?6 t plh clock to bus 5.0 2.5 7.5 12 2.0 13 ns 3 ? 6 t phl propagation delay 3.3 3.0 9.5 14.5 2.5 16 ns 3?6 t phl clock to bus 5.0 2.0 6.5 10.5 1.5 1 1.5 ns 3 ? 6 t plh propagation delay 3.3 2.5 7.5 12 2.0 13.5 ns 3?5 t plh bus to bus 5.0 1.5 5.0 8.0 1.0 9.0 ns 3 ?5 t phl propagation delay 3.3 1.5 7.5 12.5 1.5 13.5 ns 3?5 t phl bus to bus 5.0 1.5 5.0 9.0 1.0 9.5 ns 3 ?5 propagation delay 33 20 85 13 5 15 15 5 t plh sba or sab to a n or b n (w/a n or b n high or low) 3 . 3 5.0 2 . 0 1.5 8 .5 6.0 13 .5 10 1 .5 1.5 1 5.5 11 ns 3?6 propagation delay 33 15 85 13 5 15 15 t phl sba or sab to a n or b n (w/a n or b n high or low) 3 . 3 5.0 1 .5 1.5 8 .5 6.0 13 .5 10 1 .5 1.5 1 5 11 ns 3?6 t pzh enable time 3.3 2.5 7.0 1 1.5 2.0 12.5 ns 3?7 t pzh g to a n or b n 5.0 1.5 5.0 8.5 1.5 9.0 ns 3 ?7 t pzl enable time 3.3 2.5 7.5 12.5 2.0 14 ns 3?8 t pzl g to a n or b n 5.0 1.5 5.5 9.0 1.5 10 ns 3 ? 8 t phz disable time 3.3 3.0 8.0 12.5 2.5 13.5 ns 3?7 t phz g to a n or b n 5.0 2.0 6.5 10 2.0 11 ns 3 ?7 t plz disable time 3.3 2.0 7.5 12 2.0 13.5 ns 3?8 t plz g to a n or b n 5.0 1.5 6.0 9.5 1.5 10.5 ns 3 ? 8 t pzh enable time 3.3 2.0 6.5 11 1.5 12 ns 3?7 t pzh dir to a n or b n 5.0 1.5 5.0 7.5 1.0 8.5 ns 3 ?7 t pzl enable time 3.3 2.5 7.0 1 1.5 2.0 13 ns 3?8 t pzl dir to a n or b n 5.0 1.5 5.0 8.0 1.0 9.0 ns 3 ? 8 t phz disable time 3.3 2.5 7.5 1 1.5 1.5 12.5 ns 3?7 t phz dir to a n or b n 5.0 1.5 5.5 9.5 1.5 10 ns 3 ?7 t plz disable time 3.3 1.5 7.5 12 1.5 13.5 ns 3?8 t plz dir to a n or b n 5.0 1.5 5.5 9.5 1.5 10.5 ns 3 ? 8 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac646, mc74act646 http://onsemi.com 284 ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 2.0 5.0 5.5 ns 3?9 t s bus to clock 5.0 1.5 4.0 4.5 ns 3 ? 9 t h hold time, high or low 3.3 ?1.5 0 0 ns 3?9 t h bus to clock 5.0 ?0.5 0.5 1.0 ns 3 ? 9 t clock pulse width 3.3 2.0 3.5 4.5 ns 3?6 t w high or low 5.0 2.0 3.5 3.5 ns 3 ? 6 *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ?50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 i oh ?24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 i ol 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd ? i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i ozt maximum v i (oe) = v il , v ih 3-state c 5.5 ? 0.6 6.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in =v cc or gnd q supply current 5.5 ? 8 . 0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac646, mc74act646 http://onsemi.com 285 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 35 12 0 14 5 30 16 0 ns 3?6 t plh propagation delay clock to bus 5. 0 3 .5 12 . 0 14 .5 3 . 0 16 . 0 ns 3 ? 6 t phl propagation delay 50 40 12 0 14 5 35 16 0 ns 3?6 t phl propagation delay clock to bus 5. 0 4 . 0 12 . 0 14 .5 3 .5 16 . 0 ns 3 ? 6 t plh propagation delay 50 30 85 11 0 25 12 0 ns 3?5 t plh propagation delay bus to bus 5. 0 3 . 0 8 .5 11 . 0 2 .5 12 . 0 ns 3 ?5 t phl propagation delay 50 25 85 11 0 20 12 0 ns 3?5 t phl propagation delay bus to bus 5. 0 2 .5 8 .5 11 . 0 2 . 0 12 . 0 ns 3 ?5 t plh propagation delay sba or sab to a or b 50 30 95 12 0 25 13 0 ns 3?6 t plh sba or sab to a n or b n (w/a n or b n high or low) 5. 0 3 . 0 9 .5 12 . 0 2 .5 13 . 0 ns 3 ? 6 t phl propagation delay sba or sab to a or b 50 30 95 12 0 25 13 0 ns 3?6 t phl sba or sab to a n or b n (w/a n or b n high or low) 5. 0 3 . 0 9 .5 12 . 0 2 .5 13 . 0 ns 3 ? 6 t pzh enable time 50 20 90 11 0 15 12 0 ns 3?7 t pzh enable t ime g to a n or b n 5. 0 2 . 0 9 . 0 11 . 0 1 .5 12 . 0 ns 3 ?7 t pzl enable time 50 35 90 11 0 30 12 0 ns 3?8 t pzl enable t ime g to a n or b n 5. 0 3 .5 9 . 0 11 . 0 3 . 0 12 . 0 ns 3 ? 8 t phz disable time 50 50 10 5 13 0 45 14 5 ns 3?7 t phz disable t ime g to a n or b n 5. 0 5. 0 10 .5 13 . 0 4 .5 14 .5 ns 3 ?7 t plz disable time 50 35 10 0 12 5 30 14 0 ns 3?8 t plz disable t ime g to a n or b n 5. 0 3 .5 10 . 0 12 .5 3 . 0 14 . 0 ns 3 ? 8 t pzh enable time 50 20 65 12 5 15 13 5 ns 3?7 t pzh enable t ime dir to a n or b n 5. 0 2 . 0 6 .5 12 .5 1 .5 13 .5 ns 3 ?7 t pzl enable time 50 35 65 12 5 30 13 5 ns 3?8 t pzl enable t ime dir to a n or b n 5. 0 3 .5 6 .5 12 .5 3 . 0 13 .5 ns 3 ? 8 t phz disable time 50 50 85 12 5 45 13 5 ns 3?7 t phz disable t ime dir to a n or b n 5. 0 5. 0 8 .5 12 .5 4 .5 13 .5 ns 3 ?7 t plz disable time 50 35 85 12 5 30 13 5 ns 3?8 t plz disable t ime dir to a n or b n 5. 0 3 .5 8 .5 12 .5 3 . 0 13 .5 ns 3 ? 8 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac646, mc74act646 http://onsemi.com 286 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 ? 70 80 ns 3?9 t s setup t ime, high or low bus to clock 5. 0 ? 7. 0 8 . 0 ns 3 ? 9 t h hold time, high or low 50 ? 25 25 ns 3?9 t h hold t ime, high or low bus to clock 5. 0 ? 2 .5 2 .5 ns 3 ? 9 t clock pulse width 50 ? 70 80 ns 3?6 t w clock pulse width high or low 5. 0 ? 7. 0 8 . 0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c i/o input/output capacitance 15 pf v cc = 5.0 v c pd power dissipation capacitance 60 pf v cc = 5.0 v
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 287 publication order number: mc74ac652/d the mc74ac/act652 consists of registered bus transceiver circuits, with outputs, d?type flip?flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. data on the a or b bus will be loaded into the respective registers on the low?to?high transition of the appropriate clock pin (cab or cba). the four fundamental data handling functions available are illustrated in figures 1 to 4. ? independent registers for a and b buses ? multiplexed real?time and stored data transfers ? choice of true and inverting data paths ? 3?state outputs ? 300 mil slim dual?in?line package ? outputs source/sink 24 ma ? act652 has ttl compatible inputs http://onsemi.com marking diagrams device package shipping ordering information mc74ac652n pdip?24 15 units/rail mc74ac652dw soic?24 30 units/rail mc74act652n pdip?24 15 units/rail mc 74a c652dwr 2 soic?24 1000 tape & reel mc74act652dw soic?24 30 units/rail mc 74a c t652dwr2 soic?24 1000 tape & reel a= assembly location l, wl = wafer lot y, yy = year w, ww = work week pdip?24 n suffix case 724 so?24 dw suffix case 751e act652 aw l yyww 1 24 mc74act652n aw l yyww 1 24 pdip?24 so?24 mc74ac652n aw l yyww ac652 aw l yyww figure 1. figure 2. figure 3. figure 4.
mc74ac652, mc74act652 http://onsemi.com 288 pin assignment pin function a 0 ?a 7 data register a inputs data register a outputs b 0 ?b 7 data register b inputs data register b outputs cab, cba clock pulse inputs sab, sba t ransmit/receive inputs gab, gba output enable inputs figure 6. logic symbol figure 7. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 5. pinout: 24?lead plastic package (top view)
mc74ac652, mc74act652 http://onsemi.com 289 function table inputs data i/o* operation or function gab gba cab cba sab sba a 0 ? a 7 b 0 ? b 7 operation or function l h h or l h or l x x input input isolation l h ? ? x x i npu t i npu t store a and b data x h ? h or l x x input unspecified* store a, hold b h h ? ? x** x input output store a in both registers l x h or l ? x x unspecified* input hold a, store b l l ? ? x x** output input store b in both registers l l x x x l output input real-time b data to a bus l l x h or l x h o u t pu t i npu t stored b data to a bus h h x x l x input output real-time a data to b bus h h h or l x h x i npu t o u t pu t stored a data to b bus h l horl horl h h output output stored a data to b bus and h l h or l h or l h h o u t pu t o u t pu t stored a data to b bus and stored b data to a bus *the data output functions may be enabled or disabled by various signals at the gba and gab inputs. data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the appropriate clock inputs. **select control = l: clocks can occur simultaneously. h = high voltage level; l = low voltage level; x = immaterial; ? = low-to-high transition maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ min unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v v cc @ 3.0 v ? 150 ? t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v ? 40 ? ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v ? 25 ? tt f in p ut rise and fall time ( note 2 ) v cc @ 4.5 v ? 10 ? ns/v t r , t f input rise and fall t ime (note 2) act devices except schmitt inputs v cc @ 5.5 v ? 8.0 ? ns/v t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac652, mc74act652 http://onsemi.com 290 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ? 50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ? 12 ma 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 ? 24 ma v ol minimum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i ozt maximum v i (oe) = v il , v ih 3-state 5.5 ? 0.6 6.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic oc 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in = v cc or gnd q supply current 5.5 ? 8 . 0 80 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one input loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v.
mc74ac652, mc74act652 http://onsemi.com 291 ac characteristics 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min max min max t plh propagation delay 3.0 4.0 17.0 3.0 19.0 ns t plh pg y cpba or cpab to a n or b n 5.0 2.5 12.0 2.0 14.0 ns t phl propagation delay 3.0 3.0 14.5 2.5 16.5 ns t phl pg y cpba or cpab to a n or b n 5.0 2.0 10.5 1.5 12.0 ns t plh propagation delay 3.0 3.0 14.0 2.5 16.0 ns t plh pg y a or b to b n or a n 5.0 2.0 9.5 1.5 1 1.0 ns t phl propagation delay 3.0 2.5 13.0 2.0 15.0 ns t phl pg y a or b to b n or a n 5.0 1.5 9.0 1.0 10.5 ns t plh propagation delay 3.0 3.0 14.0 2.5 16.0 ns t plh pg y sba or sab to a n or b n 5.0 2.5 10.0 2.0 1 1.5 ns t phl propagation delay 3.0 2.5 13.5 2.0 15.5 ns t phl pg y sba or sab to a n or b n 5.0 2.0 10.0 1.5 1 1.5 ns t pzh output enable time 3.0 2.5 12.0 2.0 13.5 ns t pzh p oeba to a n 5.0 1.5 9.0 1.0 10.0 ns t pzl output enable time 3.0 2.5 12.0 2.0 14.0 ns t pzl p oeba to a n 5.0 1.5 9.0 1.0 10.5 ns t phz output disable time 3.0 3.0 13.0 2.5 14.0 ns t phz p oeba to a n 5.0 2.0 1 1.0 1.5 12.0 ns t plz output disable time 3.0 2.5 12.5 2.0 14.0 ns t plz p oeba to a n 5.0 2.0 10.5 1.5 12.0 ns *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
mc74ac652, mc74act652 http://onsemi.com 292 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input voltage 5.5 1.5 2.0 2.0 v or v cc ? 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input voltage 5.5 1.5 0.8 0.8 v or v cc ? 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = ? 50 a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 i oh ? 24 ma v ol minimum low level 4.5 0.001 0.1 0.1 v i out = ? 50 a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 ? 0.36 0.44 v i oh ? 24 ma 5.5 ? 0.36 0.44 i oh ? 24 ma i in maximum input 55 ? 01 10 a v i = v cc , gnd p leakage current 5.5 ? 0 . 1 1 . 0 a icc , i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i ozt maximum v i (oe) = v il , v ih 3-state 5.5 ? 0.6 6.0 a v i = v cc , gnd current v o = v cc , gnd i old ?minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent 55 ? 80 80 a v in = v cc or gnd q supply current 5.5 ? 8 . 0 80 a in cc *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one input loaded at a time.
mc74ac652, mc74act652 http://onsemi.com 293 ac characteristics 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit min max min max t plh propagation delay 50 40 14 5 35 16 5 ns t plh propagation delay cpba or cpab to a n or b n 5. 0 4 . 0 14 .5 3 .5 16 .5 ns t phl propagation delay 50 35 14 5 30 16 5 ns t phl propagation delay cpba or cpab to a n or b n 5. 0 3 .5 14 .5 3 . 0 16 .5 ns t plh propagation delay 50 25 11 5 20 13 0 ns t plh propagation delay a or b to b n or a n 5. 0 2 .5 11 .5 2 . 0 13 . 0 ns t phl propagation delay 50 25 11 5 20 13 0 ns t phl propagation delay a or b to b n or a n 5. 0 2 .5 11 .5 2 . 0 13 . 0 ns t plh propagation delay 50 25 12 0 20 13 5 ns t plh propagation delay sba or sab to a n or b n 5. 0 2 .5 12 . 0 2 . 0 13 .5 ns t phl propagation delay 50 30 12 0 25 13 5 ns t phl propagation delay sba or sab to a n or b n 5. 0 3 . 0 12 . 0 2 .5 13 .5 ns t pzh output enable time 50 20 11 5 15 13 0 ns t pzh output enable t ime oeba to a n 5. 0 2 . 0 11 .5 1 .5 13 . 0 ns t pzl output enable time 50 25 11 5 20 13 0 ns t pzl output enable t ime oeba to a n 5. 0 2 .5 11 .5 2 . 0 13 . 0 ns t phz output disable time 50 30 13 0 25 14 0 ns t phz output disable t ime oeba to a n 5. 0 3 . 0 13 . 0 2 .5 14 . 0 ns t plz output disable time 50 25 12 5 20 14 0 ns t plz output disable t ime oeba to a n 5. 0 2 .5 12 .5 2 . 0 14 . 0 ns t pzh output enable time 50 25 12 0 20 13 5 ns t pzh output enable time oeab to b n 5. 0 2 .5 12 . 0 2 . 0 13 .5 ns t pzl output enable time 50 25 12 0 20 13 5 ns t pzl output enable t ime oeab to b n 5. 0 2 .5 12 . 0 2 . 0 13 .5 ns t phz output enable time 50 35 13 5 30 14 5 ns t phz output enable t ime oeab to b n 5. 0 3 .5 13 .5 3 . 0 14 .5 ns t plz output enable time 50 30 13 5 25 15 0 ns t plz output enable t ime oeab to b n 5. 0 3 . 0 13 .5 2 .5 1 5. 0 ns t s setup time, high or low 50 70 ? 80 ? ns t s setup t ime, high or low a n or b n to cpba or cpab 5. 0 7. 0 ? 8 . 0 ? ns t h hold time, high or low 50 25 ? 25 ? ns t h hold t ime, high or low a n or b n to cpba or cpab 5. 0 2 .5 ? 2 .5 ? ns t cpab, cpba pulse width 50 60 ? 70 ? ns t w cpab, cpba pulse width high or low 5. 0 6 . 0 ? 7. 0 ? ns *voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter 74act typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c i/o input/output capacitance 15 pf v cc = 5.0 v c pd power dissipation capacitance 60.0 pf v cc = 5.0 v
? semiconductor components industries, llc, 2001 may, 2001 ? rev. 5 294 publication order number: mc74ac4040/d the mc74ac4040 consists of 12 master-slave flip-flops. the output of each flip-flop feeds the next and the frequency at each output is half that of the preceding one. the state of the counter advances on the negative-going edge of the clock input. reset is asynchronous and active-high. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and may have to be gated with the clock of the mc74ac4040 for some designs. ? 140 mhz typ. clock ? outputs source/sink 24 ma ? operating voltage range: 2.0 to 6.0 v ? high noise immunity figure 1. pinout: 16?lead packages conductors (top view) function table clock reset output state l no change l advance to next state x h all outputs are low http://onsemi.com dip?16 n suffix case 648 1 16 so?16 d suffix case 751b 1 16 tssop?16 dt suffix case 948f 1 16 see general marking information in the device marking section on page 297 of this data sheet. device marking information 1 16 eiaj?16 m suffix case 966 device package shipping ordering information mc74ac4040n pdip?16 25 units/rail mc74ac4040d soic?16 48 units/rail mc74ac4040dr2 2500 tape & reel mc74ac4040dt tssop?16 96 units/rail mc74ac4040dtr2 tssop?16 soic?16 2500 tape & reel mc74ac4040m eiaj?16 50 units/rail
mc74ac4040 http://onsemi.com 295 figure 2. logic diagram pin 16 = v cc pin 8 = gnd maximum ratings* symbol parameter v alue unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma p d power dissipation in still air plastic soic package 750 500 mw t stg storage temperature ?65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c *maximum ratings are those values beyond which damage to the device may occur. ? derating: plastic dip: ? 10mw/ c from 65 c to 125 c soic package: ?7.0 mw/ c from 65 c to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in /v out input voltage, output voltage (ref. to gnd) 0 v cc ? t a operating temperature, all package types ?40 +85 c t r /t f in p ut rise/fall time v cc = 3.0 v 0 150 ns/v t r /t f input rise/fall t ime (figure 1) v cc = 3 . 0 v v cc = 4.5 v 0 0 150 40 ns/v (figure 1) v cc 4.5 v v cc = 5.5 v 0 0 40 25
mc74ac4040 http://onsemi.com 296 dc characteristics (unless otherwise specified) symbol parameter v alue unit v in = v cc or gnd i cc maximum quiescent supply voltage 80 a v cc = 5.5 v, cc qppyg a v cc = 5.5 v, cc qppy c dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = ?40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 ? 2.1 2.1 v out = 0.1 v g input voltage 4.5 ? 3.15 3.15 v or v cc ? 0.1 v 5.5 ? 3.85 3.85 v il maximum low level 3.0 ? 0.9 0.9 v out = 0.1 v input voltage 4.5 ? 1.35 1.35 v or v cc ? 0.1 v 5.5 ? 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = ?50 a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 ? 2.56 2.46 v ?12 ma 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 ? 0.36 0.44 v 12 ma 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input 55 ? 01 10 a v i =v cc gnd p leakage current 5.5 ? 0 . 1 1 . 0 a v i = v cc , gnd i old minimum dynamic ot tc t 5.5 ? ? 75 ma v old = 1.65 v max i ohd output current 5.5 ? ? ?75 ma v ohd = 3.85 v min *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74ac4040 http://onsemi.com 297 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum clock 3.3 110 120 ? 100 ? mhz ? f max frequency 5.0 130 140 ? 120 ? mh z ? n cp to q1 propagation delay 3.3 2.0 ? 11 2.0 14 ns ? n cp to q1 n cp to q1 5.0 2.0 ? 8.0 2.0 10 ns ? q n to q n +1 propagation delay 3.3 0 ? 5.5 0 6.5 ns ? q n to q n + 1 q n to q n +1 5.0 0 ? 3.5 0 4.5 ns ? mr to q propagation delay 3.3 3.0 ? 12 3.0 15 ns ? q t hl mr to q 5.0 3.0 ? 10 3.0 12 ns ? t rec recovery time 3.3 0 ?2.5 ? 0 ? ns ? rec n cp to mr r ecovery ti me 5.0 0 ?1.5 ? 0 ? ns ? tn cp minimum pulse width 3.3 4.0 3.5 ? 4.5 ? ns ? t w n cp clock pin 5.0 3.0 2.5 ? 3.5 ? ns ? tmr minimum pulse width 3.3 4.0 3.5 ? 4.5 ? ns ? t w mr master reset 3.0 3.0 2.5 ? 3.5 ? ns ? *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v marking diagrams a= assembly location wl, l = wafer lot yy, y = year ww, w = work week ac4040 awl yww mc74ac4040n aw l yyww ac 4040 alyw dip?16 so?16 tssop?16 eiaj?16 74ac4040 alyw
? semiconductor components industries, llc, 2001 june, 2001 ? rev. 2 298 publication order number: mc74act241/d the mc74act241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved pc board density. ? 3?state outputs drive bus lines or buffer memory address registers ? outputs source/sink 24 ma ? ttl compatible inputs figure 1. pinout: 20?lead packages conductors (top view) truth table inputs outputs oe 1 d (pins 12, 14, 16, 18) l l l l h h h x z h = high voltage level l = low voltage level x = immaterial z = high impedance truth table inputs outputs oe 2 d (pins 3, 5, 7, 9) h l l h h h l x z h = high voltage level l = low voltage level x = immaterial z = high impedance http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74act241n pdip?20 18 units/rail mc74act241dw soic?20 38 units/rail mc74act241dwr2 soic?20 1000 tape & reel mc74act241dt tssop?20 75 units/rail mc74act241dtr2 tssop?20 2500 tape & reel mc74act241m eiaj?20 40 units/rail mc74act241mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 302 of this data sheet. device marking information
mc74act241 http://onsemi.com 299 maximum ratings (note 1) symbol parameter v alue unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 v i v cc 0.5 v v o dc output voltage (note 2) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 100 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 67 96 128 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul?94?vo (0.125 in) v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 > 1000 v i latch?up latch?up performance above v cc and below gnd at 85 c (note 6) 100 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not implied. 2. i o absolute maximum rating must be observed. 3. tested to eia/jesd22?a114?a. 4. tested to eia/jesd22?a115?a. 5. tested to jesd22?c101?a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc dc input voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?40 25 +85 c t r , t f in p ut rise and fall time ( note 8 ) v cc = 4.5 v 0 10 10 ns/v t r , t f input rise and fall t ime (note 8) v cc = 4 . 5 v v cc = 5.5 v 0 0 10 8.0 10 8.0 ns/v t j junction temperature (pdip) 140 c i oh output current ? high ?24 ma i ol output current ? low 24 ma 7. unused inputs may not be left open. all inputs must be tied to a high voltage level or low logic voltage level. 8. v in from 0.8 v to 2.0 v; refer to individual data sheets for devices that differ from the typical input rise and fall times.
mc74act241 http://onsemi.com 300 dc characteristics t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level i nput voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 v v v out = 0.1 v or v cc ? 0.1 v v il maximum low level i nput voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 v v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 v v i out = ?50 a 4.5 5.5 3.86 4.86 3.76 4.76 v v *v in = v il or v ih ?24 ma i oh ?24 ma v ol maximum low level output voltage 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 v v i out = 50 a 4.5 5.5 0.36 0.36 0.44 0.44 v v *v in = v il or v ih 24 ma i ol 24 ma i in maximum input leakage current 5.5 0.1 1.0 a v i = v cc , gnd i cct additional maximum i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1 v i oz maximum 3?state current 5.5 0.5 5.0 a v i (oe) = v il , v ih v i = v cc , gnd v o = v cc , gnd i old i ohd ?minimum dynamic output current 5.5 5.5 75 ?75 ma ma v old = 1.65 v max v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics t r = t f = 3.0 ns ( for figures and waveforms, see figures 2, 3, and 4.) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf symbol parameter v cc * (v) min typ max min max unit t plh propagation delay data to output 5.0 1.5 6.5 9.0 1.5 10.0 ns t phl propagation delay data to output 5.0 1.5 7.0 9.0 1.5 10.0 ns t pzh output enable time 5.0 1.5 6.0 9.0 1.0 10.0 ns t pzl output enable time 5.0 1.5 7.0 10.0 1.5 1 1.0 ns t phz output disable time 5.0 1.5 8.0 10.5 1.5 1 1.5 ns t plz output disable time 5.0 2.0 7.0 10.5 1.5 1 1.5 ns *voltage range 5.0 v is 5.0 v 0.5 v capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v
mc74act241 http://onsemi.com 301 switching waveforms figure 2. input data output t r t f 3.0 v gnd 50% 50% t plh t phl figure 3. *includes all probe and jig capacitance c l * 50 scope test point device under test output t w 1/f max figure 4. test circuit 450 input 1.3 v gnd v ol v oh output y t pzl t plz t pzh t phz high impedance oe 1 10% 90% gnd 3.0 v 3.0 v high impedance 1.3 v 1.3 v 1.3 v oe 2 output y (12, 14, 16, 18) (3, 5, 7, 9)
mc74act241 http://onsemi.com 302 marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 241 alyw act241 aw l yyww mc74act241n aw l yyww 74act241 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
? semiconductor components industries, llc, 2001 june, 2001 ? rev. 1 303 publication order number: mc74act323/d the mc74act323 is an 8-bit universal shift/storage register with3-state outputs. its function is similar to the mc74act299 with the exception of synchronous reset. parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. separate serial inputs and outputs are provided for q 0 and q 7 to allow easy cascading. four operation modes are possible: hold (store), shift left, shift right and parallel load. ? common parallel i/o for reduced pin count ? additional serial inputs and outputs for expansion ? four operating modes: shift left, shift right, load and store ? 3-state outputs for bus-oriented applications ? outputs source/sink 24 ma ? ttl compatible inputs http://onsemi.com marking diagrams tssop?20 dt suffix case 948e 20 1 so?20 dw suffix case 751d 1 20 act 323 alyw act323 aw l yyww pdip?20 n suffix case 738 1 20 device package shipping ordering information mc74act323dt tssop?20 75 units/rail mc74act323dtr2 tssop?20 2500 tape & reel mc74act323n aw l yyww mc74act323n pdip?20 18 units/rail mc74act323dw soic?20 38 units/rail mc74act323dwr2 soic?20 1000 tape & reel a= assembly location l, wl = wafer lot y, yy = year w, ww = work week 20 1 20 1 20 1
mc74act323 http://onsemi.com 304 19 20 18 17 16 15 14 2 1345 67 v cc 13 8 12 9 11 10 s 1 ds 7 q 7 i/o 7 i/o 5 i/o 3 i/o 1 cp ds 0 s 0 oe 1 oe 2 i/o 6 i/o 4 i/o 2 i/o 0 q 0 sr gnd figure 1. pinout: 20?lead packages conductors (top view) pin assignment pin function cp clock pulse input ds 0 serial data input for right shift ds 7 serial data input for left shift s 0 , s 1 mode select inputs sr synchronous master reset oe 1, oe 2 3-state output enable inputs i/o 0 ?i/o 7 multipled parallel data inputs or 3-state parallel data outputs q 0 , q 7 serial outputs figure 3. logic symbol ds 0 ds 7 q 7 s 0 s 1 cp oe sr q 0 i/o 0 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 7 1 2 truth table inputs sr s 1 s 0 cp response l x x synchronous reset; q 0 ? q 7 = low h h h parallel load; i/o n q n h l h shift right; ds 0 q 0 , q 0 q 1 , etc. h h l shift left; ds 7 q 7 , q 7 q 6 , etc. h l l x hold h = high voltage level l = low voltage level x = immaterial = low-to-high clock transition dq please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 2. logic diagram cp s 0 oe 1 oe 2 i/o 6 i/o 4 i/o 2 i/o 0 q 0 s 1 ds 7 q 7 i/o 7 i/o 5 i/o 3 ds 0 i/o 1 cp sr dq cp dq cp dq cp dq cp dq cp dq cp dq cp
mc74act323 http://onsemi.com 305 functional description the mc74act323 contains eight edge- triggered d-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. the type of operation is determined by s 0 and s 1 as shown in the mode select table. all flip-flop outputs are brought out through 3 state buffers to separate i/o pins that also serve as data inputs in the parallel load mode. q 0 and q 7 are also brought out on other pins for expansion in serial shifting of longer words. a low signal on sr overrides the select inputs and allows the flip-flops to be reset by the next rising edge of cp. all other state changes are also initiated by the low-to-high cp transition. inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of cp, are observed. a high signal on either oe 1 or oe 2 disables the 3-state buf fers and puts the i/o pins in the high impedance state. in this condition the shift, hold, load and reset operations can still occur. the 3-state buffers are also disabled by high signals on both s 0 and s 1 in preparation for a parallel load operation. maximum ratings (note 1) symbol parameter v alue unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 v i v cc 0.5 v v o dc output voltage (note 2) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 67 96 128 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 >1000 v i latch?up latch?up performance above v cc and below gnd at 85 c (note 6) 100 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not implied. 2. i o absolute maximum rating must be observed. 3. tested to eia/jesd22?a114?a. 4. tested to eia/jesd22?a115?a. 5. tested to jesd22?c101?a. 6. tested to eia/jesd78.
mc74act323 http://onsemi.com 306 recommended operating conditions symbol parameter min typ max unit v cc dc input voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?40 25 +85 c t r , t f in p ut rise and fall time ( note 8 ) v cc = 4.5 v 0 10 10 ns/v t r , t f input rise and fall t ime (note 8) v cc = 4 . 5 v v cc = 5.5 v 0 0 10 8.0 10 8.0 ns/v t j junction temperature (pdip) 140 c i oh output current ? high ?24 ma i ol output current ? low 24 ma 7. unused inputs may not be left open. all inputs must be tied to a high voltage level or low logic voltage level. 8. v in from 0.8 v to 2.0 v; refer to individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level i nput voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 v v v out = 0.1 v or v cc ? 0.1 v v il maximum low level input voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 v v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 v v i out = ?50 a 4.5 5.5 3.86 4.86 3.76 4.76 v v *v in = v il or v ih ?24 ma i oh ?24 ma v ol maximum low level output voltage 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 v v i out = 50 a 4.5 5.5 0.36 0.36 0.44 0.44 v v *v in = v il or v ih ?24 ma i oh ?24 ma i in maximum input leakage current 5.5 0.1 1.0 a v i = v cc , gnd i cct additional maximum i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1 v i oz maximum 3?state current 5.5 0.5 5.0 a v i (oe) = v il , v ih v i = v cc , gnd v o = v cc , gnd i old i ohd ?minimum dynamic output current 5.5 5.5 75 ?75 ma ma v old = 1.65 v max v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time.
mc74act323 http://onsemi.com 307 ac characteristics t r = t f = 3.0 ns (for figures and waveforms, see figures 4 and 5.) t a = +25 c t a = ?40 c to +85 c t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf symbol parameter v cc * (v) min typ max min max unit f max maximum input frequency 5.0 120 125 110 mhz t plh propagation delay cp to q 0 or q 7 5.0 5.0 9.0 12.5 4.0 14 ns t phl propagation delay cp to q 0 or q 7 5.0 5.0 9.0 13.5 4.5 15 ns t plh propagation delay cp to i/o n 5.0 5.0 8.5 12.5 4.5 14.5 ns t pzh output enable time 5.0 3.5 7.5 11 3.0 12.5 ns t pzl output enable time 5.0 3.5 7.5 1 1.5 3.0 13 ns t phz output disable time 5.0 4.0 8.5 12.5 3.0 13.5 ns t plz output disable time 5.0 3.0 8.0 1 1.5 2.5 12.5 ns *voltage range 5.0 v is 5.0 v 0.5 v ac operating requirements t a = +25 c t a = ?40 c to +85 c s y mbol parameter v cc * ( v ) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit symbol parameter v cc (v) typ guaranteed minimum unit t s setup time, high or low s 0 or s 1 to cp 5.0 2.0 5.0 5.0 ns t h hold time, high or low s 0 or s 1 to cp 5.0 0 1.5 1.5 ns t s setup time, high or low i/o n, ds 0, ds 7 to cp 5.0 1.0 4.0 4.5 ns t h hold time, high or low i/o n, ds 0, ds 7 to cp 5.0 0 1.0 1.0 ns t s setup time, high or low sr to cp 5.0 1.0 2.5 2.5 ns t h hold time, high or low sr to cp 5.0 0 1.0 1.0 ns t w cp pulse width high or low 5.0 2.0 4.0 4.5 ns *voltage range 5.0 v is 5.0 v 0.5 v capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 170 pf v cc = 5.0 v
mc74act323 http://onsemi.com 308 switching waveforms figure 4. figure 5. *includes all probe and jig capacitance c l * 50 scope test point device under test output figure 6. figure 7. 450 input t r t f 3.0 v gnd t thl t tlh 90% 50% 10% 90% 50% 10% c p t plh t phl q 0 ? q 7 t w 1/f max v cc gnd s 0 or s 1 50% 50% 50% s 1 or s 0 q 0 ?q 7 t pzl t plz t pzh t phz 10% 90% 3.0 v gnd high impedance v ol v oh high impedance 50% 50% 50% oe 1 or oe 2 q 0 ?q 7 t pzl t plz t pzh t phz 10% 90% 3.0 v gnd high impedance v ol v oh high impedance 50% mode select or data c p 3.0 v 3.0 v gnd gnd v alid t h 50% figure 8. figure 9. test circuit i/o 0 ? i/o 7 3.0 v gnd sr 50% 3.0 v c p q 0 ? q 7 i/o 0 ? i/o 7 50% t phl t h t s t s
? semiconductor components industries, llc, 2001 june, 2001 ? rev. 1 309 publication order number: mc74act564/d the mc74act564 is a high?speed, low power octal flip?flop with a buffered common clock (cp) and a buffered common output enable (oe ). the information presented to the d inputs is stored in the flip?flops on the low?to?high clock (cp) transition. the mc74act564 device is functionally indentical to the mc74act574, but with inverted outputs. ? inputs and outputs on the opposite sides of the package allowing easy interface with microprocessors ? useful as input or output port for microprocessor ? functionally indentical to the mc74act574 but with inverted outputs ? 3?state outputs for bus?oriented applications ? outputs source/sink 24 ma ? ttl compatible inputs marking diagrams tssop?20 dt suffix case 948e 20 1 so?20 dw suffix case 751d 1 20 act 564 alyw act564 aw l yyww pdip?20 n suffix case 738 1 2 0 mc74act564 aw l yyww 20 1 20 1 20 1 http://onsemi.com device package shipping ordering information mc74act564dt tssop?20 75 units/rail mc74act564dtr2 tssop?20 2500 tape & reel mc74act564n pdip?20 18 units/rail mc74act564dw soic?20 38 units/rail mc74act564dwr2 soic?20 1000 tape & reel a= assembly location l, wl = wafer lot y, yy = year w, ww = work week
mc74act564 http://onsemi.com 310 v cc o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 cp oe d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd figure 1. pinout: 20?lead packages conductors (top view) pin assignment pin d 0 ?d 7 function data inputs cp clock pulse input oe 3?state output enable input o 0 ?o 7 3?state outputs figure 2. logic symbol o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 cp oe figure 3. logic diagram d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 cd q o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 oe cp cd q cd q cd q cd q cd q cd q cd q please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. function table inputs internal outputs function oe cp d q o function h h l nc z hold h hh nc z hold h lh z load h hl z load l lh h data available l hl l data available l hl nc nc no change in data l h h nc nc no change in data h= high voltage level l= low voltage level x= immaterial z= high impedance = low?to?high transition nc = no change
mc74act564 http://onsemi.com 311 functional description the mc74act564 consists of eight edge?triggered flip?flops with individual d?type inputs and 3?state complementary outputs. the buffered clock and buffered output enable are common to all flip?flops. the eight flip?flops will store the state of their individual d inputs that meet the setup and hold times requirements on the low?to?high clock (cp) transition. with the output enable (oe ) low, the contents of the eight flip?flops are available at the outputs. when oe is high, the outputs go to the high impedance state. operation of the oe input does not affect the state of the flip?flops. maximum ratings (note 1) symbol parameter v alue unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 v i v cc 0.5 v v o dc output voltage (note 2) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 67 96 128 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul?94?vo (0.125 in) v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 > 1000 v i latch?up latch?up performance above v cc and below gnd at 85 c (note 6) 100 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not implied. 2. i o absolute maximum rating must be observed. 3. tested to eia/jesd22?a114?a. 4. tested to eia/jesd22?a115?a. 5. tested to jesd22?c101?a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc dc input voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?40 25 +85 c t r , t f in p ut rise and fall time ( note 8 ) v cc = 4.5 v 0 10 10 ns/v t r , t f input rise and fall t ime (note 8) v cc = 4 . 5 v v cc = 5.5 v 0 0 10 8.0 10 8.0 ns/v t j junction temperature (pdip) 140 c i oh output current ? high ?24 ma i ol output current ? low 24 ma 7. unused inputs may not be left open. all inputs must be tied to a high voltage level or low logic voltage level. 8. v in from 0.8 v to 2.0 v; refer to individual data sheets for devices that differ from the typical input rise and fall times.
mc74act564 http://onsemi.com 312 dc characteristics t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level i nput voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 v v v out = 0.1 v or v cc ? 0.1 v v il maximum low level input voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 v v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 v v i out = ?50 a 4.5 5.5 3.86 4.86 3.76 4.76 v v *v in = v il or v ih ?24 ma i oh ?24 ma v ol maximum low level output voltage 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 v v i out = 50 a 4.5 5.5 0.36 0.36 0.44 0.44 v v *v in = v il or v ih 24 ma i ol 24 ma i in maximum input leakage current 5.5 0.1 1.0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1 v i oz maximum 3?state current 5.5 0.5 5.0 a v i (oe) = v il , v ih v i = v cc , gnd v o = v cc , gnd i old i ohd ?minimum dynamic output current 5.5 5.5 75 ?75 ma ma v old = 1.65 v max v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics t r = t f = 3.0 ns (for figures and waveforms, see figures 4, 5, and 6.) t a = +25 c c l 50 pf t a = ?40 c to +85 c symbol parameter v cc * (v) c l = 50 pf to +85 c c l = 50 pf unit min typ max min max f max maximum clock frequency 5.0 85 75 mhz t plh propagation delay cp to q n 5.0 2.0 10.5 1.5 1 1.5 ns t phl propagation delay cp to q n 5.0 1.5 9.5 1.5 10.5 ns t pzh output enable time 5.0 1.5 9.0 1.5 9.5 ns t pzl output enable time 5.0 1.5 8.5 1.0 9.5 ns t phz output disable time 5.0 1.5 10.5 1.5 1 1.5 ns t plz output disable time 5.0 1.5 8.0 1.0 8.5 ns *voltage range 5.0 v is 5.0 v 0.5 v
mc74act564 http://onsemi.com 313 ac operating requirements t a = +25 c t a = ?40 c to +85 c s y mbol parameter v cc * ( v ) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit symbol parameter v cc (v) typ guaranteed minimum unit t s setup time, high or low d n to c p 5.0 2.5 3.0 ns t h hold time, high or low d n to c p 5.0 1.0 1.0 ns t w c p pulse width high or low 5.0 3.0 3.5 ns *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v switching waveforms figure 4. c p q t r t f 3.0 v gnd 50% 50% t plh t phl 50% data c p 3.0 v figure 5. v alid gnd *includes all probe and jig capacitance c l * 50 scope test point device under test output figure 6. t w 1/f max v cc gnd t su t h 50% figure 7. test circuit 450 50% oe c p 3.0 v 3.0 v gnd t s t h 50% input
? semiconductor components industries, llc, 2001 june, 2001 ? rev. 1 314 publication order number: mc74act640/d the mc74act640 octal bus transceiver is designed for asynchronous two-way communication between data buses. the device transmits data from bus a to bus b when t/r = high, or from bus b to bus a when t/r = low. the enable input can be used to disable the device so the buses are effectively isolated. ? bidirectional data path ? a and b outputs sink 24 ma/source ?24 ma ? ttl compatible inputs 19 20 18 16 15 14 2 13 4567 v cc 13 8 12 9 11 10 oe b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 t/r a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 gnd 17 figure 1. pinout: 20?lead packages conductors (top view) pin assignment pin function a 0 ?a 7 side a inputs or 3-state outputs oe output enable input t/r t ransmit/receive input b 0 ?b 7 side b inputs or 3-state outputs truth table oe t/r applied inputs v alid direction i/p o/p output h x x x x l h h a to b l l h l a to b h l l h b to a l l l l b to a h h = high voltage level l = low voltage level x = immaterial http://onsemi.com 1 20 pdip?20 n suffix case 738 1 20 1 20 1 20 so?20 dw suffix case 751 tssop?20 dt suffix case 948e eiaj?20 m suffix case 967 device package shipping ordering information mc74act640n pdip?20 18 units/rail mc74act640dw soic?20 38 units/rail mc74ac640dwr2 soic?20 1000 tape & reel mc74ac640dt tssop?20 75 units/rail mc74act640dtr2 tssop?20 2500 tape & reel mc74act640m eiaj?20 40 units/rail mc74ac640mel eiaj?20 2000 tape & reel see general marking information in the device marking section on page 318 of this data sheet. device marking information
mc74act640 http://onsemi.com 315 maximum ratings (note 1) symbol parameter v alue unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 v i v cc 0.5 v v o dc output voltage (note 2) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 67 96 128 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 > 1000 v i latch?up latch?up performance above v cc and below gnd at 85 c (note 6) 100 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not implied. 2. i o absolute maximum rating must be observed. 3. tested to eia/jesd22?a114?a. 4. tested to eia/jesd22?a115?a. 5. tested to jesd22?c101?a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc dc input voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?40 25 +85 c t r , t f in p ut rise and fall time ( note 8 ) v cc = 4.5 v 0 10 10 ns/v t r , t f input rise and fall t ime (note 8) v cc = 4 . 5 v v cc = 5.5 v 0 0 10 8.0 10 8.0 ns/v t j junction temperature (pdip) 140 c i oh output current ? high ?24 ma i ol output current ? low 24 ma 7. unused inputs may not be left open. all inputs must be tied to a high voltage level or low logic voltage level. 8. v in from 0.8 v to 2.0 v; refer to individual data sheets for devices that differ from the typical input rise and fall times.
mc74act640 http://onsemi.com 316 dc characteristics t a = +25 c t a = ?40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level i nput voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 v v v out = 0.1 v or v cc ? 0.1 v v il maximum low level input voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 v v v out = 0.1 v or v cc ? 0.1 v v oh minimum high level output voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 v v i out = ?50 a 4.5 5.5 3.86 4.86 3.76 4.76 v v *v in = v il or v ih ?24 ma i oh ?24 ma v ol maximum low level output voltage 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 v v i out = 50 a 4.5 5.5 0.36 0.36 0.44 0.44 v v *v in = v il or v ih ?24 ma i oh ?24 ma i in maximum input leakage current 5.5 0.1 1.0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1 v i oz maximum 3?state current 5.5 0.5 5.0 a v i (oe) = v il , v ih v i = v cc , gnd v o = v cc , gnd i old i ohd ?minimum dynamic output current 5.5 5.5 75 ?75 ma ma v old = 1.65 v max i cc maximum quiescent supply current 5.5 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ? maximum test duration 2.0 ms, one output loaded at a time. ac characteristics t r = t f = 3.0 ns (for figures and waveforms, see figures 2 and 3.) t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf symbol parameter v cc * (v) min max min max unit t plh propagation delay an to bn or bn to an 5.0 1.5 8.0 1.0 8.5 ns t phl propagation delay an to bn or bn to an 5.0 1.5 8.0 1.0 9.0 ns t pzh output enable time oe to an or bn 5.0 1.5 10.0 1.0 1 1.0 ns t pzl output enable time oe to an or bn 5.0 1.5 10.0 1.0 1 1.0 ns t phz output disable time t/r or oe to an or bn 5.0 1.5 10.0 1.0 1 1.0 ns t plz output disable time t/r or oe to an or bn 5.0 1.5 10.0 1.0 1 1.0 ns *voltage range 5.0 v is 5.0 v 0.5 v capacitance symbol parameter v alue typ unit t est conditions c in input capacitance 4.5 pf v cc = 5.0 v c i/o input/output capacitance 15 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v
mc74act640 http://onsemi.com 317 switching waveforms 10% figure 2. figure 3. *includes all probe and jig capacitance c l * 50 scope test point device under test output figure 4. test circuit 450 input 3.0 v gnd 50% 50% input a or b output a or b t plh t phl 90% 10% 90% t thl t tlh t r t f 50% 50% 50% gnd v ol v oh a or b a or b t pzl t plz t pzh t phz high impedance oe 10% 90% high impedance 3.0 v 3.0 v gnd t/r
mc74act640 http://onsemi.com 318 marking diagrams pdip?20 so?20 tssop?20 eiaj?20 act 640 alyw act640 aw l yyww mc74act640n aw l yyww 74act640 awl yww a= assembly location wl, l = wafer lot yy, y = year ww, w = work week
http://onsemi.com 319 chapter 3 case outlines and package dimensions
http://onsemi.com 320 device nomenclature f act circuit identifier package type ? n for plastic ? d for narrow soic ? dw for wide soic ? sd for plastic ssop ? dt for plastic tssop function type mc xxx yy wwwww t emperature range ? 74ac = fact (?40 to +85 c) ? 74act = ttl compatible (?40 to +85 c)
http://onsemi.com 321 case outlines and package dimensions pdip?14 n suffix 14 pin plastic dip package case 646?06 issue m b a

f hg d k c
n ?t? 14 pl l m j so?14 d suffix 14 pin plastic soic package case 751a?03 issue f ?a? ?b? g p 7 pl ?t? f r x 45
d 14 pl k c j m

http://onsemi.com 322 case outlines and package dimensions tssop?14 dt suffix 14 pin plastic tssop package case 948g?01 issue o

2x l/2 l ?u?
?t? ??? ??? ??? pin 1 ident. h g a d c b ?v? 14x ref k n n eiaj?14 m suffix 14 pin plastic eiaj package case 965?01 issue o h e a 1

l e q 1 d z e e a b view p c l detail p m
http://onsemi.com 323 case outlines and package dimensions ?a? b f c s h g d j l m 16 pl
! k ?t?

pdip?16 n suffix 16 pin plastic dip package case 648?08 issue r !
f j m r x 45 g 8 pl p ?b? ?a? ?t? d k c 16 pl

so?16 d suffix 16 pin plastic soic package case 751b?05 issue j
http://onsemi.com 324 case outlines and package dimensions tssop?16 dt suffix 16 pin plastic tssop package case 948f?01 issue o ??? ??? ???

section n?n
ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ?t? ?v? ?w? 16x ref k n n eiaj?16 m suffix 16 pin plastic eiaj package case 966?01 issue o h e a 1

l e q 1 m l detail p view p c a b e ! d z e
http://onsemi.com 325 case outlines and package dimensions pdip?20 n suffix 20 pin plastic dip package case 738?03 issue e m l j 20 pl

" ?a?
k n f g d 20 pl ?t? e b c so?20 dw suffix 20 pin plastic soic package case 751d?05 issue f " b 20x h 10x c l 18x a1 a
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http://onsemi.com 326 case outlines and package dimensions tssop?20 dt suffix 20 pin plastic tssop package case 948e?02 issue a

" pin 1 ident a b ?t? c d g h section n?n k k1 jj1 n n m f ?w?
?v? ?u? 20x ref k l l/2 2x detail e detail e eiaj?20 m suffix 20 pin plastic eiaj package case 967?01 issue o

h e a 1 l e q 1 c a z d e " b e view p detail p m l
http://onsemi.com 327 case outlines and package dimensions pdip?24 n suffix 24 pin plastic dip package case 724?03 issue d ?a? ?b? " $ " ?t?
24 pl k e f n c d g 24 pl j l m note 1

so?24 dw suffix 24 pin plastic soic package case 751e?04 issue e ?a? ?b? p 12x d 24x " $ " ?t? g 22x
k c r x 45 m f j

http://onsemi.com 328
http://onsemi.com 329 chapter 4 index
http://onsemi.com 330 index device number page mc74ac00 44 mc74ac02 49 mc74ac04 54 mc74ac05 59 mc74ac08 64 mc74ac10 69 mc74ac109 106 mc74ac11 74 mc74ac125 112 mc74ac132 117 mc74ac138 122 mc74ac139 128 mc74ac14 79 mc74ac151 134 mc74ac153 141 mc74ac157 147 mc74ac161 153 mc74ac163 153 mc74ac174 165 mc74ac175 171 mc74ac20 84 mc74ac240 177 mc74ac244 182 mc74ac245 187 mc74ac253 193 mc74ac257 200 mc74ac259 207 mc74ac273 215 mc74ac299 222 device number page mc74ac32 89 mc74ac373 231 mc74ac374 239 mc74ac377 246 mc74ac4040 294 mc74ac540 254 mc74ac541 254 mc74ac573 263 mc74ac574 271 mc74ac646 279 mc74ac652 287 mc74ac74 94 mc74ac86 101 mc74act00 44 mc74act02 49 mc74act04 54 mc74act05 59 mc74act08 64 mc74act10 69 mc74act109 106 mc74act11 74 mc74act125 112 mc74act132 117 mc74act138 122 mc74act139 128 mc74act14 79 mc74act151 134 mc74act153 141 mc74act157 147 device number page mc74act161 153 mc74act163 153 mc74act174 165 mc74act175 171 mc74act20 84 mc74act240 177 mc74act241 298 mc74act244 182 mc74act245 187 mc74act253 193 mc74act257 200 mc74act259 207 mc74act273 215 mc74act299 222 mc74act32 89 mc74act323 303 mc74act373 231 mc74act374 239 mc74act377 246 mc74act540 254 mc74act541 254 mc74act564 309 mc74act573 263 mc74act574 271 mc74act640 314 mc74act646 279 mc74act652 287 mc74act74 94 mc74act86 101
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http://onsemi.com 332 on semiconductor standard document type definitions data sheet classifications a data sheet is the fundamental publication for each individual product/device, or series of products/devices, containing detai led parametric information and any other key information needed in using, designing?in or purchasing of the product(s)/device(s) it describes. below are the three classifications of data sheet: product preview; advance information; and fully released technical data product preview a product preview is a summary document for a product/device under consideration or in the early stages of development. the product preview exists only until an ?advance information? document is published that replaces it. the product preview is often used as the first section or chapter in a corresponding reference manual. the product preview displays the following disclaimer at the bottom of the first page: ?this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice.? advance information the advance information document is for a device that is not fully qualified, but is in the final stages of the release process , and for which production is eminent. while the commitment has been made to produce the device, final characterization and qualification may not be complete. the advance information document is replaced with the ?fully released technical data? document once the device/part becomes fully qualified. the advance information document displays the following disclaimer at the bottom of the first page: ?this document contains information on a new product. specifications and information herein are s ubject to change without notice.? fully released technical data the fully released technical data document is for a product/device that is in full production (i.e., fully released). it replac es the advance information document and represents a part that is fully qualified. the fully released t echnical data document is virtu ally the same document as the product preview and the advance information document with the exception that it provides information that is unavailable for a product in the early phases of development, such as complete parametric characterization data. the fu lly released technical data document is also a more comprehensive document than either of its earlier incarnations. this document displays no disclaimer, and while it may be informally referred to as a ?data sheet,? it is not labeled as such. data book a data book is a publication that contains primarily a collection of data sheets, general family and/or parametric information, application notes and any other information needed as reference or support material for the data sheets. it may also contain cross referenc e or selector guide information, detailed quality and reliability information, packaging and case outline information, etc. application note an application note is a document that contains real?world application information about how a specific on semiconductor device/product is used, or information that is pertinent to its use. it is designed to address a particular technical issue. pa rts and/or software must already exist and be available. selector guide a selector guide is a document published, generally at set intervals, that contains key line?item, device?specific information for particular products or families. the selector guide is designed to be a quick reference tool that will assist a customer in det ermining the availability of a particular device, along with its key parameters and available packaging options. in essence, it a llows a customer to quickly ?select? a device. for detailed design and parametric information, the customer would then refer to the device?s data sheet. th e master components selector guide (sg388/d) is a listing of all currently available on semiconductor devices. reference manual a reference manual is a publication that contains a comprehensive system or device?specific descriptions of the structure and f unction (operation) of a particular part/system; used overwhelmingly to describe the functionality or application of a device, series o f devices or device category. procedural information in a reference manual is limited to less than 40 percent (usually much less). handbook a handbook is a publication that contains a collection of information on almost any give subject which does not fall into the r eference manual definition. the subject matter can consist of information ranging from a device specific design information, to system d esign, to quality and reliability information. addendum a documentation addendum is a supplemental publication that contains missing information or replaces preliminary information in the primary publication it supports. individual addendum items are published cumulatively. the addendum is destroyed upon the next revision of the primary document.
dl138/d brd8017/d rev. 4, apr-2002 clock and data management solutions high performance data management, advanced clock management and communication assps on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make c hanges without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data she ets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? mu st be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications int ended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. global literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit @ hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada japan : on semiconductor, japan customer focus center 4-32-1 nishi-gotanda, shinagawa-ku, tokyo, japan 141-0031 phone : 81-3-5740-2700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative publication ordering information

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