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| exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? preliminary XRT72L50 single channel ds3/e3 framer ic with hdlc controller january 2001 rev. p1.1.3 general description the XRT72L50, single channel ds3/e3 framer ic is designed to accept user data from the terminal equipment and insert this data into the payload bit- fields within an outbound ds3/e3 data stream. fur- ther, the framer ic is also designed to receive an in- bound ds3/e3 data stream (from the remote ter- minal equipment) and extract out the user data. the XRT72L50 ds3/e3 framer device is designed to support full-duplex data flow between terminal equip- ment and an liu (line interface unit) ic. the framer device will transmit, receive and process data in the ds3-c-bit parity, ds3-m13, e3-itu-t g.751 and e3- itu-t g.832 framing formats. the XRT72L50 ds3/e3 framer ic consists of a transmit section, receiver section, performance monitor section and a microprocessor interface. the transmit section, includes a transmit payload data input interface, a transmit overhead data input interface section, a transmit hdlc controller, a transmit ds3/e3 framer block and a transmit liu in- terface block which permits the terminal equipment to transmit data to a remote terminal. the receive section, consists of a receive liu inter- face, a receive ds3/e3 framer, a receive hdlc controller, a receive payload data output interface, and a receive overhead data interface which allows the local terminal equipment to receive data from re- mote terminal equipment. the microprocessor interface is used to configure the framer ic in different operating modes and monitor the performance of the framer. the performance monitor sections consist of a large number of "reset-upon-read" and "read-only" reg- isters that contain cumulative and "one-second" sta- tistics that reflect the performance/health of the fram- er ic/system. features ? transmits, receives and processes data in the ds3-c-bit parity, ds3-m13, e3-itu-t g.751 and e3-itu-t g.832 framing formats. ? 1 channel hdlc controller - tx and rx ? interfaces to all popular microprocessors ? integrated framer performance monitor ? available in a 100 pin pqfp package ? 3.3v power supply with 5v tolerant i/o ? operating temperature -40c to +85c applications ? network interface units ? csu/dsu equipment. ? pcm test equipment ? fiber optic terminals ? ds3/e3 frame relay equipment f igure 1. b lock d iagram of the XRT72L50 t3/e3 transmit framer t3 feac & data link controller t3/e3 receive framer performance monitor interrupt controller txohind txnibframe txframe txnibclk txlnclk txframeref txnib txser t3/e3 transmit input rxclk rxohind rxframe rxnib rxser rxoutclk t3/e3 receive output a(8:0) d[7:0] ale_as wr_r/w cs rdy_dtck reset int moto rd_ds up interface txlineclk txpos txneg rxlineclk rxpos rxneg extlos liu interface/ controller reset testmode nibblelntf txohenable txohclk txohframe txaisen txoh txohins t3/e3 transmit overhead interface rxohenable rxohclk rxoh rxred rxohframe rxoof t3/e3 receive overhead interface hdlc controller hdlc controller
XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 2 ordering information f igure 2. p in o ut of the XRT72L50 XRT72L50 tdo tdi vdd trst gnd rdy_dtck wr_rw cs ale_as rd_ds tck tms int gnd a(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) a(8) vdd nibbleintf vdd txohclk txohins/txhdlcdat4 txoh/txhdlcdat5 txohind/txhdlcdat6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 gnd vdd dmo extlos rlol gnd txnib3/txhdlcdat3 txnib2/txhdlcdat2 txnib1/txhdlcdat1 txnib0/txhdlcdat0 txser/sndmsg txaisen txinclk gnd txframeref vdd d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) gnd vdd testmode reset moto gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 rxpos rxneg rxlineclk gnd req rloop lloop taos txlev encodis txpos txneg txlineclk vdd txframe gnd txnibclk/sndfcs txnibframe/valfcs txohframe/txhdlcclk txohenable/txhdlcdat7 rxnib3/rxhdlcdat3 rxnib2/rxhdlcdat2 rxnib1/rxhdlcdat1 rxnib0/rxhdlcdat0 rxser/rxidle rxais rxclk gnd rxframe vdd rxoutclk/rxhdlcdat7 rxred rxoof rxlos rxohclk/rxhdlcclk rxohind rxoh/rxhdlcdat6 rxohenable/rxhdlcdat5 rxohframe/rxhdlcdat4 tdo 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p art n umber p ackage t ype o perating t emperature r ange XRT72L50 14x20mm, 100 lead plastic qfp -40c to +85c ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 i table of contents general description ............................................................................................... 1 features .............................................................................................................................. ................... 1 applications .............................................................................................................................. ............. 1 figure 1. block diagram of the XRT72L50 ...................................................................................... ...... 1 figure 2. pin out of the XRT72L50 ............................................................................................ ............ 2 ordering information ............................................................................................ 2 pin descriptions ........................................................................................................ 3 electrical characteristics .............................................................................. 20 a bsolute m aximums ............................................................................................................................. 20 dc e lectrical c haracteristics ......................................................................................................... 20 ac e lectrical c haracteristics ......................................................................................................... 20 ac e lectrical c haracteristics (c ont .) ............................................................................................ 22 1.0 timing diagrams ........................................................................................................... ...................... 26 figure 3. timing diagram for transmit payload input interface, when the XRT72L50 device is operating in both the ds3 and loop-timing modes ............................................................................................ ..... 26 figure 4. timing diagram for the transmit payload input interface, when the XRT72L50 device is operating in both the ds3 and local-timing modes ........................................................................................ ..... 26 figure 5. timing diagram for the transmit payload data input interface, when the XRT72L50 device is operating in both the ds3/nibble and looped-timing modes .............................................................. 27 figure 6. timing diagram for the transmit payload data input interface, when the XRT72L50 device is operating in the ds3/nibble and local-timing modes .......................................................................... 2 7 figure 7. timing diagram for the transmit overhead data input interface (method 1 access) .......... 28 figure 8. timing diagram for the transmit overhead data input interface (method 2 access) .......... 28 figure 9. transmit liu interface timing - framer is configured to update "txpos" and "txneg" on the rising edge of "txlineclk" .................................................................................................... ................. 29 figure 10. transmit liu interface timing - framer is configured to update "txpos" and "txneg" on the falling edge of "txlineclk" ................................................................................................... ................. 29 figure 11. receive liu interface timing - framer is configured to sample "rxpos" and "rxneg" on the rising edge of "rxlineclk" .................................................................................................... ................. 30 figure 12. receiver liu interface timing - framer is configured to sample "rxpos" and "rxneg" on the falling edge of "rxlineclk" ................................................................................................... ................. 30 figure 13. receive payload data output interface timing .................................................................. 31 figure 14. receive payload data output interface timing (nibble mode operation) ......................... 31 figure 15. receive overhead data output interface timing (method 1 - using rxohclk) ................ 32 figure 16. receive overhead data output interface timing (method 2 - using rxohenable) .......... 32 figure 17. microprocessor interface timing - intel type programmed i/o read operations .............. 33 figure 18. microprocessor interface timing - intel type programmed i/o write operations .............. 33 figure 19. microprocessor interface timing - intel type read burst access operation ..................... 34 figure 20. microprocessor interface timing - intel type write burst access operation ....................... 34 figure 21. microprocessor interface timing - motorola type programmed i/o read operation ........ 35 figure 22. microprocessor interface timing - motorola type programmed i/o write operation ......... 35 figure 23. microprocessor interface timing - reset pulse width ........................................................ 36 2.0 the microprocessor interface block ........................................................................................ ......... 37 figure 24. simple block diagram of the microprocessor interface block, within the framer ic .......... 37 2.1 t he m icroprocessor i nterface b lock s ignal .............................................................................................. 37 t able 1: d escription of the m icroprocessor i nterface s ignals that exhibit constant roles in both the i ntel and m otorola m odes .......................................................................................................... 38 t able 2: p in d escription of m icroprocessor i nterface s ignals - w hile the m icroprocessor i nter - face is o perating in the i ntel m ode .................................................................................................. 38 t able 3: p in d escription of the m icroprocessor i nterface s ignals while the m icroprocessor i n - terface is operating in the m otorola m ode .................................................................................... 39 2.2 i nterfacing the XRT72L50 ds3/e3 f ramer to the l ocal c/p via the m icroprocessor i nterface b lock XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary ii 39 2.2.1 interfacing the XRT72L50 ds3/e3 framer to the microprocessor over an 8 bit wide bi-directional data bus 39 2.2.2 data access modes ....................................................................................................... ......................... 40 figure 25. behavior of microprocessor interface signals during an intel-type programmed i/o read oper- ation ......................................................................................................................... .............................. 41 figure 26. behavior of the microprocessor interface signals, during an intel-type programmed i/o write operation ..................................................................................................................... .......................... 42 figure 27. illustration of the behavior of microprocessor interface signals, during a motorola-type pro- grammed i/o read operation .................................................................................................... ........... 43 figure 28. illustration of the behavior of the microprocessor interface signal, during a motorola-type pro- grammed i/o write operation ................................................................................................... ............ 44 figure 29. behavior of the microprocessor interface signals, during the initial read operation of a burst cycle (intel type processor) .................................................................................................. ............... 45 figure 30. behavior of the microprocessor interface signals, during subsequent read operations within the burst i/o cycle ........................................................................................................... ..................... 46 figure 31. behavior of the microprocessor interface signals, during the initial write operation of a burst cycle (intel-type processor) .................................................................................................. ................ 47 figure 32. behavior of the microprocessor interface signals, during subsequent write operations within the burst i/o cycle ........................................................................................................... ..................... 48 figure 33. behavior of the microprocessor interface signals, during the initial read operation of a burst cycle (motorola type processor) ............................................................................................... ........... 49 figure 34. behavior the microprocessor interface signals, during subsequent read operations within the burst i/o cycle (motorola-type c/p) ......................................................................................... ......... 50 figure 35. behavior of the microprocessor interface signals, during the initial write operation of a burst cycle (motorola-type processor) ............................................................................................... ............ 51 figure 36. behavior of the microprocessor interface signals, during subsequent write operations with the burst i/o cycle (motorola-type c/p) ......................................................................................... ......... 52 2.3 o n -c hip r egister o rganization ...................................................................................................................... 52 2.3.1 framer register addressing .............................................................................................. ...................... 52 t able 4: r egister a ddressing of the f ramer p rogrammer r egisters ......................................... 53 2.3.2 framer register description ............................................................................................. ....................... 56 p art n umber r egister (a ddress = 0 x 02) .......................................................................................... 59 v ersion n umber r egister (a ddress = 0 x 03) ..................................................................................... 59 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ........................................................................ 59 b lock i nterrupt s tatus r egister (a ddress = 0 x 05) ........................................................................ 60 test r egister (a ddress = 0 x 0c) ....................................................................................................... 61 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ........................................................... 62 r x ds3 s tatus r egister (a ddress = 0 x 11) ........................................................................................ 63 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 64 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 65 r x ds3 sync d etect e nable r egister (a ddress = 0 x 14) ................................................................ 67 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................... 67 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................... 68 r x ds3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 69 2.3.3 receive e3 framer configuration registers (itu-t g.832) ................................................................. ... 69 r x e3 c onfiguration & s tatus r egister 1 (a ddress = 0 x 10) ........................................................... 70 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................... 71 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................... 72 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) .................................................................... 73 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................... 73 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) .................................................................... 75 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) .............................................................................. 76 r x e3 lapd s tatus r egister (a ddress = 0 x 19) ................................................................................ 76 r x e3 nr b yte r egister (a ddress = 0 x 1a) ........................................................................................ 77 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 iii r x e3 gc b yte r egister (a ddress = 0 x 1b) ....................................................................................... 77 r x e3 ttb-0 r egister (a ddress = 0 x 1c) ............................................................................................ 78 r x e3 ttb-1 r egister (a ddress = 0 x 1d) ............................................................................................ 78 r x e3 ttb-2 r egister (a ddress = 0 x 1e) ............................................................................................ 78 r x e3 ttb-3 r egister (a ddress = 0 x 1f) ............................................................................................ 79 r x e3 ttb-4 r egister (a ddress = 0 x 20) ............................................................................................ 79 r x e3 ttb-5 r egister (a ddress = 0 x 21) ............................................................................................ 79 r x e3 ttb-6 r egister (a ddress = 0 x 22) ............................................................................................ 79 r x e3 ttb-7 r egister (a ddress = 0 x 23) ............................................................................................ 80 r x e3 ttb-8 r egister (a ddress = 0 x 24) ............................................................................................ 80 r x e3 ttb-9 r egister (a ddress = 0 x 25) ............................................................................................ 80 r x e3 ttb-10 r egister (a ddress = 0 x 26) .......................................................................................... 81 r x e3 ttb-11 r egister (a ddress = 0 x 27) .......................................................................................... 81 r x e3 ttb-12 r egister (a ddress = 0 x 28) .......................................................................................... 81 r x e3 ttb-13 r egister (a ddress = 0 x 29 ........................................................................................... 81 r x e3 ttb-14 r egister (a ddress = 0 x 2a) .......................................................................................... 82 r x e3 ttb-15 r egister (a ddress = 0 x 2b) .......................................................................................... 82 r x e3 ssm r egister (a ddress = 0 x 2b) ................................................................................................ 82 2.3.4 receive e3 framer configuration registers (itu-t g.751) ................................................................. .. 83 r x e3 c onfiguration & s tatus r egister - 1 g.751 (a ddress = 0 x 10) ............................................. 83 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ........................................................ 83 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) ................................................................... 84 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) ................................................................... 85 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) ................................................................... 85 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................... 86 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ............................................................................. 87 r x e3 lapd s tatus r egister (a ddress = 0 x 19) ................................................................................ 87 r x e3 s ervice b it r egister (a ddress = 0 x 1a) ................................................................................... 88 2.3.5 transmit ds3 configuration registers .................................................................................... ................ 88 t ransmit ds3 c onfiguration r egister (a ddress = 0 x 30) ............................................................... 89 t ransmit ds3 feac c onfiguration & s tatus r egister (a ddress = 0 x 31) .................................... 90 t x ds3 feac r egis t er (a ddress = 0 x 32) .......................................................................................... 91 t x ds3 lapd c onfiguration r egister (a ddress = 0 x 33) ................................................................. 91 t x ds3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ..................................................... 92 t x ds3 m-b it m ask r egister (a ddress = 0 x 35) ................................................................................. 92 t x ds3 f-b it m ask r egister - 1 (a ddress = 0 x 36) ............................................................................. 93 t x ds3 f-b it m ask r egister - 2 (a ddress = 0 x 37) ............................................................................. 94 t x ds3 f-b it m ask r egister - 3 (a ddress = 0 x 38) ............................................................................. 94 t x ds3 f-b it m ask r egister - 4 (a ddress = 0 x 39) ............................................................................. 94 2.3.6 transmit e3 (itu-t g.832) configuration registers ....................................................................... ........ 94 t x e3 c onfiguration r egister (a ddress = 0 x 30) .............................................................................. 95 t x e3 lapd c onfiguration r egister (a ddress = 0 x 33) ................................................................... 96 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ........................................................ 96 t x e3 gc b yte r egister (a ddress = 0 x 35) ........................................................................................ 97 t x e3 ma b yte r egister (a ddress = 0 x 36) ........................................................................................ 98 t x e3 ma b yte r egister (a ddress = 0 x 36) ........................................................................................ 98 t x e3 nr b yte r egister (a ddress = 0 x 37) ........................................................................................ 98 t x e3 ttb-0 r egister (a ddress = 0 x 38) ............................................................................................. 99 t x e3 ttb-1 r egister (a ddress = 0 x 39) ............................................................................................. 99 t x e3 ttb-2 r egister (a ddress = 0 x 3a) ............................................................................................ 99 t x e3 ttb-3 r egister (a ddress = 0 x 3b) .......................................................................................... 100 t x e3 ttb-4 r egister (a ddress = 0 x 3c) .......................................................................................... 100 t x e3 ttb-5 r egister (a ddress = 0 x 3d) .......................................................................................... 101 t x e3 ttb-6 r egister (a ddress = 0 x 3e) .......................................................................................... 101 t x e3 ttb-7 r egister (a ddress = 0 x 3f) .......................................................................................... 101 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary iv t x e3 ttb-8 r egister (a ddress = 0 x 40) ........................................................................................... 102 t x e3 ttb-9 r egister (a ddress = 0 x 41) ........................................................................................... 102 t x e3 ttb-10 r egister (a ddress = 0 x 42) ......................................................................................... 103 t x e3 ttb-11 r egister (a ddress = 0 x 43) ......................................................................................... 103 t x e3 ttb-12 r egister (a ddress = 0 x 44) ......................................................................................... 103 t x e3 ttb-13 r egister (a ddress = 0 x 45) ......................................................................................... 104 t x e3 ttb-14 r egister (a ddress = 0 x 46) ......................................................................................... 104 t x e3 ttb-15 r egister (a ddress = 0 x 47) ......................................................................................... 104 t x e3 fa1 e rror m ask r egister (a ddress = 0 x 48) ......................................................................... 105 t x e3 fa2 e rror m ask r egister (a ddress = 0 x 49) ......................................................................... 105 t x e3 bip-8 e rror m ask r egister (a ddress = 0 x 4a) ...................................................................... 105 2.3.7 transmit e3 framer configuration registers (itu-t g.751) ................................................................ . 106 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 106 t x e3 lapd c onfiguration r egister (a ddress = 0 x 33) .................................................................. 107 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 108 t x e3 s ervice b its r egister (a ddress = 0 x 35) ................................................................................ 109 t x e3 fas e rror m ask r egister - 0 (a ddress = 0 x 48) ................................................................... 109 t x e3 fas e rror m ask r egister - 1 (a ddress = 0 x 49) ................................................................... 109 t x e3 bip-4 e rror m ask r egister (a ddress = 0 x 4a) ...................................................................... 110 2.3.8 performance monitor registers ........................................................................................... .................. 110 pmon lcv e vent c ount r egister - lsb (a ddress = 0 x 51) ........................................................... 110 pmon f raming b it /b yte e rror c ount r egister - msb (a ddress = 0 x 52) ................................... 111 pmon f raming b it /b yte e rror c ount r egister - lsb (a ddress = 0 x 53) .................................... 111 pmon p arity e rror c ount r egister - msb (a ddress = 0 x 54) ..................................................... 111 pmon p arity e rror c ount r egister - lsb (a ddress = 0 x 55) ...................................................... 111 pmon febe e vent c ount r egister - msb (a ddress = 0 x 56) ........................................................ 112 pmon febe e vent c ount r egister - lsb (a ddress = 0 x 57) ......................................................... 112 pmon cp-b it e rror c ount r egister - msb (a ddress = 0 x 58) ..................................................... 112 pmon cp-b it e rror c ount r egister - lsb (a ddress = 0 x 59) ...................................................... 113 pmon h olding r egister (a ddress = 0 x 6c) ..................................................................................... 113 o ne -s econd e rror s tatus r egister (a ddress = 0 x 6d) ................................................................ 113 lcv - o ne -s econd a ccumulator r egister - msb (a ddress = 0 x 6e) ............................................ 114 lcv - o ne -s econd a ccumulator r egister - lsb (a ddress = 0 x 6f) .............................................. 114 f rame p arity e rrors - o ne -s econd a ccumulator r egister - msb (a ddress = 0 x 70) ................ 114 f rame p arity e rrors - o ne -s econd a ccumulator r egister - lsb (a ddress = 0 x 71) ................. 115 f rame cp-b it e rrors - o ne -s econd a ccumulator r egister - msb (a ddress = 0 x 72) ............... 115 f rame p arity e rrors - o ne -s econd a ccumulator r egister - lsb (a ddress = 0 x 73) ................. 115 l ine i nterface d rive r egister (a ddress = 0 x 80) ............................................................................ 116 l ine i nterface s can r egister (a ddress = 0 x 81) ............................................................................. 118 hdlc c ontrol r egister (a ddress = 0 x 82) ..................................................................................... 119 2.4 t he l oss of c lock e nable f eature ............................................................................................................. 119 a ddress = 0 x 01, f ramer i/o c ontrol r egister .............................................................................. 120 2.5 u sing the pmon h olding r egister .............................................................................................................. 120 2.6 t he i nterrupt s tructure within the f ramer m icroprocessor i nterface s ection ................................. 120 t able 5: l ist of all of the p ossible c onditions that can g enerate i nterrupts within each channel of the XRT72L50 f ramer d evice ...................................................................................................... 121 t able 6: a l isting of the XRT72L50 f ramer d evice i nterrupt b lock r egisters ( for ds3 a pplica - tions ) ............................................................................................................................. ...................... 121 t able 7: a l isting of the XRT72L50 f ramer d evice i nterrupt b lock r egisters ( for e3, itu-t g.832 a pplications ) ............................................................................................................................. ......... 121 t able 8: a l isting of the XRT72L50 f ramer d evice i nterrupt b lock r egister ( for e3, itu-t g.751 a pplications ) ............................................................................................................................. ......... 122 b lock i nterrupt s tatus r egister (a ddress = 0 x 05) ...................................................................... 122 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ...................................................................... 123 t able 9: i nterrupt s ervice r outine g uide ( for ds3 a pplications ) ............................................. 123 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 v t able 10: i nterrupt s ervice r outine g uide ( for e3, itu-t g.832 a pplications ) ....................... 124 t able 11: i nterrupt s ervice r outine g uide ( for e3, itu-t g.751 a pplications ) ....................... 124 2.6.1 automatic reset of interrupt enable bits ................................................................................ .............. 124 framer operating mode r egister (a ddress = 0 x 00) ...................................................................... 125 2.6.2 one-second interrupts ................................................................................................... ....................... 125 2.7 i nterfacing the framer to an intel - type microprocessor ........................................................................ 125 t able 12: a lternate f unctions of p ort 3 p ins ............................................................................. 126 t able 13: i nterrupt s ervice r outine l ocation ( in c ode m emory ) for the int0* and int1* i nterrupt i nput pins .............................................................................................................................. .............. 127 figure 37. schematic depicting how to interface the XRT72L50 ds3/e3 framer ic to the 8051 microcon- troller ....................................................................................................................... ............................ 127 2.8 i nterfacing the f ramer ic to a m otorola - type m icroprocessor ............................................................ 128 figure 38. schematic depicting how to interface the XRT72L50 ds3/e3 framer ic to the mc68000 micro- processor ..................................................................................................................... ....................... 128 t able 14: a uto -v ector t able for the mc68000 m icroprocessor .............................................. 129 3.0 the line interface and scan section ....................................................................................... ......... 129 figure 39. schematic depicting how to interface the XRT72L50 ds3/e3 framer ic to the xrt73l00 ds3/ e3/sts-1 liu ic (one channel shown) ........................................................................................... .... 130 3.1 b it -f ields within the l ine i nterface d rive r egister .................................................................................. 130 line interface drive r egister (a ddress = 0 x 80) ..................................................................... 130 t able 15: t he r elationship between the states of rloop, lloop and the resulting loop - back mode with the xrt7300 device .................................................................................................................. 132 3.2 b it -f ields within the l ine i nterface s can r egister ................................................................................... 132 line interface s can r egister (a ddress = 0 x 81) ...................................................................... 133 XRT72L50 configuration ..................................................................................... 135 4.0 ds3 operation of the XRT72L50 ............................................................................................. ......... 135 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 135 4.1 d escription of the ds3 f rames and a ssociated o verhead b its .............................................................. 135 figure 40. ds3 frame format for c-bit parity ................................................................................. .. 135 figure 41. ds3 frame format for m13 .......................................................................................... .... 136 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 136 t able 16: t he r elationship between the content of b it 2, (c-b it p arity */m13) within the f ramer o p - erating m ode r egister and the resulting ds3 f raming f ormat ................................................. 137 t able 17: c- bit f unctions for the c- bit p arity ds3 f rame f ormat ............................................ 137 4.1.1 frame synchronization bits (applies to both m13 and c-bit parity framing formats) ......................... 137 4.1.2 performance monitoring/error detection bits (parity) .................................................................... ....... 138 4.1.3 alarm and signaling-related overhead bits ............................................................................... .......... 138 valid m-bits, f-bits, and p-bits ........................................................................................ 138 4.1.4 the data link related overhead bits ..................................................................................... .............. 139 4.2 t he t ransmit s ection of the XRT72L50 (ds3 m ode o peration ) ............................................................... 139 figure 42. a simple illustration of the transmit section, within the XRT72L50, when it has been configured to operate in the ds3 mode .................................................................................................... ............ 140 4.2.1 the transmit payload data input interface block ......................................................................... ........ 140 figure 43. a simple illustration of the transmit payload data input interface block ......................... 141 t able 18: l isting and d escription of the pins associated with the t ransmit p ayload d ata i nput i n - terface .............................................................................................................................. ................. 142 figure 44. illustration of the terminal equipment being interfaced to the transmit payload data input inter- face block (of the XRT72L50) for mode 1(serial/loop-timing) operation .......................................... 144 figure 45. behavior of the terminal interface signals between the transmit payload data input interface block of the XRT72L50 and the terminal equipment (for mode 1 operation) .................................... 145 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 145 figure 46. illustration of the terminal equipment being interfaced to the transmit payload data input inter- face block of the XRT72L50 for mode 2 (serial/local-timed/frame-slave) operation ...................... 146 figure 47. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (mode 2 operation) ............................................................................................................ ................. 147 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary vi f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 147 figure 48. illustration of the terminal equipment being interfaced to the transmit payload data input inter- face block of the XRT72L50 for mode 3 (serial/local-timed/frame-master) operation .................... 148 figure 49. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (ds3 mode 3 operation) ........................................................................................................ ............. 149 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 150 figure 50. illustration of the terminal equipment being interfaced to the transmit payload data input inter- face block of the XRT72L50 for mode 4 (nibble-parallel/loop-timed) operation .............................. 151 figure 51. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (mode 4 operation) ............................................................................................................ ................. 152 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 152 figure 52. illustration of the terminal equipment being interfaced to the transmit payload data input inter- face block of the XRT72L50 for mode 5 (nibble-parallel/local-timed/frame-slave) operation ........ 154 figure 53. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (ds3 mode 5 operation) ........................................................................................................ ............. 155 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 155 figure 54. illustration of the terminal equipment being interfaced to the transmit payload data input inter- face block of the XRT72L50 for mode 6 (nibble-parallel/local-timed/frame-master) operation ...... 156 figure 55. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (ds3 mode 6 operation) ........................................................................................................ ............. 157 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 158 4.2.2 the transmit overhead data input interface .............................................................................. .......... 158 figure 56. simple illustration of the transmit overhead data input interface block .......................... 158 t able 19: a l isting of the o verhead bits within the ds3 frame , and their potential sources , within the XRT72L50 ic .................................................................................................................. .............. 159 t able 20: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals ...................... 160 figure 57. illustration of the terminal equipment being interfaced to the transmit overhead data input in- terface (method 1) ............................................................................................................ ................... 161 t able 21: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since t x o- hf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being processed ............... 162 figure 58. illustration of the signal that must occur between the terminal equipment and the XRT72L50, in order to configure the XRT72L50 to transmit a yellow alarm to the remote terminal equipment .... 164 t able 22: d escription of m ethod 2 t ransmit o verhead i nput i nterface s ignals ...................... 165 figure 59. illustration of the terminal equipment being interfaced to the transmit overhead data input in- terface (method 2) ............................................................................................................ ................... 166 t able 23: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the ds3 o verhead b it , that is being processed by the XRT72L50 167 figure 60. behavior of transmit overhead data input interface signals between the XRT72L50 and the terminal equipment (for method 2) ............................................................................................. ........ 169 4.2.3 the transmit ds3 hdlc controller ........................................................................................ .............. 169 t x ds3 feac r egister (a ddress = 0 x 32) ........................................................................................ 170 t ransmit ds3 feac c onfiguration and s tatus r egister (a ddress = 0 x 31) ............................... 170 t ransmit ds3 feac c onfiguration and s tatus r egister (a ddress = 0 x 31) ............................... 170 figure 61. a flow chart depicting how to transmit a feac message via the feac transmitter ...... 171 figure 62. lapd message frame format ......................................................................................... . 172 t able 24: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i nfor - mation p ayload .............................................................................................................................. .... 172 t ransmit ds3 lapd c onfiguration r egister (a ddress = 0 x 33) ................................................... 173 t able 25: r elationship between t x lapd m sg l ength and the lapd m essage s ize .................. 173 t ransmit ds3 lapd c onfiguration r egister (a ddress = 0 x 33) ................................................... 173 t able 26: r elationship between t x lapd m sg l ength and the lapd m essage s ize .................. 173 t ransmit ds3 lapd s tatus /i nterrupt r egister (a ddress = 0 x 34) ............................................... 174 figure 63. flow chart depict how to use the lapd transmitter ........................................................ 175 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 176 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ...................................................................... 176 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 vii 4.2.4 the transmit ds3 framer block ........................................................................................... ................ 176 figure 64. a simple illustration of the transmit ds3 framer block and the associated paths to other func- tional blocks ................................................................................................................. ....................... 177 t x ds3 c onfiguration r egister (a ddress = 0 x 30) ........................................................................ 178 t able 27: t he r elationship between the contents of b it 7 (t x y ellow a larm ) within the t x ds3 c on - figuration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction .......................... 178 t able 28: t he r elationship between the contents of b it 6 (t x x-b its ) within the t x ds3 c onfigura - tion r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction ..................................... 178 t able 29: t he r elationship between the contents of b it 5 (t x i dle ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer a ction .......................................................... 179 t able 30: t he r elationship between the contents of b it 4 (t x ais p attern ) within the t x ds3 c on - figuration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction .......................... 179 t able 31: t he r elationship between the contents of b it 3 (t x los) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction ............................................. 180 t x ds3 m-b it m ask r egister , a ddress = 0 x 35 ............................................................................... 180 t x ds3 f-b it m ask 1 r egister , a ddress = 0 x 36 .............................................................................. 181 t x ds3 f-b it m ask 2 r egister , a ddress = 0 x 37 .............................................................................. 181 t x ds3 f-b it m ask 3 r egister , a ddress = 0 x 38 .............................................................................. 181 t x ds3 f-b it m ask 4 r egister , a ddress = 0 x 39 .............................................................................. 181 4.2.5 the transmit ds3 line interface block ................................................................................... .............. 181 figure 65. approach to interfacing the XRT72L50 framer ic to the xrt73l00 ds3/e3/sts-1 transmitter liu (one channel shown) ....................................................................................................... ............. 182 figure 66. a simple illustration of the transmit ds3 liu interface block .......................................... 183 figure 67. the behavior of txpos and txneg signals during data transmission while the transmit ds3 liu interface is operating in the unipolar mode ............................................................................... ... 183 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 184 t able 32: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c on - trol r egister and the t ransmit ds3 f ramer l ine i nterface o utput m ode ................................ 184 figure 68. illustration of ami line code ..................................................................................... ........ 185 figure 69. illustration of two examples of b3zs encoding ................................................................. 185 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 186 t able 33: t he r elationship between b it 4 (ami/b3zs*) within the i/o c ontrol r egister and the b i - polar l ine c ode that is output by the t ransmit ds3 liu i nterface b lock ................................. 186 ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 186 t able 34: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ..................... 186 figure 70. waveform/timing relationship between txlineclk, txpos and txneg - txpos and txneg are configured to be updated on the rising edge of txlineclk ............................................................ 187 figure 71. waveform/timing relationship between txlineclk, txpos and txneg - txpos and txneg are configured to be updated on the falling edge of txlineclk ........................................................... 187 4.2.6 transmit section interrupt processing ................................................................................... ............... 187 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ..................................................................... 188 t ransmit ds3 feac c onfiguration & s tatus r egister (a ddress = 0 x 31) .................................. 188 t ransmit ds3 feac c onfiguration & s tatus r egister (a ddress = 0 x 31) .................................. 189 t x ds3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ................................................... 189 t x ds3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ................................................... 190 4.3 t he r eceive s ection of the XRT72L50 (ds3 m ode o peration ) ................................................................. 190 figure 72. a simple illustration of the receive section of the XRT72L50, when it has been configured to operate in the ds3 mode ....................................................................................................... ............. 190 4.3.1 the receive ds3 liu interface block ..................................................................................... .............. 190 figure 73. a simple illustration of the receive ds3 liu interface block ........................................... 191 figure 74. behavior of the rxpos, rxneg and rxlineclk signals during data reception of unipolar data 191 ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 192 t able 35: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary viii r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ..................... 192 figure 75. illustration on how the receive ds3 framer (within the XRT72L50 framer ic) being interfaced to thexrt73l00 liu, while the framer is operating in bipolar mode (one channel shown) ............... 192 figure 76. illustration of ami line code ..................................................................................... ........ 193 figure 77. illustration of two examples of b3zs decoding ................................................................. 194 ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 194 t able 36: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r eg - ister , and the sampling edge of the r x l ine c lk signal ................................................................... 194 figure 78. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the rising edge of rxlineclk ................................................................ 195 figure 79. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the falling edge of rxlineclk ............................................................... 195 4.3.2 the receive ds3 framer block ............................................................................................ ................ 195 figure 80. a simple illustration of the receive ds3 framer block and the associated paths to the other functional blocks ............................................................................................................. ................... 196 figure 81. the state machine diagram for the receive ds3 framer block's frame acquisition/mainte- nance algorithm ............................................................................................................... .................... 197 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 198 t able 37: t he r elationship between the contents of b it 2 (f raming on p arity ) within the r x ds3 c onfiguration and s tatus r egister , and the resulting f raming a cquisition c riteria .............. 198 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 198 t able 38: t he r elationship between the contents of b it 1 (f-s ync a lgo ) within the r x ds3 c onfig - uration and s tatus r egister , and the resulting f- bit oof d eclaration criteria used by the r eceive ds3 f ramer block ............................................................................................................................. 199 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 199 t able 39: t he r elationship between the contents of b it 0 (m-s ync a lgo ) within the r x ds3 c onfig - uration and s tatus r egister , and the resulting m-b it oof d eclaration c riteria used by the r e - ceive ds3 f ramer block .................................................................................................................... 199 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 199 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 200 pmon f raming b it e rror e vent c ount r egister - msb (a ddress = 0 x 52) ................................. 200 pmon f raming b it e rror e vent c ount r egister - lsb (a ddress = 0 x 53) .................................. 200 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 201 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 201 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 202 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 202 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ................................................... 202 r x ds3 s tatus r egister (a ddress = 0 x 11) ..................................................................................... 203 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 203 r x ds3 s tatus r egister (a ddress = 0 x 11) ...................................................................................... 204 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ..................................................................... 204 pmon p arity e rror e vent c ount r egister - msb (a ddress = 0 x 54) .......................................... 204 pmon p arity e rror e vent c ount r egister - lsb (a ddress = 0 x 55) ........................................... 204 figure 82. a simple illustration of the locations of the source, mid-network and sink terminal equipment (for cp-bit processing) ....................................................................................................... ................. 205 figure 83. illustration of the presumed configuration of the mid-network terminal equipment ........ 206 4.3.3 the receive hdlc controller block ....................................................................................... .............. 207 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................ 208 r x ds3 feac r egister (a ddress = 0 x 16) ....................................................................................... 208 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................ 208 figure 84. flow diagram depicting how the receive feac processor functions ............................. 209 figure 85. lapd message frame format ......................................................................................... . 210 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................ 210 r x ds3 lapd s tatus r egister (a ddress = 0 x 19) ........................................................................... 210 t able 40: t he r elationship between r x lapdt ype [1:0] and the resulting lapd m essage type and ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 ix size .............................................................................................................................. ........................ 211 figure 86. flow chart depicting the functionality of the lapd receiver .......................................... 212 4.3.4 the receive overhead data output interface .............................................................................. ........ 212 figure 87. a simple illustration of the receive overhead output interface block ............................. 213 t able 41: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock .............................................................................................................................. .. 214 figure 88. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 1). ............................................................................................... ............. 214 t able 42: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x o- hf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being output via the r x oh output pin .............................................................................................................................. ......................... 215 figure 89. illustration of the signals that are output via the receive overhead output interface (for method 1). ........................................................................................................................... ............................. 217 t able 43: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (m ethod 2) ............................................................................................................. 218 figure 90. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 2). ............................................................................................... ............. 219 t able 44: t he r elationship between the n umber of r x ohe nable output pulses (( since r x ohf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being output via the r x oh output pin 220 figure 91. illustration of the signals that are output via the receive overhead data output interface block (for method 2). ............................................................................................................... ...................... 222 4.3.5 the receive payload data output interface ............................................................................... .......... 222 figure 92. a simple illustration of the receive payload data output interface block ........................ 223 t able 45: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i n - terface block .............................................................................................................................. ...... 224 figure 93. illustration of the XRT72L50 ds3/e3 framer ic being interfaced to the receive terminal equip- ment (serial mode operation) .................................................................................................. ........... 225 figure 94. an illustration of the behavior of the signals between the receive payload data output interface block of the XRT72L50 and the terminal equipment (serial mode operation) .................................. 226 figure 95. illustration of the XRT72L50 ds3/e3 framer ic being interfaced to the receive section of the terminal equipment (nibble-mode operation) ................................................................................... 227 figure 96. an illustration of the behavior of the signals between the receive payload data output interface block of the XRT72L50 and the terminal equipment (nibble-mode operation). ............................... 228 4.3.6 receive section interrupt processing .................................................................................... ............... 228 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ..................................................................... 229 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) .................................................................... 229 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 230 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ......................................................... 230 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) .................................................................... 231 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 231 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ......................................................... 231 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) .................................................................... 232 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 232 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ......................................................... 233 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) .................................................................... 233 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 234 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ......................................................... 234 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) .................................................................... 234 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 235 r x ds3 s tatus r egister (a ddress = 0 x 11) ...................................................................................... 235 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) .................................................................... 235 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 236 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) .................................................................... 236 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) .................................................................... 236 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary x r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ..................................................................... 237 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ..................................................................... 237 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................. 238 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................. 238 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................. 239 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................. 239 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ......................................................................... 240 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ......................................................................... 240 5.0 e3/itu-t g.751 operation of the XRT72L50 .................................................................................. ... 241 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 241 5.1 d escription of the e3, itu-t g.751 f rames and a ssociated o verhead b its ........................................... 241 figure 97. illustration of the e3, itu-t g.751 framing format. ......................................................... 241 5.1.1 definition of the overhead bits ......................................................................................... ..................... 241 5.2 t he t ransmit s ection of the XRT72L50 (e3, itu-t g.751 m ode o peration ) ............................................ 242 figure 98. a simple illustration of the XRT72L50 transmit section when it has been configured to operate in the e3 mode ................................................................................................................ .................... 242 5.2.1 the transmit payload data input interface block ......................................................................... ........ 242 figure 99. a simple illustration of the transmit payload data input interface block ......................... 243 t able 46: l isting and d escription of the pins associated with the t ransmit p ayload d ata i nput i n - terface .............................................................................................................................. ................. 244 figure 100. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 1 (serial/loop-timed) operation ........................................ 245 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 246 figure 101. behavior of the terminal interface signals between the XRT72L50 transmit payload data input interface block and the terminal equipment (for mode 1 operation) .................................................. 248 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 248 figure 102. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 2 (serial/local-timed/frame-slave) operation .................. 249 figure 103. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (mode 2 operation) ............................................................................................................ ................. 250 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 250 figure 104. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 3 (serial/local-time/frame-master) operation .................. 251 figure 105. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (e3 mode 3 operation) ......................................................................................................... ............... 252 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 252 figure 106. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 4 (nibble-parallel/loop-timed) operation .......................... 253 figure 107. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (mode 4 operation) ............................................................................................................ ................. 254 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 254 figure 108. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 5 (nibble-parallel/local-timed/frame-slave) operation .... 256 figure 109. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (e3, mode 5 operation) ........................................................................................................ ............... 257 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 257 figure 110. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 6 (nibble-parallel/local-timed/frame-master) operation .. 258 figure 111. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (e3 mode 6 operation) ......................................................................................................... ............... 259 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 259 5.2.2 the transmit overhead data input interface .............................................................................. .......... 259 figure 112. simple illustration of the transmit overhead data input interface block ........................ 260 t able 47: a l isting of the o verhead bits within the e3 frame , and their potential sources , within the XRT72L50 ic .................................................................................................................. .............. 261 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 xi t able 48: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals ..................... 262 figure 113. illustration of the terminal equipment being interfaced to the transmit overhead data input interface (method 1) .......................................................................................................... .................. 263 t able 49: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since t x o- hf rame was last sampled "h igh ") to the e3 o verhead b it , that is being processed ................. 264 figure 114. illustration of the signal that must occur between the terminal equipment and the XRT72L50 in order to configure the XRT72L50 to transmit a yellow alarm to the remote terminal equipment ... 265 t able 50: d escription of m ethod 2 t ransmit o verhead i nput i nterface s ignals ..................... 266 figure 115. illustration of the terminal equipment being interfaced to the transmit overhead data input interface (method 2) .......................................................................................................... .................. 267 t able 51: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the e3 o verhead b it , that is being processed by the XRT72L50 268 figure 116. behavior of transmit overhead data input interface signals between the XRT72L50 and the terminal equipment (for method 2) ............................................................................................. ....... 269 5.2.3 the transmit e3 hdlc controller ......................................................................................... ............... 269 figure 117. lapd message frame format ....................................................................................... 270 t able 52: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i nfor - mation p ayload .............................................................................................................................. .... 270 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 271 t ransmit e3 lapd c onfiguration r egister (a ddress = 0 x 33) ..................................................... 271 t able 53: r elationship between t x lapd m sg l ength and the lapd m essage s ize .................. 272 t x e3 lapd c onfiguration r egister (a ddress = 0 x 33) ................................................................. 272 t ransmit e3 lapd c onfiguration r egister (a ddress = 0 x 33) ..................................................... 272 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 273 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 273 figure 118. flow chart depicting how to use the lapd transmitter ................................................. 275 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ..................................................................... 276 5.2.4 the transmit e3 framer block ............................................................................................ ................. 277 figure 119. a simple illustration of the transmit e3 framer block and the associated paths to other func- tional blocks ................................................................................................................. ....................... 278 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 278 t able 54: t he r elationship between the contents of b it 2 (t x ais e nable ) within the t x e3 c onfig - uration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction ................................. 279 t able 55: t he r elationship between the contents of b it 1 (t x los) within the t x e3 c onfiguration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction ............................................... 279 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 279 t x e3 s ervice b its r egister (a ddress = 0 x 35) ................................................................................ 280 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 280 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 281 t x e3 fas e rror m ask r egister - 0 (a ddress = 0 x 48) ................................................................... 281 t x e3 fas e rror m ask r egister - 1 (a ddress = 0 x 49) ................................................................... 281 t x e3 bip-4 e rror m ask r egister (a ddress = 0 x 4a) ...................................................................... 282 5.2.5 the transmit e3 line interface block .................................................................................... ............... 282 figure 120. approach to interfacing the XRT72L50 framer ic to the xrt73l00 ds3/e3/sts-1 liu 282 figure 121. a simple illustration of the transmit e3 liu interface block ........................................... 283 figure 122. the behavior of txpos and txneg signals during data transmission while the transmit ds3 liu interface is operating in the unipolar mode ............................................................................... ... 284 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 284 t able 56: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c on - trol r egister and the t ransmit e3 f ramer l ine i nterface o utput m ode .................................. 284 figure 123. illustration of ami line code .................................................................................... ....... 285 figure 124. illustration of two examples of hdb3 encoding .............................................................. 286 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 286 t able 57: t he r elationship between b it 4 (ami/hdb3*) within the i/o c ontrol r egister and the b i - polar l ine c ode that is output by the t ransmit e3 liu i nterface b lock ................................... 286 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary xii ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 286 t able 58: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ..................... 287 figure 125. waveform/timing relationship between txlineclk, txpos and txneg - txpos and txneg are configured to be updated on the rising edge of txlineclk ............................................................ 287 figure 126. waveform/timing relationship between txlineclk, txpos and txneg - txpos and txneg are configured to be updated on the falling edge of txlineclk ........................................................... 288 5.2.6 transmit section interrupt processing ................................................................................... ............... 288 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ...................................................................... 288 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 289 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 289 5.3 t he r eceive s ection of the XRT72L50 (e3 m ode o peration ) .................................................................... 289 figure 127. a simple illustration of the receive section of the XRT72L50 configured to operate in the e3 mode .......................................................................................................................... .......................... 290 5.3.1 the receive e3 liu interface block ...................................................................................... ................ 290 figure 128. a simple illustration of the receive e3 liu interface block ............................................ 291 figure 129. behavior of the rxpos, rxneg and rxlineclk signals during data reception of unipolar data 291 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 292 t able 59: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ..................... 292 figure 130. illustration on how a channel of the receive e3 framer (within the XRT72L50 framer ic) being interface to thexrt73l00 line interface unit, while operating in bipolar mode ................................. 293 figure 131. illustration of ami line code .................................................................................... ....... 294 figure 132. illustration of two examples of hdb3 decoding .............................................................. 294 ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 295 t able 60: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r eg - ister , and the sampling edge of the r x l ine c lk signal ................................................................... 295 figure 133. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the rising edge of rxlineclk ................................................................ 296 figure 134. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the falling edge of rxlineclk ............................................................... 296 5.3.2 the receive e3 framer block ............................................................................................. .................. 296 figure 135. a simple illustration of the receive e3 framer block and the associated paths to the other functional blocks ............................................................................................................. ................... 297 figure 136. the state machine diagram for the receive e3 framer e3 frame acquisition/maintenance al- gorithm ....................................................................................................................... .......................... 298 figure 137. illustration of the e3, itu-t g.751 framing format ........................................................ 298 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 299 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 300 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 300 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 300 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 301 pmon f raming b it /b yte e rror c ount r egister - msb (a ddress = 0 x 52) ................................... 301 pmon f raming b it /b yte e rror c ount r egister - lsb (a ddress = 0 x 53) .................................... 301 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 302 t able 61: t he r elationship between the l ogic s tate of the r x oof and r x lof output pins , and the f raming s tate of the r eceive e3 f ramer block ............................................................................ 302 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 303 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 303 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 303 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 304 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 304 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 304 r x e3 c onfiguration & s tatus r egister - 1 g.751 (a ddress = 0 x 10) ............................................ 305 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 xiii r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 305 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ...................................................... 305 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ...................................................... 306 figure 138. illustration of the local receive e3 framer block, receiving an e3 frame (from the remote terminal) with a correct bip-4 value. ......................................................................................... ........ 306 figure 139. illustration of the local receive e3 framer block, transmitting an e3 frame (to the remote terminal) with the a bit set to 0 ......................................................................................... ............. 307 figure 140. illustration of the local receive e3 framer block, receiving an e3 frame (from the remote terminal) with an incorrect bip-4 value. ...................................................................................... ....... 308 figure 141. illustration of the local receive e3 framer block, transmitting an e3 frame (to the remote terminal) with the a bit-field set to 1 ................................................................................... ........... 308 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 309 pmon p arity e rror c ount r egister - msb (a ddress = 0 x 54) ..................................................... 309 pmon p arity e rror c ount r egister - lsb (a ddress = 0 x 55) ...................................................... 309 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 309 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) ................................................................. 310 5.3.3 the receive hdlc controller block ....................................................................................... .............. 310 figure 142. lapd message frame format ....................................................................................... 311 r x e3 lapd c ontrol r egister (a ddress = 0 x 18 ............................................................................ 311 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 312 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 312 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 313 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 313 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 313 t able 62: t he r elationship between the c ontents of r x lapdt ype [1:0] bit - fields and the pmdl m es - sage t ype /s ize .............................................................................................................................. ..... 314 r x e3 lapd c ontrol r egister (a ddress = 0 x 18 ............................................................................ 314 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 314 figure 143. flow chart depicting the functionality of the lapd receiver ........................................ 315 5.3.4 the receive overhead data output interface .............................................................................. ........ 315 figure 144. a simple illustration of the receive overhead output interface block ........................... 316 figure 145. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 1). ............................................................................................... ............. 317 t able 63: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (f or m ethod 1) ..................................................................................................... 318 t able 64: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x o- hf rame was last sampled "h igh ) to the e3 o verhead b it , that is being output via the r x oh output pin .............................................................................................................................. ......................... 318 figure 146. illustration of the signals that are output via the receive overhead output interface (for method 1). ........................................................................................................................... ............................. 319 t able 65: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (m ethod 2) ............................................................................................................. 320 figure 147. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 2). ............................................................................................... ............. 321 t able 66: t he r elationship between the n umber of r x ohe nable output pulses ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin .. 322 figure 148. illustration of the signals that are output via the receive overhead data output interface block (for method 2). ............................................................................................................... ...................... 322 5.3.5 the receive payload data output interface ............................................................................... .......... 323 figure 149. a simple illustration of the receive payload data output interface block ...................... 323 t able 67: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i n - terface block .............................................................................................................................. ...... 324 figure 150. illustration of the terminal equipment being interfaced to the receive payload data input in- terface block of the XRT72L50 framer ic (serial mode operation) ................................................... 325 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary xiv figure 151. an illustration of the behavior of the signals between the receive payload data output inter- face block of the XRT72L50 and the terminal equipment .................................................................. 326 figure 152. illustration of the XRT72L50 ds3/e3 framer ic being interfaced to the receive section of the terminal equipment (nibble-parallel mode operation) ....................................................................... 327 figure 153. illustration of the signals that are output via the receive payload data output interface block (for nibble-parallel mode operation). ......................................................................................... ......... 328 5.3.6 receive section interrupt processing .................................................................................... ............... 328 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ...................................................................... 329 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 329 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 330 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 330 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 331 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 331 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ......................................................... 331 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 332 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 332 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 333 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 333 r x e3 i nterrupt enable r egister - 1 (a ddress = 0 x 12) ................................................................ 334 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 334 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) .................................................................. 335 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) .................................................................. 335 r x e3 c onfiguration & s tatus r egister - 2 (a ddress = 0 x 11) ....................................................... 335 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) .................................................................. 336 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) .................................................................. 336 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) .................................................................. 337 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) .................................................................. 337 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ............................................................................ 337 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ............................................................................ 338 6.0 e3/itu-t g.832 operation of the XRT72L50 .................................................................................. ... 339 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 339 6.1 d escription of the e3, itu-t g.832 f rames and a ssociated o verhead b ytes ........................................ 339 figure 154. illustration of the e3, itu-t g.832 framing format. ....................................................... 339 6.1.1 definition of the overhead bytes ........................................................................................ ................... 339 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 340 t able 68: d efinition of the t rail t race b uffer b ytes , within t he e3, itu-t g.832 f raming f ormat 340 t he m aintenance and a daptation ( ma ) byte format ........................................................................ 341 t able 69: a l isting of the v arious p ayload t ype v alues and their corresponding m eaning ... 342 6.2 t he t ransmit s ection of the XRT72L50 (e3 m ode o peration ) .................................................................. 342 figure 155. a simple illustration of the transmit section, within the XRT72L50, when it has been configured to operate in the e3 mode ..................................................................................................... .............. 343 6.2.1 the transmit payload data input interface block ......................................................................... ........ 343 figure 156. a simple illustration of the transmit payload data input interface block ....................... 344 t able 70: l isting and d escription of the pins associated with the t ransmit p ayload d ata i nput i n - terface .............................................................................................................................. ................. 345 figure 157. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 1 (serial/loop-timed) operation ........................................ 347 figure 158. behavior of the terminal interface signals between the transmit payload data input interface block of the XRT72L50 and the terminal equipment (for mode 1 operation) .................................... 348 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 348 figure 159. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 2 (serial/local-timed/frame-slave) operation .................. 349 figure 160. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (mode 2 operation) ............................................................................................................ ................. 350 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 xv f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 350 figure 161. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 3 (serial/local-timed/frame-master) operation ................ 351 figure 162. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (e3 mode 3 operation) ......................................................................................................... ............... 352 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 352 figure 163. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 4 (nibble-parallel/loop-timed) operation .......................... 353 figure 164. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (mode 4 operation) ............................................................................................................ ................. 354 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 355 figure 165. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 5 (nibble-parallel/local-time/frame-slave) operation ..... 356 figure 166. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (e3 mode 5 operation) ......................................................................................................... ............... 357 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 357 figure 167. illustration of the terminal equipment being interfaced to the transmit payload data input in- terface block of the XRT72L50 for mode 6 operation ......................................................................... 35 8 figure 168. behavior of the terminal interface signals between the XRT72L50 and the terminal equipment (e3 mode 6 operation) ......................................................................................................... ............... 359 f ramer o perating m ode r egister (a ddress = 0 x 00) ..................................................................... 359 6.2.2 the transmit overhead data input interface .............................................................................. .......... 359 figure 169. simple illustration of the transmit overhead data input interface block ........................ 360 t able 71: a l isting of the o verhead bits within the e3 frame , and their potential sources , within the XRT72L50 ic .................................................................................................................. .............. 361 t able 72: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals ..................... 363 figure 170. illustration of the terminal equipment being interfaced to the transmit overhead data input interface (method 1) .......................................................................................................... .................. 364 t able 73: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since "t x o- hf rame " was last sampled "h igh ") to the e3 o verhead b it , that is being processed ................ 365 figure 171. illustration of the signal that must occur between the terminal equipment and the XRT72L50, in order to configure the XRT72L50 to transmit a yellow alarm to the remote terminal equipment ... 367 t able 74: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals ..................... 368 figure 172. illustration of the terminal equipment being interfaced to the transmit overhead data input interface (method 2) .......................................................................................................... .................. 369 t able 75: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the e3 o verhead b it , that is being processed by the XRT72L50 370 figure 173. behavior of transmit overhead data input interface signals between the XRT72L50 and the terminal equipment (for method 2) ............................................................................................. ....... 372 6.2.3 the transmit e3 hdlc controller ......................................................................................... ............... 372 figure 174. lapd message frame format ....................................................................................... 373 t able 76: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i nfor - mation p ayload .............................................................................................................................. .... 373 t ransmit e3 lapd c onfiguration r egister (a ddress = 0 x 33) ..................................................... 374 t able 77: r elationship between t x lapd m sg l ength and the lapd m essage s ize .................. 374 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 375 t x e3 lapd c onfiguration r egister (a ddress = 0 x 33) ................................................................. 375 t ransmit e3 lapd c onfiguration r egister (a ddress = 0 x 33) ..................................................... 375 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 376 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 377 figure 175. flow chart depicting how to use the lapd transmitter (lapd transmitter is configured to re- transmit the lapd message frame repeatedly at one-second intervals) ........................................... 378 figure 176. flow chart depicting how to use the lapd transmitter (lapd transmitter is configured to transmit a lapd message frame only once). ..................................................................................... . 379 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ..................................................................... 380 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary xvi 6.2.4 the transmit e3 framer block ............................................................................................ .................. 380 figure 177. a simple illustration of the transmit e3 framer block and the associated paths to other func- tional blocks ................................................................................................................. ....................... 381 t x e3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 382 t able 78: t he r elationship between the contents of b it 2 (t x ais e nable ) within the t x e3 c onfig - uration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction .................................. 382 t able 79: t he r elationship between the contents of b it 1 (t x los) within the t x e3 c onfiguration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction ................................................ 382 6.2.5 the transmit e3 line interface block .................................................................................... ............... 383 figure 178. approach to interfacing the XRT72L50 framer ic device to the xrt73l00 ds3/e3/sts-1 liu 384 figure 179. a simple illustration of the transmit e3 liu interface block ........................................... 385 figure 180. the behavior of txpos and txneg signals during data transmission while the transmit ds3 liu interface is operating in the unipolar mode ............................................................................... ... 385 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 386 t able 80: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c on - trol r egister and the t ransmit e3 f ramer l ine i nterface o utput m ode ................................... 386 figure 181. illustration of ami line code .................................................................................... ....... 387 figure 182. illustration of two examples of hdb3 encoding .............................................................. 387 i/o c ontrol r egister (a ddress = 0 x 01) .......................................................................................... 388 t able 81: t he r elationship between b it 4 (ami/hdb3*) within the i/o c ontrol r egister and the b i - polar l ine c ode that is output by the t ransmit e3 liu i nterface b lock .................................... 388 ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 388 t able 82: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ..................... 388 figure 183. waveform/timing relationship between txlineclk, txpos and txneg - txpos and txneg are configured to be updated on the rising edge of txlineclk ............................................................ 389 figure 184. waveform/timing relationship between txlineclk, txpos and txneg - txpos and txneg are configured to be updated on the falling edge of txlineclk ........................................................... 389 6.2.6 transmit section interrupt processing ................................................................................... ............... 389 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ...................................................................... 390 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 390 t x e3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 391 6.3 t he r eceive s ection of the XRT72L50 (e3 m ode o peration ) .................................................................... 391 figure 185. a simple illustration of the receive section of the XRT72L50, when it has been configured to operate in the e3 mode ........................................................................................................ ............... 391 6.3.1 the receive e3 liu interface block ...................................................................................... ................ 391 figure 186. a simple illustration of the receive e3 liu interface block ............................................ 392 figure 187. behavior of the rxpos, rxneg and rxlineclk signals during data reception of unipolar data 393 ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 393 t able 83: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ..................... 393 figure 188. illustration on how the XRT72L50 receive e3 framer is interfaced to the xrt73l00 line in- terface unit while operating in the bipolar mode (one channel shown) ............................................... 394 figure 189. illustration of ami line code .................................................................................... ....... 395 figure 190. illustration of two examples of hdb3 decoding .............................................................. 395 ii/o c ontrol r egister (a ddress = 0 x 01) ......................................................................................... 396 t able 84: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r eg - ister , and the sampling edge of the r x l ine c lk signal ................................................................... 396 figure 191. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the rising edge of rxlineclk ................................................................ 397 figure 192. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the falling edge of rxlineclk ............................................................... 397 6.3.2 the receive e3 framer block ............................................................................................. .................. 397 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 xvii figure 193. a simple illustration of the receive e3 framer block and the associated paths to the other functional blocks ............................................................................................................. ................... 398 figure 194. the state machine diagram for the receive e3 framer e3 frame acquisition/maintenance al- gorithm ....................................................................................................................... ......................... 399 figure 195. illustration of the e3, itu-t g.832 framing format ........................................................ 400 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) ................................................................. 401 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 401 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) ................................................................. 402 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) ................................................................. 402 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 402 pmon f raming b it /b yte e rror c ount r egister - msb (a ddress = 0 x 52) ................................... 403 pmon f raming b it /b yte e rror c ount r egister - lsb (a ddress = 0 x 53) .................................... 403 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 403 t able 85: t he r elationship between the l ogic s tate of the r x oof and r x lof output pins , and the f raming s tate of the r eceive e3 f ramer block ............................................................................ 404 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 404 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) ................................................................. 404 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 405 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) ................................................................. 405 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 405 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 406 t he m aintenance and a daptation ( ma ) byte format ....................................................................... 406 r x e3 c onfiguration & s tatus r egister 1 - (e3, itu-t g.832) (a ddress = 0 x 10) ........................ 406 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) ................................................................. 407 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 407 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ........................................................ 407 figure 196. illustration of the local receive e3 framer block, receiving an e3 frame (from the remote terminal) with a correct em byte. ............................................................................................. .......... 408 figure 197. illustration of the local receive e3 framer block, transmitting an e3 frame (to the remote terminal) with the febe bit (within the ma byte-field) set to 0 ......................................................... 408 figure 198. illustration of the local receive e3 framer block, receiving an e3 frame (from the remote terminal) with an incorrect em byte. .......................................................................................... ........ 409 figure 199. illustration of the local receive e3 framer block, transmitting an e3 frame (to the remote terminal) with the febe bit (within the ma byte-field) set to 1 ......................................................... 410 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 410 pmon p arity e rror c ount r egister - msb (a ddress = 0 x 54) ..................................................... 410 pmon p arity e rror c ount r egister - lsb (a ddress = 0 x 55) ...................................................... 411 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 411 pmon febe e vent c ount r egister - msb (a ddress = 0 x 56) ....................................................... 411 pmon febe e vent c ount r egister - lsb (a ddress = 0 x 57) ........................................................ 411 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 412 6.3.3 the receive hdlc controller block ....................................................................................... .............. 412 figure 200. lapd message frame format ....................................................................................... 413 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................... 414 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................... 414 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 414 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 415 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 415 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 416 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 416 t able 86: t he r elationship between the c ontents of r x lapdt ype [1:0] bit - fields and the pmdl m es - sage t ype /s ize .............................................................................................................................. ..... 416 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................... 417 r x e3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 417 figure 201. flow chart depicting the functionality of the lapd receiver ........................................ 418 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary xviii figure 202. flow chart depicting the functionality of the lapd receiver (continued) ..................... 419 6.3.4 the receive overhead data output interface .............................................................................. ........ 419 figure 203. a simple illustration of the receive overhead output interface block ............................ 419 figure 204. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 1). ............................................................................................... .............. 420 t able 87: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock .............................................................................................................................. ... 421 t able 88: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x o- hf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin .............................................................................................................................. .......................... 421 figure 205. illustration of the signals that are output via the receive overhead output interface (for method 1). ........................................................................................................................... ............................. 423 t able 89: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (m ethod 2) ............................................................................................................. 424 figure 206. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 2). ............................................................................................... .............. 425 t able 90: t he r elationship between the n umber of r x ohe nable output pulses ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin ... 425 figure 207. illustration of the signals that are output via the receive overhead data output interface block (for method 2). ............................................................................................................... ...................... 428 6.3.5 the receive payload data output interface ............................................................................... .......... 428 figure 208. a simple illustration of the receive payload data output interface block ...................... 429 t able 91: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i n - terface block .............................................................................................................................. ...... 430 figure 209. illustration of the receive payload data output interface block (of the XRT72L50 ds3/e3 framer ic) being interfaced to the receive terminal equipment (serial mode operation) ................ 431 figure 210. an illustration of the behavior of the signals between the receive payload data output inter- face block of the XRT72L50 and the terminal equipment .................................................................. 432 figure 211. illustration of the XRT72L50 ds3/e3 framer ic being interfaced to the receive section of the terminal equipment (nibble-mode operation) .................................................................................... 433 figure 212. illustration of the signals that are output via the receive overhead data output interface block (for method 2). ............................................................................................................... ...................... 434 6.3.6 receive section interrupt processing .................................................................................... ............... 434 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ...................................................................... 435 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 435 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 436 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ......................................................... 436 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 437 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 437 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ......................................................... 437 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 438 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ......................................................... 438 r x e3 i nterrupt enable r egister - 1 (a ddress = 0 x 12) ................................................................ 439 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 439 r x e3 i nterrupt e nable r egister - 1 (a ddress = 0 x 12) .................................................................. 439 r x e3 i nterrupt s tatus r egister - 1 (a ddress = 0 x 14) .................................................................. 440 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ......................................................... 440 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) .................................................................. 440 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) .................................................................. 441 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) .................................................................. 441 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) .................................................................. 442 r x e3 c onfiguration & s tatus r egister 2 (a ddress = 0 x 11) ......................................................... 442 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) .................................................................. 442 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) .................................................................. 443 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 xix r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) ................................................................. 443 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 443 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) ................................................................. 444 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 444 r x e3 c onfiguration & s tatus r egister 1 (a ddress = 0 x 10) ........................................................ 445 r x e3 i nterrupt e nable r egister - 2 (a ddress = 0 x 13) ................................................................. 445 r x e3 i nterrupt s tatus r egister - 2 (a ddress = 0 x 15) ................................................................. 445 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................... 446 r x e3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................... 446 7.0 diagnostic operation of the XRT72L50 framer ic ............................................................................ .. 447 figure 213. illustration of the framer local loop-back path, within the XRT72L50 ds3/e3 framer ic 447 8.0 high speed hdlc controller mode of operation ........................................................................... 44 9 8.1 c onfiguring the c hannel to operate in the h igh s peed hdlc c ontroller m ode ................................. 449 t able 92: a ddress l ocations of each of the hdlc control r egisters within the XRT72L50 d e - vice . ............................................................................................................................. ....................... 449 hdlc c ontrol r egister (a ddress = 0 x 82) ..................................................................................... 449 8.2 o perating the h igh s peed hdlc c ontroller ............................................................................................ 449 8.2.1 operating the transmit hdlc controller block ............................................................................ ........ 450 t able 93: d escription of e ach of the t ransmit hdlc c ontroller p ins .................................... 451 figure 214. a simple illustration of an outbound hdlc frame, as assembled by the transmit hdlc con- troller, when crc-32 is selected. ............................................................................................. ........... 452 figure 215. a simple illustration of an outbound hdlc frame, as assembled by the transmit hdlc con- troller, when crc-16 is selected. ............................................................................................. ........... 453 8.2.2 operating the receive hdlc controller block ............................................................................. ........ 453 t able 94: d escription of e ach of the r eceive hdlc c ontroller p ins ...................................... 454 ordering information ........................................................................................ 455 .............................................................................................................................. ..................................... 455 package dimensions ............................................................................................ 455 r evision h istory .............................................................................................................................. .. 456 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 3 pin descriptions pin description p in #p in n ame t ype d escription 1 tdo o test data out: boundary scan test data output. 2 tdi i test data in: boundary scan test data input. 3 vdd **** power supply 3.3v + 5% 4 trst i jtag reset pin: resets boundary scan logic. 5 gnd **** ground 6 rdy_dtck o ready or dtack: this active-low output pin will function as the ready output, when the micro- processor interface is running in the "intel" mode; and will function as the dtack output, when the microprocessor interface is running in the "motorola" mode. "intel" mode - ready output: when the framer negates this output pin (e.g., toggles it "low"), it indicates (to the p) that the current read or write cycle is to be extended until this sig- nal is asserted (e.g., toggled "high"). "motorola" mode - dtack (data transfer acknowledge) output: the framer device will assert this pin in order to inform the local microproces- sor that the present read or write cycle is nearly complete. if the framer device requires that the current read or write cycle be extended, then the framer will delay its assertion of this signal. the 68000 family of ps requires this signal from its peripheral devices, in order to quickly and properly com- plete a read or write cycle. 7 wr _rw i write data strobe (intel mode): if the microprocessor interface is operating in the intel mode, then this active- low input pin functions as the wr (write strobe) input signal from the p. once this active-low signal is asserted, then the framer will latch the contents of the p data bus, into the addressed register (or ram location) within the framer ic. in the intel mode, data gets latched on the rising edge of wr r/w input pin (motorola mode): when the microprocessor interface section is operating in the motorola mode, then this pin is functionally equivalent to the r/w pin. in the motorola mode, a read operation occurs if this pin is at a logic "1". similarly, a write operation occurs if this pin is at a logic "0". 8 cs i chip select input: this active-low input signal selects the microprocessor interface section of the framer device and enables read/write operations between the local microprocessor and the framer on-chip registers and ram locations. 9 ale_as i address latch enable/address strobe: this input is used to latch the address (present at the microprocessor inter- face address bus, a(8:0)) into the framer microprocessor interface circuitry and to indicate the start of a read/write cycle. this input is active-high in the intel mode (moto = "low") and active-low in the motorola mode (moto = "high"). ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 4 10 rd _ds i read data strobe (intel mode): if the microprocessor interface is operating in the intel mode, then this input will function as the rd (read strobe) input signal from the local p. once this active-low signal is asserted, then the framer will place the contents of the addressed registers (within the framer) on the microprocessor data bus (d(7:0)). when this signal is negated, the data bus will be tri-stated. data strobe (motorola mode): if the microprocessor interface is operating in the motorola mode, then this pin will function as the active-low data strobe signal. 11 tck i test clock: boundary scan clock input. 12 tms i test mode select: boundary scan mode select input. 13 int o interrupt request output: this open-drain, active-low output signal will be asserted when the framer device is requesting interrupt service from the local microprocessor. this out- put pin should typically be connected to the "interrupt request" input of the local microprocessor. 14 gnd **** ground 15 a(0) i address bus input (microprocessor interface) - lsb (least significant bit): (please see description for a(8) pin 23) 16 a(1) i address bus input (microprocessor interface) - bit 7 see description of pin 23 17 a(2) i address bus input (microprocessor interface) - bit 7 see description of pin 23 18 a(3) i address bus input (microprocessor interface) - bit 7 see description of pin 23 19 a(4) i address bus input (microprocessor interface) - bit 7 see description of pin 23 20 a(5) i address bus input (microprocessor interface) - bit 7 see description of pin 23 21 a(6) i address bus input (microprocessor interface) - bit 7 see description of pin 23 22 a(7) i address bus input (microprocessor interface) - bit 7 see description of pin 23 23 a(8) i address bus input (microprocessor interface) - msb (most significant bit): this input pin, along with inputs a0 - a7 are used to select the on-chip framer register and ram space for read/write operations with the "local" micro- processor. 24 vdd **** power supply 3.3v + 5% pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 5 25 nibbleintf i nibble interface select input pin: this input pin allows the user to configure the transmit payload data input interface and the receive payload data output interface to operate in either the "serial-mode" or the "nibble/parallel-mode". setting this input pin "high" configures the transmit and receive terminal interfaces to operate in the "nibble/parallel-mode". in this mode, the transmit payload data input interface block will accept the outbound payload data (from the terminal equipment) in a nibble-parallel manner via the txnib[3:0] input pins. further, the receive payload data output interface block will output the inbound payload data (to the terminal equipment) in a nibble-parallel manner via the rxnib[3:0] output pin. setting this input pin "low" configures the transmit and receive terminal interfaces to operate in the "serial" mode. in this mode, the transmit payload data input interface block will accept the outbound payload data (from the terminal equipment) in a serial manner via the txser input pin. further, the receive payload data output interface block will output the inbound payload data (to the terminal equipment) in a serial manner via the rxser output pin. 26 gnd **** ground 27 moto i motorola/intel processor interface select mode: this input pin allows the user to configure the microprocessor interface to interface with either a "motorola-type" or "intel-type" microprocessor/micro- controller. tying this input pin to vcc, configures the microprocessor interface to operate in the motorola mode (e.g., the framer device can be readily inter- faced to a "motorola type" local microprocessor). tying this input pin to gnd configures the microprocessor interface to operate in the intel mode (e.g., the framer device can be readily interfaced to a intel type" local microproces- sor). 28 reset i reset input: when this "active-low" signal is asserted, the framer device will be asynchro- nously reset. additionally, all outputs will be "tri-stated", and all on-chip regis- ters will be reset to their default values. 29 testmode *** factory test pin: the user should tie this pin to ground. 30 vdd **** power supply 3.3v + 5% 31 gnd **** ground 32 d(0) i/o bit 6 of bi-directional data bus (microprocessor interface section): see description of pin 39 d(7) 33 d(1) i/o bit 6 of bi-directional data bus (microprocessor interface section): see description of pin 39 d(7) 34 d(2) i/o bit 6 of bi-directional data bus (microprocessor interface section): see description of pin 39 d(7) 35 d(3) i/o bit 6 of bi-directional data bus (microprocessor interface section): see description of pin 39 d(7) pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 6 36 d(4) i/o bit 6 of bi-directional data bus (microprocessor interface section): see description of pin 39 d(7) 37 d(5) i/o bit 6 of bi-directional data bus (microprocessor interface section): see description of pin 39 d(7) 38 d(6) i/o bit 6 of bi-directional data bus (microprocessor interface section): see description of pin 39 d(7) 39 d(7) i/o msb of bi-directional data bus (microprocessor interface section): this pin, along with pins d0 - d6, function as the microprocessor interface bi- directional data bus, and is intended to be interfaced to the "local" micropro- cessor. 40 vdd **** power supply 3.3v + 5% 41 txframeref i transmit framer reference input: this input pin functions as the "transmit frame generation" reference signal, if the XRT72L50 has been configured to operate in the "local-time/frame slave" mode. if the XRT72L50 has been configured to operate in the "local- time/frame-slave" mode, then the user's terminal equipment is expected to apply a pulse (to this input pin) once every 106.4 microseconds (for ds3 applications); once every 125 microseconds (for e3, itu-t g.832 applica- tions) or once every 44.7 microseconds (for e3, itu-t g.751 applications). in the "local-time/frame-slave" mode, the transmit section of the XRT72L50 framer ic will initiate its generation of a new "outbound" ds3 or e3 frame, upon the rising edge of this signal. n ote : the user can configure the XRT72L50 framer ic to operate in the "local time/frame slave" mode by writing "xxxx xx01" into the "framer oper- ating mode" register (address = 0x00). 42 gnd **** ground 43 txinclk i transmit framer reference clock input: this input pin functions as the "timing reference" for the transmit section of the XRT72L50 framer ic; if the device has been configured to operate in the "local-time" mode. further, if the XRT72L50 framer ic has been configured to operate in the "local-time" mode, the "transmit payload data input inter- face will sample the data at the txser input pin, upon the rising edge of "txin- clk". for e3 applications, the user should apply a 34.368mhz clock signal. for ds3 applications, the user should apply a 44.736mhz clock signal. the user can configure the XRT72L50 framer ic to operate in the "local- time" mode by writing "xxxx xx01" or "xxxx xx1x" into the "framer operating mode" register (address = 0x00) 44 txaisen i transmit ais command input: setting this input pin "high" configures the transmit section to generate and transmit an ais pattern. setting this input pin "low" configures the transmit section to generate e3 or ds3 traffic in a normal manner. pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 7 45 txser/ sndmsg i transmit serial payload data input pin: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over an e3 or ds3 transport medium. the framer ic will take data, applied to this pin, and insert it into an outbound "e3 or ds3" frame. if the XRT72L50 framer ic has been configured to operate in the "local time" mode, then it will sample the data (on this pin) upon the rising edge of "txinclk". if the XRT72L50 framer ic has been configured to operate in the "loop-time" mode, then it will sample the data (on this pin) upon the rising edge of "rxoutclk". n ote : this input pin is active only if the serial mode has been selected. send message: this input is to remain high during the entire duration of the hdlc packet (including fcs bytes) to be transmitted, when the hdlc controller is turned on. 46 txnib0/ txhdlcdat0 i transmit nibble-parallel payload data input -0: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over an e3 or ds3 transport medium. the framer ic will take data, applied to this pin (along with txnib1, txnib2, and txnib3), and insert it into an outbound "e3 or ds3" frame. the XRT72L50 will sample the data that is at these input pins, upon the rising edge of the "txnib- clk" signal. n ote : this input pin is active only if the nibble-parallel mode has been selected. transmit hdlc data input - 0: this pin accepts bit 0 txhdlc data when the hdlc controller is turned on. 47 txnib1/ txhdlcdat1 i transmit nibble-parallel payload data input -1: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over an e3 or ds3 transport medium. the framer ic will take data, applied to this pin, and insert it into an outbound "e3 or ds3" frame. the XRT72L50 will sample the data that is at these input pins, upon the rising edge of the "txnibclk" signal. n ote : this input pin is active only if the nibble-parallel mode has been selected. transmit hdlc data input - 1: this pin accepts bit 1 txhdlc data when the hdlc controller is turned on. 48 txnib2/ txhdlcdat2 i transmit nibble-parallel payload data input -2: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over an e3 or ds3 transport medium. the framer ic will take data, applied to this pin, and insert it into an outbound "e3 or ds3" frame. the XRT72L50 will sample the data that is at these input pins, upon the rising edge of the "txnibclk" signal. n ote : this input pin is active only if the nibble-parallel mode has been selected. transmit hdlc data input - 2: this pin accepts bit 2 txhdlc data when the hdlc controller is turned on. pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 8 49 txnib3/ txhdlcdat3 i transmit nibble-parallel payload data input -3: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over an e3 or ds3 transport medium. the framer ic will take data, applied to this pin (along with txnib1, txnib2, and txnib3), and insert it into an outbound "e3 or ds3" frame. the XRT72L50 will sample the data that is at these input pins, upon the rising edge of the "txnib- clk" signal. n ote : this input pin is active only if the nibble-parallel mode has been selected. transmit hdlc data input - 3: this pin accepts bit 3 txhdlc data when the hdlc controller is turned on. 50 gnd **** ground 51 vdd **** power supply 3.3v + 5% 52 txohclk o transmit overhead clock: this output signal serves two purposes: 1. the transmit overhead data input interface block will provide a rising clock edge on this signal, one bit-period prior to the start to the instant that the transmit overhead data input interface block is processing an overhead bit. 2. the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of this clock signal (provided that the txohins input pin is high). n ote : the transmit overhead data input interface block will supply a clock edge for all overhead bits within the ds3 or e3 frame (via the txohclk out- put signal). this includes those overhead bits that the transmit overhead data input interface will not accept from the terminal equipment. 53 txohins/ txhdlcdat4 i transmit overhead data insert input: asserting this input signal (e.g., setting it "high") enables the transmit over- head data input interface to accept "overhead" data from the terminal equip- ment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the "txoh" input pin, on the falling edge of the "txohclk" output signal. conversely, setting this pin "low" configures the "transmit overhead data input interface" to not sample (e.g., ignore) the data at the "txoh" input pin, on the falling edge of the "txohclk" output signal. n ote : if the terminal equipment attempts to insert an overhead bit that can- not be accepted by the "transmit overhead data input interface" (e.g., if the terminal equipment asserts the "txohins" signal, at a time when one of these "non-insertable" overhead bits are being processed); that particular insertion effort will be ignored. transmit hdlc data input - 4: this pin accepts bit 4 txhdlc data when the hdlc controller is turned on. pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 9 54 txoh/ txhdlcdat5 i transmit overhead input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the "overhead" bit position within the very next "outbound" ds3 or e3 frame. if the "txohins" pin is pulled "high", the trans- mit overhead data input interface will sample the data at this input pin (txoh), on the falling edge of the "txohclk" output pin. conversely, if the "txohins" pin is pulled "low", then the transmit overhead data input inter- face will not sample the data at this input pin (txoh). consequently, this data will be ignored. transmit hdlc data input - 5: this pin accepts bit 5 txhdlc data when the hdlc controller is turned on. 55 txohind/ txhdlcdat6 o i transmit overhead data indicator: this output pin will pulse "high" one-bit period prior to the time that the trans- mit section of the XRT72L50 will be processing an overhead bit. the pur- pose of this output pin is to warn the terminal equipment that, during the very next bit-period, the XRT72L50 is going to be processing an "overhead" bit and will be ignoring any data that is applied to the "txser" input pin. n ote : for ds3 applications, this output pin is only active if the XRT72L50 is operating in the "serial" mode. this output pin will be pulled "low" if the device is operating in the "nibble-parallel" mode. transmit hdlc data input - 6: this pin accepts bit 6 txhdlc data when the hdlc controller is turned on. 56 txohenable/ txhdlcdat7 o i transmit overhead input enable: the XRT72L50 will assert this signal, for one txinclk period, just prior to the instant that the transmit overhead data input interface will be sampling and processing an overhead bit. if the terminal equipment intends to insert its own value for an overhead bit, into the outbound ds3 or e3 frame, it is expected to sample the state of this signal, upon the falling edge of txinclk. upon sampling the txohenable high, the terminal equipment should (1) place the desired value of the over- head bit, onto the txoh input pin and (2) assert the txohins input pin. the transmit overhead data input interface block will sample and latch the data on the txoh signal, upon the rising edge of the very next txinclk input signal. transmit hdlc data input - 7: this pin accepts bit 7 txhdlc data when the hdlc controller is turned on. 57 txohframe/ txhdlcclk o transmit overhead framing pulse: this output pin pulses "high" when the transmit overhead data input inter- face block is expecting the first overhead bit, within a ds3 or e3 frame to be applied to the txoh input pin. this pin is "high" for one clock period of txohclk. transmit hdlc output clock: when the hdlc controller is on, txhdlcdat is updated by the 72l53 by this clock signal. pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 10 58 txnibframe/ valfcs o transmit frame boundary indicator - nibble/parallel interface: this output pin pulses "high" when the last nibble of a given ds3 or e3 frame is expected at the txnib[3:0] input pins. the purpose of this output pin is to alert the terminal equipment that it needs to begin transmission of a new ds3 or e3 frame to the XRT72L50. valid frame check sequence: when the hdlc is on, this pin will go high at the end of a valid frame check sequence. 59 txnibclk/ sndfcs o i transmit nibble clock signal: if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the XRT72L50 will derive this clock signal from either the txinclk or the rxlineclk signal (depending upon which signal is selected as the timing reference). the user is advised to configure the terminal equipment to output the outbound payload data (to the XRT72L50 framer ic) onto the tx- nib[3:0] input pins, upon the rising edge of this clock signal. n otes : 1. for ds3 applications, the XRT72L50 framer ic will output 1176 clock edges (to the terminal equipment) for each outbound ds3 frame. 2. for e3, itu-t g.832 applications, the XRT72L50 framer ic will out- put 1074 clock edges (to the terminal equipment) for each out- bound e3 frame. 3. for e3, itu-t g.751 applications, the XRT72L50 framer ic will out- put 384 clock edges (fo the terminal equipment) for each outbound e3 frame. send frame check sequence: when the hdlc controller is turned on, this pin is driven high during the time when fcs bytes are being sent after a valid hdlc message. 60 gnd **** ground 61 txframe o transmit end of ds3 or e3 frame indicator: the transmit section of the xrt72l56 device will pulse this output pin "high" (for one bit-period), when the transmit payload data input interface is pro- cessing the last bit of a given ds3 or e3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin transmission of a new ds3 or e3 frame to the xrt72l56 device (e.g., to permit the xrt72l56 device to maintain transmit ds3/e3 framing align- ment control over the terminal equipment). 62 vdd **** power supply 3.3v + 5% 63 txlineclk o transmit line interface clock: this clock signal is output to the line interface framer, along with the txpos and txneg signals. the purpose of this output clock signal is to provide the liu with timing information that it can use to generate the ami pulses and deliver them over the transmission medium to the far-end receiver. the user can configure the source of this clock to be either the rxlineclk (from the receiver portion of the framer) or the txinclk input. the nominal frequency of this clock signal is 34.368 mhz. pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 11 64 txneg o transmit negative polarity pulse: the exact role of this output pin depends upon whether the framer is operat- ing in the unipolar or bipolar mode. unipolar mode: this output signal pulses "high" for one bit period, at the end of each "out- bound" ds3 or e3 frame. this output signal is at a logic "low" for all of the remaining bit-periods of the "outbound" ds3 or e3 frames bipolar mode: this output pin functions as one of the two dual-rail output signals that com- mands the sequence of pulses to be driven on the line. txpos is the other output pin. this input is typically connected to the tndata input of the exter- nal ds3/e3 line interface unit ic. when this output is asserted, it will com- mand the liu to generate a negative polarity pulse on the line. 65 txpos o transmit positive polarity pulse: the exact role of this output pin depends upon whether the framer is operat- ing in the unipolar or bipolar mode. unipolar mode: this output pin functions as the "single-rail" output signal for the "outbound" ds3 or e3 data stream. the signal, at this output pin, will be updated on the "user-selected" edge of the txlineclk signal. bipolar mode: this output pin functions as one of the two dual rail output signals that com- mands the sequence of pulses to be driven on the line. txneg is the other output pin. this input is typically connected to the tpdata input of the exter- nal ds3 or e3 line interface unit ic. when this output is asserted, it will com- mand the liu to generate a positive polarity pulse on the line 66 encodis o encoder (hdb3) disable output pin (intended to be connected to the xrt7300 ds3/e3 line interface unit ic): this output pin is intended to be connected to the encodis input pin of the xrt7300 ds3/e3 line interface unit ic. the user can control the state of this output pin by writing a "0" or "1" to bit 3 (encodis) within the line interface driver register (address = 0x80). if the user commands this signal to toggle "high" then it will disable the b3zs/hdb3 encoder circuitry within the xrt7300 ic. conversely, if the user commands this output signal to toggle "low", then the b3zs/hdb3 encoder circuitry, within the xrt7300 ic will be enabled. writing a "1" to bit 3 of the line interface driver register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". the user is advised to disable the b3zs/hdb3 encoder (within the xrt7300 ic) if the XRT72L50 framer ic has been configured to operate in the b3zs/ hdb3 line code. n ote : if the customer is not using the xrt7300 ds3/e3 line interface unit ic, then he/she can use this output pin for a variety of other purposes. pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 12 67 txlev o transmit line build-out enable/disable select output (to be connected to the xrt7300 ds3/e3 line interface unit ic): this output pin is intended to be connected to the txlev input pin of the xrt7300 ds3/e3 line interface unit ic. the user can control the state of this output pin by writing a "0" or a "1" to bit 2 (txlev) within the line interface driver register (address = 0x80). writing a "1" to bit 2 of the line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". for ds3 application: if the user commands this signal to toggle "high" then the "transmit line build-out" circuit (within the xrt7300 device) will be disabled. in this mode, the xrt7300 device will output unshaped (e.g., square) pulses onto the line (via the ttip and tring output pins). conversely, if the user commands this signal to toggle "low" then the "trans- mit line build-out" circuit (within the xrt7300 device) will be disabled. in this mode, the xrt7300 device will output shaped (e.g., more rounded) pulses onto the line (via the ttip and tring output pins). in order to comply with the "dsx-3 isolated pulse template requirement" (per bellcore gr-499-core), the user is advised to command this output pin to be "high" if the cable length (between the transmit output of the xrt7300 device and the dsx-3 cross-connect system) is greater than 225 feet. con- versely, the user is advised to command this output pin to be "low" if the cable length (between the transmit output of the xrt7300 device and the dsx- 3cross connect system) is less than 225 feet. for e3 applications: this pin can be used as a general purpose output pin. the transmit line build-out circuitry (within the xrt7300 device) is not active for e3 applica- tions. n ote : if the customer is not using the xrt7300 ds3/e3 line interface unit ic, then he/she can use this output pin for a variety of other purposes. 68 ta o s o transmit all ones signal" (taos) command (for the xr-t7300 line interface unit ic): this output pin is intended to be connected to the taos input pin of the xr- t7300 ds3/e3 line interface unit ic. the user can control the state of this output pin by writing a '0' or '1' to bit 4 (taos) of the line interface drive reg- ister (address = 0x80). if the user commands this signal to toggle "high" then it will force the xrt7300 line interface unit ic to transmit an "all ones" pat- tern onto the line. conversely, if the user commands this output signal to tog- gle "low" then the xr-t7300 ds3/e3 line interface unit ic will proceed to transmit data based upon the pattern that it receives via the txpos and txneg output pins. writing a "1" to bit 4 of the line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". if the customer is not using the xr-t7300 ds3/e3 line transceiver ic, then he/she can use this output pin for a variety of other purposes. pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 13 69 lloop o local loopback output pin (to the xrt7300 ds3/e3 line interface unit ic): this output pin is intended to be connected to the lloop input pin of the xrt7300 liu ic. the user can command this signal to toggle "high" and, in turn, force the liu into the "local loopback" mode. (for a detailed description of the xrt7300 ds3/e3 line interface unit ic's operation during local loop- back, please see the xrt7300 ds3/sts-1/e3 line interface unit ic's data sheet). writing a "1" to bit 1 of the "line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause the rloop output to toggle "low". n ote : if the user is not using the xrt7300 ds3/e3 line interface unit ic, then he/she can use this output pin for a variety of other purposes. 70 rloop o remote loopback output pin (to the xrt7300 ds3/e3 line interface unit ic): this output pin is intended to be connected to the rloop input pin of the xrt7300 ds3/e3 line interface unit ic. the user can command this signal to toggle "high" and, in turn, force the xrt7300 ds3/e3 line interface unit ic into the "remote loopback" mode. conversely, the user can command this signal to toggle "low" and allow the xrt7300 device to operate in the normal mode. (for a detailed description of the xr-t7300 ds3/e3 line interface unit ic's operation during remote loopback, please see the xr-t7300 ds3/sts- 1/ e3 line interface unit ic's data sheet). writing a "1" to bit 1 of the "line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause the rloop output to toggle "low". n ote : if the customer is not using the xrt7300 ds3/e3 line interface unit ic, then he/she can use this output pin for a variety of other purposes. 71 req o receive equalization enable/disable select output pin - (to be con- nected to the xrt7300 ds3/e3 line interface unit ic): this output pin is intended to be connected to the req input pin of the xrt7300 ds3/e3 (reqdis or reqen of the xrt73l03 or xrt 73l04) line interface unit ic. the user can control the state of this output pin by writing a '0' or '1' to bit 5 (req ) within the line interface driver register (address = 0x80). if the user commands this signal to toggle "high" then the internal receive equalizer (within the xrt7300 device) will be disabled. conversely, if the user commands this output signal to toggle "low", then the internal receive equalizer (within the xrt7300 device) will be enabled. for information on the criteria that should be used when deciding whether to bypass the equalization circuitry or not, please consult the "xrt7300 ds3/e3 line interface unit" data sheet. writing a "1" to bit 5 of the line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". if the exar xrt7300 ds3/e3 family of line interface unit ics are not used, then this output pin can be used for other purposes. 72 gnd **** ground pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 14 73 rxlineclk i receiver liu (recovered) clock: this input signal serves three purposes: 1. the receive framer uses it to sample and "latch" the signals at the rxpos and rxneg input pins (into the receive framer circuitry). 2. this input signal functions as the timing reference for the receive framer block. 3. the transmit framer block can be configured to use this input signal as its timing reference. this signal is the recovered clock from the external ds3/e3 liu (line inter- face unit) ic, which is derived from the incoming ds3/e3 data. 74 rxneg i receive negative data input: the exact role of this input pin depends upon whether the framer is operating in the unipolar or bipolar mode. unipolar mode: this input pin is inactive, and should be pulled ("low" or "high") when the framer is operating in the unipolar mode. bipolar mode: this input pin functions as one of the dual rail inputs for the incoming ami/ hdb3 encoded ds3 or e3 data that has been received from an external line interface unit (liu) ic. rxpos functions as the other dual rail input for the framer. when this input pin is asserted, it means that the liu has received a "negative polarity" pulse from the line. 75 rxpos i receive positive data input: the exact role of this input pin depends upon whether the framer is operating in the unipolar or bipolar mode. unipolar mode: this input pin functions as the "single-rail" input for the "incoming" e3 data stream. the signal at this input pin will be sampled and latched (into the receive ds3/e3 framer) on the "user-selected" edge of the rxlineclk signal. bipolar mode: this input functions as one of the dual rail inputs for the incoming ami/hdb3 encoded ds3 or e3 data that has been received from an external line inter- face unit (liu) ic. rxneg functions as the other dual rail input for the framer. when this input pin is asserted, it means that the liu has received a "positive polarity" pulse from the line. pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 15 76 rlol i receive loss of lock indicator - from the xrt7300 ds3/e3 line inter- face unit ic: this input pin is intended to be connected to the rlol (receive loss of lock) output pin of the xrt7300 line interface unit ic. the user can monitor the state of this pin by reading the state of bit 1 (rlol) within the line interface scan register (address = 0x81). if this input pin is "low", then it means that the "clock recovery phase-locked- loop" circuitry, within the xrt7300 device is properly locked onto the incom- ing ds3 e3 data-stream; and is properly recovering clock and data from this ds3/e3 data-stream. however, if this input pin is "high", then it means that the phase-locked-loop circuitry, within the xrt7300 device has lost lock with the incoming ds3 or e3 data-stream, and is not properly recovering clock and data. for more information on the operation of the xrt7300 ds3/e3 line interface unit ic, please consult the "xrt7300 ds3/e3 line interface unit" data sheet. if the customer is not using the xrt7300 ds3/e3 line interface unit ic, he/ she can use this input pin for other purposes. 77 extlos i receive los (loss of signal) indicator input (from xrt7300 liu ic): this input pin is intended to be connected to the rlos (receive loss of sig- nal) output pin of the xrt7300 line interface unit ic. the user can monitor the state of this pin by reading the state of bit 0 (rlos) within the line inter- face scan register (address = 0x81). if this input pin is "low", then it means that the xrt7300 device is currently not declaring an "los (loss of signal) condition. however, if this input pin is "high", then it means that the xrt7300 device is currently declaring an los (loss of signal) condition. for more information on the operation of the xr-t7300 ds3/e3 line receiver ic, please consult the "xrt7300 ds3/sts-1/e3 line interface unit ic" data sheet. asserting the rlos input pin will cause the XRT72L50 ds3/e3 framer device to declare an "los (loss of signal) condition. therefore, this input pin should not be used as a general purpose input. 78 dmo i "drive monitor output" input (from the xr-t7300 ds3/e3 line interface unit ic): this input pin is intended to be tied to the dmo output pin of the xrt7300 ds3/e3 line interface unit ic. the user can determine the state of this input pin by reading bit 2 (dmo) within the line interface scan register (address = 0x81). if this input signal is "high", then it means that the drive monitor cir- cuitry (within the xrt7300 ds3/e3 line interface unit ic) has not detected any bipolar signals at the mtip and mring inputs within the last 128 (32 bit- periods. if this input signal is "low", then it means that bipolar signals are being detected at the mtip and mring input pins of the xrt7300 device. if this customer is not using the xr-t7300 ds3/e3 line interface unit ic, then he/she can use this input pin for a variety of other purposes. 79 vdd **** power supply 3.3v + 5% 80 gnd **** ground pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 16 81 rxnib3/ rxhdlcdat3 o receive nibble output - 3: the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib0, rxnib1 and rxnib2. the data at this pin is updated on the rising edge of the rxclk output signal. n ote : this output pin is active only if the nibble-parallel mode has been selected. receive hdlc data output - 3: this pin contains bit 3 rxhdlc data when the hdlc controller is on. 82 rxnib2/ rxhdlcdat2 o receive nibble output - 2: the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib0, rxnib1 and rxnib2. the data at this pin is updated on the rising edge of the rxclk output signal. n ote : this output pin is active only if the nibble-parallel mode has been selected. receive hdlc data output - 2: this pin contains bit 2 rxhdlc data when the hdlc controller is on. 83 rxnib1/ rxhdlcdat1 o receive nibble output - 1: the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib0, rxnib2 and rxnib3. the data at this pin is updated on the rising edge of the rxclk output signal. n ote : this output pin is active only if the nibble-parallel mode has been selected. receive hdlc data output - 1: this pin contains bit 1 rxhdlc data when the hdlc controller is on. 84 rxnib0/ rxhdlcdat0 o receive nibble output - 0: the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib1, rxnib2 and rxnib3. the data at this pin is updated on the rising edge of the rxclk output signal. n ote : this output pin is active only if the nibble-parallel mode has been selected. receive hdlc data output - 0: this pin contains bit 0 rxhdlc data when the hdlc controller is on. 85 rxser/ rxidle o receive serial output: if the user opts to operate the XRT72L50 in the "serial" mode, then the chip will output the payload data, of the incoming ds3 or e3 frames, via this pin. the XRT72L50 will output this data upon the rising edge of rxclk. the user is advised to design the terminal equipment such that it will sample this data on the falling edge of rxclk. n ote : this signal is only active if the "nibint" input pin is pulled "low". receive idle: this pin will go high indicating the idle period of sent hdlc data packets. al- so, in combination with valfcs it can indicate error conditions. pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 17 86 rxais o receive "alarm indication signal" output pin: the framer will assert this pin to indicate that the alarm indication signal (ais) has been identified in the receive ds3 or e3 data stream. for ds3 applications: the framer will assert this pin to indicate that the alarm indication signal (ais) has been identified in the receive ds3 data stream. an "ais" is detected if the payload consists of the recurring pattern of 1010... and this pattern persists for 63 m-frames. an additional requirement for ais indication is that the c-bits are set to 0, and the x-bits are set to 1. this pin will be negated when a sufficient number of frames, not exhibiting the "1010..." pat- tern in the payload has been detected. for e3 applications: the receive section will declare an ais condition, if it detects two consecu- tive e3 frames, each containing 7 or less "0s". 87 rxclk o receive clock output signal for serial and nibble/parallel data inter- face: the exact behavior of this signal depends upon whether the XRT72L50 is operating in the "serial" or in the "nibble-parallel-mode". serial mode operation: in the "serial" mode, this signal is a 44.736mhz clock output signal (for ds3 applications) or 34.368mhz clock output signal (for e3 applications). the receive payload data output interface will update the data via the rxser out- put pin, upon the rising edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sam- ple the data on the "rxser" pin, upon the falling edge of this clock signal. nibble-parallel mode operation: in this nibble-parallel mode, the XRT72L50 will derive this clock signal, from the rxlineclk signal. the XRT72L50 will pulse this clock signal 1176 times for each "inbound" ds3 frame (or 1074 times for each inbound e3/itu-t g.832 frame, or 384 times for each inbound e3/itu-t g.751 frame). the receive payload data output interface will update the data, on the "rxnib[3:0]" output pins upon the falling edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sam- ple the data on the "rxnib[3:0] output pins, upon the rising edge of this clock signal 88 gnd **** ground 89 rxframe o receive boundary of ds3 or e3 frame output indicator: the exact functionality of this output pin depends upon whether the XRT72L50 framer ic is operating in the serial or nibble-parallel mode. serial mode operation: the receive section of the XRT72L50 will pulse this output pin high (for one bit-period) when the receive payload data output interface block is driving the very first bit of a given ds3 or e3 frame, onto the rxser output pin. nibble-parallel operation: the receive section of the XRT72L50 will pulse this output pin high (for one nibble-period), when the receive payload data output interface block is driving the very first nibble of a given ds3 or e3 frame, onto the rxnib[3:0] output pins. 90 vdd **** power supply 3.3v + 5% pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 18 91 rxoutclk/ rxhdlcdat7 o receive out clock - transmit terminal interface clock for loop-timing: this clock signal functions as the "terminal interface" clock source, if the XRT72L50 framer ic is operating in the "loop-timing" mode. in this mode, the transmitting terminal equipment is expected to input data to the framer ic, via the txser input pin, upon the rising edge of this clock sig- nal. the XRT72L50 will use the rising edge of this clock signal to sample the data at the txser input. this clock signal is a buffered version of the rxlineclk signal. receive hdlc data output - 7: this pin contains bit 7 rxhdlc data when the hdlc controller is on. 92 rxred o receiver red alarm indicator - receive framer: the framer asserts this output pin to denote that one of the following events has been detected by the receive framer: los - loss of signal condition oof - out of frame condition ais - alarm indication signal detection 93 rxoof o receiver "out of frame" indicator: the receive section of the XRT72L50 framer ic will assert this output signal whenever it has declared an "out of frame" (oof) condition with the incom- ing ds3 or e3 frames. this signal is negated when the framer correctly locates the framing alignment bits or bytes and correctly aligns itself with the incoming ds3 or e3 frames. 94 rxlos o receive section - loss of signal output indicator: this pin is asserted when the receive section encounters a string of 180 consecutive 0's (for ds3 operation) or 32 consecutive 0's (for e3 operation) via the rxpos and rxneg pins. this pin will be negated once the receive section has detected at least 60 pulses within 180 bit-periods (for ds3 operation); or the receive section has detected a string of 32 consecutive bits, that does not contain a string of 4 consecutive "0s" (for e3 operation). 95 rxohclk/ rxhdlcclk o receive overhead output clock signal: the XRT72L50 will output the overhead bits (within the incoming ds3 or e3 frames), via the "rxoh" output pin, upon the falling edge of this clock signal. as a consequence, the "user's data link equipment" should use the rising edge of this clock signal to sample the data on both the "rxoh" and "rxo- hframe" output pins. n ote : this clock signal is always active. receive hdlc output clock: when the hdlc controller is on, rxhdlcdat is updated by the 72l53 on this clock signal. pin description p in #p in n ame t ype d escription XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 19 96 rxohind o receive overhead bit indicator: the exact functionality of this output pin depends upon whether the XRT72L50 framer ic is operating in the serial or nibble-parallel mode. serial mode operation: this output pin pulses "high" (for one bit-period) whenever an "overhead" bit is being output via the "rxser" output pin, by the "receive payload data out- put interface" block. nibble-parallel mode operation: this output pin pulses high (for one nibble-period) whenever an overhead nibble is being output via the rxnib[3:0] output pins, by the receive payload data output interface block. n ote : the purpose of this output pin is to alert the "receive terminal equip- ment" that an overhead bit is being output via the "rxser" output pin, and that this data should be ignored. 97 rxoh/ rxhdlcdat6 o receive overhead output port: all overhead bits, which are received via the "receive section" of the framer ic; will be output via this output pin, upon the rising edge of rxohclk. receive hdlc data output - 6: this pin contains bit 6 rxhdlc data when the hdlc controller is on. 98 rxohenable/ rxhdlcdat5 o receive overhead enable indicator: the XRT72L50 will assert this output signal for one rxoutclk period when it is safe for the terminal equipment to sample the data on the rxoh output pin. receive hdlc data output - 5: this pin contains bit 5 rxhdlc data when the hdlc controller is on. 99 rxohframe/ rxhdlcdat4 o receive overhead frame boundary indicator: this output pin pulses "high" whenever the receive overhead data output interface block outputs the first overhead bit (or nibble) of a new ds3 or e3 frame. receive hdlc data output - 4: this pin contains bit 4 rxhdlc data when the hdlc controller is on. 100 tdo o test data out: boundary scan test data output. pin description p in #p in n ame t ype d escription ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 20 electrical characteristics absolute maximums power supply......................................... - 0.3v to +3.6v power dissipation pqfp package........................ 1.2w storage temperature ...............................-55c to 150c input voltage (any pin) .....................-0.3v to vdd + 0. 3v voltage at any pin .......................... -0.3v to vdd + 0.3v input current (any pin) ...................................... + 100ma dc electrical characteristics test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions i cc power supply current 120 ma all channels on v il input low voltage 0.3*vdd v v ih input high voltage 0.7*vdd v v ol output low voltage 0.4 v i ol = -1.6ma v oh output high voltage 2.4 v i oh = 40a i ih input high voltage current -10 10 a v ih = vdd i il input low voltage current -1 1 a v il = gnd ac electrical characteristics test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions transmit payload data input interface - loop-timed/serial mode (see figure 3) t 1 payload data (txser) set-up time to rising edge of rxoutclk 12 ns t 2 payload data (txser) hold time, from rising edge of rxoutclk 0ns t 3 rxoutclk to txframe output delay 5 ns t 4 rxoutclk to txohind output delay 6 ns transmit payload data input interface - local timed/serial mode (see figure 4) t 5 payload data (txser) set-up time to rising edge of txinclk 4ns t 6 payload data (txser) hold time, from rising edge of txinclk 0ns t 7 txframeref set-up time to rising edge of txinclk 2 ns framer ic is frame slave t 8 txframeref hold-time, from rising edge of txinclk 0 ns frame ic is frame slave t 9 txinclk to txohind output delay 15 ns XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 21 t 10 txinclk to txframe output delay 13 ns transmit payload data input interface - looped-timed/nibble mode (see figure 5) t 13a max delay of rising edge of txnibclk to data valid on txnib[3:0] ds3 e3 20 27 ns ns ds3 applications e3 applications transmit payload data input interface - looped-timed/nibble mode (see figure 5) t 13 txnibclk to txnibframe output delay 25 31 ns ns ds3 applications e3 applications transmit payload data input interface - local-timed/nibble mode (see figure 6) t 14 max input delay from txnicclk to txnib 20 27 ns ns ds3 applications e3 applications t 15 payload nibble hold time, from latching edge of txnibclk 0ns t 16 txframeref set-up time, to latching edge of txinclk 20 27 ns ns ds3 applications e3 applications framer ic is frame slave t 17 txframeref hold time, from latching edge of txnib- clk 0 ns frame ic is frame slave t 18 txnibclk to txnibframe output delay time 20 25 31 ns ns ds3 applications e3 applications ac electrical characteristics test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 22 ac electrical characteristics (cont.) test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions transmit overhead input interface timing - method 1 (figure 7) t 21 txohclk to txohframe output delay 111 0 0 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 22 txohins set-up time, to falling edge of txohclk 194 305 17 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 23 txohins hold time, from falling edge of txohclk 48 110 7 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 24 txoh data set-up time, to falling edge of txohclk 194 305 17 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 25 txoh data hold time, from falling edge of txohclk 48 110 7 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications transmit overhead data input interface - method 2 (figure 8) t 26 txohins to txinclk (falling edge) set-up time 254 72 15 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 23 t 27 txinclk clock (falling) edge to txohins hold-time 0 0 0 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 28 txohins to txinclk (falling edge) set-up time 254 72 15 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 29 txinclk clock (falling) edge to txohins hold-time 0 0 0 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 29a txohenable to txohins/txoh delay 1 ns transmit liu interface timing (see figure 9 and figure 10) t 30 rising edge of txlineclk to rising edge of txpos or txneg output signal. (framer is configured to output data on txpos and txneg on rising edge of txlineclk 2.0 ns t 31 falling edge of txlineclk to rising edge of txpos or txneg (framer is configured to output data via txpos and txneg on falling edge of txlineclk) 2.4 ns f txlineclk period of txlineclk clock signal 44.736 mhz ds3 applications f txlineclk period of txlineclk clock signal 34.368 mhz e3 applications t 32 period of txlineclk 22.36 ns ds3 applications t32 period of txlineclk 29.10 ns e3 applications receive liu interface timing (see figure 11 and figure 12) t 38 rxpos or rxneg set-up time to rising edge of rxlineclk. (framer is configured to sample data on rxpos and rxneg input pins, on the rising edge of rxlineclk) 0ns t 39 rxpos or rxneg hold time, from rising edge of rxlineclk (framer is configured to sample data on rxpos and rxneg input pins, on the rising edge of rxlineclk) 4ns ac electrical characteristics (cont.) test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 24 t 40 rxpos or rxneg set-up time to falling edge of rxlineclk. (framer is configured to sample data on rxpos and rxneg input pins, on the falling edge of rxlineclk) 0ns t 41 rxpos or rxneg hold time, from falling edge of rxlineclk (framer is configured to sample data on rxpos and rxneg input pins, on the falling edge of rxlineclk) 3ns receive payload data output inteface timing - serial mode operation (see figure 13) t 50 rising edge of rxclk to payload data (rxser) out- put delay 13 16 ns ns ds3 applications e3 applications t 51 rising edge of rxclk to rxframe output delay 13 16 ns ns ds3 applications e3 applications t 52 rising edge of rxclk to rxohind output delay. 13 16 ns ns ds3 applications e3 applications receive payload data output interface timing - nibble mode operation (see figure 14) t 53 falling edge of rxclk to rising edge of rxframe out- put delay 2.1 ns t 54 falling edge of rxclk to rising edge of rxnib[3:0] output delay 2ns receive overhead data output interface timing - method 1 - using rxohenable (see figure 15) t 59a falling edge of rxohclk to rxframe output 20 25 23 0 ns ns ds3 applications e3 applications t 59b falling edge of rxclk to rxoh output delay 20 25 23 0 ns ns ds3 applications e3 applications receive overheadf data output interface timing - method 2 - using rxohenable (see figure 16) t 60 rising edge of rxoutclk to rising edge of rxohenable delay. 29.4ns t 60a rising edge of rxohframe to rising edge of rxohenable delay 88 224 28 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications t 60b rxoh data valid to rising edge of rxohenable delay 88 85 28 ns ns ns ds3 applications e3, itu-t g.832 applications e3, itu-t g.751 applications ac electrical characteristics (cont.) test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 25 microprocessor interface - intel (see figure 17) t 64 a(9) - a(0) setup time to ale_as low 0 ns t 65 a(9) - a(0) hold time from ale_as low. 1 ns intel type read operations (see figure 17 and figure 19) t 66 rd _ds, wr _r/w pulse width 87 ns t 67 data valid from rd _ds low. 32 ns t 68 data bus floating from rd _ds high 9 ns t 69 ale to rd time 3 ns t 701 rd time to not ready (e.g., rdy _dtck toggling low) 16 ns t 70 rd to ready time (e.g., rdy _dtck toggling high) 80 ns t 76 minimum time between read burst access (e.g., the rising edge of rd to falling edge of rd ) 33 ns intel type write operations (figure 18 and figure 20) t 71 data setup time to wr _r/w high 0 ns t 72 data hold time from wr _r/w high 3 ns t 73 high time between reads and/or writes 33 ns t 74 ale to wr time 3 ns t 77 min time between write burst access (e.g., the ris- ing edge of wr to the falling edge of wr ) 33 ns t 770 cs assertion to falling edge of wr _r/w 28 ns microprocessor interface - motorola read operations (see figure 21) t 78 a(9) - a(0) setup time to falling edge of ale_as 0 ns t 79 rising edge of rd _ds to rising edge of rdy _dtck delay 16 ns t 80 rising edge of rdy _dtck to tri-state of d[7:0] 0 ns microprocessor interface - motorola read & write operations (see figure 22) t 78 a(9) - a(0) setup time to falling edge of ale_as 0 ns t 81 d[7:0] set-up time to falling edge of rd _ds 0 ns t 82 rising edge of rd _ds to rising edge of rdy _dtck delay 13 ns reset pulse width - both motorola and intel operations (see figure 23) t 90 reset pulse width 200 ns ac electrical characteristics (cont.) test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions ? ? ? ? xrt72l5 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 26 1.0 timing diagrams f igure 3. t iming d iagram for t ransmit p ayload i nput i nterface , when the XRT72L50 d evice is operat - ing in both the ds3 and l oop -t iming m odes xrt72l5x transmit payload data i/f signals rxoutclk txser txframe txoh_ind payload[4702] payload[4703] x-bit payload[0] ds3 frame number n ds3 frame number n + 1 t1 t2 t3 t4 f igure 4. t iming d iagram for the t ransmit p ayload i nput i nterface , when the XRT72L50 d evice is operating in both the ds3 and l ocal -t iming m odes xrt72l5x transmit payload data i/f signals txinclk txser txframeref txoh_ind payload[4702] payload[4703] x-bit payload[1] ds3 frame number n ds3 frame number n + 1 t5 t6 t7 t8 t9 t10 xrt72l5 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 27 f igure 5. t iming d iagram for the t ransmit p ayload d ata i nput i nterface , when the XRT72L50 d evice is operating in both the ds3/n ibble and l ooped -t iming m odes rxoutclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of xrt72l5x device t11 t12 t13 t13a f igure 6. t iming d iagram for the t ransmit p ayload d ata i nput i nterface , when the XRT72L50 d evice is operating in the ds3/n ibble and l ocal -t iming m odes ds3 frame number n ds3 frame number n + 1 txinclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of the xrt72l5x device t14 t15 txframeref t16 t17 t18 ? ? ? ? xrt72l5 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 28 f igure 7. t iming d iagram for the t ransmit o verhead d ata i nput i nterface (m ethod 1 a ccess ) txohclk txohins txohframe txoh remaining overhead bits with ds3 frame x bit = 0 x bit = 0 t21 t22 t24 t23 t25 f igure 8. t iming d iagram for the t ransmit o verhead d ata i nput i nterface (m ethod 2 a ccess ) txinclk txohframe txohenable txohins txoh xrt72l5x samples txoh here. txohenable pulse # 8 x bit = 0 x bit = 0 t26 t27 t28 t29 t29a xrt72l5 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 29 f igure 9. t ransmit liu i nterface t iming - f ramer is configured to update "t x pos" and "t x neg" on the rising edge of "t x l ine c lk " txlineclk txpos txneg t32 t30 t33 f igure 10. t ransmit liu i nterface t iming - f ramer is configured to update "t x pos" and "t x neg" on the falling edge of "t x l ine c lk " txlineclk txpos txneg t31 t32 t33 ? ? ? ? xrt72l5 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 30 f igure 11. r eceive liu i nterface t iming - f ramer is configured to sample "r x pos" and "r x neg" on the rising edge of "r x l ine c lk " rxlineclk rxpos rxneg t40 t41 f igure 12. r eceiver liu i nterface t iming - f ramer is configured to sample "r x pos" and "r x neg" on the falling edge of "r x l ine c lk " rxlineclk rxpos rxneg t38 t39 t42 xrt72l5 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 31 f igure 13. r eceive p ayload d ata o utput i nterface t iming xrt72l5x receive payload data i/f signals rxclk rxser rxframe rxohind payload[4702] payload[4703] x-bit payload[0] t50 t51 t52 f igure 14. r eceive p ayload d ata o utput i nterface t iming (n ibble m ode o peration ) xrt72l5x receive payload data i/f signals ds3 frame number n ds3 frame number n + 1 rxoutclk rxframe rxclk rxnib[3:0] nibble [0] nibble [1] recommended sampling edge of terminal equipment t53 t54 ? ? ? ? xrt72l5 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 32 f igure 15. r eceive o verhead d ata o utput i nterface t iming (m ethod 1 - u sing r x ohc lk ) rxohclk rxohframe rxoh x f1 aic f0 feac t59a t59b f igure 16. r eceive o verhead d ata o utput i nterface t iming (m ethod 2 - u sing r x ohe nable ) rxoutclk rxohenable rxohframe rxoh udl f1 x1 f1 aic t60 t60a t60b xrt72l5 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 33 f igure 17. m icroprocessor i nterface t iming - i ntel t ype p rogrammed i/o r ead o perations ale_as rd_ds a[9:0] cs d[7:0] rdy_dtck not valid valid address of target wr_r/w t64 t65 t67 t68 t66 t70 t69 t701 f igure 18. m icroprocessor i nterface t iming - i ntel t ype p rogrammed i/o w rite o perations ale_as a[9:0] cs d[7:0] wr_r/w data to be written address of target rd_ds t64 t65 t71 t72 t73 t66 t770 ? ? ? ? xrt72l5 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 34 f igure 19. m icroprocessor i nterface t iming - i ntel t ype r ead b urst a ccess o peration ale_as rd_ds a[9:0] cs d[7:0] rdy_dtck not valid valid data at offset =0x01 wr_r/w not valid valid data at offset =0x02 address of initial target register (offset = 0x00) t 70 t 76 t 68 f igure 20. m icroprocessor i nterface t iming - i ntel type w rite b urst a ccess o peration ale_as a(9:0) cs d(7:0) rd_ds wr_r/w not valid valid data at offset = 0x01 address of initial target register (offset = 0x00) t 76 t 68 not valid valid data at offset = 0x02 xrt72l5 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 35 f igure 21. m icroprocessor i nterface t iming - m otorola t ype p rogrammed i/o r ead o peration f igure 22. m icroprocessor i nterface t iming - m otorola t ype p rogrammed i/o w rite o peration ale_as a(9:0) cs d(7:0) rd_ds wr_r/w rdy_dtck not valid valid data address of target register t 79 t 80 t 78 ale_as a(9:0) cs d(7:0) rd_ds wr_r/w rdy_dtck data to be written address of target register t 82 t 81 t 78 ? ? ? ? xrt72l5 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 36 f igure 23. m icroprocessor i nterface t iming - r eset p ulse w idth reset t90 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 37 2.0 the microprocessor interface block the microprocessor interface section supports com- munication between the local microprocessor (p) and the framer ic. in particular, the microprocessor interface section supports the following operations between the local microprocessor and the framer. ? the writing of configuration data into the framer on-chip (addressable) registers. ? the writing of an outbound pmdl (path mainte- nance data link) message into the transmit lapd message buffer (within the framer ic). ? the framer ic's generation of an interrupt request to the p. ? the p's servicing of the interrupt request from the framer ic. ? the monitoring of the system's health by periodi- cally reading the on-chip performance monitor reg- isters. ? the reading of an inbound pmdl message from the receive lapd message buffer (within the framer ic). each of these operations (between the local micro- processor and the framer ic) will be discussed in some detail, throughout this data sheet. figure 24 presents a simple block diagram of the mi- croprocessor interface section, within the framer ic. 2.1 t he m icroprocessor i nterface b lock s ig - nal the framer ic may be configured into a wide variety of different operating modes and have its perfor- mance monitored by software through a standard (lo- cal housekeeping) microprocessor, using data, ad- dress and control signals. the local p configures the framer ic (into a desired operating mode) by writing data into specific address- able, on-chip read/write registers, or on-chip ram. the microprocessor interface provides the signals which are required for a general purpose micropro- cessor to read or write data into these registers. the microprocessor interface also supports polled and in- terrupt driven environments. these interface signals are described below in table 1, table 2, and table 3. the microprocessor interface can be configured to operate in the motorola mode or in the intel mode. when the microprocessor interface is operating in the motorola mode, then some of the control signals function in a manner as required by the motorola 68000 family of microprocessors. likewise, when the microprocessor interface is operating in the intel mode, then some of these control signals function in a manner as required by the intel 80xx family of mi- croprocessors. table 1 lists and describes those microprocessor in- terface signals whose role is constant across the two modes. table 2 describes the role of some of these signals when the microprocessor interface is operat- ing in the intel mode. likewise, table 3 describes the role of these signals when the microprocessor inter- face is operating in the motorola mode. f igure 24. s imple b lock d iagram of the m icroprocessor i nterface b lock , within the f ramer ic a(8:0) wr_r/w rd_ds cs ale_as reset int d[7:0] moto rdy_dtck microprocessor & programable registers ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 38 t able 1: d escription of the m icroprocessor i nterface s ignals that exhibit constant roles in both the i ntel and m otorola m odes p in n ame t ype d escription moto i selection input for intel/motorola p interface. setting this pin to a logic "high" configures the microprocessor interface to operate in the motorola mode. likewise, setting this pin to a logic "low" configures the microprocessor interface to operate in the intel mode. d[7:0] i/o bi-directional data bus for register read or write operations a[8:0] i nine bit address bus input: this nine bit address bus is provided to allow the user to select an on-chip register or on-chip ram location and select the desired framer channel to address. cs i chip select input. this active-low signal selects the microprocessor interface of the uni device and enables read/ write operations with the on-chip registers/on-chip ram. int o interrupt request output: this open-drain/active-low output signal will inform the local p that the uni has an interrupt condi- tion that needs servicing. t able 2: p in d escription of m icroprocessor i nterface s ignals - w hile the m icroprocessor i nterface is o perating in the i ntel m ode p in n ame e quivalent p in in i ntel environment t ype d escription ale_as ale i address-latch enable: this active-high signal is used to latch the contents on the address bus, a[10:0]. the contents of the address bus are latched into the a[10:0] inputs on the falling edge of ale_as. additionally, this signal can be used to indicate the start of a burst cycle. rd _ds rd* i read signal: this active-low input functions as the read signal from the local p . when this signal goes "low", the uni microprocessor interface will place the contents of the addressed register on the data bus pins (d[15:0]). the data bus will be "tri-stated" once this input signal returns "high". wr _r/w wr* i write signal: this "active-low" input functions as the write signal from the local p . the contents of the data bus (d[15:0]) will be written into the addressed reg- ister (via a[10:0]), on the rising edge of this signal. rdy _dtck ready* o ready output: this "active-low" signal is provided by the uni device, and indi- cates that the current read or write cycle is to be extended until this signal is asserted. the local p will typically insert wait states until this signal is asserted. this output will toggle "low" when the device is ready for the next read or write cycle. XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 39 2.2 i nterfacing the XRT72L50 ds3/e3 f ramer to the l ocal c/p via the m icroprocessor i nterface b lock the microprocessor interface block, within the framer device is very flexible and provides the following op- tions to the user. ? to interface the framer device to a c/p over an 8-bit wide bi-directional data bus. ? to interface the framer to an intel-type or motorola- type c/p. ? to transfer data (between the framer ic and the c/p) via the programmed i/o or burst mode each of the options are discussed in detail below. section 2.2.1 will discussed the issues associated with interfacing the framer to a c/p over an 8-bit bi-directional data bus. afterwards, section 2.2.2 will discuss data access (e.g., programmed i/o and burst) mode when interfaced to both motorola-type and intel-type c/p. 2.2.1 interfacing the XRT72L50 ds3/e3 framer to the microprocessor over an 8 bit wide bi-direc- tional data bus the XRT72L50 ds3/e3 framer microprocessor inter- face permits the user to interface it to a c/p over an 8-bit wide bi-directional data bus. 2.2.1.1 interfacing the framer to the c/p over an 8-bit wide bi-directional data bus. in general, interfacing the framer to an 8-bit c/p is quite straight-forward. this is because most of the registers, within the framer, are 8-bits wide. further, in this mode, the c/p can read or write data into both even and odd numbered addresses within the framer address space. reading performance monitor (pmon) registers the only awkward issue that the user should be wary of (while operating in the 8-bit mode) occurs whenev- er the c/p needs to read the contents of one of the pmon (performance monitor) registers. the XRT72L50 ds3/e3 framer device consists of the following pmon registers. ? pmon lcv event count register ? pmon framing error event count register ? pmon received febe event count register ? pmon parity error event count register ? pmon received single-bit hec error count reg- ister ? pmon received multiple-bit hec error count register ? pmon received idle cell count register ? pmon received valid cell count register ? pmon discarded cell count register ? pmon transmitted idle cell count register ? pmon transmitted valid cell count register. unlike most of the registers within the framer, the pmon registers are 16-bit registers (or 16-bits wide). table 4 lists each of these pmon registers as con- sisting of two 8-bit registers. one of these 8-bit regis- ter is labeled msb (or most significant byte) and the other register is labeled lsb (or least significant t able 3: p in d escription of the m icroprocessor i nterface s ignals while the m icroprocessor i nterface is operating in the m otorola m ode p in n ame e quivalent p in in m otorola environment t ype d escription ale_as as* i address strobe: this "active-low" signal is used to latch the contents on the address bus input pins: a[10:0] into the microprocessor interface circuitry. the contents of the address bus are latched into the uni device on the rising edge of the ale_as signal. this signal can also be used to indicate the start of a burst cycle. rd _ds ds* i data strobe: this signal latches the contents of the bi-directional data bus pins into the addressed register (within the uni) during a write cycle. wr _r/w r/w* i read/write* input: when this pin is "high", it indicates a read cycle. when this pin is "low", it indicates a write cycle. rdy _dtc k dtack* o data transfer acknowledge: the uni device asserts dtack* in order to inform the cpu that the present read or write cycle is nearly complete. the 68000 family of cpus requires this signal from its peripheral devices, in order to quickly and properly complete a read or write cycle. ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 40 byte). when an 8-bit pmon register is concatenat- ed with its companion 8-bit pmon register, one ob- tains the full 16-bit expression within that pmon reg- ister. the consequence of having these 16-bit registers is that an 8-bit c/p will have to perform two consecu- tive read operations in order to read in the full 16-bit expression contained within a given pmon register. to complicate matters, these pmon registers are reset-upon-read registers. more specifically, these pmon register are reset-upon-read in the sense that, the entire 16-bit contents, within a given pmon register is reset, as soon as an 8-bit c/p reads in either byte of this two-byte (e.g., 16 bit) expression. for example; consider that an 8-bit c/p needs to read in the pmon lcv event count register. in order to ac- complish this task, the 8-bit c/p is going to have to read in the contents of pmon lcv event count reg- ister - msb (located at address = 0x50) and the con- tents of the pmon lcv event count register - lsb (located at address = 0x51). these two eight-bit reg- isters, when concatenated together, make up the pmon lcv event count register. if the 8-bit c/p reads in the pmon lcv event count-lsb register first, then the entire pmon lcv event count register will be reset to 0x0000. as a consequence, if the 8-bit c/p attempts to read in the pmon lcv event count-msb register in the very next read cycle, it will read in the value 0x00. the pmon holding register in order to resolve this reset-upon-read problem, the XRT72L50 ds3/e3 framer device includes a spe- cial register, which permits 8-bit c/p to read in the full 16-bit contents of these pmon registers. this special register is called the pmon holding register and is located at 0x6c within the framer address space. the operation of the pmon holding register is as fol- lows. whenever an 8-bit c/p reads in one of the bytes (of the 2-byte pmon register), the contents of the unread (e.g., other) byte will be stored in the pmon holding register. therefore, the 8-bit c/p must then read in the contents of the pmon holding register in the very next read operation. in summary: whenever an 8-bit c/p needs to read a pmon register, it must execute the follow- ing steps. step 1: read in the contents of a given 8-bit pmon register (it does not matter whether the c/p reads in the msb or the lsb register). step 2: read in the contents of the pmon holding register (located at address = 0x6c). this register will contain the contents of the other byte. 2.2.2 data access modes as mentioned earlier, the microprocessor interface block supports data transfer between the framer and the c/p (e.g., read and write operations) via two modes: the programmed i/o and the burst modes. each of these data access modes are discussed in detail below. 2.2.2.1 data access using programmed i/o programmed i/o is the conventional manner in which a microprocessor exchanges data with a peripheral device. however, it is also the slowest method of data exchange between the framer and the c/p. the next two sections present detailed information on programmed i/o access, when the XRT72L50 ds3/ e3 framer is operating in the intel mode or in the mo- torola mode. 2.2.2.1.1 programmed i/o access in the intel mode if the XRT72L50 ds3/e3 framer is interfaced to an intel-type c/p (e.g., the 80x86 family, etc.), then it should be configured to operate in the intel mode (by tying the moto pin to ground). intel-type read and write operations are described below. 2.2.2.1.1.1 the intel mode read cycle whenever an intel-type c/p wishes to read the contents of a register or some location within the re- ceive lapd message buffer or the receive oam cell buffer, (within the framer device), it should do the fol- lowing. 1. place the address of the target register or buffer location (within the framer) on the address bus input pins a[10:0]. 2. while the c/p is placing this address value on the address bus, the address decoding circuitry (within the user's system) should assert the cs (chip select) pin of the framer, by toggling it "low". this action enables further communica- tion between the c/p and the framer micropro- cessor interface block. 3. toggle the ale_as (address latch enable) input pin "high". this step enables the address bus input drivers, within the microprocessor interface block of the framer. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate address data setup time), the c/p should toggle the ale_as pin "low". this step causes the framer device to latch the contents of the address bus into its internal circuitry. at this point, the address XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 41 of the register or buffer locations (within the framer), has now been selected. 5. next, the c/p should indicate that this current bus cycle is a read operation by toggling the rd _ds (read strobe) input pin "low". this action also enables the bi-directional data bus output drivers of the framer device. at this point, the bi-directional data bus output drivers will pro- ceed to drive the contents of the latched addressed register (or buffer location) onto the bi- directional data bus, d[7:0]. 6. immediately after the c/p toggles the read strobe signal "low", the framer device will toggle the rdy _dtck output pin "low". the framer device does this in order to inform the c/p that the data (to be read from the data bus) is not ready to be latched into the c/p. 7. after some settling time, the data on the bi-direc- tional data bus will stabilize and can be read by the c/p. the XRT72L50 ds3/e3 framer will indicate that this data can be read by toggling the rdy _dtck (ready) signal "high". 8. after the c/p detects the rdy _dtck signal (from the XRT72L50 ds3/e3 framer), it can then terminate the read cycle by toggling the rd _ds (read strobe) input pin "high". figure 25 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during an intel-type programmed i/o read opera- tion. 2.2.2.1.1.2 the intel mode write cycle whenever an intel-type c/p wishes to write a byte or word of data into a register or buffer location, within the framer, it should do the following. 1. assert the ale_as (address latch enable) input pin by toggling it "high". when the c/p asserts the ale_as input pin, it enables the address bus input drivers within the framer chip. 2. place the address of the target register or buffer location (within the framer), on the address bus input pins, a[10:0]. 3. while the c/p is placing this address value onto the address bus, the address decoding cir- cuitry (within the user's system) should assert the cs input pin of the framer device by toggling it "low". this step enables further communication between the c/p and the framer microproces- sor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate address setup time), the c/p should toggle the ale_as input pin "low". this step causes the framer device to latch the contents of the address bus into its internal circuitry. at this point, the address of the register or buffer location (within the framer), has now been selected. 5. next, the c/p should indicate that this current bus cycle is a write operation by toggling the wr _r/w (write strobe) input pin "low". this action also enables the bi-directional data bus input drivers of the framer device. 6. the c/p should then place the byte or word that it intends to write into the target register, on the bi-directional data bus, d[7:0]. 7. after waiting the appropriate amount of time for the data (on the bi-directional data bus) to settle, f igure 25. b ehavior of m icroprocessor i nterface signals during an i ntel - type p rogrammed i/o r ead o peration ale_as a(8:0) cs d(7:0) rd_ds wr_r/w rdy_dtck not valid valid address of target register ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 42 the c/p should toggle the wr _r/w (write strobe) input pin "high". this action accom- plishes two things: a. it latches the contents of the bi-directional data bus into the XRT72L50 ds3/e3 framer micropro- cessor interface block. b. it terminates the write cycle. figure 26 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during an intel-type programmed i/o write opera- tion. 2.2.2.1.2 programmed i/o access in the motor- ola mode if the XRT72L50 ds3/e3 framer is interfaced to a motorola-type c/p (e.g., the mc680x0 family, etc.), it should be configured to operate in the motorola mode (by tying the moto pin to vcc). motorola-type programmed i/o read and write operations are de- scribed below. 2.2.2.1.2.1 the motorola mode read cycle whenever a motorola-type c/p wishes to read the contents of a register or some location within the re- ceive lapd message or receive oam cell buffer, (within the framer device) it should do the following. 1. assert the ale_as (address-strobe) input pin by toggling it low. this step enables the address bus input drivers, within the microprocessor inter- face block of the framer ic. 2. place the address of the target register (or buffer location) within the framer, on the address bus input pins, a[10:0]. 3. at the same time, the address decoding circuitry (within the user's system) should assert the cs (chip select) input pin of the framer device, by toggling it "low". this action enables further communication between the c/p and the framer microprocessor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate address setup time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the address bus into its internal circuitry. at this point, the address of the register or buffer location (within the framer) has now been selected. 5. further, the c/p should indicate that this cycle is a read cycle by setting the wr _r/w (r/w ) input pin "high". 6. next the c/p should initiate the current bus cycle by toggling the rd _ds (data strobe) input pin "low". this step enables the bi-directional data bus output drivers, within the XRT72L50 ds3/e3 framer device. at this point, the bi-direc- tional data bus output drivers will proceed to driver the contents of the address register onto the bi-directional data bus, d[7:0]. 7. after some settling time, the data on the bi-direc- tional data bus will stabilize and can be read by the c/p. the XRT72L50 ds3/e3 framer will indicate that this data can be read by asserting the rdy _dtck (dtack) signal. 8. after the c/p detects the rdy _dtck signal (from the XRT72L50 ds3/e3 framer) it will termi- f igure 26. b ehavior of the m icroprocessor i nterface s ignals , during an i ntel - type p rogrammed i/o w rite o peration ale_as a(8:0) cs d(7:0) rd_ds wr_r/w rdy_dtck data to be written address of target register XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 43 nate the read cycle by toggling the rd _ds (data strobe) input pin "high". figure 27 presents a timing diagram which illustrates the behavior of the microprocessor interface signals during a motorola-type programmed i/o read opera- tion. 2.2.2.1.2.2 the motorola mode write cycle whenever a motorola-type c/p wishes to write a byte or word of data into a register or buffer location, within the framer, it should do the following. 1. assert the ale_as (address select) input pin by toggling it "low". this step enables the address bus input drivers (within the framer chip). 2. place the address of the target register or buffer location (within the framer), on the address bus input pins, a[10:0]. 3. while the c/p is placing this address value onto the address bus, the address-decoding cir- cuitry (within the user's system) should assert the cs (chip select) input pins of the framer by tog- gling it "low". this step enables further commu- nication between the c/p and the framer microprocessor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate address setup time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the address bus into its own circuitry. at this point, the address of the register or buffer location (within the framer), has now been selected. 5. further, the c/p should indicate that this cur- rent bus cycle is a write operation by toggling the wr _r/w (r/w ) input pin "low". 6. the c/p should then place the byte or word that it intends to write into the target register, on the bi-directional data bus, d[7:0]. 7. next, the c/p should initiate the bus cycle by toggling the rd _ds (data strobe) input pin "low". when the XRT72L50 ds3/e3 framer senses that the wr _r/w (r/w ) input pin is "high" and that the rd _ds (data strobe) input pin has toggled "low", it will enable the input drivers of the bi-directional data bus, d[7:0]. 8. after waiting the appropriate time, for this newly placed data to settle on the bi-directional data bus (e.g., the data setup time) the framer will assert the rdy _dtck output signal. 9. after the c/p detects the rdy _dtck signal (from the framer), the c/p should toggle the rd _ds input pin "high". this action accom- plishes two things. a. it latches the contents of the bi-directional data bus into the XRT72L50 ds3/e3 microprocessor interface block. b. it terminates the write cycle. figure 28 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during a motorola-type programmed i/o write opera- tion. f igure 27. i llustration of the b ehavior of m icroprocessor i nterface signals , during a m otorola - type p rogrammed i/o r ead o peration ale_as a(8:0) cs d(7:0) rd_ds wr_r/w rdy_dtck not valid address of target register valid data ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 44 2.2.2.2 data access using burst mode i/o burst mode i/o access is a much faster way to trans- fer data between the c/p and the microprocessor interface (of the XRT72L50 ds3/e3 framer), than programmed i/o. the reason why burst mode i/o is faster is explained below. data is placed upon the address bus input pins a[10:0] only for the very first access, within a given burst access. the remaining read or write operations (within this burst access) do not require the place- ment of the address data on the address data bus. as a consequence, the user does not have to wait through the address setup and hold times for each of these read/write operation, within the burst access. it is important to note that there are some limitations associated with burst mode i/o operations. 1. all cycles within the burst access, must be either all read or all write cycles. no mixing of read and write cycles is permitted. 2. a burst access can only be used when read or write operations are to be employed over a con- tiguous range of address locations, within the framer device. 3. the very first read or write cycle, within a burst access, must start at the lowest address value, of the range of addresses to be accessed. subse- quent operations will automatically be incre- mented to the very next higher address value. examples of burst mode i/o operations are present- ed below for read and write operations, with both in- tel-type and motorola-type c/p. 2.2.2.2.1 burst i/o access in the intel mode if the XRT72L50 ds3/e3 framer is interfaced to an intel-type c/p (e.g., the 80x86 family, etc.), then it should be configured to operate in the intel mode (by tying the moto pin to ground). intel-type read and write burst i/o access operations are described be- low. 2.2.2.2.1.1 the intel-mode read burst access whenever an intel-type c/p wishes to read the contents of numerous registers or buffer locations over a contiguous range of addresses, then it should do the following. a. perform the initial read operation of the burst access. b. perform the remaining read operations of the burst access. c. terminate the burst access operation. each of these operations within the burst access are described below. 2.2.2.2.1.1.1 the initial read operation the initial read operation of an intel-type read burst access is accomplished by executing a programmed i/o read cycle as summarized below. a.0 execute a single ordinary (programmed i/ o) read cycle, as described in steps a.1 through a.7 below. a.1 place the address of the initial-target register or buffer location (within the framer) on the address bus input pins a[10:0]. a.2 while the c/p is placing this address value onto the address bus, the address decoding f igure 28. i llustration of the b ehavior of the m icroprocessor i nterface signal , during a m otorola - type p rogrammed i/o w rite o peration rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w data to be written address of target register XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 45 circuitry (within the user's system) should assert the cs input pin of the framer, by tog- gling it "low". this step enables further com- munication between the c/p and the framer microprocessor interface block. a.3 assert the ale_as (address latch enable) pin by toggling it "high". this step enables the address bus input drivers, within the micropro- cessor interface block of the framer. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate address data setup time), the c/p should then toggle the ale_as pin "low". this step latches the contents, on the address bus pins, a[10:0], into the XRT72L50 ds3/e3 framer microprocessor interface block. at this point, the initial address of the burst access has now been selected. n ote : the ale_as input pin should remain "low" for the remainder of this burst access operation. a.5 next, the c/p should indicate that this cur- rent bus cycle is a read operation by toggling the rd _ds (read strobe) input pin "low". this action also enables the bi-directional data bus output drivers of the framer device. at this point, the bi-directional data bus output drivers will proceed to drive the contents of the addressed register onto the bi-directional data bus, d[7:0]. a.6 immediately after the c/p toggles the read strobe signal "low", the framer device will tog- gle the rdy _dtck (ready) output pin "low". the framer device does this in order to inform the c/p that the data (to be read from the data bus) is not ready to be latched into the c/p. a.7 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the XRT72L50 ds3/e3 framer will indicate that this data is ready to be read, by toggling the rdy _dtck (ready) sig- nal "high". a.8 after the c/p detects the rdy _dtck signal (from the XRT72L50 ds3/e3 framer ic), it can then will terminate the read cycle by toggling the rd _ds (read strobe) input pin "high". figure 29 presents an illustration of the behavior of the microprocessor interface signals, during the initial read operation, within a burst i/o cycle for an intel- type c/p. at the completion of this initial read cycle, the c/p has read in the contents of the first register or buffer location (within the XRT72L50 ds3/e3 framer) for this particular burst i/o access operation. in order to illustrate how this burst access operation works, the byte (or word) of data, that is being read in figure 29, has been labeled valid data at offset = 0x00. this label indicates that the c/p is reading the very first register (or buffer location) in this burst access opera- tion. 2.2.2.2.1.1.2 the subsequent read operations the procedure that the c/p must use to perform the remaining read cycles, within this burst access operation, is presented below. f igure 29. b ehavior of the m icroprocessor i nterface s ignals , during the i nitial r ead o peration of a b urst c ycle (i ntel t ype p rocessor ) rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w not valid address of "initial" target register (offset = 0x00) valid data of offset = 0x00 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 46 b.0 execute each subsequent read cycles, as described in steps 1 through 3 below. b.1 without toggling the ale_as input pin (e.g., keeping it "low"), toggle the rd _ds input pin "low". this step accomplishes the following. a. the framer will internally increments the latched address value (within the microprocessor inter- face circuitry). b. the output drivers of the bi-directional data bus, d[7:0] are enabled. at some time later, the regis- ter or buffer location corresponding to the incre- mented latched address value will be driven onto the bi-directional data bus. b.2 immediately after the read strobe pin toggles "low" the framer ic will toggle the rdy _dtck (ready) output pin "low" to indicate its not ready status. b.3 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the XRT72L50 ds3/e3 framer will indicate that this data is ready to be read by toggling the rdy _dtck (ready) sig- nal "high". b.4 after the c/p detects the rdy _dtck signal (from the XRT72L50 ds3/e3 framer), it can then terminates the read cycle by toggling the rd _ds (read strobe) input pin "high". for subsequent read operations, within this burst cy- cle, the c/p simply repeats steps 1 through 3, as il- lustrated in figure 30. in addition to the behavior of the microprocessor in- terface signals, figure 30 also illustrates other points regarding the burst access operation. a. the framer internally increments the address value, from the original latched value shown in figure 29. this is illustrated by the data, appear- ing on the data bus, (for the first read access) being labeled valid data at offset = 0x01 and that for the second read access being labeled valid data at offset = 0x02. b. the framer performs this address incrementing process even though there are no changes in the address bus data, a[10:0]. 2.2.2.2.1.1.3 terminating the burst access operation the burst access operation will be terminated upon the rising edge of the ale_as input signal. at this point the framer will cease to internally increment the latched address value. further, the c/p is now free to execute either a programmed i/o access or to start another burst access operation with the XRT72L50 ds3/e3 framer. 2.2.2.2.1.2 the intel-mode write burst access whenever an intel-type c/p wishes to write data in- to a contiguous range of addresses, then it should do the following. a. perform the initial write operation of the burst access. b. perform the remaining write operations, of the burst access. c. terminate the burst access operation. each of these operations within the burst access are described below. f igure 30. b ehavior of the m icroprocessor i nterface s ignals , during subsequent r ead o perations within the b urst i/o c ycle rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w not valid address of "initial" target register (offset = 0x00) valid data at offset = 0x01 not valid valid data at offset = 0x02 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 47 2.2.2.2.1.2.1 the initial write operation the initial write operation of an intel-type write burst access is accomplished by executing a programmed i/o write cycle as summarized below. a.0 execute a single ordinary (programmed i/ o) write cycle, as described in steps a.1 through a.7 below. a.1 place the address of the initial target register (or buffer location) within the framer, on the address bus pins, a[10:0]. a.2 at the same time, the address-decoding cir- cuitry (within the user's system) should assert the cs (chip select) input pin of the framer, by toggling it "low". this step enables further communication between the c/p and the framer microprocessor interface block. a.3 assert the ale_as (address latch enable) input pin "high". this step enables the address bus input drivers, within the microprocessor interface block of the framer. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate address setup time), the c/p should then toggle the ale_as input pin "low". this step latches the contents, on the address bus pins, a[10:0], into the XRT72L50 ds3/e3 framer microprocessor interface block. at this point, the initial address of the burst access has now been selected. n ote : the ale_as input pin should remain "low" for the remainder of this burst i/o access operation. a.5 next, the c/p should indicate that this cur- rent bus cycle is a write operation by keeping the rd _ds pin "high" and toggling the wr _r/ w (write strobe) pin "low". this action also enables the bi-directional data bus input drivers of the framer device. a.6 the c/p places the byte (or word) that it intends to write into the target register on the bi-directional data bus, d[7:0]. a.7 after waiting the appropriate amount of time, for the data (on the bi-directional data bus) to set- tle, the c/p should toggle the wr _r/w (write strobe) input pin "high". this action accom- plishes two things. a. it latches the contents of the bi-directional data bus into the XRT72L50 ds3/e3 framer micropro- cessor interface block. b. it terminates the write cycle. figure 31 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during the initial write operation within a burst ac- cess, for an intel-type c/p. at the completion of this initial write cycle, the c/p has written a byte or word into the first register or buffer location (within the XRT72L50 ds3/e3 framer) for this particular burst access operation. in order to illustrate this point, the byte (or word) of data, that is being written in figure 31 has been labeled data to be written (offset = 0x00). f igure 31. b ehavior of the m icroprocessor i nterface signals , during the i nitial w rite o peration of a b urst c ycle (i ntel - type p rocessor ) rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w address of "initial" target register (offset = 0x00) data to be written (offset = 0x00) ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 48 2.2.2.2.1.2.2 the subsequent write operations the procedure that the c/p must use to perform the remaining write cycles, within this burst access operation, is presented below. b.0 execute each subsequent write cycle, as described in steps b.1 through b.3. b.1 without toggling the ale_as input pin (e.g., keeping it "low"), apply the value of the next byte or word (to be written into the framer) to the bi-directional data bus pins, d[7:0]. b.2 toggle the wr _r/w (write strobe) input pin "low". this step accomplishes two things. a. it enables the input drivers of the bi-directional data bus. b. it causes the framer to internally increment the value of the latched address. b.3 after waiting the appropriate amount of settling time the data, in the internal data bus, will stabi- lize and is ready to be latched into the framer microprocessor interface block. at this point, the c/p should latch the data into the framer by toggling the wr _r/w input pin "high". for subsequent write operations, within this burst i/o access, the c/p simply repeats steps b.1 through b.3, as illustrated in figure 32. 2.2.2.2.1.2.3 terminating the burst i/o access burst access operation will be terminated upon the rising edge of the ale_as input signal. at this point the framer will cease to internally increment the latched address value. further, the c/p is now free to execute either a programmed i/o access or to start another burst access operation with the XRT72L50 ds3/e3 framer. 2.2.2.2.2 burst i/o access in the motorola mode if the XRT72L50 ds3/e3 framer is interfaced to a motorola-type c/p (e.g., the mc680x0 family, etc.), then it should be configured to operate in the motoro- la mode (by tying the moto pin to vcc). motorola- type read and write burst i/o access operations are described below. 2.2.2.2.2.1 the motorola-mode read burst i/o access operation whenever a motorola-type c/p wishes to read the contents of numerous registers or buffer locations over a contiguous range of addresses, then it should do the following. a. perform the initial read operation of the burst access. b. perform the remaining read operations in the burst access. c. terminate the burst access operation. each of these operations, within the burst access are discussed below. 2.2.2.2.2.1.1 the initial read operation the initial read operation of a motorola-type read burst access is accomplished by executing a pro- grammed i/o read cycle, as summarized below. a.0 execute a single ordinary (programmed i/ o) read cycle, as described in steps a.1 through a.8 below. f igure 32. b ehavior of the m icroprocessor i nterface s ignals , during subsequent w rite o perations within the b urst i/o c ycle rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w address of "initial" target register (offset = 0x00) data written at offset = 0x01 data written at offset = 0x02 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 49 a.1 assert the ale_as (as*) input pin by toggling it "low". this step enables the address bus input drivers (within the XRT72L50 ds3/e3 framer) within the framer microprocessor interface block. a.2 place the address of the initial target register or buffer location (within the framer), on the address bus input pins, a[10:0]. a.3 at the same time, the address-decoding cir- cuitry (within the user's system) should assert the cs (chip select) input pins of the framer by toggling it "low". this action enables further communication between the c/p and the framer microprocessor interface block. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate address setup time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the address bus into its internal circuitry. at this point, the initial address of the burst access has now been selected. a.5 further, the c/p should indicate that this cycle is a read cycle by setting the wr _r/w (r/w*) input pin "high". a.6 next the c/p should initiate the current bus cycle by toggling the rd _ds (data strobe) input pin "low". this step will enable the bi- directional data bus output drivers, within the XRT72L50 ds3/e3 framer device. at this point, the bi-directional data bus output drivers will proceed to driver the contents of the address register onto the bi-directional data bus. a.7 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the XRT72L50 ds3/e3 framer will indicate that this data can be read by asserting the rdy _dtck (dtack) signal. a.8 after the c/p detects the rdy _dtck signal (from the XRT72L50 ds3/e3 framer) it will ter- minate the read cycle by toggling the rd _ds (data strobe) input pin "high". figure 33 presents an illustration of the behavior of the microprocessor interface signals during the initial read operation, within a burst i/o cycle, for a motor- ola-type c/p. at the completion of this initial read cycle, the c/p has read in the contents of the first register or buffer location (within the XRT72L50 ds3/e3 framer) for this particular burst access operation. in order to il- lustrate how this burst i/o cycle works, the byte (or word) of data, that is being read in figure 33 has been labeled valid data at offset = 0x00. this indi- cates that the c/p is reading the very first register (or buffer location) in this burst access. 2.2.2.2.2.1.2 the subsequent read operations the procedure that the c/p must use to perform the remaining read cycles, within this burst access operation, is presented below. f igure 33. b ehavior of the m icroprocessor i nterface s ignals , during the i nitial r ead o peration of a b urst c ycle (m otorola t ype p rocessor ) ale_as a(8:0) cs d(7:0) rd_ds wr_r/w rdy_dtck not valid address of "initial" target register (offset = 0x00) valid data at offset = 0x00 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 50 b.0 execute each subsequent read cycle, as described in steps b.1 through b.3, below. b.1 without toggling the ale_as input pin (e.g., keeping it "high"), toggle the rd _ds (data strobe) input pin "low". this step accom- plishes the following. a. the framer internally increments the latched address value (within the microprocessor inter- face circuitry). b. the output drivers of the bi-directional data bus (d[7:0]) are enabled. at some time later, the reg- ister or buffer location corresponding to the incre- mented latched address value will be driven onto the bi-directional data bus. n ote : in order to insure that the XRT72L50 ds3/e3 framer device will interpret this signal as being a read sig- nal, the c/p should keep the wr _r/w input pin "high". b.2 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the XRT72L50 ds3/e3 framer will indicate that this data is ready to be read by asserting the rdy _dtck (dtack*) signal. b.3 after the c/p detects the rdy _dtck signal (from the XRT72L50 ds3/e3 framer), it termi- nates the read cycle by toggling the rd _ds (data strobe) input pin "high". for subsequent read operations, within this burst cy- cle, the c/p simply repeats steps b.1 through b.3, as illustrated in figure 34. 2.2.2.2.2.1.3 terminating the burst access operation the burst i/o access will be terminated upon the fall- ing edge of the ale_as input signal. at this point the framer will cease to internally increment the latched address value. further, the c/p is now free to exe- cute either a programmed i/o access or to start an- other burst access operation with the XRT72L50 ds3/e3 framer. 2.2.2.2.2.2 the motorola-mode write burst access whenever a motorola-type c/p wishes to write the contents of numerous registers or buffer locations over a contiguous range of addresses, then it should do the following. a. perform the initial write operation of the burst access. b. perform the remaining write operations, of the burst access. c. terminate the burst access operation. each of these operations within the burst access are described below. 2.2.2.2.2.2.1 the initial write operation the initial write operation of a motorola-type write burst access is accomplished by executing a pro- grammed i/o write cycle as summarized below. a.0 execute a single ordinary (programmed i/ o) write cycle, as described in steps a.1 through a.7 below. f igure 34. b ehavior the m icroprocessor i nterface s ignals , during subsequent r ead o perations within the b urst i/o c ycle (m otorola - type c/p) rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w not valid address of "initial" target register (offset = 0x00) valid data at offset = 0x01 not valid valid data at offset = 0x02 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 51 a.1 assert the ale_as (address strobe) input pin by toggling it "low". this step enables the address bus input drivers (within the XRT72L50 ds3/e3 framer). a.2 place the address of the initial target register or buffer location (within the framer), on the address bus input pins, a[10:0]. a.3 at the same time, the address-decoding cir- cuitry (within the user's system) should assert the cs input pin of the framer by toggling it "low". this step enables further communica- tion between the c/p and the framer micro- processor interface block. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate address setup time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the address bus into its own circuitry. at this point, the initial address of the burst access has now been selected. a.5 further, the c/p should indicate that this cur- rent bus cycle is a write operation by toggling the wr _r/w (r/w ) input pin "low". a.6 the c/p should then place the byte or word that it intends to write into the target register, on the bi-directional data bus, d[7:0]. a.7 next, the c/p should initiate the bus cycle by toggling the rd _ds (data strobe) input pin "low". when the XRT72L50 ds3/e3 framer device senses that the wr _r/w input pin is "low", and that the rd _ds input pin has tog- gled "low" it will enable the input drivers of the bi-directional data bus, d[7:0]. a.8 after waiting the appropriate amount of time, for this newly placed data to settle on the bi-direc- tional data bus (e.g., the data setup time) the framer will assert the rdy _dtck (dtack) output signal. a.9 after the p/c detects the rdy _dtck signal (from the framer) it should toggle the rd _ds input pin "high". this action accomplishes two things: a. it latches the contents of the bi-directional data bus into the XRT72L50 ds3/e3 framer micropro- cessor interface block. b. it terminates the write cycle. figure 35 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during the initial write operation within a burst ac- cess, for a motorola-type c/p. at the completion of this initial write cycle, the c/p has written a byte or word into the first register or buffer location (within the XRT72L50 ds3/e3 framer) for this particular burst i/o access. in order to illus- trate how this burst i/o cycle works, the byte (or word) of data, that is being written in figure 35 has been la- beled data to be written (offset = 0x00). 2.2.2.2.2.2.2 the subsequent write operations f igure 35. b ehavior of the m icroprocessor i nterface signals , during the i nitial w rite o peration of a b urst c ycle (m otorola - type p rocessor ) rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w data to be written (offset = 0x00) address of "initial" target register (offset = 0x00) ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 52 the procedure that the c/p must use to perform the remaining write cycles, within this burst access operation, is presented below. b.0 execute each subsequent write cycle, as described in steps b.1 through b.3 b.1 without toggling the ale_as (address strobe) input pin (e.g., keeping it "high"), apply the value of the next byte or word (to be written into the framer) to the bi-directional data bus pins, d[7:0]. b.2 toggle the rd _ds (data strobe) input pin "low". this step accomplishes the following. a. the framer internally increments the latched address value (within the microprocessor inter- face). b. the input drivers of the bi-directional data bus are enabled. n ote : in order to insure that the XRT72L50 ds3/e3 framer device will interpret this signal as being a write sig- nal, the c/p should keep the wr _r/w input pin "low". b.3 after some settling time, the data, in the inter- nal data bus, will stabilize and is ready to be latched into the framer microprocessor inter- face block. the microprocessor interface block will indicate that this data is ready to be latched by asserting the rdy _dtck (dtack) output signal. at this point, the c/p should latch the data into the framer by toggling the rd _ds input pin "high". for subsequent write operations, within this burst i/o access, the c/p simply repeats steps b.1 through b.3 as illustrated in figure 36. 2.2.2.2.2.2.3 terminating the burst i/o access the burst i/o access will be terminated upon the fall- ing edge of the ale_as input signal. at this point the framer will cease to internally increment the latched address value. further, the c/p is now free to exe- cute either a programmed i/o access or to start an- other burst i/o access with the XRT72L50 ds3/e3 framer. 2.3 o n -c hip r egister o rganization the microprocessor interface section, within the framer device allows the user to do the following. ? configure the framer into a wide variety of operat- ing modes. ? employ various features of the framer device. ? perform status monitoring ? enable/disable and service interrupt conditions all of these things are accomplished by reading from and writing to the many on-chip registers within the framer device. table 4 lists each of these registers and their corresponding address locations within the framer address space. 2.3.1 framer register addressing the array of on-chip registers consists of a variety of register types. these registers are denoted in table 4, as follows. r/o - read only registers. r/w - read/write registers rur - reset-upon-read registers f igure 36. b ehavior of the m icroprocessor i nterface s ignals , during subsequent w rite o perations with the b urst i/o c ycle (m otorola - type c/p) rdy_dtck ale_as a(8:0) cs d(7:0) rd_ds wr_r/w address of "initial" target register (offset = 0x00) data written at offset = 0x01 data written at offset = 0x02 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 53 additionally, some of these registers consists of both r/o and r/w bit-fields. these registers are denoted in table 4 as combination of r/w and r/o. the bit-format and definitions for each of these regis- ters are presented in section 3.3.2 t able 4: r egister a ddressing of the f ramer p rogrammer r egisters a ddress r egister n ame p ower u p d efault v alue r egister type 0x00 operating mode register b00100011 r/w 0x01 i/o control register b10100000 r/w, r/o 0x02 part number register b00000001 r/o 0x03 version number register b00000011 r/o 0x04 block interrupt enable register b00000000 r/w 0x05 block interrupt status register b00000000 r/o 0x06-0x0b reserved 0x0c test register b00000000 r/w, r/o 0x0d-0x0f reserved 0x10 rxds3 configuration & status register rxe3 configuration & status register 1 - g.832 rxe3 configuration & status register 1 - g.751 b00010000 b00000010 b00000010 r/w, r/o 0x11 rxds3 status register rxe3 configuration & status register 2 - g.832 rxe3 configuration & status register 2 - g.751 b00000000 b01100111 b01100111 r/w, r/o 0x12 rxds3 interrupt enable register rxe3 interrupt enable registers -1 g.832 rxe3 interrupt enable registers - 1 g.751 b00000000 b00000000 b00000000 r/w, r/o 0x13 rxds3 interrupt status register rxe3 interrupt enable register -2 g.832 rxe3 interrupt enable register - 2 g.751 b00000000 b00000000 b00000000 r/w, r/o 0x14 rxds3 sync detect enable register rxe3 interrupt status register 1 - g.832 rxe3 interrupt status register 1 - g.751 b00011111 b00000000 b00000000 rur, r/o 0x15 rxe3 interrupt status register 2 - g.832 rxe3 interrupt status register 2 - g.751 b00000000 b00000000 rur, r/o 0x16 rxds3 feac register b01111110 r/o 0x17 rxds3 feac interrupt enable/status register b00000000 r/o 0x18 rxds3 lapd control register rxe3 lapd control register b00000000 r/w, rur 0x19 rxds3 lapd status register rxe3 lapd status register b00000000 b00000000 r/o 0x1a rxe3 nr byte register - g.832 rxe3 service bit register g.751 b00000000 b00000000 r/o 0x1b rxe3 gc byte register - g.832 b00000000 r/o 0x1c rxe3 ttb-0 register - g.832 b00000000 r/o ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 54 0x1d rxe3 ttb-1 register - g.832 b00000000 r/o 0x1e rxe3 ttb-2 register - g.832 b00000000 r/o 0x1f rxe3 ttb-3 register - g.832 b00000000 r/o 0x20 rxe3 ttb-4 register - g.832 b00000000 r/o 0x21 rxe3 ttb-5 register - g.832 b00000000 r/o 0x22 rxe3 ttb-6 register - g.832 b00000000 r/o 0x23 rxe3 ttb-7 register - g.832 b00000000 r/o 0x24 rxe3 ttb-8 register - g.832 b00000000 r/o 0x25 rxe3 ttb-9 register - g.832 b00000000 r/o 0x26 rxe3 ttb-10 register - g.832 b00000000 r/o 0x27 rxe3 ttb-11 register - g.832 b00000000 r/o 0x28 rxe3 ttb-12 register - g.832 b00000000 r/o 0x29 rxe3 ttb-13 register - g.832 b00000000 r/o 0x2a rxe3 ttb-14 register - g.832 b00000000 r/o 0x2b rxe3 ttb-15 register - g.832 b00000000 r/o 0x2c rxssm register - g.832 b0xxx0000 r/w, r/o 0x2c - 0x2f reserved b00000000 r/o 0x30 txds3 configuration register txe3 configuration register - g.832 txe3 configuration register - g.751 b00000111 b00000000 b00000000 r/w 0x31 txds3 feac configuration and status register b00000000 r/o, r/w, rur 0x32 txds3 feac register b01111110 r/w 0x33 txds3 lapd configuration register txe3 lapd configuration register b00000000 b00000000 r/w 0x34 txds3 lapd status/interrupt register txe3 lapd status/interrupt register b00000000 b00000000 r/w, r/o, rur 0x35 txds3 m-bit mask register txe3 gc byte register - g.832 txe3 service bits register - g.751 b00000000 b00000000 b00000000 r/w 0x36 txds3 f-bit mask register 1 txe3 ma byte register - g.832 b00000000 b00000000 r/w 0x37 txds3 f-bit mask register 2 txe3 nr byte register - g.832 b00000000 b00000000 r/w 0x38 txds3 f-bit mask register 3 txe3 ttb-0 register - g.832 b00000000 b00000000 r/w t able 4: r egister a ddressing of the f ramer p rogrammer r egisters a ddress r egister n ame p ower u p d efault v alue r egister type XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 55 0x39 txds3 f-bit mask register 4 txe3 ttb-1 register - g.832 b00000000 b00000000 r/w 0x3a txe3 ttb-2 register - g.832 b00000000 r/w 0x3b txe3 ttb-3 register - g.832 b00000000 r/w 0x3c txe3 ttb-4 register - g.832 b00000000 r/w 0x3d txe3 ttb-5 register - g.832 b00000000 r/w 0x3e txe3 ttb-6 register - g.832 b00000000 r/w 0x3f txe3 ttb-7 register - g.832 b00000000 r/w 0x40 txe3 ttb-8 register - g.832 b00000000 r/w 0x41 txe3 ttb-9 register - g.832 b00000000 r/w 0x42 txe3 ttb-10 register - g.832 b00000000 r/w 0x43 txe3 ttb-11 register - g.832 b00000000 r/w 0x44 txe3 ttb-12 register - g.832 b00000000 r/w 0x45 txe3 ttb-13 register - g.832 b00000000 r/w 0x46 txe3 ttb-14 register - g.832 b00000000 r/w 0x47 txe3 ttb-15 register - g.832 b00000000 r/w 0x48 txe3 fa1 error mask register - g.832 txe3 fas error mask upper register - g.751 b00000000 b00000000 r/w 0x49 txe3 fa2 error mask register - g.832 txe3 fas error mask lower register - g.751 b00000000 b00000000 r/w 0x4a txe3 bip-8 mask register - g.832 txe3 bip-4 mask register - g.751 b00000000 b00000000 r/w 0x4b txssm register - g.832 b0xxx0000 r/w 0x4c-0x4f reserved 0x50 pmon lcv event count register - msb b00000000 rur 0x51 pmon lcv event count register - lsb b00000000 rur 0x52 pmon framing bit error event count register - msb b00000000 rur 0x53 pmon framing bit error event count register - lsb b00000000 rur 0x54 pmon parity error event count register - msb b00000000 rur 0x55 pmon parity error event count register - lsb b00000000 rur 0x56 pmon febe event count register - msb b00000000 rur 0x57 pmon febe event count register - lsb b00000000 rur 0x58 pmon cp bit error event count register - msb b00000000 rur 0x59 pmon cp bit error event count register - lsb b00000000 rur t able 4: r egister a ddressing of the f ramer p rogrammer r egisters a ddress r egister n ame p ower u p d efault v alue r egister type ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 56 2.3.2 framer register description this section provides a function description of each bit-field within each of the on-chip framer registers. n ote : for all on-chip registers, a table containing the bit- format of the register is presented. additionally, these tables also contain the default values for each of these reg- ister bits. finally, the functional description, associated with each register bit-field is presented, along with a reference to a section number, within this data sheet, that provides a more in-depth discussion of the functions associated with this register bit-field. 2.3.2.1 framer operating mode register 0x5a - 0x67 reserved b00000000 r/o 0x68 prbs bit error counter - msb b00000000 rur 0x69 prbs bit error counter - lsb b00000000 rur 0x6a-0x6b reserved b00000000 r/o 0x6c pmon holding register b00000000 rur 0x6d one-second error status register b00000000 r/o 0x6e lcv one-second accumulator register - msb b00000000 r/o 0x6f lcv one-second accumulator register - lsb b00000000 r/o 0x70 frame parity error one-second accumulator register - msb (bip-8 in g.832) b00000000 r/o 0x71 frame parity error one-second accumulator register - lsb (bip-8 in g.832) b00000000 r/o 0x72 frame cp bit error - one-second accumulator register - msb b00000000 r/o 0x73 frame cp bit error - one-second accumulator register - lsb b00000000 r/o 0x74 - 0x7f reserved 0x80 line interface drive register b00001000 r/w 0x81 line interface scan register b00000000 r/o 0x82 hdlc control register b00000000 r/w 0x83 - 0x85 reserved 0x86 - 0xdd transmit lapd message buffer (ram) bxxxxxxx r/w 0xde - 0x135 receive lapd message buffer (ram) bxxxxxxx r/w t able 4: r egister a ddressing of the f ramer p rogrammer r egisters a ddress r egister n ame p ower u p d efault v alue r egister type framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 011 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 57 bit 7 - local loopback mode this read/write bit-field permits the user to com- mand the framer chip to operate in the local loop- back mode. setting this bit-field to "0", configures the framer chip to operate in the normal mode. setting this bit-field to "1", configures the framer chip to operate in the local-loopback mode. n ote : for a detailed description of the local loopback mode, please see section 6.0 bit 6 - ds3/e3* select this read/write bit-field permits the user to com- mand the framer chip to operate in either the ds3 mode or the e3 mode. setting this bit-field to "0", configures the framer chip to operate in the e3 mode. setting this bit-field to "1", configures the framer chip to operate in the ds3 mode. bit 5 - internal los enable select this read/write bit-field permits the user to configure the framer chip to either declare an los condition, based upon the internal circuit's criteria or not. setting this bit-field to "0", configures the framer chip to not declare an los condition, based upon its own internal criteria. setting this bit-field to "1", configures the framer chip to declare an los condition based upon its own inter- nal criteria. n otes : 1. the XRT72L50 framer chip will declare an los condition, anytime the rlos input pin (pin 78) is set "high", independent of the setting of this bit- field. 2. for more information on the XRT72L50 framer device's internal criteria for loss of signal please see section 3.3.2.5. bit 4 - reset: this read/write bit-field permits the user to com- mand the XRT72L50 framer chip into the reset state. if the XRT72L50 framer chip is commanded into the reset state, all of its internal register bits will automatically be set to their default condition. setting this bit-field to "0" configures the XRT72L50 framer chip to operate normally. setting this bit-field to "1" configures the XRT72L50 framer chip to go in- to the reset mode. bit 3 - interrupt enable reset this read/write bit-field permits the user to configure the XRT72L50 framer chip to automatically disable all interrupts that are activated. setting this bit-field to "0" configures the XRT72L50 framer chip to not disable the interrupt enable sta- tus, of any interrupts, following their activation. setting this bit to "1" configures the XRT72L50 fram- er chip to automatically disable any interrupt that is activated. n ote : for more information on this feature, please see section 1.6.1. bit 2 - frame format select this read/write bit-field, along with the ds3/e3 se- lect bit-field (bit 6 in this register) permits the user to select the framing format that the XRT72L50 will op- erate in. the following table relates the states of this bit-field (bit 2) and that of bit 6 to the selected framing format for this chip. bits 1 & 0 - timrefsel[1:0] - timing reference se- lect these two read/write bit-fields permits the user to select both a framing reference and timing refer- ence for the transmit section of the XRT72L50. the following table relates the states of these two bit- fields to the selected framing and timing references. n ote : for more information on framing and timing refer- ences, please see section 3.2. b it 6 - ds3/e3 s elect b it 2 - f rame f ormat s elect s elected f raming f ormat 0 0 e3, itu-t g.751 0 1 e3, itu-t g.832 1 0 ds3, c-bit parity 11ds3, m13 t im r ef s el [1:0] f raming r eference t iming r eference 00 asynchronous rxlineclk input signal 01 txframeref txinclk input sig- nal 10 asynchronous txinclk input sig- nal 11 asynchronous txinclk input sig- nal ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 58 2.3.2.2 i/o control register bit 7 - disabletxloc this read/write bit-field permits the user to enable or disable the transmit loss of clock feature. setting this bit-field to "0" enables the transmit loss of clock feature. conversely, setting this bit-field to "1" disables the transmit loss of clock feature. n ote : for more details into the transmit loss of clock fea- ture, please see section 1.4. bit 6 - loc (loss of clock) status this read-only bit-field reflects the loss of clock status for the XRT72L50. the XRT72L50 will set this bit-field to "0" under normal operation conditions. conversely, if the XRT72L50 has experiences a loss of clock event, then it will set this bit-field to "1". n ote : for more details into the loss of clock status, please see section 1.4. bit 5 - disablerxloc this read/write bit-field permits the user to enable or disable the receive loss of clock feature. setting this bit-field to "0" enables the receive loss of clock feature. conversely, setting this bit-field to "1" disables the receive loss of clock feature. n ote : for more details into the receive loss of clock fea- ture, please see section 1.4. bit 4 - ami/zerosup* this read/write bit-field permits the user to configure the XRT72L50 to transmit and receive data via the ami (alternate mark inversion) line code or via a ze- ro-suppression (e.g, b3zs/hdb3) line code. setting this bit-field to "0" configures the XRT72L50 to transmit and receive data via a zero-suppression line code. setting this bit-field to "1" configures the XRT72L50 to transmit and receive data via the alternate mark in- version line code. n otes : 1. if the XRT72L50 is configured to transmit and receive data, using a zero-suppression code, while operating in the ds3 mode, then the chip will trans- mit and receive data using the b3zs line code. 2. if the XRT72L50 is configured to transmit and receive data, using a zero-suppression code, while operating in the e3 mode, then the chip will trans- mit and receive data using the hdb3 line code. 3. this bit-field will be ignored if bit 3 (unipolar/bipo- lar*) of this register is set to "1" (for unipolar mode). bit 3 - unipolar/bipolar* this read/write bit-field permits the user to configure the XRT72L50 to transmit data to and receive data from an liu ic, in either the single-rail or dual-rail format. setting this bit-field to "0" configures the XRT72L50 to operate in the bipolar or dual-rail format. in this mode, the transmit section of the XRT72L50 will out- put data to the liu via both the txpos and txneg output pins. additionally, the receive section of the device will receive data from the liu via both the rx- pos and rxneg output pins. setting this bit-field to "1" configures the XRT72L50 to operate in the unipolar or single-rail format. in this mode, the transmit section of the XRT72L50 will out- put data to the liu, in a binary data stream manner via the txpos output pin. additionally, the receive section of the device will receive data from the liu, in a binary data stream manner, via the rxpos input pin. n ote : for more information on the transmission and reception of data in the single-rail or dual-rail format, please see section 3.2.5. bit 2 - txlineclk invert this read/write bit-field permits the user to configure the XRT72L50 to output data, via the txpos and tx- neg output pins, on the rising or falling edge of txli- neclk. setting this bit-field to "0" configures the XRT72L50 to output data, via the txpos and txneg output pins, on the rising edge of txlineclk. i/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/ zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 10100000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 59 setting this bit-field to "1" configures the XRT72L50 to output data, via the txpos and txneg output pins, on the falling edge of txlineclk. bit 1 - rxlineclk invert this read/write bit-field permits the user to configure the XRT72L50 to latch data on the rxpos and rx- neg input pins, into the XRT72L50, on the rising or falling edge of rxlineclk. setting this bit-field to "0" configures the XRT72L50 to latch the data on the rxpos and rxneg input pins, into the device, on the rising edge of rxlineclk. setting this bit-field to "1" configures the XRT72L50 to latch the data on the rxpos and rxneg input pins, into the device, data, on the falling edge of rxlineclk. bit 0 - reframe this read/write bit-field permits the user to configure the receive section of the XRT72L50 to start a new frame search. a "0" to "1" transition, in this bit-field will force the chip to start a new frame search. 2.3.2.3 part number register the part number register can be used by system- level software to identify this particular device as the XRT72L50 3-channel ds3/e3 framer ic. the value of the part number register, within this device is 0x09. 2.3.2.4 version number register the version number register permits the users software to identify the revision number of the part. the very first revision of the part will contain the value 0x01. 2.3.2.5 block interrupt enable register bit 7 - rxds3/e3 interrupt enable this read/write bit-field permits the user to enable or disable all receive section related interrupts (within the XRT72L50), at the block level. setting this bit-field to "0" disables all receive section related interrupts within the XRT72L50. setting this bit-field to "1" enables the receive sec- tion related interrupts (within the XRT72L50) at the block level. n ote : setting this bit-field to "1" does not enable all receive section related interrupts. each of these interrupts can still be disabled at the source level. however, setting part number register (address = 0x02) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 part number value ro ro ro ro ro ro ro ro 00001001 version number register (address = 0x03) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 version number value ro ro ro ro ro ro ro ro 00000001 block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one-second interrupt enable r/wrororororor/wr/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 60 this bit-field to "0" does disable all receive section related interrupts. bit 1 - txds3/e3 interrupt enable this read/write bit-field permits the user to enable or disable all transmit section related interrupts (within the XRT72L50), at the block level. setting this bit-field to "0" disables all transmit sec- tion related interrupts within the XRT72L50. setting this bit-field to "1" enables the transmit sec- tion related interrupts (within the XRT72L50) at the block level. n ote : setting this bit-field to "1" does not enable all trans- mit section related interrupts. each of these interrupts can still be disabled at the source level. however, setting this bit-field to "0" does disable all transmit section related interrupts. bit 0 - one-second interrupt enable this read/write bit-field permits the user to enable or disable the one-second interrupt, within the XRT72L50. if this interrupt is enabled, then the XRT72L50 will generate interrupts to the c/p at one-second intervals. setting this bit-field to "0" disables the one-second interrupt. conversely, setting this bit-field to "1" en- ables the one-second interrupt. 2.3.2.6 block interrupt status register bit 7 - rxds3/e3 interrupt status indicator this read-only bit-field indicates whether or not a receive-section related interrupt has been requested and is awaiting service. if this bit-field is set to "0", then there are no receive- section related interrupts awaiting service. con- versely, if this bit-field is set to "1", then there is at least one receive section related interrupt, awaiting service. n ote : if this bit-field is set to "1", then the c/p must read the source-level interrupt status register, in order to clear this bit-field. bit 1 - txds3/e3 interrupt status indicator this read-only bit-field indicates whether or not a transmit-section related interrupt has been request- ed and is awaiting service. if this bit-field is set to "0", then there are no transmit- section related interrupts awaiting service. con- versely, if this bit-field is set to "1", then there is at least one transmit section related interrupt, awaiting service. n ote : if this bit-field is set to "1", then the c/p must read the source-level interrupt status register, in order to clear this bit-field. bit 0 - one-second interrupt status this reset-upon-read bit field indicates whether or not a one-second interrupt has been requested and is awaiting service. if this bit-field is set to "0", then the one-second inter- rupt is not awaiting service. conversely, if this bit- field is set to "1", then the one-second interrupt is awaiting service. n ote : this bit-field will be cleared immediately after the c/p has read this register. block interrupt status register (address = 0x05) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt status not used txds3/e3 interrupt status one-second interrupt status ro ro ro ro ro ro ro rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 61 2.3.2.7 test register bit 7 - txoh source select this read/write bit-field permits the user to configure the transmit section of the channel to accept over- head bits/bytes via the txser[n]or txnib[3:0][n] input pins. setting this bit-field to 1 configures the transmit section of the channel to accept overhead bits/bytes via either the txser[n] or txnib[3:0][n]input pins. setting this bit-field to 0 configures the transmit section of the channel to either internally generate or accept the overhead bits/bytes via the txoh[n] input pin. bit 6 - rx payload clock enable this read/writebit-field permits the user to configure the receive payload data output interface block to output the receive data in a gapped-clockmanner. if the user chooses this option, then the receive pay- load data output interface will only generate a clock edge (via the rxclk[n] output pin) whenever a pay- load bit is being output via the rxser[n] output pin. the receive payload data output interface will not generate a clock edge (via the rxclk[n] output pin) whenever an overhead bit is being output via the rx- ser[n]output pin. if the user does not select this option then the re- ceive payload data output interface block will gener- ate a clock edge for all bits (payload and overhead); as they are output via the rxser[n] output pin. how- ever, the receive payload data output interface will also pulse the rxohind[n] output pin high each time an overhead bit is being output via the rxser[n] output pin. setting this bit-field to 1 enables this feature. set- ting this bit-field to 0 disables this feature. bit 5 - tx payload clock enable this read/write bit-field permits the user to configure the txohind[n] output pin to function as either of the following roles. 1. the transmit overhead data output indicator 2. the transmit payload data clock output signal. if the txohind[n] output pin is configured to function as the transmit overhead data output signal, then this output pin will pulse high one bit-period prior to the instant that the transmit section of the channel (within the XRT72L50 device) is processing an over- head bit. if the txohind[n] output pin is configured to function as the transmit payload data clock output signal, then the transmit payload data output interface block will generate a clock edge via the txohind[n] output pin. the local terminal equipment is expect- ed to output outbound payload data to the transmit payload data input interface block (via the txser[n] input pin) upon the falling edge of this clock signal. n ote : in this mode, the txohind_n output pin will not gen- erate a clock edge, whenever the transmit section of the XRT72L50 device is about to process an overhead bit. setting this bit-field to 0 configures the txohind[n] output pin to function as the transmit overhead data output signal. setting this bit-field to 1 configures the txohind[n] output pin to function as the transmit payload data clock output signal. bit 4 - rx prbs lock this read-only bit-field indicates whether or not the prbs receiver has acquired prbs lock (or pattern sync) with the data generated by the prbs genera- tor. if this bit-field is set to 1, then the prbs receiver has acquired prbs lock with the data generated by the prbs generator. if this bit-field is set to 0, then the prbs receiver has not acquired prbs lock with the data generated by the prbs generator. n ote : this bit-field is only valid if both the rxprbs enable and tx prbs enable bit-fields are both set to 1. bit 3 - rx prbs enable this read/write bit-field permits the user to enable the prbs receiver within the channel. test register (address = 0x0c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txoh source select rx payload clock enable tx payload clock enable rx prbs lock rx prbs enable tx prbs enable reserved r/w r/w r/w ro r/w r/w ro rur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 62 setting this bit-field to 1 enables the prbs receiver within the channel. setting this bit-field to 0 disables the prbs receiver. bit 2 - tx prbs enable this read/write bit-field permits the user to enable the prbs generator within the channel. setting this bit-field to 1 enables the prbs genera- tor within the channel. setting this bit-field to 0 dis- ables the prbs generator. receive ds3 framer configuration registers 2.3.2.8 receive ds3 configuration & status register bit 7 - rxais (receive ais pattern) indicator this read-only bit-field indicates whether or not the receive section of the channel, within the XRT72L50 is currently receiving an ais pattern or not. the channel will set this bit-field to "0" if it is not cur- rently detecting an ais pattern in the incoming data stream. conversely, the channel will set this bit-field to "1" if it is currently receiving an ais pattern in the incoming data stream. n ote : for a more detailed discussion on the ais pattern for ds3 applications, please see section 3.3.2.5.2 bit 6 - rxlos (receive los condition) indicator this read-only bit-field indicates whether or not the receive section of the channel (within the framer de- vice) is currently declaring an los (loss of signal) condition of the incoming ds3 or e3 data stream. if this bit-field is set to "0", then the receive section (of the channel) is currently not declaring an los condition. if this bit-field is set to "1", then the receive section (of the channel) is currently declaring an los condi- tion. n ote : for more information on the los declaration crite- ria, for ds3 and e3 applications, please see section 3.3.2.5.2. bit 5 - rxidle (receive idle pattern) indicator this read-only bit-field indicates whether or not the receive section of the channel (within the framer de- vice) is currently detecting the idle-pattern in the in- coming ds3 data stream. if this bit-field is set to "0" then the receive section (of the channel) is currently not detecting the idle-pat- tern in the incoming ds3 data stream. if this bit-field is set to "1" then the receive section (of the channel) is currently detecting the idle pattern in the incoming ds3 data stream. n otes : 1. this bit-field is only relevant for ds3 applications. 2. for more information on the idle pattern, please see section 3.3.2.5.3 bit 4 - rxoof (receive out-of-frame) indicator this read-only bit-field indicates whether or not the receive section of the channel (within the framer de- vice) is currently declaring an oof (out of frame) condition. if this bit-field is set to "0", then the receive section (of the channel) is currently not declaring the oof condition. if this bit-field is set to "1", then the receive section (of the chip) is currently declaring the oof condition. n ote : for more information on the oof declaration crite- ria, for ds3 applications, please see section 3.3.2.2. bit 3 - reserved. bit 2 - framing on parity on/off select this read/write bit field allows the user to require that the receive ds3/e3 framer block (within the channel) include parity (p-bit) verification as a condi- tion for declaring itself in-frame, during frame acqui- sition. this requirement will be imposed in addition to those criteria selected via bits 0 and 1 of this register. this feature also imposes an additional frame main- tenance requirement on the receive ds3/e3 framer block, in addition to the requirements specified in the user's selection of bits 0 and 1 of this register. in par- ticular, if this additional requirement is implemented, the receive ds3/e3 framer block will perform a frame search if it detects p-bit errors in at least 2 out of 5 ds3 frames. writing a "1" to this bit-field impos- rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 63 es these additional requirements. whereas, writing a '0' causes the receive ds3/e3 framer block to waive this requirement. n ote : for more information on framing with parity please see section 3.3.2.2. bit 1 - f sync algo(rithim select) this 'read/write' bit-field, in conjunction with bits 0 and 2 of this register, allows the user to completely define the frame maintenance criteria of the receive ds3/e3 framer block. this particular bit-field allows the user to define the frame maintenance criteria as it applies to f-bits. if the user writes a "1" to this bit-field, then the re- ceive ds3/e3 framer block will declare an out of frame (oof) condition if 3 out of 16 f-bits are in er- ror. if the user writes a "0" to this bit-field, then the receive ds3/e3 framer block will declare an out of frame (oof) condition is 6 out of 16 f-bits are in er- ror. n ote : for more information on the use of this bit, and the framing maintenance operation of the receive ds3/e3 framer block, please see section 3.3.2.2. bit 0 - m sync algo(rithm select) this 'read/write' bit-field in conjunction with bits 1 and 2 of this register, allows the user to completely define the frame maintenance criteria of the receive ds3/e3 framer block. this particular bit-field allows the user to define the frame maintenance criteria, as it applies to m-bits. if the user writes a "1" to this bit-field, then the re- ceive ds3/e3 framer block will declare an out of frame (oof) condition if 3 out of 4 m-bits are in error. if the user writes a "0" to this bit-field, then the re- ceive ds3/e3 framer block will ignore the occurrence of m-bit errors while operating in the frame mainte- nance mode. n ote : for more information on the use of this bit-field, and the framing maintenance operation of the receive ds3/e3 framer block, please see section 3.3.2.2. 2.3.2.9 receive ds3 status register bit 4 - rxferf indicator this read only bit-field indicates whether or not the receive section of the channel is declaring a ferf (far-end-receive failure) condition. if this bit-field is set to "0", then the receive section (of the channel) is currently not declaring an ferf condition. if this bit-field is set to "1", then the receive section (of the chip) is currently declaring an ferf condition. n ote : for more information on how the receive section of the channel declares the ferf condition, please see sec- tion 3.3.2.5.4. bit 3 - rxaic this read only bit-field reflect the value of the aic bit-field, within the incoming ds3 frames, as detect- ed by the receive ds3/e3 framer block (within the channel). this bit-field is set to "1" if the incoming frame is determined to be in the c-bit parity format (aic bit = 1) for at least 63 consecutive frames. this bit-field is set to "0" if two (2) or more m-frames, out of the last 15 m-frames, contain a "0" in the aic bit posi- tion. bits 2:0 - rxfebe[2:0] these read-only bit-fields reflect the febe value, within the most recently received ds3 frame. if these bit-fields are set to "111", then it indicates that the remote receiving terminal is receiving ds3 frames in an un-erred manner. if these bit-fields are set to "011", then it indicates that the remote receiving terminal has detected fram- ing or parity bit errors in the ds3 frames that it is re- ceiving. n ote : for more information on febe (far-end-block error) please see section 3.3.2.5.5. rxds3 status register (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxferf rxaic rxfebe[2:0] ro ro ro ro ro ro ro ro 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 64 2.3.2.10 receive ds3 interrupt enable register bit 7 - cp bit error interrupt enable this read/write bit-field is used to enable or disable the detection of cp-bit error interrupt. setting this bit-field to 1 enables this interrupt. setting this bit- field to 0 disables this interrupt. n otes : 1. for more information on the cp-bit error checking/ detection, please see section 3.3.2.6.2. 2. this bit-field is only valid if the channel has been configured to operate in the ds3, c-bit parity framing format. bit 6 - los interrupt enable this read/write bit-field is used to enable or disable the change in los condition interrupt. setting this bit-field to "1" enables this interrupt. setting this bit- field to "0" disables this interrupt. n ote : for more information on the los condition, please see sections 3.3.2.5.1. bit 5 - ais interrupt enable this read/write bit-field is used to enable or disable the change in ais condition interrupt. setting this bit- field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the ais condition, please see sections 3.3.2.5.2. bit 4 - idle interrupt enable this read/write bit-field is used to enable or disable the change in idle condition interrupt. setting this bit- field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the idle condition, please see section 3.3.2.5.3. bit 3 - ferf interrupt enable this read/write bit-field is used to enable or disable the change in ferf (far end receive failure) sta- tus interrupt. setting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this in- terrupt. n ote : for more information on far-end receive failures (or yellow alarms) please see section 3.3.2.5.4. bit 2 - aic interrupt enable this read/write bit field allows the user to enable or disable the change in aic value interrupt. setting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on this interrupt condition, please see section 3.3.2.5.6. bit 1 - oof interrupt enable this read/write bit field is used to enable or disable the change in out-of-frame (oof) status interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. n ote : for more information on the oof' condition, please see section 3.3.2.2. bit 0 - p-bit error interrupt enable this read/write bit-field is used to enable or disable the detection of p-bit error interrupt. setting this bit- field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the p-bit error checking/ detection, please see section 3.3.2.6.1. rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 65 2.3.2.11 receive ds3 interrupt status register bit 7 - cp bit error interrupt status this reset-upon-read bit-field indicates whether or not the detection of cp bit error interrupt has oc- curred since the last read of this register. this bit- field will be 0 if the detection of cp-bit error inter- rupt has not occurred since the last read of this regis- ter. conversely, this bit-field will be set to 1 if this in- terrupt has occurred since the last read of this regis- ter. the detection of cp bit error interrupt will occur if the receive ds3/e3 framer block detects a cp bit- error in the incoming ds3 frame. n ote : this bit-field is only valid if the channel has been configured to operate in the ds3, c-bit parity framing for- mat. bit 6 - los interrupt status this reset upon read bit will be set to "1", if the re- ceive ds3/e3 framer block has detected a change in the los status condition, since the last time this reg- ister was read. this bit-field will be asserted under ei- ther of the following conditions: for ds3 applications 1. when the receive ds3/e3 framer block detects the occurrence of an los condition (e.g., the occurrence of 180 consecutive spaces in the incoming ds3 data stream), and 2. when the receive ds3/e3 framer block detects the end of an los condition (e.g., when the receive ds3 framer detects 60 mark pulses in the last 180 bit periods). for e3 applications 3. when the receive ds3/e3 framer block detects the occurrence of an los condition (e.g., the occurrence of 32 consecutive spaces in the incoming e3 data stream). 4. when the receive ds3/e3 framer block detects the end of an los condition (e.g., the occur- rence of 32 consecutive bits that does not contain a string of 4 consecutive 0s. the local p can determine the current state of the los condition by reading bit 6 of the rx ds3 config- uration and status register (address = 0x10). n ote : for more information in the los of signal (los) alarm, please see section 3.3.2.5.1. bit 5 - ais interrupt status this reset upon read bit field will be set to "1", if the receive ds3/e3 framer block has detected a change in the ais condition, since the last time this register was read. this bit-field will be asserted un- der either of the following two conditions: 1. when the receive ds3/e3 framer block first detects an ais condition in the incoming ds3 data stream, and 2. when the receive ds3/e3 framer block has detected the end of an ais condition. the local p can determine the current state of the ais condition by reading bit 7 of the rx ds3 configu- ration and status register (address = 0x10). n ote : for more information on the ais condition please see sections 3.3.2.5.2. bit 4 - idle interrupt status this reset upon read bit-field is set to "1" when the receive ds3/e3 framer block detects a change in the idle condition in the incoming ds3 data stream. specifically, the receive ds3/e3 framer block will as- sert this bit-field under either of the following two con- ditions: 1. when the receive ds3/e3 framer block detects the onset of the idle condition and 2. when the receive ds3/e3 framer block detects the end of the idle condition. the local p can determine the current state of the idle condition by reading bit 5 of the rx ds3 configu- ration and status register (address = 0x10). n ote : for more information into the idle condition, please see section 3.3.2.5.3. bit 3 - ferf interrupt status this reset upon read bit will be set to '1' if the re- ceive ds3/e3 framer block has detected a change in rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rurrurrurrurrurrurrurrur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 66 the rx ferf condition, since the last time this regis- ter was read. this bit-field will be asserted under either of the fol- lowing two conditions. 1. when the receive ds3/e3 framer block first detects the occurrence of an rx ferf condition (all x-bits are set to '0'). 2. when the receive ds3/e3 framer block detects the end of the rx ferf condition (all x-bits are set to '0'). the local microprocessor can determine the current state of the ferf condition by reading bit 4, within the rx ds3 status register (address = 0x11). n ote : for more information on the rx ferf (yellow alarm) condition, please see section 3.3.2.5.4. bit 2 - (change in) aic interrupt status this reset upon read bit-field is set to "1" if the aic bit-field, within the incoming ds3 frames, has changed state since the last read of this register. n ote : for more information on this interrupt condition, please see section 3.3.2.5.6. bit 1 - oof interrupt status this reset upon read bit-field is set to "1" if the re- ceive ds3/e3 framer block has detected a change in the out-of-frame (oof) condition, since the last time this register was read. therefore, this bit-field will be asserted under either of the following two conditions: 1. when the receive ds3/e3 framer block has detected the appropriate conditions to declare an oof condition. 2. when the receive ds3/e3 framer block has transitioned from the oof condition (frame acquisition mode) into the in-frame condition (frame maintenance mode). n ote : for more information of the oof condition, please see section 3.3.2.2. XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 67 bit 0 - p-bit error interrupt status this reset upon read bit-field indicates whether or not the detection of p-bit error interrupt has occurred since the last read of this register. this bit-field will be "0" if the detection of p-bit error interrupt has not occurred since the last read of this register. this bit- field will be set to "1", if this interrupt has occurred since the last read of this register. the detection of p-bit error interrupt will occur if the receive ds3/e3 framer block detects a p-bit error in the incoming ds3 frame. n ote : for more information into the role of p-bits please see section 3.3.2.6.1. 3.3.2.11 receive ds3 sync detect enable register rxds3 sync detect enable register (address = 0x14) bits 4 - 0 enable5 f(4)- f(0) these read/write bit-fields allows the user to enable or disable the 5 parallel searches for valid m and f- bit, while the receive ds3 framer is operating in the frame acquisition mode. for proper operation, the user is highly encouraged to ensure that all of these bit-fields are set to "1". 2.3.2.12 receive ds3 feac register this read/write register contains the latest 6-bit feac code that has been received and validated by the receive feac processor. the contents of this register will be cleared if the previously validated code has been removed by the feac processor. n otes : 1. for more information on the operation of the receive feac processor, please see section 3.3.3.1. 2. this register is only valid if the channel has been configured to operate in the ds3, c-bit parity fram- ing format. 2.3.2.13 receive ds3 feac interrupt enable/ status register bit 4 - feac valid this read only bit is set to "1" when an incoming feac message code has been validated by the re- rxds3 sync detect enable register (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used enable f[4] enable f[3] enable f[2] enable f[1] enable f[0] ro ro ro r/w r/w r/w r/w r/w 00011111 rxds3 feac register (address = 0x16) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxfeac[5:0] not used ro ro ro ro r/o r/o r/o r/o 01111110 rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 68 ceive ds3/e3 framer block. this bit is cleared to "0" when the feac code is removed. n ote : for more information on the role of this bit-field and the receive feac processor, please see section 3.3.3.1. bit 3 - rxfeac remove interrupt enable this read/write bit-field permits the user to enable/ disable the rxfeac removal interrupt. writing a "1" to this bit enables this interrupt. likewise, writing a "0" to this bit-field disables this interrupt. n ote : for more information on the role of this bit-field and the receive feac processor, please see section 3.3.3.1. bit 2 - rxfeac remove interrupt status a "1" in this read only bit-field indicates that the most recently received and validated feac message has now been removed by the receive feac pro- cessor. the receive feac processor will remove a validated feac message if 3 out of the last 10 re- ceived feac messages differ from the latest valid feac message. n ote : for more information on this bit-field and the receive feac processor, please see section 3.3.3.1. bit 1 - rxfeac valid interrupt enable this read/write bit-field permits the user to enable or disable the rx feac valid interrupt. writing a "1" to this bit-field enables this interrupt. whereas, writing a "0" disables this interrupt. the value of this bit-field is "0" following power up or reset. n ote : for more information on this bit-field and the receive feac processor, please see section 3.3.3.1. bit 0 - rxfeac valid interrupt status a "1" in this read only bit-field indicates that a newly received feac message has been validated by the receive feac processor. the receive feac processor will validate a new feac message, once that message has been re- ceived in 8 out of 10 most recently received feac messages. n ote : for more information on this bit-field and the receive feac processor, please see section 3.3.3.1. 2.3.2.14 receive ds3 lapd control register bit 2 rxlapd enable this read/write bit-field permits the user to enable or disable the lapd receiver. the lapd receiver must be enabled before it can begin to receive and process any lapd message frames from the incom- ing ds3 data stream. writing a "0" to this bit-field disables the lapd re- ceiver (the default condition). writing a "1" to this bit- field enables the lapd receiver. bit 1 rxlapd (message frame reception com- plete) interrupt enable this read/write bit-field permits the user to enable or disable the lapd message frame reception com- plete interrupt. if this interrupt is enabled, then the channel (within the framer ic) will generate this inter- rupt to the local p, once the last bit of a lapd mes- sage frame has been received and the pmdl mes- sage has been extracted and written into the receive lapd message buffer. writing a "0" to this bit-field disables this interrupt (the default condition). writing a "1" to this bit-field en- ables this interrupt. bit 0 rxlapd (message reception complete) in- terrupt status this read-only bit field indicates whether or not the lapd message reception complete interrupt has occurred since the last read of this register. the lapd message reception complete interrupt will oc- cur once the lapd receiver has received the last bit of a complete lapd message frame, extracted the pmdl message from this lapd message frame and has written this (pmdl) message frame into the re- ceive lapd message buffer. the purpose of this in- terrupt is to notify the local p that the receive lapd message buffer contains a new pmdl message, that needs to be read and/or processed. a "0" in this bit-field indicates that the lapd message reception complete interrupt has not occurred since the last read of this register. a "1" in this bit- rxds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 69 field indicates that the lapd message reception complete interrupt has occurred since the last read of this register. n ote : for more information on the lapd receiver, please see section 3.3.3.2. 2.3.2.15 receive ds3 lapd status register bit 6 - rxabort (receive abort sequence) this read-only bit-field indicates whether or not the lapd receiver has detected the occurrence of an abort sequence (e.g., a string of seven or more con- secutive "1s") from the remote lapd transmitter. a "0" in this bit-field indicates that no abort-sequence has been detected. a "1" in this bit-field indicates that the abort-sequence has been detected. n ote : for more information on the lapd receiver, please see section 3.3.3.2. bits, 5 and 4 - rxlapdtype[1, 0] these two read only bit-fields combine to indicate the type of lapd message frame that has been re- ceived by the lapd receiver. the relationship be- tween these two bit-fields and the lapd message type follows: bit 3 - rxcr (command/response) type this read only bit field indicates the value of the c/r (command/response) bit-field of the latest received lapd message. bit 2 - rx fcs (frame check sequence) error this read-only bit-field indicates whether or not the lapd receiver has detected a frame check se- quence (fcs) error in the most recently received lapd message frame. a "0" in this bit-field indicates that the fcs for the latest received lapd message frame is correct. a "1" in this bit-field indicates that the fcs for the latest received lapd message frame is incorrect. n ote : for more information on the lapd receiver, please see section 3.3.3.2. bit 1 - end of message this read-only bit-field indicates whether or not the lapd receiver has completed its reception of the lat- est incoming lapd message frame. the local p can poll the progress of the lapd receiver by peri- odically reading this bit-field. a "0" in this bit-field indicates that the lapd receiver is still receiving the latest message from the remote lapd transmitter. a "1" in this bit-field indicates that the lapd receiver has finished receiving the com- plete lapd message frame. bit 0 - flag present this read-only bit-field indicates whether or not the lapd receiver has detected the occurrence of the flag sequence byte (0x7e) within the inbound lapd channel (e.g., the dl bits in ds3 applications). a "0" in this bit-field indicates that the lapd receiver does not detect the occurrence of the flag sequence byte. a "1" in this bit-field indicates that the lapd receiver does detect the occurrence of the flag sequence byte. n ote : for more information on the lapd receiver, please see section 3.3.3.2. 2.3.3 receive e3 framer configuration regis- ters (itu-t g.832) 2.3.3.1 receive e3 configuration & status register 1 (e3, itu-t g.832) rxds3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0} rxcr type rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000000 b it 5b it 4m essage t ype m essage length 0 0 cl path identification 76 bytes 0 1 idle signal identification 76 bytes 1 0 test signal identification 76 bytes 1 1 itu-t path identification 82 bytes ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 70 bit 7 - 5 - rxpldtype[2:0] (received payload type[2:0]) these three read-only bit-fields contain the payload type value within the ma byte of the most recently re- ceived e3 frame. n otes : 1. the payload type mismatch interrupt will be gener- ated if the contents of these bit-fields differ from that of the expected payload types in bits 2 through 0 within this register. 2. these bit-fields are ignored is the channel is config- ured to support the october 1998 version of the itu-t g.832 framing format for e3. bit 4 - rxferf algo this read/write bit-field allows the user to select one of the two rxferf declaration algorithms: writing a "0" to this bit-field selects the following rxferf declaration algorithm: ? the receive ds3/e3 framer declares a far end receive failure (ferf) if the ferf bit-field, within the ma byte is set to "1" for 3 consecutive incoming e3 frames. likewise, the receive ds3/e3 framer block will negate the far end receive failure condi- tion if the ferf bit-field, within the ma byte is set to "0" for 3 consecutive incoming e3 frames. writing a "1" to this bit-field selects the following rxferf declaration algorithm: ? the receive ds3/e3 framer block declares a far end receive failure (ferf) if the ferf bit-field, within the ma byte is set to "1" for 5 consecutive e3 frames. likewise, the receive e3/ds3 framer block will negate the far end receive failure condi- tion if the ferf bit-field, within the ma byte is set to "0" for 5 consecutive incoming e3 frames. bit 3 - rxtmark algorithm this read/write bit-field allows the user to select the number of consecutive incoming e3 frames, that the timing marker bit-field (within the ma byte-field) must be of a given logic state, before it is validated by the receive ds3/e3 framer block. once the receive ds3/e3 framer block has validated the state of the timing marker bit-field, then it will write this logic state into bit 1 (rxtmark) within the rx e3 configura- tion & status register 2 (address = 0x11) writing a "0" into this bit-field causes the receive ds3/e3 framer block to validate the timing marker value after receiving 3 consecutive incoming e3 frames, with the timing marker bit-field of a given val- ue. writing a "1" into this bit-field causes the receive ds3/e3 framer block to validate the timing marker value after receiving 5 consecutive incoming e3 frames, with the timing marker bit-field of a given val- ue. n ote : this bit-field is ignored if the channel is configured to support the october 1998 version of the itu-t g.832 framing format for e3. bits 2 - 0: rxpldexp[2:0] this read/write bit-field allows the user to specify the payload type that is expected in the ma bytes, of each incoming e3 frame. if the receive ds3/e3 framer detects a payload type that differs from the values within these bit-fields, then the framer will generate the payload type mismatch interrupt. rxe3 configuration & status register 1 (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxpldtype[2:0] rxferf algo rxtmark algo rxpldexp[2:0] ro ro ro ro ro r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 71 2.3.3.2 receive e3 configuration & status register 2 (e3, itu-t g.832) bit 7 - rxlof algo (loss of frame declaration al- gorithm) this read/write bit-field allows the user to select the lof (loss of frame) declaration criteria, that will be used by the receive ds3/e3 framer. writing a "0" to this bit-field configures the receive ds3/e3 framer to declare an lof condition, after it has been in the oof condition for 24 frame periods (3 ms). writing a "1" to this bit-field configures the receive ds3/e3 framer to declare an lof condition, after it has been in the oof condition for 8 frame periods (1 ms). bit 6 - rxlof (loss of frame declaration) this read-only bit-field indicates whether or not the receive ds3/e3 framer block is currently in the loss of frame (lof) condition. if this bit-field is set to "1", then the receive ds3/e3 framer block is currently in the lof condition. conversely, if this bit-field is set to "0", then the receive ds3/e3 framer block is current- ly not in the lof condition. bit 5 - rxoof (out of frame declaration) this read-only bit field indicates whether or not the receive ds3/e3 framer block is currently experienc- ing an out of frame (oof) condition. the receive ds3/e3 framer block will declare an oof condition if it has detected errors in the frame alignment bytes (fa1 and fa2) in four consecutive frames. if this bit- field is set to "1", then the receive ds3/e3 framer block has declared, and is continuing to experience an oof condition. if this bit-field is set to "0", then the receive ds3/e3 framer block is currently not ex- periencing an oof condition. bit 4 - rxlos (loss of signal declaration) this read-only bit-field indicates whether or not the receive ds3/e3 framer block is currently experienc- ing a loss of signal (los) condition. the receive ds3/e3 framer block will declare an los condition if it has detected a string of 32 consecutive "0s", via the rxpos and rxneg input pins. if this bit-field is set to "1", then the receive ds3/e3 framer block has de- clared, and is continuing to experience an los condi- tion. if this bit-field is set to "0", then the receive ds3/e3 framer block is currently not experiencing an los condition. bit 3 - rxais (alarm indication status declara- tion) this read-only bit-field indicates whether or not the receive ds3/e3 framer block is currently experienc- ing an ais condition. the receive ds3/e3 framer block will declare an ais condition if it has detected two consecutive e3 frames, that each contain less than seven (7) "0s" . if this bit-field is set to "1", then the receive ds3/e3 framer block has declared, and is continuing to experience an ais condition. if this bit-field is set to "0", then the receive ds3/e3 framer block is currently not experiencing an ais condition. bit 2 - rxpldtype unstab this read-only bit-field indicates whether or not the receive ds3/e3 framer block has been receiving a consistent payload type value (within the ma byte- field) in the last 5 consecutive incoming e3 frames. if the receive ds3/e3 framer block has detected a change in the payload type value, within the last 5 in- coming e3 frames, then it will set this bit-field to "1". if the payload type value has been consistent in the last 5 e3 frames, then the receive ds3/e3 framer block will set this bit-field to "0". bit 1 - rx tmark this read-only bit-field reflects the most recently val- idated timing marker value. the receive ds3/e3 framer block will validate the timing marker state, af- ter it has detected a user-selectable number of con- secutive incoming e3 frames with a consistent timing marker value. the user makes this selection by writ- ing the appropriate value to bit 3 (rxtmarkalgo) with- in the rx e3 configuration/status register (address = 0x0e). bit 0 - rxferf (far end receive failure) this read-only bit-field indicates whether or not the receive ds3/e3 framer block is experiencing an ferf (far-end-receive-failure) condition. the re- ceive ds3/e3 framer block will declare a ferf con- dition, if it has received a user-selectable number of rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rxtmark rxferf r/wrororororororo 01111111 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 72 consecutive e3 frames, with the ferf bit-field (within the ma byte) set to "1". this user-selectable number is either 3 or 5 e3 frames. conversely, the receive e3 framer will negate the ferf declaration, if it has received this user-selectable number of consecutive e3 frames, with the ferf bit-field set to "0". if this bit-field is set to "1", then the receive ds3/e3 framer block has declared an ferf condition. if this bit-field is set to "0", then the receive ds3/e3 framer block has not declared an ferf condition. n ote : please see section 5.1.1.4, for a more detailed dis- cussion on the meaning of the ferf bit-field, within the e3 frame. 2.3.3.3 3.3.2.17 receive e3 interrupt enable register (e3, itu-t g.832) bit 6 - ssm message interrupt enable this read/write bit-field permits the user to enable or disable the change in synchronous status message (ssm) interrupt. setting this bit-field to 1 enables this interrupt. setting this bit-field to 0 disables this interrupt. n ote : this bit-field is ignored if the channel is configured to support the november 1995 revision of the itu-t g.832 framing format for e3. bit 5 - ssm oof (out of sequence) interrupt en- able this read/write bit-field permits the user to enable or disable the change in ssm out of sequence state interrupt. setting this bit-field to 1 enables this inter- rupt. setting this bit-field to 0 disables this interrupt. n ote : this bit-field is ignored if the channel is configured to support the november 1995 revision of the itu-t g.832 framing format for e3. bit 4 - change of frame alignment (cofa) inter- rupt enable this read/write bit-field allows the user to enable or disable the change of frame alignment interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. bit 3 - oof (out of frame) interrupt enable this read/write bit field allows the user to enable or disable the change in out-of-frame (oof) status in- terrupt. setting this bit-field to "1" enables this inter- rupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the oof condition, please see section 5.3.2.1. bit 2 - lof (loss of frame) interrupt enable this read/write bit-field allows the user to enable or disable the change in loss-of-frame (lof) status in- terrupt. setting this bit-field to "1" enables this inter- rupt. setting this bit-field to "0" disables this interrupt. for more information on the lof condition, please see section 5.3.2.1. bit 1 - los (loss of signal) interrupt enable this read/write bit-field allows the user to enable or disable the change in los condition interrupt. set- ting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the los condition, please see section 5.3.2.6. bit 0 - ais interrupt enable this read/write bit-field allows the user to enable or disable the change in ais condition interrupt. setting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the ais condition, please see section 5.3.2.6.2. rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ssm msg interrupt enable ssm oos interrupt enable cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro r/wr/wr/wr/wr/wr/wr/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 73 2.3.3.4 3.3.2.18 receive e3 interrupt enable register - 2 (e3, itu-t g.832) bit 6 - ttb change interrupt enable this read/write bit-field allows the user to enable or disable the change in trail trace buffer message in- terrupt. setting this bit-field to "1" enables this inter- rupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on trail trace buffer mes- sages, please see section 5.3.2.9. bit 5 - received lapd message interrupt enable this read/write bit-field allows the user to enable or disable the received lapd message frame interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. n ote : for more information on this interrupt, please see section 5.3.6.1.12. bit 4 - febe (far-end block error) interrupt en- able this read/write bit-field allows the user to enable or disable the far-end-block error (febe) interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. n ote : for more information on the febe interrupt condi- tion, please see section 5.3.6.1.8. bit 3 - ferf (far-end receive failure) interrupt enable this read/write bit-field allows the user to enable or disable the change in ferf condition interrupt. set- ting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the change in ferf condi- tion interrupt, please see section 5.3.6.1.7. bit 2 - em byte error interrupt enable this read/write bit-field allows the user to enable or disable the em byte error interrupt. setting this bit- field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on this interrupt, please see section 5.3.6.1.9. bit 1 - framing byte error interrupt enable this read/write bit-field allows the user to enable or disable the framing byte error interrupt. setting this bit-field to "1" enables this interrupt. setting this bit- field to "0" disables this interrupt. n ote : for more information on this interrupt, please see section 5.3.6.1.10. bit 0 - receive payload type mismatch interrupt enable this read/write bit-field allows the user to enable or disable the receive payload type mismatch interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. n ote : for more information on this interrupt, please see section 5.3.6.1.11. 2.3.3.5 receive e3 interrupt status register - 1 (e3, itu-t g.832) rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 00000000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ssm msg interrupt status ssm oos interrupt status cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro rur rur rur rur rur rur rur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 74 bit 6 - ssm message interrupt status this reset-upon-read bit-field indicates whether or not a change of synchronization status message (ssm) interrupt has occurred since the last read of this register. this interrupt will occur whenever a change in the contents of the ssm (within the in- bound e3 data stream) has been detected. if this bit-field has been set to 1, then the change of ssm interrupt has occurred since the last read of this register. conversely, if this bit-field has been set to 0, then the change of ssm interrupt has not oc- curred since the last read of this register. n ote : this bit-field is invalid if the channel has been con- figured to support the november 1995 revision of the itu-t g.832 framing format for e3. bit 5 - ssm out of sequence interrupt status this reset-upon-read bit-field indicates whether or not the change in ssm out of sequence state inter- rupt has occurred since the last read of this register. this interrupt will occur in response to either of the following conditions. 1. the receive section losses sequence synchroni- zation with the ssm data. 2. the receive section re-acquires sequence syn- chronization with the ssm data. n ote : this bit-field is invalid if the channel has been con- figured to support the november 1995 revision of the itu-t g.832 framing format for e3. bit 4 - cofa (change of frame alignment) inter- rupt status this reset-upon-read bit-field will be set to "1" if the change of frame alignment interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the change of frame alignment interrupt if it has detect- ed a change in frame alignment in the incoming e3 frames. bit 3 - oof (receive e3 framer) interrupt status this reset upon read bit-field is set to "1" if the re- ceive ds3/e3 framer block has detected a change in the out-of-frame (oof) condition, since the last time this register was read. therefore, this bit-field will be asserted under either of the following two conditions: 1. when the receive ds3/e3 framer block has detected the appropriate conditions to declare an oof condition. 2. when the receive ds3/e3 framer block has transitioned from the oof condition (frame acquisition mode) into the in-frame condition (frame maintenance mode). n ote : for more information of the oof condition, please see section 5.3.2.1. bit 2 - lof (loss of frame) interrupt status this reset-upon-read bit-field will be set to "1" if a change in lof condition interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the change in lof condition interrupt is response to ei- ther of the following two occurrences. 1. whenever the receive ds3/e3 framer block transitions from the oof condition state into the lof condition state, within the e3 framing acquisition/maintenance algorithm (per figure 194). 2. whenever the receive ds3/e3 framer block transitions from the fa1, fa2 octet verification state to the in-frame state, within the e3 framing acquisition/maintenance algorithm (per figure 194). bit 1 - los (loss of signal) interrupt status this reset upon read bit will be set to "1", if the re- ceive ds3/e3 framer block has detected a change in the los status condition, since the last time this register was read. this bit-field will be as- serted under either of the following two conditions: 1. when the receive ds3/e3 framer block detects the occurrence of an los condition (e.g., the occurrence of 32 consecutive spaces in the incoming e3 data stream), and 2. when the receive ds3/e3 framer block detects the end of an los condition (e.g., when the receive ds3/e3 framer block detects a string 32 bits that does not contain a string of four consec- utive "0s"). the local p can determine the current state of the los condition by reading bit 6 of the rx e3 configu- ration and status register (address = 0x11). n ote : for more information in the los of signal (los) alarm, please see section 5.3.2.6. bit 0 - ais interrupt status this reset upon read bit field will be set to "1", if the receive ds3/e3 framer block has detected a change in the ais condition, since the last time this register was read. this bit-field will be asserted un- der either of the following two conditions: 1. when the receive ds3/e3 framer block first detects an ais condition in the incoming e3 data stream. 2. when the receive ds3/e3 framer block has detected the end of an ais condition in the incoming e3 data stream. XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 75 the local p can determine the current state of the ais condition by reading bit 7 of the rx e3 configura- tion and status register (address = 0x11). n ote : for more information on the ais condition please see section 5.3.2.6.2. 2.3.3.6 receive e3 interrupt status register - 2 (e3, itu-t g.832) bit 6 - ttb change interrupt status (receipt of new trail trace buffer message interrupt) this reset-upon-read bit-field will be set to "1" if a receipt of new trail trace buffer message interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the receipt of new trail trace buffer message interrupt, if it receives an e3 frame in which the value of the tr byte-field is of the form "1xxxxxxxb". a tr byte-field value of this form is identified as the frame start mark- er. n ote : please see section 5.3.6.1.6 for a more detailed dis- cussion of this interrupt. bit 4 - febe (far-end block error) interrupt status this reset-upon-read bit-field will be set to "1" if the febe (far-end-block error) interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the febe interrupt anytime it detects a "1" in the febe bit-field within an incoming e3 frame. n ote : please see section 5.3.6.1.8 for a more detailed dis- cussion of this interrupt. bit 3 - ferf interrupt status this reset upon read bit will be set to '1' if the re- ceive e3 framer has detected a change in the rx ferf condition, since the last time this register was read. this bit-field will be asserted under either of the fol- lowing two conditions. 1. when the receive ds3/e3 framer block first detects the occurrence of an rxferf condition (e.g., when the ferf bit, within the last 3 or 5 consecutive e3 frames are set to "1"). 2. when the receive ds3/e3 framer block detects the end of the rxferf condition (e.g., when the ferf bit, within the last 3 or 5 consecutive e3 frames are set to "0"). n ote : for more information on the rxferf (yellow alarm) condition, please see section 5.3.2.6.3. bit 2 - em (bip-8) byte error interrupt status this reset-upon-read bit-field will be set to "1" if the bip-8 error interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the bip-8 error interrupt if it has concluded that it has re- ceived an errored e3 frame, from the remote termi- nal. n ote : please see section 5.3.6.1.9 for a more detailed dis- cussion of this interrupt. bit 1 - framing byte error interrupt status this reset-upon-read bit-field will be set to "1" if the framing byte error interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the framing byte error interrupt if it has detected an error in the fa1 or fa2 bytes, on an incoming e3 frame. n ote : please see section 5.3.6.1.10 for a more detailed discussion of this interrupt. bit 0 - rx pld mis interrupt status this reset-upon-read bit-field will be set to "1" if the payload type mismatch interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the payload type mismatch interrupt when it detects that the values, within the payload type bit-fields of the in- coming e3 frame, has changed from that of the previ- ous e3 frame. n ote : please see section 5.3.6.1.11 for a more detailed discussion on this interrupt. rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 76 2.3.3.7 receive e3 lapd control register (e3, itu-t g.832) bit 3 - dl from nr this read/write bit-field allows the user to specify whether the lapd receiver should retrieve the bytes, comprising the incoming lapd message frame, from the nr byte-field, or from the gc byte-field, within each incoming e3 frame. writing a "1" configures the lapd receiver to re- trieve the incoming lapd message frame octets from the nr byte-field, within each incoming e3 frame. writing a "0" configures the lapd receiver to re- trieve the incoming lapd message frame octets from the gc byte. bit 2 - rxlapd enable this read/write bit-field allows the user to enable or disable the lapd receiver, for reception of incoming lapd message frames from the remote lapd transmitter. writing a "1" to this bit-field enables the lapd re- ceiver. writing a "0" to this bit-field disables the lapd receiver. bit 1 - rxlapd (received lapd message) inter- rupt enable this read/write bit-field allows the user to enable or disable the received lapd message frame interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. for more information on this interrupt, please see section 5.3.3. bit 0 - rxlapd (received lapd message) inter- rupt status this reset-upon-read bit-field will be set to "1" if the receipt of new lapd message frame interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate this receipt of new lapd message frame interrupt when the lapd receiver has received a complete lapd message frame from the remote lapd transmitter. n ote : please see section 5.3.6.1.12 for a more detailed discussion of this interrupt. 2.3.3.8 receive e3 lapd status register (e3, itu-t g.832 bit 6 - rx abort this read-only bit-field indicates whether or not the lapd receiver is currently detecting an abort se- quence (e.g., a string of 7 consecutive "1s"). this bit-field is set to "1" if the lapd receiver is cur- rently detecting an abort sequence in the incoming lapd channel. conversely, this bit-field is set to "0" if the lapd receiver has not detected an abort se- quence, since the last read of this register. bit 5, 4 - rxlapd type[1:0] these two read-only bit-fields combine to indicate the type and size of lapd message frame that has been received by the lapd receiver. the following rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used dl from nr rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro r/w r/w r/w rur 00000000 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx abort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro r/w r/w r/w rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 77 table relates the contents of these bit-fields to the lapd message type/size. bit 3 - rx cr type this read-only bit-field indicates the state of the c/r bit-field, within octet # 2 of the most recently received lapd message frame. bit 2 - rx fcs error this read-only bit-field indicates whether or not the lapd receiver has detected an fcs (frame check sequence) error, in the most recently received lapd message frame. this bit-field is set to "0" if the lapd receiver does not detect an fcs error in this lapd message frame. conversely, this bit-field is set to "1" if the lapd receiver does detect an fcs error in this lapd message frame. n ote : for a more detailed discussion on the lapd receiver's handling of the fcs bytes, please see section 5.3.3. bit 1 - endofmessage the lapd receiver will assert this read-only bit-field, when it has received a complete lapd message frame. this bit-field, along with the receipt of new lapd message frame interrupt, serves to inform the local p that the receive lapd message buffer con- tains a new pmdl message that needs to be read and processed. this bit-field is cleared (to "0") upon reading this reg- ister. bit 0 - flag present the lapd receiver will assert this read-only bit-field when it is currently detecting the flag sequence octet (7eh) in the incoming lapd channel (e.g., either the gc or the nr byte-field, within each e3 frame). the lapd receiver will negate this bit-field when it is no longer receiving the flag sequence octet in the in- coming lapd channel. 2.3.3.9 receive e3 nr byte register (e3, itu-t g.832) this read-only register contains the value of the nr byte, within the most recently received e3 frame. please see section 5.3.3 for a more detailed discus- sion on this register. 2.3.3.10 receive e3 gc byte register (e3, itu- t g.832) r x lapdt ype [1:0] lapd m essage f rame t ype pmdl m essage s ize (i nformation s ection ) 00 cl path identification type 76 bytes 01 idle signal identification type 76 bytes 10 test signal identification type 76 bytes 11 itu-t path identification type 82 bytes rxe3 nr byte register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxnr[7:0] ro ro ro ro ro ro ro ro 00000000 rxe3 gc byte register (address = 0x1b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxgc[7:0] ro ro ro ro ro ro ro ro 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 78 this read-only register contains the value of the gc byte, residing in the most recently received e3 frame. please see section 5.3.3 for a more detailed discus- sion on this register. 2.3.3.11 receive e3 ttb-0 register (e3, itu-t g.832) this read-only register contains the frame start marker byte of the 16 byte trail trace buffer message that has been received from the remote terminal, via the tr byte-field within the incoming e3 frames. the remaining bytes, of this trail trace buffer message can be found in the rxttb-1 through rxttb-15 reg- isters. the data in this register is typically of the form [1, c6, c5, c4, c3, c2, c1, c0]. the "1" in the msb position identifies this byte as being the frame start marker (e.g., the first byte within the 16 byte trail trace buffer message). the remaining bits: c0 - c6 contain the crc-7 value that was calculated over the previous 16 byte trail trace buffer message. n otes : 1. the XRT72L50 framer device will not compute or verify this crc-7 value. it is up to the user's hard- ware and/or software to compute and verify this value. 2. for more information on the use of this register, please see section 5.3.2.9. 2.3.3.12 receive e3 ttb-1 register (e3, itu-t g.832) this read-only register contains the second (2nd) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.13 receive e3 ttb-2 register (e3, itu-t g.832) this read-only register contains the third (3rd) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is re- quired for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. rxe3 ttb-0 register (address = 0x1c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-0 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-1 register (address = 0x1d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-1 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-2 register (address = 0x1e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-2 ro ro ro ro ro ro ro ro 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 79 2.3.3.14 receive e3 ttb-3 register (e3, itu-t g.832) this read-only register contains the fourth (4th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is re- quired for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.15 receive e3 ttb-4 register (e3, itu-t g.832) this read-only register contains the fifth (5th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is re- quired for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.16 receive e3 ttb-5 register (e3, itu-t g.832) this read-only register contains the sixth (6th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is re- quired for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.17 receive e3 ttb-6 register (e3, itu-t g.832) rxe3 ttb-3 register (address = 0x1f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-3 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-4 register (address = 0x20) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxnr[7:0] ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-5 register (address = 0x21) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-5 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-6 register (address = 0x22) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxnr[7:0] ro ro ro ro ro ro ro ro 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 80 this read-only register contains the seventh (7th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.18 receive e3 ttb-7 register (e3, itu-t g.832) this read-only register contains the eighth (8th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is re- quired for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.19 receive e3 ttb-8 register (e3, itu-t g.832) this read-only register contains the ninth (9th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is re- quired for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.20 receive e3 ttb-9 register (e3, itu-t g.832) this read-only register contains the tenth (10th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is re- quired for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. rxe3 ttb-7 register (address = 0x23) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-7 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-8 register (address = 0x24) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxnr[7:0] ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-9 register (address = 0x25) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-9 ro ro ro ro ro ro ro ro 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 81 2.3.3.21 receive e3 ttb-10 register (e3, itu-t g.832) this read-only register contains the eleventh (11th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.22 receive e3 ttb-11 register (e3, itu-t g.832) this read-only register contains the twelfth (12th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.23 receive e3 ttb-12 register (e3, itu-t g.832) this read-only register contains the thirteenth (13th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.24 receive e3 ttb-13 register (e3, itu-t g.832) rxe3 ttb-10 register (address = 0x26) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-10 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-11 register (address = 0x27) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-11 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-12 register (address = 0x28) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-12 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-13 register (address = 0x29 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-13 ro ro ro ro ro ro ro ro 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 82 this read-only register contains the fourteenth (14th) byte within the 16 byte trail trace buffer mes- sage, that has been received from the remote termi- nal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.25 receive e3 ttb-14 register (e3, itu-t g.832) this read-only register contains the fifteenth (15th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.26 receive e3 ttb-15 register (e3, itu-t g.832) this read-only register contains the sixteenth (16th) byte within the 16 byte trail trace buffer message, that has been received from the remote terminal. this register typical contains an ascii character that is required for the e.164 numbering format. n ote : for more information on the use of this register, please see section 5.3.2.9. 2.3.3.27 receive e3 framer ssm register bit 7 - rxssm enable this read/write bit-field permits the user to configure the receive section of a given channel to support processing of the ma byte via either the old or the new itu-t g.832 framing format. setting this bit-field to 1 configures the receive section to support the new e3, itu-t g.832 framing standard (october 1998 revision). setting this bit- field to 0 configures the receive section to support the old e3, itu-t g.832 framing standard (novem- ber 1995). bits 6, 5 - mf[1:0] - ssm multiframe indicator bits these two bits reflect the states of the ssm multi- frame phase indicators, within the most recently re- ceived e3 frame. stated another ways, these two bit- fields reflect bits 2 and 1 within the ma byte, in the most recently received e3 frame. n ote : these two bit-fields are only valid if the receive section of the channel has been configured to support the rxe3 ttb-14 register (address = 0x2a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-14 ro ro ro ro ro ro ro ro 00000000 rxe3 ttb-15 register (address = 0x2b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxttb-15 ro ro ro ro ro ro ro ro 00000000 rxe3 ssm register (address = 0x2b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxssm enable mfi[1:0] reserved rxssm[3:0] r/wrororororororo 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 83 october 1998 revision of the itu-t g.832 framing format for e3. bits 3-0 - rxssm[3:0] - received synchronization status message these four read-only bits reflect the content of the ssm, which is currently being received via the in- bound e3 data stream. n ote : these four bit-fields are only valid if the receive section of the channel has been configured to support the october 1998 revision of the itu-t g.832 framing format for e3. 2.3.4 receive e3 framer configuration regis- ters (itu-t g.751) 2.3.4.1 receive e3 framer configuration & status register - 1 (e3, itu-t g.751) bit 4 - rxferf algo(rithm) select this read/write bit-field permits the user to select the received ferf declaration algorithm. setting this bit-field to "0", configures the receive section of the channel to declare a ferf (far-end- receive failure), after three (3) consecutive e3 frames, with the a-bit set to "1", have been received. further, the receive section of the channel will clear ferf, after three (3) consecutive e3 frames, with the a-bit set to "0", have been received. setting this bit-field to "1", configures the receive section of the channel to declare a ferf, after five (5) consecutive e3 frames, with the a-bit set to "1", have been received. further, the receive section of the channel will clear ferf after five (5) consecutive e3 frames, with the a-bit set to "0", have been re- ceived. bit 0 - rxbip4 enable this read/write bit-field permits the user to configure the receive section of the channel to verify (or not verify) the bip-4 value within each incoming e3 frame. setting this bit-field to "0", configures the receive section of the channel to not verify the bip-4 value within each incoming e3 frame. setting this bit-field to "1", configures the receive section of the channel to verify the bip-4 value within each incoming e3 frame. 2.3.4.2 receive e3 framer configuration & status register -2 (e3, itu-t g.751) bit 7 - rxlof (receive loss of frame) al- go(rithm) select this read/write bit-field permits the user to select the receive loss of frame declaration algorithm, for the receive section of the channel. setting this bit-field to "0" configures the receive section to declare a loss of frame condition, if it re- sides in the oof (out of frame) condition for 24 e3 frame periods. likewise, the receive section will clear the loss of frame condition, if it resides in the in-frame condition for 24 e3 frame periods. setting this bit-field to "1" configures the receive section to declare a loss of frame condition, if it re- sides in the oof (out of frame) condition for 8 e3 frame periods. likewise, the receive section will rxe3 configuration & status register - 1 g.751 (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxferf algo reserved rxbip4 ro ro ro r/w ro ro ro r/w 00000000 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 84 clear the loss of frame condition, if it resides in the in-frame condition for 8 e3 frame periods. n ote : for more information on the lof and oof condi- tion, please see section 4.3.2.2. bit 6 - rxlof (receive loss of frame) status this read-only bit-field indicates whether or not the receive section of the framer ic is operating in the loss of frame state. if this bit-field is set to "0", then the receive section is not operating in the loss of frame state. converse- ly, if this bit-field is set to "1", then the receive sec- tion is operating in the loss of frame state. n ote : for more information on the "loss of frame" state, please see section 4.3.2.2. bit 5 - rxoof (receive out of frame) status this read-only bit-field indicates whether or not the receive section of the channel is operating in the out of frame state. if this bit-field is set to "0", then the receive section is not operating in the out of frame state. conversely, if this bit-field is set to "1", then the receive section is operating in the out of frame state. n ote : for more information on the out of frame state, please see section 4.3.2.2. bit 4 - rxlos (receive loss of signal) status this read-only bit-field indicates whether or not the receive section of the channel is currently declaring an los (loss of signal) condition. if this bit-field is set to "0", then the receive section is not declaring a loss of signal condition. converse- ly, if this bit-field is set to "1", then the receive sec- tion is declaring the loss of signal condition. n ote : for more information on the loss of signal condi- tion, please see section 4.3.2.7. bit 3 - rxais (receive alarm indication signal) status this read-only bit-field indicates whether or not the receive section of the channel is currently declaring an ais (alarm indication signal) condition. if this bit-field is set to "0", then the receive section is not declaring a ais condition. conversely, if this bit- field is set to "1", then the receive section is declar- ing an ais condition. n ote : for more information on the ais condition, please see section 4.3.2.8. bit 0 - rxferf (received far-end-receive-fail- ure) status this read-only bit-field indicates whether or not the receive section of the channel is currently declaring a ferf (far-end receive failure) condition. if this bit-field is set to "0", then the receive section is not declaring a ferf condition. conversely, if this bit-field is set to "1", then the receive section is de- claring an ferf condition. n ote : for more information on the ferf condition, please see section 4.3.2.9. 2.3.4.3 receive e3 framer interrupt enable register - 1 (e3, itu-t g.751) bit 4 - cofa (change of frame alignment) inter- rupt enable this read/write bit-field allows the user to enable or disable the change of frame alignment interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. bit 3 - oof (change in oof condition) interrupt enable this read/write bit field allows the user to enable or disable the change in out-of-frame (oof) status in- terrupt. setting this bit-field to "1" enables this inter- rupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the oof condition, please see section 4.3.2.2. bit 2 - lof (change in lof condition) interrupt enable this read/write bit-field allows the user to enable or disable the change in loss-of-frame (lof) status in- terrupt. setting this bit-field to "1" enables this inter- rupt. setting this bit-field to "0" disables this interrupt. rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 85 n ote : for more information on the lof condition, please see section 4.3.2.2. bit 1 - los (change in los condition) interrupt enable this read/write bit-field allows the user to enable or disable the change in los condition interrupt. set- ting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the los condition, please see section 4.3.2.7. bit 0 - ais (change in ais condition) interrupt en- able this read/write bit-field allows the user to enable or disable the change in ais condition interrupt. setting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the ais condition, please see section 4.3.2.8 2.3.4.4 receive e3 interrupt enable register - 2 (e3, itu-t g.751) bit 3 - ferf (far-end receive failure) interrupt enable this read/write bit-field allows the user to enable or disable the change in ferf condition interrupt. set- ting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on the change in ferf condi- tion interrupt, please see section 4.3.6.1.6. bit 2 - bip-4 error interrupt enable this read/write bit-field allows the user to enable or disable the bip-4 error interrupt. setting this bit-field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on this interrupt, please see section 4.3.6.1.7. bit 1 - framing error interrupt enable this read/write bit-field allows the user to enable or disable the framing error interrupt. setting this bit- field to "1" enables this interrupt. setting this bit-field to "0" disables this interrupt. n ote : for more information on this interrupt, please see section 4.3.6.1.8. 2.3.4.5 receive e3 interrupt status register - 1 (e3, itu-t g.751) bit 4 - cofa (change of framing alignment) in- terrupt status this reset-upon-read bit-field will be set to "1" if the change of frame alignment interrupt has occurred since the last read of this register. the receive e3 framer will generate the change of frame alignment interrupt if it has detected a change in frame alignment in the incoming e3 frames. bit 3 - oof (change in oof condition) interrupt status this reset upon read bit-field is set to "1" if the re- ceive ds3/e3 framer block has detected a change in rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt enable bip-4 error interrupt enable framing error interrupt enable not used r/w ro ro ro r/w r/w r/w ro 00000000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status r/w ro ro rur rur rur rur rur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 86 the out-of-frame (oof) condition, since the last time this register was read. therefore, this bit-field will be asserted under either of the following two conditions: 1. when the receive ds3/e3 framer block has detected the appropriate conditions to declare an oof condition. 2. when the receive ds3/e3 framer block has transitioned from the oof condition (frame acquisition mode) into the in-frame condition (frame maintenance mode). n ote : for more information of the oof condition, please see section 4.3.2.2. bit 2 - lof (change in lof condition) interrupt status this reset-upon-read bit-field will be set to "1" if a change in lof condition interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the change in lof condition interrupt is response to ei- ther of the following two occurrences. 1. whenever the receive ds3/e3 framer block transitions from the oof condition state into the lof condition state, within the e3 framing acquisition/maintenance algorithm (per figure 114). 2. whenever the receive ds3/e3 framer block transitions from the fa1, fa2 octet verification state to the in-frame state, within the e3 framing acquisition/maintenance algorithm (per figure 114). bit 1 - los (change in los condition) interrupt status this reset upon read bit will be set to "1", if the re- ceive ds3/e3 framer block has detected a change in the los status condition, since the last time this reg- ister was read. this bit-field will be asserted under ei- ther of the following two conditions: 1. when the receive ds3/e3 framer block detects the occurrence of an los condition (e.g., the occurrence of 32 consecutive spaces in the incoming e3 data stream), and 2. when the receive ds3/e3 framer block detects the end of an los condition (e.g., when the receive ds3/e3 framer block detects a string 32 bits that does not contain a string of four consec- utive "0s"). the local p can determine the current state of the los condition by reading bit 6 of the rx e3 configu- ration and status register (address = 0x11). n ote : for more information in the los of signal (los) alarm, please see section 4.3.2.7. bit 0 - ais (change in ais condition) interrupt status this reset upon read bit field will be set to "1", if the receive ds3/e3 framer block has detected a change in the ais condition, since the last time this register was read. this bit-field will be asserted un- der either of the following two conditions: 1. when the receive ds3/e3 framer block first detects an ais condition in the incoming e3 data stream. 2. when the receive ds3/e3 framer block has detected the end of an ais condition in the incoming e3 data stream. the local p can determine the current state of the ais condition by reading bit 7 of the rx e3 configura- tion and status register (address = 0x11). n ote : for more information on the ais condition please see section 4.3.2.8. 2.3.4.6 receive e3 interrupt status register - 2 (e3, itu-t g.751) bit 3 - ferf (change in ferf condition) interrupt status this reset upon read bit will be set to '1' if the re- ceive ds3/e3 framer block has detected a change in the rx ferf condition, since the last time this regis- ter was read. this bit-field will be asserted under either of the fol- lowing two conditions. rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt status bip-4 error interrupt status framing error interrupt status not used ro ro ro ro rur rur rur rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 87 1. when the receive ds3/e3 framer block first detects the occurrence of an rx ferf condition (e.g., when the ferf bit, within the last 3 or 5 consecutive e3 frames are set to "1"). 2. when the receive ds3/e3 framer block detects the end of the rx ferf condition (e.g., when the ferf bit, within the last 3 or 5 consecutive e3 frames are set to "0"). n ote : for more information on the rx ferf (yellow alarm) condition, please see section 4.3.2.9. bit 2 - bip-4 (detection of bip-4) error interrupt status this reset-upon-read bit-field will be set to "1" if the bip-4 error interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate the bip-4 error interrupt if it has concluded that it has re- ceived an errored e3 frame, from the remote termi- nal. n ote : please see section 4.3.6.1.7 for a more detailed dis- cussion of this interrupt. bit 1 - framing error interrupt status this reset-upon-read bit-field will be set to "1" if the framing byte error interrupt has occurred since the last read of this register. the receive ds3/e3 framer blockwill generate the framing error interrupt if it has detected an error in the fas (or framing alignment), in an incoming e3 frame. n ote : please see section 4.3.6.1.8 for a more detailed dis- cussion of this interrupt. 2.3.4.7 receive e3 lapd control register (e3, itu-t g.751) bit 2 - rxlapd enable this read/write bit-field allows the user to enable or disable the lapd receiver, for reception of incoming lapd message frames from the remote lapd transmitter. writing a "1" to this bit-field enables the lapd re- ceiver. writing a "0" to this bit-field disables the lapd receiver. bit 1 - rxlapd (received lapd message) inter- rupt enable this read/write bit-field allows the user to enable or disable the received lapd message frame interrupt. setting this bit-field to "1" enables this interrupt. set- ting this bit-field to "0" disables this interrupt. n ote : for more information on this interrupt, please see section 4.3.6.1.9. bit 0 - rxlapd (received lapd message) inter- rupt status this reset-upon-read bit-field will be set to "1" if the receipt of new lapd message frame interrupt has occurred since the last read of this register. the receive ds3/e3 framer block will generate this receipt of new lapd message frame interrupt when the lapd receiver has received a complete lapd message frame from the remote lapd transmitter. n ote : please see section 4.3.6.1.9 for a more detailed dis- cussion of this interrupt. 2.3.4.8 receive e3 lapd status register (e3, itu-t g.751) rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt enable ro ro ro ro ro r/w r/w rur 00000000 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0] rxcr type rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 88 bit 6 - rxabort this read-only bit-field indicates whether or not the lapd receiver is currently detecting an abort se- quence (e.g., a string of 7 consecutive "1s"). this bit-field is set to "1" if the lapd receiver is cur- rently detecting an abort sequence in the incoming lapd channel. conversely, this bit-field is set to "0" if the lapd receiver has not detected an abort se- quence, since the last read of this register. bit 5, 4 - rxlapd type[1:0] these two read-only bit-fields combine to indicate the type and size of lapd message frame that has been received by the lapd receiver. the following table relates the contents of these bit-fields to the lapd message type/size. bit 3 - rxcr type this read-only bit-field indicates the state of the c/r bit-field, within octet # 2 of the most recently received lapd message frame. bit 2 - rxfcs error this read-only bit-field indicates whether or not the lapd receiver has detected an fcs (frame check sequence) error, in the most recently received lapd message frame. this bit-field is set to "0" if the lapd receiver does not detect an fcs error in this lapd message frame. conversely, this bit-field is set to "1" if the lapd receiver does detect an fcs error in this lapd message frame. n ote : for a more detailed discussion on the lapd receiver's handling of the fcs bytes, please see section 4.3.3. bit 1 - endofmessage the lapd receiver will assert this read-only bit-field, when it has received a complete lapd message frame. this bit-field, along with the receipt of new lapd message frame interrupt, serves to inform the local p that the receive lapd message buffer con- tains a new pmdl message that needs to be read and processed. this bit-field is cleared (to "0") upon reading this reg- ister. bit 0 - flag present the lapd receiver will assert this read-only bit-field when it is currently detecting the flag sequence octet (0x7e) in the incoming lapd channel (e.g., either the gc or the nr byte-field, within each e3 frame). the lapd receiver will negate this bit-field when it is no longer receiving the flag sequence octet in the in- coming lapd channel. 2.3.4.9 receive e3 service bits register (e3, itu-t g.751) bit 1 - rxa (a-bit) this read-only bit-field reflects the state of the a bit-field, within the most recently received e3 frame. bit 0 - rxn (n-bit) this read-only bit-field reflects the state of the n bit-field, within the most recently received e3 frame. 2.3.5 transmit ds3 configuration registers 2.3.5.1 transmit ds3 configuration register (ds3 applications) r x lapdt ype [1:0] lapd m essage f rame t ype pmdl m essage s ize (i nformation s ection ) 00 cl path identification type 76 bytes 01 idle signal identification type 76 bytes 10 test signal identification type 76 bytes 11 itu-t path identification type 82 bytes rxe3 service bit register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxa rxn ro ro ro ro ro ro ro ro 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 89 bit 7 - tx yellow alarm this read/write bit-field permits the user to com- mand the transmit ds3/e3 framer block to transmit a yellow alarm (e.g., x bits are all "0") in the outbound ds3 data stream. writing a "0" to this bit-field disables this feature (the default condition). in this condition, the x-bits in the out-bound ds3 frame, are internally generated (based upon receiver conditions). writing a "1" to this bit-field invokes this command. in this condition, the transmit ds3/e3 framer block will override the internally-generated x-bits and force all of the x-bits of each outbound ds3 frame to "0". n ote : for more information in this feature, please see sec- tion 3.2.4.2.1.1. n ote : this bit-setting is ignored if bits 3, 4 or 5 (within this register) are set to "1". bit 6 - tx x-bit (force x bits to "1") this "read/write" bit-field permits the user to com- mand the transmit ds3/e3 framer block to force all of the x-bits, in the outbound ds3 frames, to "1". writing a "0" to this bit-field disables this feature (the default condition). in this case, the transmit ds3/e3 framer block will generate x-bits based upon the re- ceive conditions. writing a "1" to this bit-field invokes this command. in this case, the transmit ds3/e3 framer block will overwrite the internally-generated x-bits and set them all to "1". n ote : for more information on this feature, please see section 3.2.4.2.1.2. n ote : this bit-setting is ignored if bits 3, 4, 5, or 7 (within this register) are set to "1". bit 5 - tx idle (pattern) this read/write bit-field permits the user to com- mand the transmit ds3/e3 framer block to transmit the idle condition pattern. if the user invokes this command, then the transmit ds3/e3 framer block will force the outbound ds3 frames to have the fol- lowing patterns. ? valid m-bits, f-bits and p-bits ? the three cp-bits (f-frame #3) are "0" ? the x-bits are set to "1" ? a repeating "1100..." pattern in written into the pay- load portion of the ds3 frames. writing a "1" to this bit-field invokes this command. writing a "0" allows the transmit ds3/e3 framer block to function normally (e.g., the transmit ds3/e3 framer block will transmit its payload and internally generated overhead bits). n ote : for more information on this feature, please see section 3.2.4.2.1.3. n ote : this bit-setting is ignored if bits 3 or 4 (within this register) are set to "1". bit 4 - tx ais (pattern) this read/write bit-field permits the user to com- mand the transmit ds3/e3 framer block to transmit an ais pattern. if the user invokes this command, then the transmit ds3/e3 framer block will force the outbound ds3 frames to have the following patterns. ? valid m-bits, f-bits, and p-bits ? all c-bits are set to '0' ? all x-bits are set to '1' ? a repeating '1010...' pattern is written into the pay- load of the ds3 frames. writing a "1' to this bit-field invokes this command. writing a "0" allows the transmit ds3/e3 framer block to function normally (e.g., the transmit ds3/e3 framer block will transmit its payload and internally generated overhead bits). n ote : for more information on this feature, please see section 3.2.4.2.1.4. bit 3 - tx los (loss of signal) this read/write bit-field permits the user to com- mand the transmit ds3/e3 framer block to simulate an los condition. if the user invokes this command, then the transmit ds3/e3 framer block will stop sending mark pulses out on the line and will transmit an all-zero pattern. writing a '0' to this bit-field disables (or shuts off) this feature, thereby allowing internally generated ds3 frames to be generated and transmitted over the line. transmit ds3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx yellow alarm tx x bits tx idle tx ais tx los ferf on los ferf on oof ferf on ais r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 90 writing a '1' to this bit-field invokes this command, causing the transmit ds3/e3 framer block to gener- ate an all '0' pattern. n ote : for more information on this feature, please see section 3.2.4.2.1.5. bit 2 - ferf on los this read/write bit-field allows the user to configure the transmit ds3/e3 framer block to generate a yel- low alarm if the near-end receive ds3/e3 framer block (within the same channel) detects a los (loss of signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section 3.2.4.2.1.6. bit 1 - ferf on oof this read/write bit-field allows the user to configure the transmit ds3/e3 framer block to generate a yel- low alarm if the near-end receive ds3/e3 framer block (within the same channel) detects an oof (out-of-frame) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section 3.2.4.2.1.7. bit 0 - ferf on ais this read/write bit-field allows the user to configure the transmit ds3/e3 framer block to generate a yel- low alarm if the near-end receive ds3/e3 framer block (within the same channel) detects an ais (alarm indication signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section 3.2.4.2.1.8. 2.3.5.2 transmit ds3 feac configuration & status register (ds3 applications) bit 4 - tx feac interrupt enable this read-write bit-field permits the user to enable or disable the transmit feac interrupt. setting this bit-field to 0 disables this interrupt. conversely, setting this bit-field to 1 enables this in- terrupt. bit 3 - txfeac interrupt status this read-only bit-field indicates whether or not the feac message transmission complete interrupt has occurred since the last read of this register. this in- terrupt will occur once the transmit feac processor has finished its 10th transmission of the 16 bit feac message (6 bit feac code word + 10 framing bits). the purpose of this interrupt is to let the local p know that the transmit feac processor has complet- ed its transmission of its latest feac message and is now ready to transmit another feac message. if this bit-field is "0", then the feac message trans- mission complete interrupt has not occurred since the last read of this register. if this bit-field is 1, then the feac message trans- mission complete interrupt has occurred since the last read of this register. n ote : for more information on the transmit feac proces- sor, please see section 3.2.3.1. bit 2 - txfeac enable this read/write bit-field allows the user to enable or disable the transmit feac processor. the transmit feac processor will not function until it has been enabled. writing a "0" to this bit-field disables the transmit feac processor. writing a "1" to this bit-field en- ables the transmit feac processor. bit 1 - txfeac go this bit-field allows the user to invoke the transmit feac message command. once this command has been invoked, the transmit feac processor will do the following: ? encapsulate the 6 bit feac code word, from the tx ds3 feac register (address = 0x32) into a 16 bit feac message transmit ds3 feac configuration & status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used tx feac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w rur r/w r/w ro 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 91 ? serially transmit this 16-bit feac message to the far-end receiver via the outbound ds3 data-stream, 10 consecutive times. n ote : for more information on the transmit feac proces- sor, please see section 3.2.3.1. bit 0 - txfeac busy this read-only bit-field allows the local p to poll and determine if the transmit feac processor has completed its 10th transmission of the 16-bit feac message. this bit-field will contain a "1", if the trans- mit feac processor is still transmitting the feac message. this bit-field will toggle to "0", once the transmit feac processor has completed its 10th transmission of the feac message. n ote : for more information on the transmit feac proces- sor, please see section 3.2.3.1. 2.3.5.3 transmit ds3 feac register (ds3 applications) this register contains a six (6) bit read/write field that allows the user to write in the six-bit feac code word, that is desired to be transmitted to the far end re- ceive feac processor, via the outgoing ds3 data stream. the transmit feac processor will encapsu- late this six-bit code into a 16-bit feac message, and will proceed to transmit this message to the remote receiver via the feac bit-field within each out-going ds3 frame. n ote : for more information on the operation of the trans- mit feac processor, please see section 3.2.3.1. 2.3.5.4 transmit ds3 lapd configuration register (ds3 applications) bit 3 - auto retransmit this read/write bit-field allows the user to configure the lapd transmitter to either transmit the lapd message frame only once or, repeatedly at one-sec- ond intervals. writing a "0" to this bit-field configures the lapd transmitter to transmit the lapd message frame once. afterwards, the lapd transmitter will halt transmission, until it has commanded to transmit an- other lapd message frame. writing a "1" to this bit-field configures the lapd transmitter to transmit the lapd message frame re- peatedly at one-second intervals. in this configura- tion, the lapd transmitter will repeat its transmission of the lapd message frame until it has been dis- abled. bit 1 - txlapd message length select this read/write bit-field permits the user to select the length of the outbound lapd message frame. setting this bit-field to "0" configures the outbound lapd message frame to be 76 bytes in length. set- ting this bit-field to 1 configures the outbound lapd message frame to be 82 bytes in length. bit 0 - txlapd enable this read/write bit-field allows the user to enable or disable the lapd transmitter. the lapd transmitter must be enabled before it can be commanded to transmit a lapd message frame (containing a pmdl message) via the outbound ds3 frames, to the far- end terminal. writing a 0" disables the lapd transmitter (default condition). writing a "1" enables the lapd transmit- ter. txds3 feac register (address = 0x32) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txfeac[5:0] not used ro r/wr/wr/wr/wr/wr/w ro 01111110 txds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable ro r/wr/wr/wr/wr/wr/w ro 00001000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 92 n ote : for information on the lapd transmitter, please see section 3.2.3.2. 2.3.5.5 transmit ds3 lapd status and inter- rupt register (ds3 applications) bit 3 - txdl start this read/write bit-field allows the user to invoke the transmit lapd message command. once the user invokes this command, the lapd transmitter will do the following: ? read in the pmdl message from the transmit lapd message buffer. ? encapsulate the pmdl message into a complete lapd message frame by including the necessary header and trailer bytes (e.g., flag sequence bytes, sapi, cr, ea values, etc.). ? compute the frame check sequence word (16 bit value) ? insert the frame check sequence value into the 2 octet slot after the payload section of the message. ? proceed to transmit the lapd message frame to the far end terminal via the outgoing ds3 frames. writing a "1" to this bit-field start the transmission of the lapd message frame, via the lapd transmitter. n ote : for more information on the lapd transmitter, please see section 3.2.3.2. bit 2 - txdl busy this read-only bit-field allows the local p to poll and determine if the lapd transmitter has completed its transmission of the lapd message frame. this bit-field will contain a "1", if the lapd transmitter is still transmitting the lapd message frame to the far- end terminal. this bit-field will toggle to "0", once the lapd transmitter has completed its transmission of the lapd message frame. n ote : for more information on the lapd transmitter, please see section 3.2.3.2. bit 1 - txlapd interrupt enable this read/write bit-field allows the user to enable or disable the lapd message frame transmission complete interrupt. writing a "0" to this bit-field disables this interrupt. writing a "1" to this bit-field enables this interrupt. bit 0 - txlapd interrupt status this reset upon read bit-field indicates whether or not the lapd message frame transmission complete interrupt has occurred since the last read of this reg- ister. the purpose of this interrupt is to let the local p know that the lapd transmitter has completed its transmission of the lapd message frame (containing the latest pmdl message) and is now ready to trans- mit another lapd message frame. a "0" in this bit-field indicates that the lapd message frame transmission complete interrupt has not oc- curred since the read of this register. a "1" in this bit- field indicates that this interrupt has occurred since the last read of this register. n ote : for more information on the txlapd interrupt, please see section 3.2.6. 2.3.5.6 transmit ds3 m-bit mask register (ds3 applications) txds3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 txds3 m-bit mask register (address = 0x35) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txfebedat[2:0] febe reg enable tx error p-bit mbit mask[2] mbit mask[1] mbit mask[0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 93 bit 7 - 5: txfebedat[2:0] these three (3) read/write bit-fields, along with bit 4 of this register, allows the user to configure and trans- mit his/her choice for the three (3) febe (far-end block error) bits in each outgoing ds3 frame. the user will write his/her value for the febe bits into these bit-fields. the transmit ds3 framer block will insert these values into the febe bit-fields of each outgoing ds3 frame, once the user has written a "1" to bit 4 (febe register enable). n ote : for more information on this feature, please see section 3.2.4.2.1.9. bit 4 - febe register enable this read/write bit-field permits the user to configure the transmit ds3 framer to insert the contents of txfebedat[2:0] into the febe bit-fields each out- bound ds3 frame. writing a "0" to this bit-field disables this feature (e.g., the transmit ds3 framer block will transmit the inter- nally generated febe bits). writing a "1" to this bit- field enables this features (e.g., the internally gener- ated febe bits are overwritten by the contents of the txfebedat[2:0] bit-field). n ote : for more information on this feature, please see section 3.2.4.2.1.9. bit 3 - transmit erred p-bit this read/write bit-field permits the user to insert er- rors into the p-bits within the outbound ds3 frames (via the transmit ds3/e3 framer block). if the user enables this feature, then the transmit ds3/e3 fram- er block will proceed to invert each and every p-bit, from its computed value, prior to transmission to the remote terminal. writing a "0" to this bit-field (the default condition) dis- ables this feature (e.g., the correct p-bits are sent). writing a "1" to this bit-field enables this feature (e.g., the incorrect p-bits are sent). n ote : for more information on this feature, please see section 3.2.4.2.2. bit 2 - 0 m-bit mask[2:0] these read/write bit-fields permit the user to insert errors in the m-bits for test and diagnostic purposes. the transmit ds3/e3 framer block automatically per- forms an xor operation on the actual contents of the m-bit fields to these register bit-fields. therefore, for every '1' that exists in these bit-fields, will result in a change of state of the corresponding m-bit, prior to being transmitted to the remote terminal equipment. if the transmit ds3/e3 framer block is to be operated in the normal mode (e.g., when no errors are being injected into the m-bit fields of the outbound ds3 frame), then these bit-fields must be all 0s. 2.3.5.7 transmit ds3 f-bit mask register - 1 (ds3 applications) bits 3 - 0 f-bit mask[27:24] these read/write bit-fields permit the user to insert errors into the first four f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3/e3 framer block automatically performs an xor opera- tion on the actual contents of these f-bit fields to these register bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being trans- mitted to the remote receive ds3/e3 framer. if the transmit ds3/e3 framer block is to be operated in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then all of these bit-fields must be "0s". 2.3.5.8 transmit ds3 f-bit mask register - 2 (ds3 applications) txds3 f-bit mask register - 1 (address = 0x36) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used fbit mask[27] fbit mask[26] fbit mask[25] fbit mask[24] ro ro ro ro r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 94 bits 7 - 0 f-bit mask[23:16] these read/write bit-fields permit the user to insert errors into the fifth through twelfth f-bits of a ds3 m- frame, for test and diagnostic purposes. the trans- mit ds3/e3 framer block automatically performs an xor operation on the actual contents of these f-bit fields to these register bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the remote terminal equipment. if the transmit ds3/e3 framer block is to be operated in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then all of these bit-fields must be "0s". 2.3.5.9 transmit f-bit mask register - 3 (ds3 applications) bits 7 - 0 f-bit mask[15:8] these read/write bit-fields permit the user to insert errors into the thirteenth through twentieth f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3/e3 framer block automatically per- forms an xor operation on the actual contents of these f-bit fields to these register bit-fields. there- fore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the remote termi- nal equipment. if the transmit ds3/e3 framer block is to be operated in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then all of these bit-fields must be "0s". 2.3.5.10 transmit f-bit mask register - 4 (ds3 applications) bits 7 - 0 f-bit mask[7:0] these read/write bit-fields allow the user to insert errors into the last eight f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3/e3 framer block automatically performs an xor opera- tion on the actual contents of these f-bit fields to these register bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being trans- mitted to the remote terminal equipment. if the transmit ds3/e3 framer block is to be operated in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then all of these bit-fields must be "0s". 2.3.6 transmit e3 (itu-t g.832) configuration registers txds3 f-bit mask register - 2 (address = 0x37) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[23] fbit mask[22] fbit mask[21] fbit mask[20] fbit mask[19] fbit mask[18] fbit mask[17] fbit mask[16] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txds3 f-bit mask register - 3 (address = 0x38) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[15] fbit mask[14] fbit mask[13] fbit mask[12] fbit mask[11] fbit mask[10] fbit mask[9] fbit mask[8] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txds3 f-bit mask register - 4 (address = 0x39) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[7] fbit mask[6] fbit mask[5] fbit mask[4] fbit mask[3] fbit mask[2] fbit mask[1] fbit mask[0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 95 2.3.6.1 transmit e3 configuration register (e3, itu-t g.832) bit 4 - dlinnr this read/write bit-field permits the user to specify whether the lapd transmitter should insert the out- bound lapd message frame octets into the nr byte- field, or in the gc-byte-field, within each outbound e3 frame. writing a "1" configures the lapd transmitter to in- sert the octets of the outbound lapd message frame into the nr byte-field, within each outbound e3 frame. writing in "0" configures the lapd transmitter to insert the octets of the outbound lapd message frame into the gc byte-field, within each outbound e3 frame. bit 2 - txais enable this read/write bit-field allows the user to command the transmit e3 framer to transmit an ais pattern, upon demand. writing a "0" to this bit-field allows the transmit ds3/ e3 framer block to transmit internally generated data (e.g., the itu-t g.832 compatible e3 frames with the e3 payload data) to the remote terminal. writing a "1" to this bit-field causes the transmit ds3/e3 fram- er block to transmit an all "1s" pattern to the remote te r m i n a l . n ote : if the transmit ds3/e3 framer block is transmitting an ais pattern to the remote terminal, then it is not trans- mitting any e3 frames. consequently, if this command is invoked, the remote terminal will experience an oof (out of frame) condition. bit 1 - txlos enable this read/write bit-field allows the user to command the transmit e3 framer to transmit an los pattern, upon demand. writing a "0" to this bit-field allows the transmit e3 framer to transmit internally generated data (e.g., the itu-t g.832 compatible e3 frames with atm cell da- ta) to the remote terminal. writing a "1" to this bit- field causes the transmit ds3/e3 framer block to transmit an "all 0s" pattern to the remote terminal. n ote : if the transmit ds3/e3 framer block is transmitting an los pattern to the remoteterminal, then it is not trans- mitting any e3 frames. consequently, the remote terminal will experience an los (loss of signal) and oof (out of frame) condition. bit 0 - marx (ferf and febe bit-field loopback) this read/write bit-field allows the user to specify whether the value of the ferf and febe bit-fields, in the outbound e3 frames, should be based upon re- ceive ds3/e3 framer conditions or upon the content of the tx ma byte register (address = 0x2a). ferf and febe values are based upon receive e3 framer conditions if the user selects receive ds3/e3 framer condi- tions, then the transmit ds3/e3 framer block will set and clear the ferf and febe bit-fields in response to the following conditions. a. ferf bit-field if the receive ds3/e3 framer block (in the same channel) is currently experiencing an los, ais, or lof condition, then the transmit ds3/e3 framer block will set the ferf bit-field (in the outbound e3 frame) to "1". conversely, if the receive ds3/e3 framer block is not experiencing any of these condi- tions, then the transmit e3 framer will set the ferf bit-field (in the outbound e3 frame) to "0". b. febe bit-field if the receive ds3/e3 framer block detects a bip-8 error in the incoming e3 frame, then the transmit ds3/e3 framer block will set the febe bit-field (in the outbound e3 frame) to "1". conversely, if the re- ceive ds3/e3 framer block does not detect a bip-8 error in the incoming e3 frame, then the transmit ds3/e3 framer block will set the febe bit-field (in the e3 outbound e3 frame) to "0". febe and ferf values are based upon the contents of the tx ma byte register if the user selects the contents of the tx ma byte reg- ister, then whatever value has been written into bit 7 (ferf), within the tx ma byte register (address = txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl in nr not used txais enable txlos enable txmarx ro ro ro r/w ro r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 96 2ah), will be the value of the ferf bit-field, in the outbound e3 frame. likewise, whatever value has been written into bit 6 (febe) within the tx ma byte register, will be the value of the febe bit-field, in the outbound e3 frame. writing a "1" into bit 0 (max) within the tx e3 config- uration register configures the transmit ds3/e3 framer block to set the ferf and febe bit-fields (in the outbound e3 frames) to values based upon re- ceive e3 framer conditions. writing a "0" into this bit- field configures the transmit ds3/e3 framer block to set the febe and febe bit-fields (in the outbound e3 frames) to the values written into bit-fields 6 and 7 within the tx ma byte register. 2.3.6.2 transmit e3 lapd configuration reg- ister (e3, itu-t g.832) bit 3 - auto retransmit this read/write bit-field permits the user to configure the lapd transmitter to either transmit the lapd message frame only once, or repeatedly at one-sec- ond intervals. writing a "0" to this bit-field configures the lapd transmitter to transmit the lapd message frame once. afterwards, the lapd transmitter will halt transmission, until it has commanded to transmit an- other lapd message frame. writing a "1" to this bit-field configures the lapd transmitter to transmit the lapd message frame re- peatedly at one-second intervals. in this configura- tion, the lapd transmitter will repeat its transmission of the lapd message frame until it has been dis- abled. bit 1 - txlapd message length select this read/write bit-field permits the user to select the length of the outbound lapd message frame. setting this bit-field to "0" configures the outbound lapd message frame to be 76 bytes in length. set- ting this bit-field to "1" configures the outbound lapd message frame to be 82 bytes in length. bit 0 - txlapd enable this read/write bit-field permits the user to enable or disable the lapd transmitter. the lapd transmitter must be enabled before it can be commanded to transmit a lapd message frame (containing a pmdl message) via the outbound e3 frames, to the remote terminal. writing a "0" disables the lapd transmitter (default condition). writing a "1" enables the lapd transmit- ter. n ote : for information on the lapd transmitter, please see section 3.2.3.2. 2.3.6.3 transmit e3 lapd status and interrupt register (e3, itu-t g.832) bit 3 - txdl start this read/write bit-field permits the user to com- mand the lapd transmitter to do the following. ? scan through the pmdl message, within the trans- mit lapd message buffer, and search for a string of five (5) consecutive "1s". the lapd transmitter will then insert (or stuff) a "0" into the pmdl mes- txe3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable ro ro ro ro r/w ro r/w r/w 00001000 txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 97 sage data, immediately following any string of 5 consecutive "1s". ? read in this stuffed pmdl message from the trans- mit lapd message buffer, and encapsulate it into a lapd message frame. ? fragment the resulting lapd message frame into octets. ? insert these octets into either the gc byte-field or the nr byte-field (depending upon the user's selec- tion) into each outbound e3 frame. a "0" to "1" transition, in this bit-field commands the lapd transmitter to initiate the above-mentioned procedure. n ote : once the user has commanded the lapd transmit- ter to start transmission, the lapd transmitter will repeat the above-mentioned process once each second and will insert flag sequence octets into the outbound lapd chan- nel, during the idle periods between transmissions. bit 2 - txdl busy this read-only bit-field permits the user to poll or monitor the status of the lapd transmitter to see if it has completed its transmission of the lapd message frame. the lapd transmitter will set this bit-field to "1", while it is in the process of transmitting the lapd message frame. however, the lapd transmitter will clear this bit-field to "0" once it has completed its transmission of the lapd message frame. bit 1 - txlapd interrupt enable this read/write bit-field permits the user to enable or disable the lapd message frame transmission com- plete interrupt. writing a "0" to this bit-field disables this interrupt. writing a "1" to this bit-field enables this interrupt. bit 0 - txlapd interrupt status this reset-upon-read bit-field permits the user to determine if the lapd message frame transmission complete interrupt has occurred since the last read of this register. if this bit-field contains a "1" then the lapd message frame transmission complete inter- rupt has occurred since the last read of this register. conversely, if this bit-field contains a "0" then it has not. 2.3.6.4 transmit e3 gc byte register (e3, itu- t g.832) this read/write byte-field permits the user to specify the contents of the gc byte-field in each outbound e3 frame. n ote : the contents of this register is ignored, if the lapd transmitter is enabled and has been configured to insert the comprising octets of an outbound lapd message frame into the gc byte-field of each outbound e3 frame (e.g., if dlinnr = "0"). 2.3.6.5 transmit e3 ma byte register (e3, itu- t g.832) the bit-format of the txe3 ma byte register de- pends upon whether the channel has been config- ured to support the november 1995 or the october 1998 revision of the itu-t g.832 framing format for e3. the bit-format of the txe3 ma byte register, for each of these cases is discussed below. 2.3.6.5.1 the november 1995 revision if the channel has been configured to support the november 1995 revision of the itu-t g.832 fram- ing format for e3, then the bit-format of the txe3 ma byte register is as presented below. txe3 gc byte register (address = 0x35) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txgc[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 98 this read/write byte-fields permits the user to speci- fy the contents of the ma byte-field in each outbound e3 frame. n ote : the values written into bit-fields 6 (febe) and 7 (ferf) are inserted into outbound e3 frames, only if bit- field 0 (max) within the tx e3 configuration register (address = 0x28) is set to "0". otherwise, the transmit ds3/e3 framer block will set the ferf and febe values, within each outbound e3 frame, to values based upon receive ds3/e3 framer block conditions. 2.3.6.5.2 the october 1998 revision if the channel has been configured to support the october 1998 revision of the itu-t g.832 framing format for e3; then the bit-format of the txe3 ma byte register is as presented below. this read/write byte-fields permits the user to speci- fy the contents of the ma byte-field in each outbound e3 frame. n ote : the values written into bit-fields 6 (febe) and 7 (ferf) are inserted into outbound e3 frames, only if bit- field 0 (max) within the tx e3 configuration register (address = 0x28) is set to "0". otherwise, the transmit ds3/e3 framer block will set the ferf and febe values, within each outbound e3 frame, to values based upon receive ds3/e3 framer block conditions. 2.3.6.6 transmit e3 nr byte register (e3, itu- t g.832) this read/write byte-field permits the user to specify the contents of the nr byte-field in each outbound e3 frame. n ote : the contents of this register is ignored, if the lapd transmitter is enabled and has been configured to insert the comprising octets of an outbound lapd message frame into the nr byte-field of each outbound e3 frame (e.g., if dlinnr = "1"). 2.3.6.7 transmit e3 ttb-0 register (e3, itu-t g.832) txe3 ma byte register (address = 0x36) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 transmit ma byte ferf febe payload type payload dependent timing marker r/w r/w r/w r/w r/w r/w r/w r/w 00010000 txe3 ma byte register (address = 0x36) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 transmit ma byte ferf febe payload type mfi[1:0] ssm r/w r/w r/w r/w r/w r/w r/w r/w 00010000 txe3 nr byte register (address = 0x37) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txnr[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00010000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 99 this read/write byte-field, along with the tx ttb-1 through tx ttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the re- mote receiving terminal will use this sequence of bytes to verify that it is connected to the proper trans- mitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the first of a set of 16 e3 frames, the transmit ds3/ e3 framer block will read in the contents of this regis- ter, and insert it into the tr byte-field, within the very next outbound e3 frame. this particular byte-field should contain the pattern "[1, c6, c5, c4, c3, c2, c1, c0]" where the bits c6 through c0 are the results of a crc-7 calculation over the previous 16-byte frame. n ote : the XRT72L50 framer ic will not compute this crc-7 value. it is up to the user's hardware and/or soft- ware to compute this value, prior to writing it into this regis- ter. 2.3.6.8 transmit e3 ttb-1 register (e3, itu-t g.832) this read/write byte-field, along with the txttb-0 and txttb-2 through txttb-15 register permit a us- er to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving terminal will use this se- quence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 regis- ters, and insert them into the tr byte of the outbound e3 frame. in the second of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte- field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-2 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.9 transmit e3 ttb-2 register (e3, itu-t g.832) this read/write byte-field, along with the txttb-0, txttb-1 and txttb-3 through txttb-15 register permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the re- mote terminal. the remote receiving terminal will use this sequence of bytes to verify that it is connect- ed to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these txe3 ttb-0 register (address = 0x38) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb0[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 10010000 txe3 ttb-1 register (address = 0x39) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-1[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-2 register (address = 0x3a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-2[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 100 16 registers, and insert them into the tr byte of the outbound e3 frame. in the third of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1, and tx ttb-3 through tx ttb-15 are used to trans- mit 15 ascii characters required for the e.164 num- bering format. 2.3.6.10 transmit e3 ttb-3 register (e3, itu-t g.832) this read/write byte-field, along with the txttb-0 through txttb-2 and txttb-4 through txttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the fourth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1, tx ttb-2 and tx ttb-4 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.11 transmit e3 ttb-4 register (e3, itu-t g.832) this read/write byte-field, along with the txttb-0 through txttb-3 and txttb-5 through txttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the fifth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-3 and tx ttb-5 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.12 transmit e3 ttb-5 register (e3, itu-t g.832) txe3 ttb-3 register (address = 0x3b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-3[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-4 register (address = 0x3c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-4[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 101 this read/write byte-field, along with the tx ttb-0 through tx ttb-4 and tx ttb-6 through tx ttb-15 registers allows a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the sixth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-4 and tx ttb-6 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.13 transmit e3 ttb-6 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-5 and tx ttb-7 through tx ttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the seventh of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-5 and tx ttb-7 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.14 transmit e3 ttb-7 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-6 and tx ttb-8 through tx ttb-15 registers allows a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the eighth of a set of 16 txe3 ttb-5 register (address = 0x3d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-5[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-6 register (address = 0x3e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-6[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-7 register (address = 0x3f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-7[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 102 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-6 and tx ttb-8 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.15 transmit e3 ttb-8 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-7 and tx ttb-9 through tx ttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the ninth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-7 and tx ttb-9 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.16 transmit e3 ttb-9 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-8 and tx ttb-10 through tx ttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the tenth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-8 and tx ttb-10 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.17 transmit e3 ttb-10 register (e3, itu-t g.832) txe3 ttb-8 register (address = 0x40) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-8[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-9 register (address = 0x41) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-9[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 103 this read/write byte-field, along with the tx ttb-0 through tx ttb-9 and tx ttb-11 through tx ttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving termi- nal will use this sequence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the eleventh of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-9 and tx ttb-11 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.18 transmit e3 ttb-11 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-10 and tx ttb-12 through tx ttb- 15 registers permit a user to define a trail access point identifier sequence of bytes, that will be trans- mitted to the remote terminal. the remote receiv- ing terminal will use this sequence of bytes to verify that it is connected to the proper transmitting termi- nal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the twelfth of a set of 16 e3 frames, the transmit ds3/e3 fram- er block will read in the contents of this register, and insert it into the tr byte-field, within the very next out- bound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-10 and tx ttb-12 through tx ttb- 15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.19 3.3.2.77 transmit e3 ttb-12 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-11 and tx ttb-13 through tx ttb- 15 registers permit a user to define a trail access point identifier sequence of bytes, that will be trans- mitted to the remote terminal. the remote receiv- ing terminal will use this sequence of bytes to verify that it is connected to the proper transmitting termi- nal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the thir- txe3 ttb-10 register (address = 0x42) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-10[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-11 register (address = 0x43) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-11[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-12 register (address = 0x44) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-12[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 104 teenth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-11 and tx ttb-13 through tx ttb- 15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.20 transmit e3 ttb-13 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-12, tx-ttb-14, and tx ttb-15 regis- ters permit a user to define a trail access point iden- tifier sequence of bytes, that will be transmitted to the remote terminal. the remote receiving terminal will use this sequence of bytes to verify that it is con- nected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the fourteenth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-12, tx ttb-14 and tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.21 transmit e3 ttb-14 register (e3, itu-t g.832) this read/write byte-field, along with the tx ttb-0 through tx ttb-13 and tx ttb-15 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote termi- nal. the remote receiving terminal will use this se- quence of bytes to verify that it is connected to the proper transmitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 regis- ters, and insert them into the tr byte of the outbound e3 frame. in the fifteenth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte- field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-13 and tx ttb-15 are used to trans- mit 15 ascii characters required for the e.164 num- bering format. 2.3.6.22 transmit e3 ttb-15 register (e3, itu-t g.832) txe3 ttb-13 register (address = 0x45) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-13[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-14 register (address = 0x46) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-14[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 ttb-15 register (address = 0x47) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txttb-15[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 105 this read/write byte-field, along with the tx ttb-0 through tx ttb-14 registers permit a user to define a trail access point identifier sequence of bytes, that will be transmitted to the remote terminal. the re- mote receiving terminal will use this sequence of bytes to verify that it is connected to the proper trans- mitting terminal. the transmit ds3/e3 framer block will take the contents of these 16 registers, and insert them into the tr byte of the outbound e3 frame. in the sixteenth of a set of 16 e3 frames, the transmit ds3/e3 framer block will read in the contents of this register, and insert it into the tr byte-field, within the very next outbound e3 frame. the contents of this register, along with tx ttb-1 through tx ttb-15 are used to transmit 15 ascii characters required for the e.164 numbering format. 2.3.6.23 transmit e3 fa1 byte error mask reg- ister (e3, itu-t g.832) this read/write bit-field permits the user to insert er- rors into the framing alignment octet, fa1 of each outbound e3 frame. the user may wish to do this for equipment testing purposes. prior to transmission, the transmit ds3/e3 framer block reads in the fa1 byte, and performs an xor operation with it and the contents of this register. the results of this operation are written back into the fa1 octet position, in each outbound e3 frame. consequently, to insure errors are not injected into the fa1 octet of the outbound e3 frames, the contents of this register must be set to all 0s (the default value). 2.3.6.24 transmit e3 fa2 byte error mask reg- ister (e3, itu-t g.832) this read/write bit-field permits the user to insert er- rors into the framing alignment octet, fa2 of each outbound e3 frame. the user may wish to do this for equipment testing purposes. prior to transmission, the transmit ds3/e3 framer block reads in the fa2 byte, and performs an xor operation with it and the contents of this register. the results of this operation are written back into the fa2 octet position, in each outbound e3 frame. consequently, to insure errors are not injected into the fa2 octet of the outbound e3 frames, the contents of this register must be set to all "0s" (the default value). 2.3.6.25 transmit e3 bip-8 error mask register (e3, itu-t g.832) txe3 fa1 error mask register (address = 0x48) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txfa1_error_mask_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 fa2 error mask register (address = 0x49) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txfa2_error_mask_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txe3 bip-8 error mask register (address = 0x4a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txbip-8_error_mask_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 106 this read/write bit-field permits the user to insert er- rors into em (error monitor) octet of each outbound e3 frame. the user may wish to do this for equip- ment testing purposes. prior to transmission, the transmit ds3/e3 framer block reads in the em byte, and performs an xor operation with it and the con- tents of this register. the results of this operation are written back into the em octet position, in each out- bound e3 frame. consequently, to insure errors are not injected into the em octet of the outbound e3 frames, the contents of this register must be set to all "0s" (the default value). 2.3.7 transmit e3 framer configuration regis- ters (itu-t g.751) 2.3.7.1 transmit e3 configuration register (itu-t g.751) bit 7 - txbip-4 enable this read/write bit-field permits the user to configure the transmit section of the channel, to compute an insert the bip-4 value into each outbound e3 frame. setting this bit-field to "0", configures the transmit section of the channel to not compute and insert the bip-4 value into each outbound e3 frame. in- stead these four bits will contain data that has been input via the input interface. setting this bit-field to "1", configures the transmit section of the channel to compute and insert the bip-4 value into each outbound e3 frame. n ote : for more information on these bip-4 calculations, please see section 4.2.4.2.2. bit 6, 5, txasourcesel[1:0] these two read/write bit-fields combine to specify the source of the a-bit, within each outbound e3 frame. the relationship between these two bit-fields and the resulting source of the a bit is tabulated be- low. n ote : for more information on the a-bit, within the itu-t g.751 frame, please see section 4.1.1.1. bits 4, 3, txnsourcesel[1:0] these two read/write bit-fields combine to specify the source of the n-bit, within each outbound e3 frame. the relationship between these two bit-fields and the resulting source of the n bit is tabulated be- low. txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w 00000000 t x as ource s el [1:0] s ource of a b it 00 txe3 service bits register (address = 0x35) 01 transmit overhead data input interface 10 transmit payload data input interface 11 functions as a febe (far-end-block error) bit-field. this bit-field is set to "0", if the near-end receive section (within this chip) detects no bip-4 errors within the incoming e3 frames. this bit-field is set to "1", if the near-end receive section (within this chip) detects a bip-4 error within the incoming e3 frame. t x ns ource s el [1:0] s ource of n b it 00 txe3 service bits register (address = 0x35) XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 107 n ote : for more information on the n-bit, within the itu-t g.751 frame, please see section 4.1.1.2. bit 2 - txais enable this read/write bit-field permits the user to configure the transmit section of the framer ic to transmit an ais pattern to the remote terminal setting this bit-field to "0" configures the transmit section (of the chip) to transmit data in a normal man- ner (e.g., as received via the input interface). setting this bit-field to "1" configures the transmit section (of the chip) to transmit an "all ones" pattern (e.g., an ais pattern) to the remote terminal. n ote : for more information on the ais pattern, please see section 4.2.4.2.1.1. bit 1 - txlos enable this read/write bit-field permits the user to configure the transmit section of the framer ic to transmit an los (e.g., all zeros) pattern to the remote terminal setting this bit-field to "0" configures the transmit section (of the chip) to transmit data in a normal man- ner (e.g., as received via the input interface). setting this bit-field to "1" configures the transmit section (of the chip) to transmit an "all zeros" pattern (e.g., an los pattern) to the remote terminal. n ote : for more information on the los pattern, please see section 4.2.4.2.1.2. bit 0 - txfas source select this read/write bit-field permits the user to configure the transmit section of the channel to either: a. internally generate the fas (framing alignment signal) pattern, within the outbound e3 frames, or to b. use the input interface as the source for the fas pattern. setting this bit-field to "0" configures the transmit section of the channel to internally generate the fas pattern, for each outbound e3 frame. setting this bit-field to "1" configures the transmit section of the channel to use the input interface as the source for the fas pattern. n ote : for more information on the fas pattern, please see section 4.1. 2.3.7.2 transmit e3 lapd configuration reg- ister (itu-t g.751) bit 3 - auto retransmit this read/write bit-field permits the user to configure the lapd transmitter to either transmit the lapd message frame only once, or repeatedly at one-sec- ond intervals. writing a "0" to this bit-field configures the lapd transmitter to transmit the lapd message frame once. afterwards, the lapd transmitter will halt transmission, until it has commanded to transmit an- other lapd message frame. writing a "1" to this bit-field configures the lapd transmitter to transmit the lapd message frame re- peatedly at one-second intervals. in this configura- tion, the lapd transmitter will repeat its transmission of the lapd message frame until it has been dis- abled. bit 1 - txlapd message length select this read/write bit-field permits the user to select the length of the outbound lapd message frame. setting this bit-field to "0" configures the outbound lapd message frame to be 76 bytes in length. set- 01 transmit overhead data input interface 10 transmit lapd controller 11 transmit payload data input interface . t x ns ource s el [1:0] s ource of n b it txe3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used auto retrans- mit not used txlapd msg length txlapd enable ro ro ro ro r/w ro r/w r/w 00001000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 108 ting this bit-field to "1" configures the outbound lapd message frame to be 82 bytes in length. bit 0 - txlapd enable this read/write bit-field permits the user to enable or disable the lapd transmitter. the lapd transmitter must be enabled before it can be commanded to transmit a lapd message frame (containing a pmdl message) via the outbound e3 frames, to the remote te r m i n a l . writing a "0" disables the lapd transmitter (default condition). writing a "1" enables the lapd transmit- ter. n ote : for information on the lapd transmitter, please see section 4.2.3. 2.3.7.3 transmit e3 lapd status and interrupt register (itu-t g.751) bit 3 - txdl start this read/write bit-field permits the user to com- mand the lapd transmitter to do the following. ? scan through the pmdl message, within the trans- mit lapd message buffer, and search for a string of five (5) consecutive "1s". the lapd transmitter will then insert (or stuff) a "0" into the pmdl mes- sage data, immediately following any string of 5 consecutive "1s". ? read in this stuffed pmdl message from the trans- mit lapd message buffer, and encapsulate it into a lapd message frame. ? fragment the resulting lapd message frame into octets. ? insert these octets into either the gc byte-field or the nr byte-field (depending upon the user's selec- tion) in each outbound e3 frame. a "0" to "1" transition, in this bit-field commands the lapd transmitter to initiate the above-mentioned procedure. n ote : once the user has commanded the lapd transmit- ter to start transmission, the lapd transmitter will repeat the above-mentioned process once each second and will insert flag sequence octets into the outbound lapd chan- nel, during the idle periods between transmissions. bit 2 - txdl busy this read-only bit-field permits the user to poll or monitor the status of the lapd transmitter to see if it has completed its transmission of the lapd message frame. the lapd transmitter will set this bit-field to "1", while it is in the process of transmitting the lapd message frame. however, the lapd transmitter will clear this bit-field to "0" once it has completed its transmission of the lapd message frame. bit 1 - txlapd interrupt enable this read/write bit-field permits the user to enable or disable the lapd message frame transmission com- plete interrupt. writing a "0" to this bit-field disables this interrupt. writing a "1" to this bit-field enables this interrupt. bit 0 - txlapd interrupt status this reset-upon-read bit-field permits the user to determine if the lapd message frame transmission complete interrupt has occurred since the last read of this register. if this bit-field contains a "1" then the lapd message frame transmission complete inter- rupt has occurred since the last read of this register. conversely, if this bit-field contains a "0" then it has not. 2.3.7.4 transmit e3 service bits register (itu- t g.751) txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 109 bit 1 - a bit this read/write bit-field permits the user to define the value of the a bit within a given outbound e3 frame. if the user has configured the source of the a bit to be the txe3 service bits register (by setting txasource[1:0] = 00, within the txe3 configuration register, address = 0x30), then the value written in this bit-field will specify the value of the a bit within the outbound e3 frame. bit 0 - n bit this read/write bit-field permits the user to define the value of the n bit within a given outbound e3 frame. if the user has configured the source of the n bit to be the txe3 service bits register (by setting txnsource[1:0] = 00, within the txe3 configuration register, address = 0x30), then the value written in this bit-field will specify the value of the n bit within the outbound e3 frame. 2.3.7.5 transmit e3 fas mask register - 0 (itu-t g.751) bits 4 - 0, txfas_error_mask_upper[4:0] this read/write bit-field permits the user to insert er- rors into the upper five bits of the framing alignment signal, fas of each outbound e3 frame. the user may wish to do this for equipment testing purposes. prior to transmission, the transmit e3 framer block reads in the upper five (5) bits of the fas value, and performs an xor operation with it and the contents of this register. the results of this operation are written back into the upper five (5) bits of the fas value, in each outbound e3 frame. consequently, to insure er- rors are not injected into the fas of the outbound e3 frames, the contents of this register must be set to all "0s" (the default value). 2.3.7.6 transmit e3 fas error mask register - 1 (itu-t g.751) bits 4 - 0, txfas_error_mask_lower[4:0] this read/write bit-field permits the user to insert er- rors into the lower five bits of the framing alignment signal, fas of each outbound e3 frame. the user may wish to do this for equipment testing purposes. prior to transmission, the transmit e3 framer block reads in the lower five (5) bits of the fas value, and performs an xor operation with it and the contents of this register. the results of this operation are written back into the lower five (5) bits of the fas value, in each outbound e3 frame. consequently, to insure er- rors are not injected into the fas of the outbound e3 frames, the contents of this register must be set to all "0s" (the default value). txe3 service bits register (address = 0x35) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used a bit n bit ro ro ro ro ro ro r/w r/w 00000010 txe3 fas error mask register - 0 (address = 0x48) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txfas_error_mask_upper[4:0] ro ro ro r/w r/w r/w r/w r/w 00000000 txe3 fas error mask register - 1 (address = 0x49) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txfas_error_mask_lower[4:0] ro ro ro r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 110 2.3.7.7 transmit e3 bip-4 error mask register (itu-t g.751) bits 3 - 0: txbip-4 mask[3:0] this read/write bit-field permits the user to insert er- rors into the bip-4 value within each outbound e3 frame. the user may wish to do this for equipment testing purposes. prior to transmission, the transmit ds3/e3 framer block reads in the bip-4 value, and performs an xor operation with it and the contents of this register. the results of this operation are written back into the bip-4 nibble position, in each outbound e3 frame. consequently, to insure errors are not in- jected into the bip-4 value of the outbound e3 frames, the contents of this register must be set to all "0s" (the default value). n ote : this register is ignored if bit 7 (tx bip-4 enable) within the txe3 configuration register (address = 0x30) is set to 0. 2.3.8 performance monitor registers 2.3.8.1 pmon line code violation count reg- ister - msb this reset-upon-read register, along with the pmon lcv event count register - lsb (address = 0x51) contains a 16-bit representation of the number of line code violations that have been detected by the re- ceive ds3/e3 framer block, since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.8.2 pmon line code violation count reg- ister - lsb this reset-upon-read register, along with the pmon lcv event count register - lsb (address = 0x50) contains a 16-bit representation of the number of line code violations that have been detected by the re- ceive ds3/e3 framer block, since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 2.3.8.3 pmon framing bit/byte error count register - msb txe3 bip-4 error mask register (address = 0x4a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txbip-4 mask[3:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 pmon lcv event count register - msb (address = 0x50) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv count - high byte rur rur rur rur rur rur rur rur 00000000 pmon lcv event count register - lsb (address = 0x51) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv count - low byte rur rur rur rur rur rur rur rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 111 this reset-upon-read register, along with the pmon framing bit/byte error count register - lsb (ad- dress = 0x53) contains a 16-bit representation of the number of framing bit or byte errors that have been detected by the receive ds3/e3 framer block, since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expres- sion. 2.3.8.4 pmon framing bit/byte error count register - lsb this reset-upon-read register, along with the pmon framing bit/byte error count register - msb (ad- dress = 0x52) contains a 16-bit representation of the number of framing bit or byte errors that have been detected by the receive ds3/e3 framer block, since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expres- sion. 2.3.8.5 pmon parity error count register - msb this reset-upon-read register, along with the pmon parity error count register - lsb (address = 0x55) contains a 16-bit representation of the number of p- bit errors (for ds3 applications), bip-4 errors (for e3/ itu-t g.751 applications) or bip-8 errors (for e3/ itu-t g.832 applications) that have been detected by the receive ds3/e3 framer block, since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.8.6 pmon parity error count register - lsb pmon framing bit/byte error count register - msb (address = 0x52) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit/byte error count - high byte rurrurrurrurrurrurrurrur 00000000 pmon framing bit/byte error count register - lsb (address = 0x53) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit/byte error count - low byte rurrurrurrurrurrurrurrur 00000000 pmon parity error count register - msb (address = 0x54) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - high byte rurrurrurrurrurrurrurrur 00000000 pmon parity error count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - low byte rurrurrurrurrurrurrurrur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 112 this reset-upon-read register, along with the pmon parity error count register - msb (address = 0x54) contains a 16-bit representation of the number of p- bit errors (for ds3 applications), bip-4 errors (for e3/ itu-t g.751 applications) or bip-8 errors (for e3/ itu-t g.832 applications) that have been detected by the receive ds3/e3 framer block, since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 2.3.8.7 pmon febe event count register - msb this reset-upon-read register, along with the pmon febe event count register - lsb (address = 0x57) contains a 16-bit representation of the number of febe events that have been detected by the receive ds3/e3 framer block, since the last read of these registers. this register contains the msb (or upper- byte) value of this 16 bit expression. 2.3.8.8 pmon febe event count register - lsb this reset-upon-read register, along with the pmon febe event count register - msb (address = 0x56) contains a 16-bit representation of the number of febe events that have been detected by the receive ds3/e3 framer block, since the last read of these registers. this register contains the lsb (or lower- byte) value of this 16 bit expression. 2.3.8.9 pmon cp-bit error event count regis- ter - msb this reset-upon-read register, along with the pmon cp-bit error count register - lsb (address = 0x59) contains a 16-bit representation of the number of cp- bit errors that have been detected by the receive ds3/e3 framer block (within the channel), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. n ote : this register is only active if the channel has been configured to operate in the ds3, c-bit parity framing for- mat. 2.3.8.10 pmon cp-bit error event count regis- ter - lsb pmon febe event count register - msb (address = 0x56) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - high byte rur rur rur rur rur rur rur rur 00000000 pmon febe event count register - lsb (address = 0x57) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - low byte rur rur rur rur rur rur rur rur 00000000 pmon cp-bit error count register - msb (address = 0x58) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error count - high byte rur rur rur rur rur rur rur rur 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 113 this reset-upon-read register, along with the pmon cp-bit error count register - msb (address = 0x58) contains a 16-bit representation of the number of cp- bit errors that have been detected by the receive ds3/e3 framer block (within the channel), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. n ote : this register is only active if the channel has been configured to operate in the ds3, c-bit parity framing for- mat. 2.3.8.11 pmon holding register each of the above-defined pmon registers are 16 bit reset-upon-read registers. however, the bi-drec- tional data bus (of the framer ic) is only 8-bits wide. as a consequence, whenever the microprocessor in- tends to read a pmon register, there are two things to bear in mind. 1. this microprocessor is going to require two read accesses in order read out the full 16-bit expres- sion of these pmon registers. 2. the entire 16-bit expression (of a given pmon register) is going to be reset to 0x0000, immedi- ately after the microprocessor has completed its first read access to the pmon register. hence, the contents of the other byte (of the partially read pmon register) will reside within the pmon holding register. 2.3.8.12 one-second error status register bit 1 - errored second this bit field indicates whether or not an error has oc- curred within the last one-second accumulation in- terval. this bit-field will be set to 1 if at least one er- ror has occurred during the last one-second accu- mulation interval. conversely, this bit-field will be set to "0" if no errors has occurred during the last one- second accumulation interval. bit 0 - severely errored second this bit-field indicates whether or not the error rate in the last one-second interval was greater than 1 in 1000. a "0" indicates that the error rate did not ex- ceed 1 in 1000 in the last one-second interval. 2.3.8.13 one-second line code violation accu- mulator register - msb pmon cp-bit error count register - lsb (address = 0x59) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error count - low byte rurrurrurrurrurrurrurrur 00000000 pmon holding register (address = 0x6c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 pmon holding value rurrurrurrurrurrurrurrur 00000000 one-second error status register (address = 0x6d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 errored second severely errored second ro ro ro ro ro ro ro ro 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 114 this read-only register, along with the lcv - one- second accumulator register - lsb (address = 0x6f) contains a 16-bit representation of the number of lcv (line code violation) events that have been detected by the receive ds3/e3 framer block, within the last one-second sampling period. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.8.14 one-second line code violation accu- mulator register - lsb this read-only register, along with the lcv - one- second accumulator register - msb (address = 0x6e) contains a 16-bit representation of the number of lcv (line code violation) events that have been detected by the receive ds3/e3 framer block, within the last one-second sampling period. this register contains the lsb (or lower-byte) value of this 16 bit expression. 2.3.8.15 one-second frame parity error accu- mulator register - msb this read-only register, along with the frame parity errors - one-second accumulator register - lsb (address = 0x71) contains a 16-bit representation of the number of frame parity errors that have been de- tected by the receive ds3/e3 framer block, within the last one-second sampling period. this register contains the msb (or upper-byte) value of this 16 bit expression. n otes : 1. for ds3 applications, the frame-parity errors - one second accumulator register contains the number of p-bit errors that have been detected in the last one-second sampling period. 2. for e3, itu-t g.751 applications, the frame-par- ity error - one second accumulator register con- tains the number of bip-4 errors that have been detected in the last one-second sampling period. 3. for e3, itu-t g.832 applications, the frame-par- ity error - one second accumulator register con- tains the number of bip-8 errors that have been detected in the last one-second sampling period. 2.3.8.16 one-second frame parity error accu- mulator register - lsb lcv - one-second accumulator register - msb (address = 0x6e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv - one-second count - high byte ro ro ro ro ro ro ro ro 00000000 lcv - one-second accumulator register - lsb (address = 0x6f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv - one-second count - low byte ro ro ro ro ro ro ro ro 00000000 frame parity errors - one-second accumulator register - msb (address = 0x70) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 frame parity error count - high byte ro ro ro ro ro ro ro ro 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 115 this read-only register, along with the frame parity errors - one-second accumulator register - msb (address = 0x70) contains a 16-bit representation of the number of frame parity errors that have been de- tected by the receive ds3/e3 framer block, within the last one-second sampling period. this register contains the lsb (or lower-byte) value of this 16 bit expression. n otes : 1. for ds3 applications, the frame-parity errors - one second accumulator register contains the number of p-bit errors that have been detected in the last one-second sampling period. 2. for e3, itu-t g.751 applications, the frame-par- ity error - one second accumulator register con- tains the number of bip-4 errors that have been detected in the last one-second sampling period. 3. for e3, itu-t g.832 applications, the frame-par- ity error - one second accumulator register con- tains the number of bip-8 errors that have been detected in the last one-second sampling period. 2.3.8.17 one-second frame cp-bit error accu- mulator register - msb this read-only register, along with the frame cp-bit error - one-second accumulator register - lsb (ad- dress = 0x73) contains a 16-bit representation of the number of cp bit errors tjhat have been detected by the receive ds3/e3 framer block, within the last one-second sampling period. this register contains the msb (or upper byte) value of this 16-bit expres- sion. n ote : this register is only active if the channel has been configured to operate in the ds3, c-bit parity framing for- mat. 2.3.8.18 one-second frame cp-bit error accu- mulator register - lsb this read-only register, along with the frame cp-bit error - one-second accumulator register - msb (ad- dress = 0x72) contains a 16-bit representation of the number of cp bit errors tjhat have been detected by the receive ds3/e3 framer block, within the last one-second sampling period. this register contains the lsb (or lower byte) value of this 16-bit expres- sion. n ote : this register is only active if the channel has been configured to operate in the ds3, c-bit parity framing for- mat. frame parity errors - one-second accumulator register - lsb (address = 0x71) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 frame parity error count - low byte ro ro ro ro ro ro ro ro 00000000 frame cp-bit errors - one-second accumulator register - msb (address = 0x72) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error count - high byte ro ro ro ro ro ro ro ro 00000000 frame parity errors - one-second accumulator register - lsb (address = 0x73) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error count - low byte ro ro ro ro ro ro ro ro 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 116 2.3.8.19 line interface drive register bit 5 - reqb - (receive equalization bypass con- trol) this read/write bit-field permits the user to control the state of the reqb output pin of the framer de- vice. this output pin is intended to be connected to either the reqb or the reqen input pin of the ds3/ e3 liu ic. if the user connects the reqb output pin of the framer to either the reqdis or the reqen input pin of the ds3/e3 liu ic, then the user will have mi- croprocessor control over the state of the receive equalizer within the ds3/e3 liu ic. writing a "1" to this bit-field causes the channel to toggle the reqb output pin "high". writing a "0" to this bit-field causes the channel to toggle the reqb output pin "low". n ote : if the customer is not using an exar xrt73l0x ds3/e3/sts-1 liu ic, then this bit-field and the reqb out- put pin can be used for other purposes. bit 4 - taos - (transmit all ones signal) this read/write bit-field permits the user to control the state of the taos output pin of the framer device. this output pin is intended to be connected to the taos input pin of the ds3/e3 liu ic. if the user forc- es this signal to toggle "high", then the liu device will transmit an "all ones" pattern onto the line. con- versely, if the user commands this output signal to toggle "low" then the liu ic will proceed to transmit data based upon the pattern that it receives via the txpos[n] and txneg[n] output pins (of the framer ic). writing a "1" to this bit-field will cause the taos[n] output pin to toggle "high". writing a "0" to this bit- field will cause this output pin to toggle "low". n ote : if the customer is not using an exar xrt73l0x ds3/e3/sts-1 liu ic, then this bit-field, and the taos out- put pin can be used for other purposes. bit 3 - encodis - (b3zs encoder disable) this read/write bit-field allows the user to control the state of the encodis output pin of the framer device. this output pin is intended to be connected to either the encodis or the endecdis input pin of the ds3/ e3 liu ic. if the user forces this signal to toggle "high", then the internal b3zs/hdb3 encoder (within the liu device) will be disabled. conversely, if the us- er command this output signal to toggle "low", then the internal b3zs/hdb3 encoder (within the liu de- vice) will be enabled. writing a "1" to this bit-field causes the channel to toggle the encodis[n] output pin "high". writing a "0" to this bit-field will cause the channel to toggle this output pin "low". n otes : 1. the b3zs/hdb3 encoder, within the ds3/e3 liu device, is not to be confused with the b3zs/hdb3 encoding capable that exists within the transmit section of the framer ic. 2. the user is advised to disabled the b3zs/hdb3 encoder (within the liu ic) if the channel is config- ured to operate in the b3zs/hdb3 line code. 3. if the customer is not using an exar xrt73l0x ds3/e3/sts-1 liu ic, then this bit-field and the encodis[n] output pin can be used for other pur- poses. bit 2 - txlev - (transmit output line build-out select output) this read/write bit-field permits the user to control the state of the txlev[n] output pin of the framer de- vice. this output pin is intended to be connected to the txlev input pin of the ds3/e3 liu ic. if the user commands this signal to toggle high, then the ds3/ e3 liu ic will disable the transmit line build-out cir- cuitry, and will transmit unshaped (square-wave) puls- es onto the line. if the user commands this signal to toggle "low", then the ds3/e3 liu ic will enable the transmit line build-out circuitry, and will transmit shaped pulses onto the line. in order to insure that the transmit output pulses of the liu device meet the dsx-3 isolated pulse tem- plate requirements (per bellcore gr-499-core), the user is advised to set this bit-field to "0", if the length of cable (between the liu transmit output and the dsx-3 cross connect system) is greater than 225 feet. line interface drive register (address = 0x80) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reqb taos encodis txlev rloop lloop r/w r/w r/w r/w r/w r/w r/w r/w 00001000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 117 conversely, the user is advised to set this bit-field to "1", if the length of cable (between the liu transmit output and the dsx-3 cross connect system) is less than 225 feet. writing a "1" to this bit-field commands the framer to toggle the txlev output "high". writing a "0" to this bit-field commands the framer to toggle this output signal "low". n otes : 1. the txlev function is only applicable to ds3 appli- cations. e3 lius do not support this kind of line build out feature. 2. if the customer is not using an exar xrt73l0x ds3/e3 liu ic, then this bit-field and the txlev output pin can be used for other purposes. bit 1 - rloop - (remote loopback) this read/write bit-field permits the user to control the state of the rloop[n] output pin of the framer device. this output pin is intended to be connected to the rloop input pin of the ds3/e3 liu ic. when using exars family of xrt73l0x ds3/e3 liu devices, the state of the rloop and the lloop pins are used to dictate which loop-back mode the liu de- vice will operate in. the following table presents the relationship between the state of these two input pins (or bit-fields) and the resulting loop-back modes. writing a "1" into this bit-field commands the framer ic to toggle the rloop[n] output signal "high". writ- ing a "0" into this bit-field commands the framer ic to toggle this output signal "low". for a detailed description on the operation of a partic- ular exar xrt73l0x ds3/e3 liu, while configured into each of these above-mentioned loop-back modes, please consult the appropriate liu data sheet. currently the following xrt73l0x family of ds3/e3/ sts-1 liu ic data sheets are now available: ? xrt7300 1-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l00 1-channel ds3/e3/sts-1 liu ic (3.3v) ? xrt7302 2-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l03 3-channel ds3/e3/sts-1 liu ic (3.3v) ? xrt73l04 4-channel ds3/e3/sts-1 liu ic (3.3v) ? n ote : if the customer is not using an exar xrt73l0x ds3/e3/sts-1 liu ic, then this bit-field and the rloop[n] output pin can be used for other purposes. bit 0 - lloop - (local loop-back) this read/write bit-field permits the user to control the state of the lloop[n] output pin of the framer device. this output pin is intended to be connected to the lloop input pin of the ds3/e3 liu ic. when using exars family of xrt73l0x ds3/e3 liu devices, the state of the rloop and the lloop pins are used to dictate which loop-back mode the liu de- vice will operate in. the following table presents the relationship between the state of these two input pins (or bit-fields) and the resulting loop-back modes. writing a "1" into this bit-field commands the framer to toggle the lloop[n] output signal "high". writing a "0" into this bit-field commands the framer to toggle this output signal "low". for a detailed description of the operation of a partic- ular exar xrt73l0x ds3/e3 liu, while configured into each of these above-mentioned loop-back rloop lloop r esulting l oop - back m ode of the ds3/e3 liu d evice 0 0 normal operation (no loop-back mode) 0 1 analog local loop-back mode 1 0 remote loop-back mode 1 1 digital local loop-back mode rloop lloop r esulting l oop - back m ode of the ds3/e3 liu d evice 0 0 normal operation (no loop-back mode) 0 1 analog local loop-back mode 1 0 remote loop-back mode 1 1 digital local loop-back mode ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 118 modes, please consult the appropriate liu ic data sheet. currently the following xrt73l0x family of ds3/e3/ sts-1 liu ic data sheets are now available: ? xrt7300 1-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l00 1-channel ds3/e3/sts-1 liu ic (3.3v) ? xrt7302 2-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l03 3-channel ds3/e3/sts-1 liu ic (3.3v) ? xrt73l04 4-channel ds3/e3/sts-1 liu ic (3.3v) n ote : if the customer is not using an exar xrt73l0x ds3/e3/sts-1 liu ic, then this bit-field and the the lloop[n] output pin can be used for other purposes. 2.3.8.20 line interface scan register bit 2 - dmo - (drive monitor output) this read-only bit-field indicates the logic state of the dmo[n] input pin of the framer device. this input pin is intended to be connected to the dmo output pin of an exar xrt73l0x-type of ds3/e3 liu ic. if this bit-field contains a logic "1", then the dmo input pin is "high". an exar xrt73l0x-type of ds3/e3 liu ic will set this pin "high" if the drive monitor cir- cuitry (within the liu device) has not detected any bi- polar signals at the mtip and mring inputs (of the liu device) within the last 128 + 32 bit periods. conversely, if this bit-field contains a logic "0", then the dmo input pin is "high". the ds3/e3 liu ic will set this pin "low" if bipolar signals are being detected at the mtip and mring input pins. as a consequence, the dmo output pin can be thought of as a transmit driver failure indicator. n ote : if this customer is not using an exar xrt73l0x-type of ds3/e3 liu ic, then this input pin and bit-field can be used for a variety of other purposes. bit 1 - rlol - (receive loss of lock) this read-only bit-field indicates the logic state of the rlol[n] input pin of the framer device. this in- put pin is intended to be connected to the rlol out- put pin of an exar xrt73l0x-type of ds3/e3 liu ic. if this bit-field contains a logic "1", then the rlol[n] input pin is "high". an exar xrt73l0x- type of ds3/e3 liu ic will set this pin "high" if the clock recovery phase-locked-loop circuitry (within the liu device) has lost lock with the incoming ds3/e3 data-stream and is not properly recovering clock and data. conversely, if this bit-field contains a logic "0", then the rlol input pin is "low". the ds3/e3 liu ic will hold this pin "low" as long as this clock recovery phase-locked-loop circuitry (within the liu device) is properly locked onto the incoming ds3 or e3 data- stream, and is properly recovering clock and data from this data-stream. for more information on the operation of these exar xrt73l0x-type of ds3/e3/sts-1 liu ics, please consult any of the following data sheets. ? xrt7300 1-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l00 1-channel ds3/e3/sts-1 liu ic (3.3v) ? xrt7302 2-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l03 3-channel ds3/e3/sts-1 liu ic (3.3v) ? xrt73l04 4-channel ds3/e3/sts-1 liu ic (3.3v) n ote : if the customer is not using an exar xrt73l0x- type of ds3/e3/sts-1 ic, then this bit-field, and the rlol[n] input pin can be used for other purposes. bit 0 - rlos - (receive loss of signal) this read-only bit-field indicates the logic state of the rlos[n] input pin of the framer device. this in- put pin is intended to be connected to the rlos out- put pin of the ds3/e3 liu ic. if this bit-field contains a logic "1", then the rlos[n] input pin is "high". the liu device will toggle this signal "high" if it (the liu ic) is currently declaring an los (loss of signal) condition. conversely, if this bit-field contains a logic "0", then the rlos input pin is "low". the liu device will hold this signal "low" if it is not currently declaring an los (loss of signal) condition. for more information on the los declaration and clearance criteria within the exar xrt73l0x type of ds3/e3/sts-1 liu ic, please consult any of the fol- lowing data sheets. ? xrt7300 1-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l00 1-channel ds3/e3/sts-1 liu ic (3.3v) line interface scan register (address = 0x81) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 dmo rlol rlos ro ro ro ro ro ro ro ro 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 119 ? xrt7302 2-channel ds3/e3/sts-1 liu ic (5v) ? xrt73l03 3-channel ds3/e3/sts-1 liu ic (3.3v) ? xrt73l04 4-channel ds3/e3/sts-1 liu ic (3.3v) n ote : asserting the rlos input pin will cause the XRT72L50 framer ic device to generate the change in los condition interrupt and declare an los (loss of sig- nal) condition. therefore, this input pin should not be used as a general purpose input. 2.3.8.21 hdlc control register bit 7 - framer by-pass this read/write bit-field permits the user to enable or disable (by-pass) the ds3/e3 framer circuitry, within a given channel in the XRT72L50 device. this feature permits the user to operate a given channel in the un-framed mode. further, this fea- ture also permits the user to transmit and receive hdlc frames at the ds3 or e3 line rate of 44.736mbps or 34.368mbps, without sacrificing any bandwidth to support the overhead bits/bytes/ setting this bit-field to 1 disables the transmit and receive ds3/e3 framer blocks within the channel. setting this bit-field to 0 enables the transmit and receive ds3/e3 framer blocks. bit 6 - hdlc on this read/write bit-field permits the user to config- ure a given channel to operate in the high-speed hdlc controller mode. if the user invokes this fea- ture, then a transmit and receive byte-wide interface will be enabled, and the channel will be configured to transmit and receive hdlc frames via the ds3 or e3 payload bits. setting this bit-field to 1 configures the channel to operate in the high-speed hdlc controller mode. bit 5 - crc-32 this read/write bit-field permits the user to config- ure a given channel to do the following. 1. to configure the transmit hdlc controller block to compute and append either a crc-16 or a crc-32 value as a trailer to the outbound hdlc frame. 2. to configure the receive hdlc controller block to compute and verify either crc-16 or the crc- 32 value within each inbound hdlc frame. setting this bit-field to 0 configures the transmit hdlc controller block to compute and append the crc-16 value to the end of the outbound hdlc frame. further, this setting also configures the re- ceive hdlc controller block compute and verify the crc-32 value, which has been appended to the end of the inbound hdlc frame. setting this bit-field to 1 configures the transmit hdlc controller block to compute and append the crc-32 value to the end of the outbound hdlc frame. further, this same setting also configures the receive hdlc controller block to compute and verify the crc-32 value, which has been appended to the end of the inbound hdlc frame. n ote : this bit-field is only active if the channel has been configured to operate in the high-speed hdlc controller mode. bit 3 - hdlc loop-back 2.4 t he l oss of c lock e nable f eature the timing for the microprocessor interface section, originates from a line rate (e.g., either a 34.368mhz or 44.736 mhz) signal that is provided by either the txinclk[n] or the rxlineclk[n] signals. however, if the framer device experiences a loss of clock signal event such that neither the txinclk[n] nor the rxli- neclk[n] signal are present, then the framer micro- processor interface section cease to function. the framer device offers a loss of clock (loc) pro- tection feature that allows the microprocessor inter- face section to at least complete or terminate an in- process read or write cycle (with the local p) should this loss of clock event occur. the loc cir- cuitry consists of a ring oscillator that continuously checks for signal transitions at the txinclk[n] and rx- lineclk[n] input pins. if a loss of clock signal event occur such that no transitions are occurring on these pins, then the loc circuitry will automatically assert the rdy _dtck signal in order to complete (or termi- hdlc control register (address = 0x82) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framer by-pass hdlc on crc-32 select reserved hdlc loop-back reserved r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 120 nate) the current read or write cycle with the framer microprocessor interface section. the user may enable or disable this loc protection feature by writing to bit 7 (loc enable) within the framer i/o register, as depicted below. writing a "1" to this bit-field enables this loc protec- tion feature. writing a "0" to this bit-field disables this feature. n ote : the ring oscillator can be a source of noise, within the framer chip. hence, there may be situations where the user will wish to disable the loc protection feature. 2.5 u sing the pmon h olding r egister the microprocessor interface section consists of an 8-bit bi-directional data bus. as a consequence, the local p will be able to read from and write to the framer on-chip registers, 8 bit per (read or write) cy- cle. since most of the framer on-chip registers con- tain 8-bits, communicating with the local p, over an 8-bit data bus, is not much of an inconvenience. however, all of the pmon registers, within the framer ic, contain 16 bits. consequently, any reads of the pmon registers, will require two read cycles. to make matters potentially more complicated, these pmon registers are reset-upon-read registers. therefore, the contents of both the msb and lsb registers (of the read pmon register) are reset to zero upon the first of these two read cycles. fortunately, the XRT72L50 framer ic includes a fea- ture that will make reading a pmon register a slightly less complicated task. the framer chip address space contains a read-only register known as the pmon holding register, which is located at 0x6c. whenever the local p reads in an 8-bit value of a given pmon registers (e.g., either the upper-byte or the lower byte value of the pmon register), the other 8-bit value of that pmon register will automatically be loaded into the pmon holding register. as a conse- quence, the other 8-bit value of the pmon register is accessible by reading the pmon holding register. hence, anytime the local p is trying to read in the contents of a pmon register, the first read access must be made directly to one of the 8-bit values of the pmon registers (e.g., for example: the pmon lcv event count register - msb, address = 0x50). how- ever, the second read must always be made to a con- stant location in system memory, the pmon holding register. 2.6 t he i nterrupt s tructure within the f ramer m icroprocessor i nterface s ection the XRT72L50 framer device is equipped with a so- phisticated interrupt servicing structure. this inter- rupt structure includes an interrupt request output, int , numerous interrupt enable registers and numer- ous interrupt status registers. the interrupt servic- ing structure, within each of the three channels con- tains two levels of hierarchy. the top level is at the functional block level (e.g., the receive section, the transmit section, etc.). the lower hierarchical level is at the individual interrupt or source level. each hier- archical level consists of a complete set of interrupt status registers/bits and interrupt enable registers/ bits, as will be discussed below. both of the functional sections, within each channel, are capable of generating interrupt requests to the local p/c. the framer device interrupt structure has been carefully designed to allow the user to quickly determine the exact source of the interrupt (with minimal latency) which will aid the local p/c in determining which interrupt service routine to call up in order to respond to or eliminate the condition(s) causing the interrupt. table 5 lists all of the possible conditions that can generate interrupts, with each functional section of a given channel. address = 0x01, framer i/o control register b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loc enable test pmon interrupt enable reset ami/b3zs* unipolar/ bipolar* txline clk inv rxline clk inv reframe r/w r/w r/w r/w r/w r/w r/w r/w 10100000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 121 each of the three channels, within the XRT72L50 framer device contains an interrupt block that comes equipped with the following registers to support the servicing of these potential interrupt request sources. table 6, 7 , and 8 lists these registers, and their ad- dresses, within the framer ic for ds3, e3 (itu-t g.832) and e3 (itu-t g.751) framing formats. t able 5: l ist of all of the p ossible c onditions that can g enerate i nterrupts within each channel of the XRT72L50 f ramer d evice f unction s ection i nterrupting c ondition transmit section feac message transfer complete (ds3, c-bit parity only) lapd message frame transfer complete (ds3, c-bit parity, all e3) receive section change of status on receive los, oof, ais idle detection validation and removal of received feac code (ds3, c-bit parity only) new pmdl message in receive lapd message buffer. detection of parity errors (e.g., p-bit, cp-bit, bip-4 and bip-8 errors) detection of framing bit/byte errors. framer chip level one-second interrupt t able 6: a l isting of the XRT72L50 f ramer d evice i nterrupt b lock r egisters ( for ds3 a pplications ) a ddress l ocation r egister n ame 0 x 04 block interrupt enable register 0 x 05 block interrupt status register 0 x 12 rxds3 interrupt enable register 0 x 13 rxds3 interrupt status register 0 x 17 rxds3 feac interrupt enable/status register 0 x 18 rxds3 lapd control register 0 x 31 txds3 feac configuration and status register 0 x 34 txds3 lapd status/interrupt register t able 7: a l isting of the XRT72L50 f ramer d evice i nterrupt b lock r egisters ( for e3, itu-t g.832 a pplications ) a ddress l ocation r egister n ame 0 x 04 block interrupt enable register 0 x 05 block interrupt status register 0 x 12 rxe3 interrupt enable register -1 0 x 13 rxe3 interrupt enable register -2 0 x 14 rxe3 interrupt status register - 1 0 x 15 rxe3 interrupt status register - 2 0 x 18 rxe3 lapd control register 0 x 34 txe3 lapd status/interrupt status ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 122 general flow of framer chip interrupt servicing when any of the conditions, presented in table 5 oc- curs, (if their interrupts is enabled), then the framer will generate an interrupt request to the local p/c by asserting the active-low interrupt request output pin, int . shortly after the local p/c has detected the activated int signal, it will enter into the appropri- ate user-supplied interrupt service routine. the first task for the local p/c, while running this interrupt service routine, may be to isolate the source of the in- terrupt request down to the device level (e.g., the XRT72L50 framer device), if multiple peripheral de- vices exist in the user's system. however, once the interrupting peripheral device has been identified, the next task for the local p/c is to determine exactly what feature or functional section within the device re- quested the interrupt. determine the channel requesting the interrupt if the interrupting device turns out to be the XRT72L50 3-channel ds3/e3 framer ic; determine the functional block(s) requesting the interrupt if the interrupt device turns out to be the XRT72L50 ds3/e3 framer ic, then the local c/p must deter- mine which functional block requested the interrupt. hence, upon reaching this state, one of the very first things that the local c/p must do within the user supplied framer interrupt service routine, is to per- form a read of the block interrupt status register (address = 0x05) within the XRT72L50 framer de- vice. the bit format of the block interrupt status reg- ister is presented below. the block interrupt status register presents the in- terrupt request status of each functional block, within the chip. the purpose of the block interrupt status register is to help the local p/c identify which func- tional block(s) has requested the interrupt. whichev- er bit(s) are asserted in this register, identifies which block(s) have experienced an interrupt-generating condition as presented in table 5. once the local p/ c has read this register, it can determine which branch within the interrupt service routine that it must follow, in order to properly service this interrupt. the framer further supports the functional block hi- erarchy by providing the block interrupt enable reg- ister (address = 0x04). the bit format of this register is identical to that for the block interrupt status regis- t able 8: a l isting of the XRT72L50 f ramer d evice i nterrupt b lock r egister ( for e3, itu-t g.751 a pplications ) a ddress l ocation r egister n ame 0 x 04 block interrupt enable register 0 x 05 block interrupt status register 0 x 12 rxe3 interrupt enable register -1 0 x 13 rxe3 interrupt enable register -2 0 x 14 rxe3 interrupt status register - 1 0 x 15 rxe3 interrupt status register - 2 0 x 18 rxe3 lapd control register 0 x 34 txe3 lapd status/interrupt status block interrupt status register (address = 0x05) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt status not used txds3/e3 interrupt status one-second interrupt status ro ro ro ro ro ro ro ro 00000000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 123 ter, and is presented below for the sake of complete- ness. the block interrupt enable register allows the user to individually enable or disable the interrupt requesting capability of the functional blocks, within the framer ic. if a particular bit-field, within this register contains the value "0", then the corresponding functional block has been disabled from generating any interrupt re- quests. conversely, if that bit-field contains the value "1", then the corresponding functional block has been enabled for interrupt generation (e.g., those potential interrupts, within the enabled functional block that are enabled at the source level, are now enabled). the user should be aware of the fact that each functional block, within the framer ic contains anywhere from 1 to 12 potential interrupt sources. each of these lower level interrupt sources contain their own set of inter- rupt enable bits and interrupt status bits, existing in various on-chip registers. interrupt service routing branching: after reading the block interrupt status register. the contents of the block interrupt status register identify which of 3 functional blocks (within the fram- er ic) has requested interrupt service. the local p should use this information in order to determine where, within the interrupt service routing, program control should branch to. table 9 can be viewed as an interrupt service routine guide. it lists each of the functional blocks, that contain a bit-field in the block interrupt status register. additionally, this table also presents a list and addresses of corresponding on- chip registers that the interrupt service routine should branch to and read, based upon the interrupt- ing functional block. table 9, table 10, and table 11 presents the interrupt service routine guide for ds3, e3/itu-t g.832 and e3/itu-t g.751 applications, respectively. block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt status not used txds3/e3 interrupt status one-second interrupt status r/wrororororor/wr/w 00000000 t able 9: i nterrupt s ervice r outine g uide ( for ds3 a pplications ) i nterrupting f unctional b lock t he n ext r egisters to be r ead d uring the i nterrupt s ervice r outine r egister a ddress receive section rxds3 interrupt status register 0 x 013 rxds3 feac interrupt enable/status register 0 x 17 rxds3 lapd control register 0 x 18 transmit section txds3 feac configuration and status register 0 x 31 txds3 lapd status/interrupt register 0 x 34 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 124 once the microprocessor/microcontroller has read the register that corresponds to the interrupting source within the framer, the following things will happen. 1. the asserted interrupt status bit-fields within this register will be reset upon read. 2. the asserted bit-field, within the block interrupt status register will be reset. 3. the framer device will negate the int (interrupt request) output pin, by drving this output pin "high. 2.6.1 automatic reset of interrupt enable bits occassionally, the users system (which includes the framer device) may experience a fault condition, such that a framer interrupt condition will continu- ously exist. if this particular interrupt condition has been enabled (within the framer ic) then the framer device will generate an interrupt request to the micro- processor/microcontroller. afterwards, the micropro- cessor/microcontroller will attempt to service this in- terrupt by reading the block interrupt status register and the subsequent source level interrupt status reg- isters. additionally, the microprocessor/microcontrol- ler will attempl to perform some system-related tasks in order to try to resolve those conditions causing the interrupt. after the microprocessor/microcontroller has attempted all of these things, the framer ic will negate the int output pin. however, because the system fault still remains, the conditions causing the framer to issue this interrupt request, also still exists. consequently, the framer device will generate anoth- er interrupt request, which forces the microprocessor/ microcontroller to once again attempt to service this interrupt. this phenomenon quickly results in the lo- cal microprocessor/microcontroller being tied up in a continuous cycle of executing this one interrupt ser- vice routine. consequently, the local microprocessor/ microcontroller (along with portions of the overall sys- tem) now becomes non-functional. in order to prevent this phenomenon from ever occur- ing, the framer ic allows the user to automatically re- set the interrupt enable bits, following their activation. the user can implement this feature by writing the ap- propriate value into bit 3 (interrupt enable reset) t able 10: i nterrupt s ervice r outine g uide ( for e3, itu-t g.832 a pplications ) i nterrupting f unctional b lock t he n ext r egisters to be r ead d uring the i nterrupt s ervice r outine r egister a ddress receive section rxe3 interrupt status register - 1 0 x 014 rxe3 interrupt status register - 2 0 x 15 rxe3 lapd control register 0 x 18 transmit section txe3 lapd status and interrupt register 0 x 34 t able 11: i nterrupt s ervice r outine g uide ( for e3, itu-t g.751 a pplications ) i nterrupting f unctional b lock t he n ext r egisters to be r ead d uring the i nterrupt s ervice r outine r egister a ddress receive section rxe3 interrupt status register - 1 0 x 014 rxe3 interrupt status register - 2 0 x 15 rxe3 lapd control register 0 x 18 transmit section txe3 lapd status and interrupt register 0 x 34 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 125 within the framer operating mode register, as illus- trated below. writing a 1 to this bit-field configures the framer to automatically disable a given interrupt, following its activation. writing a 0 to this bit-field configures the framer to leave the interrupt enable bit as is, follow- ing interrupt activation. if a user opts to implement the automatic reset of in- terrupt enable bits feature, then he/she might wish to configure the microprocessor/microcontroller to go back and re-enable these interrupts at a later time. 2.6.2 one-second interrupts the block interrupt status register, and block inter- rupt enable register each contain a bit-field for the one-second interrupt. if this interrupt is enabled (within the block interrupt enable register), then the framer device will automatically generate an interrupt request to the microprocessor/microcontroller repeat- edly at one-second intervals. at a minimum, the us- ers interrupt service routine must service this inter- rupt by reading the block interrupt status register (address = 0x05). once the microprocessor/micro- controller has read this register, then the following things will happen. 1. the one-second interrupt bit-field, within the block interrupt status register, will be reset to 0. 2. the framer will negate the int (interrupt request) output pin. the purpose of providing this one-second interrupt is to allow the microprocessor/microcontroller the op- portunity to perform certain tasks at one-second in- tervals. the user can accomplish this by including the necessary code (for these various tasks) as a part of the interrupt service routine, for the one-second type interrupt. some of these tasks could include: ? reading in the contents of the one-second perfor- mance monitor registers. ? reading various other performance monitor regis- ters. ? writing a new pmdl message into the transmit lapd message buffer. after the lapd transmitter has been enabled and commanded to initiate trans- mission of the lapd message frame (containing the pmdl message, residing within the transmit lapd message buffer), the lapd transmitter will continue to re-transmit this same lapd message frame, repeatedly at one-second intervals, until it has been disabled. if a new pmdl message is written into the transmit lapd message buffer immediately following the occurrence of a one-sec- ond interrupt, then this will ensure that this write activity will not interfere with this periodic transmis- sion of the lapd message frames. notes regarding the block interrupt enable and block interrupt status registers: 1. the block interrupt enable register allows the user to globally disable all potential interrupts within either the transmit or receive sections, by writing a 0 into the appropriate bit-field of this register. however, the block interrupt enable register does not allow the user to globally enable all potential interrupts within a given functional block. in other words, enabling a given functional block does not automatically enable all of its potential interrupt sources. those potential inter- rupt sources that have been disabled at the source level will remain disabled, independent of the status of their associated functional blocks. 2. the block interrupt enable register is set to 0x00 upon power or reset. therefore, the user will have to write some 1s into this register, in order to enable some of the interrupts. the remaining registers, listed in table 9, table 10 and table 11 will be presented in the discussion of the functional blocks, within the XRT72L50 framer ic. these discussions will present more details about the interrupt causes and how to properly service. them. 2.7 i nterfacing the framer to an intel - type microprocessor the framer can be interfaced to either intel-type or motorola-type microprocessor/microcontrollers. the following sections will provide one example for each type of processor. this section discusses how to in- framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 local loop-back ds3 /e3 internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 126 terface the XRT72L50 ds3/e3 framer ic to the 8051 microcontroller. the 8051 microcontroller the 8051 family of microcontrollers is manufactured by intel and comes with a variety of amenities. some of these amenities include: ? on-chip serial port ? four (4) 8-bit i/o ports (p0 - p3) ? 4k bytes of rom ? 128 bytes of ram the 8051 microcontroller consists of 4 - 8-bit i/o ports. some of these ports have alternate functions as will be discussed below. port 0 (p0.0 - p0.7) this port is a dual-purpose port on pins 32-39 of the 8051 ic. in minimal component designs, it is used as a general purpose i/o port. for larger designs with external memory, it becomes a multiplexed address and data bus (ad0 - ad7). port 1 (p1.0 - p1.7) port 1 is a dedicated port on pins 1 - 8. the pins, designated at p1.0, p1.1, ... p1.7 are available for in- terfacing as required. no alternative functions are as- signed for port 1 pins, thus they are used solely for in- terfacing external devices. exceptions are the 8032 and 8052 ics, which use p1.0 and p1.1 as either as i/ o lines or as extenal inputs to the third timer. port 2 (p2.0 - p2.7) port 2 (pins 21 - 28) is a dual-purpose port that can function as a general purpose i/o, or as the high-byte of the address bus for designs with external code memory of more than 256 bytes of external data memory (a8 - a15). port 3 port 3 is a dual purpose port on pins 10 - 17. in addi- tion to functioning as general purpose i/o, these pins have multiple functions. each of these pins have an alternate purpose, as listed in table 12 below. the 8051 also has numerous additional pins which are relevant to interfacing to the XRT72L50 ds3/e3 uni or other peripherals. these pins are: ale - address latch enable if port 0 is used in its alternative mode -as the data bus and the lower byte of the address bus -- ale is the signal that latches the address into an external register during the first half of a memory cycle. once this is done, port 0 lines are then available for data in- put or output during the second half of the memory cycle, when the data transfer takes place. int0* (p3.2) and int1* (p3.3) int0* and int1* are external interrupt request inputs to the 8051 microcontroller. each of these interrupt pins support direct interrupt processing. in this case, the term direct means that if one of these inputs are asserted, then program control will automatically branch to a specific (fixed) location in code memory. this location is determined by the circuit design of the 8051 microcontroller ic and cannot be changed. table 13 presents the location (in code memory) where the program control will branch to, if either of these inputs are asserted. t able 12: a lternate f unctions of p ort 3 p ins b it n ame a lternate f unction p3.0 rxd receive data for serial port p3.1 txd transmit data for serial port p3.2 int0* external interrupt 0 p3.3 int1* external interrupt 1 p3.4 t0 timer/counter 0 external input p3.5 t1 timer/counter 1 external input p3.6 wr* external data/memory write strobe p3.7 rd* external data/memory read strobe XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 127 therefore, if the user is using either one of these in- puts as an interrupt request input, then the user must ensure that the appropriate interrupt service routine or unconditional branch instruction (to the interrupt service routine) is located at one of these address lo- cations. if the 8051 microcontroller ic is required to interface to external components in the data memory space of sizes greater than 256 bytes, then both ports 0 and 2 must be used as the address and data lines. port 0 will function as a multiplexed address/data bus. dur- ing the first half of a memory cycle, port 0 will operate as the lower address byte. during the second half of the memory cycle, port 0 will operate as the bi-direc- tional data bus. port 2 will be used as the upper ad- dress byte. ale and the use of a 74hc373 transpar- ent latch device can be used to de-multiplex the ad- dress and data bus signals. figure 37 presents a schematic illustrating how the XRT72L50 ds3/e3 framer can be interfaced to the 8051 microcontroller ic. the circuitry in figure 37 will function as follows, dur- ing a framer-request interrupt. the framer device would request an interrupt from the cpu by asserting its active low int output pin. this will cause the int0* input pin of the cpu to go "low. when this happens the 8051 cpu will finish executing its cur- rent instruction, and will then branch program control to the framer device interrupt service routine. in the case of figure 37, the interrupt service routine will be located in 0x0003 in code memory. the 8051 cpu t able 13: i nterrupt s ervice r outine l ocation ( in c ode m emory ) for the int0* and int1* i nterrupt i nput pins i nterrupt pin b ranch to location ( in s ystem m emory ) int0* 0x0003 int1* 0x0013 f igure 37. s chematic depicting how to interface the XRT72L50 ds3/e3 f ramer ic to the 8051 m icro - controller +5v u2 8051 wr 16 rd 17 ad0 39 ad1 38 ad2 37 ad3 36 ad4 35 ad5 34 ad6 33 ad7 32 ale 30 a8 21 a9 22 a10 23 a11 24 a12 25 a13 26 a14 27 a15 28 int0 12 int1 13 u1 xrt7250 reset 28 rdb_ds 29 ale_as 31 int 13 cs 8 wrb_rw 7 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 a0 14 a1 15 a2 16 a3 17 a4 18 a5 19 a6 20 a7 21 a8 22 moto/intel 27 rdy_dtck 6 u? 74hc373 d0 3 d1 4 d2 7 d3 8 d4 13 d5 14 d6 17 d7 18 oc 1 g 11 q0 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 to address decoder from address decoder ale ale interrupt interrupt reset command circuitry ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 128 does not issue an interrupt acknowledge signal back to the framer ic. it will just begin processing through the framers interrupt service routine. one the cpu has eliminated the cause(s) of the interrupt request, the framers int output pin will be negated (e.g., go "high) and the cpu will return from the interrupt ser- vice routine and resume normal operation. 2.8 i nterfacing the f ramer ic to a m otorola - type m icroprocessor this section discusses how to interface the XRT72L50 ds3/e3 framer ic to the mc68000 micro- processor. figure 38 presents a schematic on how to interface the XRT72L50 ds3/e3 framer ic to the mc68000 microprocessor, over an 8-bit wide bi-directional data bus. in general, the approach to interfacing these two de- vices is straightforward. however, the user must be aware of the fact that the XRT72L50 ds3/e3 framer ic does not provide an interrupt vector to the mc68000 during an interrupt acknowledge cycle. therefore, the user must configure his/her design to support auto-vectored interrupts. auto-vectored in- terrupt processing is a feature offered by the mc68000 family of microprocessors, where, if the microprocessor knows (prior to any iack cycle) the interrupt level of this current interrupt, and that the interrupting peripheral does not support vectored in- terrupts, then the microprocessor will generate its own interrupt vector. the schematic shown in figure 38, has been configured to support auto-vec- tored interrupts. f igure 38. s chematic d epicting how to interface the XRT72L50 ds3/e3 f ramer ic to the mc68000 m icroprocessor +5v +5v +5v u2 mc68000 reset 18 r/w 9 dtack 10 d0 5 d1 4 d2 3 d3 2 d4 1 d5 64 d6 63 d7 62 d8 61 d9 60 d10 59 d11 58 d12 57 d13 56 d14 55 d15 54 a1 29 a2 30 a3 31 a4 32 a5 33 a6 34 a7 35 a8 36 a9 37 fc0 28 fc1 27 fc2 26 vpa 21 ipl0 25 ipl1 24 ipl2 23 as 6 uds 7 lds 8 a10 38 a11 39 a12 40 a13 41 a14 42 a15 43 a16 44 a17 45 a18 46 a19 47 a20 48 a21 49 a22 50 a23 51 u1 xrt7250 reset 28 wrb_rw 7 rdy_dtck 6 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 a0 14 a1 15 a2 16 a3 17 a4 18 a5 19 a6 20 a7 21 a8 22 int 13 cs 8 moto/intel 27 rdb_ds 10 ale_as 9 u4 74ahct148 0 10 1 11 2 12 3 13 4 1 5 2 6 3 7 4 ei 5 a0 9 a1 7 a2 6 gs 14 eo 15 u5 74ahct138 a 1 b 2 c 3 g1 6 g2a 4 g2b 5 y0 15 y1 14 y2 13 y3 12 y4 11 y5 10 y6 9 y7 7 u3 74ahct138 a 1 b 2 c 3 g1 6 g2a 4 g2b 5 y0 15 y1 14 y2 13 y3 12 y4 11 y5 10 y6 9 y7 7 u7a 74ahct04 1 2 u7b 74ahct04 3 4 u6a 74ahct00 1 2 3 d[15:8] to address decoder from address decoder address_strobe data_strobe address_strobe data_strobe XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 129 functional description of circuit illustrated in figure 38. when the XRT72L50 ds3/e3 framer ic generates an interrupt, the int output will toggle "low. this will force input 6, of the interrupt priority encoder chip (u4) to also toggle "low. in response to this, the in- terrupt priority encoder chip will set its three outputs to the following states: a2 = 0, a1 = 0 and a0 = 1 (which is the number 6 in highinverted binary format). the state of three output pins will be read by the ac- tive-low interrupt request inputs of the microproces- sor (ipl2, ipl1, ipl0). when the mc68000 micro- processor detects this value at its three interrupt re- quest inputs, it will know two things. 1. an interrupt request has been issued by one of the peripheral devices. 2. the interrupt request is a level 6 interrupt request (due to the values of the a2 - a0 outputs from the interrupt priority encoder ic). once the mc68000 microprocessor has determined these two things it will initiate an interrupt acknowl- edge (iack) cycle by doing the following: 1. identify this new bus cycle as an interrupt service routine by setting all of its function code output pins (fc2 - fc0) to "high. 2. placing the interrupt level on the address output pins a[3:1]. when the mc68000 microprocessor has toggled all of its function code output pin "high, the function code decoder chip (u3) will read this value from the fc2 - fc0 pins as being the binary value for 7. as a result, u3 will assert its active-low y7 output pin. at the same time, the address lines a[3:1] are carrying the current interrupt level of this iack cycle (level = 6, or 110 in this example) and applying this value to the a, b, and c inputs of the iack level decoder chip (u5). initially, all of the outputs of u5 are tri-stated. due to the fact that its active-low g2a and g2b inputs are negated (e.g., at a logic "high). however, when the mc68000 microprocessor begins the iack cycle, it will assert its address strobe (as*) signal. this ac- tion will result in asserting the g2a input pin of u5. additionally, since the function code decoder chip has also asserted its y7 output pin this will, in turn, assert the g2a input pin of u5. at this point, the out- put of u5 will no longer be tri-stated. u5 will read in the contents of its a, b, and c inputs, and assert the active-low vpa* (valid peripheral address) input pin of the mc68000. anytime the mc68000 detects its vpa* pin being asserted during an iack cycle, it knows that this is an auto-vectored interrupt cycle. further, it also knows that it will not receive an inter- rupt vector from the peripheral device (e.g., the XRT72L50 ds3/e3 framer ic, in this case), and that it must generate its own vector. in the very next bus cycle, the mc68000 is going to implement a pseudo- read of the data bus. however, in reality, no data will be read from the XRT72L50. the mc68000 will in- stead have determined that since this current iack cycle is an auto-vectored - level 6 interrupt cycle, which corresponds to vector number 30, within the mc68000s exception vector table. vector number 30 corresponds to an address space of 0x78, in the mc68000s address space. in the case of this exam- ple, the user is required to place an unconditional branch statement (to the location of the XRT72L50 in- terrupt service routine) at 0x78 in system memory. table 14 presents the auto-vector table (e.g., the re- lationship between the interrupt level and the corre- sponding location in memory for this unconditional branch statement) for the mc68000 microprocessor. 3.0 the line interface and scan section the line interface and scan section of the XRT72L50 ds3/e3 framer ic consists of 5 output t able 14: a uto -v ector t able for the mc68000 m icroprocessor i nterrupt l evel v ector n umber a ddress l ocation ( of u nconditional b ranch i nstruction - for i nterrupt s ervice r outine ) 125 0x064 226 0x068 327 0x06c 428 0x070 529 0x074 630 0x078 731 0x07c ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 130 pins, 3 input pins, a read/write register, and a read- only register. the purpose of the line interface drive and scan section is to permit the user to monitor and exercise control over many aspects of the xrt7300 ds3/e3/ sts-1 liu ic without having to develop the neces- sary off-chip glue-logic. figure 39 presents a simple circuit schematic that de- picts how the XRT72L50 ds3/e3 framer ic could be interfaced to the xrt7300 ds3/e3/sts-1 liu ic. 3.1 b it -f ields within the l ine i nterface d rive r egister as mentioned above, the line interface drive and scan section consists of five output pins and three in- put pins. the logic state of the output pins are con- trolled by the contents within the line interface drive register, as depicted below. the role of each of these bit-fields are their corre- sponding output pins are depicted below. f igure 39. s chematic d epicting how to interface the XRT72L50 ds3/e3 f ramer ic to the xrt73l00 ds3/e3/sts-1 liu ic ( one channel shown ) 5v u1 xrt7250 txpos 65 txneg 64 txlineclk 63 dmo 79 extlos 78 rlol 77 lloop 69 rloop 70 taos 68 txlev 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 txser 46 txinclk 43 txframe 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 xrt7300 tpdata 37 tndata 38 tclk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tring 40 mtip 44 mring 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 taos 2 txlev 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 txser txinclk nibbleintf resetb rtip rring csb rw ds as txframe rxser rxclk rxframe rxlos rxoof rxred rxais a[8:0] tring ttip intb d[7:0] intb line interface drive register (address = 0x80) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 iloop reqb taos encodis txlev rloop lloop r/o r/o r/w r/w r/w r/w r/w r/w 00001000 XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 131 bit 7 - iloop (internal remote loop-back) this read/write bit-field permits the user to config- ure the corresponding channel (within the XRT72L50 device) to operate in the internal remote loop-back mode. once the user configures the channel to oper- ate in this remote loop-back mode, then the rx- posn, rxnegn and rxlineclk_n signals will be routed directly to the txposn, txnegn and txlineclk_n signals. setting this bit-field to 1 configures the channel to operate in the remote loop-back mode. bit 5 - reqb - (receive equalization enable/dis- able select) this read/write bit-field allows the user to control the state of the reqb output pin of the framer device. this output pin is intended to be connected to the reqb input pin of the xrt7300 ds3/e3/sts-1 liu ic. if the user forces this signal to toggle "high, then the internal receive equalizer (within the xrt7300 device) will be disabled. conversely, if the user forces this signal to toggle "low, then the receive equalizer (within the xrt7300 device) will be enabled. the purpose of the internal receive equalizer (within the xrt7300 device) is to compensate for the fre- quency-dependent attenuation (e.g., cable loss), that a line signal will experience as it travels through coax- ial cable, from the transmitting to the receiving termi- nal. writing a 1 to this bit-field causes the framer device to toggle the reqb output pin "high. writing a 0 to this bit-field causes the framer device to toggle the reqb output pin "low. for information on the criteria that should be used when deciding whether to enable or disable the re- ceive equalizer, please consult the xrt7300 ds3/ e3/sts-1 liu ic data sheet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 ic, then this bit-field and the reqb output pin can be used for other purposes. bit 4 - taos - (transmit all ones signal) this read/write bit-field allows the user to control the state of the taos output pin of the framer device. this output pin is intended to be connected to the taos input pin of the xrt7300 ds3/e3/sts-1 liu ic. if the user forces this signal to toggle "high, then the xrt7300 device will transmit an all ones pat- tern onto the line. conversely, if the user commands this output signal to toggle "low then the xrt7300 ds3/e3/sts-1 liu ic will proceed to transmit data based upon the data that it receives via the txpos and txneg output pins (of the framer ic). writing a 1 to this bit-field causes the taos output pin to toggle "high. writing a 0 to this bit-field will cause this output pin to toggle "low. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then this bit-field, and the taos output pin can be used for other purposes. bit 3 - encodis - (b3zs/hdb3 encoder disable) this read/write bit-field allows the user to control the state of the encodis output pin of the framer de- vice. this output pin is intended to be connected to the encodis input pin of the xrt7300 ds3/e3/ sts-1 liu ic. if the user forces this signal to toggle "high, then the internal b3zs/hdb3 encoder (within the xrt7300 device) will be disabled. conversely, if the user commands this output signal to toggle "low, then the internal b3zs/hdb3 encoder (within the xrt7300 device) will be enabled. writing a 1 to this bit-field causes the framer ic to toggle the encodis output pin "high. writing a 0 to this bit-field will cause the framer ic to toggle this output pin "low. n otes : 1. the b3zs/hdb3 encoder, within the xrt7300 device is not to be confused with the b3zs/hdb3 encoding capabilities that exists within the transmit ds3/e3 framer block of the framer ic. 2. the user is advised to disable the b3zs/hdb3 encoder (within the xrt7300 ic) if the transmit and receive ds3/e3 framer (within the XRT72L50) are configured to operate in the b3zs/ hdb3 line code. 3. if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then this bit-field and the encodis output pin can be used for other purposes. 4. it is permissible to tie both the encodis and decodis input pins (of the xrt7300 device) to the encodis output pin of the XRT72L50 ds3/e3 framer ic. bit 2 - txlev (transmit line build-out enable/ disable select) this read/write bit-field allows the user to control the state of the txlev output pin of the framer device. this output pin is intended to be connected to the tx- lev input pin of the xrt7300 ds3/e3/sts-1 liu ic. writing a 1 to this bit-field commands the framer to drive the txlev output pin "high. writing a 0 to this bit-field commands the framer to drive this output signal "low. if the user commands this signal to toggle "high, then the transmit line build-out circuitry, within the xrt7300 device will be disabled. in this mode, the xrt7300 liu ic will generate unshaped (e.g., ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 132 square) pulses out onto the line, via the ttip and tring output pins. conversely, if the user commands this signal to toggle "low, then the transmit line build-out circuitry, with- in the xrt7300 device will be enabled. in this mode, the xrt7300 device will generate shaped pulses on- to the line, via the ttip and tring output pins. in order to comply with the isolated dsx-3 pulse template requirements (per bellcore gr-499- core), the user is advised to set this bit-field to 0 if the cable length (between the transmit output of the xrt7300 device and the dsx-3 cross connect sys- tem) is less than 225 feet. conversely, the user is ad- vised to set this bit-field to 1 if the cable length (be- tween the transmit output of the xrt7300 device and the dsx-3 cross connect system) is greater than 225 feet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 ic, then this bit-field and the txlev output pin can be used for other purposes. bit 1 - rloop (remote loop-back select) this read/write bit-field permits the user to control the state of the rloop output pin of the framer de- vice. this output pin is intended to be connected to the rloop input pin of the xrt73001 liu ic. the state of this bit-field (or pin) along with lloop are used to configure the xrt7300 device into one of four (4) loop-back modes. the relationship of the val- ues of rloop, lloop and the resulting loop-back mode (within the xrt7300 device) is tabulated below. writing a 1 into this bit-field commands the framer to drive the rloop output signal "high. writing a 0 into this bit-field commands the framer to drive this output signal "low. for a detailed description of the xrt7300 lius oper- ation during each of these loop-back modes, please see the xrt7300 ds3/e3/sts-1 liu ic data sheet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then this bit-field and the rloop output pin can be used for other purposes. bit 0 - lloop (local loop-back select) this read/write bit-field allows the user to control the state of the lloop output pin of the framer device. this output pin is intended to be connected to the lloop input pin of the xrt7300 ds3/e3/sts-1 liu ic. the state of this bit-field (or pin) along with rloop are used to configure the xrt7300 into one of four (4) loop-back modes. the relationship of the values of rloop, lloop and the resulting loop-back modes (within the xrt7300 device) are presented in table 15. writing a 1 into this bit-field commands the framer to toggle the lloop output pin "high. writing a 0 into this bit-field commands the framer to toggle this output signal "low. for a detailed description of the xrt7300 lius oper- ation during each of these loop-back modes, please see the xrt7300 ds3/e3/sts-1 liu ic data sheet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then this bit-field and the lloop output pin can be used for other purposes. 3.2 b it -f ields within the l ine i nterface s can r egister the xrt7300 device contains three output pins which can be made accessible to the microprocessor interface, via the line interface scan register. these three output pins are listed below. ? dmo - drive monitor output ? rlol - receive loss of lock indicator ? rlos - receive loss of signal indicator. the logic state of each of these input pins (or output pins from the liu) can be monitored by reading the contents of the line interface scan register, as de- picted below. t able 15: t he r elationship between the states of rloop, lloop and the resulting loop - back mode with the xrt7300 device rloop lloop resulting loop-back mode (within the xrt7300 ds3/e3/sts-1 liu ic) 0 0 normal mode (no loop-back) 0 1 analog local loop-back mode 1 0 remote loop-back mode 1 1 digital local loop-back mode XRT72L50 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 133 the meaning/role of each of these bit-field and their corresponding input pins are defined below. bit 2 - dmo - drive monitor output this read-only bit-field indicates the logic state of the dmo output pin of the framer device. this input pin is intended to be connected to the dmo output pin of the xrt7300 ds3/e3/sts-1 liu ic. if this bit- field contains a logic 1, then the dmo input pin is "high. the xrt7300 ds3/e3/sts-1 liu ic will set this pin "high if the transmit driver monitor circuitry (within the xrt7300 device) has not detected any bi- polar signals at the mtip and mring inputs (of the xrt7300 device) within the last 128 + 32 bit periods. conversely, if this bit-field is set to 0, then the dmo input pin is "low. the xrt7300 ds3/e3/sts-1 liu ic will set this pin "low if bipolar signals are being detected at the mtip and mring input pins. for more information on the user/purpose of the drive monitor feature, within the xrt7300 liu ic, please see the xrt7300 ds3/e3/sts-1 liu ic data sheet. n ote : if this customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then this register bit-field and input pin can be used for a variety of other purposes. bit 1 - rlol - receive loss of lock this read-only bit-field indicates the logic state of the rlol input pin of the framer device. this input pin is intended to be connected to the rlol output pin of the xrt7300 ds3/e3/sts-1 liu ic. if this bit- field contains a logic 1, then the rlol input pin is "high. the xrt7300 liu ic will drive this pin "high if the clock recovery phase locked loop circuitry (with- in the xrt7300 device) has lost lock with the incom- ing ds3 or e3 data-stream and is not properly recov- ering clock and data. conversely, if this bit-field contains a logic 0, then the rlol input pin is "low. the xrt7300 ds3/e3/ sts-1 liu ic will hold this pin "low for as long as this clock recovery phase-locked-loop circuit (within the xrt7300 device) is properly locked onto the in- coming ds3 or e3 data stream and is properly recov- ering clock and data from this data stream. bit 0 - rlos- receive loss of signal this read-only bit-field indicates the logic state of the rlos input pin of the framer device. this input pin is intended to be connected to the rlos output pin of the xrt7300 ds3/e3/sts-1 liu ic. if this bit- field contains a logic 1, then the rlos input pin is "high. the xrt7300 liu ic will drive this signal "high if it is currently declaring an los (loss of sig- nal) condition. conversely, if this bit-field contains a logic 0, then the rlos input pin is "low. the xrt7300 liu ic will drive this signal "low, if it is not currently de- claring an los (loss of signal) condition. for more information on the los declaration/clear- ance criteria, used by the xrt7300 device, please see the xrt7300 ds3/e3/sts-1 liu ic data sheet. n ote : asserting the rlos input pin will cause the framer device to generate a change in los condition interrupt and declare an los (loss of signal) condition to the micro- processor/microcontroller. therefore, the user is not advised to use the rlos input pin as a general purpose input pin. line interface scan register (address = 0x81) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used dmo rlol rlos r/o r/o r/o r/o r/o r/o r/o r/o 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller XRT72L50 preliminary rev. p1.1.3 134 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 135 XRT72L50 configuration the XRT72L50 ds3/e3 framer ic can be configured to support any of the following four framing formats. ? ds3/c-bit parity ? ds3/m13 ? e3/itu-t g.832 ? e3/itu-t g.751 as a consequence, the discussion of the XRT72L50 framer ic will be organized as follows: ? section 4.0 - ds3 mode operation of the XRT72L50 ? section 5.0 - e3, itu-t g.751 operation of the XRT72L50 ? section 6.0 - e3, itu-t g.832 operation of the XRT72L50 ? section 7.0 - framer local loop-back mode operation ? section 8.0 - high speed hdlc controller mode of operation 4.0 ds3 operation of the XRT72L50 this section will discuss in detail, the operation of the XRT72L50 framer ic, when it has been configured to operate in the ds3 mode. configuring the XRT72L50 to operate in the ds3 mode the XRT72L50 can be configured to operate in the ds3 mode by writing a "1" into bit-field 6 within the framer operating mode register, as illustrated below. prior to describing the functional blocks within the transmit and receive sections of the XRT72L50, it is important to describe the following two framing for- mats. ? m13 ? c-bit parity 4.1 d escription of the ds3 f rames and a ssoci - ated o verhead b its the role of the various overhead bits are best de- scribed by discussing the ds3 frame format as a whole. the ds3 frame contains 4760 bits, of which 56 bits are overhead and the remaining 4704 bits are payload bits. the payload data is formatted into packets of 84 bits and the overhead (oh) bits are in- serted between these payload packets. the XRT72L50 framer supports the following two ds3 framing formats: ? c-bit parity ? m13 figures 40 and 41 present the ds3 frame format for c-bit parity and m13, respectively. framer operating mode register (address = 0x00) b it 7 b it 6b it 5b it 4b it 3b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w x 1x 0 x x x x f igure 40. ds3 f rame f ormat for c- bit p arity x if1 iaic if0 ina if0 i feac if1 i i x if1 i udl if0 ina if0 i udl if1 i ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 136 x = signaling bit for network control i = payload information (84 bit packets) fi = frame synchronization bit with logic value i p = parity bit mi = multiframe synchronization bit with logic value i aic = application identification channel na = reserved for network application feac = far end alarm and control dl = data link cp = cp (path)-bit parity febe = far end block error udl = user data link x = signaling bit for network control i = payload information (84 bit packets) fi = frame synchronization bit with logic value i cij = jth stuff code bit of ith channel p = parity bit mi = multiframe synchronization bit with logic values i the user can choose between these two frame for- mats, by writing the appropriate data to bit 2 of the framer operating mode register (address = 0x00), as depicted below. p if1 icp if0 icp if0 icp if1 i p if1 i febe if0 i febe if0 i febe if1 i m0 if1 idl if0 idl if0 idl if1 i m1 if1 i udl if0 i udl if0 i udl if1 i m0 if1 i udl if0 i udl if0 i udl if1 i f igure 40. ds3 f rame f ormat for c- bit p arity f igure 41. ds3 f rame f ormat for m13 x if1 ic11 if0 ic12 if0 ic13 if1 i i x if1 ic21 if0 ic22 if0 ic23 if1 i p if1 ic31 if0 ic32 if0 ic33 if1 i p if1 ic41 if0 ic42 if0 ic43 if1 i m0 if1 ic51 if0 ic52 if0 ic53 if1 i m1 if1 ic61 if0 ic62 if0 ic63 if1 i m0 if1 ic71 if0 ic72 if0 ic73 if1 i framer operating mode register (address = 0x00) b it 7 b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 137 table 16 lists the relationship between the value of the this bit-field and the resulting ds3 frame format. n ote : this bit setting also configures the frame format for both the transmit and receive section of the XRT72L50. each of the two ds3 frame formats, as presented in figure 40 and figure 41, constitute an m-frame (or a full ds3 frame). each m-frame consists of 7 - 680 bit f-frames (sometimes referred to as, subframes). in figure 40 and 41, each f-frame is represented by the individual rows of payload and overhead bits. each f-frame can be further divided into 8 blocks of 85 bits, with 84 of the 85 bits available for payload in- formation and the remaining one bit used for frame overhead. differences between the m13 and c-bit parity frame formats the frame formats for m13 and c-bit parity are very similar. however, the main difference between these two framing formats is in the use of the c-bits. in the m13 format, the c-bits reflect the status of stuff-op- portunities that either were or were not used while multiplexing the 7 ds2 signals into this ds3 signal. if two of the three stuff bits, within a f-frame, are "1", then the associated stuff bit, si (not shown in figure 41), is interpreted as being a stuff bit. in the c-bit parity framing format, the c bits take on different roles, as presented in table 17. definition of the ds3 frame overhead bits in general, the ds3 frame overhead bits serve the following three purposes: 1. support frame synchronization between the local and remote ds3 terminals 2. provide parity bits in order to facilitate perfor- mance monitoring and error detection. 3. support the transmission of alarms, status, and data link information to the remote ds3 termi- nal. the overhead bits supporting each of these purpos- es are further defined below. 4.1.1 frame synchronization bits (applies to both m13 and c-bit parity framing formats) each ds3 frame (m-frame) contains a total of 31 bits that support frame synchronization. each ds3 m- frame contains three m-bits. according to figure 40 and figure 41, these m-bits are the first bits in f- frames 5, 6 and 7. these three bits appear in each m-frame with the repeating pattern of "010". this fact is also presented in figure 40 and figure 41, which contains bit-fields that are designated as: m0, m1, and m0 (where m0 = "0", and m1 = "1"). each f-frame contains four f-bits, which also aid in synchronization between the local and the remote x 1x 0 x xxx framer operating mode register (address = 0x00) b it 7 b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 t able 16: t he r elationship between the content of b it 2, (c-b it p arity */m13) within the f ramer o perating m ode r egister and the resulting ds3 f raming f ormat b it 2 ds3 f rame f ormat 0 c-bit parity 1m13 t able 17: c- bit f unctions for the c- bit p arity ds3 f rame f ormat c - b it f unction of c- bits while in the c-b it p arity f raming f ormat c11 aic (c-bit parity mode) c12 na (reserved for network application) c13 feac (far end alarm & control) c21, c22, c23 (udl) user data link (undefined for ds3 frame) c31,c32, c33 cp (path) parity bits c41, c42, c43 febe (far end block error) indicators c51, c52, c53 (dl) path maintenance data link c61, c62, c63, c71, c72, c73 (udl) user data link (undefined for ds3 frame) ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 138 ds3 terminals. therefore, each ds3 m-frame con- sists of a total of 28 f-bits. these f-bits exhibit a re- peating pattern of "1001" within each f-frame. this fact is also presented in figure 40 and figure 41, which contains bit-fields that are designated as: f1, f0, f0, and f1 (where f0 = "0", and f1 = "1"). each of these bit-fields will be used by the receive ds3 framer block, within the remote terminal equip- ment, to perform frame acquisition and frame main- tenance functions. n ote : for more information on how the receive ds3 framer uses these bit-fields, please see section 3.3.2. 4.1.2 performance monitoring/error detection bits (parity) the ds3 frame uses numerous bit fields to support performance monitoring of the transmission link be- tween the local transmitting terminal and the re- mote receiving terminal. the ds3 frame can con- tain two types of parity bits, depending upon the fram- ing format chosen. p-bits are available in both the m13 and c-bit parity formats. however, the c-bit parity format also includes additional cp-parity bits. p-bits (applies to m13 and c-bit parity frame for- mats) each ds3 m-frame consists of two (2) p-bits. these two p-bits carry the parity information of the previous ds3 frame for performance monitoring. these two p- bits must be identical, within a given ds3 frame. the transmit section will compute the even parity over all 4704 payload bits within a given ds3 frame, and in- sert the resulting parity information in the p-bit fields of the very next ds3 frame. the two p-bits are set to "1" if the payload of the previous ds3 frame consists of an odd number of "ones" in the frame. conversely, the two p-bits are set to zero if an even number of "ones" is found in the payload of the previous ds3 frame. for information on how the receive ds3 framer handles p-bits, please see section 3.3.2.6.1. cp-(path) parity bits (applies to only the c-bit parity framing format) each ds3 m-frame consists of tw0 (2) cp-bits. these two bits have a very similar role to those of p- bits. further, the XRT72L50 framer ic processes cp-bits in an identical manner that it handles p-bits. however for some ds3 applications, there is a differ- ence between p and cp-bits, that should be noted. ? p-bits are used to support error detection of a ds3 data stream as it travels from one t.e. to the next. (e.g., a single ds3 link between two t.e.) ? cp-bits are used to support error detection of ds3 data stream as it travels from the source t.e. (where the ds3 data stream originated), to the sink t.e, (where the ds3 data stream is termi- nated.) n ote : this transmission path from source t.e. to sink t.e. may involve numerous t.e. ? p-bits are verified and recomputed as it passes through a mid-network t.e. (which is neither a source nor sink t.e.) ? the values of the cp-bits (as generated by the source t.e.) must be preserved as a ds3 frame travels to the sink t.e. (through any number of mid-network t.e.) for more information on how cp-bits are processed, please see section 3.3.2.6.2 4.1.3 alarm and signaling-related overhead bits the ds3 frame consists of mumerous bit-fields which are used to support the handling of alarm and signal- ing information. each of these bit-fields are defined below. the alarm indication signal (ais) pattern (c-bit parity framing format only) the alarm indication signal (ais) pattern is an alarm signal that is inserted into the outbound ds3 stream when a failure is detected by the local terminal. the transmit ds3 framer will generate the ais pattern as defined in ansi.t1.107a-1990, which is described as follows. v alid m- bits , f- bits , and p- bits ? all c-bits are zeros ? all x-bits are set to "1" ? a repeating "1010..." pattern is written into the pay- load of the ds3 frames. consequently, no user (or payload) data will be trans- mitted while the transmit section of the chip is trans- mitting the ais pattern. the idle condition signal the idle condition signal is used to indicate that the ds3 channel is functionally sound, but has not yet been assigned any traffic. the transmit section will transmit the idle condition signal as defined in ansi t1.107a-1990, which is described as follows. ? valid m-bits, f-bits, and p-bits ? the three cp-bits (f-frame #3) are zeros ? the x-bits are set to "1" ? a repeating "1100.." pattern is written into the pay- load of the ds3 frames. feac - far end alarm & control (only available for the c-bit parity frame format) xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 139 the third c-bit (c13 or feac) in the first f-frame is used as the far end alarm and control (feac) chan- nel between the near-end ds3 terminal and the re- mote ds3 terminal. the feac channel carries: ? alarm and status information ? loopback commands to initiate and deactivate ds3 and ds1 loopbacks at the distant terminals. the feac message consists of a six (6) bit code word of the form [d5, d4, d3, d2, d1 d0]. this mes- sage is encapsulated with 10 framing bits to form a 16 bit feac message, as illustrated below. the feac signals are encoded into repeating 16 bit mes- sage of the form: since each ds3 frame carries only one feac bit, 16 ds3 frames are required to deliver 1 complete feac message. the six bits labeled "dx" can represent up- to 64 distinct messages, of which 43 have been de- fined in the standards. for a more detailed discus- sion on the transmission of feac messages, please see section 3.2.3.1. febe - far end block error (only available for the c-bit parity frame format) f-frame # 4 consists of 3 bit fields for the febe (far- end block error) channel. if the (local) receive sec- tion (within the framer ic) detects p-bit parity errors, cp-bit errors or a framing error on the incoming (re- ceived) ds3 stream it will inform the transmit section of this fact. the transmit section will, in turn, set the three febe bits (within an outgoing ds3 frame) to any pattern other than "111" to indicate an error. the transmit section will then transmit this information out to the remote terminal (e.g., the source of the er- rored-data). the febe bits, in the outbound ds3 frames, are set to "111" only if both of the following conditions are true: ? the receive ds3 framer has detected no m-bit or f-bit framing errors, and ? no p-bit parity errors have been detected. ? no cp-bit errors have been detected. n ote : a more detailed discussion on the transmit sec- tion's handling of the febe bit-fields can be found in sec- tion 3.2.4.2.1.9. the yellow alarm or ferf (far-end receive fail- ure) indicator the x-bits are used for sending yellow alarms or the ferf (far-end receive failure) indication. when the receive section (of the XRT72L50), within the remote receiving terminal equipment, cannot identi- fy valid framing, or detects an ais pattern in the in- coming ds3 data-stream, the framer ic can be con- figured such that the transmit section will send a yel- low alarm or a ferf (far-end receive failure) indi- cation to the remote terminal by setting both of the x-bits to zero in the outbound (returning) ds3 path. the x-bits are set to "1" during non-alarm conditions. 4.1.4 the data link related overhead bits udl: user data link (c-bit parity frame format only) these bit-fields are not used by the framer and are set to "1" by default. however, these bits may be used for the transmission of data via a proprietary da- ta link. the user can access these bit-fields via the transmit overhead data input interface and the re- ceive overhead data output interface blocks. dl: path maintenance data link (c-bit parity frame format only) the lapd transceiver block uses these bit-fields for the transmission and reception of path maintenance data link (pmdl) messages via itu-t q.921 (lap-d) message frames. please see sections 3.2.3.2 and 3.3.3.2 for more information on the operation and function of the lapd transmitter. 4.2 t he t ransmit s ection of the XRT72L50 (ds3 m ode o peration ) when the XRT72L50 has been configured to operate in the ds3 mode, the transmit section of the XRT72L50 consists of the following functional blocks. ? transmit payload data input interface block ? transmit overhead data input interface block ? transmit ds3 framer block ? transmit ds3 hdlc controller block ? transmit liu interface block figure 42 presents a simple illustration of the trans- mit section of the XRT72L50 framer ic. 0 d5 d4 d3 d2 d1 d0011111111 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 140 each of these functional blocks will be discussed in detail in this document. 4.2.1 the transmit payload data input interface block figure 43 presents a simple illustration of the trans- mit payload data input interface block. f igure 42. a s imple i llustration of the t ransmit s ection , within the XRT72L50, when it has been con - figured to operate in the ds3 m ode transmit payload data input interface block transmit ds3/e3 framer block transmit liu interface block txser txnib[3:0] txinclk txpos txneg txlineclk transmit overhead input interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe tx ds3 hdlc controller/buffer tx ds3 hdlc controller/buffer from microprocessor interface block xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 141 each of the input and output pins of the transmit pay- load data input interface are listed in table 18 and described below. the exact role that each of these inputs and output pins assume, for a variety of operat- ing scenarios, are described throughout this section. f igure 43. a s imple i llustration of the t ransmit p ayload d ata i nput i nterface b lock transmit payload data input interface block transmit payload data input interface block txoh_ind txser txnib[3:0] txinclk txnibclk txframe txframeref to transmit ds3 framer block ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 142 t able 18: l isting and d escription of the pins associated with the t ransmit p ayload d ata i nput i nterface s ignal n ame t ype d escription txser input transmit serial payload data input pin: if the user opts to operate the XRT72L50 in the serial mode, then the terminal equipment is expected to apply the payload data (that is to be transported via the outbound ds3 data stream) to this input pin. the XRT72L50 will sample the data that is at this input pin upon the rising edge either the rxoutclk or the txinclk signal (whichever is appropriate). n ote : this signal is only active if the nibint input pin is pulled "low". txnib[3:0] input transmit nibble-parallel payload data input pins: if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the terminal equip- ment is expected to apply the payload data (that is to be transported via the outbound ds3 data stream) to these input pins. the XRT72L50 will sample the data that is at these input pins upon the rising edge of the txnibclk signal. n ote : these pins are only active if the nibint input pin is pulled "high". txnibframe output transmit end of frame output indicator - nibble mode the transmit section of the XRT72L50 will pulse this output pin "high" (for one nibble-period), when the transmit payload data input interface is processing the last nibble of a given ds3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin trans- mission of a new ds3 frame to the XRT72L50. txinclk input transmit section timing reference clock input pin: the transmit section of the XRT72L50 can be configured to use this clock signal as the tim- ing reference. if the user has made this configuration selection, then the XRT72L50 will use this clock signal to sample the data on the txser input pin. n ote : if this configuration has been selected, then a 44.736 mhz clock signal must be applied to this input pin. txnibclk output transmit nibble mode output if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the XRT72L50 will derive this clock signal from the selected timing reference for the transmit section of the chip (e.g., either the txinclk or the rxlineclk signals). the user is advised to configure the terminal equipment to output the outbound payload data (to the XRT72L50 framer ic) onto the txnib[3:0] input pins, upon the rising edge of this clock signal. n ote : for ds3 applications, the XRT72L50 framer ic will output 1176 clock edges (to the terminal equipment) for each outbound ds3 frame. txohind output transmit overhead bit indicator output: this output pin will pulse "high" one-bit period prior to the time that the transmit section of the XRT72L50 will be processing an overhead bit. the purpose of this output pin is to warn the terminal equipment that, during the very next bit-period, the XRT72L50 is going to be pro- cessing an overhead bit and will be ignoring any data that is applied to the txser input pin. for ds3 applications, this output pin is only active if the XRT72L50 is operating in the serial mode. this output pin will be pulled "low" if the device is operating in the nibble-parallel mode. txframe output transmit end of frame output indicator: the transmit section of the XRT72L50 will pulse this output pin "high" (for one bit-period), when the transmit payload data input interface is processing the last bit of a given ds3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin trans- mission of a new ds3 frame to the XRT72L50 (e.g., to permit the XRT72L50 to maintain transmit ds3 framing alignment control over the terminal equipment). xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 143 operation of the transmit payload data input in- terface the transmit payload data input interface is extreme- ly flexible, in that it permits the user to make the fol- lowing configuration options. ? the serial or the nibble-parallel interface mode ? the loop-timing or the txinclk (local timing) mode further, if the XRT72L50 has been configured to op- erate in the txinclk (local timing) mode, then the user has two additional options. ? the XRT72L50 functions as the frame master (e.g., it dictates when the terminal equipment will initiate the transmission of data within a new ds3 frame). ? the XRT72L50 functions as the frame slave (e.g., the terminal equipment will dictate when the XRT72L50 initiates the transmission of a new ds3 frame). given these three set of options, the transmit termi- nal input interface can be configured to operate in one of the six (6) following modes. ? mode 1 - serial/loop-timed mode ? mode 2 - serial/local-timed/frame slave mode ? mode 3 - serial/local-timed/frame master mode ? mode 4 - nibble/loop-timed mode ? mode 5 - nibble/local-timed/frame slave mode ? mode 6 - nibble/local-timed/frame master mode each of these modes are described, in detail, below. 4.2.1.1 mode 1 - the serial/loop-timing mode the behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. a. loop-timing (uses the rxlineclk signal as the timing reference) since the XRT72L50 is configured to operate in the loop-timed mode, the transmit section (of the XRT72L50) will use the rxlineclk input clock signal (e.g., the recovered clock signal, from the liu) as its timing source. when the XRT72L50 is operating in this mode it will do the following. 1. it will ignore any signal at the txinclk input pin. 2. the XRT72L50 will output a 44.736mhz clock signal via the rxoutclk output pin. this clock signal functions as the transmit payload data input interface block clock signal. 3. the XRT72L50 will use the rising edge of the rxoutclk signal to latch in the data residing on the txser input pin. b. serial mode the XRT72L50 will accept the ds3 payload data from the terminal equipment, in a serial-manner, via the txser input pin the transmit payload data input in- terface block will latch this data into its circuitry, on the rising edge of the rxoutclk output clock signal. c. delineation of outbound ds3 frames the XRT72L50 will pulse the txframe output pin "high" for one bit-period coincident with the XRT72L50 processing the last bit of a given ds3 frame. d. sampling of payload data, from the terminal equipment in mode 1, the XRT72L50 will sample the data at the txser input, on the rising edge of rxoutclk. interfacing the transmit payload data input inter- face block (of the XRT72L50) to the terminal equipment for mode 1 operation txframeref input transmit frame reference input: the XRT72L50 permits the user to configure the transmit section to use this input pin as a frame reference. if the user makes this configuration selection, then the transmit section will initiate its transmission of a new ds3 frame, upon the rising edge of this signal. the purpose of this input pin is to permit the terminal equipment to maintain transmit ds3 framing alignment control over the XRT72L50. rxoutclk output loop-timed timing reference clock output pin: the transmit section of the XRT72L50 can be configured to use the rxlineclk signal as the timing reference (e.g., loop-timing). if the user has made this configuration selection, then the XRT72L50 will: ? output a 44.736 mhz clock signal via this pin, to the terminal equipment. ? sample the data on the txser input pin, upon the rising edge of this clock signal. t able 18: l isting and d escription of the pins associated with the t ransmit p ayload d ata i nput i nterface s ignal n ame t ype d escription ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 144 figure 44 presents an illustration of the transmit pay- load data input interface block (within the XRT72L50) being interfaced to the terminal equipment, for mode 1 operation. mode 1, operation of the terminal equipment when the XRT72L50 is operating in this mode, it will function as the source of the 44.736mhz clock signal (via the rxoutclk signal). this clock signal will be used as the terminal equipment interface clock by both the XRT72L50 ic and the terminal equipment. the terminal equipment will serially output the pay- load data of the outbound ds3 data stream via its ds3_data_out pin. the terminal equipment will up- date the data on the ds3_data_out pin upon the ris- ing edge of the 44.736 mhz clock signal, at its ds3_clock_in input pin (as depicted in figure 44 and figure 45). the XRT72L50 will latch the outbound ds3 data stream (from the terminal equipment) on the rising edge of the rxoutclk signal. the XRT72L50 will indicate that it is processing the last bit, within a given outbound ds3 frame, by puls- ing its txframe output pin "high" for one bit-period. when the terminal equipment detects this pulse at its tx_start_of_frame input, it is expected to begin transmission of the very next outbound ds3 frame to the XRT72L50 via the ds3_data_out (or txser pin). finally, the XRT72L50 will indicate that it is about to process an overhead bit by pulsing the txoh_ind output pin "high" one bit period prior to its processing of an oh (overhead) bit. in figure 44, the txoh_ind output pin is connected to the ds3_overhead_ind in- put pin of the terminal equipment. whenever the ds3_overhead_ind pin is pulsed "high" the terminal equipment is expected to not transmit a ds3 payload bit upon the very next clock edge. instead, the termi- nal equipment is expected to delay its transmission of the very next payload bit, by one clock cycle. the behavior of the signals, between the XRT72L50 and the terminal equipment, for ds3 mode 1 opera- tion is illustrated in figure 45. f igure 44. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block ( of the XRT72L50) for m ode 1(s erial /l oop -t iming ) o peration terminal equipment xrt72l5x ds3 framer ds3_data_out ds3_clock_in tx_start_of_frame ds3_overhead_ind txser rxoutclk txframe txoh_ind nibint 44.736 mhz xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 145 . how to configure the XRT72L50 into the serial/ loop-timed/non-overhead interface mode 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit fields (within the framer operating mode register) to "00", as illustrated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 44. n ote : the XRT72L50 framer ic cannot support the framer local loop-back mode of operation, when operat- ing in the loop-timing mode. the user must configure the XRT72L50 framer ic into any of the following modes, prior to configuring the framer local loop-back mode. ? mode 2 - serial/local-timed/frame-slave mode. ? mode 3 - serial/local-timed/frame-master mode. ? mode 5 - nibble-parallel/local-timed/frame-slave mode. ? mode 6 - nibble-parallel/local-timed/frame-mas- ter mode. for more detailed information on framer local loop- back mode of operation, please see section 6.0. 4.2.1.2 mode 2 - the serial/local-timed/ frame-slave mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows. f igure 45. b ehavior of the t erminal i nterface signals between the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 and the t erminal e quipment ( for m ode 1 o peration ) terminal equipment signals ds3_clock_in ds3_data_out tx_start_of_frame ds3_overhead_ind xrt72l5x transmit payload data i/f signals rxoutclk txser txframe txoh_ind payload[4702] payload[4703] x-bit payload[0] payload[4702] payload[4703] x-bit payload[0] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: txframe pulses high to denote ds3 frame boundary. note: txoh_ind pulses high to denote overhead data (e.g., the x-bit). framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 0 0 0 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 146 a. local-timing - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal as its timing reference. b. serial mode the XRT72L50 will receive the ds3 payload data, in a serial manner, via the txser input pin. the trans- mit payload data input interface (within the XRT72L50) will latch this data into its circuitry, on the rising edge of the txinclk input clock signal. c. delineation of outbound ds3 frames (frame slave mode) the transmit section (of the XRT72L50) will use the txinclk input as its timing reference, and will use the txframeref input signal as its framing reference. in other words, the transmit section of the XRT72L50 will initiate frame generation upon the rising edge of the txframeref input signal). d. sampling of payload data, from the terminal equipment in mode 2, the XRT72L50 will sample the data, at the txser input pin, on the rising edge of txinclk. interfacing the transmit payload data input inter- face block (of the XRT72L50) to the terminal equipment for mode 2 operation figure 46 presents an illustration of the transmit pay- load data input interface block (within the XRT72L50) being interfaced to the terminal equipment, for mode 2 operation. mode 2, operation of the terminal equipment as shown in figure 46, both the terminal equipment and the XRT72L50 will be driven by an external 44.736mhz clock signal. the terminal equipment will receive the 44.736mhz clock signal via its ds3_clock_in input pin, and the XRT72L50 framer ic will receive the 44.736mhz clock signal via the tx- inclk input pin. the terminal equipment will serially output the pay- load data of the outbound ds3 data stream, via the ds3_data_out output pin, upon the rising edge of the signal at the ds3_clock_in input pin. n ote : the ds3_data_out output pin of the terminal equipment is electrically connected to the txser input pin. the XRT72L50 framer ic will latch the data, residing on the txser input line, on the rising edge of the txin- clk signal. in this case, the terminal equipment has the respon- sibility of providing the framing reference signal by pulsing its tx_start_of_frame output signal (and in turn, the txframeref input pin of the XRT72L50), "high" for one-bit period, coincident with the first bit of a new ds3 frame. once the XRT72L50 detects the rising edge of the input at its txframeref input pin, it will begin generation of a new ds3 frame. f igure 46. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 2 (s erial /l ocal -t imed /f rame -s lave ) o peration terminal equipment xrt72l5x ds3 framer ds3_data_out ds3_clock_in tx_start_of_frame ds3_overhead_ind txser txinclk txframeref txoh_ind nibint 44.736 mhz clock source xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 147 n otes : 1. in this case, the terminal equipment is controlling the start of frame generation, and is therefore referred to as the frame master. conversely, since the XRT72L50 does not control the generation of a new ds3 frame, but is rather driven by the terminal equipment. hence, the XRT72L50 is referred to as the frame slave. 2. if the user opts to configure the XRT72L50 to oper- ate in mode 2, it is imperative that the tx_start_of_frame (or txframeref) signal is syn- chronized to the txinclk input clock signal. finally, the XRT72L50 will pulse its txoh_ind output pin, one bit-period prior to it processing a given over- head bit, within the outbound ds3 frame. since the txoh_ind output pin of the XRT72L50 is electrically connected to the ds3_overhead_ind, whenever the XRT72L50 pulses the txoh_ind output pin "high", it will also be driving the ds3_overhead_ind input pin (of the terminal equipment) "high". whenever the terminal equipment detects this pin toggling "high", it should delay transmission of the very next ds3 frame payload bit by one clock cycle. the behavior of the signals between the XRT72L50 and the terminal equipment for ds3 mode 2 opera- tion is illustrated in figure 47. how to configure the XRT72L50 to operate in this mode. 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01" as depicted below. f igure 47. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (m ode 2 o peration ) terminal equipment signals ds3_clock_in ds3_data_out tx_start_of_frame ds3_overhead_ind xrt72l5x transmit payload data i/f signals txinclk txser txframeref txoh_ind payload[4702] payload[4703] x-bit payload[1] payload[4702] payload[4703] x-bit payload[1] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: txframe pulses high to denote ds3 frame boundary. note: txoh_ind pulses high to denote overhead data (e.g., the x-bit). framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 148 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 46. 4.2.1.3 mode 3 - the serial/local-timed/ frame-master mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows. a. local timing - (uses the txinclk signal as the timing reference) in this mode, the transmit section of the XRT72L50 will use the txinclk signal as its timing reference. b. serial mode the XRT72L50 will receive the ds3 payload data, in a serial manner, via the txser input pin. the trans- mit payload data input interface (within the XRT72L50) will latch this data into its circuitry, on the rising edge of the txinclk input clock signal. c. delineation of outbound ds3 frames (frame master mode) the transmit section of the XRT72L50 will use the txinclk signal as its timing reference, and will initiate ds3 frame generation, asynchronously with respect to any externally applied signal. the XRT72L50 will pulse its txframe output pin "high" whenever its it processing the very last bit-field within a given ds3 frame. d. sampling of payload data, from the terminal equipment in mode 3, the XRT72L50 will sample the data, at the txser input pin, on the rising edge of txinclk. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 3 operation figure 48 presents an illustration of the transmit pay- load data input interface block (within the XRT72L50) being interfaced to the terminal equipment, for mode 3 operation. mode 3 operation of the terminal equipment in figure 48, both the terminal equipment and the XRT72L50 are driven by an external 44.736mhz clock signal. this clock signal is connected to the ds3_clock_in input of the terminal equipment and the txinclk input pin of the XRT72L50. the terminal equipment will serially output the pay- load data on its ds3_data_out output pin, upon the 0 0 101 0 0 1 framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 f igure 48. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 3 (s erial /l ocal -t imed /f rame -m aster ) o peration terminal equipment xrt72l5x ds3 framer ds3_data_out ds3_clock_in tx_start_of_frame ds3_overhead_ind txser txinclk txframe txoh_ind nibint 44.736 mhz clock source xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 149 rising edge of the signal at the ds3_clock_in input pin. similarly, the XRT72L50 will latch the data, resid- ing on the txser input pin, on the rising edge of txin- clk. the XRT72L50 will pulse the txframe output pin "high" for one bit-period, coincident while it is pro- cessing the last bit-field within a given outbound ds3 frame. the terminal equipment is expected to moni- tor the txframe signal (from the XRT72L50) and to place the first bit, within the very next outbound ds3 frame on the txser input pin. n ote : in this case, the XRT72L50 dictates exactly when the very next ds3 frame will be generated. the terminal equipment is expected to respond ap- propriately by providing the XRT72L50 with the first bit of the new ds3 frame, upon demand. hence, in this mode, the XRT72L50 is referred to as the frame master and the terminal equipment is referred to as the frame slave. finally, the XRT72L50 will pulse its txoh_ind output pin, one bit-period prior to it processing a given over- head bit, within the outbound ds3 frame. since the txoh_ind output pin (of the XRT72L50) is electrically connected to the ds3_overhead_ind whenever the XRT72L50 pulses the txoh_ind output pin "high", it will also be driving the ds3_overhead_ind input pin (of the terminal equipment) "high". whenever the terminal equipment detects this pin toggling "high", it should delay transmission of the very next ds3 frame payload bit by one clock cycle. the behavior of the signal between the XRT72L50 and the terminal equipment for ds3 mode 3 opera- tion is illustrated in figure 49. how to configure the XRT72L50 to operate in this mode. 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "10 or 11" as depicted below. f igure 49. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (ds3 m ode 3 o peration ) terminal equipment signals ds3_clock_in ds3_data_out tx_start_of_frame ds3_overhead_ind xrt72l5x transmit payload data i/f signals txinclk txser txframe txoh_ind payload[4702] payload[4703] x-bit payload[1] payload[4702] payload[4703] x-bit payload[1] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: txframe pulses high to denote ds3 frame boundary. note: txoh_ind pulses high to denote overhead data (e.g., the x-bit). ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 150 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 48. 4.2.1.4 mode 4 - the nibble-parallel/loop- timed mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. a. looped timing (uses the rxlineclk as the timing reference) in this mode, the transmit section of the XRT72L50 will use the rxlineclk signal as its timing reference. when the XRT72L50 is operating in the nibble-mode, it will internally divide the rxlineclk signal, by a fac- tor of four (4) and will output this signal via the txnib- clk output pin. b. nibble-parallel mode the XRT72L50 will accept the ds3 payload data, from the terminal equipment in a nibble-parallel man- ner, via the txnib[3:0] input pins. the transmit ter- minal equipment input interface block will latch this data into its circuitry, on the rising edge of the txnib- clk output signal. c. delineation of the outbound ds3 frames the XRT72L50 will pulse the txnibframe output pin "high" for one bit-period coincident with the XRT72L50 processing the last nibble of a given ds3 frame. d. sampling of payload data, from the terminal equipment in mode 4, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the rxoutclk clock signal, following a pulse in the txnib- clk signal (see figure 51). n ote : the txnibclk signal, from the XRT72L50 operates nominally at 11.184 mhz (e.g., 44.736 mhz divided by 4). however, for reasons described below, txnibclk effectively operates at a "low"er clock frequency. the transmit pay- load data input interface is only used to accept the payload data, which is intended to be carried by outbound ds3 frames. the transmit payload data input interface is not designed to accommodate the entire ds3 data stream. the ds3 frame consists of 4704 payload bits or 1176 nibbles. therefore, the XRT72L50 will supply 1176 txnibclk pulses between the rising edges of two con- secutive txnibframe pulses. the ds3 frame repeti- tion rate is 9.398khz. hence, 1176 txnibclk pulses for each ds3 frame period amounts to txnibclk run- ning at approximately 11.052 mhz. the method by which the 1176 txnibclk pulses are distributed throughout the ds3 frame period is presented below. nominally, the transmit section within the XRT72L50 will generate a txnibclk pulse for every 4 rxoutclk (or txinclk) periods. however, in 14 cases (within a ds3 frame period), the transmit payload data input interface will allow 5 txinclk periods to occur be- tween two consecutive txnibclk pulses. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 4 operation figure 50 presents an illustration of the transmit pay- load data input interface block (within the XRT72L50) being interfaced to the terminal equipment, for mode 4 operation. framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 0 1 x xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 151 mode 4 operation of the terminal equipment when the XRT72L50 is operating in this mode, it will function as the source of the 11.184mhz (e.g., the 44.736mhz clock signal divided by "4") clock signal, that will be used as the terminal equipment interface clock by both the XRT72L50 and the terminal equip- ment. the terminal equipment will output the payload data of the outbound ds3 data stream via its ds3_data_out[3:0] pins on the rising edge of the 11.184mhz clock signal at the ds3_nib_clock_in in- put pin. the XRT72L50 will latch the outbound ds3 data stream (from the terminal equipment) on the rising edge of the txnibclk output clock signal. the XRT72L50 will indicate that it is processing the last nibble, within a given ds3 frame, by pulsing its txnib- frame output pin "high" for one txnibclk clock peri- od. when the terminal equipment detects a pulse at its tx_start_of_frame input pin, it is expected to transmit the first nibble, of the very next outbound ds3 frame to the XRT72L50 via the ds3_data_out[3:0] (or txnib[3:0] pins). finally, for the nibble-parallel mode operation, the XRT72L50 will continuously pull the txohind output pin "low". the behavior of the signals between the XRT72L50 and the terminal equipment for ds3 mode 4 opera- tion is illustrated in figure 51. f igure 50. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 4 (n ibble -p arallel /l oop -t imed ) o peration terminal xrt72l5x ds3 ds3_data_out[3:0 ] ds3_nib_clock_in tx_start_of_fram txnib[3:0] txnibclk txnibframe nibint vcc 4 rxlineclk 44.736mhz 11.184mhz ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 152 how to configure the XRT72L50 into mode 4 1. set the nibintf input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to 00" as illus- trated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 50. n ote : the XRT72L50 framer ic cannot support the framer local loop-back mode of operation. the user must configure the XRT72L50 framer ic into any of the following modes, prior to configuring the framer local-loop-back mode operation. ? mode 2 - serial/local-timed/frame-slave mode. ? mode 3 - serial/local-timed/frame-master mode. ? mode 5 - nibble-parallel/local-timed/frame-slave mode. ? mode 6 - nibble-parallel/local-timed/frame-mas- ter mode. for more detailed information on the framer local loop-back mode operation, please see section 6.0. f igure 51. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (m ode 4 o peration ) terminal equipment signals xrt72l5x transmit payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: txnibframe pulses high to denote ds3 frame boundary. rxoutclk tx_start_of_frame ds3_nib_clock_in ds3_data_out[3:0] nibble [1175] nibble [0] rxoutclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of xrt72l5x device framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 0 0 0 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 153 4.2.1.5 mode 5 - the nibble-parallel/local- timed/frame-slave interface mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows: a. local-timed (uses the txinclk signal as the timing reference) in this mode, the transmit section of the XRT72L50 will use the txinclk signal at its timing reference. further, the chip will internally divide the txinclk clock signal by a factor of 4 and will output this divid- ed clock signal via the txnibclk output pin. the transmit terminal equipment input interface block (within the XRT72L50) will use the rising edge of the txnibclk signal, to latch the data, residing on the tx- nib[3:0] into its circuitry. b. nibble-parallel mode the XRT72L50 will accept the ds3 payload data, from the terminal equipment, in a parallel manner, via the txnib[3:0] input pins. the transmit terminal equipment input interface will latch this data into its circuitry, on the rising edge of the txnibclk output signal. c. delineation of outbound ds3 frames the transmit section will use the txinclk input signal as its timing reference and will use the txframeref input signal as its framing reference (e.g., the trans- mit section of the XRT72L50 initiates frame genera- tion upon the rising edge of the txframeref signal). n ote : in this case, the terminal equipment should pulse the txframeref input signal (of the XRT72L50 framer ic) coincident with it applying the first payload nibble, within a given outbound ds3 frame. hence, the duration of this pulse should be one nibble-period of the ds3 signal (see figure 53). d. sampling of payload data, from the terminal equipment in mode 5, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the txinclk clock signal, following a pulse in the txnibclk signal (see figure 53). n ote : the txnibclk signal, from the XRT72L50 operates nominally at 11.184 mhz (e.g., 44.736 mhz divided by 4). however, for reasons described below, txnibclk effectively operates at a "low"er clock frequency. the transmit pay- load data input interface is only used to accept the payload data, which is intended to be carried by outbound ds3 frames. the transmit payload data input interface is not designed to accommodate the entire ds3 data stream. the ds3 frame consists of 4704 payload bits or 1176 nibbles. therefore, the XRT72L50 will supply 1176 txnibclk pulses between the rising edges of two con- secutive txnibframe pulses. the ds3 frame repeti- tion rate is 9.398khz. hence, 1176 txnibclk pulses for each ds3 frame period amounts to txnibclk run- ning at approximately 11.052 mhz. the method by which the 1176 txnibclk pulses are distributed throughout the ds3 frame period is presented below. nominally, the transmit section within the XRT72L50 will generate a txnibclk pulse for every 4 rxoutclk (or txinclk) periods. however, in 14 cases (within a ds3 frame period), the transmit payload data input interface will allow 5 txinclk periods to occur be- tween two consecutive txnibclk pulses. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 5 operation figure 52 presents an illustration of the transmit pay- load data input interface block (within the XRT72L50) being interfaced to the terminal equipment, for mode 5 operation. ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 154 mode 5 operation of the terminal equipment in figure 52 both the terminal equipment and the XRT72L50 will be driven by an external 11.184mhz clock signal. the terminal equipment will receive the 11.184mhz clock signal via the ds3_nib_clock_in input pin. the XRT72L50 will output the 11.184mhz clock signal via the txnibclk output pin. the terminal equipment will serially output the data on the ds3_data_out[3:0] pins, upon the rising edge of the signal at the ds3_clock_in input pin. n ote : the ds3_data_out[3:0] output pins of the terminal equipment is electrically connected to the txnib[3:0] input pins. the XRT72L50 will latch the data, residing on the tx- nib[3:0] input pins, on the rising edge of the txnibclk signal. in this case, the terminal equipment has the respon- sibility of providing the framing reference signal by pulsing the tx_start_of_frame output pin (and in turn, the txframeref input pin of the XRT72L50) "high" for one bit-period, coincident with the first nib- ble of a new ds3 frame. once the XRT72L50 detects the rising edge of the input at its txframeref input pin, it will begin generation of a new ds3 frame. finally, the XRT72L50 will always internally generate the overhead bits, when it is operating in both the ds3 and nibble-parallel modes. the XRT72L50 will pull the txohind input pin "low". the behavior of the signals between the XRT72L50 and the terminal equipment for ds3 mode 5 opera- tion is illustrated in figure 53. f igure 52. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 5 (n ibble -p arallel /l ocal -t imed /f rame -s lave ) o per - ation terminal equipment xrt72l5x ds3 framer ds3_data_out[3:0] ds3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txframeref nibint vcc 4 44.736mhz clock source txinclk 11.184mhz xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 155 how to configure the XRT72L50 into mode 5 1. set the nibintf input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01" as illus- trated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 52. 4.2.1.6 mode 6 - the nibble-parallel/txinclk/ frame-master interface mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows: a. local-timed (uses the txinclk signal as the timing reference) in this mode, the transmit section of the XRT72L50 will use the txinclk signal at its timing reference. further, the chip will internally divide the txinclk clock signal by a factor of 4 and will output this divid- ed clock signal via the txnibclk output pin. the transmit terminal equipment input interface block (within the XRT72L50) will use the rising edge of the f igure 53. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (ds3 m ode 5 o peration ) terminal equipment signals xrt72l5x transmit payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: txframeref is pulsed high to denote first nibble within a new ds3 frame txinclk tx_start_of_frame ds3_nib_clock_in ds3_data_out[3:0] nibble [0] nibble [1] txinclk txframeref txnibclk txnib[3:0] nibble [0] nibble [1] nibble [1175] nibble [1175] sampling edge of the xrt72l5x device framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0010 1 0 0 1 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 156 txnibclk signal, to latch the data, residing on the tx- nib[3:0] into its circuitry. b. nibble-parallel mode the XRT72L50 will accept the ds3 payload data, from the terminal equipment, in a parallel manner, via the txnib[3:0] input pins. the transmit terminal equipment input interface will latch this data into its circuitry, on the rising edge of the txnibclk output signal. c. delineation of outbound ds3 frames the transmit section will use the txinclk input signal as its timing reference and will initiate the generation of ds3 frames, asynchronous with respect to any ex- ternal signal. the XRT72L50 will pulse the txframe output pin "high" whenever it is processing the last nibble, within a given outbound ds3 frame. d. sampling of payload data, from the terminal equipment in mode 6, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the txinclk clock signal, following a pulse in the txnibclk signal (see figure 55). n ote : the txnibclk signal from the XRT72L50, operates nominally at 11.184 mhz (e.g., 44.736 mhz divided by 4). however, for reasons described below, txnibclk effectively operates at a "low"er clock frequency. the transmit pay- load data input interface is only used to accept the payload data, which is intended to be carried by outbound ds3 frames. the transmit payload data input interface is not designed to accommodate the entire ds3 data stream. the ds3 frame consists of 4704 payload bits or 1176 nibbles. therefore, the XRT72L50 will supply 1176 txnibclk pulses between the rising edges of two con- secutive txnibframe pulses. the ds3 frame repeti- tion rate is 9.398khz. hence, 1176 txnibclk pulses for each ds3 frame period amounts to txnibclk run- ning at approximately 11.052 mhz. the method by which the 1176 txnibclk pulses are distributed throughout the ds3 frame period is presented below. nominally, the transmit section within the XRT72L50 will generate a txnibclk pulse for every 4 rxoutclk (or txinclk) periods. however, in 14 cases (within a ds3 frame period), the transmit payload data input interface will allow 5 txinclk periods to occur be- tween two consecutive txnibclk pulses. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 6 operation figure 54 presents an illustration of the transmit pay- load data input interface block (within the XRT72L50) being interfaced to the terminal equipment, for mode 6 operation. mode 6 operation of the terminal equipment in figure 54 both the terminal equipment and the XRT72L50 will be driven by an external 11.184mhz clock signal. the teriminal equipment will receive f igure 54. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 6 (n ibble -p arallel /l ocal -t imed /f rame -m aster ) o peration terminal equipment xrt72l5x ds3 framer ds3_data_out[3:0] ds3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txnibframe nibint vcc 4 44.736mhz clock source txinclk 11.184mhz xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 157 the 11.184mhz clock signal via the ds3_nib_clock_in input pin. the XRT72L50 will out- put the 11.184mhz clock signal via the txnibclk out- put pin. the terminal equipment will serially output the data on the ds3_data_out[3:0] pins upon the rising edge of the signal at the ds3_clock_in input pin. the XRT72L50 will latch the data, residing on the tx- nib[3:0] input pins, on the rising edge of the txnibclk signal. in this case the XRT72L50 has the responsibility of providing the framing reference signal by pulsing the txframe output pin (and in turn the tx_start_of_frame input pin of the terminal equip- ment) "high" for one bit-period, coincident with the last bit within a given ds3 frame. finally, the XRT72L50 will always internally generate the overhead bits, when it is operating in both the ds3 and nibble-parallel modes. the XRT72L50 will pull the txohind input pin "low". the behavior of the signals between the XRT72L50 and the terminal equipment for ds3 mode 6 opera- tion is illustrated in figure 55. how to configure the XRT72L50 into mode 6 1. set the nibint input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to 1x as illus- trated below. f igure 55. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (ds3 m ode 6 o peration ) terminal equipment signals xrt72l5x transmit payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: txnibframe pulses high to denote ds3 frame boundary. txinclk tx_start_of_frame ds3_nib_clock_in ds3_data_out[3:0] nibble [1175] nibble [0] txinclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of the xrt72l5x device ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 158 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 54. 4.2.2 the transmit overhead data input inter- face figure 56 presents a simple illustration of the trans- mit overhead data input interface block within the XRT72L50. the ds3 frame consists of 4760 bits. of these bits, 4704 bits are payload bits and the remaining 56 bits are overhead bits. the XRT72L50 has been de- signed to handle and process both the payload type and overhead type bits for each ds3 frame. within the transmit section within the XRT72L50, the trans- mit payload data input interface has been designed to handle the payload data. likewise, the transmit overhead data input interface has been designed to handle and process the overhead bits. the transmit section of the XRT72L50 generates or processes the various overhead bits within the ds3 frame, in the following manner. the frame synchronization overhead bits (e.g., the f and m bits) the f and m bits are always internally generated by the transmit section of the XRT72L50. these over- head bits are used (by the remote terminal equip- ment) for frame synchronization purposes. hence, the user cannot insert his/her value for the f and m bits into the outbound ds3 data stream, via the transmit overhead data input interface. any attempt to externally insert values for the f and m bits, will be ignored by the transmit overhead data input in- terface"high" block. framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0010 1 0 1 x f igure 56. s imple i llustration of the t ransmit o verhead d ata i nput i nterface block transmit overhead data input interface block transmit overhead data input interface block txohframe txohenable txoh txohclk txohins to transmit ds3 framer block xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 159 the performance monitoring overhead bits (p and cp bits) the p-bits are always internally generated by the transmit section of the XRT72L50. the p bits are used by the remote terminal equipment to perform error-checking/detection of a ds3 data stream, as it is transmitted from one terminal equipment to adja- cent terminal equipment (e.g., point-to-point check- ing). hence, the user cannot insert his/her value for the p-bits into the outbound ds3 data stream, via the transmit overhead data input interface. in contrast to p bits, cp bits are used perform er- ror-checking/detection of a ds3 data stream from the source terminal equipment to the sink terminal equipment. in applications where a given ds3 data stream is received via one port, and is output via an- other port, it is necessary that the cp bit-values re- main constant. the only way to insure this to (1) ex- tract out the cp bit values, via the receiving line card and (2) insert these cp-bit values into the out- bound ds3 data stream, via the transmit overhead data input interface block. hence, the transmit over- head data input interface block will permit the user to externally insert the cp bits into the outbound ds3 data stream. the alarm and signaling related overhead bits bits that are used to transport the alarm conditions can be either internally generated by the transmit section within the XRT72L50, or can be externally generated and inserted into the outbound ds3 data stream, via the transmit overhead data input inter- face. the ds3 frame overhead bits that fall into this category are: ? the x bits ? the feac bits ? the febe bits. the data link related overhead bits the ds3 frame structure also contains bits which can be used to transport user data link information and path maintenance data link information. the udl (user data link) bits are only accessible via the transmit overhead data input interface. the path maintenance data link (pmdl) bits can either be sourced from the transmit lapd controller/buffer or via the transmit overhead data input interface. table 19 lists the overhead bits within the ds3 frame. additionally, this table also indicates whether or not these overhead bits can be sourced by the transmit overhead data input interface or not. n otes : * the XRT72L50 contains mask register bits that per- mit the user to alter the state of the internally generat- ed value for these bits. + the transmit lapd controller/buffer can be config- ured to be the source of the dl bits, within the out- bound ds3 data stream. in all, the transmit overhead data input interface per- mits the user to insert overhead data into the out- bound ds3 frames via the following two different methods. ? method 1 - using the txohclk clock signal ? method 2 - using the txinclk and the txohenable signals. each of these methods are described below. 4.2.2.1 4.2.2.1 method 1 - using the txohclk clock signal t able 19: a l isting of the o verhead bits within the ds3 frame , and their potential sources , within the XRT72L50 ic o verhead b it i nternally generated a ccessible via the t ransmit o verhead d ata i nput i nterface b uffer /r egister a ccessible pyes no yes* x yes yes yes fyes no yes* myes no yes* feac no yes yes f e b e ye s ye s ye s dl no yes yes+ udl no yes no cp no yes no ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 160 the transmit overhead data input interface consists of the five signals. of these five (5) signals, the fol- lowing four (4) signals are to be used when imple- menting method 1. ? txoh ? txohclk ? txohframe ? txohins each of these signals are listed and described below. table 20. interfacing the transmit overhead data input in- terface to the terminal equipment. figure 57 illustrates how one should interface the transmit overhead data input interface to the termi- nal equipment, when using method 1. t able 20: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input inter- face to accept overhead data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of the txohclk output signal. conversely, setting this pin "low" configures the transmit overhead data input interface to not sample (e.g., ignore) the data at the txoh input pin, on the falling edge of the txohclk output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the transmit overhead data input interface (e.g., if the terminal equipment asserts the txohins signal, at a time when one of these non-insertable overhead bits are being processed), that par- ticular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the overhead bit position within the very next outbound ds3 frame. if the txohins pin is pulled "high", the transmit overhead data input interface will sam- ple the data at this input pin (txoh), on the falling edge of the txohclk output pin. conversely, if the txohins pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. txohclk output transmit overhead input interface clock output signal: this output signal serves two purposes: 1. the transmit overhead data input interface will provide a rising clock edge on this signal, one bit-period prior to the instant that the transmit overhead data input interface is processing an overhead bit. 2. the transmit overhead data input interface will sample the data at the txoh input, on the fall- ing edge of this clock signal (provided that the txohins input pin is "high"). n ote : the transmit overhead data input interface will supply a clock edge for all overhead bits within the ds3 frame (via the txohclk output signal). this includes those overhead bits that the transmit overhead data input interface will not accept from the terminal equipment. txohframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L50 is processing the last bit within a given ds3 frame. the purpose of this output signal is to alert the terminal equipment that the transmit overhead data input interface block is about to begin processing the overhead bits for a new ds3 frame. xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 161 method 1 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the outbound ds3 data stream, (via the transmit overhead data input interface), then it is expected to do the following. 1. to sample the state of the txohframe signal (e.g., the tx_start_of_frame input signal) on the rising edge of the txohclk (e.g., the ds3_oh_clock_in signal). 2. to keep track of the number of rising clock edges that have occurred, via the txohclk (e.g., the ds3_oh_clock_in signal) since the last time the txohframe signal was sampled "high". by doing this the terminal equipment will be able to keep track of which overhead bit is being pro- cessed by the transmit overhead data input interface block at any given time. when the ter- minal equipment knows which overhead bit is being processed, at a given txohclk period, it will know when to insert a desired overhead bit value into the outbound ds3 data stream. from this, the terminal equipment will know when it should assert the txohins input pin and place the appropriate value on the txoh input pin (of the XRT72L50). table 21relates the number of rising clock edges (in the txohclk signal, since txohframe was sampled "high") to the ds3 overhead bit, that is being pro- cessed. f igure 57. i llustration of the t erminal e quipment being interfaced to the t ransmit o verhead d ata i nput i nterface (m ethod 1) terminal equipment xrt72l5x ds3 framer ds3_oh_out] ds3_oh_clock_in tx_start_of_frame txohclk txohframe txohins 44.736 mhz clock source txinclk txoh insert_oh rxlineclk 44.736 mhz clock source ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 162 t able 21: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since t x ohf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being processed n umber of r ising c lock e dges in t x ohc lk t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? 0 (clock edge is coincident with txo- hframe being detected "high") xyes 1f1no 2aicyes 3f0no 4nayes 5f0no 6feacyes 7f1no 8xyes 9f1no 10 udl yes 11 f0 no 12 udl yes 13 f0 no 14 udl yes 15 f1 no 16 p no 17 f1 no 18 cp yes 19 f0 no 20 cp yes 21 f0 no 22 cp yes 23 f1 no 24 p no 25 f1 no 26 febe yes 27 f0 no 28 febe yes 29 f0 no 30 febe yes 31 f1 no 32 m0 no 33 f1 no 34 dl yes 35 f0 no 36 dl yes 37 f0 no xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 163 3. after the terminal equipment has waited the appropriate number of clock edges (from the txohframe signal being sampled "high"), it should assert the txohins input signal. concur- rently, the terminal equipment should also place the appropriate value (of the inserted overhead bit) onto the txoh signal. 4. the terminal equipment should hold both the txohins input pin "high" and the value of the txoh signal, stable until the next rising edge of txohclk is detected. case study: the terminal equipment intends to insert the appropriate overhead bits into the transmit overhead data input interface (using method 1) in order to transmit a yellow alarm to the remote terminal equipment. in this example, the terminal equipment intends to in- sert the appropriate overhead bits, into the transmit overhead data input interface, such that the XRT72L50 will transmit a yellow alarm to the remote terminal equipment. recall that, for ds3 applica- tions, a yellow alarm is transmitted by setting both of the x bits (within each outbound ds3 frame) to 0. if one assumes that the connection between the ter- minal equipment and the XRT72L50 are as illustrated in figure 57 then figure 58 presents an illustration of the signaling that must go on between the terminal equipment and the XRT72L50. 38 dl yes 39 f1 no 40 m1 no 41 f1 no 42 udl yes 43 fo no 44 udl yes 45 fo no 46 udl yes 47 f1 no 48 m0 no 49 f1 no 50 udl yes 51 f0 no 52 udl yes 53 f0 no 54 udl yes 55 f1 no t able 21: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since t x ohf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being processed n umber of r ising c lock e dges in t x ohc lk t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 164 in figure 58 the terminal equipment samples the tx- ohframe signal being "high" at the rising clock edge # 0. at this point, the terminal equipment knows that the XRT72L50 is just about to process the very first overhead bit within a given outbound ds3 frame. ad- ditionally, according to table 21, the very first over- head bit to be processed is the first x bit. in order to facilitate the transmission of the yellow alarm, the terminal equipment must set this x bit to 0. hence, the terminal equipment starts this process by imple- menting the following steps concurrently. a. assert the txohins input pin by setting it "high". b. set the txoh input pin to 0. after the terminal equipment has applied these sig- nals, the XRT72L50 will sample the data on both the txohins and txoh signals upon the very next falling edge of txohclk (designated at 0- in figure 58. once the XRT72L50 has sampled this data, it will then insert a "0" into the first x bit position, in the out- bound ds3 frame. upon detection of the very next rising edge of the tx- ohclk clock signal (designated as clock edge 1 in figure 58), the terminal equipment will negate the txohins signal (e.g., toggles it "low") and will cease inserting data into the transmit overhead data input interface, until rising clock edge # 8 (of the txohclk signal). according to table 21, rising clock edge # 8 indicates that the XRT72L50 is just about ready to process the second x bit within the outbound ds3 frame. once again, in order to facilitate the transmis- sion of the yellow alarm this x-bit must also be set to 0. hence, the terminal equipment will (once again) implement the following steps, concurrently. a. assert the txohins input pin by setting it "high". b. set the txoh input to 0. once again, after the terminal equipment has ap- plied these signals, the XRT72L50 will sample the da- ta on both the txohins and txoh signal upon the very next falling edge of txohclk (designated as 8- in figure 58). once the XRT72L50 has sampled this data, it will then insert a "0" into the second x bit posi- tion, in the outbound ds3 frame. 4.2.2.2 method 2 - using the txinclk and txo- henable signals f igure 58. i llustration of the signal that must occur between the t erminal e quipment and the XRT72L50, in order to configure the XRT72L50 to transmit a y ellow a larm to the remote terminal equipment terminal equipment/xrt72l5x interface signals txohclk txohins txohframe txoh remaining overhead bits with ds3 frame x bit = 0 x bit = 0 txohframe is sample high terminal equipment asserts txohins and data on txoh line xrt72l5x device samples the txohins and txoh signals. txohframe is sample high terminal equipment asserts txohins and data on txoh line xrt72l5x device samples the txohins and txoh signals. 0 0- 1 2 3 4 5 6 7 8 8- xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 165 method 1 requires the use of an additional clock sig- nal, txohclk. however, there may be a situation in which the user does not wish to accommodate and process this extra clock signal to their design, in order to use the transmit overhead data input interface. hence, method 2 is available. when using method 2, either the txinclk or rxoutclk signal is used to sam- ple the overhead bits and signals which are input to the transmit overhead data input interface. method 2 involves the use of the following signals: ? txoh ? txinclk ? txohframe ? txohenable each of these signals are listed and described in table 22. interfacing the transmit overhead data input interface to the terminal equipment figure 59 illustrates how one should interface the transmit overhead data input interface to the termi- nal equipment when using method 2. t able 22: d escription of m ethod 2 t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohenable output transmit overhead data enable output pin the XRT72L50 will assert this signal, for one txinclk period, just prior to the instant that the transmit overhead data input interface is processing an overhead bit. txohframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L50 is processing the last bit within a given ds3 frame. txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input inter- face to accept overhead data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of the txinclk output signal. conversely, setting this pin "low" configures the transmit overhead data input interface to not sample (e.g., ignore) the data at the txoh input pin, on the falling edge of the txohclk output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the transmit overhead data input interface (e.g., if the terminal equipment asserts the txohins signal, at a time when one of these non-insertable overhead bits are being processed), that par- ticular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the overhead bit position within the very next outbound ds3 frame. if the txohins pin is pulled "high", the transmit overhead data input interface will sam- ple the data at this input pin (txoh), on the falling edge of the txohclk output pin. conversely, if the txohins pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 166 method 2 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the outbound ds3 data stream (via the transmit overhead data input interface), then it is ex- pected to do the following. 1. to sample the state of both the txohframe and the txohenable input signals, via the ds3_clock_in (e.g., either the txinclk or the rxoutclk signal of the XRT72L50) signal. if the terminal equipment samples the txohenable signal "high", then it knows that the XRT72L50 is about to process an overhead bit. further, if the terminal equipment samples both the txo- hframe and the txohenable pins "high" (at the same time) then the terminal equipment knows that the XRT72L50 is about to process the first overhead bit, within a new ds3 frame. 2. to keep track of the number of times that the txohenable signal has been sampled "high" since the last time both the txohframe and the txohenable signals were sampled "high". by doing this, the terminal equipment will be able to keep track of which overhead bit the transmit overhead data input interface is about ready to process. from this, the terminal equipment will know when it should assert the txohins input pin and place the appropriate value on the txoh input pins (of the XRT72L50). table 23 also relates the number of txohenable out- put pulses (that have occurred since both the txo- hframe and txohenable pins were sampled "high") to the ds3 overhead bit, that is being processed. f igure 59. i llustration of the t erminal e quipment being interfaced to the t ransmit o verhead d ata i nput i nterface (m ethod 2) terminal equipment xrt72l5x ds3 framer ds3_oh_out ds3_oh_enable tx_start_of_frame txohenable txohframe txohins 44.736 mhz clock source txinclk txoh insert_oh rxlineclk 44.736 mhz clock source ds3_clock_in xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 167 t able 23: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the ds3 o verhead b it , that is being processed by the XRT72L50 n umber of t x ohe nable p ulses t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? 0 (the txohenable and txohframe signals are both sampled "high") xyes 1f1no 2aicyes 3f0no 4nayes 5f0no 6feacyes 7f1no 8xyes 9f1no 10 udl yes 11 f0 no 12 udl yes 13 f0 no 14 udl yes 15 f1 no 16 p no 17 f1 no 18 cp yes 19 f0 no 20 cp yes 21 f0 no 22 cp yes 23 f1 no 24 p no 25 f1 no 26 febe yes 27 f0 no 28 febe yes 29 f0 no 30 febe yes 31 f1 no 32 m0 no 33 f1 no 34 dl yes 35 f0 no 36 dl yes 37 f0 no ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 168 3. after the terminal equipment has waited through the appropriate number of pulses via the txo- henable pin, it should then assert the txohins input signal. concurrently, the terminal equip- ment should also place the appropriate value (of the inserted overhead bit) onto the txoh signal. 4. the terminal equipment should hold both the txohins input pin "high" and the value of the txoh signal stable, until the next txohenable pulse is detected. case study: the terminal equipment intends to insert the appropriate overhead bits into the transmit overhead data input interface (using method 2) in order to transmit a yellow alarm to the remote terminal equipment. in this case, the terminal equipment intends to insert the appropriate overhead bits, into the transmit over- head data input interface such that the XRT72L50 will transmit a yellow alarm to the remote terminal equipment. recall that, for ds3 applications, a yel- low alarm is transmitted by setting all of the x bits to 0. if one assumes that the connection between the ter- minal equipment and the XRT72L50 is as illustrated in figure 59 then, figure 60 presents an illustration of the signaling that must go on between the terminal equipment and the XRT72L50. 38 dl yes 39 f1 no 40 m1 no 41 f1 no 42 udl yes 43 fo no 44 udl yes 45 fo no 46 udl yes 47 f1 no 48 m0 no 49 f1 no 50 udl yes 51 f0 no 52 udl yes 53 f0 no 54 udl yes 55 f1 no t able 23: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the ds3 o verhead b it , that is being processed by the XRT72L50 n umber of t x ohe nable p ulses t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 169 4.2.3 the transmit ds3 hdlc controller the transmit ds3 hdlc controller block can be used to transport either bit-oriented signaling (bos) or message-oriented signaling (mos) type messag- es or both types of messages to the remote terminal equipment. both bos and mos types of hdlc mes- sage processing are discussed in detail below. 4.2.3.1 bit-oriented signaling (or feac mes- sage) processing via the transmit ds3 hdlc controller. the transmit ds3 hdlc controller block consists of two major blocks: ? the transmit feac processor. ? the lapd transmitter. this section describes how to operate the transmit feac processor. if the transmit ds3 framer is oper- ating in the c-bit parity framing format then the feac (far-end alarm & control) bit-field of the ds3 frame can be used to transmit the feac messages (see figure 42). the feac code word is a 6-bit val- ue which is encapsulated by 10 framing bits, forming a 16-bit feac message of the form: where '[d5, d4, d3, d2, d1, d0]' is the feac code word. the rightmost bit (e.g., a 1) of the feac mes- sage, is transmitted first. since each ds3 frame con- tains only 1 feac bit, 16 ds3 frames are required to transmit the 16 bit feac code message. the XRT72L50 contains the following two registers that support feac message transmission. ? tx ds3 feac register (address = 0x32) ? tx ds3 feac configuration and status register (address = 0x33) operating the transmit feac processor in order to transmit a feac message to the remote terminal, the user must execute the following steps. f igure 60. b ehavior of t ransmit o verhead d ata i nput i nterface signals between the XRT72L50 and the t erminal e quipment ( for m ethod 2) txinclk txohframe txohenable txohins txoh terminal equipment samples txohframe and txohenable being high terminal equipment responds by asserting txohins and placing desired data on txoh. xrt72l5x samples txoh here. txohenable pulse # 8 x bit = 0 x bit = 0 0 d5 d4 d3 d2 d1 d0011111111 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 170 1. write the 6-bit feac code (to be sent) into the tx ds3 feac register. 2. enable the transmit feac processor. 3. initiate the transmission of the feac message. each of these steps will be described in detail below. step 1 - writing in the six bit feac codeword (to be sent) in this step, the p/c writes the six bit feac code word into the tx ds3 feac register. the bit format of this register is presented below. step 2 - enabling the transmit feac processor in order to enable the transmit feac processor (within the transmit ds3 hdlc controller block) the user must write a 1 into bit 2 (tx feac enable) within the tx ds3 feac configuration and status register, as depicted below. at this point, the transmit feac processor can be commanded to begin transmission (see step 3). step 3 - initiate the transmission of the feac message the user can initiate the transmission of the feac code word (residing in the tx ds3 feac register) by writing a 1 to bit 1 (tx feac go) within the tx ds3 feac configuration and status register, as depicted below. n ote : while executing this particular write operation, the user should write the binary value 000xx110b into the tx ds3 feac configuration and status register. by doing this the user insures that a 1 is also being written to bit 2 (tx feac enable) of the register, in order to keep the transmit feac processor enabled. once this step has been completed, the transmit feac processor will proceed to transmit the 16 bit feac code via the outbound ds3 frames. this 16 bit feac message will be transmitted repeatedly 10 consecutive times. hence, this process will require a total of 160 ds3 frames. during this process the tx feac busy bit (bit 0, within the transmit ds3 feac configuration and status register) will be asserted, indicating that the tx feac processor is currently transmitting the feac message to the remote termi- nal. this bit-field will toggle to "0" upon completion of the 10th transmission of the feac code message. the transmit feac processor will generate an inter- rupt (if enabled) to the local p/c, upon completion of the 10th transmission of the feac message. the purpose of having the framer ic generating this inter- rupt is to let the local p/c know that the transmit feac processor is now available and ready to trans- mit a new feac message. finally, once the transmit feac processor has completed its 10th transmission of a feac code message it will then begin sending tx ds3 feac register (address = 0x32) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1b it 0 not used txfeac[5] txfeac[4] txfeac[3] txfeac[2] txfeac[1] txfeac[0] not used ro r/w r/w r/w r/w r/w r/w r0 0 d5 d4 d3 d2 d1 d0 0 transmit ds3 feac configuration and status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 not used not used not used txfeac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w ro r/w r/w r0 xxxxx 1xx transmit ds3 feac configuration and status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 not used not used not used txfeac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w ro r/w r/w r0 xxxxx1 1x xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 171 all 1s in the feac bit-field of each ds3 frame. the receive feac processor (at the remote terminal equipment) will interpret this all 1s message as an idle feac message. the transmit feac processor will continue sending all 1s in the feac bit field, for an indefinite period of time, until the local p/c com- mands it to transmit a new feac message. figure 61 presents a flow chart depicting how to use the transmit feac processor. for a detailed description of the receive feac pro- cessor (within the receive ds3 hdlc controller block), please see section 3.3.3.1. 4.2.3.2 message-oriented signaling (e.g., lap-d) processing via the transmit ds3 hdlc controller the lapd transmitter (within the transmit ds3 hdlc controller block) allows the user to transmit path maintenance data link (pmdl) messages to the remote terminal via the outbound ds3 frames. in this case the message bits are inserted into and car- ried by the 3 dl bit fields of f-frame #5 within each ds3 m-frame. the on-chip lapd transmitter sup- ports both the 76 byte and 82 byte length message formats, and the framer ic allocates 88 bytes of on- chip ram (e.g., the transmit lapd message buffer) to store the message to be transmitted. the mes- sage format complies with itu-t q.921 (lap-d) pro- tocol with different addresses and is presented below in figure 62. f igure 61. a f low c hart depicting how to transmit a feac m essage via the feac t ransmitter start start write six-bit outbound feac value into the txds3 feac register this register is located at address 0x32. write six-bit outbound feac value into the txds3 feac register this register is located at address 0x32. enable the transmit feac processor. this is accomplished by writing xxxx x1xx into the txds3 feac configuration & status register enable the transmit feac processor. this is accomplished by writing xxxx x1xx into the txds3 feac configuration & status register initiate transmission of the outbound feac message. this is accomplished by writing xxxx xx1x into the txds3 feac configuration & status register. initiate transmission of the outbound feac message. this is accomplished by writing xxxx xx1x into the txds3 feac configuration & status register. transmit feac processor encapsulates the outbound feac value into a 16 bit framing structure . transmit feac processor encapsulates the outbound feac value into a 16 bit framing structure . transmit feac processor proceeds to insert the 16-bit message (in a bit-by-bit manner) into the feac bit-fields of each outbound ds3 frame. transmit feac processor proceeds to insert the 16-bit message (in a bit-by-bit manner) into the feac bit-fields of each outbound ds3 frame. is transmission of the 16 bit feac message complete ? is transmission of the 16 bit feac message complete ? has the 16-bit feac message been transmitted to the remote terminal 10 times ? has the 16-bit feac message been transmitted to the remote terminal 10 times ? generate the transmit feac interrupt generate the transmit feac interrupt invoke the transmit feac interrupt service routine. invoke the transmit feac interrupt service routine. 1 1 1 1 no yes no yes ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 172 where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the following sections defines each of these bit/byte- fields within the lapd message frame format. flag sequence byte the flag sequence byte is of the value 0x7e, and is used to for two purposes 1. to denote the boundaries of the lapd message frame, and 2. to function as the idle pattern (e.g., transmit hdlc controller block transmits a continuous stream of flag sequence octets, whenever no lapd message is being transmitted). sapi - service access point identifier the sapi bit-fields are assigned the value of 001111b or 15 (decimal). tei - terminal endpoint identifier the tei bit-fields are assigned the value of 0x00. the tei field is used in n-isdn systems to identify a terminal out of multiple possible terminal. however, since the framer ic transmits data in a point-to-point manner, the tei value is unimportant. control the control identifies the type of frame being trans- mitted. there are three general types of frame for- mats: information, supervisory, and unnumbered. the framer assigned the control byte the value 0x03. hence, the framer will be transmitting and receiving unnumbered lapd message frames. information payload the information payload is the 76 bytes or 82 bytes of data (e.g., the pmdl message) that the user has writ- ten into the on-chip transmit lapd message buffer (which is located at addresses 0x86 through 0xdd). it is important to note that the user must write in a specific octet value into the first byte position within the transmit lapd message buffer (located at ad- dress = 0x86, within the framer). the value of this octet depends upon the type of lapd message frame/pmdl message that the user wishes to trans- mit. table 24 presents a list of the various types of lapd message frames/pmdl messages that are supported by the XRT72L50 framer and the corre- sponding octet value that the user must write into the first octet position within the transmit lapd message buffer. frame check sequence bytes f igure 62. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) t able 24: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i nformation p ayload lapd m essage t ype v alue of f irst b yte , within i nformation p ayload of m essage m essage s ize cl path identification 0x38 76 bytes idle signal identification 0x34 76 bytes test signal identification 0x32 76 bytes itu-t path identification 0x3f 82 bytes xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 173 the 16 bit fcs (frame check sequence) is calculat- ed over the lapd message header and information payload bytes, by using the crc-16 polynomial, x 16 + x 12 + x 5 + 1. operation of the lapd transmitter if a message is to be transmitted via the lapd trans- mitter, the information portion (or the body) of the message must be written into the transmit lapd message buffer, which is located at 0x86 through 0xdd in on-chip ram via the microprocessor inter- face. afterwards, the user must do three things: 1. specify the length of lapd message to be trans- mitted. 2. enable the lapd transmitter. 3. initiate the transmission of the pmdl message. each of these steps will be discussed in detail. step 1 - specifying the length of the lapd mes- sage one of two different sizes of lapd messages can be transmitted. this is accomplish by writing the appro- priate data to bit 1 within the tx ds3 lapd configu- ration register. the bit-format of this register is pre- sented below. the relationship between the contents of bit-fields 1 and the lapd message size is given in table 25. n ote : the message type selected must correspond with the contents of the first byte of the information (payload) portion, as presented in table 24. step 2 - enabling the lapd transmitter prior to the transmission of any data via the lapd transmitter the lapd transmitter must be enabled. this is accomplish this by writing a 1 to bit 0 of the tx ds3 lapd configuration register, as depicted below. bit 0 - txlapd enable this bit-field allow the user to enable or disable the lapd transmitter in accordance with table 26. transmit ds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0000x0 xx t able 25: r elationship between t x lapd m sg l ength and the lapd m essage s ize t x lapd m sg l ength lapd m essage l ength 0 lapd message size is 76 bytes 1 lapd message size is 82 bytes transmit ds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0000x0x 1 t able 26: r elationship between t x lapd m sg l ength and the lapd m essage s ize t x lapd e nable r esulting a ction of the lapd t ransmitter 0 the lapd transmitter is disabled and the dl bits, in the ds3 frame, are transmitted as all 1s. 1 the lapd transmitter is enabled and is transmitting a continuous stream of flag sequence octets (0x7e). ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 174 prior to executing step 2 (enabling the lapd trans- mitter), the lapd transmitter will be disabled and the transmit ds3 framer block will be setting each of the dl bits (within the outbound ds3 data stream) to 1. after the user executes this step, the lapd transmit- ter will begin transmitting the flag sequence octet (0x7e) via the dl bits. n ote : upon power up or reset, the lapd transmitter is disabled. therefore, the user must set this bit to "1" in order to enable the lapd transmitter. step 3 - initiate the transmission at this point, the lapd transmitter is ready to begin transmission. the user has written the information portion of the pmdl message into the on-chip trans- mit lapd message buffer. further, the user has specified the type of lapd message that he/she wishes to transmit, and has enabled the lapd trans- mitter. the only thing remaining to do is to initiate the transmission of this message. the user initiates this process by writing a "1" to bit 3 of the tx ds3 lapd status/interrupt register (txdl start). the bit format of this register is presented below. a "0" to "1" transition of bit 3 (txdl start) in this reg- ister, initiates the transmission of the data link mes- sage. while the lapd transmitter is transmitting the message, the 'txdl busy' (bit 2) bit will be set to 1. this bit-field allows the user to poll the status of the lapd transmitter. once the message transfer is completed, this bit-field will toggle back to '0'. the user can configure the lapd transmitter to inter- rupt the c/p upon completion of transmission of the lapd message, by setting bit-field "1" (txlapd interrupt enable) of the tx ds3 lapd status/inter- rupt register to 1. the purpose of this interrupt is to let the local c/p know that the lapd transmitter is available and ready to transmit a new message. bit 0 will reflect the interrupt status for the lapd transmit- ter. n ote : this bit-field will be reset on reading this register. details associated with the transmission of a pmdl message once the user has invoked the txdl start command, the lapd transmitter will do the following. ? generate the four octets of lapd frame header (e.g., flag sequence, sapi, tei, control, etc.) and insert it into the lapd message, prior to the user's information (see the lapd message frame format in figure 62). ? compute the 16 bit frame check sum (fcs) of the lapd message frame (e.g., of the lapd message header and information payload) and append this value to the lapd message. ? append a trailer flag sequence octet to the end of the message lapd (following the 16 bit fcs value). ? serialize the composite lapd message and begin inserting the lapd message into the dl bit fields of each outgoing ds3 frame. ? complete the transmission of the frame overhead, payload, fcs value, and trailer flag sequence octet via the transmit ds3 framer. once the lapd transmitter has completed its trans- mission of the lapd message, the framer will gener- ate an interrupt to the local c/p (if enabled). after- wards, the lapd transmitter will proceed to retrans- mit the lapd message, repeatedly at one second in- tervals. during idle periods (e.g., in between these transmission of the lapd message), the lapd transmitter will be sending a continuous stream of flag sequence bytes. the lapd transmitter will continue this behavior until the user has disabled the lapd transmitter by writing a "0" to bit 0 (txlapd enable) within the tx ds3 lapd configuration reg- ister. if the lapd transmitter is idle, then it will con- tinuously send the flag sequence octets (via the dl bits of each outbound ds3 frame) to the remote ter- minal equipment. n ote : in order to prevent the user's data (e.g., the payload portion of the lapd message frame) from mimicking the flag sequence byte, the lapd transmitter will insert a "0" into the lapd data stream immediately following the detec- tion of five (5) consecutive 1s (this stuffing occurs only while the information payload is being transmitted). the 'remote' lapd receiver (see section 4.3.3.2) will have the responsi- bility of detecting the 5 consecutive 1s and removing the transmit ds3 lapd status/interrupt register (address = 0x34) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 not used tx dl start tx dl busy txlapd interrupt enable txlapd interrupt status r/o r/o r/o r/o r/w ro r/w rur 0000 1xxx xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 175 subsequent "0" from the payload portion of the incoming lapd message. figure 63 presents a flow chart depicting the proce- dure (in 'white boxes') that the user should use in or- der to transmit a lapd message. this figure also in- dicates (via the shaded boxes) what the lapd trans- mitter circuitry will do before and during message transmission. the mechanics of transmitting a new lapd mes- sage as mentioned above, after the lapd transmitter has been enabled, and commanded to transmit the mes- sage, residing in the transmit lapd message buffer, it will continue to transmit this message at one-sec- ond intervals. if another (e.g., different) pmdl mes- sage is to be transmitted to the remote lapd re- ceiver, the new message will have to be written into the transmit lapd message buffer, via the micropro- cessor interface section of the framer. however, care must be taken when writing in this new message. if this message is written into the transmit lapd mes- sage buffer at the wrong time (with respect to these one-second transmissions), the user's action could interfere with these transmissions, thereby causing the lapd transmitter to transmit a corrupted mes- sage to the remote lapd receiver. in order to avoid this problem, while writing the new message into the transmit lapd message buffer, the user should do the following: 1. configure the framer to automatically reset acti- vated interrupts this can be done by writing a "1" into bit 3 of the framer operating mode register, as depicted below. f igure 63. f low c hart depict how to use the lapd t ransmitter start start write in data link information the user accomplishes this by writing the information that he/she wishes to transmit (via the lapd transmitter) to locations 0x86 through 0xdd, within the framer address space. enable the lapd transmitter for transmission this is accomplished by writing 00000xx1b to the tx ds3 lapd configuration register. (where xx dictates lapd message length) initiate transmission of lapd message this is accomplished by writing 000010x0b to the tx ds3 lapd status/interrupt register. (where x indicates the users choice to enable/disable lapd message transfer complete interrupt lapd transmitter inserts frame header octets in front of the user payload. lapd transmitter computes the 16 bit fcs (a crc-16 value) and inserts it into the lapd message, following the user payload lapd transmitter appends a flag sequence trailer octet to the end of the lapd message (after the 16 bit fcs). is 5 consecutive 1s detected ? is message transmission complete ? insert a 0 after the string of 5 consecutive 1s end generate interrupt lapd transmitter will continue to transmit flag sequence octets. yes no yes no ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 176 this action will prevent the lapd transmitter from generating its own one-second interrupts. 2. enable the one-second interrupt this can be done by writing a "1" into bit 0 of the block interrupt enable register, as depicted below. 3. write the new message into the transmit lapd message buffer immediately after the occurrence of the one-second interrupt. by timing the writes to the transmit lapd message buffer to occur immediately after the occurrence of the one-second interrupt, the user avoids conflicting with the one-second transmissions of the lapd mes- sage, and will transmit the correct messages to the remote lapd receiver. 4.2.4 the transmit ds3 framer block 4.2.4.1 brief description of the transmit ds3 framer the transmit ds3 framer block accepts data from any of the following three sources, and uses it to form the ds3 data stream. ? the transmit payload data input block ? the transmit overhead data input block ? the transmit hdlc controller block ? the internal overhead data generator the manner in how the transmit ds3 framer block handles data from each of these sources is described below. handling of data from the transmit payload data input interface for ds3 applications, all data that is input to the transmit payload data input interface will be inserted into the payload bit positions within the outbound ds3 frames. handling of data from the internal overhead bit generator by default, the transmit ds3 framer block will inter- nally generate the overhead bits. however, if the ter- minal equipment inserts its own values for the over- head bits (via the transmit overhead data input inter- face) or, if the user enables and employs the transmit ds3 hdlc controller block, then these internally generated overhead bits will be overwritten. handling of data from the transmit overhead da- ta input interface for ds3 applications, the transmit ds3 framer block automatically generates and inserts the framing align- ment bits (e.g., the f and m bits) into the outbound ds3 frames. further, the transmit ds3 framer block will automatically compute and insert the p-bits into the outbound ds3 frames. hence, the transmit ds3 framer block will not accept data from the transmit oh data input interface block for the f, m and p bits. however, the transmit ds3 framer block will accept (and insert) data from the transmit overhead data in- put interface for the following bit-fields. ? x-bits ? febe bits ? feac bits ? dl bits ? udl bits ? cp bits framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 local loop- back ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0110 1xxx block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one second interrupt enable r/wrororororor/w r/w 0000000 x xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 177 if the user's local data link equipment activates the transmit overhead data input interface block and writes data into this interface for these bits, then the transmit ds3 framer block will insert this data into the appropriate overhead bit-fields, within the out- bound ds3 frames. handling of data from the transmit hdlc con- troller block the exact manner in how the transmit ds3 framer handles data from the transmit hdlc controller block depends upon whether the transmit hdlc controller is transmitting bos (bit oriented signal- ing) or mos (message oriented signaling) data. if the transmit ds3 hdlc controller block is not acti- vated, then the transmit ds3 framer block will insert a 1 into each feac and dl bit-field, within each outbound ds3 frame. if the transmit ds3 hdlc controller block is activat- ed, and is configured to transmit either a bos or mos type message, then data will be inserted into the feac and dl bit-fields as described in section 3.2.3. 4.2.4.2 detailed functional description of the transmit ds3 framer block the transmit ds3 framer receives data from the fol- lowing three sources and combines them together to form a ds3 data stream. ? the transmit payload data input interface block. ? the transmit overhead data input interface block ? the transmit hdlc controller block. afterwards, this ds3 data stream will be routed to the transmit ds3 liu interface block, for further process- ing. figure 64 presents a simple illustration of the trans- mit ds3 framer block, along with the associated paths to the other functional blocks within the chip. in addition to taking data from multiple sources and multiplexing them, in appropriate manner, to create the outbound ds3 frames, the transmit ds3 framer block has the following roles. ? generating alarm conditions ? generating errored frames (for testing purposes) ? routing outbound ds3 frames to the transmit ds3 liu interface block each of these additional roles are discussed below. 4.2.4.2.1 generating alarm conditions the transmit ds3 framer block permits the user to, by writing the appropriate data into the on-chip regis- ters, to override the data that is being written into the transmit payload data and overhead data input in- terfaces and transmit the following alarm conditions. ? generate the yellow alarms (or ferf indicators) ? manipulate the x-bit (set them to 1) ? generate the ais pattern ? generate the idle pattern ? generate the los pattern ? generate ferf (yellow) alarms, in response to detection of a red alarm condition (via the receive section of the XRT72L50). f igure 64. a s imple i llustration of the t ransmit ds3 f ramer b lock and the associated paths to other f unctional b locks transmit ds3 framer block transmit ds3 framer block transmit hdlc controller/buffer transmit overhead data input interface transmit payload data input interface to transmit ds3 liu interface block ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 178 ? generate and transmit a desired value for febe (far-end-block error). the procedure and results of generating any of these alarm conditions is presented below. the user can exercise each of these options by writ- ing the appropriate data to the tx ds3 configuration register (address = 0x30). the bit format of this reg- ister is presented below. the role/function of each of these bit-fields within the register, are discussed below. 4.2.4.2.1.1 transmit yellow alarm - bit 7 this read/write bit field permits the user to force the transmission of a yellow alarm to the remote terminal equipment via software control. if the user opts to transmit a yellow alarm then both of the x-bits, within the outbound ds3 frames will be set to '0'. table 27 relates the content of this bit field to the transmit ds3 framer block's action. n ote : this bit is ignored when either the txidle, txais, or the txlos bit-fields are set. 4.2.4.2.1.2 transmit x-bit - bit 6 this bit field functions as the logical complement to bit 7 (e.g., tx yellow alarm). this read/write bit field permits the user to force all of the x-bits, in the out- bound ds3 frames, to "1" and transmit them to the re- mote terminal equipment. table 28 relates the con- tent of this bit field to the transmit ds3 framer block's action. n ote : this bit is ignored when either the transmit yellow alarm, tx ais, tx idle, or txlos bit is set. 4.2.4.2.1.3 transmit idle pattern - bit 5 this read/write bit field permits the user to transmit an idle pattern to the remote terminal equipment upon software control. table 29 relates the contents of this bit field to the transmit ds3 framer's action. tx ds3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 tx yellow alarm tx x-bit tx idle pattern tx ais pattern tx los pattern ferf on los ferf on oof ferf on ais r/w r/w r/w r/w r/w r/w r/w r/w 0010 1011 t able 27: t he r elationship between the contents of b it 7 (t x y ellow a larm ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 7t ransmit ds3 f ramer ' s a ction 0 normal operation: the x-bits are generated by the transmit ds3 framer block based upon near end receiving conditions (as detected by the receive section of the chip) 1 transmit yellow alarm: the transmit ds3 framer block will overwrite the x-bits by setting them all to 0. the payload information is not modified and is transmitted as normal. t able 28: t he r elationship between the contents of b it 6 (t x x-b its ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 6t ransmit ds3 f ramer ' s a ction 0 normal operation: the x-bits are generated by the transmit ds3 framer block based upon receiving conditions (as detected by the receive section of the framer chip). 1 set x-bits to 1: the transmit ds3 framer will overwrite the x-bits by setting them to 1. payload information is not modified and is transmitted as normal. xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 179 n ote : this bit is ignored when either the tx ais or the tx los bit is set. 4.2.4.2.1.4 transmit ais pattern - bit 4 this read/write bit field allows the user to transmit an ais pattern to the remote terminal equipment, upon software control. table 30 relates the contents of this bit field to the transmit ds3 framer block's action. n ote : this bit is ignored when the txlos bit is set. 4.2.4.2.1.5 transmit los pattern - bit 3 this read/write bit field allows the user to transmit an los (loss of signal) pattern to the remote terminal, upon software control. table 31 relates the contents of this bit field to the transmit ds3 framer block's ac- tion. t able 29: t he r elationship between the contents of b it 5 (t x i dle ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer a ction b it 5t ransmit ds3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the transmit overhead data input interface or the transmit hdlc controller blocks. the payload bits are received from the transmit payload data input interface. 1 transmit idle condition pattern: when this command is invoked, the transmit ds3 framer will do the following: ? set the x-bits to 1 ? set the cp-bits (f-frame #3) to 0 ? generate valid m, f, and p bits overwrite the data in the ds3 payload with a repeating 1100... pattern. t able 30: t he r elationship between the contents of b it 4 (t x ais p attern ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 4t ransmit ds3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the transmit overhead data input interface or the transmit hdlc controller blocks. the payload bits are received from the transmit payload data input interface. 1 transmit ais pattern: when this command is invoked, the transmit ds3 framer block will do the following. ? set the x-bits to 1 ? set all the c-bits to 0 ? generate valid m, f, and p bits overwrite the data in the ds3 payload with a repeating 1010... pattern ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 180 n ote : when this bit is set, it overrides all of the other bits in this register. 4.2.4.2.1.6 ferf (far-end receive failure) on los - bit 2 this read/write bit-field allows the user to configure the transmit ds3 framer block to automatically gen- erate a yellow alarm if the near-end receive section (of the XRT72L50) detects a los (loss of signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. 4.2.4.2.1.7 ferf (far-end receive failure) on oof - bit 1 this read/write bit-field allows the user to configure the transmit ds3 framer block to automatically gen- erate a yellow alarm if the near-end receive section (of the XRT72L50) detects an oof (out-of-frame) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. 4.2.4.2.1.8 ferf (far-end receive failure) on ais - bit 0 this read/write bit-field allows the user to configure the transmit ds3 framer block to automatically gen- erate a yellow alarm if the near-end receive section (of the XRT72L50) detects an ais (alarm indication signal) pattern. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. 4.2.4.2.1.9 transmitting febe (far-end block error) values by default, the transmit ds3 framer block will set the three (3) febe bit-fields to [1, 1, 1] if all of the follow- ing conditions are true. ? the local receive ds3 framer block detects no p- bit errors. ? the local receive ds3 framer block detects no cp-bit errors conversely, the transmit ds3 framer block will set the three (3) febe bit-fields to a value other than [1, 1, 1] if any one of the following conditions are true. ? the local receive ds3 framer block detects a p- bit error in the most recently received ds3 frame. ? the local receive ds3 framer block detects a cp bit error in the most recently received ds3 frame. 4.2.4.2.2 generating errored ds3 frames the transmit ds3 framer block permits the user to insert errors into the framing and error detection over- head bits (e.g., the p, m and f-bits) of the outbound ds3 data stream in order to support far-end equip- ment testing. the user can exercise this option by writing data to any of the numerous transmit ds3 mask registers. these mask registers and their comprising bit-fields are defined below. t able 31: t he r elationship between the contents of b it 3 (t x los) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 3t ransmit ds3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the transmit overhead data input interface or the transmit hdlc controller blocks. the payload bits are received from the transmit payload data input interface. 1 transmit los pattern: when this command is invoked the transmit ds3 framer will do the following. ? set all of the overhead bits to "0" (including the m, f, and p bits) overwrite the ds3 payload bits with an all zeros pattern. tx ds3 m-bit mask register, address = 0x35 b it 7b it 6b it 5b it 4 b it 3 b it 2 b it 1 b it 0 txfebe dat[2] txfebe dat[1] txfebe dat[0] febe reg enable txerr pbit mbit mask(2) mbit mask(1) mbit mask(0) r/w r/w r/w r/w r/w r/w r/w r/w xxxx x x x x xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 181 the bit-fields of the tx ds3 m-bit mask register, that are relevant to error-insertion are shaded. the re- maining bit-fields pertain to the febe bit-fields, and are discussed in section 4.2.4.2.1.9. the tx ds3 m-bit mask register serves two purpos- es 1. it allows the user to transmit his/her own value for febe (3 bits) - please see section 4.2.4.2.1.9. 2. it allows the user to transmit errored p-bits. 3. it allows the user to insert errors into the m-bit (framing bits) in order to support equipment test- ing. each of these bit-fields are discussed below. bit 3 - tx err (transmit errored) p-bit this bit-field allows the user to insert errors into the p-bits, of each outbound ds3 frame, for equipment testing purposes. if this bit-field is 0, then the p-bits are transmitted as calculated from the payload of the previous ds3 frames. however, if this bit-field is 1, then the p-bits are inverted (from their calculated val- ue) prior to transmission. bits 2 - 0: m-bit mask[2:0] the transmit ds3 framer will automatically perform an xor operation with the m-bits (in the ds3 data- stream) and the contents of the corresponding bit- field, within this register. the results of this operation will be written back into the m-bit positions within the outbound ds3 frames. therefore, to insure that no errors are inserted into the m-bits, make sure that the contents of the m-bit mask[2:0] bit-fields are 0. f-bit error insertion the remaining mask registers (tx ds3 f-bit mask1 through mask4 registers) contain bit-fields which cor- respond to each of the 28 f-bits, within the ds3 frame. prior to transmission, these bit-fields are auto- matically xored with the contents of the correspond- ing bit fields within these mask registers. the result of this xor operation is written back into the corre- sponding bit-field, within the outgoing ds3 frame, and is transmitted on the line. therefore, if none of the bits are to be modified, then these registers must con- tain all 0s (the default value). 4.2.5 the transmit ds3 line interface block tx ds3 f-bit mask1 register, address = 0x36 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused unused unused unused fbit mask(27) fbit mask(26) fbit mask(25) fbit mask(24) ro ro ro ro r/w r/w r/w r/w 00000000 tx ds3 f-bit mask2 register, address = 0x37 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask(23) fbit mask(22) fbit mask(21) fbit mask(20) fbit mask(19) fbit mask(18) fbit mask(17) fbit mask(16) r/w r/w r/w r/w r/w r/w r/w r/w 00000000 tx ds3 f-bit mask3 register, address = 0x38 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask(15) fbit mask(14) fbit mask(13) fbit mask(12) fbit mask(11) fbit mask(10) fbit mask(9) fbit mask(8) r/w r/w r/w r/w r/w r/w r/w r/w 00000000 tx ds3 f-bit mask4 register, address = 0x39 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask(7) fbit mask(6) fbit mask(5) fbit mask(4) fbit mask(3) fbit mask(2) fbit mask(1) fbit mask(0) r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 182 the XRT72L50 framer ic is a digital device that takes ds3 payload and overhead bit information from some terminal equipment, processes this data and ul- timately, multiplexes this information into a series of outbound ds3 frames. however, for ds3 coaxial ca- ble applications, the XRT72L50 framer ic lacks the current drive capability to be able to directly transmit this ds3 data stream through some transformer-cou- pled coax cable with enough signal strength for it to comply with the isolated pulse template require- ments and be received by the remote receiver. therefore, in order to get around this problem, the framer ic requires the use of an liu (line interface unit) ic. an liu is a device that has sufficient drive capability, along with the necessary pulse-shaping circuitry to be able to transmit a signal through the transmission medium in a manner that it can (1) com- ply with the dsx-3 isolated pulse template require- ments and (2) be reliably received by the remote ter- minal equipment. figure 65 presents a circuit draw- ing depicting the framer ic interfacing to an liu (xrt7300 ds3/e3/sts-1 transmit liu). the transmit section of the XRT72L50 contains a block which is known as the transmit ds3 liu inter- face block. the purpose of the transmit ds3 liu in- terface block is to take the outbound ds3 data stream, from the transmit ds3 framer block, and to do the following: 1. encode this data into one of the following line codes a. unipolar (e.g., single-rail) b. ami (alternate mark inversion) c. b3zs (bipolar 3 zero substitution) 2. and to transmit this data to the liu ic. figure 66 presents a simple illustration of the trans- mit ds3 liu interface block. f igure 65. a pproach to i nterfacing the XRT72L50 f ramer ic to the xrt73l00 ds3/e3/sts-1 t rans - mitter liu ( one channel shown ) 5v u1 x r t7250 tx p o s 65 tx n e g 64 txlinec lk 63 dmo 79 e xtlos 78 rlol 77 lloop 69 rloop 70 ta o s 68 tx le v 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 tx s e r 46 tx inc l k 43 tx frame 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 x r t7300 tp d a ta 37 tn d a ta 38 tc lk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tr i n g 40 mtip 44 mr in g 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 ta o s 2 tx le v 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 tx s e r tx inc l k nibbleintf resetb rtip rring csb rw ds as tx f rame rxser rxclk rxfra me rxlos rxoof rxred rxais a[8:0] tr i n g ttip intb d[7:0] intb xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 183 the transmit ds3 liu interface block can transmit data to the liu ic or other external circuitry via two different output modes: unipolar or bipolar. if the un- ipolar (or single rail) mode is selected, then the con- tents of the ds3 frame is output, in a binary (nrz manner) data stream via the txpos pin to the liu ic. the txneg pin will only be used to denote the frame boundaries. txneg will pulse "high" for one bit peri- od, at the start of each new ds3 frame, and will re- main "low" for the remainder of the frame. figure 67 presents an illustration of the txpos and txneg sig- nals during data transmission while the transmit ds3 liu interface block is operating in the unipolar mode. this mode is sometimes referred to as single rail mode because the data pulses only exist in one po- larity: positive. when the transmit ds3 liu interface block is operat- ing in the bipolar (or dual rail) mode, then the con- tents of the ds3 frame is output via both the txpos and txneg pins. if the bipolar mode is chosen, then the ds3 data to the liu can be transmitted via one of two different line codes: alternate mark inversion (ami) or binary - 3 zero substitution (b3zs). each one of these line codes will be discussed below. bi- polar mode is sometimes referred to as dual rail be- cause the data pulses occur in two polarities: positive and negative. the role of the txpos, txneg and f igure 66. a s imple i llustration of the t ransmit ds3 liu i nterface block from transmit ds3 framer block txpos txneg txlineclk transmit ds3 liu interface block f igure 67. t he b ehavior of t x pos and t x neg signals during data transmission while the t ransmit ds3 liu i nterface is operating in the u nipolar m ode txpos txneg txlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 frame boundary ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 184 txlineclk output pins, for this mode are discussed below. txpos - transmit positive polarity pulse: the transmit ds3 liu interface block will assert this out- put to the liu ic when it desires for the liu to gener- ate and transmit a positive polarity pulse to the re- mote terminal equipment. txneg - transmit negative polarity pulse: the transmit ds3 liu interface block will assert this out- put to the liu ic when it desires for the liu to gener- ate and transmit a negative polarity pulse to the re- mote terminal equipment. txlineclk - transmit line clock: the liu ic uses this signal from the transmit ds3 liu interface block to sample the state of its txpos and txneg inputs. the results of this sampling dictates the type of pulse (positive polarity, zero, or negative polarity) that it will generate and transmit to the remote receive ds3 framer. 4.2.5.1 selecting the various line codes either the unipolar mode or bipolar mode can be se- lected by writing the appropriate value to bit 3 of the i/ o control register (address = 0x01), as shown be- low. table 32 relates the value of this bit field to the trans- mit ds3 liu interface output mode. n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the operation of the receive ds3 liu interface block 4.2.5.1.1 the bipolar mode line codes if framer is to be operated in the bipolar mode, then the ds3 data-stream can be transmitted via the ami (alternate mark inversion) or the b3zs line codes. the definition of ami and b3zs line codes follow. 4.2.5.1.1.1 the ami line code ami or alternate mark inversion, means that consec- utive one's pulses (or marks) will be of opposite polar- ity with respect to each other. the line code involves the use of three different amplitude levels: +1, 0, and - 1. +1 and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" amplitude pulses (or the absence of a pulse) are used to represent ze- ros (or space) pulses. the general rule for ami is: if a given mark pulse is of positive polarity, then the very next mark pulse will be of negative polarity and vice versa. this alternating-polarity relationship exists be- tween two consecutive mark pulses, independent of the number of 'zeros' that may exist between these two pulses. figure 68 presents an illustration of the ami line code as would appear at the txpos and txneg pins of the framer, as well as the output sig- nal on the line. i/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 32: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c ontrol r egister and the t ransmit ds3 f ramer l ine i nterface o utput m ode b it 3t ransmit ds3 f ramer liu i nterface o utput m ode 0 bipolar mode: ami or b3zs line codes are transmitted and received 1 unipolar (single rail) mode of transmission and reception of ds3 data is selected. xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 185 n ote : one of the main reasons that the ami line code has been chosen for driving transformer-coupled media is that this line code introduces no dc component, thereby minimizing dc distortion in the line. 4.2.5.1.1.2 the b3zs line code the transmit ds3 framer and the associated liu ic combine the data and timing information (originating from the txlineclk signal) into the line signal that is transmitted to the far-end receiver. the far-end re- ceiver has the task of recovering this data and timing information from the incoming ds3 data stream. many clock and data recovery schemes rely on the use of phase locked loop technology. phase- locked-loop (pll) technology for clock recovery re- lies on transitions in the line signal, in order to main- tain lock with the incoming ds3 data stream. howev- er, pll-based clock recovery scheme, are vulnerable to the occurrence of a long stream of consecutive ze- ros (e.g., the absence of transitions). this scenario can cause the pll to lose lock with the incoming ds3 data, thereby causing the clock and data recovery process of the receiver to fail. therefore, some ap- proach is needed to insure that such a long string of consecutive zeros can never happen. one such tech- nique is b3zs encoding. b3zs (or bipolar 3 zero substitution) is a form of ami line coding that imple- ments the following rule. in general the b3zs line code behaves just like ami with the exception of the case when a long string of consecutive zeros occur on the line. any string of 3 consecutive zeros will be replaced with either a 00v or a b0v where b refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the ami coding rule). and v refers to a bipolar violation pulse (e.g., a pulse with a polarity that violates the alternat- ing polarity scheme of ami.) the decision between inserting an 00v or a b0v is made to insure that an odd number of bipolar (b) pulses exist between any two bipolar violation (v) pulses. figure 69 presents a timing diagram that illustrates examples of b3zs en- coding. the user chooses between ami or b3zs line coding by writing to bit 4 of the i/o control register (address = 0x01), as shown below. f igure 68. i llustration of ami l ine c ode data txpos txneg line signal 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 f igure 69. i llustration of two examples of b3zs e ncoding data txpos txneg 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 v line signal b 0 v ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 186 table 33 relates the content of this bit-field to the bi- polar line code that ds3 data will be transmitted and received at. n otes : 1. this bit is ignored if the unipolar mode is selected. 2. this selection also effects the operation of the receive ds3 liu interface block 4.2.5.2 txlineclk clock edge selection the framer also allows the user to specify whether the ds3 output data (via txpos and/or txneg out- put pins) is to be updated on the rising or falling edg- es of the txlineclk signal. the purpose of this fea- ture is to insure that the framer will always be able to output data to the liu ic, in such a way that the liu set-up and hold time requirements can always be met. this selection is made by writing to bit 2 of the i/ o control register, as depicted below. table 34 relates the contents of this bit field to the clock edge of txclk that ds3 data is output on the txpos and/or txneg output pins. n ote : the user will typically make the selection based upon the set-up and hold time requirements of the transmit liu ic. i/o control register (address = 0x01) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/wr/wr/wr/wr/w 101 00000 t able 33: t he r elationship between b it 4 (ami/b3zs*) within the i/o c ontrol r egister and the b ipolar l ine c ode that is output by the t ransmit ds3 liu i nterface b lock b it 4b ipolar l ine c ode 0 b3zs 1ami ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 10100 xx0 t able 34: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 2r esult 0 rising edge: outputs on txpos and/or txneg are updated on the rising edge of txlineclk. see figure 70 for timing relationship between txlineclk, txpos and txneg signals, for this selection. 1 falling edge: outputs on txpos and/or txneg are updated on the falling edge of txlineclk. see figure 71 for timing relationship between txlineclk, txpos and txneg signals, for this selection. xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 187 4.2.6 transmit section interrupt processing the transmit section of the XRT72L50 can generate an interrupt to the microcontroller/microprocessor for the following two reasons. ? completion of transmission of feac message ? completion of transmission of lapd message 4.2.6.1 enabling transmit section interrupts as mentioned in section 1.6, the interrupt structure, within the XRT72L50 contains two hierarchical levels: ? block level ? source level the block level the enable state of the block level for the transmit section interrupts dictates whether or not interrupts (if enabled at the source level), are actually enabled. the user can enable or disable these transmit sec- tion interrupts, at the block level by writing the appro- priate data into bit 1 (tx ds3/e3 interrupt enable) within the block interrupt enable register (address = 0x04), as illustrated below. f igure 70. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the rising edge of t x l ine c lk txlineclk txpos txneg t32 t30 t33 f igure 71. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the falling edge of t x l ine c lk txlineclk txpos txneg t31 t32 t33 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 188 setting this bit-field to 1 enables the transmit sec- tion (at the block level) for interrupt generation. conversely, setting this bit-field to 0 disables the transmit section for interrupt generation. what does it mean for the transmit section inter- rupts to be enabled or disabled at the block lev- el? if the transmit section is disabled (for interrupt gener- ation) at the block level, then all transmit section interrupts are disabled, independent of the interrupt enable/disable state of the source level interrupts. if the transmit section is enabled (for interrupt gener- ation) at the block level, then a given interrupt will be enabled at the source level. conversely, if the trans- mit section is enabled (for interrupt generation) at the block level, then a given interrupt will still be disabled, if it is disabled at the source level. as mentioned earlier, the transmit section of the XRT72L50 framer ic contains the following two inter- rupts ? completion of transmission of feac message interrupt. ? completion of transmission of lapd message interrupt. the enabling/disabling and servicing of each of these interrupts is described below. 4.2.6.1.1 the completion of transmission of feac message interrupt. if the transmit section interrupts have been enabled at the block level, then the user can enable or disable the completion of transmission of a feac message interrupt by writing the appropriate value into bit 4 (tx feac interrupt enable) within the transmit ds3 feac configuration & status register (address = 0x31) as illustrated below. setting this bit-field to 1 enables the completion of transmission of a feac message interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. 4.2.6.1.2 servicing the completion of trans- mission of a feac message interrupt as mentioned earlier, once the user commands the transmit feac processor to begin its transmission of a feac message, it will do the following. 1. it will read in the six-bit contents of the tx ds3 feac register (address = 0x32) and encapsu- late these 6 bits into a 16-bit data structure. 2. the transmit feac processor will then begin to transmit this 16-bit data structure (to the remote terminal equipment) repeatedly for 10 consecu- tive times. 3. upon completion of the 10th transmission, the XRT72L50 framer ic will generate the comple- tion of transmission of a feac message inter- rupt to the microcontroller/microprocessor. once the XRT72L50 framer ic generates this interrupt, it will do the following. ? assert the interrupt output pin (int) by toggling it "low". block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one second interrupt enable r/wrororororor/wr/w 00000000 transmit ds3 feac configuration & status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used tx feac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w rur r/w r/w ro 000x0000 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 189 ? set bit 3 (tx feac interrupt status) within the tx ds3 feac configuration & status register, as illustrated below. the purpose of this interrupt is to alert the microcon- troller/microprocessor that the transmit feac pro- cessor has completed its transmission of a given feac message and is now ready to transmit the next feac message, to the remote terminal equipment. 4.2.6.1.3 the completion of transmission of the lapd message interrupt if the transmit section interrupts have been enabled at the block level, then the user can enable or disable the completion of transmission of a lapd message interrupt by writing the appropriate value into bit 1 (txlapd interrupt enable) within the tx ds3 lapd status & interrupt register (address = 0x34), as illus- trated below. setting this bit-field to 1 enables the completion of transmission of a lapd message interrupt. con- versely, setting this bit-field to 0 disables the com- pletion of transmission of a lapd message interrupt. 4.2.6.1.4 servicing the completion of trans- mission of a lapd message interrupt as mentioned previously, once the user commands the lapd transmitter to begin its transmission of a lapd message, it will do the following. 1. it will parse through the contents of the transmit lapd message buffer (located at address loca- tions 0x86 through 0xdd) and search for a string of five (5) consecutive 1s. if the lapd trans- mitter finds a string of five consecutive 1s (within the content of the lapd message buffer, then it will insert a 0 immediately after this string. 2. it will compute the fcs (frame check sequence) value and append this value to the back-end of the user-message. 3. it will read out of the content of the user (zero- stuffed) message and will encapsulate this data into a lapd message frame. 4. finally, it will begin transmitting the contents of this lapd message frame via the dl bits, within each outbound ds3 frame. 5. once the lapd transmitter has completed its transmission of this lapd message frame (to the remote terminal equipment), the XRT72L50 framer ic will generate the completion of trans- mission of a lapd message interrupt to the microcontroller/microprocessor. once the XRT72L50 framer ic generates this interrupt, it will do the following. ? assert the interrupt output pin (int) by toggling it "low". ? set bit 0 (txlapd interrupt status) within the txds3 lapd status and interrupt register, as illustrated below. transmit ds3 feac configuration & status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used tx feac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w rur r/w r/w ro 00011000 txds3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 190 the purpose of this interrupt is to alert the microcon- troller/microprocessor that the lapd transmitter has completed its transmission of a given lapd (or pm- dl) message, and is now ready to transmit the next pmdl message, to the remote terminal equipment. 4.3 t he r eceive s ection of the XRT72L50 (ds3 m ode o peration ) when the XRT72L50 has been configured to operate in the ds3 mode, the receive section of the XRT72L50 consists of the following functional blocks. ? receive liu interface block ? receive hdlc controller block ? receive ds3 framer block ? receive overhead data output interface block ? receive payload data output interface block figure 72 presents a simple illustration of the receive section of the XRT72L50 framer ic. each of these functional blocks will be discussed in detail in this document. 4.3.1 the receive ds3 liu interface block the purpose of the receive ds3 liu interface block is two-fold: 1. to receive encoded digital data from the ds3 liu ic. 2. to decode this data, convert it into a binary data stream and to route this data to the receive ds3 framer block. txds3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000001 f igure 72. a s imple i llustration of the r eceive s ection of the XRT72L50, when it has been config - ured to operate in the ds3 m ode receive payload data input interface block receive ds3/e3 framer block receive liu interface block rxser rxnib[3:0] rxclk rxpos rxneg rxlineclk receive overhead input interface block rxohclk rxohind rxoh rxohenable rxohframe rxframe rx ds3 hdlc controller/buffer rx ds3 hdlc controller/buffer from microprocessor interface block xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 191 figure 73 presents a simple illustration of the receive ds3 liu interface block. the receive section of the XRT72L50 will via the re- ceive ds3 liu interface block receive timing and data information from the incoming ds3 data stream. the ds3 timing information will be received via the rxli- neclk input pin and the ds3 data information will be received via the rxpos and rxneg input pins. the receive ds3 liu interface block is capable of receiv- ing ds3 data pulses in unipolar or bipolar format. if the receive ds3 framer is operating in the bipolar for- mat, then it can be configured to decode either ami or b3zs line code data. each of these input formats and line codes will be discussed in detail, below. 4.3.1.1 unipolar decoding if the receive ds3 liu interface block is operating in the unipolar (single-rail) mode, then it will receive the single rail nrz ds3 data pulses via the rxpos in- put pin. the receive ds3 liu interface block will al- so receive its timing signal via the rxlineclk signal. n ote : the rxlineclk signal will function as the timing source for the entire receive section of the XRT72L50. no data pulses will be applied to the rxneg input pin. the receive ds3 liu interface block receives a logic "1" when a logic "1" level signal is present at the rxpos pin, during the sampling edge of the rxli- neclk signal. likewise, a logic "0" is received when a logic "0" level signal is applied to the rxpos pin. figure 74 presents an illustration of the behavior of the rxpos, rxneg and rxlineclk input pins when the receive ds3 liu interface block is operating in the unipolar mode. the user can configure the receive ds3 liu inter- face block to operate in either the unipolar or the bi- polar mode by writing the appropriate data to the i/o control register, as depicted below. f igure 73. a s imple i llustration of the r eceive ds3 liu i nterface b lock rxpos rxneg rxlineclk to receive ds3 framer block receive ds3 liu interface block f igure 74. b ehavior of the r x pos, r x neg and r x l ine c lk signals during data reception of u nipolar d ata rxpos rxneg rxlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 192 table 35 relates the value of this bit-field to the re- ceive ds3 liu interface input mode. n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the transmit ds3 framer line interface output mode 4.3.1.2 bipolar decoding if the receive ds3 liu interface block is operating in the bipolar mode, then it will receive the ds3 data pulses via both the rxpos, rxneg, and the rxli- neclk input pins. figure 75 presents a circuit dia- gram illustrating how the receive ds3 liu interface block interfaces to the line interface unit while the framer is operating in bipolar mode. the receive ds3 liu interface block can be configured to decode the incoming data from either the ami or b3zs line codes. ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 35: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 3r eceive ds3 liu i nterface i nput m ode 0 . bipolar mode (dual rail): ami or b3zs line codes are transmitted and received. 1 unipolar mode (single rail) mode of transmission and reception of ds3 data is selected. f igure 75. i llustration on how the r eceive ds3 f ramer ( within the XRT72L50 f ramer ic) being inter - faced to the xrt73l00 liu, while the f ramer is operating in b ipolar m ode ( one channel shown ) 5v u1 xrt7250 txpos 65 txneg 64 txlineclk 63 dmo 79 extlos 78 rlol 77 lloop 69 rloop 70 taos 68 txlev 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 txser 46 txinclk 43 txframe 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 xrt7300 tpdata 37 tndata 38 tclk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tring 40 mtip 44 mring 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 taos 2 txlev 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 txser txinclk nibbleintf resetb rtip rring csb rw ds as txframe rxser rxclk rxframe rxlos rxoof rxred rxais a[8:0] tring ttip intb d[7:0] intb xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 193 4.3.1.2.1 ami decoding ami or alternate mark inversion, means that consec- utive one's pulses (or marks) will be of opposite polar- ity with respect to each other. this line code involves the use of three different amplitude levels: +1, 0, and - 1. the +1 and -1 amplitude signals are used to repre- sent one's (or mark) pulses and the "0" amplitude pulses (or the absence of a pulse) are used to repre- sent zeros (or space) pulses. the general rule for the ami line code is: if a given mark pulse is of positive polarity, then the very next mark pulse will be of nega- tive polarity and vice versa. this alternating-polarity relationship exists between two consecutive mark pulses, independent of the number of zeros that exist between these two pulses. figure 76 presents an il- lustration of the ami line code as would appear at the rxpos and rxneg input pins of the framer, as well as the corresponding output signal on the line. n ote : one of the reasons that the ami line code has been chosen for driving copper medium, isolated via trans- formers, is that this line code has no dc component, thereby eliminating dc distortion in the line. 4.3.1.2.2 b3zs decoding the transmit ds3 liu interface block and the associ- ated liu embed and combine the data and clocking information into the line signal that is transmitted to the remote terminal equipment. the remote terminal equipment has the task of recovering this data and timing information from the incoming ds3 data stream. most clock and data recovery schemes rely on the use of phase-locked-loop technology. one of the problems of using phase-locked-loop (pll) technology for clock recovery is that it relies on transi- tions in the line signal, in order to maintain lock with the incoming ds3 data-stream. therefore, these clock recovery scheme, are vulnerable to the occur- rence of a long stream of consecutive zeros (e.g., no transitions in the line). this scenario can cause the pll to lose lock with the incoming ds3 data, thereby causing the clock and data recovery process of the receiver to fail. therefore, some approach is needed to insure that such a long string of consecutive zeros can never happen. one such technique is b3zs (or bipolar 3 zero substitution) encoding. in general the b3zs line code behaves just like ami with the exception of the case when a long string of consecutive zeros occurs on the line. any 3 consecu- tive zeros will be replaced with either a 00v or a b0v where b refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the alternating polarity scheme of the ami coding rule). and v refers to a bi- polar violation pulse (e.g., a pulse with a polarity that violates the alternating polarity scheme of ami.) the decision between inserting an 00v or a b0v is made to insure that an odd number of bipolar (b) pulses ex- ist between any two bipolar violation (v) pulses. the receive ds3 framer, when operating with the b3zs line code is responsible for decoding the b3zs-en- coded data back into a unipolar (binary-format). for instance, if the receive ds3 framer detects a 00v or a b0v pattern in the incoming pattern, the receive ds3 framer will replace it with three consecutive ze- ros. figure 77 presents a timing diagram that illus- trates examples of b3zs decoding. f igure 76. i llustration of ami l ine c ode data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 rxpos rxneg line signal ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 194 4.3.1.2.3 line code violations the receive ds3 liu interface block will also check the incoming ds3 data stream for line code viola- tions. for example, when the receive ds3 liu inter- face block detects a valid bipolar violation (e.g., in b3zs line code), it will substitute three zeros into the binary data stream. however, if the bipolar violation is invalid, then an lcv (line code violation) is flagged and the pmon lcv event count register (address = 0x50 and 0x51) will also be incremented. additionally, the lcv-one second accumulation reg- isters (address = 0x6e and 0x6f) will be increment- ed. for example: if the incoming ds3 data is b3zs encoded, the receive ds3 liu interface block will al- so increment the lcv one second accumulation register if three (or more) consecutive zeros are re- ceived. 4.3.1.2.4 rxlineclk clock edge selection the incoming unipolar or bipolar data, applied to the rxpos and the rxneg input pins are clocked into the receive ds3 liu interface block via the rxli- neclk signal. the framer ic allows the user to spec- ify which edge (e.g, rising or falling) of the rxlineclk signal will sample and latch the signal at the rxpos and rxneg input signals into the framer ic. this feature was included in the XRT72L50 design in order to insure that the user can always meet the rxpos and rxneg to rxlineclk set-up and hold time re- quirements. the user can make this selection by writing the appropriate data to bit 1 of the i/o control register, as depicted below. table 36 depicts the relationship between the value of this bit-field to the sampling clock edge of rxlineclk. f igure 77. i llustration of two examples of b3zs d ecoding data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 rxpos rxneg 0 0 v line signal b 0 v ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 101000 00 t able 36: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r egister , and the sampling edge of the r x l ine c lk signal r x clki nv (b it 1) r esult 0 rising edge: rxpos and rxneg are sampled at the rising edge of rxlineclk. see figure 78 for timing relationship between rxlineclk, rxpos, and rxneg. 1 falling edge: rxpos and rxneg are sampled at the falling edge of rxlineclk. see figure 79 for timing relationship between rxlineclk, rxpos, and rxneg. xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 195 figure 78 and figure 79 present the waveform and timing relationships between rxlineclk, rxpos and rxneg for each of these configurations. 4.3.2 the receive ds3 framer block the receive ds3 framer block accepts decoded ds3 data from the receive ds3 liu interface block, and routes data to the following destinations. ? the receive payload data output interface block ? the receive overhead data output interface block. ? the receive ds3 hdlc controller block figure 80 presents a simple illustration of the receive ds3 framer block along with the associated paths to the other functional blocks within the framer chip. f igure 78. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the rising edge of r x l ine c lk rxlineclk rxpos rxneg t38 t39 t42 f igure 79. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the falling edge of r x l ine c lk rxlineclk rxpos rxneg t40 t41 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 196 once the b3zs (or ami) encoded data has been de- coded into a binary data-stream, the receive ds3 framer block will use portions of this data-stream in order to synchronize itself to the remote terminal equipment. at any given time, the receive ds3 framer block will be operating in one of two modes. ? the frame acquisition mode: in this mode, the receive ds3 framer block is trying to acquire syn- chronization with the incoming ds3 frames, or ? the frame maintenance mode: in this mode, the receive ds3 framer block is trying to maintain frame synchronization with the incoming ds3 frames. figure 81 presents a state machine diagram that de- picts the receive ds3 framer block's ds3 frame ac- quisition/maintenance algorithm. f igure 80. a s imple i llustration of the r eceive ds3 f ramer b lock and the a ssociated p aths to the o ther f unctional b locks receive ds3 framer block receive ds3 framer block to receive ds3 hdlc buffer receive overhead data output interface receive payload data output interface from receive ds3 liu interface block xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 197 4.3.2.1 frame acquisition mode operation the receive ds3 framer block will be performing frame acquisition operation while it is operating in any of the following states (per the ds3 frame acqui- sition/maintenance algorithm state machine diagram, as depicted in figure 81.) ? the f-bit search state ? the m-bit search state ? the p-bit check state (optional) once the receive ds3 framer block enters the in- frame state (per figure 81), then it will begin frame maintenance operation. when the receive ds3 framer block is in the frame- acquisition mode, it will begin to look for valid ds3 frames by first searching for the f-bits in the incoming ds3 data stream. at this initial point the receive ds3 framer block will be operating in the f-bit search state within the ds3 frame acquisition/maintenance algorithm state machine diagram (see figure 81). recall from the discussion in section 4.1, that each ds3 f-frame consists of four (4) f-bits that occur in a repeating 1001 pattern. the receive ds3 framer block will attempt to locate this f-bit pattern by per- forming five (5) different searches in parallel. the f- bit search has been declared successful if at least 10 consecutive f-bits are detected. after the f-bit match has been declared, the receive ds3 framer block will then transition into the m-bit search state within the ds3 frame acquisition/maintenance algorithm (per figure 81). when the receive ds3 framer block reaches this state, it will begin searching for valid m- bits. recall from the discussion in section 3.1 that each ds3 m-frame consists of three (3) m-bits that occur in a repeating 010 pattern. the m-bit search is declared successful if three consecutive m-frames (or 21 f-frames) are detected correctly. once this occurs an m-frame lock is declared, and the receive ds3 framer block will then transition to the in-frame state. at this point, the receive ds3 framer block will de- f igure 81. t he s tate m achine d iagram for the r eceive ds3 f ramer block ' s f rame a cquisition /m ain - tenance a lgorithm f-bit search m-bit search f-bit synch achieved in-frame rxoof pin is negated. 10 consecutive f-bits correctly received parity check (only if framing on parity is selected) m-bits correctly detected for 3 consecutive m-frames (framing on parity is selected) m-bits correctly detected for 3 consecutive m-frames (framing on parity is not selected) oof criteria based upon values for f-sync algo and m-sync algo valid parity parity error in 2 out of 5 frames ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 198 clare itself in the in-frame condition, and will begin frame maintenance operations. the receive ds3 framer block will then indicate that it has transitioned from the oof condition into the in-frame condition by doing the following. ? generate a change in oof condition interrupt to the local p. ? negate the rxoof output pin (e.g., toggle it "low"). ? negate the rxoof bit-field (bit 4) within the receive ds3 configuration and status register. the user can configure the receive ds3 framer to operate such that 'valid parity' (p-bits) must also be detected before the receive ds3 framer can declare itself in frame. the user can set this configuration by writing the appropriate data to the rx ds3 configura- tion and status register, as depicted below. table 37 relates the contents of this bit field to the framing acquisition criteria. once the receive ds3 framer block is operating in the in-frame condition, normal data recovery and processing of the ds3 data stream begins. the max- imum average reframing time is less than 1.5 ms. 4.3.2.2 frame maintenance mode operation when the receive ds3 framer block is operating in the in-frame state (per figure 81), it will then begin to perform frame maintenance operations, where it will continue to verify that the f- and m-bits are present, at their proper locations. while the receive ds3 framer block is operating in the frame maintenance mode, it will declare an out-of-frame (oof) condition if 3 or 6 f-bits (depending upon user selection) out of 16 consecutive f-bits are in error. the user makes this selection for the oof declaration criteria by writ- ing the appropriate value to bit 1 (f-sync algo) of the rx ds3 configuration and status register, as depict- ed below. table 38 relates the contents of this bit-field to the oof declaration criteria rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo ro ro ro ro r/w r/w r/w r/w xxxxx xxx t able 37: t he r elationship between the contents of b it 2 (f raming on p arity ) within the r x ds3 c onfiguration and s tatus r egister , and the resulting f raming a cquisition c riteria f raming on p arity (b it 2) f raming a cquisition c riteria 0 the in-frame is declared after f-bit synchronization (10 f-bit matches) followed by m-bit synchronization (m- bit matches for 3 ds3 m-frames) 1 the in-frame condition is declared after f-bit synchronization, followed by m-bit synchronization, with valid parity over the frames. also, the occurrence of parity errors in 2 or more out of 5 frames starts a frame search rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo ro ro ro ro r/w r/w r/w r/w xxxxxx xx xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 199 n ote : once the receive ds3 framer block has declared an oof condition, it will transition back to the f-bit search state within the ds3 frame acquisition/maintenance algo- rithm (per figure 81). in addition to selecting an oof declaration criteria for the f-bits, the user has the following options for configuring the oof declaration criteria based upon m-bits. 1. m-bit errors do not cause a oof declaration, or 2. oof will be declared if 3 out of 4 consecutive m- bits are in error. the user will select between these two options by writing the appropriate value to bit 0 (m-sync algo) within the receive ds3 configuration and status register, as depicted below. table 39 relates the contents of this bit field to the m- bit error criteria for declaration of oof. the framing on parity criteria for oof declara- tion finally, the framer ic offers the framing on parity op- tion, which also effects the oof declaration criteria. as was mentioned earlier, the framer ic allows the user to configure the receive ds3 framer block to detect 'valid-parity' before declaring itself in-frame. this same selection also configures the receive ds3 framer block to also declare an oof condition if a p- bit error is detected in 2 of the last 5 m-frames. whenever the receive ds3 framer block declares oof after being in the in-frame state the following will happen. ? the receive ds3 framer will assert the rxoof output pin (e.g., toggles it "high"). ? bit 4 (rxoof) within the rx ds3 configuration and status register will be set to "1" as depicted below. rx ds3 configuration and status register, (address = 0x10) t able 38: t he r elationship between the contents of b it 1 (f-s ync a lgo ) within the r x ds3 c onfiguration and s tatus r egister , and the resulting f- bit oof d eclaration criteria used by the r eceive ds3 f ramer block f-s ync a lgo (b it 1) oof d eclaration c riteria 0 oof is declared when 6 out of 16 consecutive f-bits are in error. 1 oof is declared when 3 out of 16 consecutive f-bits are in error. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo ro ro ro ro r/w r/w r/w r/w xxxxxxx x t able 39: t he r elationship between the contents of b it 0 (m-s ync a lgo ) within the r x ds3 c onfiguration and s tatus r egister , and the resulting m-b it oof d eclaration c riteria used by the r eceive ds3 f ramer block ms ync a lgo oof d eclaration c riteria 0 m-bit errors do not result in the declaration of oof 1 oof is declared when 3 out of 4 m-bits are in error. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 200 ? the receive ds3 framer block will also issue a change in oof status interrupt request, anytime there is a change in the oof status. 4.3.2.3 forcing a reframe via software com- mand the framer ic permits the user to force a reframe procedure of the receive ds3 framer block via soft- ware command. if the user writes a "1" into bit 0 the i/o control register, as depicted below, then the re- ceive ds3 framer will be forced into the frame acqui- sition mode, (or more specifically, in the f-bit search state per figure 81). afterwards, the receive ds3 framer block will begin its search for valid f-bits. the framer ic will also respond to this command by as- serting the rxoof output pin, and generating a change in oof status interrupt. 4.3.2.4 performance monitoring of the receive ds3 framer block the user can monitor the number of framing bit errors (m and f bits) that have been detected by the re- ceive ds3 framer block. this is accomplished by pe- riodically reading the pmon framing bit error count registers (address = 0x52 and 0x53), as depicted below. when the p/c reads these registers, it will read in the number of framing bit errors that have been de- tected since the last read of these two registers. these registers are reset upon read. 4.3.2.5 ds3 receive alarms the receive ds3 framer block is capable of detect- ing any of the following alarm conditions. ? los (loss of signal) ? ais (alarm indication signal) ? the idle pattern. ? ferf (far-end receive failure) of yellow alarm condition. ? febe (far-end-block error) ? change in aic state the methods by which the receive ds3 framer block uses to detect and declare each of these alarm condi- tions are described below. 4.3.2.5.1 the loss of signal (los) alarm the receive ds3 framer block will declare a loss of signal (los) state when it detects 180 consecutive r/o r/o r/o r/o r/w r/w r/w r/w xxx xxxxx rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 i/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010000 0 pmon framing bit error event count register - msb (address = 0x52) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 f-bit error count - high byte ro ro ro ro ro ro ro ro 10100000 pmon framing bit error event count register - lsb (address = 0x53) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 f-bit error count - low byte ro ro ro ro ro ro ro ro 00000000 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 201 incoming 0s via the rxpos and rxneg input pins or if the rlos input pin (from the xrt7300 ds3 liu or the xrt7295 line receiver ic) is asserted (e.g., driv- en "high"). the receive ds3 framer block will indi- cate the occurrence of an los condition by: 1. asserting the rxlos output pin (e.g., toggles it "high"). 2. setting bit 6 (rxlos) within the rx ds3 configu- ration and status register to 1, as depicted below. 3. the receive ds3 framer block will generate a change in los status interrupt request. n ote : the receive ds3 framer will also declare an oof condition and perform all of the notification procedures as described in section 3.3.2.2. 4. force the on-chip transmit section to transmit a ferf (far-end receive failure) indicator back out to the remote terminal. the receive ds3 framer block will clear the los condition when at least 60 out of 180 consecutive re- ceived bits are 1. n ote : the receive ds3 framer block will also generate the change in los condition interrupt, when it clears the los condition. the framer chip allows the user to modify the los declaration criteria such that an los condition is de- clared only if the rlos input pin (from the xrt7300 ds3/e3/sts-1 liu ic) is asserted. in this case, the internally-generated los criteria of 180 consecutive 0s will be disabled. the user can accomplish this by writing a "1" to bit 3 (int los disable) of the rx ds3 configuration and status register, as depicted below. n ote : for more information on the rlos input pin, please see section 2.1. 4.3.2.5.2 the alarm indication signal (ais) the receive ds3 framer block will identify and de- clare an ais condition if it detects all of the following conditions in the incoming ds3 data stream: ? valid m-bits, f-bits and p-bits ? all c-bits are zeros. ? x-bits are set to 1 ? the payload portion of the ds3 frame exhibits a repeating 1010... pattern. the receive ds3 framer block contains, within its circuitry, an up/down counter that supports the as- sertion and negation of the ais condition. this counter begins with the value of 0x00 upon power up or reset. the counter is then incremented anytime the receive ds3 framer block detects an ais type m-frame. this counter is then decremented, or kept at zero value, when the receive ds3 framer block detects a non-ais type m-frame. the receive ds3 framer block will declare an ais condition if this counter reaches the value of 63 m-frames or greater. explained another way, the ais condition is declared if the number of ais-type m-frames is detected, such that it meets the following conditions: nais - nvalid > 63 where: nais = the number of m-frames containing the ais pattern. nvalid = the number of m-frames not containing the ais pattern if at anytime, the contents of this up/down counter exceeds 63 m-frames, then the receive ds3 framer block will: 1. assert the rxais output pin by toggling it "high". 2. set bit 7 (rxais) within the rx ds3 configuration and status register, to "1" as depicted below. rx ds3 configuration and status register, (address = 0x10) b it 7 b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo r/o r/o r/o r/o r/w r/w r/w r/w 0 101xxxx rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo ro ro ro ro r/w r/w r/w r/w xxxx 1xxx ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 202 3. generate a change in ais status interrupt request to the p/c. 4. force the transmit section to transmit a ferf indication back to the remote terminal. the receive ds3 framer block will clear the ais con- dition when the following expression is true. nais - nvalid < 0. in other words, once the receive ds3 framer block has detected a sufficient number of normal (or non- ais) m-frames, such that this up/down counter reaches zero, then the receive ds3 framer block will clear the ais condition indicators. the receive ds3 framer block will inform the c/p of this negation of the ais status by generating a change in ais status interrupt. 4.3.2.5.3 the idle (condition) alarm the receive ds3 framer block will identify and de- clare an idle condition if it receives a sufficient num- ber of m-frames that meets all of the following condi- tions. ? valid m-bits, f-bits, and p-bits ? the 3 cp-bits (in f-frame #3) are zeros. ? the x-bits are set to 1 ? the payload portion of the ds3 frame exhibits a repeating 1100... pattern. the receive ds3 framer block circuitry includes an up/down counter that is used to track the number of m-frames that have been identified as exhibiting the idle condition by the receive ds3 framer block. the contents of this counter are set to zero upon reset or power up. this counter is then incremented whenev- er the receive ds3 framer block detects an idle-type m-frame. the counter is decremented, or kept at ze- ro if a non-idle m-frame is detected. if the receive ds3 framer block detects a sufficient number of idle- type m-frames, such that the counter reaches the number 63, then the receive ds3 framer block will declare the idle condition. explained another way, the receive ds3 framer block will declare an idle condition if the number of idle-pattern m-frames is detected such that it meets the following conditions. nidle - nvalid > 63, where: nidle = the number of m-frames containing the idle pattern nvalid = the number of m-frames not exhibit the idle pattern anytime the contents of this up/down counter reach- es the number 63, then the receive ds3 framer block will: 1. set bit 5 (rxidle) within the rx ds3 configuration and status register, to "1" as depicted below. rx ds3 configuration and status regis- ter, (address = 0x10) 2. generate a change in idle status interrupt request to the local p/c. the receive ds3 framer block will clear the idle condition if it has detected a sufficient number of non-idle m-frames, such that this up/down counter reaches the value 0. 4.3.2.5.4 the detection of (ferf) or yellow alarm condition the receive ds3 framer block will identify and de- clare a yellow alarm condition or a far-end receive failure (ferf) condition, if it starts to receive ds3 frames with both of its x-bits set to 0. when the receive ds3 framer block detects a ferf condition in the incoming ds3 frames, then it will then do the following. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo 1xxxxxxx rx ds3 configuration and status register, (address = 0x10) b it 7b it 6 b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof int los disable framing on parity f-sync algo m-sync algo r/o r/o r/o r/o r/w r/w r/w r/w xx 1xxxxx xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 203 1. it will assert the rxferf (bit-field 4) within the rx ds3 status register, as depicted below. this bit-field will remain asserted for the duration that the yellow alarm condition exists. 2. the receive ds3 framer block will also generate a change in ferf status interrupt to the p/c. consequently, the receive ds3 framer block will also assert the ferf interrupt status bit, within the rx ds3 interrupt status register, as depicted below. the receive ds3 framer block will clear the ferf condition, when it starts to receive receive ds3 frames that have its x bits set to 1. n ote : the ferf indicator is frequently referred to as the yellow alarm. 4.3.2.5.5 the detection of the febe events as described in section 3.2.4.2.1.9, a given terminal equipment will set the three febe (far-end block er- ror) bit-fields to the value [1, 1, 1] (e.g., all of the febe bits are set to 1) within the outbound ds3 frames if, all of the following conditions are true about the incoming ds3 line signal. ? the receive circuitry (within the terminal equip- ment) detects no p-bit errors. ? the receive circuitry (within the terminal equip- ment) detects no cp-bit errors. if the receive section of the terminal equipment de- tects any p or cp bit errors, then the transmit section of the terminal equipment will set the three febe bits (within the outbound ds3 data stream) to a value other than [1, 1, 1]. how does the receive ds3 framer block (within the XRT72L50) respond when it receives a ds3 frame with all three (3) of its febe bit-fields set to 1? as mentioned above, the terminal equipment will transmit ds3 frames, with the febe bits set to [1, 1, 1], during un-erred conditions. hence, if the receive ds3 framer block (within the XRT72L50 framer ic) receives ds3 frames with the febe bits set to [1, 1, 1] it will interpret this event as an un-erred event, and will continue normal operation. however, if the receive ds3 framer block receives a ds3 frame with the febe bits set to a value other than [1, 1, 1], then it will increment the pmon febe event count registers (which are located at address locations 0x58 and 0x59 within the framer address space). 4.3.2.5.6 detection of change in the aic state section 3.1 indicates that the aic (application identi- fication channel) bit-field is the third overhead bit, within f-frame # 1. this particular bit-field is set to 1 for the c-bit parity framing format, and is set to 0 for the m13 framing format. hence, a given terminal equipment receiving a ds3 data stream can identify the framing format of this ds3 data stream, by reading the value fo the aic bit- field. the receive ds3 framer block permits the us- ers microcontroller/microprocessor to determine the state of the aic bit-field (within the incoming ds3 da- ta stream) by writing the value of the aic bit-field, within the most recently received ds3 frame, into bit 3 (rxaic) within the rx ds3 status register (address = 0x11), as illustrated below. rx ds3 status register (address = 0x11) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 not used rx ferf rxaic rxfebe [2] rxfebe [1] rxfebe [0] ro ro ro ro ro ro ro ro 000 1xxxx rx ds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 cp bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf inter- rupt status aic interrupt status oof interrupt status p-bit interrupt status ro rur rur rur rurrurrurrur 0xxx 1xxx ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 204 the receive ds3 framer block will also generate an interrupt if it detects a change of state in the aic bit- field (within the incoming ds3 data stream). if this occurs, then the receive ds3 framer block will set bit 2 (aic interrupt status) within the rx ds3 inter- rupt stauts register (address = 0x13) to 1 as illus- trated below.r 4.3.2.6 performance monitoring of the ds3 transport medium the ds3 frame consists of some overhead bits that are used to support performance monitoring of the ds3 transmission link. these bits are the p-bits and the cp-bits. 4.3.2.6.1 p-bit checking/options the remote transmit ds3 framer will compute the even parity of the payload portion of an outbound ds3 frame and will place the resulting parity bit value in the 2 p-bit-fields within the very next outbound ds3 frame. the value of these two bits fields is expected to be the identical. the receive ds3 framer block, while receiving each of these ds3 frames (from the remote transmit ds3 framer), will compute the even-parity of the payload portion of the frame. the receive ds3 framer block will then compare this locally computed parity value to that of the p-bit fields within the very next ds3 frame. if the receive ds3 framer block detects a parity error, then two things will happen: 1. the receive ds3 framer block will inform the p/ c of this occurrence by generating a detection of p-bit error interrupt, 2. the receive ds3 framer block will alter the value of the febe bits, (to a pattern other than 111) that the near-end transmit ds3 framer will be transmitting back to the remote terminal. 3. the XRT72L50 framer ic will increment the pmon parity error event count registers (address = 0x54 and 0x55) for each detected parity error, in the incoming ds3 data stream. the bit-format of these two registers follows. rxds3 status register (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxferf rxaic rxfebe[2:0] ro ro ro ro ro ro ro ro 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00000100 pmon parity error event count register - msb (address = 0x54) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - high byte ro ro ro ro ro ro ro ro 00000000 pmon parity error event count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - "low" byte ro ro ro ro ro ro ro ro xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 205 when the p reads these registers, it will read in the number of parity-bit errors that have been detected by the receive ds3 framer block, since the last time these registers were read. these registers are reset upon read. n ote : when the framing with parity option is selected, the receive ds3 framer block will declared an oof condition if p-bit errors were detected in two out of 5 consecutive ds3 m-frames. 3.3.2.6.2 cp-bit checking/options cp-bits are very similar to p-bits except for the follow- ing. 1. cp-bits are used to permit performance monitor- ing over an entire ds3 path (e.g., from the source terminal) through any number of mid-network ter- minals to the sink terminal). 2. p-bits are used to permit performance monitoring of a ds3 data stream, as it is transmitted from one terminal to an adjacent terminal. how cp-bits are processed the following section describes how the cp-bits are processed at three locations. ? the source terminal equipment ? the mid-network terminal equipment ? the sink terminal equipment figure_62 presents a simple illustration of the loca- tions of these three types of terminal equipment, within the wide-area network. n ote : the use of the terms source and sink terminal equipment are used to simplify this discussion of cp-bit processing. in reality, the source terminal equipment (in figure_62) will also function as the sink terminal equip- ment (for ds3 traffic traveling in the opposite direction). likewise, the sink terminal equipment (in figure_62) will also function as the source terminal equipment. processing at the source terminal equipment the source terminal equipment (located at one edge of the wide-area network) will typically receive its ds3 payload data from some customer premise equip- ment (cpe). as the source terminal equipment re- ceives this data from the cpe, it will compute the even-parity value over all bits within a given outbound ds3 frame. the terminal equipment will then insert this even parity value into both of the p-bit fields and 00000000 pmon parity error event count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 f igure 82. a s imple i llustration of the l ocations of the s ource , m id -n etwork and s ink t erminal e quipment ( for cp-b it p rocessing ) source terminal equipment source terminal equipment sink terminal equipment sink terminal equipment mid-network terminal equipment mid-network terminal equipment the wide area network customer premises equipment customer premises equipment customer premises equipment customer premises equipment ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 206 both of the cp-bits fields, within the very next out- bound ds3 frame. hence, both the p-bit values and cp-bit values will originate at the source terminal equipment. processing at the mid-network terminal equip- ment the mid-network terminal equipment has the task of doing the following. ? receiving a ds3 data stream, via the receive wan interface line card. ? transmitting this same ds3 data stream (out to another remote terminal equipment) via the trans- mit wan interface line card. figure 83 presents an illustration of the basic archi- tecture of the mid-network terminal equipment. operation of the receive wan interface line card the receive wan interface line card receives a ds3 data stream from some remote terminal equipment. as the receive wan interface card does this, it will also do the following: 1. compute and verify the p-bits of each inbound ds3 frame. 2. compute and verify the cp-bits of each inbound ds3 frame. 3. output both the payload and overhead bits to the system back-plane. operation of the transmit wan interface line card the transmit wan interface line card receives the outbound ds3 data stream from the system back- plane. as the transmit wan interface line card re- ceives this data it will also do the following. 1. extract out the cp-bit values, from the receive wan interface line card (via the system back- plane) and insert these values into the cp-bit fields, within the outbound ds3 data stream, via the transmit overhead data input interface block of the XRT72L50 framer ic. 2. compute the even-parity over all bits, within a given outbound ds3 frame, and insert this value into the p bits within the very next outbound ds3 frame. 3. transmit this resulting ds3 data stream to the remote terminal equipment. processing at the sink terminal f igure 83. i llustration of the p resumed c onfiguration of the m id -n etwork t erminal e quipment the receiving ds3 line card the receiving ds3 line card the transmitting ds3 line card the transmitting ds3 line card system back-plane ds3 traffic from source terminal equipment ds3 traffic to sink terminal equipment the mid-network terminal equipment xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 207 the sink terminal equipment (located at the opposite edge of the wide-area-network, from the source ter- minal equipment) will receive and terminate this ds3 data stream. as the sink terminal equipment re- ceives this ds3 data stream it will also do the follow- ing. 1. compute and verify the p-bits within each inbound ds3 frame. 2. compute and verify the cp bits within each inbound ds3 frame. 4.3.3 the receive hdlc controller block the receive ds3 hdlc controller block can be used to receive either bit-oriented signaling (bos) or mes- sage-oriented signaling (mos) type data link mes- sages. the receive ds3 hdlc controller block can also be configured to receive both types of message from the remote terminal equipment. both bos and mos types of hdlc message pro- cessing are discussed in detail below. 4.3.3.1 bit-oriented signaling (or feac) pro- cessing via the receive ds3 hdlc controller. the receive ds3 hdlc controller block consists of two major sub-blocks ? the receive feac processor ? the lapd receiver this section describes how to operate the receive feac processor. if the receive ds3 framer block is operating in the c- bit parity framing format, then the feac bit-field within the ds3 frame can be used to receive feac (far end alarm and control) messages (see figure 84). each feac code word is actually six bits in length. however, this six bit feac code word is encapsulated with 10 framing bits to form a 16 bit message of the form: where, [d5, d4, d3, d2, d1, d0] is the feac code word. the rightmost bit of the 16-bit data structure (e.g., a 1) will be received first. since each ds3 frame contains only 1 feac bit-field, 16 ds3 frames are required to transmit the 16 bit feac code mes- sage. the six bits, labeled d5 through d0 can rep- resent 64 distinct messages, of which 43 have been defined in the standards. the receive feac processor frames and validates the incoming feac data from the remote transmit feac processor via the received feac channel. ad- ditionally, the receive feac processor will write the received feac code words into an 8 bit rx-feac register. framing is performed by looking for two 0s spaced 6 bits apart preceded by 8 1s. the receive ds3 hdlc controller contains two registers that sup- port feac message reception. ? rx ds3 feac register (address = 0x16) ? rx ds3 feac interrupt enable/status register (address = 0x17) the receive feac processor generates an interrupt upon validation and removal of the incoming feac code words. operation of the receive ds3 feac processor the receive feac processor will validate or remove feac code words that it receives from the remote transmit feac processor. the feac code valida- tion and removal functions are described below. feac code validation when the remote terminal equipment wishes to send a feac message to the local receive feac proces- sor, it (the remote terminal equipment) will transmit this 16 bit message, repeatedly for a total of 10 times. the receive feac processor will frame to this in- coming feac code message, and will attempt to val- idate this message. once the receive feac proces- sor has received the same feac code word in at least 8 out of the last 10 received codes, it will vali- date this code word by writing this 6 bit code word in- to the receive ds3 feac register. the receive feac processor will then inform the c/p of this receive feac validation event by generating a rx feac valid interrupt and asserting the feac valid and the rxfeac valid interrupt status bits in the rx ds3 interrupt enable/status register, as depicted below. the bit format of the rx ds3 feac register is presented below. feac c ode w ord f raming 0 d5 d4 d3 d2 d1 d0011111111 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 208 the bit-format of the rx ds3 feac register is pre- sented below. it is important to note that the last vali- dated feac code word will be written into the shaded bit-fields below. the purpose of generating an interrupt to the p, up- on feac code word validation is to inform the local p that the framer has a newly received feac mes- sage that needs to be read. the local p would read- in this feac code word from the rx ds3 feac reg- ister (address = 0x16). feac code removal after the 10th transmission of a given feac code word, the remote terminal equipment may proceed to transmit a different feac code word. when the re- ceive feac processor detects this occurrence, it must remove the feac codeword that is presently residing in the rx ds3 feac register. the receive feac processor will remove the existing feac code word when it detects that 3 (or more) out of the last 10 received feac codes are different from the latest validated feac code word. the receive feac pro- cessor will inform the local p/c of this removal event by generating a rx feac removal interrupt, and asserting the rxfeac remove interrupt status bit in the rx ds3 interrupt enable/status register, as depicted below. additionally, the receive feac processor will also denote the removal event by setting the feac valid bit-field (bit 4), within the rx ds3 feac interrupt en- able/status register to 0, as depicted above. the description of bits 0 through 3 within this register, all support interrupt processing, and will therefore be presented in section 3.3.6. figure 84 presents a flow diagram depicting how the receive feac processor functions. rx ds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1 b it 0 not used not used not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur xxx 1x01 1 rx ds3 feac register (address = 0x16) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1b it 0 not used rxfeac [5] rxfeac [4] rxfeac [3] rxfeac [2] rxfeac [1] rxfeac [0] not used ro ro ro ro ro ro ro ro 0 d5 d4 d3 d2 d1 d0 0 rx ds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5 b it 4b it 3 b it 2b it 1b it 0 not used not used not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur xxx 01 1x0 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 209 n otes : 1. the white (e.g., unshaded) boxes reflect tasks that the users system must perform in order to config- ure the receive feac processor to receive feac messages. 2. a brief description of the steps that must exist within the feac validation and feac removal interrupt service routines exists in section 3.6 4.3.3.2 the message oriented signaling (e.g., lap-d) processing via the receive ds3 hdlc controller block the lapd receiver (within the receive ds3 hdlc controller block) allows the user to receive pmdl messages from the remote terminal equipment, via the inbound ds3 frames. in this case, the inbound message bits will be carried by the 3 dl bit-fields of f-frame 5, within each ds3 m-frame. the remote lapd transmitter will transmit a lapd message to the near-end receiver via these three bits within each ds3 frame. the lapd receiver will receive and store the information portion of the received lapd frame into the receive lapd message buffer, which is located at addresses: 0xde through 0x135 within the on-chip ram. the lapd receiver has the following responsibilities. ? framing to the incoming lapd messages ? filtering out stuffed 0s (within the information pay- load) ? storing the frame message into the receive lapd message buffer ? perform frame check sequence (fcs) verification ? provide status indicators for end of message (eom) flag sequence byte detected abort sequence detected message type c/r type the occurrence of fcs errors f igure 84. f low d iagram depicting how the r eceive feac p rocessor f unctions start start enable the feac removal and validation interrupts . this is accomplished by writing xxxx 1010 into the rxds3 feac interrupt/status register (address = 0x17) enable the feac removal and validation interrupts . this is accomplished by writing xxxx 1010 into the rxds3 feac interrupt/status register (address = 0x17) receive feac processor begins reading in the feac bit-fields (of incoming ds3 frames) the receive feac processor checks for the feac framing alignment pattern of 01111110. receive feac processor begins reading in the feac bit-fields (of incoming ds3 frames) the receive feac processor checks for the feac framing alignment pattern of 01111110. is the feac framing alignmentpattern present in the feac channel ? is the feac framing alignmentpattern present in the feac channel ? read in the 6-bit feac code word the 6-bit feac code word immediately follows the feac framing alignment pattern. read in the 6-bit feac code word the 6-bit feac code word immediately follows the feac framing alignment pattern. has this same feac code word been received in 8 out of the last 10 feac message receptions? has this same feac code word been received in 8 out of the last 10 feac message receptions? has a feac code word (other than the last validated code word) been received in 3 out of the last 10 feac message receptions? has a feac code word (other than the last validated code word) been received in 3 out of the last 10 feac message receptions? generate feac validation interrupt generate feac validation interrupt invoke feac validation interruptservice routine . invoke feac validation interruptservice routine . generate feac removal interrupt generate feac removal interrupt invoke feac removal interruptservice routine . invoke feac removal interruptservice routine . 1 1 1 1 1 1 no yes yes no no yes ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 210 the lapd receiver's actions are facilitated via the fol- lowing two registers. ? rx ds3 lapd control register ? rx ds3 lapd status register operation of the lapd receiver the lapd receiver, once enabled, will begin search- ing for the boundaries of the incoming lapd mes- sage. the lapd message frame boundaries are de- lineated via the flag sequence octets (0x7e), as de- picted in figure 85. where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the 16 bit fcs is calculated using crc-16, x16 + x12 + x5 + 1 the microprocessor/microcontroller (at the remote terminal), while assembling the lapd message frame, will insert an additional byte at the beginning of the information (payload) field. this first byte of the information field indicates the type and size of the message being transferred. the value of this infor- mation field and the corresponding message type/ size follow: cl path identification = 0x38 (76 bytes) idle signal identification = 0x34 (76 bytes) test signal identification = 0x32 (76 bytes) itu-t path identification = 0x3f (82 bytes) the lapd receiver must be enabled before it can begin receiving any lapd messages. the lapd re- ceiver can be enabled by writing a "1" into bit 2 (rx- lapd enable) within the rx ds3 lapd control reg- ister. the bit format of this register is depicted below. once the lapd receiver has been enabled, it will be- gin searching for the flag sequence octets (0x7e), in the dl bit-fields, within the incoming ds3 frames. when the lapd receiver finds the flag sequence byte, it will assert the flag present bit (bit 0) within the rx ds3 lapd status register, as depicted below. the receipt of the flag sequence octet can mean one of two things. f igure 85. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) rx ds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 not used not used not used not used not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000 1xx rx ds3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 not used rxabort rxlapd type[1, 0] rxcr type rxfcs error end of message flag present xxxxx xx1 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 211 1. the flag sequence byte marks the beginning or end of an incoming lapd message. 2. the received flag sequence octet could be just one of many flag sequence octets that are trans- mitted via the ds3 transport medium, during idle periods between the transmission of lapd mes- sages. the lapd receiver will clear the flag present bit as soon as it has received an octet that is something other than the flag sequence octet. at this point, the lapd receiver should be receiving either octet #2 of the incoming lapd message, or an abort sequence (e.g., a string of seven or more consecutive 1s). if this next set of data is an abort sequence, then the lapd receiver will assert the rxabort bit (bit 6) with- in the rx ds3 lapd status register. however, if this next octet is octet #2 of an incoming lapd message, then the rx ds3 lapd status register will begin to present some additional status information on this in- coming message. each of these indicators is pre- sented below in sequential order. bit 3 - rxcr type - c/r (command/response) type this bit-field reflects the contents of the c/r bit-field within octet #2 of the lapd frame header. when this bit is "0" it means that this message is originating from a customer installation. when this bit is "1" it means that this message is originating from a net- work terminal. bit 4,5 - rxlapd type[1, 0] - lapd message type the combination of these two bit fields indicate the message type and the message size of the incoming lapd message frame. table 40 relates the values of bits 4 and 5 to the incoming lapd message type/ size. n ote : the message size pertains to the size of the infor- mation portion of the lapd message frame (as presented in figure 85). bit 3 - flag present the lapd receiver should receive another flag se- quence octet, which marks the end of the message. therefore, this bit field should be asserted once again. bit 1 - endofmessage - end of lapd message frame upon receipt of the closing flag sequence octet, this bit-field should be asserted. the assertion of this bit- field indicates that a lapd message frame has been completely received. additionally, if this newly re- ceived lapd message is different from the previous message, then the lapd receiver will inform the c/ p of the endofmessage event by generating an in- terrupt. bit 2 - rxfcserr - frame check sequence error indicator the lapd receiver will take the incoming lapd message and compute its own version of the frame check sequence (fcs) word. afterwards, the lapd receiver will compare its computed value with that it has received from the remote lapd transmitter. if these two values match, then the lapd receiver will presume that the lapd message has been properly received and the contents of the received lapd message (payload portion) will be retained at loca- tions 0xde through 0x135 in on-chip ram. the lapd receiver will indicate an error-free reception of the lapd message by keeping this bit field negated (bit 2 = 0). however, if these two fcs values do not match, then the received lapd message is corrupted and the user is advised not to process this erroneous information. the lapd receiver will indicate an erred receipt of this message by setting this bit-field to 1. n ote : the receive ds3 hdlc controller block will not generate an interrupt to the p due to the detection of an fcs error. therefore, the user is advised to validate each and every received lapd message by checking this bit- field prior to processing the lapd message. removal of stuff bits from the payload portion of the incoming lapd message while the lapd receiver is receiving a lapd mes- sage, it has the responsibility of removing all of the "0" stuff bits from the payload portion of the incoming lapd message frame. recall that the text in section 3.2.3.2 indicated that the lapd transmitter (at the re- mote terminal) will insert a "0" immediately following a string of 5 consecutive 1s within the payload portion t able 40: t he r elationship between r x lapdt ype [1:0] and the resulting lapd m essage type and size r x lapd t ype [1, 0] m essage t ype m essage s ize 00 test signal identification 76 bytes 01 idle signal identification 76 bytes 10 cl path identification 76 bytes 11 tu-t path identification 82 bytes ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 212 of the lapd message frame. the lapd transmitter performs this bit-stuffing procedure in order to prevent the user data from mimicking the flag sequence oc- tet (0x7e) or the abort sequence. therefore, in or- der to recover the user data to its original content (pri- or to the bit-stuffing), the lapd receiver will remove the "0" that immediately follows a string of 5 consecu- tive 1s. writing the incoming lapd message into the re- ceive lapd message buffer the lapd receiver will obtain the lapd message frame from the incoming ds3 data-stream. in addi- tion to processing the framing overhead octets, per- forming error checking (via fcs) and removing the stuffed 0s from the user payload data. the lapd re- ceiver will also write the payload portion of the lapd frame into the receive lapd message buffer at loca- tions 0xde through 0x135 in on-chip ram. therefore, the local p/c must read this location when it wishes to process this newly received lapd message. figure 86 presents a flow chart depicting how the lapd receiver works. n otes : 1. the white (e.g., unshaded) boxes reflect tasks that the users system must perform in order to config- ure the lapd receiver to receive lapd messages. 2. a brief description of the steps that must exist within the receive lapd interrupt service routine exists in section 3.3.6. 4.3.4 the receive overhead data output inter- face figure 87 presents a simple illustration of the receive overhead data output interface block within the XRT72L50. f igure 86. f low c hart depicting the f unctionality of the lapd r eceiver start start enable the lapd receiver this is done by writing the value 0xfc into the rxlapd control register (address = 0x18) lapd receiver begins reading in the dl bits from each inbound ds3 frame does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? flag sequence flag sequence abort sequence abort sequence lapd receiver is reading in a lapd message frame, containing a pmdl message. lapd receiver is reading in a lapd message frame, containing a pmdl message. does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? end of message (eom) end of message (eom) verify the fcs value report results in the rxlapd status register.. verify the fcs value report results in the rxlapd status register.. un-stuff contents of received message un-stuff contents of received message write received pmdl message into the receive lapd message buffer (addresses 0xde - 0x135) write received pmdl message into the receive lapd message buffer (addresses 0xde - 0x135) generate received lapd interrupt generate received lapd interrupt execute receive lapd interrupt service routine execute receive lapd interrupt service routine 1 1 1 1 no yes no yes yes no yes no xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 213 the ds3 frame consists of 4760 bits. of these bits, 4704 bits are payload bits and the remaining 56 bits are overhead bits. the XRT72L50 has been de- signed to handle and process both the payload type and overhead type bits for each ds3 frame. the receive payload data output interface block, within the receive section of the XRT72L50, has been designed to handle the payload bits. likewise, the receive overhead data output interface block has been designed to handle and process the over- head bits. the receive overhead data output interface block unconditionally outputs the contents of all overhead bits within the incoming ds3 data stream. the XRT72L50 does not offer the user a means to shut off this transmission of data. however, the receive overhead output interface block does provide the us- er with the appropriate output signals for external da- ta link layer equipment to sample and process these overhead bits, via the following two methods. ? method 1- using the rxohclk clock signal. ? method 2 - using the rxclk and rxohenable out- put signals. each of these methods are described below. 4.3.4.1 method 1 - using the rxohclk clock signal the receive overhead data output interface block consists of four (4) signals. of these four signals, the following three signals are to be used when sampling the ds3 overhead bits via method 1. ? rxoh ? rxohclk ? rxohframe each of these signals are listed and described below in table 41. f igure 87. a s imple i llustration of the r eceive o verhead o utput i nterface block receive overhead output interface block receive overhead output interface block from receive ds3 framer block rxohframe rxoh rxohclk rxohenable ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 214 interfacing the receive overhead data output in- terface block to the terminal equipment (method 1) figure 88 illustrates how one should interface the re- ceive overhead data output interface block to the terminal equipment when using method 1 to sample and process the overhead bits from the inbound ds3 data stream. method 1 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound ds3 data stream (via t able 41: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L50 will output the overhead bits, within the incoming ds3 frames, via this pin. the receive overhead data output interface block will output a given overhead bit, upon the falling edge of rxohclk. hence, the external data link equipment should sample the data, at this pin, upon the rising edge of rxohclk. the XRT72L50 will always output the ds3 overhead bits via this output pin. there are no external input pins or register bit settings available that will disable this output pin. rxohclk output receive overhead data output interface clock signal: the XRT72L50 will output the overhead bits (within the incoming ds3 frames), via the rxoh output pin, upon the falling edge of this clock signal. as a consequence, the user's data link equipment should use the rising edge of this clock sig- nal to sample the data on both the rxoh and rxohframe output pins. this clock signal is always active. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L50 will drive this output pin "high" (for one period of the rxohclk signal), when- ever the first overhead bit within a given ds3 frame is being driven onto the rxoh output pin. f igure 88. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 1). terminal equipment xrt72l5x ds3 framer ic rxohclk ds3_oh_clock_in rxoh rxohframe ds3_oh_in rx_start_of_frame xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 215 the receive overhead data output interface block) then it is expected to do the following: 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input signal) on the rising edge of the rxohclk (e.g., the ds3_oh_clock_in) signal. 2. keep track of the number of rising clock edges that have occurred in the rxohclk (e.g., the ds3_oh_clock_in) signal, since the last time the rxohframe signal was sampled "high". by doing this, the terminal equipment will be able to keep track of which overhead bit is being output via the rxoh output pin. based upon this infor- mation, the terminal equipment will be able to derive some meaning from these overhead bits. table 42 relates the number of rising clock edges (in the rxohclk signal, since the rxohframe signal was last sampled "high") to the ds3 overhead bit that is being output via the rxoh output pin. t able 42: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x ohf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the XRT72L50 0 (clock edge is coincident with rxohframe being detected "high") x 1f1 2aic 3f0 4na 5f0 6 feac 7f1 8x 9f1 10 udl 11 f0 12 udl 13 f0 14 udl 15 f1 16 p 17 f1 18 cp 19 f0 20 cp 21 f0 22 cp 23 f1 24 p 25 f1 26 febe 27 f0 28 febe 29 f0 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 216 figure 89 presents the typical behavior of the re- ceive overhead data output interface block, when method 1 is being used to sample the incoming ds3 overhead bits. 30 febe 31 f1 32 m0 33 f1 34 dl 35 f0 36 dl 37 f0 38 dl 39 f1 40 m1 41 f1 42 udl 43 fo 44 udl 45 fo 46 udl 47 f1 48 m0 49 f1 50 udl 51 f0 52 udl 53 f0 54 udl 55 f1 t able 42: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x ohf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the XRT72L50 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 217 method 2 - using rxoutclk and the rxohenable signals method 1 requires that the terminal equipment be able to handle an additional clock signal, rxohclk. however, there may be a situation in which the termi- nal equipment circuitry does not have the means to accommodate and process this extra clock signal, in order to use the receive overhead data output inter- face. hence, method 2 is available. method 2 in- volves the use of the following signals. ? rxoh ? rxoutclk ? rxohenable ? rxohframe each of these signals are listed and described below in table 43. f igure 89. i llustration of the signals that are output via the r eceive o verhead o utput i nterface ( for m ethod 1). rxohclk rxohframe rxoh x f1 aic f0 feac terminal equipment should sample the rxohframe and rxoh signals here. recommended sampling edges ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 218 interfacing the receive overhead data output in- terface block to the terminal equipment (method 2) figure 90 illustrates how one should interface the re- ceive overhead data output interface block to the terminal equipment, when using method 2 to sample and process the overhead bits from the inbound ds3 data stream. t able 43: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (m ethod 2) s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L50 will output the overhead bits, within the incoming ds3 frames, via this pin. the receive overhead output interface will pulse the rxohenable output pin (for one rxout- clk period) at approximately the middle of the rxoh bit period. the user is advised to design the terminal equipment to latch the contents of the rxoh output pin, whenever the rxohen- able output pin is sampled "high" on the falling edge of rxoutclk. rxohenable output receive overhead data output enable - output pin: the XRT72L50 will assert this output signal for one rxoutclk period when it is safe for the terminal equipment to sample the data on the rxoh output pin. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L50 will drive this output pin "high" (for one period of the rxoh signal), whenever the first overhead bit, within a given ds3 frame is being driven onto the rxoh output pin. rxoutclk output receive section output clock signal: this clock signal is derived from the rxlineclk signal (from the liu) for loop-timing applica- tions, and the txinclk signal (from a local oscillator) for local-timing applications. for ds3 applications, this clock signal will operate at 44.736mhz. the user is advised to design the terminal equipment to latch the contents of the rxoh pin, anytime the rxohenable output signal is sampled "high" on the falling edge of this clock sig- nal. xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 219 method 2 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound ds3 data stream (via the receive overhead data output interface), then it is expected to do the following. 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input) on the falling edge of the rxoutclk clock signal, whenever the rxo- henable output signal is also sampled "high". 2. keep track of the number of times that the rxo- henable signal has been sampled "high" since the last time the rxohframe was also sampled "high". by doing this, the terminal equipment will be able to keep track of which overhead bit is being output via the rxoh output pin. based upon this information, the terminal equipment will be able to derive some meaning from these overhead bits. 3. table 44 relates the number of rxohenable out- put pulses (that have occurred since both the rxohframe and the rxohenable pins were both sampled "high") to the ds3 overhead bit that is being output via the rxoh output pin. f igure 90. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 2). rxoh rxohenable rxoutclk rxohframe ds3_oh_in ds3_oh_enable_in ds3_clk_in rx_start_of_frame terminal equipment xrt72l5x ds3 framer ic ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 220 t able 44: t he r elationship between the n umber of r x ohe nable output pulses (( since r x ohf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the XRT72L50 0 (the rxohenable and rxohframe signals are both sampled "high") x 1f1 2aic 3f0 4na 5f0 6 feac 7f1 8x 9f1 10 udl 11 f0 12 udl 13 f0 14 udl 15 f1 16 p 17 f1 18 cp 19 f0 20 cp 21 f0 22 cp 23 f1 24 p 25 f1 26 febe 27 f0 28 febe 29 f0 30 febe 31 f1 32 m0 33 f1 34 dl 35 f0 36 dl 37 f0 38 dl xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 221 figure 91 presents the typical behavior of the re- ceive overhead data output interface block, when method 2 is being used to sample the incoming ds3 overhead bits. 39 f1 40 m1 41 f1 42 udl 43 fo 44 udl 45 fo 46 udl 47 f1 48 m0 49 f1 50 udl 51 f0 52 udl 53 f0 54 udl 55 f1 t able 44: t he r elationship between the n umber of r x ohe nable output pulses (( since r x ohf rame was last sampled "h igh ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 222 4.3.5 the receive payload data output inter- face figure 92 presents a simple illustration of the receive payload data output interface block. f igure 91. i llustration of the signals that are output via the r eceive o verhead d ata o utput i nter - face block ( for m ethod 2). rxoutclk rxohenable rxohframe rxoh f1 x f1 aic f0 recommended sampling edges xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 223 each of the output pins of the receive payload data output interface block are listed in table 45 and de- scribed below. the exact role that each of these out- put pins assume, for a variety of operating scenarios are described throughout this section. f igure 92. a s imple illustration of the r eceive p ayload d ata o utput i nterface block receive payload data output interface receive payload data output interface rxohind rxser rxnib[3:0] rxclk rxoutclk rxframe from receive ds3 framer block ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 224 t able 45: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i nterface block s ignal n ame t ype d escription rxser output receive serial payload data output pin: if the user opts to operate the XRT72L50 in the serial mode, then the chip will output the payload data, of the incoming ds3 frames, via this pin. the XRT72L50 will output this data upon the ris- ing edge of rxclk. the user is advised to design the terminal equipment such that it will sample this data on the falling edge of rxclk. this signal is only active if the nibint input pin is pulled "low". rxnib[3:0] output receive nibble-parallel payload data output pins: if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the chip will output the payload data, of the incoming ds3 frames, via these pins. the XRT72L50 will output data via these pins, upon the falling edge of the rxclk output pin. the user is advised to design the terminal equipment such that it will sample this data upon the rising edge of rxclk. these pins are only active if the nibint input pin is pulled "high". rxclk output receive payload data output clock pin: the exact behavior of this signal depends upon whether the XRT72L50 is operating in the serial or in the nibble-parallel-mode. serial mode operation in the serial mode, this signal is a 44.736mhz clock output signal. the receive payload data output interface will update the data via the rxser output pin, upon the rising edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the rxser pin, upon the falling edge of this clock signal. nibble-parallel mode operation in this nibble-parallel mode, the XRT72L50 will derive this clock signal, from the rxlineclk sig- nal. the XRT72L50 will pulse this clock 1176 times for each inbound ds3 frame. the receive payload data output interface will update the data, on the rxnib[3:0] output pins upon the falling edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the rxnib[3:0] output pins, upon the rising edge of this clock signal rxohind output receive overhead bit indicator output: this output pin will pulse "high" whenever the receive payload data output interface outputs an overhead bit via the rxser output pin. the purpose of this output pin is to alert the terminal equipment that the current bit, (which is now residing on the rxser output pin), is an overhead bit and should not be processed by the terminal equipment. the XRT72L50 will update this signal, upon the rising edge of the rxclk signal. the user is advised to design (or configure) the terminal equipment to sample this signal (along with the data on the rxser output pin) on the falling edge of the rxclk signal. for ds3 applications, this output pin is only active if the XRT72L50 is operating in the serial mode. this output pin will be "low" if the device is operating in the nibble-parallel mode. rxframe output receive start of frame output indicator: the exact behavior of this pin, depends upon whether the XRT72L50 has been configured to operate in the serial mode or the nibble-parallel mode. serial mode operation: the receive section of the XRT72L50 will pulse this output pin "high" (for one bit period) when the receive payload data output interface block is driving the very first bit of a given ds3 frame, onto the rxser output pin. nibble-parallel mode operation: the receive section of the XRT72L50 will pulse this output pin "high" (for one nibble period), when the receive payload data output interface is driving the very first nibble of a given ds3 frame, onto the rxnib[3:0] output pins. xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 225 operation of the receive payload data output in- terface block the receive payload data output interface permits the user to read out the payload data of inbound ds3 frames, via either of the following modes. ? serial mode ? nibble-parallel mode each of these modes are described in detail, below. 4.3.5.1 serial mode operation behavior of the XRT72L50 if the XRT72L50 has been configured to operate in the serial mode, then the XRT72L50 will behave as follows. payload data output the XRT72L50 will output the payload data, of the in- coming ds3 frames via the rxser output, upon the rising edge of rxclk. delineation of inbound ds3 frames the XRT72L50 will pulse the rxframe output pin "high" for one bit-period, coincident with it driving the first bit within a given ds3 frame, via the rxser out- put pin. interfacing the XRT72L50 to the receive terminal equipment figure 93 presents a simple illustration as how the user should interface the XRT72L50 to that terminal equipment which processes receive direction pay- load data. required operation of the terminal equipment the XRT72L50 will update the data on the rxser out- put pin, upon the rising edge of rxclk. however, be- cause the rising edge of rxclk to data delay is be- tween 14ns to 16ns, the terminal equipment should sample the data on the rxser output pin (or the ds3_data_in pin at the terminal equipment) upon the rising edge of rxclk. this will still permit the ter- minal equipment with a rxser to rxclk set-up time of approximately 6ns and a hold time of 14 to 16ns. as the terminal equipment samples rxser with each ris- ing edge of rxclk it should also be sampling the fol- lowing signals. ? rxframe ? rxohind the need for sampling rxframe the XRT72L50 will pulse the rxframe output pin "high" coincident with it driving the very first bit of a given ds3 frame onto the rxser output pin. if knowl- edge of the ds3 frame boundaries is important for the operation of the terminal equipment, then this is a very important signal for it to sample. the need for sampling rxohind the XRT72L50 will indicate that it is currently driving an overhead bit onto the rxser output pin, by pulsing the rxohind output pin "high". if the terminal equip- ment samples this signal "high", then it should know f igure 93. i llustration of the XRT72L50 ds3/e3 f ramer ic being interfaced to the r eceive t erminal e quipment (s erial m ode o peration ) terminal equipment (receive payload section) xrt72l5x ds3 framer ds3_data_in rx_ds3_clock_in rx_start_of_frame rxclk rxframe rxohins 44.736 mhz clock signal rxser rx_ds3_oh_ind rxlineclk 44.736 mhz clock source ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 226 that the bit, that it is currently sampling via the rxser pin is an overhead bit and should not be processed. the behavior of the signals between the receive payload data output interface block and the ter- minal equipment the behavior of the signals between the XRT72L50 and the terminal equipment for ds3 serial mode op- eration is illustrated in figure 94. 4.3.5.2 nibble-parallel mode operation behavior of the XRT72L50 if the XRT72L50 has been configured to operate in the nibble-parallel mode, then the XRT72L50 will be- have as follows. payload data output the XRT72L50 will output the payload data of the in- coming ds3 frames, via the rxnib[3:0] output pins, upon the falling edge of rxclk. n otes : 1. in this case, rxclk will function as the nibble clock signal between the XRT72L50 the terminal equip- ment. the XRT72L50 will pulse the rxclk output signal "high" 1176 times, for each inbound ds3 frame. 2. unlike serial mode operation, the duty cycle of rxclk, in nibble-parallel mode operation is approx- imately 25%. delineation of inbound ds3 frames the XRT72L50 will pulse the rxframe output pin "high" for one nibble-period coincident with it driving the very first nibble, within a given inbound ds3 frame, via the rxnib[3:0] output pins. interfacing the XRT72L50 the terminal equip- ment. figure 95 presents a simple illustration as how the user should interface the XRT72L50 to that terminal equipment which processes receive direction pay- load data. f igure 94. a n i llustration of the behavior of the signals between the r eceive p ayload d ata o utput i nterface block of the XRT72L50 and the t erminal e quipment (s erial m ode o peration ) terminal equipment signals ds3_clock_in ds3_data_in rx_start_of_frame ds3_overhead_ind xrt72l5x receive payload data i/f signals rxclk rxser rxframe rxoh_ind payload[4702] payload[4703] x-bit payload[0] payload[4702] payload[4703] x-bit payload[0] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: rxframe pulses high to denote ds3 frame boundary. note: rxoh_ind pulses high to denote overhead data (e.g., the x-bit). xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 227 required operation of the terminal equipment the XRT72L50 will update the data on the rxnib[3:0] line, upon the falling edge of rxclk. hence, the ter- minal equipment should sample the data on the rx- nib[3:0] output pins (or the ds3_data_in[3:0] input pins at the terminal equipment) upon the rising edge of rxclk. as the terminal equipment samples rxser with each rising edge of rxclk it should also be sam- pling the rxframe signal. the need for sampling rxframe the XRT72L50 will pulse the rxframe output pin "high" coincident with it driving the very first nibble of a given ds3 frame, onto the rxnib[3:0] output pins. if knowledge of the ds3 frame boundaries is impor- tant for the operation of the terminal equipment, then this is a very important signal for it to sample. n ote : for ds3/nibble-parallel mode operation, none of the overhead bits will be output via the rxnib[3:0] output pins. hence, the rxoh_ind output pin will be in-active in this mode. the behavior of the signals between the receive payload data output interface block and the ter- minal equipment the behavior of the signals between the XRT72L50 and the terminal equipment for ds3 nibble-mode op- eration is illustrated in figure 96. f igure 95. i llustration of the XRT72L50 ds3/e3 f ramer ic being interfaced to the r eceive s ection of the t erminal e quipment (n ibble -m ode o peration ) terminal equipment (receive payload section) xrt72l5x ds3 framer ds3_data_in[3:0] rx_ds3_clock_in rx_start_of_frame rxclk rxframe 11.184 mhz clock signal rxnib[3:0] rxlineclk 44.736 mhz clock source ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 228 4.3.6 receive section interrupt processing the receive section of the XRT72L50 can generate an interrupt to the microcontroller/microprocessor for the following reasons. ? change of state of receive los (loss of signal) condition ? change of state of receive oof (out of frame) condition ? change of state of receive ais (alarm indicator signal) condition ? change of state of receive idle condition. ? change of state of receive ferf (far-end receive failure) condition. ? change of state of aic (application identification channel) bit. ? detection of p-bit error in a ds3 frame ? detection of cp-bit error in a ds3 frame ? the receive feac message - validation interrupt ? the receive feac message - removal interrupt ? completion of reception of a lapd message 4.3.6.1 enabling receive section interrupts as mentioned in section 1.6, the interrupt structure, within the XRT72L50 contains two hierarchical levels. ? block level ? source level the block level the enable state of the block level for the receive section interrupts dictates whether or not interrupts (if enabled at the source level), are actually enabled. the user can enable or disable these receive sec- tion interrupts, at the block level by writing the appro- priate data into bit 7 (rx ds3/e3 interrupt enable) within the block interrupt enable register (address = 0x04), as illustrated below. f igure 96. a n i llustration of the b ehavior of the signals between the r eceive p ayload d ata o utput i nterface b lock of the XRT72L50 and the t erminal e quipment (n ibble -m ode o peration ). terminal equipment signals xrt72l5x receive payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: rxframe pulses high to denote ds3 frame boundary. rxoutclk rx_start_of_frame rx_ds3_clock_in ds3_data_in[3:0] nibble [0] nibble [1] rxoutclk rxframe rxclk rxnib[3:0] nibble [0] nibble [1] recommended sampling edge of terminal equipment xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 229 setting this bit-field to 1 enables the receive sec- tion (at the block level) for interrupt generation. con- versely, setting this bit-field to 0 disables the re- ceive section for interrupt generation. 4.3.6.2 enabling/disabling and servicing receive section interrupts as mentioned earlier, the receive section of the XRT72L50 framer ic contains numerous interrupts. the enabling/disabling and servicing of each of these interrupts is described below. 4.3.6.2.1 the change of state on receive los interrupt if the change of state on receive los (loss of sig- nal) interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following conditions. 1. when the XRT72L50 framer ic declares an los (loss of signal) condition, and 2. when the XRT72L50 framer ic clears the los (loss of signal) condition. conditions causing the XRT72L50 framer ic to declare an los condition ? if the xrt7300 liu ic declares an los condition, and drives the rlos input pin (of the XRT72L50 framer ic) "high". ? if the XRT72L50 framer ic detects a 180 consecu- tive 0s, via the rxpos and rxneg input pins. conditions causing the XRT72L50 framer ic to clear the los condition. ? when the xrt7300 liu ic ceases declaring an los condition and drives the rlos input pin (of the XRT72L50 framer ic) "low". ? when the XRT72L50 framer ic detects at least 60 marks (via the rxpos and rxneg input pins) out of 180 bit-periods. enabling and disabling the change of state on receive los interrupt: the user can enable or disable the change of state on receive los interrupt, by writing the appropriate value into bit 6 (los interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive los in- terrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving this pin "low". block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one second interrupt enable r/wrororororor/wr/w x0000000 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 230 ? it will set bit 6 (los interrupt status) within the rxds3 interrupt status register to 1, as illustrated below. whenever the users system encounters the change of los on receive interrupt, then it should do the fol- lowing. 1. it should determine the current state of the los condition. recall, that this interrupt can gener- ated, whenever the XRT72L50 framer declares or clears the los defects. hence, the user can determine the current state of the los defect by reading the state of bit 6 (rxlos), within the rxds3 configuration & status registers, as illus- trated below. if the los state is true 1. it should transmit a ferf (far-end receive fail- ure) to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-los feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal, indicating that a loss of signal condition has been declared. if the los state is false 1. it should cease transmitting a ferf indicator to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-los feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal equipment, indicating that the loss of sig- nal condition has been cleared. 4.3.6.2.2 the change of state on receive oof interrupt if the change of state on receive oof (out-of- frame) interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to ei- ther of the following conditions. 1. when the XRT72L50 framer ic declares an oof (out of frame) condition, and 2. when the XRT72L50 framer ic clears the oof (out of frame) condition. conditions causing the XRT72L50 framer ic to declare an oof condition ? if the receive ds3 framer block (within the XRT72L50 framer ic) detects at least either 3 or 6 f-bit errors, in the last 16 f-bits. conditions causing the XRT72L50 framer ic to clear the oof condition. ? whenever, the receive ds3 framer block transi- tions from the m-bit search into the in-frame state (within the frame acquisition/maintenance state machine diagram). enabling and disabling the change of state on receive oof interrupt: the user can enable or disable the change of state on receive oof interrupt, by writing the appropriate rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 01000000 rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 01000000 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 231 value into bit 1 (oof interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive oof in- terrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving this pin "low". ? it will set bit 1 (oof interrupt status), within the rxds3 interrupt status register to 1, as indicated below. whenever the terminal equipment encounters a change in oof on receive interrupt, then it should do the following. 1. it should determine the current state of the oof condition. recall, that this interrupt can gener- ated, whenever the XRT72L50 framer declares or clears the oof defects. hence, the user can determine the current state of the oof defect by reading the state of bit 4 (rxoof), within the rxds3 configuration & status registers, as illus- trated below. if oof is true. 1. it should transmit a ferf (far-end receive fail- ure) to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-oof feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal, indicating that a service affecting condi- tion has been detected in the local terminal equipment. if oof is false 1. it should cease transmitting a ferf (far-end receive failure) indicator to the remote terminal equipment. the XRT72L50 framer ic automati- cally supports this action via the ferf-upon- oof feature. rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rurrurrurrurrurrurrurrur 00000010 rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 232 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal equipment, indicating that the service affecting condition has been cleared. 4.3.6.2.3 the change of state of receive ais interrupt if the change of state on receive ais (alarm indica- tion signal) interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to ei- ther of the following conditions. 1. when the XRT72L50 framer ic detects an ais pattern, in the incoming ds3 data stream, and 2. when the XRT72L50 framer ic no longer detects the ais pattern in the incoming ds3 data stream. conditions causing the XRT72L50 framer ic to declare an ais condition ? if the receive ds3 framer block (within the XRT72L50 framer ic) detects at least 63 ds3 frames, which contains the ais pattern. conditions causing the XRT72L50 framer ic to clear the ais condition. ? whenever, the receive ds3 framer block detects 63 ds3 frames, which do not contain the ais pat- tern. enabling and disabling the change of state on receive ais interrupt: the user can enable or disable the change of state on receive ais interrupt, by writing the appropriate value into bit 5 (ais interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive ais in- terrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving it "low". ? it will set bit 5 (ais interrupt status) within the rxds3 interrupt status register, to 1, as indi- cated below. whenever the terminal equipment encounters a change in ais on receive interrupt, it should do the following. 1. it should determine the current state of the ais condition. recall, that this interrupt can gener- ated, whenever the XRT72L50 framer declares or clears the ais defects. hence, the user can determine the current state of the ais defect by reading the state of bit 7 (rxais), within the rxds3 configuration & status registers, as illus- trated below rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00100000 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 233 if the ais condition is true 1. the local terminal equipment should transmit a ferf (far-end receive failure) to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf- upon-ais feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal, indicating that a service affecting condi- tion has been detected in the local terminal equipment. if the ais condition is false 1. the local terminal equipment should cease transmitting a ferf (far-end receive failure) indicator to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-ais feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core) to the remote ter- minal, indicates that the service affecting condi- tion no longer exists. 4.3.6.2.4 the change of state of receive idle interrupt if the change of state on receive idle interrupt is en- abled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following condi- tions. 1. when the XRT72L50 framer ic detects an idle pattern, in the incoming ds3 data stream, and 2. when the XRT72L50 framer ic no longer detects the idle pattern in the incoming ds3 data stream. conditions causing the XRT72L50 framer ic to declare an idle condition ? if the receive ds3 framer block (within the XRT72L50 framer ic) detects at least 63 ds3 frames, which contains the idle pattern. conditions causing the XRT72L50 framer ic to clear the idle condition. ? whenever, the receive ds3 framer block detects 63 ds3 frames, which do not contain the idle pat- tern. enabling and disabling the change of state on receive idle interrupt: the user can enable or disable the change of state on receive idle interrupt, by writing the appropriate value into bit 4 (idle interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive idle in- terrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving it "low". ? it will set bit 4 (idle interrupt status), within the rx ds3 interrupt status register to 1, as indicated below. rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 00000000 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 234 whenever the terminal equipment encounters the change in idle condition receive interrupt, it should do the following. 1. it should determine the current state of the idle condition. recall, that this interrupt can gener- ated, whenever the XRT72L50 framer declares or clears the idle condition. hence, the user can determine the current state of the idle condition by reading the state of bit 5 (rxidle), within the rxds3 configuration & status registers, as illus- trated below 4.3.6.2.5 the change of state of receive ferf interrupt if the change of state on receive ferf interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic detects the ferf indicator, in the incoming ds3 data stream, and 2. when the XRT72L50 framer ic no longer detects the ferf indicator, in the incoming ds3 data stream. conditions causing the XRT72L50 framer ic to declare an ferf (far-end-receive failure) condi- tion ? if the receive ds3 framer block (within the XRT72L50 framer ic) detects some incoming ds3 frames with both of the x bits set to 0. conditions causing the XRT72L50 framer ic to clear the ferf condition. ? whenever, the receive ds3 framer block starts to detect some incoming ds3 frames, in which the x bits are not set to 0. enabling and disabling the change of state on receive ferf interrupt: the user can enable or disable the change of state on receive ferf interrupt, by writing the appropriate value into bit 3 (ferf interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00010000 rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 00000000 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 235 servicing the change of state on receive ferf interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving it "high". ? it will set bit 3 (ferf interrupt status), within the rx ds3 interrupt status register, to 1, as indi- cated below. whenever the terminal equipment encounters a change in ferf condition on receive interrupt, it should do the following. 1. it should determine the current state of the ferf condition. recall, that this interrupt can gener- ated, whenever the XRT72L50 framer declares or clears the ferf condition. hence, the user can determine the current state of the ferf con- dition by reading the state of bit 5 (rxidle), within the rxds3 configuration & status registers, as illustrated below 4.3.6.2.6 the change of state of receive aic interrupt if the change of state of receive aic interrupt is en- abled, then the XRT72L50 framer ic will generate an interrupt, anytime the receive ds3 framer block has detected a change in the value of the aic bit, within the incoming ds3 data stream. enabling and disabling the change of state of receive aic interrupt: the user can enable or disable the change of state on receive aic interrupt, by writing the appropriate value into bit 2 (aic interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive aic in- terrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving it "high". rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rurrurrurrurrurrurrurrur 00001000 rxds3 status register (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxferf rxaic rxfebe[2:0] ro ro ro ro ro ro ro ro 00000000 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 236 ? it will set bit 3 (aic interrupt status), within the rx ds3 interrupt status register, to 1, as indicated below. whenever the terminal equipment encounters this in- terrupt, it should do the following. ? it should continue to check the state of the aic bit, in order to see if this change is constant. ? if this change is constant, then the user should con- figure the XRT72L50 framer ic to operate in the m13 framing format, if the aic bit-field is 0. ? conversely, if the aic bit-field is 1, then the user should configure the XRT72L50 framer ic to oper- ate in the c-bit parity framing format. 4.3.6.2.7 the detection of p-bit error interrupt if the detection of p-bit error interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt, anytime the receive ds3 framer block has de- tected a p-bit error, within the incoming ds3 data stream. enabling and disabling the detection of p-bit er- ror interrupt: the user can enable or disable the detection of p-bit error interrupt, by writing the appropriate value into bit 0 (p-bit error interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of p-bit error interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving it "high". ? it will set bit 0 (p-bit error interrupt status) within the rx ds3 interrupt status register, to 1, as indi- cated below. whenever the terminal equipment encounters the detection of p-bit error interrupt, it should read the contents of pmon parity error count register (locat- ed at 0x54 and 0x55), in order to determine the num- ber of p-bit errors recently received. rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00000100 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00000001 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 237 4.3.6.2.8 the detection of cp-bit error inter- rupt if the detection of cp-bit error interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt, anytime the receive ds3 framer block has de- tected a cp-bit error, within the incoming ds3 data stream. enabling and disabling the detection of cp-bit error interrupt: the user can enable or disable the detection of cp- bit error interrupt, by writing the appropriate value in- to bit 7 (cp-bit error interrupt enable) within the rxds3 interrupt enable register, as illustrated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of cp-bit error interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ) by driving it "high". ? it will set bit 7 (cp-bit error interrupt status) within the rx ds3 interrupt status register, to 1, as indi- cated below. whenever the terminal equipment encounters the detection of cp-bit error interrupt, it should do the following. ? it should read contents of pmon frame cp-bit error count register (located at 0x72 and 0x73), in order to determine the number of cp-bit errors recently received. 4.3.6.2.9 the receive feac message - valida- tion interrupt if the receive feac message - validation interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt any time the receive feac processor validates a new feac (far-end alarm & control) message. in particular, the receive feac processor will vali- date a feac message, it that same feac message has been received in 8 of the last 10 feac message receptions. enabling/disabling the receive feac message - validation interrupt the user can enable or disable the receive feac message - validation interrupt, by writing the appro- priate data into bit 1 (rxfeac valid interrupt enable) within the rxds3 feac interrupt enable/status reg- ister, as indicated below. rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rurrurrurrurrurrurrurrur 10000001 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 238 setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the receive feac message - validation interrupt. whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ) by driving it "low". ? it will set bit 0 (rxfeac valid interrupt status), within the rxds3 feac interrupt enable/status register to 1, as indicated below. ? it will write the contents of this validated feac message into the rx ds3 feac register, as indi- cated below. whenever the terminal equipment encounters the receive feac message - validation interrupt, then it should do the following. ? it should read the contents of the high rxds3 feac register, and respond accordingly. 4.3.6.2.10 the receive feac message - removal interrupt if the receive feac message - removal interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt any time the high receive feac proces- sor removes a new feac (far-end alarm & control) message. in particular, the receive feac processor will re- move a feac message, it has received a different feac message (from the most recently validated message) in 3 of the last 10 feac message recep- tions. enabling/disabling the receive feac message - removal interrupt the user can enable or disable the receive feac message - removal interrupt, by writing the appropri- ate data into bit 1 (rxfeac remove interrupt en- able) within the rxds3 feac interrupt enable/status register, as indicated below. rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 000000x0 rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 00000011 rxds3 feac register (address = 0x16) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxfeac[5:0] not used ro ro ro ro r/o r/o r/o r/o 00000000 xrt72l5 single channel ds3/e3 framer ic with hdlc controller ? ? ? ? preliminary rev. p1.1.3 239 setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the receive feac message - validation interrupt. whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ) by driving it "low". ? it will set bit 2 (rxfeac remove interrupt status), within the rxds3 feac interrupt enable/status register to 1, as indicated below. ? it will write the delete contents of the most recently validated feac message from the rx ds3 feac register, as indicated below. 4.3.6.2.11 the completion of reception of a lapd message interrupt if the completion of reception of a lapd message interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt anytime the receive hdlc controller block has received a new lapd message buffer, from the remote terminal equipment, and has stored the contents of this message in the receive lapd message buffer. enabling/disable the receive lapd message in- terrupt the user can enable or disable the receive lapd message interrupt by writing the appropriate data into rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 0000x0x0 rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 00000011 rxds3 feac register (address = 0x16) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxfeac[5:0] not used ro ro ro ro r/o r/o r/o r/o 0xxxxxx0 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller xrt72l5 preliminary rev. p1.1.3 240 bit 1 (rxlapd interrupt enable) within the rxds3 lapd control register, as indicated below. writing a 1 into this bit-field enables the receive lapd message interrupt. conversely, writing a 0 into this bit-field disables the receive lapd message interrupt. servicing the receive lapd message interrupt whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ) by driving it "low". ? it will set bit 0 (rxlapd interrupt status), within the rx ds3 lapd control register to 1, as indicated below. ? it will write the contents of this newly received lapd message into the receive lapd message buffer (located at 0xde through 0x135). whenever the terminal equipment encounters the receive lapd interrupt, then it should read out the contents of the receive lapd message buffer, and respond accordingly. rxds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 000000x0 rxds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000011 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 241 5.0 e3/itu-t g.751 operation of the XRT72L50 configuring the XRT72L50 to operate in the e3, itu-t g.751 mode the XRT72L50 can be configured to operate in the e3/itu-t g.751 mode by writing a 0 into bit-field 6 and a 0 into bit-field 2, within the framer operating mode register, as illustrated below. prior to describing the functional blocks within the transmit and receive sections of the XRT72L50, it is important to describe the e3, itu-t g.751 framing format. 5.1 d escription of the e3, itu-t g.751 f rames and a ssociated o verhead b its the role of the various overhead bytes are best de- scribed by discussing the e3, itu-t g.751 frame format as a whole. the e3, itu-t g.751 frame con- tains 1536 bits, of which 12 bits are overhead and the remaining 1524 bits are payload bits. each e3, itu-t g.751 frame consists of the following 12 overhead bits. ? a 10 bit fas (framing alignment signal) pattern. this pattern is assigned the constant pattern of 1111010000, and is used by the receive e3 framer block to acquire and maintain frame syn- chronization with the incoming e3 frames. ? the a (or alarm) bit. ? the n (or national) bit. ? the bip-4 bits (if configured). the frame repetition rate for this type of e3 frame is 22375 times per second, thereby resulting in the standard e3 bit rate of 34.368 mbps. figure 97 pre- sents an illustration of the e3, itu-t g.751 frame format. 5.1.1 definition of the overhead bits each of these overhead bits are further defined be- low.frame alignment signaling (fas) pattern bits the first 10 bits, within each e3, itu-t g.751 frame are known as the fas (or framing alignment signal- ing) bits. the receive e3 framer block, while trying to acquire or maintain framing synchronization with its incoming e3 frames, will attempt to locate the fas bits. the fas pattern is assigned the value 1111010000. 5.1.1.1 the a (alarm) bit the a bit typically functions as a ferf (far-end receive failure) indicator bit. however, if the user configures the XRT72L50 framer ic to transmit and receive e3 frames which are carrying the bip-4 value (located at the end of a given e3 frame), then this bit will also function as the febe indicator bit. a detailed discussion on the practical use of the a is present- ed in section 4.2.2. each of these roles of the a bit are briefly discussed below. the a bit functioning as the ferf bit-field if the receive e3 framer block (at a local terminal) is experiencing problems receiving e3 frame data from a remote terminal (e.g., an los, oof or ais framer operating mode register (address = 0x00) b it 7 b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w x 0x0x 0xx f igure 97. i llustration of the e3, itu-t g.751 f raming f ormat . frame alignment signal an data data data data bip-4 if selected 1 10 11 12 384 385 768 769 1 152 1153 1532 1536 framing alignment signal pattern = 1111010000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 242 condition), then it will inform the remote terminal equipment of this fact by commanding the local transmit e3 framer block to set the a bit-field, with- in the next outbound e3 frame, to 1. the local transmit e3 framer block will continue to set the a bit-field (within the subsequent outbound e3 frames) to 1 until the receive e3 framer block no longer ex- periences problems in receiving the e3 frame data. if the remote terminal equipment receives a certain number of consecutive e3 frames, with the a bit- field set to 1, then the remote terminal equipment will interpret this signaling as an indication of a far- end receive failure (e.g., a problem with the local terminal equipment). conversely, if the receive e3 framer block (at a lo- cal terminal equipment) is not experiencing any problems receiving e3 frame data from a remote ter- minal equipment, then it will also inform the remote terminal equipment of this fact by commanding the local transmit e3 framer block to set the a bit-field within an outbound e3 frame (which is destined for the remote terminal) to 0. the remote terminal equipment will interpret this form of signaling as an indication of a normal operation. a detailed discussion into the practical use of the a bit-field is presented in section 4.2.2. 5.1.1.2 the n bit the n bit is typically used to transport pmdl (path maintenance data link) information, from one termi- nal to the next. however, the n bit-field can also be used to transport a proprietary data link, if configured according. a detailed discussion into the practical use of the n- bit field is presented in section 4.2.2. 5.2 t he t ransmit s ection of the XRT72L50 (e3, itu-t g.751 m ode o peration ) when the XRT72L50 has been configured to operate in the e3, itu-t g.751 mode, the transmit section of the XRT72L50 consists of the following functional blocks. ? transmit payload data input interface block ? transmit overhead data input interface block ? transmit e3 framer block ? transmit hdlc controller block ? transmit liu interface block figure 98 presents a simple illustration of the trans- mit section of the XRT72L50 framer ic. each of these functional blocks will be discussed in detail in this document. 5.2.1 the transmit payload data input interface block figure 99 presents a simple illustration of the trans- mit payload data input interface block. f igure 98. a s imple i llustration of the XRT72L50 t ransmit s ection when it has been configured to operate in the e3 m ode transmit payload data input interface block transmit ds3/e3 framer block transmit liu interface block txser txnib[3:0] txinclk txpos txneg txlineclk transmit overhead input interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe tx e3 hdlc controller/buffer tx e3 hdlc controller/buffer from microprocessor interface block XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 243 each of the input and output pins of the transmit pay- load data input interface are listed in table 46 and described below. the exact role that each of these inputs and output pins assume, for a variety of operat- ing scenarios are described throughout this section. f igure 99. a s imple i llustration of the t ransmit p ayload d ata i nput i nterface b lock transmit payload data input interface block transmit payload data input interface block txoh_ind txser txnib[3:0] txinclk txnibclk txframe txframeref to transmit ds3 framer block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 244 operation of the transmit payload data input in- terface the transmit terminal input interface is extremely flexible, in that it permits the user to make the follow- ing configuration options. t able 46: l isting and d escription of the pins associated with the t ransmit p ayload d ata i nput i nterface s ignal n ame t ype d escription txser input transmit serial payload data input pin: if the user opts to operate the XRT72L50 in the serial mode, then the terminal equipment is expected to apply the payload data (that is to be transported via the outbound e3 data stream) to this input pin. the XRT72L50 will sample the data that is at this input pin upon the rising edge either the rxoutclk or the txinclk signal (whichever is appropriate). n ote : this signal is only active if the nibint input pin is pulled "low". txnib[3:0] input transmit nibble-parallel payload data input pins: if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the terminal equip- ment is expected to apply the payload data (that is to be transported via the outbound e3 data stream) to these input pins. the XRT72L50 will sample the data that is at these input pins upon the rising edge of the txnibclk signal. n ote : these pins are only active if the nibint input pin is pulled "high". txinclk input transmit section timing reference clock input pin: the transmit section of the XRT72L50 can be configured to use this clock signal as the tim- ing reference. if the user has made this configuration selection, then the XRT72L50 will use this clock signal to sample the data on the txser input pin. n ote : if this configuration is selected, then a 34.368 mhz clock signal must be applied to this input pin. txnibclk output transmit nibble mode output if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the XRT72L50 will derive this clock signal from the selected timing reference for the transmit section of the chip (e.g., either the txinclk or the rxlineclk signals). the XRT72L50 will use this signal to sample the data on the txnib[3:0] input pins. txohind output transmit overhead bit indicator output: this output pin will pulse "high" one-bit period prior to the time that the transmit section of the XRT72L50 will be processing an overhead bit. the purpose of this output pin is to warn the terminal equipment that, during the very next bit-period, the XRT72L50 is going to be pro- cessing an overhead bit and will be ignoring any data that is applied to the txser input pin. txframe output transmit end of frame output indicator: the transmit section of the XRT72L50 will pulse this output pin "high" (for one bit-period), when the transmit payload data input interface is processing the last bit of a given e3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin trans- mission of a new e3 frame to the XRT72L50 (e.g., to permit the XRT72L50 to maintain trans- mit e3 framing alignment control over the terminal equipment). txframeref input transmit frame reference input: the XRT72L50 permits the user to configure the transmit section to use this input pin as a frame reference. if the user makes this configuration selection, then the transmit section will initiate its transmission of a new e3 frame, upon the rising edge of this signal. the purpose of this input pin is to permit the terminal equipment to maintain transmit e3 framing alignment control over the XRT72L50. rxoutclk output loop-timed timing reference clock output pin: the transmit section of the XRT72L50 can be configured to use the rxlineclk signal as the timing reference (e.g., loop-timing). if the user has made this configuration selection, then the XRT72L50 will: ? output a 34.368 mhz clock signal via this pin, to the terminal equipment. ? sample the data on the txser input pin, upon the rising edge of this clock signal. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 245 ? the serial or the nibble-parallel interface mode ? the loop-timing or the txinclk (local timing) mode further, if the XRT72L50 has been configured to op- erate in the local-timing mode, then the user has two additional options. ? the XRT72L50 is the frame master (e.g., it dictates when the terminal equipment will initiate the trans- mission of data within a new e3 frame). ? the XRT72L50 is the frame slave (e.g., the termi- nal equipment will dictate when the XRT72L50 ini- tiates the transmission of a new e3 frame). given these three set of options, the transmit termi- nal input interface can be configured to operate in one of the six (6) following modes. ? mode 1 - serial/loop-timed mode ? mode 2 - serial/local-timed/frame slave mode ? mode 3 - serial/local-timed/frame master mode ? mode 4 - nibble/loop-timed mode ? mode 5 - nibble/local-timed/frame slave mode ? mode 6 - nibble/local-timed/frame master mode each of these modes are described, in detail, below. 5.2.1.1 mode 1 - the serial/loop-timing mode the behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. a. loop-timing (uses the rxlineclk signal as the timing reference) since the XRT72L50 is configured to operate in the loop-timed mode, the transmit section of the XRT72L50 will use the rxlineclk input clock signal (e.g., the recovered clock signal, from the liu) as its timing source. when the XRT72L50 is operating in this mode it will do the following. 1. it will ignore any signal at the txinclk input pin. 2. the XRT72L50 will output a 34.368mhz clock signal via the rxoutclk output pin. this clock signal functions as the transmit payload data input interface block clock signal. 3. the XRT72L50 will use the rising edge of the rxoutclk signal to latch in the data residing on the txser input pin. b. serial mode the XRT72L50 will accept the e3 payload data from the terminal equipment, in a serial-manner, via the txser input pin the transmit payload data input in- terface will latch this data into its circuitry, on the ris- ing edge of the rxoutclk output clock signal. c. delineation of outbound e3 frames the XRT72L50 will pulse the txframe output pin "high" for one bit-period coincident with the XRT72L50 processing the last bit of a given e3 frame. d. sampling of payload data, from the terminal equipment in mode 1, the XRT72L50 will sample the data at the txser input, on the rising edge of rxoutclk. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 1 operation figure 100 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 1 operation. f igure 100. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 1 (s erial /l oop -t imed ) o peration terminal equipment xrt72l5x e3 framer e3_data_out e3_clock_in tx_start_of_frame e3_overhead_ind txser rxoutclk txframe txoh_ind nibint 34.368 mhz ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 246 mode 1 operation of the terminal equipment when the XRT72L50 is operating in this mode, it will function as the source of the 34.368mhz clock signal. this clock signal will be used as the terminal equip- ment interface clock by both the XRT72L50 ic and the terminal equipment. the terminal equipment will serially output the pay- load data of the outbound e3 data stream via its e3_data_out pin. the terminal equipment will up- date the data on the e3_data_out pin upon the rising edge of the 34.368 mhz clock signal, at its e3_clock_in input pin (as depicted in figure 100 and figure 101). the XRT72L50 will latch the outbound e3 data stream (from the terminal equipment) on the rising edge of the rxoutclk signal. the XRT72L50 will indicate that it is processing the last bit, within a given outbound e3 frame, by pulsing its txframe output pin "high" for one bit-period. when the terminal equipment detects this pulse at its tx_start_of_frame input, it is expected to begin transmission of the very next outbound e3 frame to the XRT72L50 via the e3_data_out (or txser pin). finally, the XRT72L50 will indicate that it is about to process an overhead bit by pulsing the txoh_ind output pin "high" one bit period prior to its processing of an oh (overhead) bit. in figure 100, the txoh_ind output pin is connected to the e3_overhead_ind input pin of the terminal equip- ment. whenever the e3_overhead_ind pin is pulsed "high" the terminal equipment is expected to not transmit a e3 payload bit upon the very next clock edge. instead, the terminal equipment is expected to delay its transmission of the very next payload bit, by one clock cycle. the behavior of the signals, between the XRT72L50 and the terminal equipment, for e3 mode 1 operation is illustrated in figure 101. inserting the a and n bits into the outbound e3 frames via the transmit payload data input inter- face block the XRT72L50 ds3/e3 framer permits the terminal equipment to insert its own values for the a and/or n bits, into the outbound e3 frame, via the transmit payload data input interface block. if the user de- sires to do this, the XRT72L50 framer ic must be configured to accept the terminal equipments value for the a and n bits, by writing to appropriate data into the txasourcesel[1:0] and txnsourcesel[1:0] bit-fields, within the txe3 configuration register (ad- dress =0x30), as illustrated below. configuring the transmit payload data input in- terface block to accept the a bits from the ter- minal equipment if the user wishes to configure the transmit payload data input interface block to accept the a bits from the terminal equipment, then the user must write the value 10 into the txasourcesel[1:0] bit-fields. once the user does this, then any value, which re- sides on the txser input pin, when the a bit is being processed by the transmit section will be inserted in- to the a bit-field within the very next outbound e3 frame. for completeness, the relationship between the con- tents of the txasourcesel[1:0] bits and the resulting source of the a bit is listed below. bit 6, 5, txasourcesel[1:0] these two read/write bit-fields combine to specify the source of the a-bit, within each outbound e3 frame. the relationship between these two bit-fields and the resulting source of the a bit is tabulated be- low. txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w 0xxxx0 0 0 t x as ource s el [1:0] s ource of a b it 00 txe3 service bits register (address = 0x35) XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 247 configuring the transmit payload data input interface block to accept the n bits from the terminal equip- ment, then the user must write the value 11 into the txnsourcesel[1:0] bit-fields. once the user does this, then any value, which resides on the txser input pin, when the n bit is being processed by the trans- mit section will be inserted into the n bit-field within the very next outbound e3 frame. for completeness, the relationship between the con- tents of the txnsourcesel[1:0] bits and the resulting source of the n bit is listed below. bits 4, 3, txnsourcesel[1:0] these two read/write bit-fields combine to specify the source of the n-bit, within each outbound e3 frame. the relationship between these two bit-fields and the resulting source of the n bit is tabulated be- low. 01 transmit overhead data input interface 10 transmit payload data input interface 11 functions as a febe (far-end-block error) bit-field. this bit-field is set to "0", if the near-end receive section (within this chip) detects no bip-4 errors within the incoming e3 frames. this bit-field is set to "1", if the near-end receive section (within this chip) detects a bip-4 error within the incoming e3 frame. t x as ource s el [1:0] s ource of a b it t x ns ource s el [1:0] s ource of n b it 00 txe3 service bits register (address = 0x35) 01 transmit overhead data input interface 10 transmit lapd controller 11 transmit payload data input interface . ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 248 how to configure the XRT72L50 into the serial/ loop-timed/non-overhead interface mode 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit fields (within the framer operating mode register) to "00", as illustrated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 100. 5.2.1.2 mode 2 - the serial/local-timed/ frame-slave mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows. a. local-timed - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal as its timing reference. b. serial mode the XRT72L50 will receive the e3 payload data, in a serial manner, via the txser input pin. the transmit payload data input interface (within the XRT72L50) will latch this data into its circuitry, on the rising edge of the txinclk input clock signal. f igure 101. b ehavior of the t erminal i nterface signals between the XRT72L50 t ransmit p ayload d ata i nput i nterface block and the t erminal e quipment ( for m ode 1 o peration ) terminal equipment signals e3_clock_in e3_data_out tx_start_of_frame e3_overhead_ind xrt72l5x transmit payload data i/f signals rxoutclk txser txframe txoh_ind payload[1522] payload[1523] fas, bit 9 fas, bit 8 payload[1522] payload[1523] fas, bit 9 fas, bit 8 note: the fas pattern will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: txframe pulses high to denote e3 frame boundary. note: txoh_ind pulses high for 12 bit periods in order to denote overhead data (e.g., the fas pattern and the a & n bits). framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 249 c. delineation of outbound e3 frames (frame slave mode) the transmit section of the XRT72L50 will use the txinclk input as its timing reference, and will use the txframeref input signal as its framing reference. in other words, the transmit section of the XRT72L50 will initiate frame generation upon the rising edge of the txframeref input signal). d. sampling of payload data, from the terminal equipment in mode 2, the XRT72L50 will sample the data, at the txser input pin, on the rising edge of txinclk. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 2 operation figure 102 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 2 operation. mode 2 operation of the terminal equipment as shown in figure 102, both the terminal equipment and the XRT72L50 will be driven by an external 34.368mhz clock signal. the terminal equipment will receive the 34.368mhz clock signal via its e3_clock_in input pin, and the XRT72L50 framer ic will receive the 34.368mhz clock signal via the txin- clk input pin. the terminal equipment will serially output the pay- load data of the outbound e3 data stream, via the e3_data_out output pin, upon the rising edge of the signal at the e3_clock_in input pin. n ote : the e3_data_out output pin of the terminal equip- ment is electrically connected to the txser input pin the XRT72L50 framer ic will latch the data, residing on the txser input line, on the rising edge of the txin- clk signal. in this case, the terminal equipment has the respon- sibility of providing the framing reference signal by pulsing its tx_start_of_frame output signal (and in turn, the txframeref input pin of the XRT72L50), "high" for one-bit period, coincident with the first bit of a new e3 frame. once the XRT72L50 detects the ris- ing edge of the input at its txframeref input pin, it will begin generation of a new e3 frame. n otes : 1. in this case, the terminal equipment is controlling the start of frame generation, and is therefore referred to as the frame master. conversely, since the XRT72L50 does not control the generation of a new e3 frame, but is rather driven by the terminal equipment, the XRT72L50 is referred to as the frame slave. 2. if the user opts to configure the XRT72L50 to oper- ate in mode 2, it is imperative that the f igure 102. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 2 (s erial /l ocal -t imed /f rame -s lave ) o peration e3_clock_in e3_data_out txstart_of_frame e3_overhead_ind e3_clock_in e3_data_out txstart_of_frame e3_overhead_ind txinclk txser txframeref txoh_ind nibint txinclk txser txframeref txoh_ind nibint 34.368 mhz clock source 34.368 mhz clock source xrt72l5x e3 framer terminal equipment ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 250 tx_start_of_frame (or txframeref) signal is syn- chronized to the txinclk input clock signal. finally, the XRT72L50 will pulse its txoh_ind output pin, one bit-period prior to it processing a given over- head bit, within the outbound e3 frame. since the txoh_ind output pin of the XRT72L50 is electrically connected to the e3_overhead_ind whenever the XRT72L50 pulses the txoh_ind output pin "high", it will also be driving the e3_overhead_ind input pin (of the terminal equipment) "high". whenever the ter- minal equipment detects this pin toggling "high", it should delay transmission of the very next e3 frame payload bit by one clock cycle. the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 2 operation is illustrated in figure 103. how to configure the XRT72L50 to operate in this mode. 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01" as depicted below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 102. 5.2.1.3 mode 3 - the serial/local-timed/ frame-master mode behavior of the XRT72L50 f igure 103. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (m ode 2 o peration ) terminal equipment signals e3_clock_in e3_data_out tx_start_of_frame e3_overhead_ind xrt72l5x transmit payload data i/f signals txinclk txser txframeref txoh_ind payload[1522] payload[1523] fas, bit 9 fas, bit 8 payload[1522] payload[1523] fas, bit 9 fas, bit 8 note: fas pattern bits will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: txframe pulses high to denote e3 frame boundary. note: txoh_ind pulses high for 12 bit periods in order to denote overhead data (e.g., the fas pattern and the a & n bits). framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 1 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 251 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows. a. local-timed - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal as its timing reference. b. serial mode the XRT72L50 will receive the e3 payload data, in a serial manner, via the txser input pin. the transmit payload data input interface (within the XRT72L50) will latch this data into its circuitry, on the rising edge of the txinclk input clock signal. c. delineation of outbound ds3 frames (frame master mode) the transmit section of the XRT72L50 will use the txinclk signal as its timing reference, and will initiate e3 frame generation, asynchronously with respect to any externally applied signal. the XRT72L50 will pulse its txframe output pin "high" whenever its it processing the very last bit-field within a given e3 frame. d. sampling of payload data, from the terminal equipment in mode 3, the XRT72L50 will sample the data, at the txser input pin, on the rising edge of txinclk. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 3 operation figure 104 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 3 operation. mode 3 operation of the terminal equipment in figure 104, both the terminal equipment and the XRT72L50 are driven by an external 34.368 mhz clock signal. this clock signal is connected to the e3_clock_in input of the terminal equipment and the txinclk input pin of the XRT72L50. the terminal equipment will serially output the pay- load data on its e3_data_out output pin, upon the rising edge of the signal at the e3_clock_in input pin. similarly, the XRT72L50 will latch the data, residing on the txser input pin, on the rising edge of txinclk. the XRT72L50 will pulse the txframe output pin "high" for one bit-period, coincident while it is pro- cessing the last bit-field within a given outbound e3 frame. the terminal equipment is expected to moni- tor the txframe signal (from the XRT72L50) and to place the first bit, within the very next outbound e3 frame on the txser input pin. f igure 104. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 3 (s erial /l ocal -t ime /f rame -m aster ) o peration terminal equipment xrt72l5x e3 framer e3_data_out e3_clock_in tx_start_of_frame e3_overhead_ind txser txinclk txframe txoh_ind nibint 34.368 mhz clock source ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 252 n ote : in this case, the XRT72L50 dictates exactly when the very next e3 frame will be generated. the terminal equipment is expected to respond appropriately by provid- ing the XRT72L50 with the first bit of the new e3 frame, upon demand. hence, in this mode, the XRT72L50 is referred to as the frame master and the terminal equip- ment is referred to as the frame slave. finally, the XRT72L50 will pulse its txoh_ind output pin, one bit-period prior to it processing a given over- head bit, within the outbound e3 frame. since the txoh_ind output pin (of the XRT72L50) is electrically connected to the e3_overhead_ind whenever the XRT72L50 pulses the txoh_ind output pin "high, it will also be driving the e3_overhead_ind input pin (of the terminal equipment) "high". whenever the ter- minal equipment detects this pin toggling "high", it should delay transmission of the very next ds3 frame payload bit by one clock cycle. the behavior of the signal between the XRT72L50 and the terminal equipment for e3 mode 3 operation is illustrated in figure 105. how to configure the XRT72L50 to operate in this mode. 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01" as depicted below. f igure 105. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (e3 m ode 3 o peration ) terminal equipment signals e3_clock_in e3_data_out tx_start_of_frame e3_overhead_ind xrt72l5x transmit payload data i/f signals txinclk txser txframe txoh_ind payload[1522] payload[1523] fas , bit 9 fas, bit 8 payload[1522] payload[1523] fas, bit 9 fas, bit 8 note: fas pattern will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: txframe pulses high to denote e3 frame boundary. note: txoh_ind pulses high for 12 bit-periods in order to denote overhead data (e.g., the fas pattern, the a and n bits). framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 253 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 104. 5.2.1.4 mode 4 - the nibble-parallel/loop- timed mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. a. looped timing (uses the rxlineclk as the timing reference) in this mode, the transmit section of the XRT72L50 will use the rxlineclk signal as its timing reference. when the XRT72L50 is operating in the nibble-mode, it will internally divide the rxlineclk signal, by a fac- tor of four (4) and will output this signal via the txnib- clk output pin. b. nibble-parallel mode the XRT72L50 will accept the e3 payload data, from the terminal equipment in a nibble-parallel manner, via the txnib[3:0] input pins. the transmit terminal equipment input interface block will latch this data in- to its circuitry, on the rising edge of the txnibclk out- put signal. c. delineation of the outbound e3 frames the XRT72L50 will pulse the txnibframe output pin "high" for one bit-period coincident with the XRT72L50 processing the last nibble of a given e3 frame. d. sampling of payload data, from the terminal equipment in mode 4, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the rxoutclk clock signal, following a pulse in the txnib- clk signal (see figure 107). n ote : the txnibclk signal, from the XRT72L50 operates nominally at 8.592 mhz (e.g., 34.368 mhz divided by 4). the e3 frame consists of 1536 bits or 384 nibbles. therefore, the XRT72L50 will supply 384 txnibclk pulses between the rising edges of two consecutive txnibframe pulses. the e3 frame repetition rate is 22.375khz. hence, 384 txnibclk pulses for each e3 frame period amounts to txnibclk running at approx- imately 8.592 mhz. the method by which the 384 txnibclk pulses are distributed throughout the e3 frame period is presented below. nominally, the transmit section within the XRT72L50 will generate a txnibclk pulse for every 4 rxoutclk (or txinclk) periods. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 4 operation figure 106 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 4 operation. mode 4 operation of the terminal equipment when the XRT72L50 is operating in this mode, it will function as the source of the 8.592mhz (e.g., the 34.368mhz clock signal divided by 4) clock signal, that will be used as the terminal equipment interface clock by both the XRT72L50 and the terminal equip- ment. the terminal equipment will output the payload data of the outbound e3 data stream via its e3_data_out[3:0] pins on the rising edge of the f igure 106. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 4 (n ibble -p arallel /l oop -t imed ) o peration terminal equipment xrt72l5x e3 framer e3_data_out[3:0] e3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txnibframe nibint vcc 4 rxlineclk 34.368mhz 8.592 mhz txoh_ind e3_overhead_ind ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 254 8.592mhz clock signal at the e3_nib_clock_in input pin. the XRT72L50 will latch the outbound e3 data stream (from the terminal equipment) on the rising edge of the txnibclk output clock signal. the XRT72L50 will indicate that it is processing the last nibble, within a given e3 frame, by pulsing its txnib- frame output pin "high" for one txnibclk clock peri- od. when the terminal equipment detects a pulse at its tx_start_of_frame input pin, it is expected to transmit the first nibble, of the very next outbound e3 frame to the XRT72L50 via the e3_data_out[3:0] (or txnib[3:0] pins). finally, for the nibble-parallel mode operation, the XRT72L50 will pulse the txohind output pin "high for 3 nibble-periods (e.g., the 3 nibbles consisting of the 10 bit fas pattern, the a and the n bits). the txohind output pin will remain "low for the remain- der of the frame period. the txohind output pin will toggle "high one-nibble period before the transmit section (of the framer ic) processes the first four bits of the fas pattern. the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 4 operation is illustrated in figure 107. how to configure the XRT72L50 into mode 4 1. set the nibintf input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "00" as illus- trated below. f igure 107. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (m ode 4 o peration ) terminal equipment signals rxoutclk tx_start_of_frame e3_nib_clock_in e3_data_out[3:0] payload nibble [380] overhead nibble [0] xrt72l5x transmit payload data i/f signals e3 frame number n e3 frame number n + 1 note: txnibframe pulses high to denote e3 frame boundary. rxoutclk txnibframe txnibclk txnib[3:0] nibble [380] overhead nibble [0] e3_overhead_ind txoh_ind txoh_ind pulses high for 3 nibble periods framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 255 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 106. n ote : the XRT72L50 framer ic cannot support the framer local loop-back mode of operation, while operating in mode 4. the user must configure the XRT72L50 framer ic into any of the following modes prior to configuring the framer local loop-back mode operation. ? mode 2 - serial/local-timed/frame-slave mode ? mode 3 - serial/local-timed/frame-master mode ? mode 5 - nibble-parallel/local-timed/frame-slave mode ? mode 6 - nibble-parallel/local-timed/frame-mas- ter mode. for more detailed information on the framer local loop-back mode, please see section 6.0. 5.2.1.5 mode 5 - the nibble-parallel/local- timed/frame-slave interface mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows: a. local-timed - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal at its timing reference. further, the chip will internally divide the txinclk clock signal by a factor of 4 and will output this divid- ed clock signal via the txnibclk output pin. the transmit terminal equipment input interface block (within the XRT72L50) will use the rising edge of the txnibclk signal, to latch the data, residing on the tx- nib[3:0] into its circuitry. b. nibble-parallel mode the XRT72L50 will accept the e3 payload data, from the terminal equipment, in a parallel manner, via the txnib[3:0] input pins. the transmit terminal equip- ment input interface will latch this data into its circuit- ry, on the rising edge of the txnibclk output signal. c. delineation of outbound e3 frames the transmit section will use the txinclk input signal as its timing reference and will use the txframeref input signal as its framing reference (e.g., the trans- mit section of the XRT72L50 initiates frame genera- tion upon the rising edge of the txframeref signal). d. sampling of payload data, from the terminal equipment in mode 5, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the txinclk clock signal, following a pulse in the txnibclk signal (see figure 108). n ote : the txnibclk signal, from the XRT72L50 operates nominally at 8.592 mhz (e.g., 34.368 mhz divided by 4). interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 5 operation figure 108 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 5 operation. r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 0 framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 256 mode 5 operation of the terminal equipment in figure 108 both the terminal equipment and the XRT72L50 will be driven by an external 8.592mhz clock signal. the terminal equipment will receive the 8.592mhz clock signal via the e3_nib_clock_in input pin. the XRT72L50 will output the 8.592mhz clock signal via the txnibclk output pin. the terminal equipment will serially output the data on the e3_data_out[3:0] pins, upon the rising edge of the signal at the e3_clock_in input pin. n ote : the e3_data_out[3:0] output pins of the terminal equipment is electrically connected to the txnib[3:0] input pins. the XRT72L50 will latch the data, residing on the tx- nib[3:0] input pins, on the rising edge of the txnibclk signal. in this case, the terminal equipment has the respon- sibility of providing the framing reference signal by pulsing the tx_start_of_frame output pin (and in turn, the txframeref input pin of the XRT72L50) "high" for one bit-period, coincident with the first bit of a new e3 frame. once the XRT72L50 detects the ris- ing edge of the input at its txframeref input pin, it will begin generation of a new e3 frame. finally, the XRT72L50 will always internally generate the overhead bits, when it is operating in both the e3 and nibble-parallel modes. the XRT72L50 will pull the txohind input pin "low". the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 5 operation is illustrated in figure 109. f igure 108. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 5 (n ibble -p arallel /l ocal -t imed /f rame -s lave ) o per - ation terminal equipment xrt72l5x e3 framer e3_data_out[3:0] e3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txframeref nibint vcc 4 34.368mhz clock source txinclk 8.592mhz e3_overhead_ind txoh_ind XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 257 how to configure the XRT72L50 into mode 5 1. set the nibintf input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01" as illus- trated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 108. 5.2.1.6 4.2.1.6 mode 6 - the nibble-parallel/ local-timed/frame-master interface mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows: a. local-timed - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal at its timing reference. further, the chip will internally divide the txinclk clock signal by a factor of 4 and will output this divid- ed clock signal via the txnibclk output pin. the transmit terminal equipment input interface block (within the XRT72L50) will use the rising edge of the f igure 109. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (e3, m ode 5 o peration ) terminal equipment signals txinclk tx_start_of_frame e3_nib_clock_in e3_data_out[3:0] payload nibble [380] overhead nibble [0] xrt72l5x transmit payload data i/f signals e3 frame number n e3 frame number n + 1 note: terminal equipment pulses txframeref in order to denote the e3 frame boundary. txinclk txframeref txnibclk txnib[3:0] nibble [380] overhead nibble [0] e3_overhead_ind txoh_ind txoh_ind pulses high for 3 nibble periods framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 1 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 258 txnibclk signal, to latch the data, residing on the tx- nib[3:0] into its circuitry. b. nibble-parallel mode the XRT72L50 will accept the e3 payload data, from the terminal equipment, in a parallel manner, via the txnib[3:0] input pins. the transmit terminal equip- ment input interface will latch this data into its circuit- ry, on the rising edge of the txnibclk output signal. c. delineation of outbound e3 frames the transmit section will use the txinclk input signal as its timing reference and will initiate the generation of e3 frames, asynchronous with respect to any ex- ternal signal. the XRT72L50 will pulse the txframe output pin "high" whenever it is processing the last bit, within a given outbound e3 frame. d. sampling of payload data, from the terminal equipment in mode 6, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the txinclk clock signal, following a pulse in the txnibclk signal (see figure 111). n ote : the txnibclk signal, from the XRT72L50 operates nominally at 8.592 mhz (e.g., 34.368 mhz divided by 4). interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 6 operation figure 110 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 6 operation. mode 6 operation of the terminal equipment in figure 110 both the terminal equipment and the XRT72L50 will be driven by an external 8.592mhz clock signal. the terminal equipment will receive the 8.592mhz clock signal via the e3_nib_clock_in input pin. the XRT72L50 will output the 8.592mhz clock signal via the txnibclk output pin. the terminal equipment will serially output the data on the e3_data_out[3:0] pins upon the rising edge of the signal at the e3_clock_in input pin. the XRT72L50 will latch the data, residing on the tx- nib[3:0] input pins, on the rising edge of the txnibclk signal. in this case the XRT72L50 has the responsibility of providing the framing reference signal by pulsing the txframe output pin (and in turn the tx_start_of_frame input pin of the terminal equip- ment) "high" for one bit-period, coincident with the last bit within a given e3 frame. finally, the XRT72L50 will always internally generate the overhead bits, when it is operating in both the e3 and nibble-parallel modes. the XRT72L50 will pull the txohind input pin "low". the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 6 operation is illustrated in figure 111. f igure 110. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 6 (n ibble -p arallel /l ocal -t imed /f rame -m aster ) o peration terminal equipment xrt72l5x e3 framer e3_data_out[3:0] e3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txnibframe nibint vcc 4 34.368mhz clock source txinclk 8.592mhz txoh_ind e3_overhead_ind XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 259 how to configure the XRT72L50 into mode 6 1. set the nibint input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "1x" as illus- trated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 110. 5.2.2 the transmit overhead data input inter- face figure 112 presents a simple illustration of the trans- mit overhead data input interface block within the XRT72L50. f igure 111. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (e3 m ode 6 o peration ) terminal equipment signals txinclk tx_start_of_frame e3_nib_clock_in e3_data_out[3:0] payload nibble [380] overhead nibble [0] xrt72l5x transmit payload data i/f signals e3 frame number n e3 frame number n + 1 note: txnibframe pulses high to denote e3 frame boundary. txinclk txnibframe txnibclk txnib[3:0] nibble [380] overhead nibble [0] e3_overhead_ind txoh_ind txoh_ind pulses high for 3 nibble periods framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 1 x ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 260 the e3, itu-t g.751 frame consists of 1536 bits. of these bits, 1524 are payload bits and the remaining 12 are overhead bits. the XRT72L50 has been de- signed to handle and process both the payload type and overhead type bits for each e3 frame. within the transmit section within the XRT72L50, the transmit payload data input interface has been designed to handle the payload data. likewise, the transmit overhead input interface has been designed to han- dle and process the overhead bits. the transmit section of the XRT72L50 generates or processes the various overhead bits within the e3 frame, in the following manner. the frame alignment signaling (fas) overhead bits the fas (framing alignment signaling) bits are al- ways internally generated by the transmit section of the XRT72L50. hence, the user cannot insert his/her value for the fas bits into the outbound e3 data stream, via the transmit overhead data input inter- face. the a (alarm) overhead bit the a bit is used to transport the ferf (far-end receive failure) condition. this bit-field can be either internally generated by the transmit section within the XRT72L50, or can be externally generated and in- serted into the outbound e3 data stream, via the transmit overhead data input interface. the data link related overhead bits the n (national) overhead bit the e3 frame structure also contains the n bit which can be used to transport a proprietary user data link information and or path maintenance data link infor- mation. the udl (user data link) bits are only ac- cessible via the transmit overhead data input inter- face. the path maintenance data link (pmdl) bits can either be sourced from the transmit lapd con- troller/buffer or via the transmit overhead data input interface. table 47 lists the overhead bits within the e3 frame. in addition, this table also indicates whether or not these overhead bits can be sourced by the transmit overhead data input interface. f igure 112. s imple i llustration of the t ransmit o verhead d ata i nput i nterface block transmit overhead data input interface block transmit overhead data input interface block txohframe txohenable txoh txohclk txohins to transmit ds3 framer block XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 261 n otes : 1. the XRT72L50 contains mask register bits that permit the user to alter the state of the internally generated value for these bits. 2. the transmit lapd controller/buffer can be config- ured to be the source of the n bits, within the out- bound e3 data stream. the transmit overhead data input interface permits the user to insert overhead data into the outbound e3 frames via the following two different methods. ? method 1 - using the txohclk clock signal ? method 2 - using the txinclk and the txohenable signals. each of these methods are described below. 5.2.2.1 method 1 - using the txohclk clock signal the transmit overhead data input interface consists of the five signals. of these five (5) signals, the fol- lowing four (4) signals are to be used when imple- menting method 1. ? txoh ? txohclk ? txohframe ? txohins each of these signals are listed and described below. table 48. t able 47: a l isting of the o verhead bits within the e3 frame , and their potential sources , within the XRT72L50 ic o verhead b it i nternally generated a ccessible via the t ransmit o verhead d ata i nput i nterface b uffer /r egister a ccessible fas signal - bit 9 yes yes yes* fas signal - bit 8 yes yes yes fas signal - bit 7 yes yes yes* fas signal - bit 6 yes yes yes* fas signal - bit 5 yes yes yes fas signal - bit 4 yes yes yes fas signal - bit 3 yes yes yes fas signal - bit 2 yes yes yes fas signal - bit 1 yes yes yes fas signal - bit 0 yes yes yes a bit yes yes yes n bit yes yes yes ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 262 interfacing the transmit overhead data input in- terface to the terminal equipment. figure 113 illustrates how one should interface the transmit overhead data input interface to the termi- nal equipment, when using method 1. t able 48: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high) enables the transmit overhead data input inter- face to accept overhead data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of the txohclk output signal. conversely, setting this pin "low" configures the transmit overhead data input interface to not sample (e.g., ignore) the data at the txoh input pin, on the falling edge of the txohclk output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the transmit overhead data input interface (e.g., if the terminal equipment asserts the txohins signal, at a time when one of these non-insertable overhead bits are being processed), that par- ticular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the overhead bit position within the very next outbound e3 frame. if the txohins pin is pulled "high", the transmit overhead data input interface will sam- ple the data at this input pin (txoh), on the falling edge of the txohclk output pin. conversely, if the txohins pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. txohclk output transmit overhead input interface clock output signal: this output signal serves two purposes: 1. the transmit overhead data input interface will provide a rising clock edge on this signal, one bit-period prior to the instant that the transmit overhead data input interface is processing an overhead bit. 2. the transmit overhead data input interface will sample the data at the txoh input, on the fall- ing edge of this clock signal (provided that the txohins input pin is "high"). n ote : the transmit overhead data input interface will supply a clock edge for all overhead bits within the ds3 frame (via the txohclk output signal). this includes those overhead bits that the transmit overhead data input interface will not accept from the terminal equipment. txohframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L50 is processing the last bit within a given e3 frame. the purpose of this output signal is to alert the terminal equipment that the transmit overhead data input interface block is about to begin processing the overhead bits for a new e3 frame. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 263 method 1 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the outbound e3 data stream, (via the transmit overhead data input interface), then it is ex- pected to do the following. 1. to sample the state of the txohframe signal (e.g., the tx_start_of_frame input signal) on the rising edge of the txohclk (e.g., the e3_oh_clock_in signal). 2. to keep track of the number of rising clock edges that have occurred, via the txohclk (e.g., the e3_oh_clock_in signal) since the last time the txohframe signal was sampled "high". by doing this the terminal equipment will be able to keep track of which overhead bit is being pro- cessed by the transmit overhead data input interface block at any given time. when the ter- minal equipment knows which overhead bit is being processed, at a given txohclk period, it will know when to insert a desired overhead bit value into the outbound e3 data stream. from this, the terminal equipment will know when it should assert the txohins input pin and place the appropriate value on the txoh input pin (of the XRT72L50). table 49 relates the number of rising clock edges (in the txohclk signal, since txohframe was sampled "high") to the e3 overhead bit, that is being pro- cessed. f igure 113. i llustration of the t erminal e quipment being interfaced to the t ransmit o verhead d ata i nput i nterface (m ethod 1) terminal equipment xrt72l5x e3 framer e3_oh_out] e3_oh_clock_in tx_start_of_frame txohclk txohframe txohins 34.368 mhz clock source txinclk txoh insert_oh rxlineclk 34.368 mhz clock source ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 264 3. after the terminal equipment has waited the appropriate number of clock edges (from the txohframe signal being sampled "high"), it should assert the txohins input signal. concur- rently, the terminal equipment should also place the appropriate value (of the inserted overhead bit) onto the txoh signal. 4. the terminal equipment should hold both the txohins input pin "high" and the value of the txoh signal, stable until the next rising edge of txohclk is detected. case study: the terminal equipment intends to insert the appropriate overhead bits into the transmit overhead data input interface (using method 1) in order to transmit a yellow alarm to the remote terminal equipment. in this example, the terminal equipment intends to in- sert the appropriate overhead bits, into the transmit overhead data input interface, such that the XRT72L50 will transmit a yellow alarm to the remote terminal equipment. recall that, for e3, itu-t g.751 applications, a yellow alarm is transmitted by setting the "a" bit to "1". if one assumes that the connection between the ter- minal equipment and the XRT72L50 are as illustrated in figure 113 then figure 114 presents an illustration of the signaling that must go on between the terminal equipment and the XRT72L50. t able 49: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since t x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being processed n umber of r ising c lock e dges in t x ohc lk t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? 0 (clock edge is coincident with txo- hframe being detected "high) fas signal - bit 9 ye s 1 fas signal - bit 8 ye s 2 fas signal - bit 7 ye s 3 fas signal - bit 6 ye s 4 fas signal - bit 5 ye s 5 fas signal - bit 4 ye s 6 fas signal - bit 3 ye s 7 fas signal - bit 2 ye s 8 fas signal - bit 1 ye s 9 fas signal - bit 0 ye s 10 a bit ye s 11 n bit ye s XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 265 in figure 114 the terminal equipment samples the txohframe signal being "high" at rising clock edge # 0. from this point, the terminal equipment will wait until it has detected the 10th rising edge of the txo- hclk signal. at this point, the terminal equipment knows that the XRT72L50 is just about to process the a bit within a given outbound e3 frame. additionally, according to table 49, the 10th overhead bit to be processed is the "a" bit. in order to facilitate the transmission of the yellow alarm, the terminal equip- ment must set this "a" bit to "1". hence, the terminal equipment starts this process by implementing the following steps concurrently. a. assert the txohins input pin by setting it "high". b. set the txoh input pin to "1". after the terminal equipment has applied these sig- nals, the XRT72L50 will sample the data on both the txohins and txoh signals upon the very next falling edge of txohclk (designated as "10-" in figure 114). once the XRT72L50 has sampled this data, it will then insert a "1" into the "a" bit position, in the out- bound e3 frame. upon detection of the very next rising edge of the tx- ohclk clock signal (designated as clock edge 1 in figure 114, the terminal equipment will negate the txohins signal (e.g., toggles it "low") and will cease inserting data into the transmit overhead data input interface. after the terminal equipment has performed this in- sertion procedure, it leaves the remaining overhead bits (within this particular outbound e3 frame) in-tact, by terminating this overhead bit insertion proce- dure. the terminal equipment should now terminate this overhead bit insertion, by doing the following. a. assert the txohins input pin by setting it "high". b. set the txoh input to "0". if the terminal equipment wishes to continue its transmission of the yellow alarm condition to the re- mote terminal equipment, then it should resume the overhead bit insertion procedure (as described above), at the beginning of each outbound e3 frame (or each time txohframe is sampled "high). 5.2.2.2 method 2 - using the txinclk and txo- henable signals method 1 requires the use of an additional clock sig- nal, txohclk. however, there may be a situation in which the user does not wish to add this extra clock signal to their design, in order to use the transmit overhead data input interface. hence, method 2 is f igure 114. i llustration of the signal that must occur between the t erminal e quipment and the XRT72L50 in order to configure the XRT72L50 to transmit a y ellow a larm to the remote terminal equipment terminal equipment/xrt72l5x interface signals txohclk txohins txohframe txoh remaining overhead bits with e3 frame a bit = 1 txohframe is sampled high terminal equipment asserts txohins and data on txoh line. 0 1 4 5 6 7 8 9 10 10- xrt72l5x framer device samples txoh and txohins signals ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 266 available. when using method 2, either the txinclk or rxoutclk signal is used to sample the overhead bits and signals which are input to the transmit over- head data input interface. method 2 involves the use of the following signals: ? txoh ? txinclk ? txohframe ? txohenable each of these signals are listed and described in table 50. interfacing the transmit overhead data input interface to the terminal equipment figure 115 illustrates how one should interface the transmit overhead data input interface to the termi- nal equipment when using method 2. t able 50: d escription of m ethod 2 t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohen- able output transmit overhead data enable output pin the XRT72L50 will assert this signal, for one txinclk period, just prior to the instant that the transmit overhead data input interface is processing an overhead bit. txo- hframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L50 is processing the last bit within a given ds3 frame. txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input inter- face to accept overhead data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of the txinclk output signal. conversely, setting this pin "low" configures the transmit overhead data input interface to not sample (e.g., ignore) the data at the txoh input pin, on the falling edge of the txohclk output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the transmit overhead data input interface (e.g., if the terminal equipment asserts the txohins signal, at a time when one of these non-insertable overhead bits are being processed), that par- ticular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the overhead bit position within the very next outbound ds3 frame. if the txohins pin is pulled "high", the transmit overhead data input interface will sample the data at this input pin (txoh), on the falling edge of the txohclk output pin. conversely, if the txohins pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 267 method 2 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the outbound e3 data stream (via the transmit overhead data input interface), then it is ex- pected to do the following. 1. to sample the state of both the txohframe and the txohenable input signals, via the e3_clock_in (e.g., either the txinclk or the rxoutclk signal of the XRT72L50) signal. if the terminal equipment samples the txohenable signal "high", then it knows that the XRT72L50 is about to process an overhead bit. further, if the terminal equipment samples both the txo- hframe and the txohenable pins "high" (at the same time) then the terminal equipment knows that the XRT72L50 is about to process the first overhead bit, within a new e3 frame. 2. to keep track of the number of times that the txohenable signal has been sampled "high" since the last time both the txohframe and the txohenable signals were sampled "high". by doing this, the terminal equipment will be able to keep track of which overhead bit the transmit overhead data input interface is about ready to process. from this, the terminal equipment will know when it should assert the txohins input pin and place the appropriate value on the txoh input pins of the XRT72L50. table 51 also relates the number of txohenable out- put pulses (that have occurred since both the txo- hframe and txohenable pins were sampled "high") to the e3 overhead bit, that is being processed. f igure 115. i llustration of the t erminal e quipment being interfaced to the t ransmit o verhead d ata i nput i nterface (m ethod 2) terminal equipment xrt72l5x e3 framer e3_oh_out e3_oh_enable tx_start_of_frame txohenable txohframe txohins 34.368 mhz clock source txinclk txoh insert_oh rxlineclk 34.368 mhz clock source e3_clock_in ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 268 3. after the terminal equipment has waited through the appropriate number of pulses via the txo- henable pin, it should then assert the txohins input signal. concurrently, the terminal equip- ment should also place the appropriate value (of the inserted overhead bit) onto the txoh signal. 4. the terminal equipment should hold both the txohins input pin "high" and the value of the txoh signal stable, until the next txohenable pulse is detected. case study: the terminal equipment intends to insert the appropriate overhead bits into the transmit overhead data input interface (using method 2) in order to transmit a yellow alarm to the remote terminal equipment. in this case, the terminal equipment intends to insert the appropriate overhead bits, into the transmit over- head data input interface such that the XRT72L50 will transmit a yellow alarm to the remote terminal equipment. recall that, for e3, itu-t g.751 applica- tions, a yellow alarm is transmitted by setting the a bit to 1". if one assumes that the connection between the ter- minal equipment and the XRT72L50 is as illustrated in figure 115 then, figure 116 presents an illustration of the signaling that must go on between the terminal equipment and the XRT72L50. t able 51: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the e3 o verhead b it , that is being processed by the XRT72L50 n umber of t x ohe nable p ulses t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? 0 (clock edge is coincident with txo- hframe being detected "high) fas signal - bit 9 ye s 1 fas signal - bit 8 ye s 2 fas signal - bit 7 ye s 3 fas signal - bit 6 ye s 4 fas signal - bit 5 ye s 5 fas signal - bit 4 ye s 6 fas signal - bit 3 ye s 7 fas signal - bit 2 ye s 8 fas signal - bit 1 ye s 9 fas signal - bit 0 ye s 10 a bit ye s 11 n bit ye s XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 269 5.2.3 the transmit e3 hdlc controller the transmit e3 hdlc controller block can be used to transport message-oriented signaling (mos) type messages to the remote terminal equipment as dis- cussed in detail below. 5.2.3.1 message-oriented signaling (e.g., lap-d) processing via the transmit ds3 hdlc controller the lapd transmitter (within the transmit e3 hdlc controller block) allows the user to transmit path maintenance data link (pmdl) messages to the re- mote terminal via the outbound e3 frames. in this case the message bits are inserted into and carried by the n bit, within the outbound e3 frames. the on-chip lapd transmitter supports both the 76 byte and 82 byte length message formats, and the framer ic allocates 88 bytes of on-chip ram (e.g., the trans- mit lapd message buffer) to store the message to be transmitted. the message format complies with itu- t q.921 (lap-d) protocol with different addresses and is presented below in figure 117 . f igure 116. b ehavior of t ransmit o verhead d ata i nput i nterface signals between the XRT72L50 and the t erminal e quipment ( for m ethod 2) txinclk txohframe txohenable txohins txoh terminal equipment samples txohframe and txohenable being high terminal equipment counts the number of txohenable pulses. at pulse # 10 the terminal equipment asserts the txohins signal and places the desired data on txoh. xrt72l5x samples txoh here. txohenable pulse # 10 a bit = 1 txohenable pulse # 0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 270 where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the following sections defines each of these bit/byte- fields within the lapd message frame format. flag sequence byte the flag sequence byte is of the value 0x7e, and is used to denote the boundaries of the lapd message frame. sapi - service access point identifier the sapi bit-fields are assigned the value of "001111b" or 15 (decimal). tei - terminal endpoint identifier the tei bit-fields are assigned the value of 0x00. the tei field is used in n-isdn systems to identify a terminal out of multiple possible terminal. however, since the framer ic transmits data in a point-to-point manner, the tei value is unimportant. control the control identifies the type of frame being trans- mitted. there are three general types of frame for- mats: information, supervisory, and unnumbered. the framer assigned the control byte the value 03h. hence, the framer will be transmitting and receiving unnumbered lapd message frames. information payload the information payload is the 76 bytes or 82 bytes of data (e.g., the pmdl message) that the user has writ- ten into the on-chip transmit lapd message buffer (which is located at addresses 0x86 through 0xdd). it is important to note that the user must write in a specific octet value into the first byte position within the transmit lapd message buffer (located at ad- dress = 0x86, within the framer). the value of this octet depends upon the type of lapd message frame/pmdl message that the user wishes to trans- mit. table 52 presents a list of the various types of lapd message frames/pmdl messages that are supported by the XRT72L50 framer device and the corresponding octet value that the user must write in- to the first octet position within the transmit lapd message buffer. f igure 117. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) t able 52: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i nformation p ayload lapd m essage t ype v alue of f irst b yte , within i nformation p ayload of m essage m essage s ize cl path identification 0x38 76 bytes idle signal identification 0x34 76 bytes test signal identification 0x32 76 bytes itu-t path identification 0x3f 82 bytes XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 271 frame check sequence bytes the 16 bit fcs (frame check sequence) is calculat- ed over the lapd message header and information payload bytes, by using the crc-16 polynomial, x 16 + x 12 + x 5 + 1. operation of the lapd transmitter if the user wishes to transmit a message via the lapd transmitter, the information portion (or the body) of the message must be written into the trans- mit lapd message buffer, which is located at 0x86 through 0xdd in on-chip ram via the microprocessor interface. afterwards, the user must do five things: 1. configure the source of the n bit (within each outbound e3 frame, to be the lapd transmitter. 2. specify the length of lapd message to be trans- mitted. 3. specify whether the lapd transmitter should transmit this lapd message frame only once, or an indefinite number of times at one-second intervals. 4. enable the lapd transmitter. 5. initiate the transmission of the pmdl message. each of these steps will be discussed in detail. step 1 - configure the source of the n bit (with- in each outbound e3 frame, to be the lapd trans- mitter. this is accomplished by writing the appropriate data into the txnsourcesel[1:0] bit-fields, within the txe3 configuration register, as illustrated below. setting txnsourcesel[1:0] to 10 configures the transmit e3 framer block to use the lapd transmit- ter as the data source for the n bits. hence, the n bit, (within each outbound e3 frame) is now carrying lapd messages to the remote terminal equipment. step 2 - specify the type of lapd message frame to be transmitted (within the transmit lapd mes- sage buffer) the user must write in a specific octet value into the first octet position within the transmit lapd buffer (e.g., at address location 0x86 within the framer ic). this octet is referred to as the lapd message frame id octet. the value of this octet must correspond to the type of lapd message frame that is desired to be transmitted. this octet will ultimately be used by the remote terminal equipment in order to help it identify the type of lapd message frame that it is receiving. table 53 lists these octets and the corresponding lapd message types. step 3 - write the pmdl message into the re- maining part of the transmit lapd message buff- er. the user must now write in his/her pmdl message into the remaining portion of the transmit lapd mes- sage buffer (e.g., addresses 0x87 through 0x135 within the framer ic). step 4 - specifying the length of the lapd mes- sage one of two different sizes of lapd messages can be transmitted. this can be accomplished by writing the appropriate data to bit 1 within the tx e3 lapd con- figuration register. the bit-format of this register is presented below. txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w 00000000 transmit e3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0000x0 xx ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 272 the relationship between the contents of bit-fields 1 and the lapd message size is given in table 53. n ote : the message type selected must correspond with the contents of the first byte of the information (payload) portion, as presented in table 52. step 5 - specify whether the lapd transmitter should transmit the lapd message frame only once, or an indefinite number of times at one-sec- ond intervals. the transmit e3 hdlc control block allows the user to configure the lapd transmitter to transmit this lapd message frame only once, or an indefinite number of times at one-second intervals. the user implements this configuration by writing the appropri- ate value into bit 3 (auto retransmit) within the tx e3 lapd configuration register (address = 0x33), as depicted below. ) if the user writes a 1 into this bit-field, then the lapd transmitter will transmit the lapd message frame repeatedly at one-second intervals until the lapd transmitter is disabled. if the user writes a 0 into this bit-field, then the lapd transmitter will transmit the lapd message frame only once. afterwards, the lapd transmitter will halt its transmission until the user invokes the transmit lapd message frame command, once again. step 5 - enabling the lapd transmitter prior to the transmission of any data via the lapd transmitter, the lapd transmitter must be enabled. this is accomplished by writing a "1" to bit 0 (txlapd enable) of the tx e3 lapd configuration register, as depicted below. if the user writes a 0 into this bit-field, then the lapd transmitter will be enabled, and the lapd transmitter will immediately begin to transmit a con- tinuous stream of flag sequence octets (0x7e), via the n bit-field of each outbound e3 frame. conversely, if the user writes a 1 into this bit-field, then the lapd transmitter will be disabled. the transmit e3 framer block will automatically insert a 1 into the n bit-field, within each outbound e3 frame. no transmission of pmdl data will occur. step 7 - initiate the transmission at this point, the user should have written the pmdl message into the on-chip transmit lapd message buffer and the type of lapd message that is desired to be transmitted should have been specified. finally, t able 53: r elationship between t x lapd m sg l ength and the lapd m essage s ize t x lapd m essage l ength lapd m essage l ength 0 lapd message size is 76 bytes 1 lapd message size is 82 bytes txe3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable ro ro ro ro r/w ro r/w r/w 00001000 transmit e3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o e/o r/w r/o r/w r/w 0000x0x 1 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 273 the user should have enabled the lapd transmitter. the only remaining to do is initiate the transmission of this message. this process is initiated by writing a 1 to bit 3 (tx dl start) within the tx e3 lapd sta- tus and interrupt register (address = 0x34), as de- picted below. ) a 0 to 1 transition in bit 3 (tx dl start) in this reg- ister, initiates the transmission of lapd message frames. at this point, the lapd transmitter will begin to search through the pmdl message, which is resid- ing within the transmit lapd message buffer. if the lapd transmitter finds any string of five (5) consecu- tive 1s in the pmdl message then the lapd trans- mitter will insert a 0 immediately following these strings of consecutive 1s. this procedure is known as stuffing. the purpose of pmdl message stuffing is to insure that the users pmdl message does not contain strings of data that mimic the flag sequence octet (e.g., six consecutive 1s) or the abort se- quence octet (e.g., seven consecutive 1s). after- wards, the lapd transmitter will begin to encapsu- late the pmdl message, residing in the transmit lapd message buffer, into a lapd message frame. finally, the lapd transmitter will fragment the out- bound lapd message frame into bits and will begin to transport these bits via the n bit-field within each outbound e3 frame. while the lapd transmitter is transmitting this lapd message frame, the txdl busy bit-field (bit 2) within the tx e3 lapd status and interrupt register, will be set to 1. this bit-field allows the user to poll the sta- tus of the lapd transmitter. once the lapd trans- mitter has completed the transmission of the lapd message, then this bit-field will toggle back to 0. the user can configure the lapd transmitter to inter- rupt the local microprocessor/microcontroller upon completion of transmission of the lapd message frame, by setting bit-field 1 (txlapd interrupt en- able) within the tx e3 lapd status and interrupt reg- ister (address = 0x34). to 1 as depicted below. ) the purpose of t his interrupt is to let the micropro- cessor/microcontroller know that the lapd transmit- ter is available and ready to transmit a lapd mes- sage frame (which contains a new pmdl message) to the remote terminal equipment. bit 0 (tx lapd in- terrupt status) within the tx e3 lapd status and in- terrupt register will reflect the status for the transmit lapd interrupt. n ote : this bit-field will be reset upon reading this register. summary of operating the lapd transmitter once the user has invoked the txdl start command, the lapd transmitter will do the following. ? generate the four octets of the lapd message frame header (e.g., the flag sequence, sapi, tei, control, etc.,) and insert them into the header byte positions within the lapd message frame. ? it will read in the contents of the transmit lapd message buffer (e.g., the pmdl message data) and insert it into the information payload portion of the lapd message frame. txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 0000xx1x ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 274 ? compute the 16-bit frame check sequence (fcs) value of the lapd message frame (e.g, of the lapd message header and payload bytes) and insert this value into the fcs value octet positions within the lapd message frame. ? append a trailer flag sequence octet to the end of the lapd message frame (following the 16-bit fcs octets). ? fragment the resulting lapd message frame into bits and begin inserting these bits into the n bit- field within each outbound e3 frame. ? complete the transmission of the overhead bytes, information payload byte, fcs value, and the trail- ing flag sequence octets via the transmit e3 framer block. once the lapd transmitter has completed its trans- mission of the lapd message frame, the framer will generate an interrupt to the microprocessor/micro- controller (if enabled). afterwards, the lapd trans- mitter will either halt its transmission of lapd mes- sage frames or will proceed to retransmit the lapd message frame, repeatedly at one-second intervals. in between these transmissions of the lapd mes- sage frames, the lapd transmitter will be sending a continuous stream of flag sequence bytes. the lapd transmitter will continue this behavior until the user has disabled the lapd transmitter by writing a 1 into bit 3 (no data link) within the tx e3 configu- ration register. n ote : in order to prevent the users data (e.g., the pmdl message within the lapd message frame) from mimicking the flag sequence byte or an abort sequence, the lapd transmitter will parse through the pmdl message data and insert a 0 into this data, immediately following the detec- tion of five (5) consecutive 1s (this stuffing occurs while the pmdl message data is being read in from the transmit lapd message frame. the remote lapd receive (see section 4.3.5) will have the responsibility of checking the newly received pmdl messages for a string of five (5) con- secutive 1s and removing the subsequent 0 from the payload portion of the incoming lapd message. figure 118 presents a flow chart diagram. figure 118 depicts the procedure (in white boxes) that the user should use in order to transmit a pmdl message via the lapd transmitter, when the lapd transmitter is configured to retransmit the lapd mes- sage frame, repeatedly at one-second intervals. this figure also indicates (via the shaded boxes) what the lapd transmitter circuitry will do before and during message transmission. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 275 n ote : in figure 118, the unshaded boxes depict the tasks that the user must perform. the shaded boxes present the resulting tasks that the transmit hdlc controller block will perform. the mechanics of transmitting a new lapd mes- sage frame, if the lapd transmitter has been configured to re-transmit the lapd message frame, repeatedly, at one-second intervals. if the lapd transmitter has been configured to re- transmit the lapd message frame repeatedly at one- second intervals, then it will do the following (at one- second intervals). ? stuff the pmdl message. ? read in the stuffed pmdl message from the trans- mit lapd message buffer. ? encapsulate this stuffed pmdl message into a lapd message frame. ? transmit this lapd message frame to the remote terminal equipment. if another (e.g., a different) pmdl message is to be transmitted to the remote terminal equipment, this new message will have to be written into the transmit lapd message buffer, via the microprocessor inter- face block of the framer ic. however, care must be taken when writing this new pmdl message. if this message is written into the transmit lapd message buffer at the wrong time (with respect to these one- second lapd message frame transmissions), the us- ers action could interfere with these transmissions, thereby causing the lapd transmitter to transmit a corrupted message to the remote terminal equip- ment. in order to avoid this problem, while writing the new message into the transmit lapd message buff- er, the user should do the following. 1. configure the framer to automatically reset acti- vated interrupts. the user can do this by writing a 1 into bit 3 within the framer operating mode register (address = 0x00), as depicted below. f igure 118. f low c hart d epicting how to use the lapd t ransmitter start start write in data link information the user accomplishes this by writing the information that he/she wishes to transmit (via the lapd transmitter) to locations 0x86through 0xdd, within the framer address space. enable the lapd transmitter for transmission this is accomplished by writing 00000xx1bto the tx e3 lapd configuration register.(where xx dictates lapd message type) lapd transmitter inserts frame header octets in front of the user payload. lapd transmitter computes the 16 bit fcs (a crc-16 value) and inserts it into the lapd message, following the user payload lapd transmitter appends a flag sequence trailer octet to the end of the lapd message (after the 16 bit fcs). is 5 consecutive 1s detected ? is message transmission complete ? insert a 0 after the string of 5 consecutive 1s end generate interrupt lapd transmitter will continue to transmit flag sequence octets. initiate transmission of lapd message this is accomplished by writing 000010x0bto the tx e3 lapd status/interruptregister. (where x indicates the users choiceto enable/disable lapd message transfer complete interrupt yes no yes no configure the n-bit to carrylapd messages this is accomplished by setting txnsourcesel[1:0] = 1, 0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 276 this action will prevent the lapd transmitter from generating its own one-second interrupt (following each transmission of the lapd message frame). 2. enable the one-second interrupt this can be done by writing a 1 into bit 0 (one-sec- ond interrupt enable) within the block interrupt en- able register, as depicted below. 3. write the new message into the transmit lapd message buffer immediately after the occurrence of the one-second interrupt by synchronizing the writes to the transmit lapd message buffer to occur immediately after the occur- rence of the one-second interrupt, the user avoids conflicting with the one-second transmission of the lapd message frame, and will transmit the correct (uncorrupted) pmdl message to the remote lapd receiver. framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 011 block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one-second interrupt enable r/wrororororor/wr/w 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 277 5.2.4 the transmit e3 framer block 5.2.4.1 brief description of the transmit e3 framer the transmit e3 framer block accepts data from any of the following four sources, and uses it to form the e3 data stream. ? the transmit payload data input block ? the transmit overhead data input block ? the transmit hdlc controller block ? the internal overhead data generator the manner in how the transmit e3 framer block handles data from each of these sources is described below. handling of data from the transmit payload data input interface for e3 applications, all data that is input to the trans- mit payload data input interface will be inserted into the payload bit positions within the outbound e3 frames. handling of data from the internal overhead bit generator by default, the transmit e3 framer block will internal- ly generate the overhead bytes. however, if the ter- minal equipment inserts its own values for the over- head bits or bytes (via the transmit overhead data input interface) or if the user enables and employs the transmit e3 hdlc controller block, then these in- ternally generated overhead bytes will be overwritten. handling of data from the transmit overhead da- ta input interface for e3 applications, the transmit e3 framer block au- tomatically generates and inserts the framing align- ment bytes (e.g., the 10 bit fas framing alignment signal) into the outbound e3 frames. hence, the transmit e3 framer block will not accept data from the transmit oh data input interface block for the fas signal. however, the transmit e3 framer block will accept (and insert) data from the transmit overhead data in- put interface for both the a and n bit-fields. if the user's local data link equipment activates the transmit overhead data input interface block and writes data into this interface for these bits or bytes, then the transmit e3 framer block will insert this data into the appropriate overhead bit/byte-fields, within the outbound e3 frames. handling of data from the transmit hdlc control- ler block the exact manner in how the transmit e3 framer handles data from the transmit hdlc controller block depends upon whether the transmit hdlc controller is activated or not. if the transmit ds3 hdlc controller block is not activated, then the transmit e3 framer block will insert a 1 into each n bit-field, within each outbound e3 frame. if the transmit e3 hdlc controller block is activated, then data will be inserted into the n bit-fields as de- scribed in section 4.2.3. 5.2.4.2 detailed functional description of the transmit e3 framer block the transmit e3 framer receives data from the fol- lowing three sources and combines them together to form the e3 data stream. ? the transmit payload data input interface block. ? the transmit overhead data input interface block ? the transmit hdlc controller block. ? the internal overhead data generator. afterwards, this e3 data stream will be routed to the transmit e3 liu interface block, for further process- ing. figure 119 presents a simple illustration of the trans- mit e3 framer block, along with the associated paths to the other functional blocks within the chip. ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 278 in addition to taking data from multiple sources and multiplexing them, in appropriate manner, to create the outbound e3 frames, the transmit e3 framer block has the following roles. ? generating alarm conditions ? generating errored frames (for testing purposes) ? routing outbound e3 frames to the transmit e3 liu interface block each of these additional roles are discussed below. 5.2.4.2.1 generating alarm conditions the transmit e3 framer block permits the user to, by writing the appropriate data into the on-chip registers, to override the data that is being written into the transmit payload data and overhead data input in- terfaces and transmit the following alarm conditions. ? generate the yellow alarms (or ferf indicators) ? manipulate the a-bit, by forcing it to 0. ? generate the ais pattern ? generate the los pattern ? generate ferf (yellow) alarms, in response to detection of a red alarm condition (via the receive section of the XRT72L50). the procedure and results of generating any of these alarm conditions is presented below. the user can exercise each of these options by writ- ing the appropriate data to the tx e3 configuration register (address = 0x30). the bit format of this reg- ister is presented below. bit-fields 1 and 2 permit the user to transmit various alarm conditions to the remote terminal equipment. the role/function of each of these two bit-fields within the register, are discussed below. 5.2.4.2.1.1 tx ais enable - bit 2 this read/write bit field permits the user to force the transmission of an ais (alarm indication signal) pat- tern to the remote terminal equipment via software control. if the user opts to transmit an ais pattern, then the transmit section of the framer ic will begin to transmit an unframed all ones pattern to the re- mote terminal equipment. table 54 presents the rela- tionship between the contents of this bit-field, and the resulting framer action. f igure 119. a s imple i llustration of the t ransmit e3 f ramer b lock and the associated paths to other f unctional b locks transmit e3 framer block transmit e3 framer block transmit hdlc controller/buffer transmit overhead data input interface transmit payload data input interface to transmit e3 liu interface block txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 279 n ote : this bit is ignored whenever the txlos bit-field is set. 5.2.4.2.1.2 transmit los enable - bit 1 this read/write bit field allows the user to transmit an los (loss of signal) pattern to the remote terminal, upon software control. table 55 relates the contents of this bit field to the transmit e3 framer block's ac- tion. n ote : when this bit is set, it overrides all of the other bits in this register. 5.2.4.2.1.3 transmitting ferf (far-end receive failure) indicator or yellow alarm the XRT72L50 framer ic permits the user to control the state of the a bit-field, within each outbound e3 frame. this can be achieved by writing the appropri- ate data into the txasource[1:0] bit-fields within the tx e3 configuration register, as illustrated below. the following table presents the relationship between the contents of txasource[1:0] and the resulting source of the a bit. t able 54: t he r elationship between the contents of b it 2 (t x ais e nable ) within the t x e3 c onfiguration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction b it 2t ransmit e3 f ramer ' s a ction 0 normal operation: the transmit section of the XRT72L50 framer ic will transmit e3 traffic based upon data that it accepts via the transmit payload data input interface block, the transmit overhead data input interface block, the trans- mit hdlc controller block and internally generated overhead bytes. 1 transmit ais pattern: the transmit e3 framer block will overwrite the e3 traffic, within an unframed all ones pattern. t able 55: t he r elationship between the contents of b it 1 (t x los) within the t x e3 c onfiguration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction b it 1t ransmit e3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the transmit overhead data input interface or the transmit hdlc controller blocks. the payload bits are received from the transmit payload data input interface. 1 transmit los pattern: when this command is invoked the transmit e3 framer will do the following. ? set all of the overhead bytes to "0" (including the fa1 and fa2 bytes) overwrite the e3 payload bits with an "all zeros" pattern. txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w 0xx00000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 280 hence, if a yellow alarm condition needs to be trans- mitted to the remote terminal equipment, this can be accomplished by executing the following steps. step 1 - write a 1 into bit 1 (a bit) within the tx e3 service bits register, as indicated below. step 2 - write the value 00 into the txas- ource[1:0] bit-fields within the tx e3 configura- tion register, as indicated below. these two steps will cause the transmit e3 framer block to read in the contents of bit 1 (within the tx e3 service bit register) and insert it into the a bit-field within the outbound e3 data stream. hence, the a bit will be set to 1, which will be interpreted as an alarm condition, by the remote terminal equipment. 5.2.4.2.2 configuring the transmit e3 framer block to insert the bip-4 nibble into each out- bound e3 frame. the XRT72L50 framer ic permits the user to (1) con- figure the transmit section of the device to insert the bip-4 value into each outbound e3 frame and (2) to configure the receive section of the device to com- pute and verify the bip-4 value, within each inbound e3 frame. these two configurations are accomplished by setting bit 7 (tx bip-4 enable), within the tx e3 configura- tion register, to 1, as indicated below. t x as ource s el [1:0] s ource of a b it 00 txe3 service bits register (address = 0x35) 01 transmit overhead data input interface 10 transmit payload data input interface 11 functions as a febe (far-end-block error) bit-field. this bit-field is set to "0", if the near-end receive section (within this chip) detects no bip-4 errors within the incoming e3 frames. this bit-field is set to "1", if the near-end receive section (within this chip) detects a bip-4 error within the incoming e3 frame. txe3 service bits register (address = 0x35) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used a bit n bit ro ro ro ro ro ro r/w r/w 00000010 txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w x00xx x x x XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 281 setting this bit-field to 1 accomplishes the following. ? it configures the transmit e3 framer block to com- pute the bip-4 value of a given e3 frame, and insert in to the very last nibble, within the very next out- bound e3 frame. (hence, bits 1533 through 1536, within each e3 frame, will function as the bip-4 value) ? it configures the receive e3 framer block to com- pute and verify the bip-4 value of each incoming e3 frame. 5.2.4.2.3 generating errored e3 frames the transmit e3 framer block permits the user to in- sert errors into the framing and error detection over- head bites (e.g., the fas pattern, and the bip-4 nib- ble) of the outbound e3 data stream in order to sup- port remote terminal equipment testing. the user can exercise this option by writing data into any of the following registers. ? txe3 fas error mask register - 0 ? txe3 fas error mask register - 1 ? txe3 bip-4 error mask register inserting errors into the fas pattern of the out- bound e3 frames. the user can insert errors into the fas pattern bits, of each outbound e3 frame, by writing the appropriate data into either the txe3 fas error mask register - 0 or txe3 fas error mask register - 1. as the transmit e3 framer block formulates the out- bound e3 frames, the contents of the fas pattern bits are automatically xored with the contents of these two registers. the results of this xor operation is written back into the corresponding bit-field within the outbound e3 frame, and is transmitted to the remote terminal equipment. therefore, if the user does not wish to modify any of these bits, then these registers must contain all 0s (the default value). inserting errors into the bip-4 nibble, within each outbound e3 frame. the user can insert errors into the bip-4 nibble, within each outbound e3 frame, by writing the appropriate data into the txe3 bip-4 error mask register. txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w 1xxxxxxx txe3 fas error mask register - 0 (address = 0x48) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txfas_error_mask_upper[4:0] ro ro ro r/w r/w r/w r/w r/w 0 0 0xxxxx txe3 fas error mask register - 1 (address = 0x49) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txfas_error_mask_lower[4:0] ro ro ro r/w r/w r/w r/w r/w 0 0 0xxxxx ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 282 as the transmit e3 framer block formulates the out- bound e3 frames, the contents of the bip-4 bits are automatically xored with the contents of this regis- ter. the results of this xor operation is written back into the corresponding bit-field within the outbound e3 frame, and is transmitted to the remote terminal equipment. therefore, if the user does not wish to modify any of these bits, then this register must con- tain all 0s (the default value). n ote : this register is only active if the XRT72L50 framer ic has been configured to insert the bip-4 nibble into each outbound e3 frame. 5.2.5 the transmit e3 line interface block the XRT72L50 framer ic is a digital device that takes e3 payload and overhead bit information from some terminal equipment, processes this data and ul- timately, multiplexes this information into a series of outbound e3 frames. however, the XRT72L50 fram- er ic lacks the current drive capability to be able to di- rectly transmit this e3 data stream through some transformer-coupled coax cable with enough signal strength for it to be received by the remote receiver. therefore, in order to get around this problem, the framer ic requires the use of an liu (line interface unit) ic. an liu is a device that has sufficient drive capability, along with the necessary pulse-shaping circuitry to be able to transmit a signal through the transmission medium in a manner that it can be reli- ably received by the far-end receiver. figure 120 pre- sents a circuit drawing depicting the framer ic inter- facing to an liu (xrt7300 ds3/e3/sts-1 transmit liu). txe3 bip-4 error mask register (address = 0x4a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txbip-4 mask[3:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 f igure 120. a pproach to i nterfacing the XRT72L50 f ramer ic to the xrt73l00 ds3/e3/sts-1 liu 5v u1 x r t7250 tx p o s 65 tx n e g 64 txlinec lk 63 dmo 79 e xtlos 78 rlol 77 lloop 69 rloop 70 ta o s 68 tx le v 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 tx s e r 46 tx inc l k 43 tx frame 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 x r t7300 tp d a ta 37 tn d a ta 38 tc lk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tr i n g 40 mtip 44 mr in g 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 ta o s 2 tx le v 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 tx s e r tx inc l k nibbleintf resetb rtip rring csb rw ds as tx f rame rxser rxclk rxfra me rxlos rxoof rxred rxais a[8:0] tr i n g ttip intb d[7:0] intb XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 283 the transmit section of the XRT72L50 contains a block which is known as the transmit e3 liu interface block. the purpose of the transmit e3 liu interface block is to take the outbound e3 data stream, from the transmit e3 framer block, and to do the following: 1. encode this data into one of the following line codes a. unipolar (e.g., single-rail) b. ami (alternate mark inversion) c. hdb3 (high density bipolar - 3) 2. and to transmit this data to the liu ic. figure 121 presents a simple illustration of the trans- mit e3 liu interface block. the transmit e3 liu interface block can transmit data to the liu ic or other external circuitry via two differ- ent output modes: unipolar or bipolar. if the user se- lects unipolar (or single rail) mode, then the con- tents of the e3 frame is output, in a binary (nrz manner) data stream via the txpos pin to the liu ic. the txneg pin will only be used to denote the frame boundaries. txneg will pulse "high" for one bit peri- od, at the start of each new e3 frame, and will remain "low" for the remainder of the frame. figure 122 pre- sents an illustration of the txpos and txneg signals during data transmission while the transmit e3 liu interface block is operating in the unipolar mode. this mode is sometimes referred to as single rail mode because the data pulses only exist in one po- larity: positive. f igure 121. a s imple i llustration of the t ransmit e3 liu i nterface block from transmit e3 framer block txpos txneg txlineclk transmit e3 liu interface block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 284 when the transmit e3 liu interface block is operating in the bipolar (or dual rail) mode, then the contents of the e3 frame is output via both the txpos and tx- neg pins. if the bipolar mode is chosen, then e3 da- ta can be transmitted to the liu via one of two differ- ent line codes: alternate mark inversion (ami) or high density bipolar -3 (hdb3). each one of these line codes will be discussed below. bipolar mode is sometimes referred to as dual rail because the data pulses occur in two polarities: positive and negative. the role of the txpos, txneg and txlineclk output pins, for this mode are discussed below. txpos - transmit positive polarity pulse: the transmit e3 liu interface block will assert this output to the liu ic when it desires for the liu to generate and transmit a positive polarity pulse to the remote terminal equipment. txneg - transmit negative polarity pulse: the transmit e3 liu interface block will assert this output to the liu ic when it desires for the liu to generate and transmit a negative polarity pulse to the remote terminal equipment. txlineclk - transmit line clock: the liu ic uses this signal from the transmit e3 liu interface block to sample the state of its txpos and txneg inputs. the results of this sampling dictates the type of pulse (positive polarity, zero, or negative polarity) that it will generate and transmit to the remote receive e3 framer. 5.2.5.1 selecting the various line codes the user can select either the unipolar mode or bipo- lar mode by writing the appropriate value to bit 3 of the i/o control register (address = 0x01), as shown below. table 56 relates the value of this bit field to the trans- mit e3 liu interface output mode. f igure 122. t he b ehavior of t x pos and t x neg signals during data transmission while the t ransmit ds3 liu i nterface is operating in the u nipolar m ode txpos txneg txlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 frame boundary i/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 56: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c ontrol r egister and the t ransmit e3 f ramer l ine i nterface o utput m ode b it 3t ransmit e3 f ramer liu i nterface o utput m ode 0 bipolar mode: ami or hdb3 line codes are transmitted and received 1 unipolar (single rail) mode of transmission and reception of e3 data is selected. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 285 n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the operation of the receive e3 liu interface block 5.2.5.1.1 the bipolar mode line codes if the framer is choosen to operate in the bipolar mode, then the ds3 data-stream can be choosen to be transmitted via the ami (alternate mark inversion) or the hdb3 line codes. the definition of ami and hdb3 line codes follow. 5.2.5.1.1.1 the ami line code ami or alternate mark inversion, means that consec- utive "one's" pulses (or marks) will be of opposite po- larity with respect to each other. the line code in- volves the use of three different amplitude levels: +1, 0, and -1. +1 and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" ampli- tude pulses (or the absence of a pulse) are used to represent zeros (or space) pulses. the general rule for ami is: if a given mark pulse is of positive polarity, then the very next mark pulse will be of negative po- larity and vice versa. this alternating-polarity rela- tionship exists between two consecutive mark pulses, independent of the number of 'zeros' that may exist between these two pulses. figure 123 presents an il- lustration of the ami line code as would appear at the txpos and txneg pins of the framer, as well as the output signal on the line. n ote : one of the main reasons that the ami line code has been chosen for driving transformer-coupled media is that this line code introduces no dc component, thereby minimizing dc distortion in the line. 5.2.5.1.1.2 the hdb3 line code the transmit e3 framer and the associated liu ic combine the data and timing information (originating from the txlineclk signal) into the line signal that is transmitted to the remote receiver. the remote re- ceiver has the task of recovering this data and timing information from the incoming e3 data stream. many clock and data recovery schemes rely on the use of phase locked loop technology. phase-locked-loop (pll) technology for clock recovery relies on transi- tions in the line signal, in order to maintain lock with the incoming e3 data stream. however, pll-based clock recovery scheme, are vulnerable to the occur- rence of a long stream of consecutive zeros (e.g., the absence of transitions). this scenario can cause the pll to lose lock with the incoming e3 data, thereby causing the clock and data recovery process of the receiver to fail. therefore, some approach is needed to insure that such a long string of consecutive zeros can never happen. one such technique is hdb3 en- coding. hdb3 (or high density bipolar - 3) is a form of ami line coding that implements the following rule. in general the hdb3 line code behaves just like ami with the exception of the case when a long string of consecutive zeros occur on the line. any string of 4 consecutive zeros will be replaced with either a "000v" or a "b00v" where "b" refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the ami coding rule). and "v" refers to a bipolar violation pulse (e.g., a pulse with a polarity that vio- lates the alternating polarity scheme of ami.) the de- cision between inserting an "000v" or a "b00v" is made to insure that an odd number of bipolar (b) pulses exist between any two bipolar violation (v) pulses. figure 124 presents a timing diagram that il- lustrates examples of hdb3 encoding. f igure 123. i llustration of ami l ine c ode data txpos txneg line signal 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 286 the user chooses between ami or hdb3 line coding by writing to bit 4 of the i/o control register (address = 0x01), as shown below. table 57 relates the content of this bit-field to the bi- polar line code that e3 data will be transmitted and received at. n otes : 1. this bit is ignored if the unipolar mode is selected. 2. this selection also effects the operation of the receive e3 liu interface block 5.2.5.2 txlineclk clock edge selection the framer also allows the user to specify whether the e3 output data (via txpos and/or txneg output pins) is to be updated on the rising or falling edges of the txlineclk signal. this selection is made by writ- ing to bit 2 of the i/o control register, as depicted be- low. table 58 relates the contents of this bit field to the clock edge of txclk that e3 data is output on the tx- pos and/or txneg output pins. f igure 124. i llustration of two examples of hdb3 e ncoding data txpos txneg txlineclk line signal 000v b00v 101 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 100 0 00 1 1 i/o control register (address = 0x01) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/wr/wr/wr/wr/w 101 00000 t able 57: t he r elationship between b it 4 (ami/ hdb3*) within the i/o c ontrol r egister and the b ipolar l ine c ode that is output by the t ransmit e3 liu i nterface b lock b it 4b ipolar l ine c ode 0 hdb3 1 ami ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 10100 000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 287 n ote : the user will typically make the selection based upon the set-up and hold time requirements of the transmit liu ic. t able 58: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 2r esult 0 rising edge: outputs on txpos and/or txneg are updated on the rising edge of txlineclk. see figure 125 for timing relationship between txlineclk, txpos and txneg signals, for this selection. 1 falling edge: outputs on txpos and/or txneg are updated on the falling edge of txlineclk. see figure 126 for timing relationship between txlineclk, txpos and txneg signals, for this selection. f igure 125. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the rising edge of t x l ine c lk txlineclk txpos txneg t32 t30 t33 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 288 5.2.6 transmit section interrupt processing the transmit section of the XRT72L50 can generate an interrupt to the microprocessor/microcontroller for the following reasons. ? completion of transmission of lapd message 5.2.6.1 enabling transmit section interrupts the interrupt structure, within the XRT72L50 con- tains two hierarchical levels: ? block level ? source level the block level the enable state of the block level for the transmit section interrupts dictates whether or not interrupts (enabled) at the source level, are actually enabled. the user can enable or disable these transmit sec- tion interrupts, at the block level by writing the appro- priate data into bit 1 (tx ds3/e3 interrupt enable) within the block interrupt enable register (address = 0x04), as illustrated below. setting this bit-field to 1 enables the transmit sec- tion (at the block level) for interrupt generation. conversely, setting this bit-field to 0 disables the transmit section for interrupt generation. what does it mean for the transmit section inter- rupts to be enabled or disabled at the block lev- el? if the transmit section is disabled (for interrupt gener- ation) at the block level, then all transmit section interrupts are disabled, independent of the interrupt enable/disable state of the source level interrupts. if the transmit section is enabled (for interrupt gener- ation) at the block level, then a given interrupt will be enabled at the source level. conversely, if the trans- mit section is enabled (for interrupt generation) at the block level, then a given interrupt will still be disabled, if it is disabled at the source level. as mentioned earlier, the transmit section of the XRT72L50 framer ic contains the completion of transmission of lapd message interrupt. the enabling/disabling and servicing of this interrupt is presented below. f igure 126. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the falling edge of t x l ine c lk txlineclk txpos txneg t31 t32 t33 block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one-second interrupt enable r/wrororororor/wr/w 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 289 5.2.6.1.1 the completion of transmission of the lapd message interrupt if the transmit section interrupts have been enabled at the block level, then the user can enable or disable the completion of transmission of a lapd message interrupt, by writing the appropriate value into bit 1 (txlapd interrupt enable) within the tx e3 lapd status & interrupt register (address = 0x34), as illus- trated below. setting this bit-field to 1 enables the completion of transmission of a lapd message interrupt. con- versely, setting this bit-field to 0 disables the com- pletion of transmission of a lapd message interrupt. 5.2.6.1.2 servicing the completion of trans- mission of a lapd message interrupt as mentioned previously, once the user commands the lapd transmitter to begin its transmission of a lapd message, it will do the following. 1. it will parse through the contents of the transmit lapd message buffer (located at address loca- tions 0x86 through 0xdd) and search for a string of five (5) consecutive 1s. if the lapd trans- mitter finds a string of five consecutive 1s (within the content of the lapd message buffer, then it will insert a 0 immediately after this string. 2. it will compute the fcs (frame check sequence) value and append this value to the back-end of the user-message. 3. it will read out of the content of the user (zero- stuffed) message and will encapsulate this data into a lapd message frame. 4. finally, it will begin transmitting the contents of this lapd message frame via the n bits, within each outbound e3 frame. 5. once the lapd transmitter has completed its transmission of this lapd message frame (to the remote terminal equipment), the XRT72L50 framer ic will generate the completion of trans- mission of a lapd message interrupt to the microcontroller/microprocessor. once the XRT72L50 framer ic generates this interrupt, it will do the following. ? assert the interrupt output pin (int) by toggling it low. ? set bit 0 (txlapd interrupt status) within the txe3 lapd status and interrupt register, to 1 as illus- trated below. the purpose of this interrupt is to alert the microcon- troller/microprocessor that the lapd transmitter has completed its transmission of a given lapd (or pm- dl) message, and is now ready to transmit the next pmdl message, to the remote terminal equipment. 5.3 t he r eceive s ection of the XRT72L50 (e3 m ode o peration ) when the XRT72L50 has been configured to operate in the e3 mode, the receive section of the XRT72L50 consists of the following functional blocks. ? receive liu interface block txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 000000x0 txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000001 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 290 ? receive hdlc controller block ? receive e3 framer block ? receive overhead data output interface block ? receive payload data output interface block figure 127 presents a simple illustration of the re- ceive section of the XRT72L50 framer ic. each of these functional blocks will be discussed in detail in this document. 5.3.1 the receive e3 liu interface block the purpose of the receive e3 liu interface block is two-fold: 1. to receive encoded digital data from the e3 liu ic. 2. to decode this data, convert it into a binary data stream and to route this data to the receive e3 framer block. figure 128 presents a simple illustration of the re- ceive e3 liu interface block. f igure 127. a s imple i llustration of the r eceive s ection of the XRT72L50 configured to operate in the e3 m ode receive payload data input interface block receive ds3/e3 framer block receive liu interface block rxser rxnib[3:0] rxclk rxpos rxneg rxlineclk receive overhead input interface block rxohclk rxohind rxoh rxohenable rxohframe rxframe rx e3 hdlc controller/buffer rx e3 hdlc controller/buffer from microprocessor interface block XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 291 the receive section of the XRT72L50 will via the re- ceive e3 liu interface block receive timing and data information from the incoming e3 data stream. the e3 timing information will be received via the rxli- neclk input pin and the e3 data information will be re- ceived via the rxpos and rxneg input pins. the receive e3 liu interface block is capable of receiving e3 data pulses in unipolar or bipolar format. if the receive e3 framer is operating in the bipolar format, then it can be configured to decode either ami or hdb3 line code data. each of these input formats and line codes will be discussed in detail, below. 5.3.1.1 unipolar decoding if the receive e3 liu interface block is operating in the unipolar (single-rail) mode, then it will receive the single rail nrz ds3 data pulses via the rxpos in- put pin. the receive e3 liu interface block will also receive its timing signal via the rxlineclk signal. n ote : the rxlineclk signal will function as the timing source for the entire receive section of the XRT72L50. no data pulses will be applied to the rxneg input pin. the receive e3 liu interface block receives a logic "1" when a logic "1" level signal is present at the rxpos pin, during the sampling edge of the rxli- neclk signal. likewise, a logic "0" is received when a logic "0" level signal is applied to the rxpos pin. figure 129 presents an illustration of the behavior of the rxpos, rxneg and rxlineclk input pins when the receive e3 liu interface block is operating in the unipolar mode. f igure 128. a s imple i llustration of the r eceive e3 liu i nterface b lock rxpos rxneg rxlineclk to receive e3 framer block receive e3 liu interface block f igure 129. b ehavior of the r x pos, r x neg and r x l ine c lk signals during data reception of u nipo - lar d ata rxpos rxneg rxlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 292 the user can configure the receive e3 liu interface block to operate in either the unipolar or the bipolar mode by writing the appropriate data to the i/o con- trol register, as depicted below. table 59 relates the value of this bit-field to the re- ceive e3 liu interface input mode. n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the transmit e3 framer line interface output mode 5.3.1.2 bipolar decoding if the receive e3 liu interface block is operating in the bipolar mode, then it will receive the e3 data puls- es via both the rxpos, rxneg, and the rxlineclk input pins. figure 130 presents a circuit diagram il- lustrating how the receive e3 liu interface block in- terfaces to the line interface unit while the framer is operating in bipolar mode. the receive e3 liu inter- face block can be configured to decode either the ami or hdb3 line codes. i/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 59: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 3r eceive e3 liu i nterface i nput m ode 0 bipolar mode (dual rail): ami or hdb3 line codes are transmitted and received. 1 unipolar mode (single rail) mode of transmission and reception of e3 data is selected. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 293 5.3.1.2.1 ami decoding ami or alternate mark inversion, means that consec- utive "one's" pulses (or marks) will be of opposite po- larity with respect to each other. this line code in- volves the use of three different amplitude levels: +1, 0, and -1. the +1 and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" ampli- tude pulses (or the absence of a pulse) are used to represent zeros (or space) pulses. the general rule for ami is: if a given mark pulse is of positive polarity, then the very next mark pulse will be of negative po- larity and vice versa. this alternating-polarity rela- tionship exists between two consecutive mark pulses, independent of the number of zeros that exist be- tween these two pulses. figure 131 presents an illus- tration of the ami line code as would appear at the rxpos and rxneg pins of the framer, as well as the output signal on the line. f igure 130. i llustration on how a c hannel of the r eceive e3 f ramer ( within the XRT72L50 f ramer ic) being interface to the xrt73l00 l ine i nterface u nit , while operating in b ipolar m ode 5v u1 xrt7250 txpos 65 txneg 64 txlineclk 63 dmo 79 extlos 78 rlol 77 lloop 69 rloop 70 taos 68 txlev 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 txser 46 txinclk 43 txframe 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 xrt7300 tpdata 37 tndata 38 tclk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tring 40 mtip 44 mring 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 taos 2 txlev 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 txser txinclk nibbleintf resetb rtip rring csb rw ds as txframe rxser rxclk rxframe rxlos rxoof rxred rxais a[8:0] tring ttip intb d[7:0] intb ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 294 n ote : one of the reasons that the ami line code has been chosen for driving copper medium, isolated via trans- formers, is that this line code has no dc component, thereby eliminating dc distortion in the line. 5.3.1.2.2 hdb3 decoding the transmit e3 liu interface block and the associat- ed liu embed and combine the data and clocking in- formation into the line signal that is transmitted to the remote terminal equipment. the remote terminal equipment has the task of recovering this data and timing information from the incoming e3 data stream. most clock and data recovery schemes rely on the use of phase-locked-loop technology. one of the problems of using phase-locked-loop (pll) technol- ogy for clock recovery is that it relies on transitions in the line signal, in order to maintain lock with the in- coming e3 data-stream. therefore, these clock re- covery scheme, are vulnerable to the occurrence of a long stream of consecutive zeros (e.g., no transitions in the line). this scenario can cause the pll to lose lock with the incoming e3 data, thereby causing the clock and data recovery process of the receiver to fail. therefore, some approach is needed to insure that such a long string of consecutive zeros can never happen. one such technique is hdb3 (or high den- sity bipolar -3) encoding. in general the hdb3 line code behaves just like ami with the exception of the case when a long string of consecutive zeros occurs on the line. any 4 consecu- tive zeros will be replaced with either a "000v" or a "b00v" where "b" refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the ami coding rule). and "v" refers to a bipolar violation pulse (e.g., a pulse with a polarity that violates the al- ternating polarity scheme of ami.) the decision be- tween inserting an "000v" or a "b00v" is made to in- sure that an odd number of bipolar (b) pulses exist between any two bipolar violation (v) pulses. the receive e3 liu interface block, when operating with the hdb3 line code is responsible for decoding the hd-encoded data back into a unipolar (binary-for- mat). for instance, if the receive e3 liu interface block detects a "000v" or a "b00v" pattern in the in- coming pattern, the receive e3 liu interface block will replace it with four (4) consecutive zeros. figure 132 presents a timing diagram that illustrates examples of hdb3 decoding. f igure 131. i llustration of ami l ine c ode data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 rxpos rxneg line signal f igure 132. i llustration of two examples of hdb3 d ecoding line signal 000v b00v rxneg rxpos data 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 100 0 00 1 1 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 295 5.3.1.2.3 line code violations the receive e3 liu interface block will also check the incoming e3 data stream for line code violations. for example, when the receive e3 liu interface block detects a valid bipolar violation (e.g., in hdb3 line code), it will substitute four zeros into the binary data stream. however, if the bipolar violation is in- valid, then an lcv (line code violation) is flagged and the pmon lcv event count register (address = 0x50 and 0x51) will also be incremented. additional- ly, the lcv-one-second accumulation registers (ad- dress = 0x6e and 0x6f) will be incremented. for ex- ample: if the incoming e3 data is hdb3 encoded, the receive e3 liu interface block will also increment the lcv one-second accumulation register if three (or more) consecutive zeros are received. 5.3.1.2.4 rxlineclk clock edge selection the incoming unipolar or bipolar data, applied to the rxpos and the rxneg input pins are clocked into the receive e3 liu interface block via the rxlineclk signal. the framer ic allows the user to specify which edge (e.g, rising or falling) of the rxlineclk signal will sample and latch the signal at the rxpos and rxneg input signals into the framer ic. the us- er can make this selection by writing the appropriate data to bit 1 of the i/o control register, as depicted below. table 60 depicts the relationship between the value of this bit-field to the sampling clock edge of rxlineclk. figure 133 and figure 134 present the waveform and timing relationships between rxlineclk, rxpos and rxneg for each of these configurations. ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 101000 00 t able 60: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r egister , and the sampling edge of the r x l ine c lk signal r x clki nv (b it 1) r esult 0 .rising edge: rxpos and rxneg are sampled at the rising edge of rxlineclk. see figure 133 for timing relationship between rxlineclk, rxpos, and rxneg. 1 falling edge: rxpos and rxneg are sampled at the falling edge of rxlineclk. see figure 134 for timing relationship between rxlineclk, rxpos, and rxneg. ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 296 5.3.2 the receive e3 framer block the receive e3 framer block accepts decoded e3 data from the receive e3 liu interface block, and routes data to the following destinations. ? the receive payload data output interface block ? the receive overhead data output interface block. ? the receive e3 hdlc controller block figure 135 presents a simple illustration of the re- ceive e3 framer block along with the associated paths to the other functional blocks within the framer chip. f igure 133. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the rising edge of r x l ine c lk rxlineclk rxpos rxneg t38 t39 t42 f igure 134. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the falling edge of r x l ine c lk rxlineclk rxpos rxneg t40 t41 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 297 once the hdb3 (or ami) encoded data has been de- coded into a binary data-stream, the receive e3 framer block will use portions of this data-stream in order to synchronize itself to the remote terminal equipment. at any given time, the receive e3 fram- er block will be operating in one of two modes. ? the frame acquisition mode: in this mode, the receive e3 framer block is trying to acquire syn- chronization with the incoming e3 frame, or ? the frame maintenance mode: in this mode, the receive e3 framer block is trying to maintain frame synchronization with the incoming e3 frames. figure 136 presents a state machine diagram that depicts the receive e3 framer block's e3/itu-t g.751 frame acquisition/maintenance algorithm. 5.3.2.1 the framing acquisition mode the receive e3 framer block is considered to be op- erating in the frame acquisition mode, if it is operat- ing in any one of the following states within the e3 frame acquisition/maintenance algorithm per figure 136. ? fas pattern search state ? fas pattern verification state ? oof condition state ? lof condition state each of these framing acquisition states, within the receive e3 framer framing acquisition/maintenance state machine are discussed below. the fas pattern search state when the receive e3 framer block is first powered up, it will be operating in the fas pattern search state. while the receive e3 framer is operating in this state, it will be performing a bit-by-bit search for the fas (framing alignment signal) pattern, of 1111010000. figure 137, which presents an illus- tration of the e3, itu-t g.751 framing format, indi- cates that this framing alignment signal will occur at the beginning of each e3 frame. f igure 135. a s imple i llustration of the r eceive e3 f ramer b lock and the a ssociated p aths to the o ther f unctional b locks receive e3 framer block receive e3 framer block to receive e3 hdlc buffer receive overhead data output interface receive payload data output interface from receive e3 liu interface block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 298 when the receive e3 framer block detects the fas pattern, it will then transition over to the fas pattern verification state, per figure 137. the fas pattern verification state once the receive e3 framer block has detected an 1111010000 pattern, it must verify that this pattern is indeed the fas pattern and not some other set of bits, within the e3 frame, mimicking the fas pattern. f igure 136. t he s tate m achine d iagram for the r eceive e3 f ramer e3 f rame a cquisition /m aintenance a lgorithm fas pattern search fas pattern verification in frame oof condition lof condition fas pattern is detected once fas pattern is verified once fas pattern is not detected 4 consecutive in-valid frames 3 consecutive valid frames 8 or 24 framing periods of operating in the oof condition (user-selectable) frame maintenance mode f igure 137. i llustration of the e3, itu-t g.751 f raming f ormat frame alignment signal an data data data data bip-4 if selected 1 10 11 12 384 385 768 769 1 152 1153 1532 1536 framing alignment signal pattern = 1111010000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 299 hence, the purpose of the fas pattern verification state. when the receive e3 framer block enters this state, it will then quit performing its bit-by-bit search for the frame alignment signaling bits. instead, the receive e3 framer block will read in the 10 bits that occur 1536 bit (e.g., one e3 frame period later) after the candidate fas pattern was first detected. if these ten bits match the assigned values for the fas pattern octets, then the receive e3 framer block will con- clude that it has found the fas pattern and will then transition to the in-frame state. however, if these two bytes do not match the assigned values for the fas pattern then the receive e3 framer block will con- cluded that it has been fooled by data mimicking the frame alignment bytes, and will transition back to the fas pattern search state. in frame state once the receive e3 framer block enters the in- frame state, then it will cease performing frame ac- quisition functions, and will proceed to perform fram- ing maintenance functions. therefore, the operation of the receive e3 framer block, while operating in the in-frame state, can be found in section 4.3.2.2 (the framing maintenance mode). oof (out of frame) condition state if the receive e3 framer while operating in the in- frame state detects four (4) consecutive frames, which do not have the valid frame alignment signal- ing (fas) patterns, then it will transition into the oof condition state. the receive e3 framer blocks op- eration, while in the oof condition state is a unique mix of framing maintenance and framing acquisition operation. the receive e3 framer block will exhibit some framing acquisition characteristics by attempt- ing to locate (once again) the fas pattern. however, the receive e3 framer block will also exhibit some frame maintenance behavior by still using the most recent frame synchronization for its overhead bits and payload bits processing. the receive e3 framer block will inform the micro- processor/microcontroller of its transition from the in- frame state to the oof condition state, by generat- ing a change in oof condition interrupt. when this occurs, bit 3 (oof interrupt status), within the rx e3 interrupt status register - 1, will be set to 1, as de- picted below. the receive e3 framer block will also inform the ex- ternal circuitry of its transition into the oof condition state, by toggling the rxoof output pin "high. if the receive e3 framer block is capable of finding the fas pattern within a user-selectable number of e3 frame periods, then it will transition back into the in-frame state. the receive e3 framer block will then inform the microprocessor/microcontroller of its transition back into the in-frame state by generating the change in oof condition interrupt. however, if the receive e3 framer block resides in the oof condition state for more than this user-se- lectable number of e3 frame periods, then it will auto- matically transition to the lof (loss of frame) condi- tion state. the user can select this user-selectable number of e3 frame periods that the receive e3 framer block will remain in the oof condition state by writing the appropriate value into bit 7 (rxlof algo) within the rx e3 configuration & status register, as depicted below. rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 300 writing a 0 into this bit-field causes the receive e3 framer block to reside in the oof condition state for at most 24 e3 frame periods. writing a 1 into this bit-field causes the receive e3 framer block to reside in the oof condition state for at most 8 e3 frame pe- riods. lof (loss of framing) condition state if the receive e3 framer block enters the lof condi- tion state, then the following things will happen. ? the receive e3 framer block will discard the most recent frame synchronization and, ? the receive e3 framer block will make an uncon- ditional transition to the fas pattern search state. ? the receive e3 framer block will notify the micro- processor/microcontroller of its transition to the lof condition state, by generating the change in lof condition interrupt. when this occurs, bit 2 (lof interrupt status), within the rx e3 interrupt status register - 1 will be set to 1, as depicted below. finally, the receive e3 framer block will also inform the external circuitry of this transition to the lof con- dition state by toggling the rxlof output pin "high. 5.3.2.2 the framing maintenance mode once the receive e3 framer block enters the in- frame state, then it will notify the microprocessor/mi- crocontroller of this fact by generating both the change in oof condition and change in lof condi- tion interrupts. when this happens, bits 2 and 3 (lof interrupt status and oof interrupt status) will be set to 1, as depicted below. additionally, the receive e3 framer block will inform the external circuitry of its transition to the in-frame state by toggling both the rxoof and rxlof output pins "low. finally, the receive e3 framer block will negate both the rxoof and the rxlof bit-fields within the rx e3 configuration & status register, as depicted below. rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000100 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00001100 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 301 when the receive e3 framer block is operating in the in-frame state, it will then begin to perform frame maintenance operations, where it will continue to ver- ify that the frame alignment signal (fas pattern) is present, and at its proper location. while the receive e3 framer block is operating in the frame mainte- nance mode, it will declare an out-of-frame (oof) condition if it detects an invalid fas pattern in four consecutive frames. since the receive e3 framer block requires the de- tection of an invalid fas pattern in four consecutive frames, in order for it to transition to the oof condi- tion state, it can tolerate some errors in the framing alignment bytes, and still remain in the in-frame state. however, each time the receive e3 framer block detects an error in the fas pattern, it will incre- ment the pmon framing error event count regis- ters (address = 0x52 and 0x53). the bit-format for these two registers are depicted below. 5.3.2.3 forcing a reframe via software com- mand the XRT72L50 framer ic permits the user to com- mand a reframe procedure with the receive e3 fram- er block via software command. if the user writes a 1 into bit 0 (reframe) within the i/o control register (address = 0x01), as depicted below, then the re- ceive e3 framer block will be forced into the fas pat- tern search state, per figure 138., and will begin its search for the fas pattern. rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 00000111 pmon framing bit/byte error count register - msb (address = 0x52) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit/byte error count - high byte rurrurrurrurrurrurrurrur 00000000 pmon framing bit/byte error count register - lsb (address = 0x53) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit/byte error count - low byte rurrurrurrurrurrurrurrur 00000000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 302 ) the framer ic will respond to this command by doing the following. 1. asserting both the rxoof and rxlof output pins. 2. generating both the change in oof status and the change in lof status interrupts to the micro- processor. 3. asserting both the rxlof and rxoof bit-fields within the rx e3 configuration & status register, as depicted below. 5.3.2.4 performance monitoring of the frame synchronization section, within the receive e3 framer block the user can monitor the number of fas pattern er- rors that have been detected by the receive e3 framer block. this is accomplished by periodically reading the pmon framing bit/byte error event count registers (address = 0x52 and 0x53). the byte format of these registers are presented below. 5.3.2.5 the rxoof and rxlof output pin. the user can roughly determine the current framing state that the receive e3 framer block is operating in by reading the logic state of the rxoof and the rx- lof output pins. table 61 presents the relationship between the state of the rxoof and rxlof output pins, and the framing state of the receive e3 framer block. 5.3.2.6 e3 receive alarms 5.3.2.7 the loss of signal (los) alarm declaring an los condition the receive e3 framer block will declare a loss of signal (los) condition, when it detects 32 consecu- tive incoming 0s via the rxpos and rxneg input pins or if the extlos input pin (from the xrt7300 ds3/e3/sts-1 liu ic) is asserted. the receive e3 framer block will indicate that it is declaring an los condition by. i/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/ zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 10100001 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100110 t able 61: t he r elationship between the l ogic s tate of the r x oof and r x lof output pins , and the f raming s tate of the r eceive e3 f ramer block r x lof r x oof f raming s tate of the r eceive e3 f ramer block 00 in frame 01 oof condition (the receive e3 framer block is operating in the 3ms oof period). 10 invalid 11 lof condition XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 303 ? asserting the rxlos output pin (e.g., toggling it "high). ? setting bit 4 (rxlos) of the rx e3 configuration & status register to 1 as depicted below. ? the receive e3 framer block will generate a change in los condition interrupt request. upon generating this interrupt request, the receive e3 framer block will assert bit 1 (los interrupt status within the rx e3 framer interrupt status register - 1, as depicted below. clearing the los condition the receive e3 framer block will clear the los con- dition when it encounters a stream of 32 bits that does not contain a string of 4 consecutive zeros. when the receive e3 framer block clears the los condition, then it will notify the microprocessor and the external circuitry of this occurrence by: ? generating the change in los condition interrupt to the microprocessor. ? clearing bit 4 (rxlos) within the rx e3 configura- tion & status register, as depicted below. ? clear the rxlos output pin (e.g., toggle it "low). 5.3.2.8 the ais (alarm indication status) con- dition declaring the ais condition the receive e3 framer block will identify and declare an ais condition, if it detects an all ones pattern in the incoming e3 data stream. more specifically, the receive e3 framer block will declare an ais condi- tion if 7 or less 0s are detected in each of 2 consec- utive e3 frames. if the receive e3 framer block declares an ais con- dition, then it will do the following. ? generate the change in ais condition interrupt to the microprocessor. hence, the receive e3 framer block will assert bit 0 (ais interrupt status) within the rx e3 framer interrupt status register - 1, as depicted below. rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01110000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000010 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 304 ? assert the rxais output pin. ? set bit 3 (rxais) within the rx e3 configuration & status register, as depicted below. clearing the ais condition the receive e3 framer block will clear the ais condi- tion when it detects two consecutive e3 frames, with eight or more zeros in the incoming data stream. the receive e3 framer block will inform the micro- processor that the ais condition has been cleared by: ? generating the change in ais condition interrupt to the microprocessor. hence, the receive e3 framer block will assert bit 0 (ais interrupt status) within the rx e3 framer interrupt status register - 1. ? clearing the rxais output pin (e.g., toggling it "low). ? setting the rxais bit-field, within the rx e3 config- uration & status register to 0, as depicted below. 5.3.2.9 the far-end-receive failure (ferf) condition declaring the ferf condition the receive e3 framer block will declare a far-end receive failure (ferf) condition if it detects a user- selectable number of consecutive incoming e3 frames, with the a bit-field set to 1. this user-selectable number of e3 frames is either 3 or 5, depending upon the value that has been written into bit 4 (rxferf algo) within the rx e3 configura- tion & status register, as depicted below. rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000001 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01101111 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 0110100x XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 305 writing a 0 into this bit-field causes the receive e3 framer block to declare a ferf condition, if it detects 3 consecutive incoming e3 frames, that have the a bit set to 1. writing a 1 into this bit-field causes the receive e3 framer block to declare a ferf condition, if it detects 5 consecutive incoming e3 frames, that have the a bit set to 1. whenever the receive e3 framer block declares a ferf condition, then it will do the following. ? generate a change in ferf condition interrupt to the microprocessor. hence, the receive e3 framer block will assert bit 3 (ferf interrupt sta- tus) within the rx e3 framer interrupt status regis- ter - 2, as depicted below. ? set the rxferf bit-field, within the rx e3 configu- ration/status register to 1, as depicted below. clearing the ferf condition the receive e3 framer block will clear the ferf condition once it has received a user-selectable number of e3 frames with the a bit-field being set to 0 (e.g., no ferf condition). this user-selectable number of e3 frames is either 3 or 5 depending upon the value that has been written into bit 4 (rxferf al- go) of the rx e3 configuration/status register, as discussed above. whenever the receive e3 framer clears the ferf status, then it will do the following: 1. generate a change in the ferf status interrupt to the microprocessor. 2. clear the bit 0 (rxferf) within the rx e3 con- figuration & status register, as depicted below. rxe3 configuration & status register - 1 g.751 (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxferf algo reserved rxbip4 ro ro ro r/w ro ro ro r/w 00000000 rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt status bip-4 error interrupt status framing error interrupt status not used ro ro ro ro rur rur rur rur 00001000 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 306 5.3.2.10 error checking of the incoming e3 frames the receive e3 framer block can be configured to performs error-checking on the incoming e3 frame data that it receives from the remote terminal equip- ment. if configured accordingly, the receive e3 framer block will performs this error-checking by computing the bip-4 value of an incoming e3 frame. once the receive e3 framer block has obtained this value, it will compare this value with that of the bip-4 value that it receives, within the very next e3 frame. if the locally computed bip-4 value matches the em byte of the corresponding e3 frame, then the receive e3 framer block will conclude that this particular frame has been properly received. the receive e3 framer block will then inform the remote terminal equipment of this fact by having the local terminal equipment transmit e3 framer block send the re- mote terminal an e3 frame, with the a bit-field, set to 0. this procedure is illustrated in figure 138 and figure 139, below. figure 138 illustrates the local receive e3 framer receiving an error-free e3 frame. in this figure, the lo- cally computed bip-4 value of 0xa matches that re- ceived from the remote terminal, within the em byte- field. figure 139 illustrates the subsequent action of the local transmit e3 framer block, which will trans- mit an e3 frame, with the a bit-field set to 0, to the remote terminal. this signaling indicates that the local receive e3 framer has received an error-free e3 frame. rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 f igure 138. i llustration of the l ocal r eceive e3 f ramer block , receiving an e3 f rame ( from the r emote t erminal ) with a correct bip-4 v alue . transmit e3 framer receive e3 framer local terminal remote terminal bip-4 nibble locally calculated bip-4 nibble 0xa 0xa XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 307 however, if the locally computed bip-4 value does not match the bip-4 value of the corresponding e3 frame, then the receive e3 framer block will do the follow- ing. ? it will inform the remote terminal of this fact by having the local transmit e3 framer block send the remote terminal an e3 frame, with the a bit-field set to 1. this phenomenon is illustrated below in figure 140 and figure 141. figure 140 illustrates the local receive e3 framer receiving an errored e3 frame. in this figure, the lo- cal receive e3 frame block is receiving an e3 frame with an bip-4 containing the value 0xa. this value does not match the locally computed bip-4 value of 0xb. consequently, there is an error in the previous e3 frame. figure 141 illustrates the subsequent action of the local transmit e3 framer block, which will transmit an e3 frame, with the a bit-field set to 1 to the re- mote terminal. this signaling indicates that the local receive e3 framer block has received an errored e3 frame. f igure 139. i llustration of the l ocal r eceive e3 f ramer block , transmitting an e3 f rame ( to the r emote t erminal ) with the a bit set to 0 transmit e3 framer receive e3 framer local terminal remote terminal a bit value = 0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 308 in additional to the febe bit-field signaling, the re- ceive e3 framer block will generate the bip-4 error interrupt to the microprocessor. hence, it will set bit 2 (bip-8 error interrupt status) to 1, as depicted be- low. f igure 140. i llustration of the l ocal r eceive e3 f ramer block , receiving an e3 f rame ( from the r emote t erminal ) with an incorrect bip-4 value . transmit e3 framer receive e3 framer local terminal remote terminal bip-4 nibble locally calculated bip-4 nibble 0xa 0xb f igure 141. i llustration of the l ocal r eceive e3 f ramer block , transmitting an e3 f rame ( to the r emote t erminal ) with the a bit - field set to 1 transmit e3 framer receive e3 framer local terminal remote terminal a bit value = 1 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 309 finally, the receive e3 framer block will increment the pmon parity error count registers. the byte for- mat of these registers are presented below. the user can determine the number of bip-4 errors that have been detected by the receive e3 framer block, since the last read of these registers. these registers are reset-upon-read. configuring the XRT72L50 framer ic to support bip-4 error detection in order to perform bip-4 checking of each e3 frame, the user must configure the XRT72L50 framer ic ac- cordingly, by executing the following steps. 1. configure the transmit section (of the XRT72L50 framer ic) to insert the bip-4 value into the out- bound e3 frames. this is accomplished by writ- ing a 1 into bit-field 7 (tx bip-4 enable) within the txe3 configuration register, as illustrated below. rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt status bip-4 error interrupt status framing error interrupt status not used ro ro ro ro rur rur rur rur 00000100 pmon parity error count register - msb (address = 0x54) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - high byte rurrurrurrurrurrurrurrur 00000000 pmon parity error count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - low byte rurrurrurrurrurrurrurrur 00000000 txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx bip-4 enable txasourcesel[1:0] txnsourcesel[1:0] tx ais enable tx los enable tx fas source select r/w r/w r/w r/w r/w r/w r/w r/w 10000000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 310 2. enable the bip-4 error interrupt. this is accom- plished by writing a 1 into bit-field 2 (bip-4 error interrupt enable) within the rxe3 interrupt enable register, as illustrated below. after doing this, the XRT72L50 framer ic will gener- ate an interrupt to the microprocessor/microcontroller anytime the receive section detects a bip-4 error. 5.3.3 the receive hdlc controller block the receive e3 hdlc controller block can be used to receive message-oriented signaling (mos) type data link messages from the remote terminal equip- ment. the mos types of hdlc message processing is dis- cussed in detail below. the message oriented signaling (e.g., lap-d) processing via the receive e3 hdlc controller block the lapd receiver (within the receive e3 hdlc controller block) allows the user to receive pmdl messages from the remote terminal equipment, via the inbound e3 frames. in this case, the inbound message bits will be carried by the n bit-field within each inbound e3 frame. the remote lapd transmit- ter will transmit a lapd message to the local receiv- er via either the n bit within each e3 frame. the lapd receiver will receive and store the information portion of the received lapd frame into the receive lapd message buffer, which is located at addresses: 0xde through 0x135 within the on-chip ram. the lapd receiver has the following responsibilities. ? framing to the incoming lapd messages ? filtering out stuffed "0s" (within the information payload) ? storing the frame message into the receive lapd message buffer ? perform frame check sequence (fcs) verification ? provide status indicators for end of message (eom) flag sequence byte detected abort sequence detected message type c/r type the occurrence of fcs errors the lapd receiver's actions are facilitated via the fol- lowing two registers. ? rx e3 lapd control register ? rx e3 lapd status register operation of the lapd receiver the lapd receiver, once enabled, will begin search- ing for the boundaries of the incoming lapd mes- sage. the lapd message frame boundaries are de- lineated via the flag sequence octets (0x7e), as de- picted in figure 142. rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt enable bip-4 error interrupt enable framing error interrupt enable not used r/w ro ro ro r/w r/w r/w ro 0000 0 1 0 0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 311 where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the 16 bit fcs is calculated using crc-16, x16 + x12 + x5 + 1 the local p (at the remote terminal), while assem- bling the lapd message frame, will insert an addi- tional byte at the beginning of the information (pay- load) field. this first byte of the information field indi- cates the type and size of the message being trans- ferred. the value of this information field and the corresponding message type/size follow: cl path identification = 0x38 (76 bytes) idle signal identification = 0x34 (76 bytes) test signal identification = 0x32 (76 bytes) itu-t path identification = 0x3f (82 bytes) enabling and configuring the lapd receiver before the lapd receiver can begin to receive and process incoming lapd message frames, the user must do two things. 1. enabling the lapd receiver the lapd receiver must be enabled before it can begin receiving and processing any lapd message frames. the lapd receiver can be enabled by writ- ing a 1 to bit 2 (rxlapd enable) of the rx e3 lapd control register, as indicated below. ) once the lapd receiver has been enabled, it will be- gin searching for the flag sequence octet (0x7e), in the n bit-fields within each incoming e3 frame. when the lapd receiver finds the flag sequence byte, it will assert the flag present bit (bit 0) within the rx e3 lapd status register, as depicted below. f igure 142. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) rxe3 lapd control register (address = 0x18 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt enable ro ro ro ro ro r/w r/w rur 00000 0 0 0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 312 the receipt of the flag sequence octet can mean one of two things. 1. this flag sequence byte may be marking the beginning or end of an incoming lapd message frame. 2. the received flag sequence octet could be just one of many flag sequence octets that are trans- mitted via the e3 transport medium, during idle periods between the transmission of lapd mes- sage frames. the lapd receiver will negate the flag present bit as soon as it has received an octet that is something other than the flag sequence octet. once this hap- pens, the lapd receiver should be receiving either octet # 2 of the incoming lapd message, or an abort sequence (e.g., a string of seven or more consecutive 1s). if this next set of data is an abort sequence, then the lapd receiver will as- sert the rxabort bit-field (bit 6) within the rx e3 lapd status register, as depicted below. however, if this next octet is octet #2 of an incoming lapd message frame, then the lapd receiver is be- ginning to receive a lapd message frame. as the lapd receiver receives this lapd message frame, it is reading in the lapd message frame oc- tets, from n bit-fields within each incoming e3 frame. secondly, it is reassembling these bits into a lapd message frame. once the lapd receiver has received the complete lapd message frame, then it will proceed to perform the following five (5) steps. 1. pmdl message extraction the lapd receiver will extract out the pmdl mes- sage, from the newly received lapd message frame. the lapd receiver will then write this pmdl mes- sage into the receive lapd message buffer within the framer ic. n ote : as the lapd receiver is extracting the pmdl mes- sage, from the newly received lapd message frame, the lapd receiver will also check the pmdl data for the occurrence of stuff bits (e.g., 0s that were inserted into the pmdl message by the remote lapd transmitter, in order to prevent this data from mimicking the flag sequence byte or an abort sequence), and remove them prior to writing the pmdl message into the receive lapd message buffer. specifically, the lapd receiver will search through the pmdl message data and will remove any 0 that immediately follows a string of 5 consecutive 1s. n ote : for more information on how the lapd transmitter inserted these stuff bits, please see section 4.2.3.1. 2. fcs (frame check sequence) word verification the lapd receiver will compute the crc-16 value of the header octets and the pmdl message octets, within this lapd message frame and will compare it with the value of the two octets, residing in the fcs word-field of this lapd message frame. if the fcs value of the newly received lapd message frame matches the locally-computed crc-16 value, then the lapd receiver will conclude that it has received this lapd message frame in an error-free manner. however, if the fcs value does not match the locally- computed crc-16 value, then the lapd receiver will conclude that this lapd message frame is erred. rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000001 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 01000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 313 the lapd receiver will indicate the results of this fcs verification process by setting bit 2 (rxfcs er- ror) within the rx e3 lapd status register, to the ap- propriate value as tabulated below. if the lapd receiver detects an error in the fcs val- ue, then it will set the rxfcs error bit-field to 1. conversely, if the lapd receiver does not detect an error in the fcs value, then it will clear the rxfcs error bit-field to 0. n ote : the lapd receiver will extract and write the pmdl message into the receive lapd message buffer indepen- dent of the results of fcs verification. hence, the user is urged to validate each pmdl message that is read in from the receive lapd message buffer, by first checking the state of this bit-field. 3. check and report the state of the c/r bit-field after receiving the lapd message frame, the lapd receiver will check the state of the c/r bit-field, within octet # 2 of the lapd message frame header and will reflect this value in bit 3 (rx cr type) within the rx e3 lapd status register, as depicted below. when this bit-field is 0, it means that this lapd message frame is originating from a customer instal- lation. when this bit-field is 1, it means that this lapd message frame is originating from a network terminal. 4. identify the type of lapd message frame/pmdl message next, the lapd receiver will check the value of the first octet within the pmdl message field, of the lapd message frame. when operating the lapd transmitter, the user is required to write in a byte of a specific value into the first octet position within the transmit lapd message buffer. the value of this byte corresponds to the type of lapd message frame/pmdl message that is to be transmitted to the remote lapd receiver. this message-type identifi- cation octet is transported to the remote lapd re- ceiver, along with the rest of the lapd frame. from this message type identification octet, the lapd re- ceiver will know the type of size of the newly received pmdl message. the lapd receiver will then reflect this information in bits 4 and 5 (rxlapdtype[1:0]) within the rx e3 lapd status register, as depicted below. rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000100 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00001000 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 314 table 62 presents the relationship between the con- tents of rxlapdtype[1:0] and the type of message received by the lapd receiver. n ote : prior to reading in the pmdl message from the receive lapd message buffer, the user is urged to read the state of the rxlapdtype[1:0] bit-fields in order to deter- mine the size of this message. 5. inform the local microprocessor/external cir- cuitry of the receipt of the new lapd message frame. finally, after the lapd receiver has received and processed the newly received lapd message frame (per steps 1 through 4, as described above), it will in- form the local microprocessor that a lapd message frame has been received and is ready for user-sys- tem handling. the lapd receiver will inform the mi- croprocessor/microcontroller and the external circuit- ry by: ? generating a lapd message frame received interrupt to the microprocessor. the purpose of this interrupt is to let the microprocessor know that the receive lapd message buffer contains a new pmdl message that needs to be read and pro- cessed. when the lapd receiver generates this interrupt, it will set bit 0 (rxlapd interrupt status) within the rx e3 lapd control register to 1 as depicted below. ) ? setting bit 1 (end of message) within the rx e3 lapd status register, to 1 as depicted below. in summary, figure 143 presents a flow chart depict- ing how the lapd receiver functions. t able 62: t he r elationship between the c ontents of r x lapdt ype [1:0] bit - fields and the pmdl m essage t ype /s ize r x lapdt ype [1:0] pmdl m essage t ype pmdl m essage s ize 00 test signal identification 76 bytes 01 idle signal identification 76 bytes 10 cl path identification 76 bytes 11 itu-t path identification 82 bytes rxe3 lapd control register (address = 0x18 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000 0 0 1 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000010 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 315 5.3.4 the receive overhead data output inter- face figure 144 presents a simple illustration of the re- ceive overhead data output interface block within the XRT72L50. f igure 143. f low c hart depicting the f unctionality of the lapd r eceiver start start enable the lapd receiver this is done by writing the value xxxx x1xx into the rxlapd control register (address = 0x18) lapd receiver begins reading in the n bits from each inbound e3 frame does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? flag sequence flag sequence abort sequence abort sequence lapd receiver is reading in a lapd message frame, containing a pmdl message. lapd receiver is reading in a lapd message frame, containing a pmdl message. does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? end of message (eom) end of message (eom) verify the fcs value report results in the rxlapd status register.. verify the fcs value report results in the rxlapd status register.. un-stuff contents of received message un-stuff contents of received message write received pmdl message into the receive lapd message buffer (addresses 0xde - 0x135) write received pmdl message into the receive lapd message buffer (addresses 0xde - 0x135) generate received lapd interrupt generate received lapd interrupt execute receive lapd interrupt service routine execute receive lapd interrupt service routine 1 1 1 1 no yes no yes yes no yes no ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 316 the e3, itu-t g.751 frame consists of 1536 bits. of these bytes, 1524 bits are payload bits and the re- maining 12 bits are overhead bits. the XRT72L50 has been designed to handle and process both the payload type and overhead type bits for each e3 frame. within the receive section of the XRT72L50, the re- ceive payload data output interface block has been designed to handle the payload bits. likewise, the receive overhead data output interface block has been designed to handle and process the overhead bits. the receive overhead data output interface block unconditionally outputs the contents of all overhead bits. the XRT72L50 does not offer the user a means to shut off this transmission of data. however, the receive overhead output interface block does pro- vide the user with the appropriate output signals for external data link layer equipment to sample and process these overhead bits, via the following two methods. ? method 1- using the rxohclk clock signal. ? method 2 - using the rxclk and rxohenable out- put signals. each of these methods are described below. 5.3.4.1 method 1 - using the rxohclk clock signal the receive overhead data output interface block consists of four (4) signals. of these four signals, the following three signals are to be used when sampling the e3 overhead bits via method 1. ? rxoh ? rxohclk ? rxohframe each of these signals are listed and described below in table 63. interfacing the receive overhead data output in- terface block to the terminal equipment (method 1) figure 145 illustrates how one should interface the receive overhead data output interface block to the terminal equipment when using method 1 to sample and process the overhead bits from the inbound e3 data stream. f igure 144. a s imple i llustration of the r eceive o verhead o utput i nterface block receive overhead output interface block receive overhead output interface block from receive e3 framer block rxohframe rxoh rxohclk rxohenable XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 317 method 1 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound e3 data stream (via the receive overhead data output interface block) then it is expected to do the following: 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input signal) on the rising edge of the rxohclk (e.g., the e3_oh_clock_in) signal. 2. keep track of the number of rising clock edges that have occurred in the rxohclk (e.g., the e3_oh_clock_in) signal, since the last time the rxohframe signal was sampled "high. by doing this, the terminal equipment will be able to keep track of which overhead byte is being output via the rxoh output pin. based upon this infor- mation, the terminal equipment will be able to derive some meaning from these overhead bits. f igure 145. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 1). terminal equipment xrt72l5x e3 framer ic rxohclk e3_oh_clock_in rxoh rxohframe e3_oh_in rx_start_of_frame ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 318 table 64 relates the number of rising clock edges (in the rxohclk signal, since the rxohframe signal was last sampled "high) to the e3 overhead bit that is being output via the rxoh output pin. figure 146 presents the typical behavior of the re- ceive overhead data output interface block, when method 1 is being used to sample the incoming e3 overhead bits. t able 63: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (f or m ethod 1) s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L50 will output the overhead bits, within the incoming e3 frames, via this pin. the receive overhead data output interface block will output a given overhead bit, upon the falling edge of rxohclk. hence, the external data link equipment should sample the data, at this pin, upon the rising edge of rxohclk. n ote : the XRT72L50 will always output the e3 overhead bits via this output pin. there are no external input pins or register bit settings available that will disable this output pin. rxohclk output receive overhead data output interface clock signal: the XRT72L50 will output the overhead bits (within the incoming e3 frames), via the rxoh output pin, upon the falling edge of this clock signal. as a consequence, the user's data link equipment should use the rising edge of this clock sig- nal to sample the data on both the rxoh and rxohframe output pins. n ote : this clock signal is always active. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L50 will drive this output pin "high (for one period of the rxohclk signal) whenever the first overhead bit within a given e3 frame is being driven onto the rxoh output pin. t able 64: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x ohf rame was last sampled "h igh ) to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the XRT72L50 0 (clock edge is coincident with rxohframe being detected "high) fas pattern - bit 9 1 fas pattern - bit 8 2 fas pattern - bit 7 3 fas pattern - bit 6 4 fas pattern - bit 5 5 fas pattern - bit 4 6 fas pattern - bit 3 7 fas pattern - bit 2 8 fas pattern - bit 1 9 fas pattern - bit 0 10 a bit 11 n bit XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 319 method 2 - using rxoutclk and the rxohenable signals method 1 requires that the terminal equipment be able to handle an additional clock signal, rxohclk. however, there may be a situation in which the termi- nal equipment circuitry does not have the means to deal with this extra clock signal, in order to use the receive overhead data output interface. method 2 involves the use of the following signals. ? rxoh ? rxoutclk ? rxohenable ? rxohframe each of these signals are listed and described below in table 65. f igure 146. i llustration of the signals that are output via the r eceive o verhead o utput i nterface ( for m ethod 1). rxohclk rxohframe rxoh fas, bit 9 fas, bit 8 fas, bit 7 fas, bit 6 fas, bit 5 terminal equipment should sample the rxohframe and rxoh signals here. recommended sampling edges ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 320 interfacing the receive overhead data output in- terface block to the terminal equipment (method 2) figure 147 illustrates how one should interface the receive overhead data output interface block to the terminal equipment, when using method 2 to sample and process the overhead bits from the inbound e3 data stream. t able 65: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (m ethod 2) s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L50 will output the overhead bits, within the incoming e3 frames, via this pin. the receive overhead output interface will pulse the rxohenable output pin (for one rxout- clk period) at approximately the middle of the rxoh bit period. the user is advised to design the terminal equipment to latch the contents of the rxoh output pin, whenever the rxohen- able output pin is sampled "high on the falling edge of rxoutclk. rxohenable output receive overhead data output enable - output pin: the XRT72L50 will assert this output signal for one rxoutclk period when it is safe for the ter- minal equipment to sample the data on the rxoh output pin. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L50 will drive this output pin "high (for one period of the rxoh signal), whenever the first overhead bit, within a given e3 frame is being driven onto the rxoh output pin. rxoutclk output receive section output clock signal: this clock signal is derived from the rxlineclk signal (from the liu) for loop-timing applica- tions, and the txinclk signal (from a local oscillator) for local-timing applications. for e3 appli- cations, this clock signal will operate at 34.368mhz. the user is advised to design the terminal equipment to latch the contents of the rxoh pin, anytime the rxohenable output signal is sampled "high on the falling edge of this clock sig- nal. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 321 method 2 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound e3 data stream (via the receive overhead data output interface), then it is expected to do the following. 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input) on the falling edge of the rxoutclk clock signal, whenever the rxo- henable output signal is also sampled "high. 2. keep track of the number of times that the rxo- henable signal has been sampled "high since the last time the rxohframe was also sampled "high. by doing this, the terminal equipment will be able to keep track of which overhead bit is being output via the rxoh output pin. based upon this information, the terminal equipment will be able to derive some meaning from these overhead bits. 3. table 66 relates the number of rxohenable out- put pulses (that have occurred since both the rxohframe and the rxohenable pins were both sampled "high) to the e3 overhead bit that is being output via the rxoh output pin. f igure 147. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 2). rxoh rxohenable rxoutclk rxohframe e3_oh_in e3_oh_enable_in e3_clk_in rx_start_of_frame terminal equipment xrt72l5x e3 framer ic ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 322 figure 148 presents the typical behavior of the re- ceive overhead data output interface block, when method 2 is being used to sample the incoming e3 overhead bits. t able 66: t he r elationship between the n umber of r x ohe nable output pulses ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the XRT72L50 0 (clock edge is coincident with rxohframe being detected "high) fas pattern - bit 9 1 fas pattern - bit 8 2 fas pattern - bit 7 3 fas pattern - bit 6 4 fas pattern - bit 5 5 fas pattern - bit 4 6 fas pattern - bit 3 7 fas pattern - bit 2 8 fas pattern - bit 1 9 fas pattern - bit 0 10 a bit 11 n bit f igure 148. i llustration of the signals that are output via the r eceive o verhead d ata o utput i nter - face block ( for m ethod 2). rxoutclk rxohenable rxohframe rxoh bip - 4, bit 0 fas, bit 9 fas, bit 8 fas, bit 7 fas, bit 6 recommended sampling edges XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 323 5.3.5 the receive payload data output inter- face figure 149 presents a simple illustration of the re- ceive payload data output interface block. each of the output pins of the receive payload data output interface block are listed in table 67 and de- scribed below. the exact role that each of these out- put pins assume, for a variety of operating scenarios are described throughout this section. f igure 149. a s imple illustration of the r eceive p ayload d ata o utput i nterface block receive payload data output interface receive payload data output interface rxohind rxser rxnib[3:0] rxclk rxoutclk rxframe from receive e3 framer block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 324 t able 67: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i nterface block s ignal n ame t ype d escription rxser output receive serial payload data output pin: if the user opts to operate the XRT72L50 in the serial mode, then the chip will output the pay- load data, of the incoming e3 frames, via this pin. the XRT72L50 will output this data upon the rising edge of rxclk. the user is advised to design the terminal equipment such that it will sample this data on the falling edge of rxclk. this signal is only active if the nibint input pin is pulled "low". rxnib[3:0] output receive nibble-parallel payload data output pins: if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the chip will output the payload data, of the incoming e3 frames, via these pins. the XRT72L50 will output data via these pins, upon the falling edge of the rxclk output pin. the user is advised to design the terminal equipment such that it will sample this data upon the rising edge of rxclk. n ote : these pins are only active if the nibint input pin is pulled "high". rxclk output receive payload data output clock pin: the exact behavior of this signal depends upon whether the XRT72L50 is operating in the serial or in the nibble-parallel-mode. serial mode operation in the serial mode, this signal is a 34.368mhz clock output signal. the receive payload data output interface will update the data via the rxser output pin, upon the rising edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the rxser pin, upon the falling edge of this clock signal. nibble-parallel mode operation in this nibble-parallel mode, the XRT72L50 will derive this clock signal, from the rxlineclk signal. the XRT72L50 will pulse this clock 1060 times for each inbound e3 frame. the receive payload data output interface will update the data, on the rxnib[3:0] output pins upon the falling edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the rxnib[3:0] output pins, upon the rising edge of this clock signal rxohind output receive overhead bit indicator output: this output pin will pulse "high" whenever the receive payload data output interface outputs an overhead bit via the rxser output pin. the purpose of this output pin is to alert the terminal equipment that the current bit, (which is now residing on the rxser output pin), is an overhead bit and should not be processed by the terminal equipment. the XRT72L50 will update this signal, upon the rising edge of rxohind. the user is advised to design (or configure) the terminal equipment to sample this signal (along with the data on the rxser output pin) on the falling edge of the rxclk signal. n ote : for e3 applications, this output pin is only active if the XRT72L50 is operating in the serial mode. this output pin will be "low" if the device is operating in the nibble-parallel mode. rxframe output receive start of frame output indicator: the exact behavior of this pin, depends upon whether the XRT72L50 has been configured to operate in the serial mode or the nibble-parallel mode. serial mode operation: the receive section of the XRT72L50 will pulse this output pin "high" (for one bit period) when the receive payload data output interface block is driving the very first bit (or nibble) of a given e3 frame, onto the rxser output pin. nibble-parallel mode operation: the receive section of the XRT72L50 will pulse this output pin "high" for one nibble period, when the receive payload data output interface is driving the very first nibble of a given e3 frame, onto the rxnib[3:0] output pins. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 325 operation of the receive payload data output in- terface block the receive payload data output interface permits the user to read out the payload data of inbound e3 frames, via either of the following modes. ? serial mode ? nibble-parallel mode each of these modes are described in detail, below. 5.3.5.1 serial mode operation behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. payload data output the XRT72L50 will output the payload data, of the in- coming e3 frames via the rxser output pin, upon the rising edge of rxclk. delineation of inbound e3 frames the XRT72L50 will pulse the rxframe output pin "high" for one bit-period coincident with it driving the first bit within a given e3 frame, via the rxser output pin. interfacing the XRT72L50 to the receive terminal equipment figure 150 presents a simple illustration as how the user should interface the XRT72L50 to that terminal equipment which processes receive direction pay- load data. required operation of the terminal equipment the XRT72L50 will update the data on the rxser out- put pin, upon the rising edge of rxclk. hence, the terminal equipment should sample the data on the rxser output pin (or the e3_data_in pin at the termi- nal equipment) upon the rising edge of rxclk. as the terminal equipment samples rxser with each rising edge of rxclk it should also be sampling the follow- ing signals. ? rxframe ? rxohind the need for sampling rxframe the XRT72L50 will pulse the rxframe output pin "high" coincident with it driving the very first bit of a given e3 frame onto the rxser output pin. if knowl- edge of the e3 frame boundaries is important for the operation of the terminal equipment, then this is a very important signal for it to sample. the need for sampling rxohind the XRT72L50 will indicate that it is currently driving an overhead bit onto the rxser output pin, by pulsing the rxohind output pin "high". if the terminal equip- ment samples this signal "high", then it should know that the bit, that it is currently sampling via the rxser pin is an overhead bit and should not be processed. the behavior of the signals between the receive payload data output interface block and the ter- minal equipment the behavior of the signals between the XRT72L50 and the terminal equipment for e3 serial mode op- eration is illustrated in figure 151. f igure 150. i llustration of the t erminal e quipment being interfaced to the r eceive p ayload d ata i nput i nterface b lock of the XRT72L50 f ramer ic (s erial m ode o peration ) terminal equipment (receive payload section) xrt72l5x e3 framer e3_data_in rx_e3_clock_in rx_start_of_frame rxclk rxframe rxohind 34.368 mhz clock signal rxser rx_e3_oh_ind rxlineclk 34.368 mhz clock source ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 326 5.3.5.2 nibble-parallel mode operation behav- ior of the XRT72L50 if the XRT72L50 has been configured to operate in the nibble-parallel mode, then the XRT72L50 will be- have as follows. payload data output the XRT72L50 will output the payload data of the in- coming e3 frames, via the rxnib[3:0] output pins, up- on the rising edge of rxclk. n otes : 1. in this case, rxclk will function as the nibble clock signal between the XRT72L50 the terminal equip- ment. the XRT72L50 will pulse the rxclk output signal "high" 1060 times, for each inbound e3 frame. 2. unlike serial mode operation, the duty cycle of rxclk, in nibble-parallel mode operation is approx- imately 25%. delineation of inbound e3 frames the XRT72L50 will pulse the rxframe output pin "high" for one nibble-period coincident with it driving the very first nibble, within a given inbound e3 frame, via the rxnib[3:0] output pins. interfacing the XRT72L50 the terminal equip- ment. figure 152 presents a simple illustration as how the user should interface the XRT72L50 to that terminal equipment which processes receive direction pay- load data. f igure 151. a n i llustration of the behavior of the signals between the r eceive p ayload d ata o ut - put i nterface block of the XRT72L50 and the t erminal e quipment terminal equipment signals e3_clock_in e3_data_out rx_start_of_frame e3_overhead_ind xrt72l5x receive payload data i/f signals rxclk rxser rxframe rxoh_ind payload[1522] payload[1523] fas , bit 9 fas, bit 8 payload[1522] payload[1523] fas, bit 9 fas, bit 8 note: fas pattern will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: rxframe pulses high to denote e3 frame boundary. note: rxoh_ind pulses high for 12 bit-periods in order to denote overhead data (e.g., the fas pattern, the a and n bits). XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 327 required operation of the terminal equipment the XRT72L50 will update the data on the rxnib[3:0] line, upon the rising edge of rxclk. hence, the ter- minal equipment should sample the data on the rx- nib[3:0] output pins (or the e3_data_in[3:0] input pins at the terminal equipment) upon the rising edge of rxclk. as the terminal equipment samples rxser with each rising edge of rxclk it should also be sam- pling the rxframe signal. the need for sampling rxframe the XRT72L50 will pulse the rxframe output pin "high" coincident with it driving the very first nibble of a given e3 frame, onto the rxnib[3:0] output pins. if knowledge of the e3 frame boundaries is important for the operation of the terminal equipment, then this is a very important signal for it to sample. the behavior of the signals between the receive payload data output interface block and the ter- minal equipment the behavior of the signals between the XRT72L50 and the terminal equipment for e3 nibble-mode op- eration is illustrated in figure 153. f igure 152. i llustration of the XRT72L50 ds3/e3 f ramer ic being interfaced to the r eceive s ection of the t erminal e quipment (n ibble -p arallel m ode o peration ) terminal equipment (receive payload section) xrt72l5x e3 framer e3_data_in[3:0] rx_e3_clock_in rx_start_of_frame rxclk rxframe 8.592 mhz clock signal rxnib[3:0] rxlineclk 34.368 mhz clock source rxoh_ind rx_e3_oh_ind ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 328 5.3.6 receive section interrupt processing the receive section of the XRT72L50 can generate an interrupt to the microcontroller/microprocessor for the following reasons. ? change in receive los condition ? change in receive oof condition ? change in receive lof condition ? change in receive ais condition ? change in receive ferf condition ? change of framing alignment ? detection of febe (far-end block error) event ? detection of bip-4 error ? detection of framing error ? reception of a new lapd message 5.3.6.1 enabling receive section interrupts as mentioned in section 1.6, the interrupt structure within the XRT72L50 contains two hierarchical levels. ? block level ? source level the block level the enable state of the block level for the receive section interrupts dictates whether or not interrupts (if enabled at the source level), are actually enabled. the user can enable or disable these receive sec- tion interrupts, at the block level by writing the appro- priate data into bit 7 (rx ds3/e3 interrupt enable) within the block interrupt enable register (address = 0x04), as illustrated below. f igure 153. i llustration of the signals that are output via the r eceive p ayload d ata o utput i nter - face block ( for n ibble -p arallel m ode o peration ). xrt72l5x receive payload data i/f signals e3 frame number n e3 frame number n + 1 note: rxframe pulses high to denote e3 frame boundary. terminal equipment signals rxoutclk rx_start_of_frame rx_e3_clock_in e3_data_in[3:0] overhead nibble [0] overhead nibble [1] rxoutclk rxframe rxclk rxnib[3:0] overhead nibble [0] overhead nibble [1] recommended sampling edge of terminal equipment rx_e3_oh_ind rxoh_ind XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 329 setting this bit-field to 1 enables the receive sec- tion at the block level) for interrupt generation. con- versely, setting this bit-field to 0 disables the re- ceive section for interrupt generation. 5.3.6.2 enabling/disabling and servicing inter- rupts as mentioned previously, the receive section of the XRT72L50 framer ic contains numerous interrupts. the enabling/disabling and servicing of each of these interrupts is described below. 5.3.6.2.1 the change in receive los condi- tion interrupt if the change in receive los condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares an los (loss of signal) condition, and 2. when the XRT72L50 framer ic clears the los condition. conditions causing the XRT72L50 framer ic to declare an los condition. ? if the xrt7300 liu ic declares an los condition, and drives the rlos input pin (of the XRT72L50 framer ic) high. ? if the XRT72L50 framer ic detects 32 consecutive 0, via the rxpos and rxneg input pins. conditions causing the XRT72L50 framer ic to clear the los condition. ? if the xrt7300 liu ic clears the los condition and drives the rlos input pin (of the XRT72L50 framer ic) low. ? if the XRT72L50 framer ic detects a string of 32 consecutive bits (via the rxpos and rxneg input pins) that does not contain a string of 4 consecu- tive 0s. enabling and disabling the change in receive los condition interrupt the user can enable or disable the change in re- ceive los condition interrupt, by writing the appro- priate value into bit 1 (los interrupt enable), within the rxe3 interrupt enable register - 1, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive los condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 1 (los interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one-second interrupt enable r/wrororororor/wr/w x0000000 rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000000x0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 330 whenever the users system encounters the change in receive los condition interrupt, then it should do the following. 1. it should determine the current state of the los condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the los defect. hence, the user can determine the current state of the los defect by reading the state of bit 4 (rxlos) within the rx e3 configuration and status regis- ter - 2, as illustrated below. if the los state is true 1. it should transmit a ferf (far-end-receive fail- ure) indicator to the remote terminal equipment. please see section 4.2.4.2.1.3 on how to config- ure the XRT72L50 to transmit a ferf indicator to the remote terminal equipment. if the los state is false 1. it should cease transmitting the ferf indication to the remote terminal equipment. please see section 4.2.4.2.1.3 on how to control the state of the a bit, which is transmitted on each outbound e3 frame. 5.3.6.2.2 the change in receive oof condi- tion interrupt if the change in receive oof condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares an oof (out of frame) condition, and 2. when the XRT72L50 framer ic clears the oof condition. conditions causing the XRT72L50 framer ic to declare an oof condition. ? if the receive e3 framer block (within the XRT72L50 framer ic) detects framing bit errors, within four consecutive incoming e3 frames. conditions causing the XRT72L50 framer ic to clear the oof condition. ? if the receive e3 framer block (within the XRT72L50 framer ic) transitions from the fas pat- tern verification state to the in-frame state (see figure 115). ? if the receive e3 framer block transitions from the oof condition state to the in-frame state (see fig- ure 115). enabling and disabling the change in receive oof condition interrupt the user can enable or disable the change in re- ceive oof condition interrupt, by writing the appro- priate value into bit 3 (oof interrupt enable), within rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000010 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 331 the rxe3 interrupt enable register - 1, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive oof condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 3 (oof interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. whenever the users system encounters the change in receive oof condition interrupt, then it should do the following. 1. it should determine the current state of the oof condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the oof defect. hence, the user can determine the current state of the los defect by reading the state of bit 5 (rxoof) within the rx e3 configuration and status regis- ter - 2, as illustrated below. if the oof state is true 1. it should transmit a ferf (far-end-receive fail- ure) indicator to the remote terminal equipment. please see section 4.2.4.2.1.3 on how to config- ure the XRT72L50 to transmit the ferf indicator to the remote terminal equipment. if the oof state is false 1. it should cease transmitting the ferf indication to the remote terminal equipment. please see section 4.2.4.2.1.3 on how to control the state of the a bit, which is transmitted via each out- bound e3 frame. rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 0000x0x0 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00001000 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo xxxxxxxx ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 332 5.3.6.2.3 the change in receive lof condi- tion interrupt if the change in receive lof condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares an lof (out of frame) condition, and 2. when the XRT72L50 framer ic clears the lof condition. conditions causing the XRT72L50 framer ic to declare an lof condition. ? if the receive e3 framer block (within the XRT72L50 framer ic) detects framing bit errors, within four consecutive incoming e3 frames, and is not capable of transition back into the in-frame state within a 1ms or 3ms period. conditions causing the XRT72L50 framer ic to clear the lof condition. ? if the receive e3 framer block transitions from the oof condition state to the lof condition state (see figure 115). ? if the receive e3 framer block transitions back into the in-frame state. enabling and disabling the change in receive lof condition interrupt the user can enable or disable the change in re- ceive lof condition interrupt, by writing the appropri- ate value into bit 3 (lof interrupt enable), within the rxe3 interrupt enable register - 1, as indicated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive lof condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 6 (lof interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. 5.3.6.2.4 the change in receive ais condition interrupt if the change in receive ais condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares an ais (loss of signal) condition, and 2. when the XRT72L50 framer ic clears the ais condition. conditions causing the XRT72L50 framer ic to declare an ais condition. ? if the XRT72L50 framer ic detects 7 or less 0 within 2 consecutive e3 frames. conditions causing the XRT72L50 framer ic to clear the ais condition. rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000000x0 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 333 ? if the XRT72L50 framer ic detects 2 consecutive e3 frames that each contain 8 or more 0s. enabling and disabling the change in receive ais condition interrupt the user can enable or disable the change in re- ceive los condition interrupt, by writing the appro- priate value into bit 0 (ais interrupt enable), within the rxe3 interrupt enable register - 1, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive ais condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 0 (ais interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. whenever the users system encounters the change in receive ais condition interrupt, then it should do the following. 1. it should determine the current state of the ais condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the ais defect. hence, the user can determine the current state of the ais defect by reading the state of bit 3 (rxais) within the rx e3 configuration and status register - 2, as illustrated below. if the ais condition is true 1. it should begin transmitting the ferf indication to the remote terminal equipment. please see section 4.2.4.2.1.3 for instructions on how to transmit a ferf condition. if the ais condition is false 2. it should cease transmitting the ferf indication to the remote terminal equipment. please see section 4.2.4.2.1.3 for instructions on how to con- trol the state of the a bit-field, within each out- bound e3 frame. 5.3.6.2.5 the change of framing alignment interrupt if the change of framing alignment interrupt is en- abled then the XRT72L50 framer ic will generate an interrupt any time the receive e3 framer block de- tects an abrupt change of framing alignment. n ote : this interrupt is typically accompanied with the change in receive oof condition interrupt as well. conditions causing the XRT72L50 framer ic to generate this interrupt. if the XRT72L50 framer detects receives at least four consecutive e3 frames, within its framing alignment bytes in error, then the XRT72L50 framer ic will de- clare an oof condition. however, while the XRT72L50 framer ic is operating in the oof condi- rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000000x0 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 334 tion, it will still rely on the old framing alignment for e3 payload data extraction, etc. however, if the receive e3 framer had to change alignment, in order to re-acquire frame synchroniza- tion, then this interrupt will occur. enabling and disabling the change of framing alignment interrupt the user can enable or disable the change of fram- ing alignment interrupt by writing the appropriate val- ue into bit 4 (cofa interrupt enable), within the rx e3 interrupt enable register - 1. writing a 1 into this bit-field enables the change of framing alignment interrupt. conversely, writing a 0 into this bit-field disables the change of framing alignment interrupt. servicing the change of framing alignment inter- rupt whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ) by driving it low. ? it will set bit 4 (cofa interrupt status), within the rx e3 interrupt status register -1, to 1, as indi- cated below. 5.3.6.2.6 the change in receive ferf condi- tion interrupt if the change in receive ferf condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares a ferf (far-end receive failure) condition, and 2. when the XRT72L50 framer ic clears the ferf condition. conditions causing the XRT72L50 framer ic to declare an ferf condition. ? if the XRT72L50 framer ic begins receiving e3 frames which have the a bit set to 1). conditions causing the XRT72L50 framer ic to clear the ais condition. ? if the XRT72L50 framer ic begins receiving e3 frames that do not have the a bit set to 1. enabling and disabling the change in receive ais condition interrupt the user can enable or disable the change in re- ceive ferf condition interrupt, by writing the appro- priate value into bit 3 (ferf interrupt enable), within rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000x0000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00010000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 335 the rxe3 interrupt enable register - 2, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive ferf condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 3 (ferf interrupt status), within the rx e3 interrupt status register - 2 to 1, as indi- cated below. whenever the users system encounters the change in receive ferf condition interrupt, then it should do the following. 1. it should determine the current state of the ferf condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the ferf defect. hence, the user can determine the current state of the los defect by reading the state of bit 0 (rxferf) within the rx e3 configuration and status regis- ter - 2, as illustrated below. 5.3.6.2.7 the detection of bip-4 error interrupt if the detection of bip-4 error interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt, anytime the receive e3 framer block has de- tected an error in the bip-4 nibble, within an incom- ing e3 frame. n ote : this interrupt is only active if the XRT72L50 framer ic has been configured to process the bip-4 nibble within each incoming and outbound e3 frame. rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt enable bip-4 error interrupt enable framing error interrupt enable not used r/w ro ro ro r/w r/w r/w ro 00000000 rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt status bip-4 error interrupt status framing error interrupt status not used ro ro ro ro rur rur rur rur 00001000 rxe3 configuration & status register - 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxlof algo rxlof rxoof rxlos rxais not used rxferf r/wrororororororo 01100111 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 336 enabling and disabling the detection of febe event interrupt the user can enable or disable the detection of bip-4 error interrupt by writing the appropriate value into bit 2 (bip-4 interrupt enable) within the rx e3 inter- rupt enable register - 2, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of the bip-4 error inter- rupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do the following. ? it will assert the interrupt request output pin (int ), by driving it high. ? it will set the bit 2 (bip-4 interrupt status), within the rxe3 interrupt status register - 2 as indicated below. whenever the terminal equipment encounters the detection of bip-4 error interrupt, it should do the fol- lowing. ? it should read the contents of the pmon parity error event count registers (located at addresses 0x54 and 0x55) in order to determine the number of bip-4 errors that have been received by the XRT72L50 framer ic. 5.3.6.2.8 the detection of framing error inter- rupt if the detection of framing error interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt, anytime the receive e3 framer block has re- ceived an e3 frame with an incorrect fas pattern val- ue. enabling and disabling the detection of febe event interrupt the user can enable or disable the detection of framing error interrupt by writing the appropriate val- ue into bit 1 (framing error interrupt enable) within rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt enable bip-4 error interrupt enable framing error interrupt enable not used r/w ro ro ro r/w r/w r/w ro 00000x00 rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt status bip-4 error interrupt status framing error interrupt status not used ro ro ro ro rur rur rur rur 00000100 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 337 the rx e3 interrupt enable register - 2, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of framing error interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do the following. ? it will assert the interrupt request output pin (int ), by driving it high. ? it will set the bit 1 (framing error interrupt status), within the rxe3 interrupt status register - 2 as indicated below. whenever the terminal equipment encounters the detection of framing error interrupt, it should do the following. ? it should read the contents of the pmon framing bit/byte error count registers (located at addresses 0x52 and 0x53) in order to determine the number of framing errors that have been received by the XRT72L50 framer ic. 5.3.6.2.9 the receipt of new lapd message interrupt if the receive lapd message interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt anytime the receive hdlc controller block has received a new lapd message frame from the re- mote terminal equipment, and has stored the con- tents of this message into the receive lapd mes- sage buffer. enabling/disabling the receive lapd message interrupt the user can enable or disable the receive lapd message interrupt by writing the appropriate data into bit 1 (rxlapd interrupt enable) within the rx e3 lapd control register, as indicated below. rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt enable bip-4 error interrupt enable framing error interrupt enable not used r/w ro ro ro r/w r/w r/w ro 000000x0 rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ferf interrupt status bip-4 error interrupt status framing error interrupt status not used ro ro ro ro rur rur rur rur 00000000 rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt enable ro ro ro ro ro r/w r/w rur 00000 0 0 0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 338 writing a 1 into this bit-field enables the receive lapd message interrupt. conversely, writing a 0 into this bit-field disables the receive lapd message interrupt. servicing the receive lapd message interrupt whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 0 (rxlapd interrupt status), within the rx e3 lapd control register to 1, as indicated below. ? it will write the contents of the newly received lapd message into the receive lapd message buffer (located at 0xde through 0x135). whenever the terminal equipment encounters the receive lapd message interrupt, then it should read out the contents of the receive lapd message buff- er, and respond accordingly. rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt enable ro ro ro ro ro r/w r/w rur 00000 0 0 0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 339 6.0 e3/itu-t g.832 operation of the XRT72L50 configuring the XRT72L50 to operate in the e3, itu-t g.832 mode the XRT72L50 can be configured to operate in the e3/itu-t g.832 mode by writing a 0 into bit-field 6 and a 1 into bit-field 2, within the framer operating mode register, as illustrated below. prior to describing the functional blocks within the transmit and receive sections of the XRT72L50, it is important to describe the e3, itu-t g.832 framing format. 6.1 d escription of the e3, itu-t g.832 f rames and a ssociated o verhead b ytes the role of the various overhead bytes are best de- scribed by discussing the e3, itu-t g.832 frame format as a whole. the e3, itu-t g.832 frame con- tains 537 bytes, of which 7 bytes are overhead and the remaining 530 bytes are payload bytes. these 537 octets are arranged in 9 rows of 60 col- umns each, except for the last three rows which con- tain only 59 columns. the frame repetition rate for this type of e3 frame is 8000 times per second, there- by resulting in the standard e3 bit rate of 34.368 mbps. figure 154 presents an illustration of the e3, itu-t g.832 frame format. 6.1.1 definition of the overhead bytes the seven (7) overhead bytes are shown in figure 154, as fa1, fa2, em, tr, ma, nr and gc. each of these overhead bytes are further defined be- low. framer operating mode register (address = 0x00) b it 7 b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w x 0x 0 x 1xx f igure 154. i llustration of the e3, itu-t g.832 f raming f ormat . fa1 fa2 em tr ma 1 byte 59 bytes 60 columns 9 rows 530 octet payload gc nr ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 340 6.1.1.1 frame alignment (fa1 and fa2) bytes fa1 and fa2 are known as the frame alignment bytes. the receive e3 framer, while trying to ac- quire or maintain framing synchronization with its in- coming e3 frames, will attempt to locate these two bytes. fa1 is assigned the value 0xf6 and fa2 is assigned the value 0x28. 6.1.1.2 error monitor (em) byte the em byte contains the results of bip-8 (bit-inter- leaved parity) calculations over an entire e3 frame. the bit interleaved parity (bip-8) byte field supports error detection, during the transmission of e3 frames, between the local terminal equipment and the re- mote terminal equipment. the transmit e3 framer will compute the bip-8 value over the 537 octet structure, within each e3 frame. the resulting bip-8 value is then inserted into the em byte-field within the very next e3 frame. bip-8 is an eight bit code in which the nth bit of the bip-8 code reflects the even-parity bit calculated with the nth bit of each of the 537 octets within the e3 frame. thus, the bip-8 value presents the results for 8 separate even-bit parity calculations. the receive e3 framer will compute its own version of the em bytes for each e3 frame that it receives. af- terwards, it will compare the value of its locally com- puted em byte with the em byte that it receives in the very next e3 frame. if the two em byte values are equal, then the receive e3 framer will conclude that this e3 frame was received in an error-free manner. further, the receive e3 framer will block will inform the remote terminal equipment of this fact by having the local terminal equipment set the febe (far- end-block error) bit, within the ma byte of an out- bound e3 frame (to the remote terminal equipment) to 0. please see section 5.1.1 for a discussion of the ma byte. however, if the receive e3 framer block detects an error in the incoming em byte, then it will conclude that the corresponding e3 frame is errored. further, the receive e3 framer block will inform the remote terminal (e.g., the source of this erred e3 frame) of this fact by having the local terminal equipment (e.g., the transmit e3 framer block) set the febe bit, within an outbound e3 frame (destined to the re- mote terminal) to 1. n ote : a detailed discussion on the practical use of the em byte is presented in section 5.2.2. 6.1.1.3 the trail-trace buffer (ttb) byte this byte-field is used to repetitively transmit a trail- access point identifier so that a trail receiving terminal can verify its continued connection to the intended transmitter. the trail access point identifier uses the 16-byte numbering format as tabulated in table 68. framer operating mode register (address = 0x00) b it 7 b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w x 1x 0x xxx t able 68: d efinition of the t rail t race b uffer b ytes , within t he e3, itu-t g.832 f raming f ormat t rail t race b its b yte n umber b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 1 (frame start marker) 1 c6c5c4c3c2c1c0 2 xxxxxxxx * xxxxxxxx * xxxxxxxx 16 xxxxxxxx XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 341 the first byte of this 16-byte string is a frame start marker and is typically of the form [1, c6, c5, c4, c3, c2, c1, c0]. the 1 in the msb (most significant bit) of this first byte is used to identify this byte as the frame start marker (e.g., the first byte of the 16-byte trail trace buffer sequence). the bits: c6 through c0 are the results of a crc-7 calculation over the previous 16-byte frame. the subsequent 15 bytes are used for the transport of 15 ascii characters re- quired for the e.164 numbering format. 6.1.1.4 maintenance and adaptation (ma) byte the ma byte is responsible for carrying the ferf (far-end receive failure) and the febe (far-end block error) status indicators from one terminal to an- other. the ma byte-field also carries the payload type, the payload dependent and the timing marker indicators. the byte format for the ma byte is pre- sented below. bit 7 - ferf (far-end receive failure) if the receive e3 framer block (at a local terminal) is experiencing problems receiving e3 frame data from a remote terminal (e.g., an los, oof or ais condition), then it will inform the remote terminal equipment of this fact by commanding the local transmit e3 framer block to set the ferf bit-field (within the ma byte) of an outbound e3 frame, to 1. the local transmit e3 framer block will continue to set the ferf bit-field (within the subsequent out- bound e3 frames) to 1 until the receive e3 framer block no longer experiences problems in receiving the e3 frame data. if the remote terminal equipment re- ceives a certain number of consecutive e3 frames, with the ferf bit-field set to 1, then the remote terminal equipment will interpret this signaling as an indication of a far-end receive failure (e.g., a prob- lem with the local terminal equipment). conversely, if the receive e3 framer block (at a lo- cal terminal equipment) is not experiencing any problems receiving e3 frame data from a remote ter- minal equipment, then it will also inform the remote terminal equipment of this fact by commanding the local transmit e3 framer block to set the ferf bit- field (within the ma byte-field) of an outbound e3 frame (which is destined for the remote terminal) to 0. the remote terminal equipment will interpret this form of signaling as an indication of a normal op- eration. n ote : a detailed discussion into the practical use of the ferf bit-field is presented in section 5.2.4.2. bit 6 - febe (far-end block error) if a local receive e3 framer block detects an error in the em byte, within an incoming e3 frame that it has received from the remote terminal equipment, then it will inform the remote terminal equipment of this error by commanding the local transmit e3 framer block to set the febe bit-field (within the ma byte- field) of an outbound e3 frame (which is destined for the remote terminal equipment) to 1. the remote terminal equipment will interpret this signaling as an indication that the e3 frames that it is transmitting back out to the local receive e3 framer block are erred. conversely, if the local receive e3 framer block does not detect any errors in the em byte, within the incoming e3 frame, then it will also inform the re- mote terminal equipment of this fact by commanding the local transmit e3 framer block to set the febe bit-field of an outbound e3 frame (which is destined for the remote terminal equipment) to 0. n ote : a detailed discussion into the practical use of the febe bit-field is presented in section 5.2.4.2. bits 5 - 3 payload type these bit-fields indicates to the remote terminal equipment, what kind of data is being transported in the 530 bytes of e3 frame payload data. some of the defined payload type values are tabulated in table 69. the maintenance and adaptation (ma) byte format b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ferf febe payload type payload dependent timing marker ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 342 bits 2 - 1 payload dependent to be provided later. bit 0 - timing marker this bit-field is set to 0 to indicate that the timing source is traceable to a primary reference clock. otherwise, this bit-field is set to 1. 6.1.1.5 the network operator (nr) byte the nr byte or the gc byte can be configured to transport lap-d message frame octets from the lapd transmitter to the lapd receiver (of the re- mote terminal equipment) at a data rate of 64kbps (1 byte per e3 frame). if the user opts not to use the nr byte to transport these lapd message frames, then the transmit e3 framer block will read in the contents of the txnr byte register (address = 0x37), and insert this value into the nr byte-field of each outbound e3 frame. the receive e3 framer block will read in the contents of the nr byte-field within each incoming e3 frame and will write it into the rxnr byte register. conse- quently, the user can determine the value of the nr byte, within the most recently received e3 frame by reading the rx nr byte register (address = 0x1a). 6.1.1.6 the general purpose communica- tions channel (gc) byte the nr byte or the gc byte can be configured to transport lapd message frames from the lapd transmitter to the lapd receiver (of the remote ter- minal equipment) at a data rate of 64kbps (1 byte per e3 frame). if the user opts not to use the gc byte to transport these lapd message frames, then the transmit e3 framer block will read in the contents of the tx gc byte register (address = 0x35), and insert this value into the gc byte-field of each outbound e3 frame. the receive e3 framer block will read in the contents of the gc byte-field, within each incoming e3 frame, and will write it into the rxgc byte register. conse- quently, the user can determine the value of the gc byte, within the most recently received e3 frame, by reading the rx gc byte register (address = 0x1b). 6.2 t he t ransmit s ection of the XRT72L50 (e3 m ode o peration ) when the XRT72L50 has been configured to operate in the e3, itu-t g.832 mode, the transmit section of the XRT72L50 consists of the following functional blocks. ? transmit payload data input interface block ? transmit overhead data input interface block ? transmit e3 framer block ? transmit hdlc controller block ? transmit liu interface block figure 155 presents a simple illustration of the trans- mit section of the XRT72L50 framer ic. t able 69: a l isting of the v arious p ayload t ype v alues and their corresponding m eaning p ayload t ype v alue m eaning 000 unequipped 001 equipped 010 atm cells 011 sdh tu-12s XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 343 each of these functional blocks will be discussed in detail in this document. 6.2.1 the transmit payload data input interface block figure 156 presents a simple illustration of the trans- mit payload data input interface block. f igure 155. a s imple i llustration of the t ransmit s ection , within the XRT72L50, when it has been configured to operate in the e3 m ode transmit payload data input interface block transmit ds3/e3 framer block transmit liu interface block txser txnib[3:0] txinclk txpos txneg txlineclk transmit overhead input interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe tx e3 hdlc controller/buffer tx e3 hdlc controller/buffer from microprocessor interface block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 344 each of the input and output pins of the transmit pay- load data input interface are listed in table 70 and described below. the exact role that each of these inputs and output pins assume, for a variety of operat- ing scenarios are described throughout this section. f igure 156. a s imple i llustration of the t ransmit p ayload d ata i nput i nterface b lock transmit payload data input interface block transmit payload data input interface block txoh_ind txser txnib[3:0] txinclk txnibclk txframe txframeref to transmit e3 framer block XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 345 t able 70: l isting and d escription of the pins associated with the t ransmit p ayload d ata i nput i nterface s ignal n ame t ype d escription txser input transmit serial payload data input pin: if the user opts to operate the XRT72L50 in the serial mode, then the terminal equipment is expected to apply the payload data (that is to be transported via the outbound e3 data stream) to this input pin. the XRT72L50 will sample the data that is at this input pin upon the rising edge either the rxoutclk or the txinclk signal (whichever is appropriate). n ote : this signal is only active if the nibint input pin is pulled "low". txnib[3:0] input transmit nibble-parallel payload data input pins: if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the terminal equip- ment is expected to apply the payload data (that is to be transported via the outbound e3 data stream) to these input pins. the XRT72L50 will sample the data that is at these input pins upon the rising edge of the txnibclk signal. n ote : these pins are only active if the nibint input pin is pulled "high". txinclk input transmit section timing reference clock input pin: the transmit section of the XRT72L50 can be configured to use this clock signal as the timing reference. if the user has made this configuration selection, then the XRT72L50 will use this clock signal to sample the data on the txser input pin. n ote : if this configuration is selected, then a 34.368 mhz clock signal must be applied to this input pin. txnibclk output transmit nibble mode output if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the XRT72L50 will derive this clock signal from the selected timing reference for the transmit section of the chip (e.g., either the txinclk or the rxlineclk signals). the XRT72L50 will use this signal to sample the data on the txnib[3:0] input pins. txohind output transmit overhead bit indicator output: this output pin will pulse "high" one-bit period prior to the time that the transmit section of the XRT72L50 will be processing an overhead bit. the purpose of this output pin is to warn the terminal equipment that, during the very next bit-period, the XRT72L50 is going to be process- ing an overhead bit and will be ignoring any data that is applied to the txser input pin. txframe output transmit end of frame output indicator: the transmit section of the XRT72L50 will pulse this output pin "high" (for one bit-period), when the transmit payload data input interface is processing the last bit of a given e3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin trans- mission of a new e3 frame to the XRT72L50 (e.g., to permit the XRT72L50 to maintain transmit e3 framing alignment control over the terminal equipment). txframeref input transmit frame reference input: the XRT72L50 permits the user to configure the transmit section to use this input pin as a frame reference. if the user makes this configuration selection, then the transmit section will initiate its transmission of a new e3 frame, upon the rising edge of this signal. the purpose of this input pin is to permit the terminal equipment to maintain transmit e3 fram- ing alignment control over the XRT72L50. rxoutclk output loop-timed timing reference clock output pin: the transmit section of the XRT72L50 can be configured to use the rxlineclk signal as the timing reference (e.g., loop-timing). if the user has made this configuration selection, then the XRT72L50 will: ? output a 34.368 mhz clock signal via this pin, to the terminal equipment. ? sample the data on the txser input pin, upon the rising edge of this clock signal. ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 346 operation of the transmit payload data input in- terface the transmit terminal input interface is extremely flexible, in that it permits the user to make the follow- ing configuration options. ? the serial or the nibble-parallel interface mode ? the loop-timing or the txinclk (local timing) mode further, if the XRT72L50 has been configured to op- erate in the txinclk mode, then the user has two ad- ditional options. ? the XRT72L50 is the frame master (e.g., it dictates when the terminal equipment will initiate the trans- mission of data within a new e3 frame). ? the XRT72L50 is the frame slave (e.g., the termi- nal equipment will dictate when the XRT72L50 ini- tiates the transmission of a new e3 frame). given these three set of options, the transmit termi- nal input interface can be configured to operate in one of the six (6) following modes. ? mode 1 - serial/loop-timed mode ? mode 2 - serial/local-timed/frame slave mode ? mode 3 - serial/local-timed/frame master mode ? mode 4 - nibble/loop-timed mode ? mode 5 - nibble/local-timed/frame slave mode ? mode 6 - nibble/local-timed/frame master mode each of these modes are described, in detail, below. 6.2.1.1 mode 1 - the serial/loop-timing mode the behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. a. loop-timing (uses the rxlineclk signal as the timing reference) since the XRT72L50 is configured to operate in the loop-timed mode, the transmit section (of the XRT72L50) will use the rxlineclk input clock signal (e.g., the recovered clock signal, from the liu) as its timing source. when the XRT72L50 is operating in this mode it will do the following. 1. it will ignore any signal at the txinclk input pin. 2. the XRT72L50 will output a 34.368mhz clock signal via the rxoutclk output pin. this clock signal functions as the transmit payload data input interface block clock signal. 3. the XRT72L50 will use the rising edge of the rxoutclk signal to latch in the data residing on the txser input pin. b. serial mode the XRT72L50 will accept the e3 payload data from the terminal equipment, in a serial-manner, via the txser input pin the transmit payload data input in- terface will latch this data into its circuitry, on the ris- ing edge of the rxoutclk output clock signal. c. delineation of outbound e3 frames the XRT72L50 will pulse the txframe output pin "high" for one bit-period, coincident with the XRT72L50 processing the last bit of a given e3 frame. d. sampling of payload data, from the terminal equipment in mode 1, the XRT72L50 will sample the data at the txser input, on the rising edge of rxoutclk. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 1 operation figure 157 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 1 operation. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 347 mode 1 operation of the terminal equipment when the XRT72L50 is operating in this mode it will function as the source of the 34.368mhz clock signal. this clock signal will be used as the terminal equip- ment interface clock by both the XRT72L50 ic and the terminal equipment. the terminal equipment will serially output the pay- load data of the outbound e3 data stream via its e3_data_out pin. the terminal equipment will up- date the data on the e3_data_out pin upon the rising edge of the 34.368 mhz clock signal, at its e3_clock_in input pin (as depicted in figures 19 and 20). the XRT72L50 will latch the outbound e3 data stream (from the terminal equipment) on the rising edge of the rxoutclk signal. the XRT72L50 will indicate that it is processing the last bit, within a given outbound e3 frame, by pulsing its txframe output pin high for one bit-period. when the terminal equipment detects this pulse at its tx_start_of_frame input, it is expected to begin transmission of the very next outbound e3 frame to the XRT72L50 via the e3_data_out (or txser pin). finally, the XRT72L50 will indicate that it is about to process an overhead bit by pulsing the txoh_ind output pin "high" one bit period prior to its processing of an oh (overhead) bit. in figure 157, the txoh_ind output pin is connected to the e3_overhead_ind input pin, of the terminal equip- ment. whenever the e3_overhead_ind pin is pulsed "high" the terminal equipment is expected to not transmit a e3 payload bit upon the very next clock edge. instead, the terminal equipment is expected to delay its transmission of the very next payload bit, by one clock cycle. the behavior of the signals, between the XRT72L50 and the terminal equipment, for e3 mode 1 operation is illustrated in figure 158. f igure 157. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 1 (s erial /l oop -t imed ) o peration terminal equipment (receive payload section) xrt72l5x e3 framer e3_data_out e3_clock_in tx_start_of_frame rxoutclk txframe txoh_ind 34.368 mhz clock signal txser e3_oh_ind nibint ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 348 how to configure the XRT72L50 into the serial/ loop-timed/non-overhead interface mode 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit fields (within the framer operating mode register) to "00" as illus- trated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 157. 6.2.1.2 mode 2 - the serial/local-timed/ frame-slave mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows. a. local timing - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal as its timing reference. b. serial mode the XRT72L50 will receive the e3 payload data, in a serial manner, via the txser input pin. the transmit payload data input interface (within the XRT72L50) will latch this data into its circuitry, on the rising edge of the txinclk input clock signal. c. delineation of outbound e3 frames (frame slave mode) f igure 158. b ehavior of the t erminal i nterface signals between the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 and the t erminal e quipment ( for m ode 1 o peration ) terminal equipment signals e3_clock_in e3_data_out tx_start_of_frame e3_overhead_ind xrt72l5x transmit payload data i/f signals rxoutclk txser txframe txoh_ind payload[4238] payload[4239] fa1, bit 7 fa1, bit 6 payload[4238] payload[4239] fa1, bit 7 fa1, bit 6 note: the fa1 byte will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: txframe pulses high to denote e3 frame boundary. note: txoh_ind pulses high for 16 bit periods in order to denote overhead data (e.g., the fa1 and fa2 bytes) framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 0 0 0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 349 the transmit section of the XRT72L50 will use the txinclk input as its timing reference, and will use the txframeref input signal as its framing reference. in other words, the transmit section of the XRT72L50 will initiate frame generation upon the rising edge of the txframeref input signal). d. sampling of payload data, from the terminal equipment in mode 2, the XRT72L50 will sample the data, at the txser input pin, on the rising edge of txinclk. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 2 operation figure 159 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 2 operation. mode 2 operation of the terminal equipment as shown in figure 159, both the terminal equipment and the XRT72L50 will be driven by an external 34.368mhz clock signal. the terminal equipment will receive the 34.368mhz clock signal via its e3_clock_in input pin, and the XRT72L50 framer ic will receive the 34.368mhz clock signal via the txin- clk input pin. the terminal equipment will serially output the pay- load data of the outbound e3 data stream, via the e3_data_out output pin, upon the rising edge of the signal at the e3_clock_in input pin. (note: the e3_data_out output pin of the terminal equipment is electrically connected to the txser input pin). the XRT72L50 framer ic will latch the data, residing on the txser input line, on the rising edge of the txinclk signal. in this case, the terminal equipment has the respon- sibility of providing the framing reference signal by pulsing its tx_start_of_frame output signal (and in turn, the txframeref input pin of the XRT72L50), high for one-bit period, coincident with the first bit of a new e3 frame. once the XRT72L50 detects the ris- ing edge of the input at its txframeref input pin, it will begin generation of a new e3 frame. n otes : 1. in this case, the terminal equipment is controlling the start of frame generation, and is therefore referred to as the frame master. conversely, since the XRT72L50 does not control the generationi of a new e3 frame, but is rather driven by the terminal equipment, the XRT72L50 is referred to as the frame slave. 2. if the user opts to configure the XRT72L50 to oper- ate in mode 2, it is imperative that the tx_start_of_frame (or txframeref) signal is syn- chronized to the txinclk input clock signal. finally, the XRT72L50 will pulse its txoh_ind output pin, one bit-period prior to it processing a given over- head bit, within the outbound e3 frame. since the txoh_ind output pin (of the XRT72L50) is electrically connected to the e3_overhead_ind, whenever the XRT72L50 pulses the txoh_ind output pin "high", it f igure 159. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 2 (s erial /l ocal -t imed /f rame -s lave ) o peration terminal equipment xrt72l5x e3 framer e3_data_out e3_clock_in tx_start_of_frame txser txframeref nibint 34.368mhz clock source txinclk e3_overhead_ind txoh_ind ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 350 will also be driving the e3_overhead_ind input pin (of the terminal equipment) "high". whenever the ter- minal equipment detects this pin toggling "high", it should delay transmission of the very next e3 frame payload bit by one clock cycle. the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 2 operation is illustrated in figure 160. how to configure the XRT72L50 to operate in this mode. 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01" as depicted below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 159. 6.2.1.3 mode 3 - the serial/local-timed/ frame-master modebehavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows. a. local timed - uses the txinclk signal as the timing reference f igure 160. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (m ode 2 o peration ) terminal equipment signals e3_clock_in e3_data_out tx_start_of_frame e3_overhead_ind xrt7250 transmit payload data i/f signals txinclk txser txframeref txoh_ind payload[4238] payload[4239] fa1, bit 7 fa1, bit 6 payload[4238] payload[4239] fa1, bit 7 fa1, bit 6 note: the fa1 byte will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: txframeref pulses high to denote e3 frame boundary. note: txoh_ind pulses high for 16 bit periods in order to denote overhead data (e.g., the fa1 and fa2 bytes) framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 0 0 1 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 351 in this mode, the transmit section of the XRT72L50 will use the txinclk signal as its timing reference. b. serial mode the XRT72L50 will receive the e3 payload data, in a serial manner, via the txser input pin. the transmit payload data input interface (within the XRT72L50) will latch this data into its circuitry, on the rising edge of the txinclk input clock signal. c. delineation of outbound ds3 frames (frame master mode) the transmit section of the XRT72L50 will use the txinclk signal as its timing reference, and will initiate e3 frame generation, asynchronously with respect to any externally applied signal. the XRT72L50 will pulse its txframe output pin "high" whenever its it processing the very last bit-field within a given e3 frame. d. sampling of payload data, from the terminal equipment in mode 3, the XRT72L50 will sample the data, at the txser input pin, on the rising edge of txinclk. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 3 operation figure 161 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 3 operation. mode 3 operation of the terminal equipment in figure 161, both the terminal equipment and the XRT72L50 are driven by an external 34.368 mhz clock signal. this clock signal is connected to the e3_clock_in input of the terminal equipment and the txinclk input pin of the XRT72L50. the terminal equipment will serially output the pay- load data on its e3_data_out output pin, upon the rising edge of the signal at the e3_clock_in input pin. similarly, the XRT72L50 will latch the data, residing on the txser input pin, on the rising edge of txinclk. the XRT72L50 will pulse the txframe output pin "high" for one bit-period, coincident while it is pro- cessing the last bit-field within a given outbound e3 frame. the terminal equipment is expected to moni- tor the txframe signal (from the XRT72L50) and to place the first bit, within the very next outbound e3 frame on the txser input pin. n ote : in this case, the XRT72L50 dictates exactly when the very next e3 frame will be generated. the terminal equipment is expected to respond appropriately by provid- ing the XRT72L50 with the first bit of the new e3 frame, upon demand. hence, in this mode, the XRT72L50 is f igure 161. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 3 (s erial /l ocal -t imed /f rame -m aster ) o peration e3_clock_in e3_data_out txstart_of_frame e3_overhead_ind e3_clock_in e3_data_out txstart_of_frame e3_overhead_ind txinclk txser txframeref txoh_ind nibint txinclk txser txframeref txoh_ind nibint 34.368 mhz clock source 34.368 mhz clock source xrt72l5x e3 framer terminal equipment ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 352 referred to as the frame master and the terminal equip- ment is referred to as the frame slave. finally, the XRT72L50 will pulse its txoh_ind output pin, one bit-period prior to it processing a given over- head bit, within the outbound e3 frame. since the txoh_ind output pin of the XRT72L50 is electrically connected to the e3_overhead_ind whenever the XRT72L50 pulses the txoh_ind output pin "high", it will also be driving the e3_overhead_ind input pin (of the terminal equipment) "high". whenever the ter- minal equipment detects this pin toggling "high", it should delay transmission of the very next ds3 frame payload bit by one clock cycle. the behavior of the signal between the XRT72L50 and the terminal equipment for e3 mode 3 operation is illustrated in figure 162. how to configure the XRT72L50 to operate in this mode. 1. set the nibintf input pin "low". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01". 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 162. 6.2.1.4 mode 4 - the nibble-parallel/loop- timed mode behavior of the XRT72L50 f igure 162. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (e3 m ode 3 o peration ) terminal equipment signals e3_clock_in e3_data_out tx_start_of_frame e3_overhead_ind xrt72l5x transmit payload data i/f signals txinclk txser txframe txoh_ind payload[4238] payload[4239] fa1, bit 7 fa1, bit 6 payload[4238] payload[4239] fa1, bit 7 fa1, bit 6 note: the fa1 byte will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: txframe pulses high to denote e3 frame boundary. note: txoh_ind pulses high for 16 bit periods in order to denote overhead data (e.g., the fa1 and fa2 bytes) framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 0 0 0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 353 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. a. looped timing (uses the rxlineclk as the timing reference) in this mode, the transmit section of the XRT72L50 will use the rxlineclk signal as its timing reference. when the XRT72L50 is operating in the nibble-mode, it will internally divide the rxlineclk signal, by a fac- tor of four (4) and will output this signal via the txnib- clk output pin. b. nibble-parallel mode the XRT72L50 will accept the e3 payload data, from the terminal equipment in a nibble-parallel manner, via the txnib[3:0] input pins. the transmit terminal equipment input interface block will latch this data in- to its circuitry, on the rising edge of the txnibclk out- put signal. c. delineation of the outbound e3 frames the XRT72L50 will pulse the txnibframe output pin "high" for one bit-period, coincident with the XRT72L50 processing the last nibble of a given e3 frame. d. sampling of payload data, from the terminal equipment in mode 4, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the rxoutclk clock signal, following a pulse in the txnib- clk signal (see figure 164). n ote : the txnibclk signal, from the XRT72L50, operates nominally at 11.184 mhz (e.g., 44.736 mhz divided by 4). however, for reasons described below, txnibclk effectively operates at a lower clock frequency. the transmit payload data input interface is only used to accept the payload data, which is intended to be carried by outbound ds3 frames. the transmit payload data input interface is not designed to accommodate the entire ds3 data stream. the e3 frame consists of 537 bytes or 1074 nibbles. therefore, the XRT72L50 will supply 1074 txnibclk pulses between the rising edges of two consecutive txnibframe pulses. the e3 frame repetition rate is 8.0khz. hence, 1074 txnibclk pulses for each e3 frame period amounts to txnibclk running at approx- imately 8.592 mhz. the method by which the 1074 txnibclk pulses are distributed throughout the e3 frame period is presented below. nominally, the transmit section within the XRT72L50 will generate a txnibclk pulse for every 4 rxoutclk (or txinclk) periods. interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 4 operation figure 163 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 4 operation. mode 4 operation of the terminal equipment when the XRT72L50 is operating in this mode, it will function as the source of the 8.592mhz (e.g., the 34.368mhz clock signal divided by 4) clock signal that will be used as the terminal equipment interface clock by both the XRT72L50 and the terminal equip- ment. the terminal equipment will output the payload data of the outbound e3 data stream via its e3_data_out[3:0] pins on the rising edge of the f igure 163. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 4 (n ibble -p arallel /l oop -t imed ) o peration terminal equipment xrt72l5x e3 framer e3_data_out[3:0] e3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txnibframe nibint vcc 4 rxlineclk 34.368mhz 8.592 mhz txoh_ind e3_overhead_ind ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 354 8.592mhz clock signal at the e3_nib_clock_in input pin. the XRT72L50 will latch the outbound e3 data stream (from the terminal equipment) on the rising edge of the txnibclk output clock signal. the XRT72L50 will indicate that it is processing the last nibble, within a given e3 frame, by pulsing its txnib- frame output pin "high" for one txnibclk clock peri- od. when the terminal equipment detects a pulse at its tx_start_of_frame input pin, it is expected to transmit the first nibble, of the very next outbound e3 frame to the XRT72L50 via the e3_data_out[3:0] (or txnib[3:0] pins). finally, for the nibble-parallel mode operation, the XRT72L50 will pulse the txohind output pin high for a total of 14 nibble periods (e.g., for the 7 over- head bytes, within each of the e3, itu-t g.832 frames). at the beginning of an e3 frame, the XRT72L50 will pulse the txohind output pin high for 4 nibble periods. these four nibbles represent the fa1 and fa2 bytes within each e3 frame. throughout the remainder of the e3 framing period, the XRT72L50 will pulse the txohind output pin 5 times. the width (or duration) of each of these pulses will be two nibbles. clearly, each of these 5 pulses corresponds to the five remaining overhead bytes, within the e3, itu-t g.832 framing structure. the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 4 operation is illustrated in figure 164. how to configure the XRT72L50 into mode 4 1. set the nibintf input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "00" as illus- trated below. f igure 164. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (m ode 4 o peration ) terminal equipment signals rxoutclk tx_start_of_frame e3_nib_clock_in e3_data_out[3:0] payload nibble [1059] overhead nibble [0] xrt72l5x transmit payload data i/f signals e3 frame number n e3 frame number n + 1 note: txnibframe pulses high to denote e3 frame boundary. rxoutclk txnibframe txnibclk txnib[3:0] nibble [1059] overhead nibble [0] e3_overhead_ind txoh_ind txoh_ind pulses high for 4 nibble periods XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 355 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 163. 6.2.1.5 mode 5 - the nibble-parallel/local- time/frame-slave interface mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows: a. local timing - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal at its timing reference. further, the chip will internally divide the txinclk clock signal by a factor of 4 and will output this divid- ed clock signal via the txnibclk output pin. the transmit terminal equipment input interface block (within the XRT72L50) will use the rising edge of the txnibclk signal, to latch the data, residing on the tx- nib[3:0] into its circuitry. b. nibble-parallel mode the XRT72L50 will accept the ds3 payload data, from the terminal equipment, in a parallel manner, via the txnib[3:0] input pins. the transmit terminal equipment input interface will latch this data into its circuitry, on the rising edge of the txnibclk output signal. c. delineation of outbound e3 frames the transmit section will use the txinclk input signal as its timing reference and will use the txframeref input signal as its framing reference (e.g., the trans- mit section of the XRT72L50 initiates frame genera- tion upon the rising edge of the txframeref signal). d. sampling of payload data, from the terminal equipment in mode 5, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the txinclk clock signal, following a pulse in the txnibclk signal (see figure 166). n ote : the txnibclk signal, from the XRT72L50 operates nominally at 8.592 mhz (e.g., 34.368 mhz divided by 4). interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 5 operation figure 165 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 5 operation. framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0010 1 0 0 0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 356 mode 5 operation of the terminal equipment in figure 165 both the terminal equipment and the XRT72L50 will be driven by an external 8.592mhz clock signal. the terminal equipment will receive the 8.592mhz clock signal via the e3_nib_clock_in input pin. the XRT72L50 will output the 8.592mhz clock signal via the txnibclk output pin. the terminal equipment will serially output the data on the e3_data_out[3:0] pins, upon the rising edge of the signal at the e3_clock_in input pin. n ote : the e3_data_out[3:0] output pins of the terminal equipment is electrically connected to the txnib[3:0] input pins. the XRT72L50 will latch the data, residing on the tx- nib[3:0] input pins, on the rising edge of the txnibclk signal. in this case, the terminal equipment has the respon- sibility of providing the framing reference signal by pulsing the tx_start_of_frame output pin (and in turn, the txframeref input pin of the XRT72L50) "high" for one bit-period, coincident with the first bit of a new e3 frame. once the XRT72L50 detects the ris- ing edge of the input at its txframeref input pin, it will begin generation of a new e3 frame. finally, the XRT72L50 will always internally generate the overhead bits, when it is operating in both the e3 and nibble-parallel modes. the XRT72L50 will pull the txohind input pin "low". the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 5 operation is illustrated in figure 166. f igure 165. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 5 (n ibble -p arallel /l ocal -t ime /f rame -s lave ) o pera - tion terminal equipment xrt72l5x e3 framer e3_data_out[3:0] e3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txframeref nibint vcc 4 34.368mhz clock source txinclk 8.592mhz e3_overhead_ind txoh_ind XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 357 how to configure the XRT72L50 into mode 5 1. set the nibintf input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "01" as illus- trated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 165. 6.2.1.6 mode 6 - the nibble-parallel/local- timed/frame-master interface mode behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as fol- lows: a. local timing - uses the txinclk signal as the timing reference in this mode, the transmit section of the XRT72L50 will use the txinclk signal at its timing reference. further, the chip will internally divide the txinclk clock signal by a factor of 4 and will output this divid- ed clock signal via the txnibclk output pin. the transmit terminal equipment input interface block (within the XRT72L50) will use the rising edge of the txnibclk signal, to latch the data, residing on the tx- nib[3:0] into its circuitry. b. nibble-parallel mode f igure 166. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (e3 m ode 5 o peration ) terminal equipment signals rxoutclk tx_start_of_frame e3_nib_clock_in e3_data_out[3:0] payload nibble [1059] overhead nibble [0] xrt72l5x transmit payload data i/f signals e3 frame number n e3 frame number n + 1 note: terminal equipment pulses txframeref in order to denote the e3 frame boundary. rxoutclk txframeref txnibclk txnib[3:0] nibble [1059] overhead nibble [0] e3_overhead_ind txoh_ind txoh_ind pulses high for 4 nibble periods p framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001 0 1 0 0 1 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 358 the XRT72L50 will accept the e3 payload data, from the terminal equipment, in a parallel manner, via the txnib[3:0] input pins. the transmit terminal equip- ment input interface will latch this data into its circuit- ry, on the rising edge of the txnibclk output signal. c. delineation of outbound e3 frames the transmit section will use the txinclk input signal as its timing reference and will initiate the generation of e3 frames, asynchronous with respect to any ex- ternal signal. the XRT72L50 will pulse the txframe output pin "high" whenever it is processing the last bit, within a given outbound e3 frame. d. sampling of payload data, from the terminal equipment in mode 6, the XRT72L50 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the txinclk clock signal, following a pulse in the txnibclk signal (see figure 168). n ote : the txnibclk signal, from the XRT72L50 operates nominally at 8.592 mhz (e.g., 34.368 mhz divided by 4). interfacing the transmit payload data input inter- face block of the XRT72L50 to the terminal equip- ment for mode 6 operation figure 167 presents an illustration of the transmit payload data input interface block (within the XRT72L50) being interfaced to the terminal equip- ment, for mode 6 operation. mode 6 operation of the terminal equipment in figure 167 both the terminal equipment and the XRT72L50 will be driven by an external 8.592mhz clock signal. the teriminal equipment will receive the 8.592mhz clock signal via the e3_nib_clock_in input pin. the XRT72L50 will output the 8.592mhz clock signal via the txnibclk output pin. the terminal equipment will serially output the data on the e3_data_out[3:0] pins upon the rising edge of the signal at the e3_clock_in input pin. the XRT72L50 will latch the data, residing on the tx- nib[3:0] input pins, on the rising edge of the txnibclk signal. in this case the XRT72L50 has the responsibility of providing the framing reference signal by pulsing the txframe output pin (and in turn the tx_start_of_frame input pin of the terminal equip- ment) "high" for one bit-period, coincident with the last bit within a given e3 frame. finally, the XRT72L50 will always internally generate the overhead bits, when it is operating in both the e3 and nibble-parallel modes. the XRT72L50 will pull the txohind input pin "low". the behavior of the signals between the XRT72L50 and the terminal equipment for e3 mode 6 operation is illustrated in figure 168. f igure 167. i llustration of the t erminal e quipment being interfaced to the t ransmit p ayload d ata i nput i nterface block of the XRT72L50 for m ode 6 o peration terminal equipment xrt72l5x e3 framer e3_data_out[3:0] e3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txnibframe nibint vcc 4 34.368mhz clock source txinclk 8.592mhz txoh_ind e3_overhead_ind XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 359 how to configure the XRT72L50 into mode 6 1. set the nibint input pin "high". 2. set the timrefsel[1:0] bit-fields (within the framer operating mode register) to "1x" as illus- trated below. 3. interface the XRT72L50, to the terminal equip- ment, as illustrated in figure 167. 6.2.2 the transmit overhead data input inter- face figure 169 presents a simple illustration of the trans- mit overhead data input interface block within the XRT72L50. f igure 168. b ehavior of the t erminal i nterface signals between the XRT72L50 and the t erminal e quipment (e3 m ode 6 o peration ) terminal equipment signals txinclk tx_start_of_frame e3_nib_clock_in e3_data_out[3:0] payload nibble [1059] overhead nibble [0] xrt72l5x transmit payload data i/f signals e3 frame number n e3 frame number n + 1 note: txnibframe pulses high to denote e3 frame boundary. txinclk txnibframe txnibclk txnib[3:0] nibble [1059] overhead nibble [0] e3_overhead_ind txoh_ind txoh_ind pulses high for 4 nibble periods framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 01010 1 x ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 360 the e3, itu-t g.832 frame consists of 537 bytes. of these bytes, 530 bytes are payload bytes and the remaining 7 are overhead bytes. the XRT72L50 has been designed to handle and process both the pay- load type and overhead type bits for each e3 frame. within the transmit section within the XRT72L50, the transmit payload data input interface has been de- signed to handle the payload data. likewise, the transmit overhead input interface has been designed to handle and process the overhead bits. the transmit section of the XRT72L50 generates or processes the various overhead bits within the e3 frame, in the following manner. the frame alignment overhead bytes (e.g., the fa1 and fa2 bytes) the "fa1" and "fa2" bytes are always internally gen- erated by the transmit section of the XRT72L50. hence, the user cannot insert his/her value for the "fa1" and "fa2" bytes into the outbound ds3 data stream, via the transmit overhead data input inter- face. the error monitoring (em) overhead byte the em byte is always internally generated by the transmit section of the XRT72L50. hence, the user cannot insert his/her value for the em byte into the outbound e3 data stream, via the transmit overhead data input interface. the alarm and signaling related overhead bytes bytes that are used to transport the alarm conditions can be either internally generated by the transmit section within the XRT72L50, or can be externally generated and inserted into the outbound e3 data stream, via the transmit overhead data input inter- face. the e3 frame overhead bits that fall into this category are: ? the "ma byte ? the "tr byte the data link related overhead bits the e3 frame structure also contains bits which can be used to transport user data link information and path maintenance data link information. the udl (user data link) bits are only accessible via the transmit overhead data input interface. the path f igure 169. s imple i llustration of the t ransmit o verhead d ata i nput i nterface block transmit overhead data input interface block transmit overhead data input interface block txohframe txohenable txoh txohclk txohins to transmit e3 framer block XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 361 maintenance data link (pmdl) bits can either be sourced from the transmit lapd controller/buffer or via the transmit overhead data input interface. table 71 lists the overhead bits within the ds3 frame. additionally, this table also indicates whether or not these overhead bits can be sourced by the transmit overhead data input interface or not. t able 71: a l isting of the o verhead bits within the e3 frame , and their potential sources , within the XRT72L50 ic o verhead b it i nternally generated a ccessible via the t ransmit o verhead d ata i nput i nterface b uffer /r egister a ccessible fa1 - bit 7 yes no yes* fa1 - bit 6 yes no yes fa1 - bit 5 yes no yes* fa1 - bit 4 yes no yes* fa1 - bit 3 yes no yes fa1 - bit 2 yes no yes fa1 - bit 1 yes no yes+ fa1 - bit 0 yes no yes fa2 - bit 7 yes no yes fa2 - bit 6 yes no yes fa2 - bit 5 yes no yes fa2 - bit 4 yes no yes fa2 - bit 3 yes no yes fa2 - bit 2 yes no yes fa2 - bit 1 yes no yes fa2 - bit 0 yes no yes em - bit 7 yes yes yes em - bit 6 yes yes yes em - bit 5 yes yes yes em - bit 4 yes yes yes em - bit 3 yes yes yes em - bit 2 yes yes yes em - bit 1 yes yes yes em - bit 0 yes yes yes tr - bit 7 no yes yes tr - bit 6 no yes yes tr - bit 5 no yes yes tr - bit 4 no yes yes ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 362 n otes : 1. the XRT72L50 contains mask register bits that permit the user to alter the state of the internally generated value for these bits. 2. the transmit lapd controller/buffer can be config- ured to be the source of the dl bits, within the out- bound e3 data stream. in all, the transmit overhead data input interface per- mits the user to insert overhead data into the out- tr - bit 3 no yes yes tr - bit 2 no yes yes tr - bit 1 no yes yes tr - bit 0 no yes yes ma - bit 7 yes yes yes ma - bit 6 yes yes yes ma - bit 5 yes yes yes ma - bit 4 yes yes yes ma - bit 3 yes yes yes ma - bit 2 yes yes yes ma - bit 1 yes yes yes ma - bit 0 yes yes yes nr - bit 7 no yes yes nr - bit 6 no yes yes nr - bit 5 no yes yes nr - bit 4 no yes yes nr - bit 3 no yes yes nr - bit 2 no yes yes nr - bit 1 no yes yes nr - bit 0 no yes yes gc - bit 7 no yes yes gc - bit 6 no yes yes gc - bit 5 no yes yes gc - bit 4 no yes yes gc - bit 3 no yes yes gc - bit 2 no yes yes gc - bit 1 no yes yes gc - bit 0 no yes yes t able 71: a l isting of the o verhead bits within the e3 frame , and their potential sources , within the XRT72L50 ic o verhead b it i nternally generated a ccessible via the t ransmit o verhead d ata i nput i nterface b uffer /r egister a ccessible XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 363 bound e3 frames via the following two different meth- ods. ? method 1 - using the txohclk clock signal ? method 2 - using the txinclk and the txohenable signals. each of these methods are described below. 6.2.2.1 method 1 - using the txohclk clock signal the transmit overhead data input interface consists of the five signals. of these five (5) signals, the fol- lowing four (4) signals are to be used when imple- menting method 1. ? txoh ? txohclk ? txohframe ? txohins each of these signals are listed and described below. table 72. t able 72: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input inter- face to accept overhead data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of the txohclk output signal. conversely, setting this pin "low" configures the transmit overhead data input interface to not sample (e.g., ignore) the data at the txoh input pin, on the falling edge of the txohclk output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the transmit overhead data input interface (e.g., if the terminal equipment asserts the txohins signal, at a time when one of these non-insertable overhead bits are being processed), that par- ticular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the overhead bit position within the very next outbound e3 frame. if the txohins pin is pulled "high", the transmit overhead data input interface will sam- ple the data at this input pin (txoh), on the falling edge of the txohclk output pin. conversely, if the txohins pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. txohclk output transmit overhead input interface clock output signal: this output signal serves two purposes: 1. the transmit overhead data input interface will provide a rising clock edge on this signal, one bit-period prior to the instant that the transmit overhead data input interface is processing an overhead bit. 2. the transmit overhead data input interface will sample the data at the txoh input, on the fall- ing edge of this clock signal (provided that the txohins input pin is "high"). n ote : the transmit overhead data input interface will supply a clock edge for all overhead bits within the ds3 frame (via the txohclk output signal). this includes those overhead bits that the transmit overhead data input interface will not accept from the terminal equipment. txohframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L50 is processing the last bit within a given e3 frame. the purpose of this output signal is to alert the terminal equipment that the transmit overhead data input interface block is about to begin processing the overhead bits for a new e3 frame. ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 364 interfacing the transmit overhead data input in- terface to the terminal equipment. figure 170 illustrates how one should interface the transmit overhead data input interface to the termi- nal equipment, when using method 1. method 1 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the outbound e3 data stream, (via the transmit overhead data input interface), then it is ex- pected to do the following. 1. to sample the state of the txohframe signal (e.g., the tx_start_of_frame input signal) on the rising edge of the txohclk (e.g., the e3_oh_clock_in signal). 2. to keep track of the number of rising clock edges that have occurred, via the txohclk (e.g., the e3_oh_clock_in signal) since the last time the txohframe signal was sampled "high". by doing this the terminal equipment will be able to keep track of which overhead bit is being pro- cessed by the transmit overhead data input interface block at any given time. when the ter- minal equipment knows which overhead bit is being processed, at a given txohclk period, it will know when to insert a desired overhead bit value into the outbound e3 data stream. from this, the terminal equipment will know when it should assert the txohins input pin and place the appropriate value on the txoh input pin (of the XRT72L50). table 73 relates the number of rising clock edges (in the txohclk signal, since txohframe was sampled "high") to the e3 overhead bit, that is being pro- cessed. f igure 170. i llustration of the t erminal e quipment being interfaced to the t ransmit o verhead d ata i nput i nterface (m ethod 1) 34.368mhz clock source terminal equipment xrt72l5x e3 framer e3_oh_out e3_oh_clock_in tx_start_of_frame txoh txohclk txframe rxlinecl,k 34.368mhz clock source txinclk txohins insert_oh XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 365 t able 73: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since "t x ohf rame " was last sampled "h igh ") to the e3 o verhead b it , that is being processed n umber of r ising c lock e dges in t x ohc lk t he o verhead b it e xpected by the "XRT72L50" c an this overhead bit be accepted by the XRT72L50? 0 (clock edge is coincident with txo- hframe being detected high) fa1 byte - bit 7 no 1 fa1 byte - bit 6 no 2 fa1 byte - bit 5 no 3 fa1 byte - bit 4 no 4 fa1 byte - bit 3 no 5 fa1 byte - bit 2 no 6 fa1 byte - bit 1 no 7 fa1 byte - bit 0 no 8 fa2 byte - bit 7 no 9 fa2 byte - bit 6 no 10 fa2 byte - bit 5 no 11 fa2 byte - bit 4 no 12 fa2 byte - bit 3 no 13 fa2 byte - bit 2 no 14 fa2 byte - bit 1 no 15 fa2 byte - bit 0 no 16 em byte - bit 7 no 17 em byte - bit 6 no 18 em byte - bit 5 no 19 em byte - bit 4 no 20 em byte - bit 3 no 21 em byte - bit 2 no 22 em byte - bit 1 no 23 em byte - bit 0 no 24 tr byte - bit 7 yes 25 tr byte - bit 6 yes 26 tr byte - bit 5 yes 27 tr byte - bit 4 yes 28 tr byte - bit 3 yes 29 tr byte - bit 2 yes ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 366 3. after the terminal equipment has waited the appropriate number of clock edges (from the txohframe signal being sampled "high"), it should assert the txohins input signal. concur- rently, the terminal equipment should also place the appropriate value (of the inserted overhead bit) onto the txoh signal. 4. the terminal equipment should hold both the txohins input pin "high" and the value of the txoh signal, stable until the next rising edge of txohclk is detected. case study: the terminal equipment intends to insert the appropriate overhead bits into the transmit overhead data input interface (using 30 tr byte - bit 1 yes 31 tr byte - bit 0 yes 32 ma byte - bit 7 yes (ferf bit) 33 ma byte - bit 6 yes (febe bit) 34 ma byte - bit 5 yes 35 ma byte - bit 4 yes 36 ma byte - bit 3 yes 37 ma byte - bit 2 yes 38 ma byte - bit 1 yes 39 ma byte - bit 0 yes 40 nr byte - bit 7 yes 41 nr byte - bit 6 yes 42 nr byte - bit 5 yes 43 nr byte - bit 4 yes 44 nr byte - bit 3 yes 45 nr byte - bit 2 yes 46 nr byte - bit 1 yes 47 nr byte - bit 0 yes 48 gc byte - bit 7 yes 49 gc byte - bit 6 yes 50 gc byte - bit 5 yes 51 gc byte - bit 4 yes 52 gc byte - bit 3 yes 53 gc byte - bit 2 yes 54 gc byte - bit 1 yes 55 gc byte - bit 0 yes t able 73: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since "t x ohf rame " was last sampled "h igh ") to the e3 o verhead b it , that is being processed n umber of r ising c lock e dges in t x ohc lk t he o verhead b it e xpected by the "XRT72L50" c an this overhead bit be accepted by the XRT72L50? XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 367 method 1) in order to transmit a yellow alarm to the remote terminal equipment. in this example, the terminal equipment intends to in- sert the appropriate overhead bits, into the transmit overhead data input interface, such that the XRT72L50 will transmit a yellow alarm to the remote terminal equipment. recall that, for e3 applications, a yellow alarm is transmitted by setting the ferf bit (within the ma byte) to "0". if one assumes that the connection between the ter- minal equipment and the XRT72L50 are as illustrated in figure 170 then figure 171 presents an illustration of the signaling that must go on between the terminal equipment and the XRT72L50. in figure 171 the terminal equipment samples the txohframe signal being "high" at rising clock edge # 0". from this point, the terminal equipment waits until it has detected 32 rising edges in the txohclk signal. at this point, the terminal equipment knows that the XRT72L50 is just about to process the ferf bit within the ma byte (in a given outbound e3 frame). additionally, according to table 73, the 32nd overhead bit to be processed is the ferf bit. in or- der to facilitate the transmission of the yellow alarm, the terminal equipment must set this ferf bit to "1". hence, the terminal equipment starts this process by implementing the following steps concurrently. a. assert the txohins input pin by setting it "high". b. set the txoh input pin to "0". after the terminal equipment has applied these sig- nals, the XRT72L50 will sample the data on both the txohins and txoh signals upon the very next falling edge of txohclk (designated at 32- in figure 171). once the XRT72L50 has sampled this data, it will then insert a "1" into the ferf bit position, in the out- bound e3 frame. upon detection of the very next rising edge of the tx- ohclk clock signal (designated as clock edge 1 in figure 171), the terminal equipment will negate the txohins signal (e.g., toggles it "low") and will cease inserting data into the transmit overhead data input interface. 6.2.2.2 method 2 - using the txinclk and txohenable signals method 1 requires the use of an additional clock sig- nal, txohclk. however, there may be a situation in which the user does not wish to add this extra clock signal to their design, in order to use the transmit overhead data input interface. hence, method 2 is available. when using method 2, either the txinclk or rxoutclk signal is used to sample the overhead bits and signals which are input to the transmit over- f igure 171. i llustration of the signal that must occur between the t erminal e quipment and the XRT72L50, in order to configure the XRT72L50 to transmit a y ellow a larm to the remote terminal equipment terminal equipment/xrt72l5x interface signals txohclk txohins txohframe txoh remaining overhead bits with e3 frame ma, bit 7 txohframe is sample high terminal equipment asserts txohins and data on txoh line. 0 1 26 27 28 29 30 31 32 xrt72l5x framer samples txohins and txohins signal ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 368 head data input interface. method 2 involves the use of the following signals: ? txoh ? txinclk ? txohframe ? txohenable each of these signals are listed and described in table 74. interfacing the transmit overhead data input interface to the terminal equipment figure 172 illustrates how one should interface the transmit overhead data input interface to the termi- nal equipment when using method 2. t able 74: d escription of m ethod 1 t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohenable output transmit overhead data enable output pin the XRT72L50 will assert this signal, for one txinclk period, just prior to the instant that the transmit overhead data input interface is processing an overhead bit. txohframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L50 is processing the last bit within a given ds3 frame. txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input inter- face to accept overhead data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of the txinclk output signal. conversely, setting this pin "low" configures the transmit overhead data input interface to not sample (e.g., ignore) the data at the txoh input pin, on the falling edge of the txohclk output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the transmit overhead data input interface (e.g., if the terminal equipment asserts the txohins signal, at a time when one of these non-insertable overhead bits are being processed), that par- ticular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the overhead bit position within the very next outbound ds3 frame. if the txohins pin is pulled "high", the transmit overhead data input interface will sam- ple the data at this input pin (txoh), on the falling edge of the txohclk output pin. conversely, if the txohins pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 369 method 2 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the outbound e3 data stream (via the transmit overhead data input interface), then it is ex- pected to do the following. 1. to sample the state of both the txohframe and the txohenable input signals, via the e3_clock_in (e.g., either the txinclk or the rxoutclk signal of the XRT72L50) signal. if the terminal equipment samples the txohenable signal "high", then it knows that the XRT72L50 is about to process an overhead bit. further, if the terminal equipment samples both the txo- hframe and the txohenable pins "high" (at the same time) then the terminal equipment knows that the XRT72L50 is about to process the first overhead bit, within a new e3 frame. 2. to keep track of the number of times that the txohenable signal has been sampled "high" since the last time both the txohframe and the txohenable signals were sampled "high". by doing this, the terminal equipment will be able to keep track of which overhead bit the transmit overhead data input interface is about ready to process. from this, the terminal equipment will know when it should assert the txohins input pin and place the appropriate value on the txoh input pins of the XRT72L50. table 75 also relates the number of txohenable out- put pulses (that have occurred since both the txo- hframe and txohenable pins were sampled "high") to the e3 overhead bit, that is being processed. f igure 172. i llustration of the t erminal e quipment being interfaced to the t ransmit o verhead d ata i nput i nterface (m ethod 2) 34.368mhz clock source terminal equipment xrt72l5x e3 framer e3_oh_enable e3_clock_in tx_start_of_frame txoh txohenable txohframe rxlinecl,k 34.368mhz clock source txinclk txohins insert_oh e3_oh_out ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 370 t able 75: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the e3 o verhead b it , that is being processed by the XRT72L50 n umber of t x ohe nable p ulses t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? 0 (clock edge is coincident with txo- hframe being detected high) fa1 byte - bit 7 yes 1 fa1 byte - bit 6 no 2 fa1 byte - bit 5 no 3 fa1 byte - bit 4 no 4 fa1 byte - bit 3 no 5 fa1 byte - bit 2 no 6 fa1 byte - bit 1 no 7 fa1 byte - bit 0 no 8 fa2 byte - bit 7 no 9 fa2 byte - bit 6 no 10 fa2 byte - bit 5 no 11 fa2 byte - bit 4 no 12 fa2 byte - bit 3 no 13 fa2 byte - bit 2 no 14 fa2 byte - bit 1 no 15 fa2 byte - bit 0 no 16 em byte - bit 7 no 17 em byte - bit 6 no 18 em byte - bit 5 no 19 em byte - bit 4 no 20 em byte - bit 3 no 21 em byte - bit 2 no 22 em byte - bit 1 no 23 em byte - bit 0 no 24 tr byte - bit 7 yes 25 tr byte - bit 6 yes 26 tr byte - bit 5 yes 27 tr byte - bit 4 yes 28 tr byte - bit 3 yes 29 tr byte - bit 2 yes XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 371 3. after the terminal equipment has waited through the appropriate number of pulses via the txo- henable pin, it should then assert the txohins input signal. concurrently, the terminal equip- ment should also place the appropriate value (of the inserted overhead bit) onto the txoh signal. 4. the terminal equipment should hold both the txohins input pin "high" and the value of the txoh signal stable, until the next txohenable pulse is detected. case study: the terminal equipment intends to insert the appropriate overhead bits into the transmit overhead data input interface (using 30 tr byte - bit 1 yes 31 tr byte - bit 0 yes 32 ma byte - bit 7 (ferf) yes 33 ma byte - bit 6 (febe) yes 34 ma byte - bit 5 yes 35 ma byte - bit 4 yes 36 ma byte - bit 3 yes 37 ma byte - bit 2 yes 38 ma byte - bit 1 yes 39 ma byte - bit 0 yes 40 nr byte - bit 7 yes 41 nr byte - bit 6 yes 42 nr byte - bit 5 yes 43 nr byte - bit 4 yes 44 nr byte - bit 3 yes 45 nr byte - bit 2 yes 46 nr byte - bit 1 yes 47 nr byte - bit 0 yes 48 gc byte - bit 7 yes 49 gc byte - bit 6 yes 50 gc byte - bit 5 yes 51 gc byte - bit 4 yes 52 gc byte - bit 3 yes 53 gc byte - bit 2 yes 54 gc byte - bit 1 yes 55 gc byte - bit 0 yes t able 75: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the e3 o verhead b it , that is being processed by the XRT72L50 n umber of t x ohe nable p ulses t he o verhead b it e xpected by the XRT72L50 c an this overhead bit be accepted by the XRT72L50? ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 372 method 2) in order to transmit a yellow alarm to the remote terminal equipment. in this case, the terminal equipment intends to insert the appropriate overhead bits, into the transmit over- head data input interface such that the XRT72L50 will transmit a yellow alarm to the remote terminal equipment. recall that, for e3, itu-t g.832 applica- tions, a yellow alarm is transmitted by setting the ferf bit (within the ma byte) to "1". if one assumes that the connection between the ter- minal equipment and the XRT72L50 is as illustrated in figure 172 then, figure 173 presents an illustration of the signaling that must go on between the terminal equipment and the XRT72L50. 6.2.3 the transmit e3 hdlc controller the transmit e3 hdlc controller block can be used to transport message-oriented signaling (mos) type messages to the remote terminal equipment as dis- cussed in detail below. n ote : while executing this particular write operation, the user should write the binary value "000xx110b" into the tx controller block), please see section 5.3.3.1. 6.2.3.1 message-oriented signaling (e.g., lap-d) processing via the transmit ds3 hdlc controller the lapd transmitter (within the transmit e3 hdlc controller block) allows the user to transmit path maintenance data link (pmdl) messages to the re- mote terminal via the outbound e3 frames. in this case the message bits are either inserted into and carried by the nr or the gc bytes, within the out- bound e3 frames. the on-chip lapd transmitter sup- ports both the 76 byte and 82 byte length message formats, and the framer ic allocates 88 bytes of on- chip ram (e.g., the transmit lapd message buffer) to store the message to be transmitted. the mes- sage format complies with itu-t q.921 (lap-d) pro- tocol with different addresses and is presented below in figure 174. f igure 173. b ehavior of t ransmit o verhead d ata i nput i nterface signals between the XRT72L50 and the t erminal e quipment ( for m ethod 2) txinclk txohframe txohenable txohins txoh terminal equipment samples txohframe and txohenable being high terminal equipment counts the number of txohenable pulses. at pulse # 32 the terminal equipment asserts the txohins signal and places the desired data on txoh. xrt72l5x samples txoh here. txohenable pulse # 32 ma byte, bit 7 txohenable pulse # 0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 373 where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the following sections defines each of these bit/byte- fields within the lapd message frame format. flag sequence byte the flag sequence byte is of the value 0x7e, and is used to denote the boundaries of the lapd message frame. sapi - service access point identifier the sapi bit-fields are assigned the value of "001111b" or 15 (decimal). tei - terminal endpoint identifier the tei bit-fields are assigned the value of 0x00. the tei field is used in n-isdn systems to identify a terminal out of multiple possible terminal. however, since the framer ic transmits data in a point-to-point manner, the tei value is unimportant. control the control identifies the type of frame being trans- mitted. there are three general types of frame for- mats: information, supervisory, and unnumbered. the framer assigned the control byte the value 03h. hence, the framer will be transmitting and receiving unnumbered lapd message frames. information payload the information payload is the 76 bytes or 82 bytes of data (e.g., the pmdl message) that the user has writ- ten into the on-chip transmit lapd message buffer (which is located at addresses 0x86 through 0xdd). it is important to note that the user must write in a specific octet value into the first byte position within the transmit lapd message buffer (located at ad- dress = 0x86, within the framer). the value of this octet depends upon the type of lapd message frame/pmdl message that the user wishes to trans- mit. table 76 presents a list of the various types of lapd message frames/pmdl messages that are supported by the XRT72L50 framer device and the corresponding octet value that the user must write in- to the first octet position within the transmit lapd message buffer. f igure 174. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) t able 76: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i nformation p ayload lapd m essage t ype v alue of f irst b yte , within i nformation p ayload of m essage m essage s ize cl path identification 0x38 76 bytes idle signal identification 0x34 76 bytes test signal identification 0x32 76 bytes itu-t path identification 0x3f 82 bytes ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 374 frame check sequence bytes the 16 bit fcs (frame check sequence) is calculat- ed over the lapd message header and information payload bytes, by using the crc-16 polynomial, x 16 + x 12 + x 5 + 1. operation of the lapd transmitter if a message is to be transmitted via the lapd trans- mitter then, the information portion (or the body) of the message must be written into the transmit lapd message buffer, which is located at 0x86 through 0xdd in on-chip ram via the microprocessor inter- face. afterwards, the user must do three things: 1. specify the length of lapd message to be trans- mitted. 2. specify which bit-field (within the e3 frame) that the lapd message frame is to be transported on (e.g., either the gc or the nr byte). 3. specify whether the lapd transmitter should transmit this lapd message frame only once, or an indefinite number of times at one-second intervals. 4. enable the lapd transmitter. 5. initiate the transmission of the pmdl message. each of these steps will be discussed in detail. step 1 - specify the type of lapd message frame to be transmitted (within the transmit lapd mes- sage buffer) the user must write in a specific octet value into the first octet position within the transmit lapd buffer (e.g., at address location 0x86 within the framer ic). this octet is referred to as the lapd message frame id octet. the value of this octet must correspond to the type of lapd message frame that is to be trans- mitted. this octet will ultimately be used by the re- mote terminal equipment in order to help it identify the type of lapd message frame that it is receiving. table 76 lists these octets and the corresponding lapd message types. step 2 - write the pmdl message into the re- maining part of the transmit lapd message buff- er. the user must now write in his/her pmdl message into the remaining portion of the transmit lapd mes- sage buffer (e.g., addresses 0x87 through 0x135 within the framer ic). step 3 - specifying the length of the lapd mes- sage one of two different sizes of lapd messages can be transmitted, by writing the appropriate data to bit 1 within the tx e3 lapd configuration register. the bit-format of this register is presented below. the relationship between the contents of bit-fields 1 and the lapd message size is given in table 77. n ote : the message type selected must correspond with the contents of the first byte of the information (payload) portion, as presented in table 76. step 4 - specifying which byte-field (within the e3 frame) that the lapd message frame octets are to be transported on. the transmit e3 framer block allows the user to transport the lapd message frame octets via either the nr byte or the gc byte-field, within each out- bound e3 frame. the user makes this selection by writing the appropriate value to bit-field 4 (dlinnr), transmit e3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0000x0 xx t able 77: r elationship between t x lapd m sg l ength and the lapd m essage s ize t x lapd m essage l ength lapd m essage l ength 0 lapd message size is 76 bytes 1 lapd message size is 82 bytes XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 375 within the tx e3 configuration register, as depicted below. ) if the user writes a 0 into this bit-field, then the lapd transmitter will transmit the comprising octets of the outbound lapd message frame via the gc byte field. additionally, the transmit e3 framer block will insert the contents of the txnr byte register (address = 0x37) into the nr byte of each out- bound e3 frame. conversely, if the user writes a 1 into this bit-field, then the lapd transmitter will transmit the outbound lapd message frame octets via the nr byte-field, within each outbound e3 frame. additionally, the transmit e3 framer will insert the contents of the tx gc byte register (address = 0x35) into the gc byte- field of each outbound e3 frame. step 5 - specify whether the lapd transmitter should transmit the lapd message frame only once, or an indefinite number of times at one- second intervals. the transmit e3 hdlc control block allows the user to configure the lapd transmitter to transmit this lapd message frame only once, or an indefinite number of times at one-second intervals. the user implements this configuration by writing the appropri- ate value into bit 3 (auto retransmit) within the tx e3 lapd configuration register (address = 0x33), as depicted below. ) if the user writes a 1 into this bit-field, then the lapd transmitter will transmit the lapd message frame repeatedly at one-second intervals until the lapd transmitter is disabled. if the user writes a 0 into this bit-field, then the lapd transmitter will transmit the lapd message frame only once. afterwards, the lapd transmitter will halt its transmission until the user invokes the transmit lapd message frame command, once again. step 6 - enabling the lapd transmitter prior to the transmission of any data via the lapd transmitter, the lapd transmitter must be enabled by writing a "1" to bit 0 (txlapd enable) of the tx e3 lapd configuration register, as depicted below. txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl in nr not used txais enable txlos enable txmarx ro ro ro r/w ro r/w r/w r/w 00000000 txe3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable ro ro ro ro r/w ro r/w r/w 00001000 transmit e3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0000x0x x ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 376 if the user writes a 0 into this bit-field, then the lapd transmitter will be enabled, and the lapd transmitter will immediately begin to transmit a con- tinuous stream of flag sequence octets (0x7e), via either the gc or the nr byte-field of each out- bound e3 frame (depending upon which byte has been selected to carry the pmdl channel). conversely, if the user writes a 1 into this bit-field, then the lapd transmitter will be disabled. the transmit e3 framer block will insert the contents of the tx gc byte register into the gc byte-field for each outbound e3 frame. likewise, the transmit e3 framer block will also insert the contents of the tx nr byte register into the nr byte-field for each out- bound e3 frame. no transmission of pmdl data will occur. step 7 - initiate the transmission at this point, the user should have written the pmdl message into the on-chip transmit lapd message buffer and should have specified the type of lapd message that is to be transmitted. the user should have also specified whether the lapd transmitter will transport the lapd message frame octets via the gc-byte field or via the nr-byte field of each out- bound e3 frame. finally the lapd transmitter should have been enabled. then initiate the transmission of this message by writing a 1 to bit 3 (tx dl start) within the tx e3 lapd status and interrupt register (address = 0x34), as depicted below. ) a 0 to 1 transition in bit 3 (txdl start) in this regis- ter, initiates the transmission of lapd message frames. at this point, the lapd transmitter will begin to search thorugh the pmdl message, which is resid- ing within the transmit lapd message buffer. if the lapd transmitter finds any string of five (5) consecu- tive 1s in the pmdl message, then the lapd transmitter will insert a 0 immediately following these strings of consecutive 1s. this procedure is known as stuffing. the purpose of pmdl message stuffing is to insure that the users pmdl message does not contain strings of data that mimic the flag sequence octet (e.g., six consecutive 1s) or the abort sequence octet (e.g., seven consecutive 1s). afterwards, the lapd transmitter will begin to encapsulate the pmdl message, residing in the transmit lapd message buffer, into a lapd mes- sage frame. finally, the lapd transmitter will frag- ment the outbound lapd message frame into octets and will begin to transport these octets via the gc or the nr byte-fields (depending upon the users selec- tion) of each outbound e3 frame. while the lapd transmitter is transmitting this lapd message frame, the txdl busy bit-field (bit 2) within the tx e3 lapd status and interrupt register, will be set to 1. this bit-field allows the user to poll the sta- tus of the lapd transmitter. once the lapd trans- mitter has completed the transmission of the lapd message, then this bit-field will toggle back to 0. the user can configure the lapd transmitter to inter- rupt the local microprocessor/microcontroller upon completion of transmission of the lapd message frame, by setting bit-field 1 (txlapd interrupt enable) within the tx e3 lapd status and interrupt register (address = 0x34). to 1 as depicted below. txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 377 the purpose of t his interrupt is to let the micropro- cessor/microcontroller know that the lapd transmit- ter is available and ready to transmit a lapd mes- sage frame (which contains a new pmdl message) to the remote terminal equipment. bit 0 (tx lapd in- terrupt status) within the tx e3 lapd status and in- terrupt register will reflect the status for the transmit lapd interrupt. n ote : this bit-field will be reset upon reading this register. summary of operating the lapd transmitter once the user has invoked the txdl start command, the lapd transmitter will do the following. ? generate the four octets of the lapd message frame header (e.g., the flag sequence, sapi, tei, control, etc.,) and insert them into the header byte positions within the lapd message frame. ? it will read in the contents of the transmit lapd message buffer (e.g., the pmdl message data) and insert it into the information payload portion of the lapd message frame. ? compute the 16-bit frame check sequence (fcs) value of the lapd message frame (e.g, of the lapd message header and payload bytes) and insert this value into the fcs value octet positions within the lapd message frame. ? append a trailer flag sequence octet to the end of the lapd message frame (following the 16-bit fcs octets). ? fragment the resulting lapd message frame into octets and begin inserting these octets into either the gc or nr byte-fields within the outbound e3 frames (depending upon the users selection). ? complete the transmission of the overhead bytes, information payload byte, fcs value, and the trail- ing flag sequence octets via the transmit e3 framer block. once the lapd transmitter has completed its trans- mission of the lapd message frame, the framer will generate an interrupt to the microprocessor/micro- controller (if enabled). afterwards, the lapd trans- mitter will either halt its transmission of lapd mes- sage frames or will proceed to retransmit the lapd message frame, repeatedly at one-second inter- vals. in between these transmissions of the lapd message frames, the lapd transmitter will be send- ing a continuous stream of flag sequence bytes. the lapd transmitter will continue this behavior until the user has disabled the lapd transmitter by writing a 1 into bit 3 (no data link) within the tx e3 config- uration register. n ote : in order to prevent the users data (e.g., the pmdl message within the lapd message frame) from mimicking the flag sequence byte or an abort sequence, the lapd transmitter will parse through the pmdl message data and insert a 0 into this data, immediately following the detec- tion of five (5) consecutive 1s (this stuffing occurs while the pmdl message data is being read in from the transmit lapd message frame. the remote lapd receive (see section 5.3.5) will have the responsibility of checking the newly received pmdl messages for a string of five (5) con- secutive 1s and removing the subsequent 0 from the payload portion of the incoming lapd message. figure 175 is a flow chart that depicts the procedure (in white boxes) that the user should use in order to transmit a pmdl message via the lapd transmitter, when the lapd transmitter is configured to retrans- mit the lapd message frame, repeatedly at one- second intervals. this figure also indicates (via the shaded boxes) what the lapd transmitter circuitry will do before and during message transmission. txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 378 figure 176 presents the procedure (in white boxes) which the user should use in order to transmit a pm- dl message via the lapd transmitter, when the lapd transmitter is configured to transmit a lapd message frame only once, and then halt transmis- sion. f igure 175. f low c hart depicting how to use the lapd t ransmitter (lapd t ransmitter is configured to re - transmit the lapd m essage frame repeatedly at o ne -s econd intervals ) start write the lapd message frame identification octet into the first octet position within the transmit lapd message buffer (address = 0x86). write the pmdl message into the remaining portion of the transmit lapd message buffer (from 0x87 to 0xdd). specify the type/size of the lapd message frame to be transmitted. write in the appropriate value into bits 5 and 6 within the tx e3 lapd configuration register enable the lapd transmitter initiate the lapd message frame transmission. specify whether the outbound lapd message frame is to be transported via the gc or the nr byte-fields, within each outbound e3 frame lapd transmitter will generate a continuous string of flag sequence bytes. these bytes will be transported via either the gc or the nr byte field (depending upon users selection). lapd transmitter will stuff the contents of the pmdl message (residing within the transmit lapd message buffer). lapd transmitter will read out stuff pmdl message and encapsulate it into a lapd message frame. lapd transmitter will compute and insert the fcs value, into the lapd message frame. lapd transmitter will fragment lapd message frame into octets and begin to insert these octets into the gc or nr byte-field (depending upon users selection) into each outbound e3 frame. complete transmission of lapd message frame. generate completion of transmission of lapd message frame interrupt. wait one second. generate a continuous string of flag sequence bytes configure the lapd transmitter to repeat transmissions of the lapd message frame at one-second intervals. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 379 the mechanics of transmitting a new lapd mes- sage frame, if the lapd transmitter has been configured to re-transmit the lapd message frame, repeatedly, at one-second intervals. if the lapd transmitter has been configured to re- transmit the lapd message frame repeatedly at one-second intervals, then it will do the following (at one-second intervals). ? stuff the pmdl message. ? read in the stuffed pmdl message from the trans- mit lapd message buffer. ? encapsulate this stuffed pmdl message into a lapd message frame. ? transmit this lapd message frame to the remote terminal equipment. if another (e.g., a different) pmdl message is to be transmitted to the remote terminal equipment this new message will have to be written into the transmit lapd message buffer, via the microprocessor inter- face block of the framer ic. however, care must be taken when writing this new pmdl message. if this message is written into the transmit lapd message buffer at the wrong time (with respect to these one- second lapd message frame transmissions), the users action could interfere with these transmissions, thereby causing the lapd transmitter to transmit a corrupted message to the remote terminal equip- f igure 176. f low c hart depicting how to use the lapd t ransmitter (lapd t ransmitter is configured to transmit a lapd m essage frame only once ). start write the lapd message frame identification octet into the first octet position within the transmit lapd message buffer (address = 0x86) . write the pmdl message into the remaining portion of the transmit lapd message buffer (from 0x87 to 0xdd). specify the type/size of the lapd message frame to be transmitted . write in the appropriate value into bits 5 and 6 within the tx e3 lapd configuration register enable the lapd transmitter initiate the lapd message frame transmission. specify whether the outbound lapd message frame is to be transported via the gc or the nr byte-fields, within each outbound e3 frame lapd transmitter will generate a continuous string of flag sequence bytes. these bytes will be transported via either the gc or the nr byte field (depending upon users selection). lapd transmitter will stuff the contents of the pmdl message (residing within the transmit lapd message buffer). lapd transmitter will read out stuff pmdl message and encapsulate it into a lapd message frame. lapd transmitter will compute and insert the fcs value, into the lapd message frame. lapd transmitter will fragment lapd message frame into octets and begin to insert these octets into the gc or nr byte-field (depending upon users selection) into each outbound e3 frame. complete transmission of lapd message frame. generate completion of transmission of lapd message frame interrupt. halt transmission for an indefinite period. wait until the user initiates lapd message frame transmission again. configure the lapd transmitter to transmit lapd message frame only once ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 380 ment. in order to avoid this problem, while writing the new message into the transmit lapd message buff- er, the user should do the following. 1. configure the framer to automatically reset acti- vated interrupts. the user can do this by writing a 1 into bit 3 within the framer operating mode register (address = 0x00), as depicted below. this action will prevent the lapd transmitter from generating its own one-second interrupt (following each transmission of the lapd message frame). 2. enable the one-second interrupt this can be done by writing a 1 into bit 0 (one-sec- ond interrupt enable) within the block interrupt en- able register, as depicted below. 3. write the new message into the transmit lapd message buffer immediately after the occurrence of the one-second interrupt by synchronizing the writes to the transmit lapd message buffer to occur immediately after the occur- rence of the one-second interrupt, the user avoids conflicting with the one-second transmission of the lapd message frame, and will transmit the correct (uncorrupted) pmdl message to the remote lapd receiver. 6.2.4 the transmit e3 framer block 6.2.4.1 brief description of the transmit e3 framer the transmit e3 framer block accepts data from any of the following three sources, and uses it to form the e3 data stream. ? the transmit payload data input block ? the transmit overhead data input block ? the transmit hdlc controller block ? the internal overhead data generator the manner in how the transmit e3 framer block handles data from each of these sources is described below. handling of data from the transmit payload data input interface for e3 applications, all data that is input to the trans- mit payload data input interface will be inserted into the payload bit positions within the outbound e3 frames. handling of data from the internal overhead bit generator by default, the transmit e3 framer block will internal- ly generate the overhead bytes. however, if the ter- minal equipment inserts its own values for the over- head bits or bytes (via the transmit overhead data input interface) or, if the user enables and employs the transmit e3 hdlc controller block, then these in- ternally generated overhead bytes will be overwritten. handling of data from the transmit overhead da- ta input interface framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101 011 block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one-second interrupt enable r/wrororororor/wr/w 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 381 for e3 applications, the transmit e3 framer block au- tomatically generates and inserts the framing align- ment bytes (e.g., the "fa1 and fa2 framing align- ment bytes) into the outbound e3 frames. further, the transmit e3 framer block will automatically com- pute and insert the em byte into the outbound e3 frames. hence, the transmit e3 framer block will not accept data from the transmit oh data input inter- face block for the "fa1, fa2 and em bytes. however, the transmit e3 framer block will accept (and insert) data from the transmit overhead data in- put interface for the following byte-fields. ? ma byte ? tr byte ? nr byte ? gc byte if the user's local data link equipment activates the transmit overhead data input interface block and writes data into this interface for these bits or bytes, then the transmit e3 framer block will insert this data into the appropriate overhead bit/byte-fields, within the outbound e3 frames. 6.2.4.2 detailed functional description of the transmit e3 framer block the transmit e3 framer receives data from the fol- lowing three sources and combines them together to form a e3 data stream. ? the transmit payload data input interface block. ? the transmit overhead data input interface block ? the transmit hdlc controller block. afterwards, this e3 data stream will be routed to the transmit e3 liu interface block, for further process- ing. figure 177 presents a simple illustration of the trans- mit e3 framer block, along with the associated paths to the other functional blocks within the chip. in addition to taking data from multiple sources and multiplexing them, in appropriate manner, to create the outbound e3 frames, the transmit e3 framer block has the following roles. ? generating alarm conditions ? generating errored frames (for testing purposes) ? routing outbound e3 frames to the transmit e3 liu interface block each of these additional roles are discussed below. 6.2.4.2.1 generating alarm conditions the transmit e3 framer block permits the user to, by writing the appropriate data into the on-chip registers, to override the data that is being written into the transmit payload data and overhead data input in- terfaces and transmit the following alarm conditions. ? generate the yellow alarms (or ferf indicators) ? manipulate the ferf-bit, within the ma byte (set them to "0") ? generate the ais pattern ? generate the los pattern ? generate ferf (yellow) alarms, in response to detection of a red alarm condition (via the receive section of the XRT72L50). f igure 177. a s imple i llustration of the t ransmit e3 f ramer b lock and the associated paths to other f unctional b locks transmit e3 framer block transmit e3 framer block transmit hdlc controller/buffer transmit overhead data input interface transmit payload data input interface to transmit e3 liu interface block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 382 ? generate and transmit a desired value for the febe (far-end-block error) bit, within the ma byte. the procedure and results of generating any of these alarm conditions is presented below. the user can exercise each of these options by writ- ing the appropriate data to the tx e3 configuration register (address = 0x30). the bit format of this reg- ister is presented below. bit-field 2 through 0 permit the user to transmit vari- ous alarm conditions to the remote terminal equip- ment. the role/function of each of these three bit- fields within the register, are discussed below. 6.2.4.2.1.1 tx ais enable - bit 2 this read/write bit field permits the user to force the transmission of an ais (alarm indication signal) pat- tern to the remote terminal equipment via software control. if the user opts to transmit an ais pattern, then the transmit section of the framer ic will begin to transmit an unframed all ones pattern to the re- mote terminal equipment. table 78 presents the rela- tionship between the contents of this bit-field, and the resulting framer action. n ote : this bit is ignored whenever the txlos bit-field is set. 6.2.4.2.1.2 transmit los enable - bit 1 this read/write bit field allows the user to transmit an los (loss of signal) pattern to the remote terminal, upon software control. table 79 relates the contents of this bit field to the transmit e3 framer block's ac- tion. txe3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl in nr not used txais enable txlos enable txmarx ro ro ro r/w ro r/w r/w r/w 00000000 t able 78: t he r elationship between the contents of b it 2 (t x ais e nable ) within the t x e3 c onfiguration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction b it 2t ransmit e3 f ramer ' s a ction 0 normal operation: the transmit section of the XRT72L50 framer ic will transmit e3 traffic based upon data that it accepts via the transmit payload data input interface block, the transmit overhead data input interface block, the trans- mit hdlc controller block and internally generated overhead bytes. 1 transmit ais pattern: the transmit e3 framer block will overwrite the e3 traffic, within an unframed all ones pattern. t able 79: t he r elationship between the contents of b it 1 (t x los) within the t x e3 c onfiguration r egister , and the resulting t ransmit e3 f ramer b lock ' s a ction b it 1t ransmit e3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the transmit overhead data input interface or the transmit hdlc controller blocks. the payload bits are received from the transmit payload data input interface. 1 transmit los pattern: when this command is invoked the transmit e3 framer will do the following. ? set all of the overhead bytes to "0" (including the fa1 and fa2 bytes) overwrite the e3 payload bits with an "all zeros" pattern. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 383 n ote : when this bit is set, it overrides all of the other bits in this register. 6.2.4.2.1.3 txmarx - bit 0 this read/write bit-field permits the user to force the XRT72L50 framer ic to transmit either a ferf (far- end receive failure) or a febe (far-end block er- ror) indication to the remote terminal equipment. 6.2.4.2.2 configuring the transmit trail trace buffer message the XRT72L50 framer ic contains 16 bytes worth of transmit trail trace buffer registers and 16 bytes worth of receive trail trace buffer registers. the role of the receive trail trace buffer registers are de- scribed in section 5.3.7. the XRT72L50 framer ic contains 16 transmit trail trace buffer registers (e.g., tx ttb-0 through txttb- 15). the purpose of these registers are to provide a 16-byte trail access point identifier to the remote terminal equipment. the remote terminal equip- ment will use this information in order to verify that it is still receiving data from its intended transmitter. the specific use of these registers follows. for trail trace buffer message purposes, the trans- mit e3 framer block will group 16 consecutive e3 frames, into a trail trace buffer super-frame. when the transmit e3 framer block is generating the first e3 frame, within a trail trace buffer super-frame, it will read in the contents of the tx ttb-0 register (ad- dress = 0x38) and insert this value into the tr byte- field of this very first outbound e3 frame. when the transmit e3 framer is generating the very next e3 frame (e.g., the second e3 frame, within the trail trace buffer super-frame), it will read in the contents of the tx ttb-1 register (address = 0x39) and insert this value into the tr byte-field of this outbound e3 frame. as the transmit e3 framer block is creating each subsequent e3 frame, within this trail trace buffer super frame, it will continue to increment to the very next transmit trail trace buffer register. the transmit e3 framer block will then read in the con- tents of this particular transmit trail trace buffer reg- ister (tx ttb-n) and insert this value into the tr byte- field of the very next outbound e3 frame. after the transmit e3 framer block has created the 16th e3 frame, within a given trail trace buffer super-frame (e.g., it has read in the contents of tx ttb-15 register and has inserted this value into the tr byte of the 16th e3 frame), it will begin to create a new trail trace buffer super-frame, by reading the contents of the tx ttb-0 register, and repeating the above-mentioned procedure. the contents of the tx ttb-0 register will typically be of the form [1, c6, c5, c4, c3, c2, c1, c0]. the 1 in the msb (most significant bit) position of this byte is used to designate that this octet is the frame-start marker (e.g., is the first of the 16 tr bytes, within a trail trace buffer super-frame). the remaining trail trace buffer registers (txttb-1 through txttb-15) will typically contain a 0 in their msb positions. the remaining bits within the tx ttb-0 register c6 through c0 are the crc-7 bits calculated over the contents of all 16 tr bytes, within the previous trail trace buffer super-frame. the contents of the re- maining trail trace buffer registers (e.g., tx ttb-1 through tx ttb-15) will typically contain the 15 ascii characters required for the e.164 numbering format. n otes : 1. the XRT72L50 framer ic will not compute the crc-7 value, to be written into the tx ttb-0 regis- ter. the users system must compute this value prior to writing it into the tx ttb-0 register. 2. the user, when writing data into the tx ttb regis- ters, must take care to insure that only the tx ttb- 0 register contains an octet with a 1 in the msb (most significant bit) position. all remaining tx ttb registers (e.g., tx ttb-1 through tx ttb-15) must contain octets with a 0 in the msb position. the reason for this cautionary note is presented in sec- tion 5.3.2.9. 6.2.5 the transmit e3 line interface block the XRT72L50 framer ic is a digital device that takes e3 payload and overhead bit information from some terminal equipment, processes this data and ul- timately, multiplexes this information into a series of outbound e3 frames. however, the XRT72L50 fram- er ic lacks the current drive capability to be able to di- rectly transmit this e3 data stream through some transformer-coupled coax cable with enough signal strength for it to be received by the remote receiver. therefore, in order to get around this problem, the framer ic requires the use of an liu (line interface unit) ic. an liu is a device that has sufficient drive capability, along with the necessary pulse-shaping circuitry to be able to transmit a signal through the transmission medium in a manner that it can be reli- ably received by the far-end receiver. figure 178 pre- sents a circuit drawing depicting the framer ic inter- facing to an liu (xrt7300 ds3/e3/sts-1 transmit liu). ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 384 the transmit section of the XRT72L50 contains a block which is known as the transmit e3 liu interface block. the purpose of the transmit e3 liu interface block is to take the outbound e3 data stream, from the transmit e3 framer block, and to do the following: 1. encode this data into one of the following line codes a. unipolar (e.g., single-rail) b. ami (alternate mark inversion) c. hdb3 (high density bipolar - 3) 2. and to transmit this data to the liu ic. figure 179 presents a simple illustration of the trans- mit e3 liu interface block. f igure 178. a pproach to i nterfacing the XRT72L50 f ramer ic device to the xrt73l00 ds3/e3/sts-1 liu 5v u1 xrt7250 txpos 65 txneg 64 txlineclk 63 dmo 79 extlos 78 rlol 77 lloop 69 rloop 70 taos 68 txlev 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 txser 46 txinclk 43 txframe 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 xrt7300 tpdata 37 tndata 38 tclk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tring 40 mtip 44 mring 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 taos 2 txlev 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 txser txinclk nibbleintf resetb rtip rring csb rw ds as txframe rxser rxclk rxframe rxlos rxoof rxred rxais a[8:0] tring ttip intb d[7:0] intb XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 385 the transmit e3 liu interface block can transmit data to the liu ic or other external circuitry via two differ- ent output modes: unipolar or bipolar. if the user se- lects unipolar (or single rail) mode, then the con- tents of the e3 frame is output, in a binary (nrz manner) data stream via the txpos pin to the liu ic. the txneg pin will only be used to denote the frame boundaries. txneg will pulse "high" for one bit peri- od, at the start of each new e3 frame, and will remain "low" for the remainder of the frame. figure 180 pre- sents an illustration of the txpos and txneg signals during data transmission while the transmit e3 liu interface block is operating in the unipolar mode. this mode is sometimes referred to as single rail mode because the data pulses only exist in one po- larity: positive. when the transmit e3 liu interface block is operating in the bipolar (or dual rail) mode, then the contents of the e3 frame is output via both the txpos and tx- neg pins. if the bipolar mode is chosen, then the e3 data can be transmitted to the liu via one of two dif- ferent line codes: alternate mark inversion (ami) or high density bipolar -3 (hdb3). each one of these line codes will be discussed below. bipolar mode is f igure 179. a s imple i llustration of the t ransmit e3 liu i nterface block from transmit e3 framer block txpos txneg txlineclk transmit e3 liu interface block f igure 180. t he b ehavior of t x pos and t x neg signals during data transmission while the t ransmit ds3 liu i nterface is operating in the u nipolar m ode txpos txneg txlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 frame boundary ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 386 sometimes referred to as dual rail because the data pulses occur in two polarities: positive and negative. the role of the txpos, txneg and txlineclk output pins, for this mode are discussed below. txpos - transmit positive polarity pulse: the transmit e3 liu interface block will assert this output to the liu ic when it desires for the liu to generate and transmit a positive polarity pulse to the remote terminal equipment. txneg - transmit negative polarity pulse: the transmit e3 liu interface block will assert this output to the liu ic when it desires for the liu to generate and transmit a negative polarity pulse to the remote terminal equipment. txlineclk - transmit line clock: the liu ic uses this signal from the transmit e3 liu interface block to sample the state of its txpos and txneg inputs. the results of this sampling dictates the type of pulse (positive polarity, zero, or negative polarity) that it will generate and transmit to the remote receive e3 framer. 6.2.5.1 selecting the various line codes the user can select either the unipolar mode or bipo- lar mode by writing the appropriate value to bit 3 of the i/o control register (address = 0x01), as shown below. table 80 relates the value of this bit field to the trans- mit e3 liu interface output mode. n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the operation of the receive e3 liu interface block 6.2.5.1.1 the bipolar mode line codes if the framer is selected to operate in the bipolar mode, then the ds3 data-stream can be transmitted via the ami (alternate mark inversion) or the hdb3 line codes. the definition of ami and hdb3 line codes follow. 6.2.5.1.1.1 the ami line code ami or alternate mark inversion, means that consec- utive "one's" pulses (or marks) will be of opposite po- larity with respect to each other. the line code in- volves the use of three different amplitude levels: +1, 0, and -1. +1 and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" ampli- tude pulses (or the absence of a pulse) are used to represent zeros (or space) pulses. the general rule for ami is: if a given mark pulse is of positive polarity, then the very next mark pulse will be of negative po- larity and vice versa. this alternating-polarity rela- tionship exists between two consecutive mark pulses, independent of the number of 'zeros' that may exist between these two pulses. figure 181 presents an il- lustration of the ami line code as would appear at the txpos and txneg pins of the framer, as well as the output signal on the line. i/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 80: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c ontrol r egister and the t ransmit e3 f ramer l ine i nterface o utput m ode b it 3t ransmit e3 f ramer liu i nterface o utput m ode 0 bipolar mode: ami or hdb3 line codes are transmitted and received 1 unipolar (single rail) mode of transmission and reception of e3 data is selected. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 387 n ote : one of the main reasons that the ami line code has been chosen for driving transformer-coupled media is that this line code introduces no dc component, thereby minimizing dc distortion in the line. 6.2.5.1.1.2 the hdb3 line code the transmit e3 framer and the associated liu ic combine the data and timing information (originating from the txlineclk signal) into the line signal that is transmitted to the remote receiver. the remote re- ceiver has the task of recovering this data and timing information from the incoming e3 data stream. many clock and data recovery schemes rely on the use of phase locked loop technology. phase-locked-loop (pll) technology for clock recovery relies on transi- tions in the line signal, in order to maintain lock with the incoming e3 data stream. however, pll-based clock recovery scheme, are vulnerable to the occur- rence of a long stream of consecutive zeros (e.g., the absence of transitions). this scenario can cause the pll to lose lock with the incoming e3 data, thereby causing the clock and data recovery process of the receiver to fail. therefore, some approach is needed to insure that such a long string of consecutive zeros can never happen. one such technique is hdb3 en- coding. hdb3 (or high density bipolar - 3) is a form of ami line coding that implements the following rule. in general the hdb3 line code behaves just like ami with the exception of the case when a long string of consecutive zeros occur on the line. any string of 4 consecutive zeros will be replaced with either a "000v" or a "b00v" where "b" refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the ami coding rule). and "v" refers to a bipolar violation pulse (e.g., a pulse with a polarity that vio- lates the alternating polarity scheme of ami.) the de- cision between inserting an "000v" or a "b00v" is made to insure that an odd number of bipolar (b) pulses exist between any two bipolar violation (v) pulses. figure 182 presents a timing diagram that il- lustrates examples of hdb3 encoding. the user chooses between ami or hdb3 line coding by writing to bit 4 of the i/o control register (address = 0x01), as shown below. f igure 181. i llustration of ami l ine c ode data txpos txneg line signal 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 f igure 182. i llustration of two examples of hdb3 e ncoding data txpos txneg txlineclk line signal 000v b00v 101 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 100 0 00 1 1 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 388 table 81 relates the content of this bit-field to the bi- polar line code which e3 data will be transmitted and received at. n otes : 1. this bit is ignored if the unipolar mode is selected. 2. this selection also effects the operation of the receive e3 liu interface block 6.2.5.2 txlineclk clock edge selection the framer also allows the user to specify whether the e3 output data (via txpos and/or txneg output pins) is to be updated on the rising or falling edges of the txlineclk signal. this selection is made by writ- ing to bit 2 of the i/o control register, as depicted be- low. table 82 relates the contents of this bit field to the clock edge of txclk that e3 data is output on the tx- pos and/or txneg output pins. n ote : the user will typically make the selection based upon the set-up and hold time requirements of the transmit liu ic. i/o control register (address = 0x01) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/wr/wr/wr/wr/w 101 00000 t able 81: t he r elationship between b it 4 (ami/ hdb3*) within the i/o c ontrol r egister and the b ipolar l ine c ode that is output by the t ransmit e3 liu i nterface b lock b it 4b ipolar l ine c ode 0 hdb3 1ami ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 10100 000 t able 82: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 2r esult 0 rising edge: outputs on txpos and/or txneg are updated on the rising edge of txlineclk. see figure 183 for timing relationship between txlineclk, txpos and txneg signals, for this selection. 1 falling edge: outputs on txpos and/or txneg are updated on the falling edge of txlineclk. see figure 184 for timing relationship between txlineclk, txpos and txneg signals, for this selection. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 389 6.2.6 transmit section interrupt processing the transmit section of the XRT72L50 can generate an interrupt to the microprocessor/microcontroller for the following reasons. ? completion of transmission of lapd message 6.2.6.1 enabling transmit section interrupts as mentioned in section 36, the interrupt structure, within the XRT72L50 contains two hierarchical levels: ? block level ? source level the block level the enable state of the block level for the transmit section interrupts dictates whether or not interrupts (enabled) at the source level, are actually enabled. the user can enable or disable these transmit sec- tion interrupts, at the block level by writing the appro- priate data into bit 1 (tx ds3/e3 interrupt enable) within the block interrupt enable register (address = 0x04), as illustrated below. f igure 183. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the rising edge of t x l ine c lk txlineclk txpos txneg t32 t30 t33 f igure 184. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the falling edge of t x l ine c lk txlineclk txpos txneg t31 t32 t33 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 390 setting this bit-field to 1 enables the transmit sec- tion (at the block level) for interrupt generation. conversely, setting this bit-field to 0 disables the transmit section for interrupt generation. what does it mean for the transmit section inter- rupts to be enabled or disabled at the block lev- el? if the transmit section is disabled (for interrupt gener- ation) at the block level, then all transmit section interrupts are disabled, independent of the interrupt enable/disable state of the source level interrupts. if the transmit section is enabled (for interrupt gener- ation) at the block level, then a given interrupt will be enabled at the source level. conversely, if the trans- mit section is enabled (for interrupt generation) at the block level, then a given interrupt will still be disabled, if it is disabled at the source level. as mentioned earlier, the transmit section of the XRT72L50 framer ic contains the completion of transmission of lapd message interrupt. the enabling/disabling and servicing of this interrupt is presented below. 6.2.6.1.1 the completion of transmission of the lapd message interrupt if the transmit section interrupts have been enabled at the block level, then the user can enable or disable the completion of transmission of a lapd message interrupt by writing the appropriate value into bit 1 (txlapd interrupt enable) within the tx e3 lapd status & interrupt register (address = 0x34), as illus- trated below. setting this bit-field to 1 enables the completion of transmission of a lapd message interrupt. con- versely, setting this bit-field to 0 disables the com- pletion of transmission of a lapd message interrupt. 6.2.6.1.2 servicing the completion of trans- mission of a lapd message interrupt as mentioned previously, once the user commands the lapd transmitter to begin its transmission of a lapd message, it will do the following. 1. it will parse through the contents of the transmit lapd message buffer (located at address loca- tions 0x86 through 0xdd) and search for a string of five (5) consecutive 1s. if the lapd trans- mitter finds a string of five consecutive 1s (within the content of the lapd message buffer, then it will insert a 0 immediately after this string. 2. it will compute the fcs (frame check sequence) value and append this value to the back-end of the user-message. 3. it will read out of the content of the user (zero- stuffed) message and will encapsulate this data into a lapd message frame. 4. finally, it will begin transmitting the contents of this lapd message frame via the n bits, within each outbound e3 frame. 5. once the lapd transmitter has completed its transmission of this lapd message frame (to the remote terminal equipment), the XRT72L50 framer ic will generate the completion of trans- block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one-second interrupt enable r/wrororororor/wr/w 00000000 txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 000000x0 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 391 mission of a lapd message interrupt to the microcontroller/microprocessor. once the XRT72L50 framer ic generates this interrupt, it will do the following. ? assert the interrupt output pin (int) by toggling it low. ? set bit 0 (txlapd interrupt status) within the txe3 lapd status and interrupt register, to 1 as illus- trated below. the purpose of this interrupt is to alert the microcon- troller/microprocessor that the lapd transmitter has completed its transmission of a given lapd (or pm- dl) message, and is now ready to transmit the next pmdl message, to the remote terminal equipment. 6.3 t he r eceive s ection of the XRT72L50 (e3 m ode o peration ) when the XRT72L50 has been configured to operate in the e3 mode, the receive section of the XRT72L50 consists of the following functional blocks. ? receive liu interface block ? receive hdlc controller block ? receive e3 framer block ? receive overhead data output interface block ? receive payload data output interface block figure 185 presents a simple illustration of the re- ceive section of the XRT72L50 framer ic. each of these functional blocks will be discussed in detail in this document. 6.3.1 the receive e3 liu interface block the purpose of the receive e3 liu interface block is two-fold: 1. to receive encoded digital data from the e3 liu ic. txe3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000001 f igure 185. a s imple i llustration of the r eceive s ection of the XRT72L50, when it has been config - ured to operate in the e3 m ode receive payload data input interface block receive ds3/e3 framer block receive liu interface block rxser rxnib[3:0] rxclk rxpos rxneg rxlineclk receive overhead input interface block rxohclk rxohind rxoh rxohenable rxohframe rxframe rx e3 hdlc controller/buffer rx e3 hdlc controller/buffer from microprocessor interface block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 392 2. to decode this data, convert it into a binary data stream and to route this data to the receive e3 framer block. figure 186 presents a simple illustration of the re- ceive e3 liu interface block. the receive section of the XRT72L50 will via the re- ceive e3 liu interface block receive timing and data information from the incoming e3 data stream. the e3 timing information will be received via the rxli- neclk input pin and the e3 data information will be re- ceived via the rxpos and rxneg input pins. the receive e3 liu interface block is capable of receiving e3 data pulses in unipolar or bipolar format. if the receive e3 framer is operating in the bipolar format, then it can be configured to decode either ami or hdb3 line code data. each of these input formats and line codes will be discussed in detail, below. 6.3.1.1 unipolar decoding if the receive e3 liu interface block is operating in the unipolar (single-rail) mode, then it will receive the single rail nrz ds3 data pulses via the rxpos in- put pin. the receive e3 liu interface block will also receive its timing signal via the rxlineclk signal. n ote : the rxlineclk signal will function as the timing source for the entire receive section of the XRT72L50. no data pulses will be applied to the rxneg input pin. the receive e3 liu interface block receives a logic "1" when a logic "1" level signal is present at the rxpos pin, during the sampling edge of the rxli- neclk signal. likewise, a logic "0" is received when a logic "0" level signal is applied to the rxpos pin. figure 187 presents an illustration of the behavior of the rxpos, rxneg and rxlineclk input pins when the receive e3 liu interface block is operating in the unipolar mode. f igure 186. a s imple i llustration of the r eceive e3 liu i nterface b lock rxpos rxneg rxlineclk to receive ds3 framer block receive ds3 liu interface block XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 393 the user can configure the receive e3 liu interface block to operate in either the unipolar or the bipolar mode by writing the appropriate data to the i/o con- trol register, as depicted below. table 83 relates the value of this bit-field to the re- ceive e3 liu interface input mode. n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the transmit e3 framer line interface output mode 6.3.1.2 bipolar decoding if the receive e3 liu interface block is operating in the bipolar mode, then it will receive the e3 data puls- es via both the rxpos, rxneg, and the rxlineclk input pins. figure 188 presents a circuit diagram il- lustrating how the receive e3 liu interface block in- terfaces to the line interface unit while the framer is operating in bipolar mode. the receive e3 liu inter- face block can be configured to decode either the ami or hdb3 line codes. f igure 187. b ehavior of the r x pos, r x neg and r x l ine c lk signals during data reception of u nipo - lar d ata rxpos rxneg rxlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 83: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the i/o c ontrol r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 3r eceive e3 liu i nterface i nput m ode 0 . bipolar mode (dual rail): ami or hdb3 line codes are transmitted and received. 1 unipolar mode (single rail) mode of transmission and reception of e3 data is selected. ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 394 6.3.1.2.1 ami decoding ami or alternate mark inversion, means that consec- utive "one's" pulses (or marks) will be of opposite po- larity with respect to each other. this line code in- volves the use of three different amplitude levels: +1, 0, and -1. the +1 and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" ampli- tude pulses (or the absence of a pulse) are used to represent zeros (or space) pulses. the general rule for ami is: if a given mark pulse is of positive polarity, then the very next mark pulse will be of negative po- larity and vice versa. this alternating-polarity rela- tionship exists between two consecutive mark pulses, independent of the number of zeros that exist be- tween these two pulses. figure 189 presents an illus- tration of the ami line code as would appear at the rxpos and rxneg pins of the framer, as well as the output signal on the line. f igure 188. i llustration on how the XRT72L50 r eceive e3 f ramer is interfaced to the xrt73l00 l ine i nterface u nit while operating in the b ipolar mode ( one channel shown ) 5v u1 xrt7250 txpos 65 txneg 64 txlineclk 63 dmo 79 extlos 78 rlol 77 lloop 69 rloop 70 taos 68 txlev 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 txser 46 txinclk 43 txframe 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 xrt7300 tpdata 37 tndata 38 tclk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tring 40 mtip 44 mring 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 taos 2 txlev 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 txser txinclk nibbleintf resetb rtip rring csb rw ds as txframe rxser rxclk rxframe rxlos rxoof rxred rxais a[8:0] tring ttip intb d[7:0] intb XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 395 n ote : one of the reasons that the ami line code has been chosen for driving copper medium, isolated via trans- formers, is that this line code has no dc component, thereby eliminating dc distortion in the line. 6.3.1.2.2 hdb3 decoding the transmit e3 liu interface block and the associat- ed liu embed and combine the data and clocking in- formation into the line signal that is transmitted to the remote terminal equipment. the remote terminal equipment has the task of recovering this data and timing information from the incoming e3 data stream. most clock and data recovery schemes rely on the use of phase-locked-loop technology. one of the problems of using phase-locked-loop (pll) technol- ogy for clock recovery is that it relies on transitions in the line signal, in order to maintain lock with the in- coming e3 data-stream. therefore, these clock re- covery scheme, are vulnerable to the occurrence of a long stream of consecutive zeros (e.g., no transitions in the line). this scenario can cause the pll to lose lock with the incoming e3 data, thereby causing the clock and data recovery process of the receiver to fail. therefore, some approach is needed to insure that such a long string of consecutive zeros can never happen. one such technique is hdb3 (or high den- sity bipolar -3) encoding. in general the hdb3 line code behaves just like ami with the exception of the case when a long string of consecutive zeros occurs on the line. any 4 consecu- tive zeros will be replaced with either a "000v" or a "b00v" where "b" refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the ami coding rule). and "v" refers to a bipolar violation pulse (e.g., a pulse with a polarity that violates the al- ternating polarity scheme of ami.) the decision be- tween inserting an "000v" or a "b00v" is made to in- sure that an odd number of bipolar (b) pulses exist between any two bipolar violation (v) pulses. the receive e3 liu interface block, when operating with the hdb3 line code is responsible for decoding the hd-encoded data back into a unipolar (binary-for- mat). for instance, if the receive e3 liu interface block detects a "000v" or a "b00v" pattern in the in- coming pattern, the receive e3 liu interface block will replace it with four (4) consecutive zeros. figure 190 presents a timing diagram that illustrates examples of hdb3 decoding. f igure 189. i llustration of ami l ine c ode data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 rxpos rxneg line signal f igure 190. i llustration of two examples of hdb3 d ecoding line signal 000v b00v rxneg rxpos data 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 100 0 00 1 1 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 396 6.3.1.2.3 line code violations the receive e3 liu interface block will also check the incoming e3 data stream for line code violations. for example, when the receive e3 liu interface block detects a valid bipolar violation (e.g., in hdb3 line code), it will substitute four zeros into the binary data stream. however, if the bipolar violation is in- valid, then an lcv (line code violation) is flagged and the pmon lcv event count register (address = 0x50 and 0x51) will also be incremented. additional- ly, the lcv-one-second accumulation registers (address = 0x6e and 0x6f) will be incremented. for example: if the incoming e3 data is hdb3 encoded, the receive e3 liu interface block will also increment the lcv one-second accumulation register if three (or more) consecutive zeros are received. 6.3.1.2.4 rxlineclk clock edge selection the incoming unipolar or bipolar data, applied to the rxpos and the rxneg input pins are clocked into the receive e3 liu interface block via the rxlineclk signal. the framer ic allows the user to specify which edge (e.g, rising or falling) of the rxlineclk signal will sample and latch the signal at the rxpos and rxneg input signals into the framer ic. the us- er can make this selection by writing the appropriate data to bit 1 of the i/o control register, as depicted below. table 84 depicts the relationship between the value of this bit-field to the sampling clock edge of rxlineclk. figure 191 and figure 192 present the waveform and timing relationships between rxlineclk, rxpos and rxneg for each of these configurations. ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 101000 00 t able 84: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r egister , and the sampling edge of the r x l ine c lk signal r x clki nv (b it 1) r esult 0 .rising edge: rxpos and rxneg are sampled at the rising edge of rxlineclk. see figure 191 for timing relationship between rxlineclk, rxpos, and rxneg. 1 falling edge: rxpos and rxneg are sampled at the falling edge of rxlineclk. see figure 192 for timing relationship between rxlineclk, rxpos, and rxneg. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 397 6.3.2 the receive e3 framer block the receive e3 framer block accepts decoded e3 data from the receive e3 liu interface block, and routes data to the following destinations. ? the receive payload data output interface block ? the receive overhead data output interface block. ? the receive e3 hdlc controller block figure 193 presents a simple illustration of the re- ceive e3 framer block, along with the associated paths to the other functional blocks within the framer chip. f igure 191. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the rising edge of r x l ine c lk rxlineclk rxpos rxneg t38 t39 t42 f igure 192. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the falling edge of r x l ine c lk rxlineclk rxpos rxneg t40 t41 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 398 once the hdb3 (or ami) encoded data has been de- coded into a binary data-stream, the receive e3 framer block will use portions of this data-stream in order to synchronize itself to the remote terminal equipment. at any given time, the receive e3 fram- er block will be operating in one of two modes. ? the frame acquisition mode: in this mode, the receive e3 framer block is trying to acquire syn- chronization with the incoming e3 frame, or ? the frame maintenance mode: in this mode, the receive e3 framer block is trying to maintain frame synchronization with the incoming e3 frames. figure 194 presents a state machine diagram that depicts the receive e3 framer block's e3/itu-t g.832 frame acquisition/maintenance algorithm. 6.3.2.1 the framing acquisition mode the receive e3 framer block is considered to be op- erating in the frame acquisition mode, if it is operat- ing in any one of the following states within the e3 frame acquisition/maintenance algorithm per figure 194. ? fa1, fa2 octet search state ? fa1, fa2 octet verification state ? oof condition state ? lof condition state each of these framing acquisition states, within the receive e3 framer framing acquisition/maintenance state machine are discussed below. the fa1 , fa2 oc te t s ea rch s tate when the receive e3 framer block is first powered up, it will be operating in the fa1, fa2 octet search state. while the receive e3 framer is operating in this state, it will be performing a bit-by-bit search for the fa1 and fa2 framing alignment octets. fa1 is assigned the value 0xf6, and fa2 is assigned the value of 0x28. figure 195, which presents an illus- tration of the e3, itu-t g.832 framing format, indi- cates that these two octets will occur at the beginning of each e3 frame, and that the fa2 octet will appear immediately after the fa1 octet. f igure 193. a s imple i llustration of the r eceive e3 f ramer b lock and the a ssociated p aths to the o ther f unctional b locks receive e3 framer block receive e3 framer block to receive e3 hdlc buffer receive overhead data output interface receive payload data output interface from receive e3 liu interface block XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 399 f igure 194. t he s tate m achine d iagram for the r eceive e3 f ramer e3 f rame a cquisition /m aintenance a lgorithm fa1, fa2 octet search fa1, fa2 octet verification in frame oof condition lof condition fa1 and fa2 octets are detected once fa1 and fa2 octets are verified once fa1 and fa2 octets are not detected 4 consecutive in-valid frames 3 consecutive valid frames 1 or 3 ms of operating in the oof condition (user-selectable) frame maintenance mode ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 400 when the receive e3 framer block detects the fa1 octet, and determines that this octet is immediately followed by the fa2 octet, then it will transition to the fa1, fa2 octet verification state, per figure 195. the fa1, fa2 octet verification state once the receive e3 framer block has detected an 0xf628 pattern (e.g., the concatenation of the fa1 and fa2 octets), it must verify that this pattern is in- deed the fa1 and fa2 octets and not some other set of bytes, within the e3 frame, mimicking the frame alignment bytes. hence, the purpose of the fa1, fa2 octet verification state. when the receive e3 framer block enters this state, it will then quit performing its bit-by-bit search for the frame alignment bytes. instead, the receive e3 framer block will read in the two octets that occur 537 bytes (e.g., one e3 frame period later) after the candi- date frame alignment patterns were first detected. if these two bytes match the assigned values for the fa1 and fa2 octets, then the receive e3 framer block will conclude that it has found the frame align- ment bytes and will then transition to the in-frame state. however, if these two bytes do not match the assigned values for the fa1 and fa2 octets then the receive e3 framer block will concluded that it has been fooled by data mimicking the frame align- ment bytes, and will transition back to the fa1, fa2 octet search state. in frame state once the receive e3 framer block enters the in- frame state, then it will cease performing frame ac- quisition functions, and will proceed to perform fram- ing maintenance functions. therefore, the operation of the receive e3 framer block, while operating in the in-frame state, can be found in section 5.3.2.2 (the framing maintenance mode). oof (out of frame) condition state if the receive e3 framer while operating in the in- frame state detects four (4) consecutive frames, which do not have the valid frame alignment (fa1 and fa2 octet) patterns, then it will transition into the oof condition state. the receive e3 framer blocks operation, while in the oof condition state is a unique mix of framing maintenance and framing acquisition operation. the receive e3 framer block will exhibit some framing acquisition characteristics by attempting to locate (once again) the frame align- ment octets. however, the receive e3 framer block will also exhibit some frame maintenance behavior by still using the most recent frame synchronization for its overhead byte and payload byte processing. the receive e3 framer block will inform the micro- processor/microcontroller of its transition from the in- frame state to the oof condition state, by generat- ing a change in oof condition interrupt. when this occurs, bit 3 (oof interrupt status), within the rx e3 f igure 195. i llustration of the e3, itu-t g.832 f raming f ormat fa1 fa2 em tr ma 1 byte 59 bytes 60 columns 9 rows 530 octet payload gc nr XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 401 interrupt status register - 1, will be set to 1, as de- picted below. the receive e3 framer block will also inform the ex- ternal circuitry of its transition into the oof condition state, by toggling the rxoof output pin high. if the receive e3 framer block is capable of finding the framing alignment octets within a user-selectable number of e3 frame periods, then it will transition back into the in-frame state. the receive e3 framer block will then inform the microprocessor/microcon- troller of its transition back into the in-frame state by generating the change in oof condition interrupt. however, if the receive e3 framer block resides in the oof condition state for more than this user-se- lectable number of e3 frame periods, then it will auto- matically transition to the lof (loss of frame) condi- tion state. the user can select this user-selectable number of e3 frame periods that the receive e3 framer block will remain in the oof condition state by writing the appropriate value into bit 7 (rxlof algo) within the rx e3 configuration & status register, as depicted below. writing a 0 into this bit-field causes the receive e3 framer block to reside in the oof condition state for at most 24 e3 frame periods (3 ms). writing a 1 into this bit-field causes the receive e3 framer block to reside in the oof condition state for at most 8 e3 frame periods (1 ms). lof (loss of framing) condition state if the receive e3 framer block enters the lof condi- tion state, then the following things will happen. ? the receive e3 framer block will discard the most recent frame synchronization and ? the receive e3 framer block will make an uncon- ditional transition to the fa1, fa2 octet search state. ? the receive e3 framer block will notify the micro- processor/microcontroller of its transition to the lof condition state, by generating the change in lof condition interrupt. when this occurs, bit 2 (lof interrupt status), within the rx e3 interrupt status register - 1 will be set to 1, as depicted below. rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000000 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 01111111 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 402 finally, the receive e3 framer block will also inform the external circuitry of this transition to the lof con- dition state by toggling the rxlof output pin high. 6.3.2.2 the framing maintenance mode once the receive e3 framer block enters the in- frame state, then it will notify the microprocessor/mi- crocontroller of this fact by generating both the change in oof condition and change in lof condi- tion interrupts. when this happens, bits 2 and 3 (lof interrupt status and oof interrupt status) will be set to 1, as depicted below. additionally, the receive e3 framer block will inform the external circuitry of its transition to the in-frame state by toggling both the rxoof and rxlof output pins "low. finally, the receive e3 framer block will negate both the rxoof and the rxlof bit-fields within the rx e3 configuration & status register, as depicted below. when the receive e3 framer block is operating in the in-frame state, it will then begin to perform frame maintenance operations, where it will continue to ver- ify that the frame alignment octets (fa1, fa2) are present, at their proper locations. while the receive e3 framer block is operating in the frame mainte- nance mode, it will declare an out-of-frame (oof) condition if it detects invalid framing alignment bytes in four consecutive frames. since the receive e3 framer block requires the de- tection of invalid frame alignment bytes in four con- secutive frames, in order for it to transition to the oof condition state, it can tolerate some errors in the framing alignment bytes, and still remain in the in- frame state. however, each time the receive e3 framer block detects an error in the frame alignment bytes, it will increment the pmon framing error event count registers (address = 0x52 and 0x53). the bit-format for these two registers are depicted be- low. rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00001100 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 01100000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 403 6.3.2.3 forcing a reframe via software com- mand the XRT72L50 framer ic permits the user to com- mand a reframe procedure with the receive e3 fram- er block via software command. if the user writes a 1 into bit 0 (reframe) within the i/o control register (address = 0x01), as depicted below, then the re- ceive e3 framer block will be forced into the fa1, fa2 octet search state, per figure 194, and will begin its search for the fa1 and fa2 octets.) the framer ic will respond to this command by doing the following. 1. asserting both the rxoof and rxlof output pins. 2. generating both the change in oof status and the change in lof status interrupts to the micro- processor. 3. asserting both the rxlof and rxoof bit-fields within the rx e3 configuration & status register, as depicted below. 6.3.2.4 performance monitoring of the frame synchronization section, within the receive e3 framer block the user can monitor the number of framing bytes (fa1 and fa2 bytes) errors that have been detected by the receive e3 framer block. this is accom- pmon framing bit/byte error count register - msb (address = 0x52) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit/byte error count - high byte rurrurrurrurrurrurrurrur 00000000 pmon framing bit/byte error count register - lsb (address = 0x53) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit/byte error count - low byte rurrurrurrurrurrurrurrur 00000000 i/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/ zerosup* unipolar/bipo- lar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 10100001 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 01111111 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 404 plished by periodically reading the pmon framing bit/byte error event count registers (address = 0x52 and 0x53). the byte format of these registers are presented below. 6.3.2.5 the rxoof and rxlof output pin. the user can roughly determine the current framing state that the receive e3 framer block is operating in by reading the logic state of the rxoof and the rx- lof output pins. table 85 presents the relationship between the state of the rxoof and rxlof output pins, and the framing state of the receive e3 framer block. 6.3.2.6 e3 receive alarms 6.3.2.6.1 the loss of signal (los) alarm declaring an los condition the receive e3 framer block will declare a loss of signal (los) condition, when it detects 32 consecu- tive incoming 0s via the rxpos and rxneg input pins or if the extlos input pin (from the xrt7300 ds3/e3/sts-1 liu ic) is asserted. the receive e3 framer block will indicate that it is declaring an los condition by. ? asserting the rxlos output pin (e.g., toggling it high). ? setting bit 4 (rxlos) of the rx e3 configuration & status register to 1 as depicted below. ? the receive e3 framer block will generate a change in los condition interrupt request. upon generating this interrupt request, the receive e3 framer block will assert bit 1 (los interrupt status within the rx e3 framer interrupt status register - 1, as depicted below. clearing the los condition the receive e3 framer block will clear the los con- dition when it encounters a stream of 32 bits that does not contain a string of 4 consecutive zeros. t able 85: t he r elationship between the l ogic s tate of the r x oof and r x lof output pins , and the f raming s tate of the r eceive e3 f ramer block r x lof r x oof f raming s tate of the r eceive e3 f ramer block 00 in frame 01 oof condition (the receive e3 framer block is operating in the 3ms oof period). 10 invalid 11 lof condition rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 00010000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000010 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 405 when the receive e3 framer block clears the los condition, then it will notify the microprocessor and the external circuitry of this occurrence by: ? generating the change in los condition interrupt to the microprocessor. ? clearing bit 4 (rxlos) within the rx e3 configura- tion & status register, as depicted below. ? clear the rxlos output pin (e.g., toggle it "low). 6.3.2.6.2 the ais (alarm indication status) condition declaring the ais condition the receive e3 framer block will identify and declare an ais condition, if it detects an all ones pattern in the incoming e3 data stream. more specifically, the receive e3 framer block will declare an ais condi- tion if 7 or less 0s are detected in each of 2 consec- utive e3 frames. if the receive e3 framer block declares an ais con- dition, then it will do the following. ? generate the change in ais condition interrupt to the microprocessor. hence, the receive e3 framer block will assert bit 1 (ais interrupt status) within the rx e3 framer interrupt status register - 1, as depicted below. ? assert the rxais output pin. ? set bit 3 (rx ais) within the rx e3 configuration & status register, as depicted below. clearing the ais condition the receive e3 framer block will clear the ais condi- tion when it detects two consecutive e3 frames, with eight or more zeros in the incoming data stream. the receive e3 framer block will inform the micro- processor that the ais condition has been cleared by: ? generating the change in ais condition interrupt to the microprocessor. hence, the receive e3 framer block will assert bit 1 (ais interrupt status) rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 00010000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000001 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 00001000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 406 within the rx e3 framer interrupt status register - 1. ? clearing the rxais output pin (e.g., toggling it "low). ? setting the rxais bit-field, within the rx e3 config- uration & status register to 0, as depicted below. 6.3.2.6.3 the far-end-receive failure (ferf) condition declaring the ferf condition the receive e3 framer block will declare a far-end receive failure (ferf) condition if it detects a user- selectable number of consecutive incoming e3 frames, with the ferf bit-field (bit 7, within the ma byte) set to 1. recall, the bit-format of the ma byte is presented below. this user-selectable number of e3 frames is either 3 or 5, depending upon the value that has been written into bit 4 (rx ferf algo) within the rx e3 configura- tion & status register, as depicted below. writing a 0 into this bit-field causes the receive e3 framer block to declare a ferf condition, if it detects 3 consecutive incoming e3 frames, that have the ferf bit (within the ma byte) set to 1. writing a 1 into this bit-field causes the receive e3 framer block to declare a ferf condition, if it detects 5 consecutive incoming e3 frames, that have the ferf bit (within the ma byte) set to 1. whenever the receive e3 framer block declares a ferf condition, then it will do the following. ? generate a change in ferf condition interrupt to the microprocessor. hence, the receive e3 framer block will assert bit 3 (ferf interrupt sta- tus) within the rx e3 framer interrupt status regis- ter - 2, as depicted below. rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 00000000 the maintenance and adaptation (ma) byte format b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ferf febe payload type payload dependent timing marker rxe3 configuration & status register 1 - (e3, itu-t g.832) (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxpldtype[2:0] rxferf algo rxtmark algo rxpldexp[2:0] ro ro ro ro ro ro ro ro 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 407 ? set the rx ferf bit-field, within the rx e3 configu- ration/status register to 1, as depicted below. clearing the ferf condition the receive e3 framer block will clear the ferf condition once it has received a user-selectable number of e3 frames is either 3 or 5 depending upon the value that has been written into bit 4 (rx ferf algo) of the rx e3 configuration/status register, as discussed above. whenever the receive e3 framer clears the ferf status, then it will do the following: 1. generate a change in the ferf status interrupt to the microprocessor. 2. clear the bit 0 (rxferf) within the rx e3 con- figuration & status register, as depicted below. 6.3.2.7 error checking of the incoming e3 frames the receive e3 framer block performs error-check- ing on the incoming e3 frame data that it receives from the remote terminal equipment. it performs this error-checking by computing the bip-8 value of an incoming e3 frame. once the receive e3 framer block has obtained this value, it will compare this val- ue with that of the em byte that it receives, within the very next e3 frame. if the locally computed bip-8 value matches the em byte of the corresponding e3 frame, then the receive e3 framer block will con- clude that this particular frame has been properly re- ceived. the receive e3 framer block will then inform the remote terminal equipment of this fact by having the local terminal equipment transmit e3 framer block send the remote terminal an e3 frame, with the febe bit-field, within the ma byte, set to 0. this procedure is illustrated in figure 196 and figure 197. figure 196 illustrates the local receive e3 framer receiving an error-free e3 frame. in this figure, the lo- cally computed bip-8 value of 0x5a matches that received from the remote terminal, within the em byte-field. figure 197 illustrates the subsequent ac- rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 00001000 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 00000001 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo 00000001 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 408 tion of the local transmit e3 framer block, which will transmit an e3 frame to the remote terminal, with the febe bit-field set to 0 . this signaling indicates that the local receive e3 framer has received an er- ror-free e3 frame. f igure 196. i llustration of the l ocal r eceive e3 f ramer block , receiving an e3 f rame ( from the r emote t erminal ) with a correct em b yte . transmit e3 framer receive e3 framer local terminal remote terminal em byte locally calculated em byte 0x5a 0x5a f igure 197. i llustration of the l ocal r eceive e3 f ramer block , transmitting an e3 f rame ( to the r emote t erminal ) with the febe bit ( within the ma byte - field ) set to 0 transmit e3 framer receive e3 framer local terminal remote terminal ma byte x0xxxxxx febe bit XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 409 however, if the locally computed bip-8 value does not match the em byte of the corresponding e3 frame, then the receive e3 framer block will do the follow- ing. ? it will inform the remote terminal of this fact by having the local transmit e3 framer block send the remote terminal an e3 frame, with the febe bit- field, within the ma byte, set to 1. this phenome- non is illustrated below in figure 198 and figure 199. figure 198 illustrates the local receive e3 framer receiving an errored e3 frame. in this figure, the lo- cal receive e3 frame block is receiving an e3 frame with an em byte containing the value 0x5a. this value does not match the locally computed em byte value of 0x5b. consequently, there is an error in this e3 frame. figure 199 illustrates the subsequent action of the local transmit e3 framer block, which will transmit an e3 frame, with the febe bit-field set to 1 to the remote terminal. this signaling indicates that the local receive e3 framer block has received an er- rored e3 frame. f igure 198. i llustration of the l ocal r eceive e3 f ramer block , receiving an e3 f rame ( from the r emote t erminal ) with an incorrect em b yte . transmit e3 framer receive e3 framer local terminal remote terminal em byte locally calculated em byte 0x5a 0x5b ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 410 in additional to the febe bit-field signaling, the re- ceive e3 framer block will generate the bip-8 error interrupt to the microprocessor. hence, it will set bit 2 (bip-8 error interrupt status) to 1, as depicted be- low. finally, the receive e3 framer block will increment the pmon parity error count registers. the byte for- mat of these registers are presented below. f igure 199. i llustration of the l ocal r eceive e3 f ramer block , transmitting an e3 f rame ( to the r emote t erminal ) with the febe bit ( within the ma byte - field ) set to 1 transmit e3 framer receive e3 framer local terminal remote terminal ma byte x1xxxxxx febe bit rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00000000 pmon parity error count register - msb (address = 0x54) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - high byte rur rur rur rur rur rur rur rur 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 411 the user can determine the number of bip-8 errors that have been detected by the receive e3 framer block, since the last read of these registers. these registers are reset-upon-read. 6.3.2.8 processing of the far-end-block error (febe) bit-fields whenever the receive e3 framer detects an error in the incoming e3 frame, via em byte verification, it will inform the local transmit e3 framer of this fact. the local transmit e3 framer will, in turn, notify the re- mote terminal (e.g., the source of the errored e3 frame) by transmitting an e3 frame, with the febe bit-field (within the ma byte) set to 1. if the receive e3 framer receives any e3 frame, with the febe bit-field set to 1, then it will do the follow- ing. ? it will generate a febe event interrupt to the micro- processor/microcontroller. hence, the receive e3 framer block will set bit 4 (febe interrupt status) within the rx e3 framer interrupt status register - 2, as depicted below. ? increment the pmon received febe event count register - msb/lsb, which is located at 0x56 and 0x57 in the framer address space. the byte-for- mat of these registers are presented below. the user can determine the total number of febe events (e.g., e3 frames that have been received with pmon parity error count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - low byte rurrurrurrurrurrurrurrur 00000000 rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00010000 pmon febe event count register - msb (address = 0x56) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - high byte rurrurrurrurrurrurrurrur 00000000 pmon febe event count register - lsb (address = 0x57) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - low byte rurrurrurrurrurrurrurrur 00000000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 412 the febe bit-field set to 1) that have occurred since the last read of this register. this register is reset-up- on-read. 6.3.2.9 receiving the trail trace buffer mes- sages the XRT72L50 framer ic device contains 16 bytes worth of transmit trail trace buffers, and 16 bytes worth of receive trail trace buffers, as described be- low. the role of the transmit trail trace buffers are described in section 5.2.4.2.. the XRT72L50 ds3/e3 framer ic contains 16 re- ceive trail trace buffer registers (e.g., rxttb-0 through rxttb-15). the purpose of these registers are to receive and store the incoming trail access point identifier from the remote transmitting termi- nal. the local receiving terminal will use this information to verify that it is still receiving data from its intended transmitter. the specific use of these registers fol- lows. for trail trace buffer purposes, the remote transmit e3 framer block will group 16 consecutive e3 frames into a trail trace buffer super-frame. when the re- mote transmit e3 framer is generating the first e3 frame, within a trail trace buffer super-frame, it will insert the value [1, c6, c5, c4, c3, c2, c1, c0], into the tr byte-field of this outbound e3 frame. the re- maining 15 tr byte-fields (within this trail trace buff- er super-frame) will consists of ascii characters that are required for the e.164 numbering format. when the local receive e3 framer block receives an e3 frame, containing a value in the tr byte that has a 1 in the msb position, then it (the receive e3 fram- er block) will write this value into the rxttb-0 regis- ter (address = 0x1c). once this occurs, the receive e3 framer block will notify the microprocessor of this new incoming trail trace buffer message by generat- ing the change in trail trace buffer message inter- rupt. the receive e3 framer block will also set bit 6 (ttb change interrupt status) within the rx e3 framer interrupt status register - 2, as depicted be- low. the contents of the tr byte-field, in the very next e3 frame will be written into the rx ttb-1 register (ad- dress = 0x1d), and so on until all 16 bytes have been received. n otes : 1. anytime the receive e3 framer block receives an e3 frame that contains an octet in the tr byte-field, with a 1 in the msb (most significant bit) position, then the receive e3 framer block will (1) write the contents of the tr byte-field (in this e3 frame) into the rxttb-0 register, 2. it will generate the change in trail trace buffer interrupt. the receive e3 framer will do these things independent of the number of e3 frames that have been received since the last occurrence of the change in trail trace buffer interrupt. hence, the user, when writing data into the tx ttb registers, must take care to insure that only the tx ttb-0 reg- ister contains an octet with a 1 in the msb posi- tion. all remaining tx ttb registers (e.g., txttb-1 through txttb-15) must contain octets with a 0 in the msb position. 3. the framer ic will not verify the crc-7 value that is written into the rx ttb-0 register. it is up to the users system hardware and/or software to perform this verification. 6.3.3 the receive hdlc controller block the receive e3 hdlc controller block can be used to receive message-oriented signaling (mos) type data link messages from the remote terminal equip- ment. the mos types of hdlc message processing is dis- cussed in detail below. the message oriented signaling (e.g., lap-d) processing via the receive ds3 hdlc controller block the lapd receiver (within the receive e3 hdlc controller block) allows the user to receive pmdl messages from the remote terminal equipment, via rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00000000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 413 the inbound e3 frames. in this case, the inbound message bits will be carried by either the gc or the nr byte-fields within each e3 frame. the remote lapd transmitter will transmit a lapd message to the near-end receiver via either one of these bytes within each e3 frame. the lapd receiver will re- ceive and store the information portion of the re- ceived lapd frame into the receive lapd message buffer, which is located at addresses: 0xde through 0x135 within the on-chip ram. the lapd receiver has the following responsibilities. ? framing to the incoming lapd messages ? filtering out stuffed "0s" (within the information payload) ? storing the frame message into the receive lapd message buffer ? perform frame check sequence (fcs) verification ? provide status indicators for end of message (eom) flag sequence byte detected abort sequence detected message type c/r type the occurrence of fcs errors the lapd receiver's actions are facilitated via the fol- lowing two registers. ? rx e3 lapd control register ? rx e3 lapd status register operation of the lapd receiver the lapd receiver, once enabled, will begin search- ing for the boundaries of the incoming lapd mes- sage. the lapd message frame boundaries are de- lineated via the flag sequence octets (0x7e), as de- picted in figure 200. where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the 16 bit fcs is calculated using crc-16, x16 + x12 + x5 + 1 the local p (at the remote terminal), while assem- bling the lapd message frame, will insert an addi- tional byte at the beginning of the information (pay- load) field. this first byte of the information field indi- cates the type and size of the message being trans- ferred. the value of this information field and the corresponding message type/size follow: cl path identification = 0x38 (76 bytes) idle signal identification = 0x34 (76 bytes) test signal identification = 0x32 (76 bytes) itu-t path identification = 0x3f (82 bytes) enabling and configuring the lapd receiver before the lapd receiver can begin to receive and process incoming lapd message frames, the user must do two things. 1. the byte-field within each e3 frame which will be carrying the comprising octets of the lapd mes- sage frame must be specified and 2. the lapd receiver must be enabled. each of these steps are discussed in detail below. 1. specifying which byte-field, within each e3 frame, will be carrying the lapd message frame. the lapd receiver can receive the lapd message frame octets via either the gc-byte-field or the nr- byte-field, within each incoming e3 frame. the user makes this selection by writing the appropriate bit to f igure 200. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 414 bit 1 (dl from nr) within the rx e3 lapd control register, as depicted below. writing a 0 into this bit-field causes the lapd re- ceiver to read in the octets from the gc byte-field of each e3 frame and with these octets, reassembling the lapd message frame. writing a 1 into this bit- field causes the lapd receiver to receive the lapd message frame octets from the nr byte-field of each e3 frame. 2. enabling the lapd receiver the lapd receiver must be enabled before it can begin receiving and processing any lapd message frames. the lapd receiver can be enabled by writ- ing a 1 to bit 2 (rxlapd enable) of the rx e3 lapd control register, as indicated below. once the lapd receiver has been enabled, it will be- gin searching for the flag sequence octet (0x7e), in either the gc or the nr byte-fields within each in- coming e3 frame. when the lapd receiver finds the flag sequence byte, it will assert the flag present bit (bit 0) within the rx e3 lapd status register, as de- picted below. the receipt of the flag sequence octet can mean one of two things. 1. this flag sequence byte may be marking the beginning or end of an incoming lapd message frame. 2. the received flag sequence octet could be just one of many flag sequence octets that are trans- mitted via the e3 transport medium, during idle periods between the transmission of lapd mes- sage frames. the lapd receiver will negate the flag present bit as soon as it has received an octet that is something other than the flag sequence octet. once this hap- pens, the lapd receiver should be receiving either octet # 2 of the incoming lapd message, or an abort sequence (e.g., a string of seven or more consecutive 1s). if this next set of data is an rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used dl from nr rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro r/w r/w r/w rur 00000010 rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used dl from nr rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro r/w r/w r/w rur 00000110 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx abort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000001 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 415 abort sequence, then the lapd receiver will as- sert the rxabort bit-field (bit 6) within the rx e3 lapd status register, as depicted below. however, if this next octet is octet #2 of an incoming lapd message frame, then the lapd receiver is be- ginning to receive a lapd message frame. as the lapd receiver receives this lapd message frame, it is reading in the lapd message frame oc- tets, from either the gc or the nr byte-fields with- in each incoming e3 frame. secondly, it is reassem- bling these octets into a lapd message frame. once the lapd receiver has received the complete lapd message frame, then it will proceed to perform the following five (5) steps. 1. pmdl message extraction the lapd receiver will extract out the pmdl mes- sage, from the newly received lapd message frame. the lapd receiver will then write this pmdl mes- sage into the receive lapd message buffer within the framer ic. n ote : as the lapd receiver is extracting the pmdl mes- sage, from the newly received lapd message frame, the lapd receiver will also check the pmdl data for the occurrence of stuff bits (e.g., 0s that were inserted into the pmdl message by the remote lapd transmitter, in order to prevent this data from mimicking the flag sequence byte or an abort sequence), and remove them prior to writing the pmdl message into the receive lapd message buffer. specifically, the lapd receiver will search through the pmdl message data and will remove any 0 that immediately follows a string of 5 consecutive 1s. for more information on how the lapd transmitter inserted these stuff bits, please see section 5.2.3.1. 2. fcs (frame check sequence) word verification the lapd receiver will compute the crc-16 value of the header octets and the pmdl message octets, within this lapd message frame and will compare it with the value of the two octets, residing in the fcs word-field of this lapd message frame. if the fcs value of the newly received lapd message frame matches the locally-computed crc-16 value, then the lapd receiver will conclude that it has received this lapd message frame in an error-free manner. however, if the fcs value does not match the locally- computed crc-16 value, then the lapd receiver will conclude that this lapd message frame is erred. the lapd receiver will indicate the results of this fcs verification process by setting bit 2 (rxfcs er- ror) within the rx e3 lapd status register, to the ap- propriate value as tabulated below. if the lapd receiver detects an error in the fcs val- ue, then it will set the rxfcs error bit-field to 1. conversely, if the lapd receiver does not detect an error in the fcs value, the it will clear the rxfcs er- ror bit-field to 0. n ote : the lapd receiver will extract and write the pmdl message into the receive lapd message buffer indepen- dent of the results of fcs verification. hence, the user is urged to validate each pmdl message that is read in from the receive lapd message buffer, by first checking the state of this bit-field. 3. check and report the state of the c/r bit-field rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx abort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 01000000 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx abort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000100 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 416 after receiving the lapd message frame, the lapd receiver will check the state of the c/r bit-field, within octet # 2 of the lapd message frame header and will reflect this value in bit 3 (rx cr type) within the rx e3 lapd status register, as depicted below. when this bit-field is 0, it means that this lapd message frame is originating from a customer instal- lation. when this bit-field is 1, it means that this lapd message frame is originating from a network terminal. 4. identify the type of lapd message frame/pmdl message next, the lapd receiver will check the value of the first octet within the pmdl message field, of the lapd message frame. recall that from section _, that when operating the lapd transmitter, the user is required to write in a byte of a specific value into the first octet position within the transmit lapd message buffer. the value of this byte corresponds to the type of lapd message frame/pmdl message that is to be transmitted to the remote lapd receiver. this mes- sage-type identification octet is transported to the remote lapd receiver, along with the rest of the lapd frame. from this message type identification octet, the lapd receiver will know the type of size of the newly received pmdl message. the lapd re- ceiver will then reflect this information in bits 4 and 5 (rxlapdtype[1:0]) within the rx e3 lapd status register, as depicted below. table 86 presents the relationship between the con- tents of rxlapdtype[1:0] and the type of message received by the lapd receiver. n ote : prior to reading in the pmdl message from the receive lapd message buffer, the user is urged to read the state of the rxlapdtype[1:0] bit-fields in order to deter- mine the size of this message. 5. inform the local microprocessor/external cir- cuitry of the receipt of the new lapd message frame. rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx abort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00001000 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx abort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000000 t able 86: t he r elationship between the c ontents of r x lapdt ype [1:0] bit - fields and the pmdl m essage t ype /s ize r x lapdt ype [1:0] pmdl m essage t ype pmdl m essage s ize 00 test signal identification 76 bytes 01 idle signal identification 76 bytes 10 cl path identification 76 bytes 11 itu-t path identification 82 bytes XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 417 finally, after the lapd receiver has received and processed the newly received lapd message frame (per steps 1 through 4, as described above), it will in- form the local microprocessor that a lapd message frame has been received and is ready for user-sys- tem handling. the lapd receiver will inform the mi- croprocessor/microcontroller and the external circuit- ry by: ? generating a lapd message frame received interrupt to the microprocessor. the purpose of this interrupt is to let the microprocessor know that the receive lapd message buffer contains a new pmdl message that needs to be read and pro- cessed. when the lapd receiver generates this interrupt, it will set bit 0 (rxlapd interrupt status) within the rx e3 lapd control register to 1 as depicted below. ? setting bit 1 (end of message) within the rx e3 lapd status register, to 1 as depicted below. in summary, figure 201 presents a flow chart depict- ing how the lapd receiver functions. rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used dl from nr rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro r/w r/w r/w rur 00000001 rxe3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx abort rxlapdtype[1:0] rxcr ty p e rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000010 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 418 f igure 201. f low c hart depicting the f unctionality of the lapd r eceiver start indicate whether the lapd receiver should retrieve the lapd message frame octets from the nr or gc byte-field, within each incoming e3 frame. enable the lapd receiver the lapd receiver will begin searching for the flag sequence octet (0x7e) in the selected byte-field (e.g., nr or gc) of each incoming e3 frame. is flag sequence octet present? assert the flag present bit-field within the rx e3 lapd status register (address = 0x19). is non-flag sequence octet detected ? set the rxlapdtype[1:0] bit-fields to the appropriate value. continue to read in the lapd message frame octets is abort sequence detected? has the last byte of the lapd message frame been received? set the end of message bit-field within the rxe3 lapd status register (address = 0x19) unstuff the pmdl portion of the lapd message frame. goto figure 185 no a yes no yes no yes no yes XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 419 6.3.4 the receive overhead data output inter- face figure 203 presents a simple illustration of the re- ceive overhead data output interface block within the XRT72L50. the e3, itu-t g.832 frame consists of 537 bytes. of these bytes, 530 bytes are payload bits and the re- maining 7 bytes are overhead bytes. the XRT72L50 has been designed to handle and process both the payload type and overhead type bytes for each e3 frame. f igure 202. f low c hart depicting the f unctionality of the lapd r eceiver (c ontinued ) compute frame check sequence (fcs) value of incoming lapd message frame. compare locally-computed fcs value with that contained within the newly received lapd message frames. do the two fcs values match? fcs error detected assert the rx fcs error bit-field within the rx e3 lapd status register (address = 0x19). generate the receive lapd message frame interrupt. from figure 184 end a no yes f igure 203. a s imple i llustration of the r eceive o verhead o utput i nterface block receive overhead output interface block receive overhead output interface block from receive e3 framer block rxohframe rxoh rxohclk rxohenable ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 420 within the receive section of the XRT72L50, the re- ceive payload data output interface block has been designed to handle the payload bits. likewise, the receive overhead data output interface block has been designed to handle and process the overhead bits. the receive overhead data output interface block unconditionally outputs the contents of all overhead bits. the XRT72L50 does not offer the user a means to shut off this transmission of data. however, the receive overhead output interface block does pro- vide the user with the appropriate output signals for external data link layer equipment to sample and process these overhead bits, via the following two methods. ? method 1- using the rxohclk clock signal. ? method 2 - using the rxclk and rxohenable out- put signals. each of these methods are described below. 6.3.4.1 method 1 - using the rxohclk clock signal the receive overhead data output interface block consists of four (4) signals. of these four signals, the following three signals are to be used when sampling the e3 overhead bits via method 1. ? rxoh ? rxohclk ? rxohframe each of these signals are listed and described below in table 87. interfacing the receive overhead data output in- terface block to the terminal equipment (method 1) figure 204 illustrates how one should interface the receive overhead data output interface block to the terminal equipment when using method 1, to sample and process the overhead bits from the inbound e3 data stream. method 1 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound e3 data stream (via the receive overhead data output interface block) then it is expected to do the following: 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input signal) on the rising edge of the rxohclk (e.g., the e3_oh_clock_in) signal. 2. keep track of the number of rising clock edges that have occurred in the rxohclk (e.g., the e3_oh_clock_in) signal, since the last time the rxohframe signal was sampled high. by doing this, the terminal equipment will be able to keep track of which overhead byte is being output via the rxoh output pin. based upon this infor- mation, the terminal equipment will be able to derive some meaning from these overhead bits. f igure 204. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 1). terminal equipment xrt72l5x e3 framer e3_oh_in e3_oh_clock_in rx_start_of_frame rxoh rxohclk rxohframe XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 421 table 88 relates the number of rising clock edges (in the rxohclk signal, since the rxohframe signal was last sampled high) to the e3 overhead bit that is being output via the rxoh output pin. t able 87: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L50 will output the overhead bits, within the incoming e3 frames, via this pin. the receive overhead data output interface block will output a given overhead bit, upon the falling edge of rxohclk. hence, the external data link equipment should sample the data, at this pin, upon the rising edge of rxohclk. the XRT72L50 will always output the e3 overhead bits via this output pin. there are no exter- nal input pins or register bit settings available that will disable this output pin. rxohclk output receive overhead data output interface clock signal: the XRT72L50 will output the overhead bits (within the incoming e3 frames), via the rxoh output pin, upon the falling edge of this clock signal. as a consequence, the user's data link equipment should use the rising edge of this clock sig- nal to sample the data on both the rxoh and rxohframe output pins. this clock signal is always active. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L50 will drive this output pin "high" (for one period of the rxohclk signal), when- ever the first overhead bit within a given e3 frame is being driven onto the rxoh output pin. t able 88: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the XRT72L50 0 (clock edge is coincident with rxohframe being detected high) fa1 byte - bit 7 1 fa1 byte - bit 6 2 fa1 byte - bit 5 3 fa1 byte - bit 4 4 fa1 byte - bit 3 5 fa1 byte - bit 2 6 fa1 byte - bit 1 7 fa1 byte - bit 0 8 fa2 byte - bit 7 9 fa2 byte - bit 6 10 fa2 byte - bit 5 11 fa2 byte - bit 4 12 fa2 byte - bit 3 13 fa2 byte - bit 2 14 fa2 byte - bit 1 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 422 15 fa2 byte - bit 0 16 em byte - bit 7 17 em byte - bit 6 18 em byte - bit 5 19 em byte - bit 4 20 em byte - bit 3 21 em byte - bit 2 22 em byte - bit 1 23 em byte - bit 0 24 tr byte - bit 7 25 tr byte - bit 6 26 tr byte - bit 5 27 tr byte - bit 4 28 tr byte - bit 3 29 tr byte - bit 2 30 tr byte - bit 1 31 tr byte - bit 0 32 ma byte - bit 7 33 ma byte - bit 6 34 ma byte - bit 5 35 ma byte - bit 4 36 ma byte - bit 3 37 ma byte - bit 2 38 ma byte - bit 1 39 ma byte - bit 0 40 nr byte - bit 7 41 nr byte - bit 6 42 nr byte - bit 5 43 nr byte - bit 4 44 nr byte - bit 3 t able 88: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the XRT72L50 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 423 figure 205 presents the typical behavior of the re- ceive overhead data output interface block, when method 1 is being used to sample the incoming e3 overhead bits. 6.3.4.2 method 2 - using rxoutclk and the rxohenable signals 45 nr byte - bit 2 46 nr byte - bit 1 47 nr byte - bit 0 48 gc byte - bit 7 49 gc byte - bit 6 50 gc byte - bit 5 51 gc byte - bit 4 52 gc byte - bit 3 53 gc byte - bit 2 54 gc byte - bit 1 55 gc byte - bit 0 t able 88: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the XRT72L50 f igure 205. i llustration of the signals that are output via the r eceive o verhead o utput i nterface ( for m ethod 1). rxohclk rxohframe rxoh fa1, bit 7 fa1, bit 6 fa1, bit 5 fa1, bit 4 fa1, bit 3 terminal equipment should sample the rxohframe and rxoh signals here. recommended sampling edges ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 424 method 1 requires that the terminal equipment be able to handle an additional clock signal, rxohclk. however, there may be a situation in which the termi- nal equipment circuitry does not have the means to deal with this extra clock signal, in order to use the receive overhead data output interface. method 2 involves the use of the following signals. ? rxoh ? rxoutclk ? rxohenable ? rxohframe each of these signals are listed and described in table 89. interfacing the receive overhead data output in- terface block to the terminal equipment (method 2) figure 206 illustrates how one should interface the receive overhead data output interface block to the terminal equipment, when using method 2 to sample and process the overhead bits from the inbound e3 data stream. t able 89: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface b lock (m ethod 2) s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L50 will output the overhead bits, within the incoming e3 frames, via this pin. the receive overhead output interface will pulse the rxohenable output pin (for one rxout- clk period) at approximately the middle of the rxoh bit period. the user is advised to design the terminal equipment to latch the contents of the rxoh output pin, whenever the rxohen- able output pin is sampled high on the falling edge of rxoutclk. rxohenable output receive overhead data output enable - output pin: the XRT72L50 will assert this output signal for one rxoutclk period when it is safe for the ter- minal equipment to sample the data on the rxoh output pin. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L50 will drive this output pin high (for one period of the rxoh signal), whenever the first overhead bit, within a given e3 frame is being driven onto the rxoh output pin. rxoutclk output receive section output clock signal: this clock signal is derived from the rxlineclk signal (from the liu) for loop-timing applica- tions, and the txinclk signal (from a local oscillator) for local-timing applications. for e3 appli- cations, this clock signal will operate at 34.368mhz. the user is advised to design the terminal equipment to latch the contents of the rxoh pin, anytime the rxohenable output signal is sampled high on the falling edge of this clock sig- nal. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 425 method 2 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound e3 data stream (via the receive overhead data output interface), then it is expected to do the following. 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input) on the falling edge of the rxoutclk clock signal, whenever the rxo- henable output signal is also sampled high. 2. keep track of the number of times that the rxo- henable signal has been sampled high since the last time the rxohframe was also sampled high. by doing this, the terminal equipment will be able to keep track of which overhead bit is being output via the rxoh output pin. based upon this information, the terminal equipment will be able to derive some meaning from these overhead bits. 3. table 90 relates the number of rxohenable out- put pulses (that have occurred since both the rxohframe and the rxohenable pins were both sampled high) to the e3 overhead bit that is being output via the rxoh output pin. f igure 206. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 2). terminal equipment xrt72l5x e3 framer e3_oh_enable_in e3_oh_in rx_start_of_frame rxohenable rxoh rxohframe rxoutclk e3_clk_in t able 90: t he r elationship between the n umber of r x ohe nable output pulses ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the XRT72L50 0 (clock edge is coincident with rxohframe being detected high) fa1 byte - bit 7 1 fa1 byte - bit 6 2 fa1 byte - bit 5 3 fa1 byte - bit 4 4 fa1 byte - bit 3 5 fa1 byte - bit 2 6 fa1 byte - bit 1 7 fa1 byte - bit 0 8 fa2 byte - bit 7 9 fa2 byte - bit 6 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 426 10 fa2 byte - bit 5 11 fa2 byte - bit 4 12 fa2 byte - bit 3 13 fa2 byte - bit 2 14 fa2 byte - bit 1 15 fa2 byte - bit 0 16 em byte - bit 7 17 em byte - bit 6 18 em byte - bit 5 19 em byte - bit 4 20 em byte - bit 3 21 em byte - bit 2 22 em byte - bit 1 23 em byte - bit 0 24 tr byte - bit 7 25 tr byte - bit 6 26 tr byte - bit 5 27 tr byte - bit 4 28 tr byte - bit 3 29 tr byte - bit 2 30 tr byte - bit 1 31 tr byte - bit 0 32 ma byte - bit 7 33 ma byte - bit 6 34 ma byte - bit 5 35 ma byte - bit 4 36 ma byte - bit 3 37 ma byte - bit 2 38 ma byte - bit 1 39 ma byte - bit 0 40 nr byte - bit 7 t able 90: t he r elationship between the n umber of r x ohe nable output pulses ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the XRT72L50 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 427 figure 207 presents the typical behavior of the re- ceive overhead data output interface block, when method 2 is being used to sample the incoming e3 overhead bits. 41 nr byte - bit 6 42 nr byte - bit 5 43 nr byte - bit 4 44 nr byte - bit 3 45 nr byte - bit 2 46 nr byte - bit 1 47 nr byte - bit 0 48 gc byte - bit 7 49 gc byte - bit 6 50 gc byte - bit 5 51 gc byte - bit 4 52 gc byte - bit 3 53 gc byte - bit 2 54 gc byte - bit 1 55 gc byte - bit 0 t able 90: t he r elationship between the n umber of r x ohe nable output pulses ( since r x ohf rame was last sampled "h igh ") to the e3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the XRT72L50 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 428 6.3.5 the receive payload data output inter- face figure 208presents a simple illustration of the re- ceive payload data output interface block. f igure 207. i llustration of the signals that are output via the r eceive o verhead d ata o utput i nter - face block ( for m ethod 2). rxoutclk rxohenable rxohframe rxoh payload bit 4239 fa1, bit 7 fa1, bit 6 fa1, bit 5 fa1, bit 4 recommended sampling edges XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 429 each of the output pins of the receive payload data output interface block are listed in table 91 and de- scribed below. the exact role that each of these out- put pins assume, for a variety of operating scenarios are described throughout this section. f igure 208. a s imple illustration of the r eceive p ayload d ata o utput i nterface block receive payload data output interface receive payload data output interface rxohind rxser rxnib[3:0] rxclk rxoutclk rxframe from receive e3 framer block ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 430 t able 91: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i nterface block s ignal n ame t ype d escription rxser output receive serial payload data output pin: if the user opts to operate the XRT72L50 in the serial mode, then the chip will output the pay- load data, of the incoming e3 frames, via this pin. the XRT72L50 will output this data upon the rising edge of rxclk. the user is advised to design the terminal equipment such that it will sample this data on the falling edge of rxclk. n ote : this signal is only active if the nibint input pin is pulled "low". rxnib[3:0] output receive nibble-parallel payload data output pins: if the user opts to operate the XRT72L50 in the nibble-parallel mode, then the chip will output the payload data, of the incoming e3 frames, via these pins. the XRT72L50 will output data via these pins, upon the falling edge of the rxclk output pin. the user is advised to design the terminal equipment such that it will sample this data upon the rising edge of rxclk. n ote : these pins are only active if the nibint input pin is pulled "high". rxclk output receive payload data output clock pin: the exact behavior of this signal depends upon whether the XRT72L50 is operating in the serial or in the nibble-parallel-mode. serial mode operation in the serial mode, this signal is a 34.368mhz clock output signal. the receive payload data output interface will update the data via the rxser output pin, upon the rising edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the rxser pin, upon the falling edge of this clock signal. nibble-parallel mode operation in this nibble-parallel mode, the XRT72L50 will derive this clock signal, from the rxlineclk signal. the XRT72L50 will pulse this clock 1060 times for each inbound e3 frame. the receive payload data output interface will update the data, on the rxnib[3:0] output pins upon the falling edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the rxnib[3:0] output pins, upon the rising edge of this clock signal rxohind output receive overhead bit indicator output: this output pin will pulse "high" whenever the receive payload data output interface outputs an overhead bit via the rxser output pin. the purpose of this output pin is to alert the terminal equipment that the current bit, (which is now residing on the rxser output pin), is an overhead bit and should not be processed by the terminal equipment. the XRT72L50 will update this signal, upon the rising edge of rxohind. the user is advised to design (or configure) the terminal equipment to sample this signal (along with the data on the rxser output pin) on the falling edge of the rxclk signal. n ote : for e3 applications, this output pin is only active if the XRT72L50 is operating in the serial mode. this output pin will be "low" if the device is operating in the nibble-parallel mode. rxframe output receive start of frame output indicator: the exact behavior of this pin, depends upon whether the XRT72L50 has been configured to operate in the serial mode or the nibble-parallel mode. serial mode operation: the receive section of the XRT72L50 will pulse this output pin "high" (for one bit period) when the receive payload data output interface block is driving the very first bit (or nibble) of a given e3 frame, onto the rxser output pin. nibble-parallel mode operation: the receive section of the XRT72L50 will pulse this output pin "high" for one nibble period, when the receive payload data output interface is driving the very first nibble of a given e3 frame, onto the rxnib[3:0] output pins. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 431 operation of the receive payload data output in- terface block the receive payload data output interface permits the user to read out the payload data of inbound e3 frames, via either of the following modes. ? serial mode ? nibble-parallel mode each of these modes are described in detail, below. 6.3.5.1 serial mode operation behavior of the XRT72L50 if the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will behave as follows. payload data output the XRT72L50 will output the payload data, of the in- coming e3 frames, upon the rising edge of rxclk. delineation of inbound ds3 frames the XRT72L50 will pulse the rxframe output pin "high" for one bit-period, coincident with it driving the first bit within a given e3 frame, via the rxser output pin. interfacing the XRT72L50 to the receive terminal equipment figure 209 presents a simple illustration as how the user should interface the XRT72L50 to that terminal equipment which processes receive direction pay- load data. required operation of the terminal equipment the XRT72L50 will update the data on the rxser out- put pin, upon the rising edge of rxclk. hence, the terminal equipment should sample the data on the rxser output pin (or the e3_data_in pin at the termi- nal equipment) upon the rising edge of rxclk. as the terminal equipment samples rxser with each rising edge of rxclk it should also be sampling the follow- ing signals. ? rxframe ? rxohind the need for sampling rxframe the XRT72L50 will pulse the rxframe output pin "high" coincident with it driving the very first bit of a given e3 frame onto the rxser output pin. if knowl- edge of the e3 frame boundaries is important for the operation of the terminal equipment, then this is a very important signal for it to sample. the need for sampling rxohind the XRT72L50 will indicate that it is currently driving an overhead bit onto the rxser output pin, by pulsing the rxohind output pin "high". if the terminal equip- ment samples this signal "high", then it should know that the bit, that it is currently sampling via the rxser pin is an overhead bit and should not be processed. the behavior of the signals between the receive payload data output interface block and the ter- minal equipment the behavior of the signals between the XRT72L50 and the terminal equipment for e3 serial mode op- eration is illustrated in figure 210. f igure 209. i llustration of the r eceive p ayload d ata o utput i nterface b lock ( of the XRT72L50 ds3/e3 f ramer ic) being interfaced to the r eceive t erminal e quipment (s erial m ode o peration ) terminal equipment (receive payload section) xrt72l5x e3 framer e3_data_in rx_e3_clock_in rx_start_of_frame rxclk rxframe rxohind 34.368 mhz clock signal rxser rx_e3_oh_ind rxlineclk 34.368 mhz clock source ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 432 6.3.5.2 nibble-parallel mode operationbehav- ior of the XRT72L50 if the XRT72L50 has been configured to operate in the nibble-parallel mode, then the XRT72L50 will be- have as follows. payload data output the XRT72L50 will output the payload data of the in- coming e3 frames, via the rxnib[3:0] output pins, up- on the rising edge of rxclk. n otes : 1. in this case, rxclk will function as the nibble clock signal between the XRT72L50 the terminal equip- ment. the XRT72L50 will pulse the rxclk output signal "high" 1060 times, for each inbound e3 frame. 2. unlike serial mode operation, the duty cycle of rxclk, in nibble-parallel mode operation is approx- imately 25%. delineation of inbound ds3 frames the XRT72L50 will pulse the rxframe output pin "high" for one nibble-period coincident with it driving the very first nibble, within a given inbound e3 frame, via the rxnib[3:0] output pins. interfacing the XRT72L50 the terminal equip- ment. figure 211 presents a simple illustration as how the user should interface the XRT72L50 to that terminal equipment which processes receive direction pay- load data. f igure 210. a n i llustration of the behavior of the signals between the r eceive p ayload d ata o ut - put i nterface block of the XRT72L50 and the t erminal e quipment terminal equipment signals e3_clock_in e3_data_in rx_start_of_frame e3_overhead_ind xrt72l5x receive payload data i/f signals rxclk rxser rxframe rxoh_ind payload[1522] payload[1523] fas, bit 9 fas, bit 8 payload[1532] payload[1533] fas, bit 9 fas, bit 8 note: fas, a and n-bits will not be processed by the transmit payload data input interface. e3 frame number n e3 frame number n + 1 note: rxframe pulses high to denote e3 frame boundary. note: rxoh_ind pulses high to denote overhead data (e.g., the fas, a and n bits). XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 433 required operation of the terminal equipment the XRT72L50 will update the data on the rxnib[3:0] line, upon the rising edge of rxclk. hence, the ter- minal equipment should sample the data on the rx- nib[3:0] output pins (or the e3_data_in[3:0] input pins at the terminal equipment) upon the rising edge of rxclk. as the terminal equipment samples rxser with each rising edge of rxclk it should also be sam- pling the rxframe signal. the need for sampling rxframe the XRT72L50 will pulse the rxframe output pin "high" coincident with it driving the very first nibble of a given e3 frame, onto the rxnib[3:0] output pins. if knowledge of the e3 frame boundaries is important for the operation of the terminal equipment, then this is a very important signal for it to sample. the behavior of the signals between the receive payload data output interface block and the ter- minal equipment the behavior of the signals between the XRT72L50 and the terminal equipment for e3 nibble-mode op- eration is illustrated in figure 212. f igure 211. i llustration of the XRT72L50 ds3/e3 f ramer ic being interfaced to the r eceive s ection of the t erminal e quipment (n ibble -m ode o peration ) terminal equipment (receive payload section) xrt72l5x e3 framer e3_data_in[3:0] rx_e3_clock_in rx_start_of_frame rxclk rxframe 8.592 mhz clock signal rxnib[3:0] rxlineclk 34.368 mhz clock source rxoh_ind rx_e3_oh_ind ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 434 6.3.6 receive section interrupt processing the receive section of the XRT72L50 can generate an interrupt to the microcontroller/microprocessor for the following reasons. ? change in receive los condition ? change in receive oof condition ? change in receive lof condition ? change in receive ais condition ? change in receive ferf condition ? change of framing alignment ? change in receive trail trace buffer message ? detection of febe (far-end block error) event ? detection of bip-8 error ? detection of framing byte error ? detection of payload type mismatch ? reception of a new lapd message 6.3.6.1 enabling receive section interrupts as mentioned in section 1.6, the interrupt structure within the XRT72L50 contains two hierarchical levels. ? block level ? source level the block level the enable state of the block level for the receive section interrupts dictates whether or not interrupts (if enabled at the source level), are actually enabled. the user can enable or disable these receive sec- tion interrupts, at the block level by writing the appro- priate data into bit 7 (rx ds3/e3 interrupt enable) within the block interrupt enable register (address = 0x04), as illustrated below. f igure 212. i llustration of the signals that are output via the r eceive o verhead d ata o utput i nter - face block ( for m ethod 2). xrt72l5x receive payload data i/f signals e3 frame number n e3 frame number n + 1 note: rxframe pulses high to denote e3 frame boundary. terminal equipment signals rxoutclk rx_start_of_frame rx_e3_clock_in e3_data_in[3:0] overhead nibble [0] overhead nibble [1] rxoutclk rxframe rxclk rxnib[3:0] overhead nibble [0] overhead nibble [1] recommended sampling edge of terminal equipment rx_e3_oh_ind rxoh_ind XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 435 setting this bit-field to 1 enables the receive sec- tion at the block level) for interrupt generation. con- versely, setting this bit-field to 0 disables the re- ceive section for interrupt generation. 6.3.6.2 enabling/disabling and servicing inter- rupts as mentioned earlier, the receive section of the XRT72L50 framer ic contains numerous interrupts. the enabling/disabling and servicing of each of these interrupts is described below. 6.3.6.2.1 the change in receive los condi- tion interrupt if the change in receive los condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares an los (loss of signal) condition, and 2. when the XRT72L50 framer ic clears the los condition. conditions causing the XRT72L50 framer ic to declare an los condition. ? if the xrt7300 liu ic declares an los condition, and drives the rlos input pin (of the XRT72L50 framer ic) high. ? if the XRT72L50 framer ic detects 32 consecutive 0, via the rxpos and rxneg input pins. conditions causing the XRT72L50 framer ic to clear the los condition. ? if the xrt7300 liu ic clears the los condition and drives the rlos input pin (of the XRT72L50 framer ic) low. ? if the XRT72L50 framer ic detects a string of 32 consecutive bits (via the rxpos and rxneg input pins) that does not contain a string of 4 consecu- tive 0s. enabling and disabling the change in receive los condition interrupt the user can enable or disable the change in re- ceive los condition interrupt, by writing the appror- priate value into bit 1 (los interrupt enable), within the rxe3 interrupt enable register - 1, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive los condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 1 (los interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used txds3/e3 interrupt enable one-second interrupt enable r/wrororororor/wr/w x0000000 rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000000x0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 436 whenever the users system encounters the change in receive los condition interrupt, then it should do the following. 1. it should determine the current state of the los condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the los defect. hence, the user can determine the current state of the los defect by reading the state of bit 4 (rxlos) within the rx e3 configuration and status regis- ter - 2, as illustrated below. if the los state is true 1. it should transmit a ferf (far-end-receive fail- ure) indicator to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-los feature. if the los state is false 1. it should cease transmitting the ferf indication to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-los feature. 6.3.6.2.2 the change in receive oof condi- tion interrupt if the change in receive oof condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares an oof (out of frame) condition, and 2. when the XRT72L50 framer ic clears the oof condition. conditions causing the XRT72L50 framer ic to declare an oof condition. ? if the receive e3 framer block (within the XRT72L50 framer ic) detects framing byte errors, within four consecutive incoming e3 frames. conditions causing the XRT72L50 framer ic to clear the oof condition. ? if the receive e3 framer block (within the XRT72L50 framer ic) transitions from the fa1, fa2 octet verification state to the in-frame state (see figure 175). ? if the receive e3 framer block transitions from the oof condition state to the in-frame state (see fig- ure 175). enabling and disabling the change in receive oof condition interrupt the user can enable or disable the change in re- ceive oof condition interrupt, by writing the appro- priate value into bit 3 (oof interrupt enable), within rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000010 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo xxxxxxxx XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 437 the rxe3 interrupt enable register - 1, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive oof condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 3 (oof interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. whenever the users system encounters the change in receive oof condition interrupt, then it should do the following. 1. it should determine the current state of the oof condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the oof defect. hence, the user can determine the current state of the los defect by reading the state of bit 5 (rxoof) within the rx e3 configuration and status regis- ter - 2, as illustrated below. if the oof state is true 1. it should transmit a ferf (far-end-receive fail- ure) indicator to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-oof feature. if the oof state is false 1. it should cease transmitting the ferf indication to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-oof feature. 6.3.6.2.3 the change in receive lof condi- tion interrupt if the change in receive lof condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000000x0 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000010 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo xxxxxxxx ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 438 1. when the XRT72L50 framer ic declares an lof (out of frame) condition, and 2. when the XRT72L50 framer ic clears the lof condition. conditions causing the XRT72L50 framer ic to declare an lof condition. ? if the receive e3 framer block (within the XRT72L50 framer ic) detects framing byte errors, within four consecutive incoming e3 frames and is not able to transition back into the in-frame state within 1 or 3ms. conditions causing the XRT72L50 framer ic to clear the lof condition. ? if the receive e3 framer block transitions from the oof condition state to the lof condition state (see figure 175). ? if the receive e3 framer block transitions back into the in-frame state. enabling and disabling the change in receive lof condition interrupt the user can enable or disable the change in re- ceive lof condition interrupt, by writing the appropri- ate value into bit 3 (lof interrupt enable), within the rxe3 interrupt enable register - 1, as indicated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive lof condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 6 (lof interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. 6.3.6.2.4 the change of framing alignment (cofa) interrupt if the change of framing alignment interrupt is en- abled then the XRT72L50 framer ic will generate an interrupt any time the receive e3 framer block de- tects an abrupt change of framing alignment. n ote : this interrupt is typically accompanied with the change in receive oof condition interrupt as well. conditions causing the XRT72L50 framer ic to generate this interrupt. if the XRT72L50 framer detects receives at least four consecutive e3 frames, within its framing alignment bytes in error, then the XRT72L50 framer ic will de- clare an oof condition. however, while the XRT72L50 framer ic is operating in the oof condi- tion, it will still rely on the old framing alignment for e3 payload data extraction, etc. however, if the receive e3 framer had to change alignment, in order to re-acquire frame synchroniza- tion, then this interrupt will occur. enabling and disabling the change of framing alignment interrupt the user can enable or disable the change of fram- ing alignment interrupt by writing the appropriate val- ue into bit 4 (cofa interrupt rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000000x0 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo xxxxxxxx XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 439 writing a 1 into this bit-field enables the change of framing alignment interrupt. conversely, writing a 0 into this bit-field disables the change of framing alignment interrupt. servicing the change of framing alignment interrupt whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ) by driving it low. ? it will set bit 4 (cofa interrupt status), within the rx e3 interrupt status register -2, to 1, as indi- cated below. 6.3.6.2.5 the change in receive ais condition interrupt if the change in receive ais condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares an ais (loss of signal) condition, and 2. when the XRT72L50 framer ic clears the ais condition. conditions causing the XRT72L50 framer ic to declare an ais condition. ? if the XRT72L50 framer ic detects 7 or less 0 within 2 consecutive e3 frames. conditions causing the XRT72L50 framer ic to clear the ais condition. ? if the XRT72L50 framer ic detects 2 consecutive e3 frames that each contain 8 or more 0s. enabling and disabling the change in receive ais condition interrupt the user can enable or disable the change in re- ceive los condition interrupt, by writing the appro- priate value into bit 0 (ais interrupt enable), within the rxe3 interrupt enable register - 1, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000x0000 rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00010000 rxe3 interrupt enable register - 1 (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt enable oof interrupt enable lof interrupt enable los interrupt enable ais interrupt enable ro ro ro r/w r/w r/w r/w r/w 000000x0 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 440 servicing the change in receive ais condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 0 (ais interrupt status), within the rx e3 interrupt status register - 1 to 1, as indicated below. whenever the users system encounters the change in receive ais condition interrupt, then it should do the following. 1. it should determine the current state of the ais condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the ais defect. hence, the user can determine the current state of the ais defect by reading the state of bit 4 (rxais) within the rx e3 configuration and status register - 2, as illustrated below. if the ais condition is true 1. it should begin transmitting the ferf indication to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-ais feature. if the ais condition is false 2. it should cease transmitting the ferf indication to the remote terminal equipment. the XRT72L50 framer ic automatically supports this action via the ferf-upon-ais feature. 6.3.6.2.6 the change in trail trace buffer mes- sage interrupt if the change in trail trace buffer message interrupt has been enabled, then the XRT72L50 framer ic will generate an interrupt any time the receive e3 framer block receives a different trail trace buffer message, then it has previously read in. enabling and disabling the change in trail trace buffer message interrupt. the user can enable or disable the change in trail trace buffer message interrupt by writing the appro- priate value into bit 6 (ttb change interrupt enable) within the rx e3 interrupt enable register - 2, as indi- cated below. rxe3 interrupt status register - 1 (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used cofa interrupt status oof interrupt status lof interrupt status los interrupt status ais interrupt status ro ro ro rur rur rur rur rur 00000010 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo xxxxxxxx rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 0000x000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 441 writing a 1 into this bit-field enables the change in trail trace buffer message interrupt. conversely, writing a 0 into this bit-field disables the change in trail trace buffer message interrupt. servicing the change in trail trace buffer mes- sage interrupt whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ) by driving it low. ? it will set bit 6 (ttb change interrupt status), within the rx e3 interrupt status register - 2, as indicated below. ? it will write the contents of this newly received trail trace buffer message, into the rxttb-0 (located at 0x1c) through rxttb-15 (located at 0x2b) regis- ters. whenever the terminal equipment encounters the change in trail trace buffer message interrupt, then it should read out the contents of the 16 rxttb regis- ters. 6.3.6.2.7 the change in receive ferf condi- tion interrupt if the change in receive ferf condition interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L50 framer ic declares a ferf (far-end receive failure) condition, and 2. when the XRT72L50 framer ic clears the ferf condition. conditions causing the XRT72L50 framer ic to declare an ferf condition. ? if the XRT72L50 framer ic begins receiving e3 frames which have the ferf bit (within the ma byte, set to 1). conditions causing the XRT72L50 framer ic to clear the ais condition. ? if the XRT72L50 framer ic begins receiving e3 frames that do not have the ferf bit set to 1. enabling and disabling the change in receive ais condition interrupt the user can enable or disable the change in re- ceive ferf condition interrupt, by writing the appro- priate value into bit 3 (ferf interrupt enable), within the rxe3 interrupt enable register - 2, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change in receive ferf condition interrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int ), by driving it low.it will set bit 3 (ferf interrupt rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 01000000 rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 0000x000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 442 status), within the rx e3 interrupt status register - 2 to 1, as indicated below whenever the users system encounters the change in receive ferf condition interrupt, then it should do the following. 1. it should determine the current state of the ferf condition. recall, that this interrupt can be gen- erated, whenever the XRT72L50 framer ic declares or clears the ferf defect. hence, the user can determine the current state of the los defect by reading the state of bit 0 (rxferf) within the rx e3 configuration and status regis- ter - 2, as illustrated below. 6.3.6.2.8 the detection of febe (far-end- block error) event interrupt if the detection of febe event interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt, anytime the receive e3 framer block has re- ceived an e3 frame with the febe bit-field (within the ma byte) set to 1. enabling and disabling the detection of febe event interrupt the user can enable or disable the detection of febe event interrupt by writing the appropriate value into bit 4 (febe interrupt enable) within the rx e3 in- terrupt enable register - 2, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of the febe event inter- rupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do the following. ? it will assert the interrupt request output pin (int ), by driving it high.it will set the bit 4 (febe inter- rupt status), within the rxe3 interrupt status reg- ister - 2 as indicated below. rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00001000 rxe3 configuration & status register 2 (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx lof algo rxlof rxoof rxlos rxais rxpld unstab rx tmark rxferf r/wrororororororo xxxxxxxx rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 000xx000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 443 whenever the terminal equipment encounters the detection of febe event interrupt, it should do the following. ? it should read the contents of the pmon febe event count registers (located at addresses 0x56 and 0x57) in order to determine the number of febe events that have been received by the XRT72L50 framer ic. 6.3.6.2.9 the detection of bip-8 error interrupt if the detection of bip-8 error interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt, anytime the receive e3 framer block has de- tected an error in the em (error monitoring) byte, within an incoming e3 frame. enabling and disabling the detection of febe event interrupt the user can enable or disable the detection of bip-8 error interrupt by writing the appropriate value into bit 2 (bip-8 interrupt enable) within the rx e3 inter- rupt enable register - 2, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of the bip-8 error inter- rupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do the following. ? it will assert the interrupt request output pin (int ), by driving it high. ? it will set the bit 2 (bip-8 interrupt status), within the rxe3 interrupt status register - 2 as indicated below. whenever the terminal equipment encounters the detection of bip-8 error interrupt, it should do the fol- lowing. rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00010000 rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 000xx000 rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00000100 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 444 ? it should read the contents of the pmon parity error event count registers (located at addresses 0x54 and 0x55) in order to determine the number of bip-8 errors that have been received by the XRT72L50 framer ic. 6.3.6.2.10 the detection of framing byte error interrupt if the detection of framing byte error interrupt is en- abled, then the XRT72L50 framer ic will generate an interrupt, anytime the receive e3 framer block has received an e3 frame with an incorrect framing byte (e.g., fa1 or fa2) value. enabling and disabling the detection of febe event interrupt the user can enable or disable the detection of framing byte error interrupt by writing the appropri- ate value into bit 1 (framing byte error interrupt en- able) within the rx e3 interrupt enable register - 2, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of framing byte error in- terrupt whenever the XRT72L50 framer ic detects this in- terrupt, it will do the following. ? it will assert the interrupt request output pin (int ), by driving it high. ? it will set the bit 4 (framing byte error interrupt sta- tus), within the rxe3 interrupt status register - 2 as indicated below. whenever the terminal equipment encounters the detection of framing byte error interrupt, it should do the following. ? it should read the contents of the pmon framing bit/byte error count registers (located at addresses 0x52 and 0x53) in order to determine the number of framing byte errors that have been received by the XRT72L50 framer ic. 6.3.6.2.11 the detection of payload type mis- match interrupt if the detection of payload type mismatch interrupt is enabled, then the XRT72L50 framer ic will generate an interrupt, anytime the receive e3 framer block re- ceives a ma byte (within an incoming e3 frame) that contents a payload type value that is different from the expected payload type value. conditions causing this interrupt to be generated. during system configuration, the user is expected to specify the payload type value that is expected of the receive e3 framer to receive (within each e3 frame), by writing this value into the rxpldexp[2:0] bit-fields within the rx e3 configuration & status register - 1, as indicated below. as long as the receive e3 framer block receives e3 frames that contains this payload type value, no in- terrupt will be generated. however, the instant that it receives an e3 frame, that contains a different pay- rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 000xx000 rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00010000 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 445 load type value, then the XRT72L50 framer ic will generate this interrupt. enabling and disabling the detection of payload type mismatch interrupt. the user can enable or disable the detection of pay- load type mismatch interrupt by writing the appropri- ate data into bit 0 (rxpld mis interrupt enable), within the rx e3 interrupt enable register - 2, as indicated below. setting this bit-field to 1 enables the detection of payload type mismatch interrupt. conversely, setting this bit-field to 0 disables the detection of payload type mismatch interrupt. servicing the detection of payload type mis- match interrupt whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ) by driving it low. ? it will set bit 0 (rxpld mis interrupt status), within the rx e3 interrupt enable register -2 to 1, as indicated below. 6.3.6.2.12 the receive lapd message interrupt if the receive lapd message interrupt is enabled, then the XRT72L50 framer ic will generate an inter- rupt anytime the receive hdlc controller block has received a new lapd message frame from the re- mote terminal equipment, and has stored the con- tents of this message into the receive lapd mes- sage buffer. enabling/disabling the receive lapd message interrupt the user can enable or disable the receive lapd message interrupt by writing the appropriate data into bit 1 (rxlapd interrupt enable) within the rx e3 lapd control register, as indicated below. rxe3 configuration & status register 1 (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxpldtype[2:0] rxferf algo rxtmark algo rxpldexp[2:0] ro ro ro ro ro r/w r/w r/w 00000000 rxe3 interrupt enable register - 2 (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt enable not used febe interrupt enable ferf interrupt enable bip-8 error interrupt enable framing byte error interrupt enable rxpld mis interrupt enable ro r/w ro r/w r/w r/w r/w r/w 000xx00x rxe3 interrupt status register - 2 (address = 0x15) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ttb change interrupt status not used febe interrupt status ferf interrupt status bip-8 error interrupt status framing byte error interrupt status rxpld mis interrupt status ro rur ro rur rur rur rur rur 00010000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 446 writing a 1 into this bit-field enables the receive lapd message interrupt. conversely, writing a 0 into this bit-field disables the receive lapd message interrupt. servicing the receive lapd message interrupt whenever the XRT72L50 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int ), by driving it low. ? it will set bit 0 (rxlapd interrupt status), within the rx e3 lapd control register to 1, as indicated below. ? it will write the contents of the newly received lapd message into the receive lapd message buffer (located at 0xde through 0x135). whenever the terminal equipment encounters the receive lapd message interrupt, then it should read out the contents of the receive lapd message buff- er, and respond accordingly. rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used dl from nr rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro r/w r/w r/w rur 0000000x rxe3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used dl from nr rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro r/w r/w r/w rur 00000011 XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 447 7.0 diagnostic operation of the XRT72L50 framer ic the XRT72L50 ds3/e3 framer ic permits the user to command it to operate in the framer local loop-back mode. when the user does this than the data will be as follows. 1. data will enter the XRT72L50 framer ic via both the transmit payload data input interface and the transmit overhead data input interface blocks. 2. this data will be processed through the transmit ds3/e3 framer block and the transmit ds3/e3 liu interface block. 3. this transmit output data will be internally looped-back into the receive path via the receive liu interface block. 4. this data will now be processed through the receive ds3/e3 framer block and will ultimately arrive at both the receive payload data output interface and receive overhead data output interface blocks, where this data will be output to the terminal equipment. the framer local loop-back path is also illustrated below in figure 213 . the user can configure the XRT72L50 into the fram- er local-loop-back mode by writing a 1 into bit-field f igure 213. i llustration of the f ramer l ocal l oop - back path , within the XRT72L50 ds3/e3 f ramer ic receive liu interface block receive ds3/e3 framer block receive payload data output interface block microprocessor interface moto d[7:0] a[8:0] intb* csb* rdb_ds wrb_rw rdy_dtck reset* ale_as rxser rxnib[3:0] rxoutclk rxpos rxneg rxlineclk tx lapd buffer/ controller rx lapd buffer/ controller receive overhead output interface block rxnibclk rxframe transmit payload data input interface block transmit ds3/e3 framer block transmit liu interface block txser txnib[3:0] txinclk txpos txneg txlineclk transmit overhead input interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe rxohframe rxoh rxohclk rxohenable framer local loop-back path ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 448 7 (local loop-back) within the framer operating mode register, as illustrated below. n otes : 1. when the XRT72L50 ds3/e3 framer ic is operat- ing in the framer local-loop-back mode, no data will be output via the txpos and txneg output pins. 2. the XRT72L50 ds3/e3 framer ic cannot be con- figured to operate in the framer local loop-back mode, if it is configured to operate in modes 1 or mode 4 (loop-timing modes). the user must con- figure the XRT72L50 framer to operate in one of the local-timing modes. framer operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 local loopback ds3/e3* internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 1xx0x xxx XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 449 8.0 high speed hdlc controller mode of operation each channel, within the XRT72L50 device can be configured to operate in the high-speed hdlc con- troller mode. whenever a given channel is configured to operate in this mode then the following will happen. 1. the transmit section of the channel will be con- figured to accept outbound data (from the users terminal equipment) via an 8-bit wide input inter- face labeled txhdlcdat_n[7:0]. the transmit section of the channel will then encapsulate all data, that it receives via txhdlcdat_n[7:0]. 2. the transmit section of the channel will then encapsulate all data, that it receives via the txhdlcdat_n[7:0] interface, into hdlc frames. these hdlc frames are variable-length packets and are transported to the remote terminal equip- ment via the outbound ds3 or e3 payload data bits. 3. as the transmit section accepts and processes data from the users terminal equipment, then it will perform all of the necessary 0 stuffing into the outbound hdlc frame, in order to prevent the user-supplied data from mimicking either the flag sequence octet (0x7e) or the abort sequence. 4. the transmit section can also be configured to compute and append either a 16-bit or 32-bit crc value to the end of this 0 stuffed users data, as a trailer. 5. whenever the transmit section has no user data to send to the remote terminal equipment (via hdlc frames) then it will transmit a continuous stream of flag sequence octets (0x7e) via the ds3 or e3 payload bits. 6. the receive section of the channel will be con- figured to receive and extract out these hdlc frames via the inbound ds3/e3 data stream. the receive section will then output the contents of these received hdlc frames in a byte-wide man- ner via the rxhdlcdat_n[7:0] output pins. 7. if the receive section of the channel is only receiving a stream of flag sequences (0x7e) then it will terminate this data stream and will not out- put any data via the rxhdlcdat_n[7:0] output pins. 8. as the receive section of the channel receives these hdlc frames, it will also do the following. ? compute and verify the 16-bit or 32-bit crc value (which has been appended to the hdlc frame, as a trailer). ? perform the necessary 0 un-stuffing in order to restore the original content of the user-supplied data. 8.1 c onfiguring the c hannel to operate in the h igh s peed hdlc c ontroller m ode the user can configure a given channel to operate in the high speed hdlc controller mode by writing the appropriate data into the channels hdlc control register. the address location of the hdlc control register, for each of the three channels (within the XRT72L50 de- vice) is listed below in table 92 . the user can configure a given channel to operate in the high-speed hdlc controller mode by setting bit 6 (hdlc on), within the appropriate hdlc control register to 1, as depicted below. 8.2 o perating the h igh s peed hdlc c ontrol - ler once the user has configured a given channel to op- erate in the high-speed hdlc controller mode, then both the transmit and receive hdlc controller blocks, within the appropriate channel will be active. the next few sections describe how to use the trans- mit and receive hdlc controller blocks, within a giv- en channel. t able 92: a ddress l ocations of each of the hdlc control r egisters within the XRT72L50 d evice . c hannel n umber a ddress l ocation 00x82 10x282 20x482 hdlc control register (address = 0x82) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framer by-pass hdlc on crc-32 select reserved hdlc loop-back reserved r/w r/w r/w r/w r/w r/w r/w r/w 01000000 ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 450 8.2.1 operating the transmit hdlc controller block once the user has configured a given channel to op- erate in the high-speed hdlc controller mode, then certain pins (which have multiple functions) will be configured to support operation of the transmit and receive hdlc controller blocks. the transmit hdlc controller block, within each channel consists of the following pins. ? snd_msg_n ? snd_fcs_n ? txhdlcclk_n ? txhdlcdat_n[7:0] each of these pins are described below in table 93 . XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 451 whenever the user wishes to transmit data via the transmit hdlc controller block, then he/she should pull the snd_msg_n input pin "high". once the snd_msg_n pin is pulled high, then the transmit t able 93: d escription of e ach of the t ransmit hdlc c ontroller p ins p in n ame t ype d escription snd_msg_n i send message command: this input pin permits the user to command the transmit hdlc controller block to begin sampling and latching the data, which is being applied to the txhdlcdat_n[7:0] input pins. if the user pulls this input pin "high", then the transmit hdlc controller block will begin to sample and latch the data (which is applied to the txhdlcdat_n[7:0] input pins), upon the rising edge of txhdlcclk_n. each byte of this sampled data will ulti- mately be encapsulated into an outbound hdlc frame. if the user pulls this input pin "low", then the transmit hdlc controller block will not sample and latch data (which is residing on the txhdlcdat_n[7:0] input pins. as a consequence, no outbound hdlc frames will be generated, and the transmit hdlc controller block will simply generate a constant stream of flag sequence octets (0x7e). snd_fcs_n i send frame check sequence command: the users terminal equipment is expected to control both this input pin, along with the snd_msg_n input pin, during the construction and transmission of each outbound hdlc frame. this input pin permits the user to command the transmit hdlc controller block to compute and insert the compute fcs (frame-check sequence) value into the back- end of the outbound hdlc frame, as a trailer. if the user has configured the transmit hdlc controller to compute and insert a crc- 16 value into the outbound hdlc frame, then the terminal equipment is expected to pull this input pin "high" for two periods of txhdlcclk_n. conversely, if the user has configured the transmit hdlc controller to compute and insert a crc-32 value into the outbound hdlc frame, then the terminal equipment is expected to pull this input pin "high" for four periods of txhdlcclk_n. txhdlcclk_n o transmit hdlc controller clock output signal: this output signal functions as the demand clock for the transmit hdlc controller. when the user pulls the snd_msg_n input pin "high", then the transmit hdlc con- troller block will begin to sample and latch the contents of the txhdlcdat_n[7:0] upon the rising edge of this clock signal. as a consequence, the user is advised to design/ configure their terminal equipment circuitry to output data (onto the txhdlcdat_n[7:0] bus), upon the falling edge of this clock signal. since the transmit hdlc controller block is sampling and latching 8-bits of data at a given time, it may be presumed that the frequency of the txhdlcclk_n output signal is either 34.368mhz/8 or 44.736mhz/8. in general, this presumption is true. however, because the transmit hdlc controller is also performing 0 stuffing of the user data that it receives from the terminal equipment, the frequency of this signal may be slower. txhdlcdat_n[7:0] i transmit hdlc controller - input data bus: these eight input pins function as the byte-wide input interface to the transmit hdlc controller. if the user pulls the snd_msg_n input pin "high", then the transmit hdlc controller block will begin to sample and latch the contents of this data bus, into the transmit hdlc controller circuitry (upon the rising edge of txhdlcclk_n). all data that is sampled, via this byte-wide interface will ultimately be encapsulated into an out- bound hdlc controller. if the user pulls the snd_msg_n input pin "low", then the transmit hdlc controller block will ignore the data that is being applied to this data bus. ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 452 hdlc controller block will begin to sample the data on the txhdlcdat_n[7:0] input pins, upon the rising edge of the txhdlcclk_n clock output signal. each byte of data that is sampled and latched into the transmit hdlc controller block will be encapsulated into an outbound hdlc frame. after the last byte of data has been latched into the transmit hdlc controller block, then the user must pull the snd_fcs_n input pin "high" for either two or four txhdlcclk_n clock periods. if the user has configured the transmit hdlc control- ler block to append a 16-bit crc value (from here on, referred to as crc-16); then the user must pull and hold the snd_fcs_n input pin "high" for two (2) txhdlcclk_n clock periods. conversely, if the user has configured the transmit hdlc controller block to append a 32 bit crc value (from here on, referred to as crc-32); then the user must pull and hold the snd_fcs_n input pin "high" for (4) txhdlcclk_n periods. pulling the snd_fcs_n input pin "high" configures the transmit hdlc controller to begin its insertion of either the crc-16 or crc-32 value into the back-end of the outbound hdlc controller. selecting either crc-16 or crc-32 the user can configure the transmit hdlc controller block (within channel n) to append either a crc-16 or crc-32 value to the user-data within the outbound hdlc frame, by writing the appropriate value into bit 5 (crc-32 select). setting this bit-field "high" config- ures the transmit hdlc controller block to append a crc-32 value to the user data, within the outbound hdlc frame. conversely, setting this bit-field "low" configures the transmit hdlc controller block to ap- pend a crc-16 value to the user data, within the out- bound hdlc frame. a simple illustration of the resulting outbound hdlc frame (when crc-32 select, is invoked) is presented below in figure 214 . similarly, a simple illustration of the resulting out- bound hdlc frame (when crc-16 is selected) is presented below in figure 215 . f igure 214. a s imple i llustration of an o utbound hdlc f rame , as assembled by the t ransmit hdlc c ontroller , when crc-32 is selected . crc-32 trailer user supplied data hdlc frame XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 453 once the outbound hdlc frame has been formed, then it will be transmitted to the remote terminal equipment via payload bits of the outbound ds3 or e3 frames. if the users terminal equipment does not supply any more data (which needs to be encapsulated into the outbound hdlc frame and transmitted to the remote terminal equipment), then the transmit hdlc con- troller block will begin transmitting a constant stream of flag sequence octets (0x7e). these flag sequence octets will also be transmitted to the remote terminal equipment via the payload bits of the outbound ds3 or e3 frames. 8.2.2 operating the receive hdlc controller block the receive hdlc controller block, within each channel consists of the following pins. ? rxidle_n ? val_fcs_n ? rxhdlcclk_n ? rxhdlcdat_n[7:0] each of these output pins are described below in table 94 . f igure 215. a s imple i llustration of an o utbound hdlc f rame , as assembled by the t ransmit hdlc c ontroller , when crc-16 is selected . crc-16 trailer user supplied data hdlc frame ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 454 t able 94: d escription of e ach of the r eceive hdlc c ontroller p ins p in n ame t ype d escription rxidle_n o receive idle (flag sequence) indicator signal the combination of the rxidle_n and val_fcs_n output signals are used to convey information about data that is being received via the receive hdlc controller block. if rxidle_n = high the receive hdlc controller block will pulse this output pin "high" anytime the flag sequence is present on the rxhdlcdat_n[7:0] output data bus. if rxidle_n and val_fcs_n are both "high" the receive hdlc controller block has received a complete hdlc frame, and has determined that the fcs value (within this hdlc frame) is valid. if rxidle_n is "high" and val_fcs_n is "low" the receive hdlc controller block has received a complete hdlc frame, and has determined that the fcs value (within this hdlc frame) is invalid. if rxidle_n is "low" and val_fcs_n is "high" the receive hdlc controller block has received an abort sequence. val_fcs_n o valid fcs indicator signal please see description above. rxhdlcclk_n o receive hdlc controller clock output signal: the receive hdlc controller block outputs data (via the rxhdlcdat_n[7:0] output pins) upon the rising edge of this clock signal. as a consequence, the user is advised to configure/design his/her terminal equipment circuitry to sample the contents of the rxhdlcdat_n[7:0] output pins, upon the falling edge of this clock signal. rxhdlcdat_n[7:0] i receive hdlc controller - output data bus: the receive hdlc controller block outputs data (via these output pins) upon the ris- ing edge of the rxhdlcclk_n clock signal. as a consequence, the user is advised to configure/design his/her terminal equiment circuitry to sample the contents of this data bus, upon the falling edge of this clock signal. XRT72L50 ? ? ? ? single channel ds3/e3 framer ic with hdlc controller rev. p1.1.3 preliminary 455 ordering information package dimensions p art n umber p ackage t ype o perating t emperature r ange XRT72L50 14x20mm, 100 lead plastic qfp -40c to +85c 80 51 50 31 130 81 100 d d1 e e1 b e a2 a a1 a seating plane l c 100 lead plastic quad flat pac k (14 mm x 20 mm, qfp) rev. 2.00 note: the control dimension is the millimeter column 1.95 mm form inches millimeters min max min max 0.102 0.134 2.60 3.40 0.002 0.014 0.05 0.35 0.100 0.120 2.55 3.05 0.009 0.015 0.22 0.38 0.005 0.009 0.13 0.23 0.931 0.951 23.65 24.15 0.783 0.791 19.90 20.10 0.695 0.715 17.65 18.15 0.547 0.555 13.90 14.10 0.0256 bsc 0.65 bsc 0.026 0.037 0.65 0.95 0 7 0 7 symbol a a 1 a 2 b c d d 1 e e 1 e l a a a a ? ? ? ? XRT72L50 single channel ds3/e3 framer ic with hdlc controller preliminary rev. p1.1.3 456 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2000 exar corporation datasheet january 2001. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history added sections on hdlc controller. rev 1.1.3 -- made corrections to figures 37, 38, 39, 65, 75, 102, 120, 130, 161, 163, 178 and 188. |
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