MSVD-HD multi-standard high-definition video decoder (h.264, vc-1, mpeg-1/2) the multi-standard high-definition video decoder designobject? (MSVD-HD*) is one of the smallest synthesizable cores in the market, performing time multiplexed decoding of multiple streams in different standards at all resolutions up to 2048x2048 pixels. it is sub- stantially smaller than a fully programmable solution. the MSVD-HD is a real-time solution for dual-stream high-definition video decoding with a single core at a low clock rate. applications ? set-top boxes ? digital tv sets and iptv applications ? dvd, hd-dvd and blu-ray players and recorders ? portable multimedia players ? surveillance key features ? supports h.264, mpeg-1/2 & vc-1 up to 1080p @ 60 fps ? supports all dvb, atsc, hdtv, dvd, vcd resolutions ? supports picture size from 48x32 to 2048x2048 pixel ip product brief the MSVD-HD currently supports h.264, mpeg-1/2 and vc-1 standards. the decoding functionality is implemented as an autono- mously working pipeline consisting of various hardware blocks. the driver software running on an external controller, a general purpose 32- bit processor, performs setup and general con- trolling tasks. the MSVD-HD reads the input stream from a buffer located in the system memory (sdram) and generates decoded video in ycbcr 4:2:0 format. the output pictures are stored in the decoded picture buffer area within the system memory. MSVD-HD is an optimized solution for video decoding applications, based on an architecture that implements pipelining and parallelism on different levels. MSVD-HD consists of a soft- ware part and a hardware part. the hardware part is composed of two main blocks, the stream interpreter and the multi-standard video decoding engine. in order to achieve maximum performance, the two blocks work in parallel. the MSVD-HD is optimized to satisfy a wide range of applications and technologies with optimal performance at low silicon cost. its interfaces are designed for easy integration into system-on-chip designs. MSVD-HD system diagram *MSVD-HD was formerly part of the sci-worx gmbh product port- folio. silicon image acquired sci- worx in january 2007.
silicon image video cores decoder for sd resolution: ? consumer dv ? mpeg-1, mpeg-2 (multi-stream) ? mpeg-1/2/4, divx, xvid encoder for sd resolution: ? mpeg-1, mpeg-2 (i-frame) ? mpeg-1, mpeg-2 (ipb-frame) ? mpeg-1/2/4, divx, xvid (ipb-frame) decoder for hd resolution: ? mpeg-1, mpeg-2 (dual-hd) MSVD-HD features ? supported standards: - itu-t h.264, iso/iec 14496-10 (main and high profile up to level 4.2) - smpte 421m vc-1 (simple, main and advanced profile @ level 4) - iso/iec 11172-2 mpeg-1 - iso/iec 13818-2 mpeg-2 (main profile @ high level) ? supports all dvb, atsc, hdtv, dvd, vcd resolutions (e.g. 1080p, 1080i, 720p, d1) ? supports picture size from 48x32 pixel to 2048x2048 pixel ? error detection and concealment ? trick mode support ? processing of es and pes streams, extraction and provision of time stamps ? soc prototyping on fpga including asic bus interconnect and ddr2 sdram ? allegro h.264 certification test suite proven ? 64-bit ports to memory system, ocp 2.0 and amba axi compliant key advantages ? silicon area efficient solution ? true multi-stream decoding features: - hd dual-stream processing performance - multiple streams (up to 16 supported by hw, minimal sw support) - applications are program preview, multiple thumbnail streams ? fine granular context switching between streams on macroblock row level: - minimizes memory requirements for input buffers - minimizes input to output delay ? simultaneous multi-stream and multi-standard decoding: - e.g. one hd h.264 and one hd mpeg-2 stream performance ? dual-stream decode up to 1080i @ 30 fps at 150mhz core clock frequency ? single-stream decode up to 1080p @ 60 fps at 150mhz core clock frequency ? time multiplexed multi-stream decoding with fine granular context switching, possible com- binations are: - two hd video streams h.264, vc-1, mpeg-2 - one h.264 hd stream and four vc-1 sd streams - one hd stream and 16 cif streams ? hardwired, autonomously running decoding pipeline, two samples per clock throughput ? hardware supported context switching between video streams (configurable up to 16 streams) ? MSVD-HD core and memory system can run with different clocks; clock domain crossing is part of MSVD-HD ? 2007 silicon image, inc. all rights reserved. silicon image, the silicon image logo, MSVD-HD and designobject are trademarks or registered trademarks of silicon image, inc. in the united states and other coun- tries. other trademarks are property of their respective holders. product specifications are subject to change without notice. part number: MSVD-HD sii-pb-1008 rev1 3/07 silicon image, inc. 1060 e. arques avenue sunnyvale, ca 94085 t 408.616.4000 f 408.830.9530 www.siliconimage.com gate count 1 ram size MSVD-HD 970 kgates 2 152 kbits 1 gate = 2 input nand equivalent, using a tsmc 90 nm library (tsmc90g library under worst-case condition, 20% security margin), mbist not included 2 gate count includes complete memory interfacing, stream reader func- tionality and extra logic for context switch support (245 kgates) sram instances 41 MSVD-HD gate count
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