? semiconductor components industries, llc, 2003 june, 2003 - rev. 1 1 publication order number: NTMS4P01R2/d NTMS4P01R2 power mosfet -4.5 amps, -12 volts p-channel enhancement-mode single so-8 package features ? high density power mosfet with ultra low r ds(on) providing higher efficiency ? miniature so- 8 surface mount package - saves board space ? diode exhibits high speed with soft recovery ? i dss specified at elevated temperature ? drain- to- source avalanche energy specified ? mounting information for the so- 8 package is provided applications ? power management in portable and battery-powered products, i.e.: computers, printers, pcmcia cards, cellular & cordless telephones maximum ratings please see the table on the following page device package shipping ordering information NTMS4P01R2 so-8 2500/tape & reel so-8 case 751 style 13 1 single p-channel d s g 8 2 n.c. source source gate 3 4 1 7 6 5 8 drain drain drain drain top view marking diagram & pin assignment e4p01 lyww e4p01 = device code l = assembly location y = year ww = work week v dss r ds(on) typ i d max -12 v 30 m w @ -4.5 v -4.5 a http://onsemi.com
NTMS4P01R2 http://onsemi.com 2 maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain-to-source voltage v dss -12 v drain-to-gate voltage (r gs = 1.0 m ) v dgr -12 v gate-to-source voltage - continuous v gs 10 v thermal resistance - junction-to-ambient (note 1) total power dissipation @ t a = 25 c continuous drain current @ 25 c continuous drain current @ 70 c maximum operating power dissipation maximum operating drain current pulsed drain current (note 4) r q ja p d i d i d p d i d i dm 50 2.5 -6.04 -4.82 1.2 -4.18 -20 c/w w a a w a a thermal resistance - junction-to-ambient (note 2) total power dissipation @ t a = 25 c continuous drain current @ 25 c continuous drain current @ 70 c maximum operating power dissipation maximum operating drain current pulsed drain current (note 4) r q ja p d i d i d p d i d i dm 85 1.47 -4.50 -3.65 0.7 -3.20 -15 c/w w a a w a a thermal resistance - junction-to-ambient (note 3) total power dissipation @ t a = 25 c continuous drain current @ 25 c continuous drain current @ 70 c maximum operating power dissipation maximum operating drain current pulsed drain current (note 4) r q ja p d i d i d p d i d i dm 159 0.79 -3.40 -2.72 0.38 -2.32 -12 c/w w a a w a a operating and storage temperature range t j , t stg - 55 to +150 c single pulse drain-to-source avalanche energy - starting t j = 25 c (v dd = -12 vdc, v gs = -5.0 vdc, peak i l = -8.0 apk, l = 10 mh, r g = 25 w ) e as 320 mj maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. mounted onto a 2 square fr-4 board (1 sq. 2 oz cu 0.06 thick single sided), t 10 seconds. 2. mounted onto a 2 square fr-4 board (1 sq. 2 oz cu 0.06 thick single sided), t = steady state. 3. minimum fr-4 or g-10 pcb, t = steady state. 4. pulse test: pulse width = 300 s, duty cycle = 2%.
NTMS4P01R2 http://onsemi.com 3 electrical characteristics (t c = 25 c unless otherwise noted) (note 5) characteristic symbol min typ max unit off characteristics drain-to-source breakdown voltage (v gs = 0 vdc, i d = -250 m adc) temperature coefficient (positive) v (br)dss -12 - - -15 - - vdc mv/ c zero gate voltage drain current (v ds = -12 vdc, v gs = 0 vdc, t j = 25 c) (v ds = -12 vdc, v gs = 0 vdc, t j = 125 c) i dss - - - - -1.0 -10 m adc gate-body leakage current (v gs = -10 vdc, v ds = 0 vdc) i gss - - -100 nadc gate-body leakage current (v gs = +10 vdc, v ds = 0 vdc) i gss - - 100 nadc on characteristics gate threshold voltage (v ds = v gs , i d = -250 m adc) temperature coefficient (negative) v gs(th) -0.65 - -0.9 2.9 -1.15 - vdc mv/ c static drain-to-source on-state resistance (v gs = -4.5 vdc, i d = -4.5 adc) (v gs = -2.7 vdc, i d = -2.25 adc) (v gs = -2.5 vdc, i d = -2.25 adc) r ds(on) - - - 0.030 0.040 0.045 0.045 0.055 - w forward transconductance (v ds = -2.5 vdc, i d = -2.25 adc) g fs - 10 - mhos dynamic characteristics input capacitance (v 9 6 vd v 0vd c iss - 1435 1850 pf output capacitance (v ds = -9.6 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss - 635 1000 reverse transfer capacitance f = 1 . 0 mhz) c rss - 210 400 switching characteristics (notes 6 & 7) turn-on delay time t d(on) - 20 35 ns rise time (v dd = -12 vdc, i d = -4.5 adc, v gs = -4 5 vdc t r - 60 100 turn-of f delay time v gs = -4.5 vdc, r g = 6.0 w ) t d(off) - 65 100 fall time r g 6.0 w ) t f - 75 125 total gate charge (v ds =- 9.6 vdc, q tot - 20 35 nc gate-source charge (v ds = - 9 . 6 vdc , v gs = -4.5 vdc, i 4 5 ad ) q gs - 4.0 - gate-drain charge gs i d = -4.5 adc) q gd - 7.0 - body-drain diode ratings (note 6) diode forward on-voltage (i s = -4.5 adc, v gs = 0 v) (i s = -4.5 adc, v gs = 0 vdc, t j = 125 c) v sd - - -0.9 -0.7 -1.25 - vdc reverse recovery time (i 4 5 ad v 0vd t rr - 38 - ns (i s = -4.5 adc, v gs = 0 vdc, di s /dt = 100 a/ m s ) t a - 20 - di s /dt = 100 a/ m s) t b - 18 - reverse recovery stored charge q rr - 0.03 - m c 5. handling precautions to protect against electrostatic discharge is mandatory. 6. indicates pulse test: pulse width = 300 m s max, duty cycle = 2%. 7. switching characteristics are independent of operating junction temperature.
NTMS4P01R2 http://onsemi.com 4 -2.3 v figure 1. on-region characteristics -v ds , drain-to-source voltage (volts) 8 6 4 2 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 figure 2. transfer characteristics -v gs , gate-t o-source voltage (volts) 2 1.5 1 8 6 4 2 0 0 figure 3. on-resistance versus gate-t o-source voltage -v gs , gate-t o-source voltage (volts) 0.12 0.06 0.03 6 4 2 0 figure 4. on-resistance versus drain current and gate voltage -i d , drain current (amps) 6 4 2 0.03 0.02 0.01 0 0.05 figure 5. on-resistance variation with temperature t j , junction temperature ( c) 1.6 1.4 1.2 1 0.8 150 125 100 75 50 25 0 -25 -50 figure 6. drain-to-source leakage current versus voltage -v ds , drain-to-source voltage (volts) 12 10 6 2 1000 100 0.6 10,000 v ds -10 v t j = -55 c 25 c 100 c i d = -4.5 a t j = 25 c t j = 25 c v gs = -2.5 v v gs = -4.5 v i d = -4.5 a v gs = -4.5 v t j = 125 c v gs = 0 v t j = 150 c t j = 25 c v gs = -1.3 v -1.9 v -i d , drain current (amps) 7 5 -1.7 v -8 v -4.5 v -3.7 v -3.1 v -i d , drain current (amps) r ds(on) , drain-to-source resistance ( ) 0.09 r ds(on) , drain-to-source resistance ( ) 8 0.04 v gs = -2.7 v r ds(on) , drain-to-source resistance (normalized) -i dss , leakage (na) 48 -2.1 v -2.7 v -2.5 v 2.5 8 0.5 3 1
NTMS4P01R2 http://onsemi.com 5 r g , gate resistance (ohms) 1 10 100 100 10 t, time (ns) v dd = -12 v i d = -4.5 a v gs = -4.5 v t r t d(on) 10 -v gs , gate-t o-source voltage (volts) 2 0 0 1 0 q g , total gate charge (nc) -v ds , drain-to-source voltage (volts) 5 48 i d = -4.5 a t j = 25 c -v ds -v gs q2 q1 1000 t f 3 2 4 6 4 8 qt t d(off) 12 16 20 24 0.2 0.4 0.5 0.6 0 1 2 -v sd , source-to-drain voltage (volts) v gs = 0 v t j = 25 c 3 0.7 0.8 1 -i s , source current (amps) 0.9 0.3 4 gate-t o-source or drain-t o-source voltage (volts) c, capacitance (pf) 3000 figure 7. capacitance variation 10 0 6 6 t j = 25 c c iss c oss c rss 12 0 1000 2000 c iss c rss v gs = 0 v v ds = 0 v -v ds -v gs 4000 24 figure 8. gate-to-source and drain-to-source voltage versus total charge figure 9. resistive switching time variation versus gate resistance figure 10. diode forward voltage versus current 82 4810 drain-t o-source diode characteristics figure 11. maximum rated forward biased safe operating area figure 12. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 0.1 v ds , drain-to-source voltage (volts) 0.01 1 i d , drain current (amps) r ds(on) limit thermal limit package limit v gs = 10 v single pulse t c = 25 c 10 dc 1 100 100 10 10 ms 1.0 ms 0.1 mounted on 2 sq. fr4 board (1 sq. 2 oz. cu 0.06 thick single sided), 10s max.
NTMS4P01R2 http://onsemi.com 6 typical electrical characteristics figure 13. thermal response t, time (s) rthja(t), effective transient thermal resistance 1 0.1 0.01 d = 0.5 single pulse 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.2 0.05 0.01 1.0e+02 1.0e+03 0.001 10 0.0163 w 0.0652 w 0.1988 w 0.6411 w 0.9502 w 72.416 f 1.9437 f 0.5541 f 0.1668 f 0.0307 f chip ambient normalized to q ja at 10s. 0.1 0.02 information for using the so-8 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self-align when subjected to a solder reflow process. mm inches 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
NTMS4P01R2 http://onsemi.com 7 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating profileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 -189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 rampo step 2 vent soako step 3 heating zones 2 & 5 rampo step 4 heating zones 3 & 6 soako step 5 heating zones 4 & 7 spikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 14. typical solder heating profile
NTMS4P01R2 http://onsemi.com 8 package dimensions so-8 case 751-07 issue aa seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751-01 thru 751-06 are obsolete. new standard is 751-07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 -x- -y- g m y m 0.25 (0.010) -z- y m 0.25 (0.010) z s x s m style 13: pin 1. n.c. 2. source 3. source 4. gate 5. drain 6. drain 7. drain 8. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. NTMS4P01R2/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada
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