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1 features ? 64-megabit (4m x 16) flash memory 2.7v - 3.6v read/write high performance ? asynchronous access time ? 70 ns ? page mode read time ? 20 ns sector erase architecture ? eight 4k word sectors with individual write lockout ? one hundred twenty-seven 32k word main sectors with individual write lockout typical sector erase time: 32k word sectors ? 700 ms; 4k word sectors ? 200 ms four plane organization, permitting concurrent read in any of the three planes not being programmed/erased ? memory plane a: 16m memory including eight 4k word sectors ? memory plane b: 16m memory consisting of 32k word sectors ? memory plane c: 16m memory consisting of 32k word sectors ? memory plane d: 16m memory consisting of 32k word sectors suspend/resume feature for erase and program ? supports reading and programming data from any sector by suspending erase of a different sector ? supports reading any word by suspending programming of any other word low-power operation ?30 ma active ? 35 a standby 2.2v i/o option reduces overall system power vpp pin for write protection and accelerated program/erase operations reset input for device initialization cbga package top or bottom boot block configuration available 128-bit protection register common flash interface (cfi) description the AT49BV6416C(t) is a 2.7-volt 64-megabit flash memory. the memory is divided into multiple sectors and planes for erase operations. the device can be read or repro- grammed off a single 2.7v power supply, making it ideally suited for in-system programming. the device can operate in the asynchronous or page read mode. 64-megabit (4m x 16) page mode 2.7-volt flash memory AT49BV6416C AT49BV6416Ct 3465b?flash?11/04 pin configurations pin name pin function i/o0 - i/o15 data inputs/outputs a0 - a21 addresses ce chip enable oe output enable we write enable reset reset wp write protect vpp write protection and power supply for accelerated program/erase operations vccq output power supply AT49BV6416C(t) (7 x 10 mm) ? top view a b c d e f 1 234567 a13 a14 a15 a16 vccq gnd a11 a10 a12 i/o14 i/o15 i/o7 a8 we a9 i/o5 i/o6 i/o13 vpp rst a21 i/o11 i/o12 i/o4 wp a18 a20 i/o2 i/o3 vcc a19 a17 a6 i/o8 i/o9 i/o10 a7 a5 a3 ce i/o0 i/o1 a4 a2 a1 a0 gnd oe 8
2 AT49BV6416C(t) 3465b?flash?11/04 the AT49BV6416C(t) is divided into four memory planes. a read operation can occur in any of the three planes which is not being programmed or erased. this concurrent operation allows improved system performance by not r equiring the system to wait for a program or erase operation to complete before a read is per formed. to further increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or pro- gram data to any of the remaining sectors. there is no reason to suspend the erase or program operation if the data to be read is in another memory plane. the vpp pin provides data protection and faster programming and erase times. when the v pp input is below 0.7v, the program and er ase functions are inhibited. when v pp is at 1.65v or above, normal program and erase operations can be performed. with v pp at 12.0v, the pro- gram (dual-word program command) and erase operations are accelerated. device operation command sequences: when the device is first power ed on, it will be in the read mode. command sequences are used to place the device in other operating modes such as program and erase. the command sequences are written by applying a low pulse on the we input with ce low and oe high or by applying a low-going pulse on the ce input with we low and oe high. the address is latched on the first rising edge of the we or ce . valid data is latched on the rising edge of the we or the ce pulse, whichever occurs first. the addresses used in the command sequences are not affected by entering the command sequences. asynchronous read: the AT49BV6416C(t) is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. page read: the page read operation of the device is controlled by ce and oe inputs. the page size is four words. the first word access of the page read is the same as the asynchro- nous read. the first word is read at an asynch ronous speed of 70 ns. once the first word is read, toggling a0 and a1 will result in subsequent reads within the page being output at a speed of 20 ns. the page read diagram is shown on page 22. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset pin halts the present device operation and puts the outputs of the device in a high-impedance state. when a high level is reasserted on the reset pin, the device returns to read mode. erase: before a word can be reprogrammed it must be erased. the erased state of the memory bits is a logical ?1?. the entire memory can be erased by using the chip erase com- mand or individual planes can be erased by using the plane erase command or individual sectors can be erased by using the sector erase command. chip erase : chip erase is a two-bus cycle operation. the automatic erase begins on the rising edge of the last we pulse. chip erase does not alter the data of the protected sectors. the hardware reset during chip erase will stop the erase, but the data will be of an unknown state. plane erase: as an alternative to a full chip erase, the device is organized into four planes that can be individually erased. the plane erase command is a two-bus cycle operation. the plane whose address is valid at the second rising edge of we will be erased. the plane erase command does not alter the data in the protected sectors. sector erase: the device is organized into multiple sectors that can be individually erased. the sector erase command is a two-bus cycle operation. the sector whose address is valid at the second rising edge of we will be erased provided the given sector has not been protected.
3 AT49BV6416C(t) 3465b?flash?11/04 word programming: the device is programmed on a word-by-word basis. programming is accomplished via the internal device command register and is a two-bus cycle operation. the programming address and data are latched in the second cycle. the device will automati- cally generate the required internal programmi ng pulses. please note that a ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. flexible sector protection: the AT49BV6416C(t) offers two sector protection modes, the softlock and the hardlock. the softlock mode is optimized as sector protection for sectors whose content changes frequently. the hardlock protection mode is recommended for sectors whose content changes infrequently. once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. each sector can be independently programmed for either the softlock or hardlock sector protection mode. at power-up and reset, all sectors have their softlock protection mode enabled. softlock and unlock: the softlock protection mode can be disabled by issuing a two- bus cycle unlock command to the selected sector. once a sector is unlocked, its contents can be erased or programmed. to enable the softlock protection mode, a two-bus cycle softlock command must be issued to the selected sector. hardlock and write protect (wp ): the hardlock sector protection mode operates in conjunction with the write protection (wp ) pin. the hardlock sector protection mode can be enabled by issuing a two-bus cycle hardlock software command to the selected sector. the state of the write protect pin affects whether the hardlock protection mode can be overridden. when the wp pin is low and the hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. when the wp pin is high, the hardlock protection mode is overridden and the sector can be unlocked via the unlock command. to disable the hardlock sector protection mode, the chip must be either reset or power cycled. table 1. hardlock and softlock protection configurations in conjunction with wp v pp wp hard- lock soft- lock erase/ prog allowed? comments v cc 0 0 0 yes no sector is locked v cc 0 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc 0 1 1 no hardlock protection mode is enabled. the sector cannot be unlocked. v cc 1 0 0 yes no sector is locked. v cc 1 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc 1 1 0 yes hardlock protection mode is overridden and the sector is not locked. v cc 1 1 1 no hardlock protection mode is overridden and the sector can be unlocked via the unlock command. v il x x x no erase and program operations cannot be performed.
4 AT49BV6416C(t) 3465b?flash?11/04 figure 1. sector locking state diagram note: 1. the notation [x, y, z] denotes the locking state of a sector. the current locking state of a sector is defined by the state of wp and the two bits of the sector-lock status d[1:0]. sector protection detection: a software method is available to determine if the sec- tor protection softlock or hardlock features are enabled. when the device is in the software product identification mode a read from the i/o0 and i/o1 at address location 00002h within a sector will show if the sector is unlocked, softlocked, or hardlocked. read status register : the status register indicates the status of device operations and the success/failure of that operation. the read status register command causes subsequent reads to output data from the status register until another command is issued. to return to reading from the memory, issue a read command. the status register bits are output on i/o7 - i/o0. the upper byte, i/o15 - i/o8, outputs 00h when a read status register command is issued. the contents of the status register [sr7:sr0] are latched on the falling edge of oe or ce (whichever occurs last), which prevents possible bus errors that might occur if status register contents change while being read. ce or oe must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the write state machine (wsm) is active, sr7 will indicate the status of the wsm; the remaining bits in the status register indicate whether the wsm was successful in performing the preferred operation (see table 3). table 2. sector protection status i/o1 i/o0 sector protection status 0 0 sector not locked 0 1 softlock enabled 1 0 hardlock enabled 1 1 both hardlock and softlock enabled [000] [001] [011] [111] [101] [110] [100] unlocked locked wp = v il =0 wp = v ih =1 power-up/reset default power-up/reset default hardlocked is disabled by wp = v ih = unlock command = softlock command = hardlock command hardlocked ab c c ab ab c c a b c
5 AT49BV6416C(t) 3465b?flash?11/04 note: 1. a command sequence error is indicated when sr1, sr3, sr4 and sr5 are set. table 3. status register bit definition wsms ess es prs vpps pss sls pls 76543210 notes sr7 write state machine status (wsms) 1 = ready 0 = busy check write state machine bit first to determine word program or sector erase completion, before checking program or erase status bits. sr6 = erase suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to ?1? ? ess bit remains set to ?1? until an erase resume command is issued. sr5 = erase status (es) 1 = error in sector erase 0 = successful sector erase when this bit is set to ?1?, wsm has applied the max number of erase pulses to the sector and is still unable to verify successful sector erasure. sr4 = program status (prs) 1 = error in programming 0 = successful programming when this bit is set to ?1?, wsm has attempted but failed to program a word sr3 = vpp status (vpps) 1 = vpp low detect, operation abort 0 = vpp ok the v pp status bit does not provide continuous indication of vpp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered and informs the system if v pp has not been switched on. the v pp is also checked before the operation is verified by the wsm. sr2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to ?1?. pss bit remains set to ?1? until a program resume command is issued. sr1 = sector lock status 1 = prog/erase attempted on a locked sector; operation aborted. 0 = no operation to locked sectors if a program or erase operation is attempted to one of the locked sectors, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr0 = plane status (pls) indicates program or erase status of the addressed plane. table 4. status register device wsms and write status definition wsms (sr7) pls (sr0) description 0 0 the addressed plane is performing a program/erase operation. 0 1 a plane other than the one currently addressed is performing a program/erase operation. 1 x no program/erase operation is in progress in any plane. erase and program suspend bits (sr6, sr2) indicate whether other planes are suspended.
6 AT49BV6416C(t) 3465b?flash?11/04 erase suspend/erase resume: the erase suspend command allows the system to interrupt a sector erase or plane erase operation. the erase suspend command does not work with the chip erase feature. using the erase suspend command to suspend a sector erase operation, the system can program or read data from a different sector within the same plane. since this device is organized into four planes, there is no need to use the erase suspend fea- ture while erasing a sector when you want to read data from a sector in another plane. after the erase suspend command is given, the device requires a maximum time of 15 s to sus- pend the erase operation. after the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. the system can then read data or program data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operat ion, the system must write the erase resume command. the erase resume command is a one-bus cycle command, which does require the plane address. read, read status register, product id entry, clear status register, pro- gram, program suspend, erase resume, sector softlock/hardlock, sector unlock are valid commands during an erase suspend. program suspend/program resume: the program suspend command allows the system to interrupt a programming operation a nd then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 10 s to suspend the programming operati on. after the programming operation has been suspended, the system can then read from any other word within the device. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume command. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program sus- pend are the same, and the command sequence for the erase resume and program resume are the same. read, read status register, product id entry, program resume are valid com- mands during a program suspend. 128-bit protection register: the AT49BV6416C(t) contains a 128-bit register that can be used for security purposes in system design. the protection register is divided into two 64-bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. to program block b in the protection register, the two-bus cycle program protection register command must be used as shown in the command definition table on page 13. to lock out block b, the two-bus cycle lock protection register command must be used as shown in the command definition table. data bit d1 mu st be zero during the second bus cycle. all other data bits during the second bus cycle are don?t cares. to determine whether block b is locked out, the status of sector b protection command is given. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be reprogrammed. please see the protection reg- ister addressing table on page 14 for the address locations in the protection register. to read the protection register, the product id entr y command is given followed by a normal read operation from an address within the protection register. after determining whether block b is protected or not or reading the protection register, the read command must be given to return to the read mode.
7 AT49BV6416C(t) 3465b?flash?11/04 cfi: common flash interface (cfi) is a published, standardized data structure that may be read from a flash device. cfi allows system software to query the installed device to deter- mine the configurations, various electrical and timing parameters, and functions supported by the device. cfi is used to allow the system to learn how to interface to the flash device most optimally. the two primary benefits of using cfi are ease of upgrading and second source availability. the command to enter the cfi query mode is a one-bus cycle command which requires writing data 98h to any address. the cfi query command can be written when the device is ready to read data or can also be wr itten when the part is in the product id mode. once in the cfi query mode, the system can read cfi data at the addresses given in table 5 on page 25. to return to the read mode, the read command should be issued. hardware data protection: hardware features protect against inadvertent programs to the AT49BV6416C(t) in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the device is reset and the program and erase functions are inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time-out 10 ms (typi- cal) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. (e) v pp is less than v ilpp . input levels: while operating with a 2.7v to 3.6v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 2.5v without adversely affecting the operation of the device. the i/o lines can be driven from 0 to v ccq + 0.6v. output levels: for the AT49BV6416C(t), output high levels are equal to v ccq - 0.1v (not v cc ). for 2.7v to 3.6v output levels, v ccq must be tied to v cc .
8 AT49BV6416C(t) 3465b?flash?11/04 word program flowchart full status check flowchart pr ogram suspend loop start wr ite 40, wor d addr ess wr ite d ata, wor d addr ess read status register sr 7 = full status check (if desired) progr am complete suspend? 1 0 no yes (s etup) (confirm) read status register progr am successful sr3 = sr1 = 0 0 sr4 = 0 1 1 1 v pp range error device pr otect err or progr am error word program procedure full status check procedure bus operation command comments write program setup data = 40 addr = location to program write data data = data to program addr = location to program read none status register data: toggle ce or oe to update status register idle none check sr7 1 = wsm ready 0 = wsm busy repeat for subsequent word program operations. full status register check can be done after each program, or after a sequence of program operations. write ff after the last operation to set to the read state. bus operation command comments idle none check sr3: 1 = v pp error idle none check sr4: 1 = data program error idle none check sr1: 1 = sector locked; operation aborted sr3 must be cleared before the write state machine allows further program attempts. if an error is detected, clear the status register before continuing operations ? only the clear status register command clears the status register error bits.
9 AT49BV6416C(t) 3465b?flash?11/04 program suspend/resume flowchart r ead status register sr7 = sr2 = read data program completed done reading program resumed read data 0 no 0 yes 1 1 wr ite ff (read array) wr ite d 0 any address (program resume) wr ite ff (read array) start wr ite b0 any address (program suspend) wr ite 70 any address (read status) the same plane within suspend plane write 70h any address within the same plane (read status) program suspend/re sume procedure bus operation command comments write program suspend data = b0 addr = sector address to suspend (sa) write read status data = 70 addr = any address within the same plane read none status register data: toggle ce or oe to update status register addr = any address idle none check sr7 1 = wsm ready 0 = wsm busy idle none check sr2 1 = program suspended 0 = program completed write read array data = ff addr = any address within the suspended plane read none read data from any sector in the memory other than the one being programmed write program resume data = d0 addr = any address if the suspend plane was placed in read mode: write read status return plane to status mode: data = 70 addr = any address within the same plane
10 AT49BV6416C(t) 3465b?flash?11/04 erase suspend/resume flowchart erase completed read array data 0 0 1 1 start read status r egister sr7 = sr6 = er ase resumed done? r ead read or program? wr ite 70, any addr ess (read status) wr ite b 0, any addr ess (erase suspend) wr ite d 0, any addr ess (e rase re sum e) wri te ff (read a rray) no yes program loop write 70h any address within the same plane (read status) erase suspend/resume procedure bus operation command comments write erase suspend data = b0 addr = any address within the same plane write read status data = 70 addr = any address read none status register data: toggle ce or oe to update status register addr = any address within the same plane idle none check sr7 1 = wsm ready 0 = wsm busy idle none check sr6 1 = erase suspended 0 = erase completed write read or program data = ff or 40 addr = any address read or write none read or program data from/to sector other than the one being erased write program resume data = d0 addr = any address if the suspended plane was placed in read mode or a program loop: write read status return plane to status mode: data = 70 addr = any address within the same plane
11 AT49BV6416C(t) 3465b?flash?11/04 sector erase flowchart full erase status check flowchart start no suspend erase 1 0 yes suspend erase loop write 2 0, addr ess write d0, addr ess read status r egister sr7 = full erase status check (if desired) erase complete (erase) (erase confirm) sector sector sector sector 0 0 0 1 1,1 1 1 0 read status r egister erase successful sr1 = sector sector locked error sr3 = v pp range error sr4, sr5 = command sequence er r or sr5 = erase error sector sector erase procedure full erase status check procedure bus operation command comments write sector erase setup data = 20 addr = sector to be erased (sa) write erase confirm data = d0 addr = sector to be erased (sa) read none status register data: toggle ce or oe to update status register data idle none check sr7 1 = wsms ready 0 = wsms busy repeat for subsequent sector erasures. full status register check can be done after each sector erase, or after a sequence of sector erasures. write ff after the last operation to enter read mode. bus operation command comments idle none check sr3: 1 = v pp range error idle none check sr4, sr5: both 1 = command sequence error idle none check sr5: 1 = sector erase error idle none check sr1: 1 = attempted erase of locked sector; erase aborted. sr1, sr3 must be cleared before the write state machine allows further erase attempts. only the clear status register command clears sr1, sr3, sr4, sr5. if an error is detected, clear the status register before attempting an erase retry or other error recovery.
12 AT49BV6416C(t) 3465b?flash?11/04 protection register programming flowchart full status check flowchart 1 0 start write c0, pr address write pr address & data read status register sr7 = full status check (if desir ed) pr ogram complete (program setup) (confirm data) 0, 1 1, 1 read status register data pr ogram successful = v pp range error program er ror register locked; program aborted 0 0 sr1, sr4 sr1, sr4 sr3, sr4 = 0 = 1, 1 protection register programming procedure full status check procedure bus operation command comments write program pr setup data = c0 addr = first location to program write protection program data = data to program addr = location to program read none status register data: toggle ce or oe to update status register data idle none check sr7 1 = wsms ready 0 = wsms busy program protection register operation addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program, or after a sequence of program operations. write ff after the last operation to return to the read mode. bus operation command comments idle none check sr1, sr3, sr4: 0,1,1 = v pp range error idle none check sr1, sr3, sr4: 0,0,1 = programming error idle none check sr1, sr3, sr4: 1, 0,1 = sector locked; operation aborted sr3 must be cleared before the write state machine allows further program attempts. only the clear status register command clears sr1, sr3, sr4. if an error is detected, clear the status register before attempting a program retry or other error recovery.
13 AT49BV6416C(t) 3465b?flash?11/04 notes: 1. the data format shown for each bus cycle is as follows; i/o7 - i/o0 (hex). i/o15 - i/o8 are don?t care. the address for mat shown for each bus cycle is as follows: a7 - a0 (hex). address a21 through a8 are don?t care. 2. pa is the plane address (a21 - a20). any address within a plane can be used. 3. sa = sector address. any word address within a sector can be used to designate the sector address (see pages 15 - 18 for deta ils). 4. the first bus cycle address should be the same as the word address to be programmed. 5. this fast programming option enables the user to program two words in parallel only when v pp = 12v. the addresses, addr0 and addr1, of the two words, d in0 and d in1 , must only differ in address a0. this command should be used during manufacturing purposes only. 6. during the second bus cycle, the manufacturer code is read from address pa+00000h, the device code is read from address pa+00 001h, and the data in the protection register is read from addresses 000081h - 000088h. 7. the plane address should be the same during the first and second bus cycle. 8. the status register bits are output on i/o7 - i/o0. 9. any address within the user programmable protection register r egion. please see ?protection r egister addressing table? on pag e 14 10. for the AT49BV6416C, xxxx = 0000h. for the AT49BV6416Ct, xxxx = 3f80h. 11. if data bit d1 is ?0?, sector b is locked. if data bit d1 is ?1?, sector b can be reprogrammed. command definition hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle addr data addr data addr data read 1 pa (2) ff chip erase 2 xx 21 addr d0 plane erase 2 xx 22 addr d0 sector erase 2 sa (3) 20 sa (3) d0 word program 2 addr (4) 40/10 addr (4) d in dual word program (5) 3 addr0 e0 addr0 d in0 addr1 d in1 erase/program suspend 1 xx b0 erase/program resume 1 pa (2) d0 product id entry (6)(7) 1pa (2) 90 sector softlock 2 sa (3) 60 sa (3) 01 sector hardlock 2 sa (3) 60 sa (3) 2f sector unlock 2 sa (3) 60 sa (3) d0 read status register 2 pa (2) 70 pa (7) d out (8) clear status register 1 xx 50 program protection register? block b 2 xxxx (10) 8x (9) c0 xxxx (10) 8x (9) d in lock protection register ? sector b 2 xxxx80 (10) c0 xxxx80 (10) fffd status of sector b protection 2 xxxx80 (10) 90 xxxx80 (10) d out (11) cfi query 1 xx 98
14 AT49BV6416C(t) 3465b?flash?11/04 notes: 1. for the AT49BV6416C, all address lines not specified in the above table, a21 - a8, must be 0 when accessing the protect ion register. 2. for the AT49BV6416Ct, all address lines not specified in the table, a21 - a8, must be 3f80h when accessing the protection reg ister. absolute maximum ratings* temperature under bias ................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages except v pp (including nc pins) with respect to ground .....................................-0.6v to +2.5v v pp input voltage with respect to ground ......................................... 0v to 12.5v all output voltages with respect to ground ...........................-0.6v to v ccq + 0.6v protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0factorya10000001 1factorya10000010 2factorya10000011 3factorya10000100 4userb10000101 5userb10000110 6userb10000111 7userb10001000
15 AT49BV6416C(t) 3465b?flash?11/04 memory organization ? AT49BV6416C plane sector size (words) x16 address range (a21 - a0) a sa0 4k 00000 - 00fff a sa1 4k 01000 - 01fff a sa2 4k 02000 - 02fff a sa3 4k 03000 - 03fff a sa4 4k 04000 - 04fff a sa5 4k 05000 - 05fff a sa6 4k 06000 - 06fff a sa7 4k 07000 - 07fff a sa8 32k 08000 - 0ffff a sa9 32k 10000 - 17fff a sa10 32k 18000 - 1ffff a sa11 32k 20000 - 27fff a sa12 32k 28000 - 2ffff a sa13 32k 30000 - 37fff a sa14 32k 38000 - 3ffff a sa15 32k 40000 - 47fff a sa16 32k 48000 - 4ffff a sa17 32k 50000 - 57fff a sa18 32k 58000 - 5ffff a sa19 32k 60000 - 67fff a sa20 32k 68000 - 6ffff a sa21 32k 70000 - 77fff a sa22 32k 78000 - 7ffff a sa23 32k 80000 - 87fff a sa24 32k 88000 - 8ffff a sa25 32k 90000 - 97fff a sa26 32k 98000 - 9ffff a sa27 32k a0000 - a7fff a sa28 32k a8000 - affff a sa29 32k b0000 - b7fff a sa30 32k b8000 - bffff a sa31 32k c0000 - c7fff a sa32 32k c8000 - cffff a sa33 32k d0000 - d7fff a sa34 32k d8000 - dffff a sa35 32k e0000 - e7fff a sa36 32k e8000 - effff a sa37 32k f0000 - f7fff a sa38 32k f8000 - fffff b sa39 32k 100000 - 107fff b sa40 32k 108000 - 10ffff b sa41 32k 110000 - 117fff b sa42 32k 118000 - 11ffff b sa43 32k 120000 - 127fff b sa44 32k 128000 - 12ffff b sa45 32k 130000 - 137fff b sa46 32k 138000 - 13ffff b sa47 32k 140000 - 147fff b sa48 32k 148000 - 14ffff b sa49 32k 150000 - 157fff b sa50 32k 158000 - 15ffff b sa51 32k 160000 - 167fff b sa52 32k 168000 - 16ffff b sa53 32k 170000 - 177fff b sa54 32k 178000 - 17ffff b sa55 32k 180000 - 187fff b sa56 32k 188000 - 18ffff b sa57 32k 190000 - 197fff b sa58 32k 198000 - 19ffff b sa59 32k 1a0000 - 1a7fff b sa60 32k 1a8000 - 1affff b sa61 32k 1b0000 - 1b7fff b sa62 32k 1b8000 - 1bffff b sa63 32k 1c0000 - 1c7fff b sa64 32k 1c8000 - 1cffff b sa65 32k 1d0000 - 1d7fff b sa66 32k 1d8000 - 1dffff b sa67 32k 1e0000 - 1e7fff b sa68 32k 1e8000 - 1effff b sa69 32k 1f0000 - 1f7fff b sa70 32k 1f8000 - 1fffff c sa71 32k 200000 - 207fff c sa72 32k 208000 - 20ffff c sa73 32k 210000 - 217fff c sa74 32k 218000 - 21ffff c sa75 32k 220000 - 227fff c sa76 32k 228000 - 22ffff c sa77 32k 230000 - 237fff c sa78 32k 238000 - 23ffff c sa79 32k 240000 - 247fff c sa80 32k 248000 - 24ffff c sa81 32k 250000 - 257fff c sa82 32k 258000 - 25ffff c sa83 32k 260000 - 267fff c sa84 32k 268000 - 26ffff c sa85 32k 270000 - 277fff c sa86 32k 278000 - 27ffff c sa87 32k 280000 - 287fff c sa88 32k 288000 - 28ffff c sa89 32k 290000 - 297fff memory organization ? AT49BV6416C (continued) plane sector size (words) x16 address range (a21 - a0)
16 AT49BV6416C(t) 3465b?flash?11/04 c sa90 32k 298000 - 29ffff c sa91 32k 2a0000 - 2a7fff c sa92 32k 2a8000 - 2affff c sa93 32k 2b0000 - 2b7fff c sa94 32k 2b8000 - 2bffff c sa95 32k 2c0000 - 2c7fff c sa96 32k 2c8000 - 2cffff c sa97 32k 2d0000 - 2d7fff c sa98 32k 2d8000 - 2dffff c sa99 32k 2e0000 - 2e7fff c sa100 32k 2e8000 - 2effff c sa101 32k 2f0000 - 2f7fff c sa102 32k 2f8000 - 2fffff d sa103 32k 300000 - 307fff d sa104 32k 308000 - 30ffff d sa105 32k 310000 - 317fff d sa106 32k 318000 - 31ffff d sa107 32k 320000 - 327fff d sa108 32k 328000 - 32ffff d sa109 32k 330000 - 337fff d sa110 32k 338000 - 33ffff d sa111 32k 340000 - 347fff memory organization ? AT49BV6416C (continued) plane sector size (words) x16 address range (a21 - a0) d sa112 32k 348000 - 34ffff d sa113 32k 350000 - 357fff d sa114 32k 358000 - 35ffff d sa115 32k 360000 - 367fff d sa116 32k 368000 - 36ffff d sa117 32k 370000 - 377fff d sa118 32k 378000 - 37ffff d sa119 32k 380000 - 387fff d sa120 32k 388000 - 38ffff d sa121 32k 390000 - 397fff d sa122 32k 398000 - 39ffff d sa123 32k 3a0000 - 3a7fff d sa124 32k 3a8000 - 3affff d sa125 32k 3b0000 - 3b7fff d sa126 32k 3b8000 - 3bffff d sa127 32k 3c0000 - 3c7fff d sa128 32k 3c8000 - 3cffff d sa129 32k 3d0000 - 3d7fff d sa130 32k 3d8000 - 3dffff d sa131 32k 3e0000 - 3e7fff d sa132 32k 3e8000 - 3effff d sa133 32k 3f0000 - 3f7fff d sa134 32k 3f8000 - 3fffff memory organization ? AT49BV6416C (continued) plane sector size (words) x16 address range (a21 - a0)
17 AT49BV6416C(t) 3465b?flash?11/04 memory organization ? AT49BV6416Ct plane sector size (words) x16 address range (a21 - a0) d sa0 32k 00000 - 07fff d sa1 32k 08000 - 0ffff d sa2 32k 10000 - 17fff d sa3 32k 18000 - 1ffff d sa4 32k 20000 - 27fff d sa5 32k 28000 - 2ffff d sa6 32k 30000 - 37fff d sa7 32k 38000 - 3ffff d sa8 32k 40000 - 47fff d sa9 32k 48000 - 4ffff d sa10 32k 50000 - 57fff d sa11 32k 58000 - 5ffff d sa12 32k 60000 - 67fff d sa13 32k 68000 - 6ffff d sa14 32k 70000 - 77fff d sa15 32k 78000 - 7ffff d sa16 32k 80000 - 87fff d sa17 32k 88000 - 8ffff d sa18 32k 90000 - 97fff d sa19 32k 98000 - 9ffff d sa20 32k a0000 - a7fff d sa21 32k a8000 - affff d sa22 32k b0000 - b7fff d sa23 32k b8000 - bffff d sa24 32k c0000 - c7fff d sa25 32k c8000 - cffff d sa26 32k d0000 - d7fff d sa27 32k d8000 - dffff d sa28 32k e0000 - e7fff d sa29 32k e8000 - effff d sa30 32k f0000 - f7fff d sa31 32k f8000 - fffff c sa32 32k 100000 - 107fff c sa33 32k 108000 - 10ffff c sa34 32k 110000 - 117fff c sa35 32k 118000 - 11ffff c sa36 32k 120000 - 127fff c sa37 32k 128000 - 12ffff c sa38 32k 130000 - 137fff c sa39 32k 138000 - 13ffff c sa40 32k 140000 - 147fff c sa41 32k 148000 - 14ffff c sa42 32k 150000 - 157fff c sa43 32k 158000 - 15ffff c sa44 32k 160000 - 167fff c sa45 32k 168000 - 16ffff c sa46 32k 170000 - 177fff c sa47 32k 178000 - 17ffff c sa48 32k 180000 - 187fff c sa49 32k 188000 - 18ffff c sa50 32k 190000 - 197fff c sa51 32k 198000 - 19ffff c sa52 32k 1a0000 - 1a7fff c sa53 32k 1a8000 - 1affff c sa54 32k 1b0000 - 1b7fff c sa55 32k 1b8000 - 1bffff c sa56 32k 1c0000 - 1c7fff c sa57 32k 1c8000 - 1cffff c sa58 32k 1d0000 - 1d7fff c sa59 32k 1d8000 - 1dffff c sa60 32k 1e0000 - 1e7fff c sa61 32k 1e8000 - 1effff c sa62 32k 1f0000 - 1f7fff c sa63 32k 1f8000 - 1fffff b sa64 32k 200000 - 207fff b sa65 32k 208000 - 20ffff b sa66 32k 210000 - 217fff b sa67 32k 218000 - 21ffff b sa68 32k 220000 - 227fff b sa69 32k 228000 - 22ffff b sa70 32k 230000 - 237fff b sa71 32k 238000 - 23ffff b sa72 32k 240000 - 247fff b sa73 32k 248000 - 24ffff b sa74 32k 250000 - 257fff b sa75 32k 258000 - 25ffff b sa76 32k 260000 - 267fff b sa77 32k 268000 - 26ffff b sa78 32k 270000 - 277fff b sa79 32k 278000 - 27ffff b sa80 32k 280000 - 287fff b sa81 32k 288000 - 28ffff b sa82 32k 290000 - 297fff b sa83 32k 298000 -29ffff b sa84 32k 2a0000 - 2a7fff b sa85 32k 2a8000 - 2affff b sa86 32k 2b0000 - 2b7fff b sa87 32k 2b8000 - 2bffff memory organization ? AT49BV6416Ct (continued) plane sector size (words) x16 address range (a21 - a0)
18 AT49BV6416C(t) 3465b?flash?11/04 b sa88 32k 2c0000 - 2c7fff b sa89 32k 2c8000 - 2cffff b sa90 32k 2d0000 - 2d7fff b sa91 32k 2d8000 - 2dffff b sa92 32k 2e0000 - 2e7fff b sa93 32k 2e8000 - 2effff b sa94 32k 2f0000 - 2f7fff b sa95 32k 2f8000 - 2fffff a sa96 32k 300000 - 307fff a sa97 32k 308000 - 30ffff a sa98 32k 310000 - 317fff a sa99 32k 318000 - 31ffff a sa100 32k 320000 - 327fff a sa101 32k 328000 - 32ffff a sa102 32k 330000 - 337fff a sa103 32k 338000 - 33ffff a sa104 32k 340000 - 347fff a sa105 32k 348000 - 34ffff a sa106 32k 350000 - 357fff a sa107 32k 358000 - 35ffff a sa108 32k 360000 - 367fff a sa109 32k 368000 - 36ffff a sa110 32k 370000 - 377fff a sa111 32k 378000 - 37ffff memory organization ? AT49BV6416Ct (continued) plane sector size (words) x16 address range (a21 - a0) a sa112 32k 380000 - 387fff a sa113 32k 388000 - 38ffff a sa114 32k 390000 - 397fff a sa115 32k 398000 - 39ffff a sa116 32k 3a0000 - 3a7fff a sa117 32k 3a8000 - 3affff a sa118 32k 3b0000 - 3b7fff a sa119 32k 3b8000 - 3bffff a sa120 32k 3c0000 - 3c7fff a sa121 32k 3c8000 - 3cffff a sa122 32k 3d0000 - 3d7fff a sa123 32k 3d8000 - 3dffff a sa124 32k 3e0000 - 3e7fff a sa125 32k 3e8000 - 3effff a sa126 32k 3f0000 - 3f7fff a sa127 4k 3f8000 - 3f8fff a sa128 4k 3f9000 - 3f9fff a sa129 4k 3fa000 - 3fafff a sa130 4k 3fb000 - 3fbfff a sa131 4k 3fc000 - 3fcfff a sa132 4k 3fd000 - 3fdfff a sa133 4k 3fe000 - 3fefff a sa134 4k 3ff000 - 3fffff memory organization ? AT49BV6416Ct (continued) plane sector size (words) x16 address range (a21 - a0)
19 AT49BV6416C(t) 3465b?flash?11/04 notes: 1. x can be vil or vih. 2. refer to ac programming waveforms. 3. manufacturer code: 001fh; device code: 00c5h ? AT49BV6416C; 00dfh ? AT49BV6416Ct 4. the vpp pin can be tied to v cc . for faster program/erase operations, v pp can be set to 12.0v 0.5v. 5. v ihpp (min) = 1.65v. 6. v ilpp (max) = 0.7v. dc and ac operating range AT49BV6416C(t)-70 operating temperature (case) industrial -40c - 85c v cc power supply 2.7v - 3.6v operating modes mode ce oe we reset v pp (4) ai i/o read v il v il v ih v ih xai d out program/erase (3) v il v ih v il v ih v ihpp (5) ai d in standby/program inhibit v ih x (1) xv ih x x high z program inhibit xxv ih v ih x xv il xv ih x xxx x v ilpp (6) output disable x v ih xv ih x high z reset x x x v il x x high z product identification software v ih a0 = v il , a1 - a21 = v il manufacturer code (3) a0 = v ih , a1 - a21 = v il device code (3)
20 AT49BV6416C(t) 3465b?flash?11/04 note: 1. in the erase mode, i cc is 35 ma. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 1a i lo output leakage current v i/o = 0v to v cc 1a i sb1 v cc standby current cmos ce = v ccq - 0.3v to v cc 35 a i cc (1) v cc active current f = 5 mhz; i out = 0 ma 30 ma i ccre v cc read while erase current f = 5 mhz; i out = 0 ma 60 ma i ccrw v cc read while write current f = 5 mhz; i out = 0 ma 60 ma v il input low voltage 0.6 v v ih input high voltage v ccq - 0.6 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -100 a; v ccq = 2.2v - 3.6v v ccq - 0.1 v ac driving levels 2.0v 0.6v 1.5v ac measurement level v 1.8k output pin 30 pf 1.3k ccq pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 46 pf v in = 0v c out 812 pf v out = 0v
21 AT49BV6416C(t) 3465b?flash?11/04 asynchronous read cycle waveform (1)(2)(3) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). ac asynchronous read timing characteristics symbol parameter min max units t rc read cycle time 70 ns t acc access, address to data valid 70 ns t ce access, ce to data valid 70 ns t oe oe to data valid 20 ns t df ce , oe high to data float 25 ns t oh output hold from oe , ce or address, whichever occurs first 0 ns t ro reset to output delay 150 ns output valid i/o0 - i/o15 high z reset oe t oe t ce address valid t df t oh t acc t ro ce a0 - a21 t rc
22 AT49BV6416C(t) 3465b?flash?11/04 page read cycle waveform ac asynchronous read timing characteristics symbol parameter min max units t acc access, address to data valid 70 ns t ce access, ce to data valid 70 ns t oe oe to data valid 20 ns t df ce , oe high to data float 25 ns t ro reset to output delay 150 ns t pa a page address access time 20 ns t ce t acc t df t df data valid ce i/o0-i/o15 a2 -a21 oe t oe reset t ro t acc a0 -a1 t pa a
23 AT49BV6416C(t) 3465b?flash?11/04 ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min max units t as address setup time to we and ce high 50 ns t ah address hold time 0 ns t ds data setup time 50 ns t dh data hold time 0 ns t wp ce or we low pulse width 35 ns t wph ce or we high pulse width 25 ns i/o0 - i/o15 a0 - a21 we ce data valid i/o0 - i/o15 a0 - a21 ce data va l i d we
24 AT49BV6416C(t) 3465b?flash?11/04 program cycle waveforms sector, plane or chip erase cycle waveforms notes: 1. any address can be used to load data. 2. oe must be high only when we and ce are both low. 3. the data can be 40h or 10h. 4. for chip erase, any address can be used. for plane erase or sector erase, the address depends on what plane or sector is to be erased. 5. for chip erase, the data should be 21h, for plane erase, the data should be 22h, and for sector erase, the data should be 20h. program cycle characteristics symbol parameter min typ max units t bp word programming time 15 s t sec1 sector erase cycle time (4k word sectors) 200 ms t sec2 sector erase cycle time (32k word sectors) 700 ms t es erase suspend time 15 s t ps program suspend time 10 s t eres delay between erase resume and erase suspend 500 s oe program cycle input data note 3 address t bp t wp ce we a0 - a21 i/o0 - i/o15 t wph t as t ah t dh t ds t wc xx (1) (2) oe (2) d0 xx (1) word 0 word 1 note 4 t wph t wp ce we a0 - a21 t as t ah t sec1/2 t dh t ds t wc i/o0 - i/o15 note 5
25 AT49BV6416C(t) 3465b?flash?11/04 table 5. common flash interface definition for AT49BV6416C(t) address AT49BV6416Ct AT49BV6416C comments 10h 0051h 0051h ?q? 11h 0052h 0052h ?r? 12h 0059h 0059h ?y? 13h 0003h 0003h 14h 0000h 0000h 15h 0041h 0041h 16h 0000h 0000h 17h 0000h 0000h 18h 0000h 0000h 19h 0000h 0000h 1ah 0000h 0000h 1bh 0027h 0027h vcc min write/erase 1ch 0036h 0036h vcc max write/erase 1dh 00b5h 00b5h vpp min voltage 1eh 00c5h 00c5h vpp max voltage 1fh 0004h 0004h typ word write ? 15 s 20h 0000h 0000h 21h 0009h 0009h typ block erase ? 500 ms 22h 0010h 0010h typ chip erase ? 64,300 ms 23h 0004h 0004h max word write/typ time 24h 0000h 0000h n/a 25h 0003h 0003h max block erase/typ block erase 26h 0003h 0003h max chip erase/ typ chip erase 27h 0017h 0017h device size 28h 0001h 0001h x16 device 29h 0000h 0000h x16 device 2ah 0000h 0000h multiple byte write not supported 2bh 0000h 0000h multiple byte write not supported 2ch 0002h 0002h 2 regions, x = 2 2dh 007eh 0007h 64k bytes, y = 126 (top); 8k bytes, y = 7 (bottom) 2eh 0000h 0000h 64k bytes, y = 126 (top); 8k bytes, y = 7 (bottom) 2fh 0000h 0020h 64k bytes, z = 256 (top); 8k bytes, z = 32 (bottom) 30h 0001h 0000h 64k bytes, z = 256 (top); 8k bytes, z = 32 (bottom) 31h 0007h 007eh 8k bytes, y = 7 (top); 64k bytes, y = 126 (bottom) 32h 0000h 0000h 8k bytes, y = 7 (top); 64k bytes, y = 126 (bottom) 33h 0020h 0000h 8k bytes, z = 32 (top);64k bytes, z = 256 (bottom) 34h 0000h 0001h 8k bytes, z = 32 (top);64k bytes, z = 256 (bottom)
26 AT49BV6416C(t) 3465b?flash?11/04 vendor specific extended query 41h 0050h 0050h ?p? 42h 0052h 0052h ?r? 43h 0049h 0049h ?i? 44h 0031h 0031h major version number, ascii 45h 0030h 0030h minor version number, ascii 46h 00afh 00afh bit 0 ? chip erase supported, 0 ? no, 1 ? yes bit 1 ? erase suspend supported, 0 ? no, 1 ? yes bit 2 ? program suspend supported, 0 ? no, 1 ? yes bit 3 ? simultaneous operations supported, 0 ? no, 1 ? yes bit 4 ? burst mode read supported, 0 ? no, 1 ? yes bit 5 ? page mode read supported, 0 ? no, 1 ? yes bit 6 ? queued erase supported, 0 ? no, 1 ? yes bit 7 ? protection bits supported, 0 ? no, 1 ? yes 47h 0000h 0001h bit 0 ? top (?0?) or bottom (?1?) boot block device undefined bits are ?0? 48h 0000h 0000h bit 0 ? 4 word linear burst with wrap around, 0 ? no, 1 ? yes bit 1 ? 8 word linear burst with wrap around, 0 ? no, 1 ? yes bit 2 ? 16 word linear burst with wrap around, 0 ? no, 1 ? yes bit 3 ? continuous burst, 0 ? no, 1 ? yes undefined bits are ?0? 49h 0001h 0001h bit 0 ? 4 word page, 0 ? no, 1 ? yes bit 1 ? 8 word page, 0 ? no, 1 ? yes undefined bits are ?0? 4ah 0080h 0080h location of protection register lock byte, the section?s first byte 4bh 0003h 0003h # of bytes in the factory prog section of prot register ? 2*n 4ch 0003h 0003h # of bytes in the user prog section of prot register ? 2*n table 5. common flash interface definition for AT49BV6416C(t) (continued) address AT49BV6416Ct AT49BV6416C comments
27 AT49BV6416C(t) 3465b?flash?11/04 AT49BV6416C(t) ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 30 0.035 AT49BV6416C-70ci 48c20 industrial (-40 to 85 c) 70 30 0.035 AT49BV6416Ct-70ci 48c20 industrial (-40 to 85 c) package type 48c20 48-ball, plastic chip-size ball grid array package (cbga)
28 AT49BV6416C(t) 3465b?flash?11/04 packaging information ? AT49BV6416C(t) 48c20 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 48c20 , 48-ball (8 x 6 array),0.75 mm pitch, 7.0 x 10.0 x 1.0 mm chip-scale ball grid array package (cbga) a 48c20 01/8/04 a1 ball id a b c d e f 7 65432 1 d e e1 e 0.875 ref a1 ball corner 3.125 ref d1 8 a a1 common dimensions (unit of measure = mm) symbol min nom max note e 6.90 7.00 7.10 e1 5.25 typ d 9.90 10.00 10.10 d1 3.75 typ a ? ? 1.0 a1 0.21 ? ? e 0.75 bsc ? b 0.35 typ bottom view ? b top view side view
29 AT49BV6416C(t) 3465b?flash?11/04 revision history revision no. history revision a ? april 2004 ? initial release revision b ? november 2004 ? removed ?preliminary? from the datasheet. ? modified note 6 and added notes 7 and 10 on page 13. ? removed note 1 and added note 2 on page 14. ? changed the i sb1 spec to 35 a.
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