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4-bit single-chip microcomputer ? nec corporation 1993 description the m pd75p336 is a version of the m pd75336 in which the on-chip mask rom is replaced by one-time prom. as the m pd75p336 is user-programmable, it is suitable for preproduction in system development, and for short-run and multiple device-production. detailed function description, etc. are described in the following user's manual. be sure to read it when designing. m pd75336 user's manual: ieu-725 features m pd75336 compatible memory capacity: ? prom : 16256 8 bits ? ram : 768 4 bits operable over same supply voltage range as mask rom m pd75336 ?v dd = 2.7 to 6.0 v on-chip 8-bits resolution a/d converter (successive approximation type) on-chip lcd controller/driver ordering information ordering code package quality grade m pd75p336gc-3b9 80-pin plastic qfp ( 14mm) standard m pd75p336gk-be9 80-pin plastic tqfp (fine pitch)( 12mm) standard note pull-up resistor cannot be incorporated by mask option. the information in this document is subject to change without notice. mos integrated circuit m pd75p336 data sheet document no. ic-2980a (o. d. no. ic-8371a) date published october 1993p printed in japan the mark h shows major revised points. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. h
2 m pd75p336 block diagram program counter (15) program memory (rom) 16256 8 bits lcd control- ler /driver s12-s23 s24/bp0 ?31/bp7 com0?om3 v lc0 ? lc2 bias lcdcl/p30 sync/p31 f lcd port 4 4 4 p00-p03 p20-p23 4 p10-p13 4 p30-p33 /md0-md3 4 p40-p43 port 5 4 p50-p53 port 6 4 p60-p63 port 7 4 p70-p73 port 8 4 p80-p83 general reg. data memory (ram) 768 4 bits bank sp(8) alu cy decode and control reset v ss v dd cpu clock v pp stand by control system clock generator sub main clock divider clock output control x2 x1 xt2 xt1 pcl/p22 f x / 2 n a/d convert- er timer/event counter #0 watch timer clocked serial interface inter- rupt control bit seq. buffer (16) intcsi intw f lcd intt0 kr0/p60 ?r3/p63 int4/p00 int2/p12 int1/p11 int0/p10 sck/p01 so/sb0/p02 si/sb1/p03 buz/p23 ti0/p13 pto0/p20 basic interval timer intbt timer/event counter #1 intt1 ti1/p80 pto1/p21 av ref port 3 port 2 port 1 port0 12 8 4 3 an0-an7 * av ss kr4/p70 ?r7/p73 8 8 * an6/p82, an7/p83
3 m pd75p336 m pd75p336gc-3b9 m pd75p336gk-be9 pin configuration (top view) l l 80-pin plastic qfp ( n n 14mm) l l 80-pin plastic tqfp (fine pitch) ( n n 12mm) * in normal operation, v pp should be connected to v dd directly. h 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 12 s12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 48 47 46 45 44 43 42 41 49 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s24/bp0 s20 s21 s22 an2 p33/md3 p32/md2 p31/sync/md1 p30/lcdcl/md0 p23/buz p22/pcl p21/pto1 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 p73/kr7 x2 reset p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 x1 v pp * xt2 xt1 v dd av ref av ss an5 an4 an3 an1 an0 p83/an7 p82/an6 p81 p80/ti1 s13 s14 s15 s16 s17 s18 s19 s23 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7
4 m pd75p336 p00 to 03 : port 0 p10 to 13 : port 1 p20 to 23 : port 2 p30 to 33 : port 3 p40 to 43 : port 4 p50 to 53 : port 5 p60 to 63 : port 6 p70 to 73 : port 7 p80 to 83 : port 8 bp0 to 7 : bit port kr0 to 7 : key return av ref : analog reference av ss : analog ground an0 to 7 : analog input 0 to 7 sck : serial clock si : serial input so : serial output md0 to 3 : mode selection v pp : programming/verifying power supply pin name sb0, 1 : serial bus 0,1 reset : reset input s12 to 31 : segment output 12 to 31 com0 to 3 : common output 0 to 3 v lc0 to 2 : lcd power supply 0 to 2 bias : lcd power supply bias control lcdcl : lcd clock sync : lcd synchronization ti0, 1 : timer input 0, 1 pto0, 1 : programmable timer output 0, 1 buz : buzzer clock pcl : programmable clock int0, 1, 4 : external vectored interrupt 0, 1, 4 int2 : external test interrupt 2 x1, 2 : main system clock oscillation 1, 2 xt1, 2 : subsystem clock oscillation 1, 2 v dd : positive power supply v ss : ground
5 m pd75p336 contents 1. pin functions ......................................................................................................................................... 6 1.1 port pins ............................................................................................................................................................. 6 1.2 other pins .......................................................................................................................................................... 8 1.3 pin input/output circuits ...........................................................................................................................10 2. differences between m pd75p336 and m pd75336 ......................................................................... 13 2.1 program memory (prom) 16256 words 8 bits .................................................................................. 14 2.2 data memory (ram) 768 words 4 bits .................................................................................................. 15 3. instruction set and instruction operations ....................................................................... 16 4. one-time prom (program memory) write and verify operations .................................. 25 4.1 program memory write/verify operating modes ........................................................................... 26 4.2 program memory write procedure ....................................................................................................... 27 4.3 program memory read procedure ......................................................................................................... 28 5. electrical specifications ................................................................................................................ 29 6. package information ........................................................................................................................ 48 7. recommended soldering conditions ......................................................................................... 50 appendix a. list of functions .............................................................................................................. 51 appendix b. development tools ......................................................................................................... 52
6 m pd75p336 input input/output input/output input/output input input/output input/output input/output input/output p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 *2 p31 *2 p32 *2 p33 *2 p40 to p43 *2 p50 to p53 *2 p60 p61 p62 p63 p70 p71 p72 p73 dual- function pin int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 pto1 pcl buz lcdcl md0 sync md1 md2 md3 kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 i/o circuit type *1 b f - a f - b m - c b - c e - b e - b m - b m - b f - a f - a 4-bit input port (port0) internal pull-up resistor specification by software is possible for p01 to p03 as a 3-bit unit. 4-bit input port (port1) internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (port2) internal pull-up resistor specification by software is possible as a 4-bit unit. programmable 4-bit input/output port (port3) input/output settable bit-wise. internal pull-up resistor specification by software is possible as a 4-bit unit. n-ch open-drain 4-bit input/output port (port 4). data input/output pins for program memory (prom) write/verify (low-order 4 bits). n-ch open-drain 4-bit input/output port (port 5) data input/output pins for program memory (prom) write/verify (high-order 4 bits). programmable 4-bit input/output port (port6). input/output settable bit-wise. internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (port7). internal pull-up resistor specification by software is possible as a 4-bit unit. with noise elimination circuit pin name input/output function 8-bit i/o input/output input/output *1. : indicates a schmitt-triggered input. 2 . direct led drive capability. input input input input input input input input 1. pin functions 1.1 port pins (1/2) after reset
7 m pd75p336 1.1 port pins (2/2) p80 p81 p82 p83 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 dual- function pin ti1 an6 an7 s24 s25 s26 s27 s28 s29 s30 s31 i/o circuit type e - e e - b y - b g - c input * 4-bit input/output port (port8). internal pull-up resistor specification by software is possible as a 4-bit unit. 1-bit output port (bit port) dual function as segment output pins. input/output output output pin name input/output function 8-bit i/o after reset * v lcx shown below can be selected for the display outputs. s12 to s31: v lc1 , com0 to com2: v lc2 , com3: v lc0 however, display output levels depend on the display outputs and v lcx external circuit.
8 m pd75p336 b - c b - e e - b e - b e - b f - a f - b m - c b b - c b - c f - a f - a CC b e - b external event pulse input pin for timer/event counter. timer/event counter output pin clock output pin frequency output pin (for buzzer or system clock trimming) serial clock input/output pin serial data output pin serial bus input/output pin serial data input pin serial bus input/output pin edge-detected vectored interrupt input pin (both rising and falling edge detection valid). edge-detected vectored interrupt input pin (detected edge selectable) edge-detected testable input pin (rising edge detection) parallel falling edge detected testable input pins. parallel falling edge detected testable input pins. main system clock oscillation crystal/ceramic resonator inputs. when an external clock is used, the clock is input to x1 and the inverted clock to x2. subsystem clock oscillation crystal reasonator inputs when an external clock is used, the clock is input to xt1 and the inverted clock toxt2. xt1 can be used as a 1- bit input (test) pin. system reset input pin. mode selection pin for program memory (prom) write/ verify. program voltage application pin for program memory (prom) write/verify. applies +12.5 v in program memory write/verify. directly connected to v dd in normal operation. positive power supply pin gnd potential pin ti0 ti1 pto0 pto1 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0 to kr3 kr4 to kr7 x1, x2 xt1, xt2 reset md0 to md3 v pp v dd v ss clocked asynchronous asynchronous p13 p80 p20 p21 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60 to p63 p70 to p73 p30 to p33 input output output output input/output input/output input/output input input input input input input input/output input input input input input input input input input input input input input i/o circuit type * * : indicates a schmitt-triggered input. pin name input/output dual- function pin function 1.2 other pins (1/2) after reset
9 m pd75p336 g - a g - c g - b e - b e - b y y - b z z 1.2 other pins (2/2) input/output function s12 to s23 s24 to s31 com0 to com3 v lc0 to v lc2 bias lcdcl *1 sync *1 an0 to an5 an6 an7 av ref av ss *1 . pins provided for future system expansion. currently used only as pins 30 and 31. 2 .v lcx shown below can be selected for the display outputs. s12 to s31: v lc1 , com0 to com2: v lc2 , com3:v lc0 however, display output levels depend on the display outputs and v lcx external circuit. output output output input output output output input input bp0 to 7 p30 p31 p82 p83 *2 *2 *2 high impedance input input input segment signal output pins segment signal output pins common signal output pins lcd drive power supply pins external split cutting output pin external extension driver drive clock output pin external extension driver synchronization drive clock output pin a/d converter analog signal input pins a/d converter reference voltage input pin a/d converter gnd potential pin pin name dual- function pin after reset i/o circuit type
10 m pd75p336 1.3 pin input/output circuits the input/output circuits for each of the pin m pd75p336 are shown below in partially simplified form. p-ch v dd out n-ch data output disable cmos standard input buffer push-pull output that can be made high-impedance output (p-ch and n-ch off) type a (for type e-b) type d (for type e-b, f-a) type b type e-b type b-c type e-e schmitt-trigger input with hysteresis characteristic in p-ch p.u.r. p.u.r. enable v dd p.u.r. : pull-up resistor in p-ch v dd in n-ch p.u.r. p-ch in/out output disable data output disable type d type a p.u.r. : pull-up resistor v dd schmitt-trigger input with hysteresis characteristic p.u.r. p-ch in/out p.u.r. enable data output disable type d type a v dd type b p.u.r. : pull-up resistor
11 m pd75p336 type f-b type g-c type g-a type m-b type f-a type g-b p.u.r. p-ch in/out p.u.r. enable data output disable type d type b p.u.r. : pull-up resistor v dd p.u.r. in/out p.u.r. enable output disable (p) output disable data output disable (n) v dd v dd p-ch n-ch p-ch p.u.r. : pull-up resistor n-ch p-ch out seg data p-ch v lc0 v lc1 v lc2 n-ch v lc0 v lc1 v lc2 com data n-ch p-ch p-ch n-ch out n-ch p-ch p-ch v lc0 v lc1 v lc2 p-ch n-ch out seg data/bit port data n-ch v dd in/out n-ch data output disable middle-high voltage input buffer
12 m pd75p336 type y type z type m-c type y-b p.u.r. enable in/out p-ch v dd n-ch data output disable p.u.r. : pull-up resistor p.u.r. + - v dd av ss p-ch n-ch in v dd av ss input enable sampl- ing c reference voltage (from series resistance voltage tap) av ss in reference voltage type y type a in/out data output disable type d p-ch p.u.r:pull-up resistor v dd p.u.r enable
13 m pd75p336 2. differences between m pd75p336 and m pd75336 parameter program memory data memory ports 4, 5 pull-up resistor lcd drive power supply split resistor subsystem clock oscillation feedback resistor pin 69 m pd75336 mask rom 16256 8 bits 768 4 bits incorporation specifiable by mask option incorporation specifiable by mask option incorporation specifiable by mask option ic m pd75p336 one-time prom 16256 8 bits 768 4 bits no no incorporated v pp
14 m pd75p336 2.1 program memory (prom) ..... 16256 words 8 bits the program memory consists of 16256-byte prom. the program memory map is shown in fig. 2-1. fig. 2-1 program memory map ? ? ? ? ? ? ? mbe mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 0fffh 1000h 7 6 0 internal reset start address (high-order 6 bits) (low-order 8 bits) i ntbt/int4 start address (high-order 6 bits) int0 start address (high-order 6 bits) (low-order 8 bits) (low-order 8 bits) int1 start address (high-order 6 bits) (low-order 8 bits) intt0 start address (high-order 6 bits) (low-order 8 bits) geti instruction reference table callf !faddr instruction entry address brcb !caddr instruction branch address call !addr instruction branch address br !addr instruction branch address branch/call address, by geti brcb !caddr instruction branch address ? rbe rbe mbe rbe (low-order 8 bits) mbe rbe intcsi start address (high-order 6 bits) mbe rbe intt1 start address (high-order 6 bits) (low-order 8 bits) mbe rbe mbe rbe ? ? ? ? brcb !caddr instruction branch address brcb !caddr instruction branch address br $addr instruction relative branch address (-15 to -1, +2 to +16) 000ch 07ffh 0800h 1fffh 2000h 2fffh 3000h 3f7fh
15 m pd75p336 remarks in addition to the above, branching is possible with the br pcde and br pcxa instructions to addresses with the low-order 8 bits only of the pc modified. 2.2 data memory (ram) .......768 words 4 bits the configuration of the data memory is shown in fig. 2-2. the data memory comprises a data area and peripheral hardware area, the data area comprises 768 4-bit static ram. fig. 2-2 data memory map (20 4) 256 4 256 4 128 4 (32 4) data memory not on-chip memory bank 0 memory bank 1 memory bank 2 256 4 memory bank 15 f80h fffh peripheral hardware area data area static ram 768 4 general register area stack area display data memory area 2ffh 200h 1ffh 1ech 1ebh 100h 0ffh 020h 01fh 000h
16 m pd75p336 description method x, a, b, c, d, e, h, l x, b, c, d, e, h, l xa, bc, de, hl bc, de, hl bc, de xa, bc, de, hl, xa', bc', de' hl' bc, de, hl, xa', bc', de', hl' hl, hl+, hlC, de, dl de, dl 4-bit immediate date or label 8-bit immediate date or label 8-bit immediate date or label * 2-bit immediate date or label 0000h to 3f7fh immediate data or label 12-bit immediate date or label 11-bit immediate date or label 20h to 7fh immediate date (bit 0 = 0) or label port0 to port8 iebt, iecsi, iet0, iet1, ie0 to ie2, ie4, iew rb0 to rb3 mb0, mb1, mb2, mb15 3. instruction set and instruction operations (1) operand identifier and description operand identifiers and description method operands are written in the operand column for each instruction in accordance with the description method for the operand identifier for that instruction (refer to "ra75x assembler package user's manual language volume (eeu-730)" for details). where multiple items are included in the description method, one of those elements should be selected. uppercase letters and the symbols + and C are keywords and should be written as they are. in the case of immediate data, an appropriate number or label is written. descriptor reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit addr caddr faddr taddr portn ie rbn mbn fmem pmem fb0h to fbfh, ff0h to fffh immediate data or label fc0h to fffh immediate data or label * in 8-bit data processing, only an even address can be specified.
17 m pd75p336 (2) operation description legend a : a register; 4-bit accumulator b : b register; 4-bit accumulator c : c register; 4-bit accumulator d : d register; 4-bit accumulator e : e register; 4-bit accumulator h : h register; 4-bit accumulator l : l register; 4-bit accumulator x : x register; 4-bit accumulator xa : register pair (xa); 8-bit accumulator bc : register pair (bc); 8-bit accumulator de : register pair (de); 8-bit accumulator hl : register pair (hl); 8-bit accumulator xa' : extended register pair (xa') bc' : extended register pair (bc') de' : extended register pair (de') hl' : extended register pair (hl') pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : portn (n = 0 to 8) ime : interrupt master enable flag ips : interrupt priority selection register ie : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : address, bit delimiter ( ) : contents addressed by h : hexadecimal data
18 m pd75p336 *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 mb = mbe ? mbs mbs = 0, 1, 2, 15 mb = 0 mbe = 0 : mb = 0 (000h to 07fh) mb = 15 (f80h to fffh) mbe = 1 : mb = mbs (mbs = 0, 1, 2, 15) mb = 15, fmem = fb0h to fbfh, ff0h to fffh mb = 15, pmem = fc0h to fffh addr = 0000h to 3f7fh addr = (current pc) C15 to (current pc) C1 (current pc) + 2 to (current pc) + 16 caddr = 0000h to 0fffh (pc 13,12 = 00b) or 1000h to 1fffh (pc 13,12 = 01b) or 2000h to 2fffh (pc 13,12 = 10b) or 3000h to 3fffh (pc 13,12 = 11b) faddr = 0000h to 07ffh taddr = 0020h to 007fh program memory addressing (3) description of addressing area field symbols remarks 1. mb indicates the accessible memory bank. 2. mb=0 irrespective of mbe and mbs in *2. 3 . mb=15 irrespective of mbe and mbs in *4 and *5. 4. *6 to *10 indicate accessible area. (4) explanation of machine cycle column "s" indicates the number of machine cycles required when an instruction with a skip function performs a skip operation. the value of "s" is as follows: ? when a skip is not performed ....................................................................................................................... s = 0 ? when the skipped instruction is a 1-byte or 2-byte instruction ................................................................ s = 1 ? when the skipped instruction is a 3-byte instruction (br !addr or call !addr) ................................... s = 2 note a geti instruction is skipped in one machine cycle. one machine cycle is equivalent to one cycle (=t cy )of the cpu clock cycle f : any of four times can be selected according to the pcc setting. data memory addressing
19 m pd75p336 mne- monic address- ing area operand operation skip condition 1 2 2 2 2 1 2 + s 2 + s 1 2 1 2 2 2 2 2 2 2 2 2 1 2 + s 2 + s 1 2 2 2 1 2 3 3 a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @hl+ a, @hlC a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp' reg1, a rp'1, xa a, @hl a, @hl+ a, @hlC a, @rpa1 xa, @hl a, mem xa, mem a,reg1 xa, rp' xa, @pcde xa, @pcxa a ? n4 reg1 ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l C 1 a ? (rpa1) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp' reg1 ? a rp'1 ? xa a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l C1 a ? (rpa1) xa ? (hl) a ? (mem) xa ? (mem) a ? reg1 xa ? rp' xa ? (pc 13C8 + de) rom xa ? (pc 13C8 + xa) rom *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *1 *1 *2 *1 *3 *3 transfer 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 bytes machine cycles stack a stack a stack b l = 0 l = fh l = 0 l = fh note 1. instruction group 2. table reference note 1 note 2 mov xch movt
20 m pd75p336 address- ing area operand operation skip condition bytes mne- monic *4 *5 *1 *4 *5 *1 *1 *1 *1 *1 *1 *1 *1 carry carry carry carry carry borrow borrow borrow 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 1 + s 2 + s 1 + s 2 + s 2 + s 1 2 2 1 + s 2 + s 2 + s 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 machine cycles cy, fmem.bit cy, pmem.@l cy, @h + mem.bit fmem.bit, cy pmem.@l, cy @h + mem.bit, cy a, #n4 xa, #n8 a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa cy ? (fmem.bit) cy ? (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? (h + mem 3-0 .bit) (fmem.bit) ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) ? cy (h + mem 3-0 .bit) ? cy a ? a + n4 xa ? xa + n8 a ? a + (hl) xa ? xa + rp' rp'1 ? rp'1 + xa a, cy ? a + (hl) + cy xa, cy ? xa + rp' + cy rp'1, cy ? rp'1 + xa + cy a ? a - (hl) xa ? xa - rp' rp'1 ? rp'1 - xa a , cy ? a - (hl) - cy xa, cy ? xa - rp' - cy rp'1, cy ? rp'1 - xa - cy a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa mov1 adds addc subs sbuc and or xor note instruction group note bit transfer operation
21 m pd75p336 bytes operand operation mne- monic address- ing area skip condition a a reg rp1 @hl mem reg rp' reg, #n4 @hl, #n4 a, @hl xa, @hl a, reg xa, rp' cy cy cy cy cy ? a 0 , a 3 ? cy, a nC1 ? a n a ? a reg ? reg + 1 rp1 ? rp1 + 1 (hl) ? (hl) + 1 (mem) ? (mem) + 1 reg ? reg C 1 rp' ? rp' C 1 skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if xa = (hl) skip if a = reg skip if xa = rp' cy ? 1 cy ? 0 skip if cy = 1 cy ? cy 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1 2 1 + s 1 + s 2 + s 2 + s 1 + s 2 + s 2 + s 2 + s 1 + s 2 + s 2 + s 2 + s 1 1 1 + s 1 *1 *3 *1 *1 *1 machine cycles rorc not incs decs ske set1 clr1 skt not1 reg = 0 rp1 = 00h (hl) = 0 (mem) = 0 reg = fh rp' = ffh reg = n4 (hl) = n4 a = (hl) xa = (hl) a = reg xa = rp' cy = 1 note 1. instruction group 2. accumulator operation 3. increment and decrement 4. carry flag manipulation comparison note 1 note 2 note 3 note 4
22 m pd75p336 operation skip condition operand mne- monic address- ing area bytes mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit fmem.bit pmem.@l @h+mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit addr !addr !caddr $addr pcde pcxa (mem.bit) 1 (fmem.bit) 1 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 1 (h + mem 3C0 .bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 0 (h + mem 3C0 .bit) 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 skip if (h + mem 3C0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 ))= 0 skip if (h + mem 3C0 .bit) = 0 skip if (fmem.bit) = 1 and clear skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 and clear skip if (h + mem 3C0 .bit) = 1 and clear cy cy ? (fmem.bit) cy cy ? (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy cy ? (h + mem 3-0 .bit) cy cy M (fmem.bit) cy cy M (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy cy M (h + mem 3-0 .bit) cy cy M (fmem.bit) cy cy M (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy cy M (h + mem 3-0 .bit) pc 13C0 addr (the assembler selects the optimum instruction from among the brcb !caddr, and br $addr instructions.) pc 13C0 addr pc 13C0 pc 13.12 + caddr 11C0 pc 13C0 addr pc 13C0 pc 13-8 + de pc 13C0 pc 13-8 + xa 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 1 2 2 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 2 2 2 2 2 2 2 2 3 2 2 3 3 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 *6 *8 *7 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 machine cycles set1 clr1 skt skf sktclr and1 or1 xor1 br br brcb br br note instruction group branch note memory bit manipulation
23 m pd75p336 operation skip condition operand mne- monic address- ing area bytes (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, rbe, pc 13.12 pc 13C0 ? addr, sp ? sp C 4 (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, rbe, pc 13.12 pc 13C0 ? 000 + faddr, sp ? sp C 4 mbe, rbe, pc 13.12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 mbe, rbe, pc 13.12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 the skip unconditionally , , pc 13.12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 (sp C 1) (sp C 2) ? rp, sp ? sp C 2 (sp C 1) ? mbs, (sp C 2) ? rbs, sp ? sp C 2 rp ? (sp + 1) (sp), sp ? sp + 2 mbs ? (sp + 1), rbs ? (sp), sp ? sp + 2 ime (ips.3) ? 1 ie ? 1 ime (ips.3) ? 0 ie ? 0 a ? port n (n = 0C8) xa ? port n+1 , port n (n = 4, 6) port n ? a (n = 2C8) port n+1 , port n ? xa (n =4, 6) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation rbs ? n (n = 0C3) mbs ? n (n = 0,1,2,15) ? tbr instruction pc 13C0 ? (taddr) 5C0 + (taddr + 1) ? tcall instruction (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, rbe, pc 13, 12 pc 13C0 ? (taddr) 5C0 ? (taddr + 1) sp ? sp C 4 ? other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) machine cycles subroutine stack control note 1 3 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 !addr !faddr rp bs rp bs ie ie a, portn xa, portn portn, a portn, xa rbn mbn taddr call callf ret rets reti push pop ei di in *1 out *1 halt stop nop sel geti *2 3 2 3 3 + s 3 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 ----------------------------------------------------------------------- ----------------------------------------------------------------------- ----------------------------- ----------------------------- note 2 input/output note 3 special *6 *9 *10 unconditional conforms to referenced instruction.
24 m pd75p336 * 1. at in/out instruction execution, mbe = 0 or mbe = 1, mbs = 15 must be set in advance. 2. tbr and tcall instructions are assembler pseudo-instructions for table definition. note 1. instruction group 2. interruput control 3. cpu control
25 m pd75p336 4. one-time prom (program memory) write and verify operations the program memory incorporated in the m pd75p336 is 32640 8-bit electrically writable one-time prom. write/verify operations on this one-time prom are executed using the pins shown in the table below. address updating is performed by means of clock input from the x1 pin rather than by address input. voltage applecation pin for program memory write/verify (normally v dd potential). address update clock inputs for program memory write/verify. inverse of x1 pin signal is input to x2 pin. operating mode selection pin for program memory write/verify. 8-bit data input/output pins for progrm memory write/verify. supply voltage application pin. applies 2.7 to 6.0 v in normal operation, and 6 v for program memory write/verify. v pp x1, x2 md0 to md3 p40 to p43 (low-order 4 bits) p50 to p53 (high-order 4 bits) v dd note 1. pins not used in a program memory write/verify operation are handled as follows: ? pins other than xt2 .......... connect to v ss with a pull-down resistor ? xt2 pins ............................. leave open 2. since the m pd75p336 is not provided with an erase window, program memory contents cannot be erased with ultra-violet light. 4.1 program memory write/verify operating modes when +6 v is applied to the v dd pin and +12.5 v to the v pp pin, the m pd75p336 enters the program memory write/ verify mode. this mode comprises one of the operating modes shown below according to the setting of pins md0 to md3. v pp +12.5 v v dd +6v md0 h l l h md1 l h l x md2 h h h h md3 l h h h operating mode program memory address zero-clear write mode verify mode program inhibit mode x: l or h operating mode setting function pin name
26 m pd75p336 4.2 program memory write procedure the procedure for writing to program memory is as shown below, allowing high-speed writing. (1) unused pins are connected to v ss with a pull-down resistor. the x1 pin is driven low. (2) 5 v is supplied to the v dd and v pp pins. (3) 10 m s wait. (4) program memory address zero-clear mode. (5) 6 v is supplied to v dd , 12.5 v to v pp . (6) program inhibit mode. (7) data is written in 1 ms write mode. (8) program inhibit mode. (9) verify mode. if write is successful go to (10), otherwise repeat (7) to (9). (10) (number of times written in (7) to (9): x) 1 ms additional writes. (11) program inhibit mode. (12) program memory address is updated (+1) by inputting 4 pulses to the x1 pin. (13) steps (7) to (12) are repeated until the last address. (14) program memory address zero-clear mode. (15) v dd / v pp pin voltage is changed to 5 v. (16) power-off. steps (2) to (12) of this procedure are shown in the figure below. data input data input write verify additional write address increment repeated x times data output v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) ? ? ? ? ? ? ? ?
27 m pd75p336 4.3 program memory read procedure m pd75p336 program memory contents can be read using the following procedure. (1) unused pins are connected to v ss with a pull-down resistor. the x1 pin is driven low. (2) 5 v is supplied to the v dd and v pp pins. (3) 10 m s wait. (4) program memory address zero-clear mode. (5) 6 v supplied to v dd , and 12.5 v to v pp . (6) program inhibit mode. (7) verify mode. when clock pulses are input to the x1 pin, data is output sequentially, one address per 4-pulse-input cycle. (8) program inhibit mode. (9) program memory address zero-clear mode. (10) v dd / v pp pin voltage is changed to 5 v. (11) power-off. steps (2) to (9) of this procedure are shown in the figure below. data output data output v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) ? ? ? ? ? ? ? ? ?
m pd75p336 28 m pd75p336 m pd75304b m pd75p336 5. electrical specifications absolute maximum ratings (ta = 25 c) capacitance (ta = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf peak value effective value peak value effective value peak value effective value 1 pin all pins 1 pin total of ports 0, 2, 3, 5, 18 total of ports 4, 6, 7 output voltage output current high v o i oh ports 4, 5 open-drain v i2 v i1 except ports 4, 5 input voltage power supply voltage v dd v pp C15 C30 30 15 100 60 100 60 C40 to +85 C65 to +150 C0.3 to +11 C0.3 to v dd +0.3 C0.3 to +7.0 C0.3 to +13.5 C0.3 to v dd +0.3 parameter symbol test conditions rating unit v v ma ma ma ma ma ma ma ma c c v v v i ol * output current low operating temperature storage temperature t opt t stg * rms value is calculated from [effective value] = [peak value] ? duty h f = 1 mhz unmeasured pins returned to 0 v.
m pd75p336 29 m pd75p336 m pd75p336 m pd75304b m pd75p336 min. typ. max. unit after v dd reached the min. of the oscillator voltage range. v dd = 4.5 to 6.0 v x1 x1 c2 c1 v dd x1 x1 c2 c1 v dd main system clock oscillator characteristics 1.0 5.0 *3 mhz 4ms 1.0 4.19 5.0 *3 mhz 10 ms 30 ms 1.0 5.0 *3 mhz 100 500 ns esonator recommended constant parameter test conditions oscillator frequency (f x ) *1 oscillation stabilization time *2 oscillator frequency (f x ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 input high-/low-level width (t xh , t xl ) (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) ceramic resonator crystal resonator external clock *1. shows the oscillator characteristics only. for the instruction execution time, see the ac characteristics. 2. time necessary for oscillation to stabilize after v dd applied or stop mode released. 3. when the oscillator frequency is 4.19 mhz < f x 5.0 mhz, it is impossible to select of pcc = 0011 with 1 machine cycle of less than 0.95 m s as instruction execution time. x1 x2 m pd74hcu04
m pd75p336 30 m pd75p336 m pd75304b m pd75p336 xt1 xt2 c4 c3 v dd r xt1 xt2 leave open subsystem clock oscillator characteristics 32 32.768 35 khz 1.0 2 s 10 s 32 100 khz 515 m s xt1 input high-/ low-level width (t xth ,t xtl ) recommended test resonator parameter min. typ. max. unit constant conditions oscillator frequency (f xt ) v dd = 4.5 to 6.0 v oscillation stabilization time xt1 input frequency (f xt ) (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) crystal resonator external clock note when the main system clock and subsystem clock oscillation circuit are used, area inside doted lines in the figure should be wired as follows to prevent influence from the wiring capacitance, etc.. ? wiring should be as short as possible. ? do not cross other signal lines, and do not place the oscillator close to line in which varying high current flows. ? potential at the oscillator capacitor connecting point should always be the same as v dd . do not connect to the power supply pattern in which high current flows. ? do not fetch signals from the oscillator. in the subsystem clock oscillator, which is designed to be a circuit with low amplification ratio to suppress consumption current, misoperation due to noise occurs more often than in the main system clock oscillator. therefore, when using the subsystem clock, special care should be taken in the wiring method.
m pd75p336 31 m pd75p336 m pd75p336 m pd75304b m pd75p336 parameter symbol test conditions min. typ. max. unit open-drain v dd = 4.5 to 6.0 v i oh = C1 ma i oh = C100 m a v dd = 4.5 to 6.0 v i oh = C100 m a i oh = C50 m a ports 2, 3, 8 ports 0, 1, 6, 7, reset ports 4 and 5 x1, x2, xt1 ports 2, 3, 4, 5, 8 ports 0, 1, 6, 7 reset x1, x2, xt1 ports 0, 2, 3, 6, 7, 8 bias bp0 to bp7 (i oh 2 outputs) dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) (1/3) v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v oh1 v oh2 input voltage high input voltage low output voltage high 0.7 v dd 0.8 v dd 0.7 v dd v dd C0.5 0 0 0 v dd C1.0 v dd C0.5 v dd C2.0 v dd C1.0 v dd v dd 10 v dd 0.3 v dd 0.2 v dd 0.4 v v v v v v v v v v v
m pd75p336 32 m pd75p336 m pd75304b m pd75p336 dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) (2/3) parameter symbol test conditions min. typ. max. unit ports 3, 4, 5 v dd = 4.5 to 0.4 2.0 v 6.0 v i ol = 15 ma v dd = 4.5 to 6.0 v 0.4 v i ol = 1.6 ma i ol = 400 m a 0.5 v open-drain pull-up 0.2 v dd v resistor 3 1 k w v dd = 4.5 to 6.0 v 1.0 v i ol = 100 m a i ol = 50 m a 1.0 v other than below x1, x2, xt1 20 m a ports 4, 5 (when open- 20 m a drain) other than below x1, x2, xt1 C20 m a other than below ports 4 and 5 (when open- 20 m a drain) output leakage current low v dd = 5.0 v 10% v dd = 3.0 v 10% i lil2 3 m a C3 m a C3 m a 3 m a v lcd v ol1 v ol2 i lih1 i lih2 i lih3 i lil1 i loh1 i loh2 i lol r l1 ports 0, 2, 3, 4, 5, 6 7, 8 sb0, 1 bp0 to bp7 (i ol 2 outputs) v in = v dd v in = 10 v v in = 0 v v out = v dd v out = 10 v v out = 0 v ports 0, 1, 2, 3, 6 7, 8 (except p00) v in = 0 v output voltage low input leakage current high input leakage current low output leakage current high built-in pull-up resistor lcd drive voltage 15 40 80 k w 30 300 k w 2.5 v dd v
m pd75p336 33 m pd75p336 m pd75p336 m pd75304b m pd75p336 v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.7 v v lcd v dd v dd = 5 v 10 % *4 v dd = 3 v 10 % *5 halt mode operat- ing mode halt mode v dd = 3 v 10 % dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) (3/3) parameter lcd output voltage deviation *1 (common) lcd output voltage deviation *1 (segment) power supply current *2 symbol v odc v ods i dd1 i dd2 i dd3 i dd4 i dd5 test condition i o = 5 m a i o = 1 m a 4.19 mhz crystal oscillation c1= c2 = 22 pf *3 32 khz crystal oscillation *6 xt1 = 0 v stop mode v dd = 5 v 10 % min. 0 0 typ. 5 1 500 300 100 20 0.5 0.1 0.1 max. 0.2v 0.2v 15 3 1500 900 300 60 20 10 5 unit v v ma ma m a m a m a m a m a m a m a *1. the voltage deviation means a difference between the ideal value of segment or common output (v lcdn ; n = 0, 1, 2) and the output voltage. 2. current flowing in the built-in pull-up resistor and the lcd split resistor is not include. 3. including the case where the subsystem clock is operating. 4. when the processor clock control register (pcc) is set to 0011 and operated in high-speed mode. 5. when pcc is set to 0000 and operated in the low-speed mode. 6. the case where the system clock control register (scc) is set to 1001, the main system clock oscillatio stopped and the device is operated on the subsystem clock. v dd = 5 v 10 % v dd = 3 v 10 % v dd = 3 v 10 % v dd = 3 v 10 % t a = 25 c
m pd75p336 34 m pd75p336 m pd75304b m pd75p336 test condition 2.5 v av ref v dd av ref 3 0.6 v dd 2.5 v av ref v dd av ref < 0.6 v dd *2 *3 a/d converter characteristics parameter resolution absolute accuracy *1 conversion time sampling time analog input voltage analog input impedance av ref current symbol t conv t samp v ian r an i ref (ta = C40 to +85 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) C10 ta + 85 o c C40 ta < C10 o c t cy 3 1.91 m s t cy < 1.91 m s C10 ta + 85 o c C40 ta C 10 o c C40 ta + 85 o c *1. absolute accuracy excluding quantization ( 1/2lsb) error. 2. time up to end of conversion (eoc = 1) after execution of the conversion start instruction. (40.1 m s: f x = 4.19 mhz operation) 3. time up to end of sampling after execution of the conversion start instruction. (10.5 m s: f x = 4.19 mhz operation) max. 8 1.5 2.0 1.5 2.0 3.0 168/fx 44x av ref 2.0 unit bit lsb s s v m w ma typ. 8 1000 1.0 min. 8 av ss
m pd75p336 35 m pd75p336 m pd75p336 m pd75304b m pd75p336 parameter symbol test conditions min. typ. max. unit operated v dd = 4.5 by main to 6.0 v system clock 3.8 64 m s operated by subsystem 114 122 125 m s clock v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz v dd = 4.5 to 6.0 v 0.48 m s 1.8 m s int0 *2 m s int1, 2, 4 10 m s kr0 to kr7 10 m s reset low level width ac characteristics 0.95 64 m s t cy f ti t tih , t til t inth , t intl t rsl (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) 10 m s cpu clock cycle time (minimum instruction execution time = 1 machine cycle) *1 ti0, 1 input frequency ti0, 1 input high/ low level width interrupt input high/ low level width *1. the cpu clock ( f ) cycle time is determined by the oscillator frequency of the connected resonator and the system clock control register (scc) and the processor clock control register (pcc). the figure below shows the main system clock opera- tion power supply voltage v dd vs cycle time t cy characteristics. 2. becomes 2 t cy or 128/f x depending on the interrupt mode register (im0) setting. t cy vs v dd (operating on main system clock) cycle time t cy [ s] supply voltage v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 30 64 70 6 operating guaranteed range m
m pd75p336 36 m pd75p336 m pd75304b m pd75p336 serial transfer operation 2-wired and 3-wired serial i/o modes (sck ... internal clock output) parameter symbol test conditions min. typ. max. unit si setup time (to sck - ) si hold time (from sck - ) v dd = 4.5 r l = 1 k w , to 6.0 v c l = 100 pf * 1000 2-wired and 3-wired serial i/o modes (sck ... external clock input) parameter symbol test conditions min. typ. max. unit 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns si setup time 100 ns (to sck - ) si hold time 400 ns (from sck - ) v dd = 4.5 to 6.0 v 1000 ns * r l and c l are the so output line load resistance and load capacitance, respectively. 150 400 t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 t kh2 v dd = 4.5 to 6.0 v 1600 v dd = 4.5 to 6.0 v 3800 t kcy1 /2-50 t kcy1 /2-150 250 ns ns ns ns ns ns ns v dd = 4.5 to 6.0 v 800 r l = 1 k w , c l = 100 pf * ns 300 ns ns sck cycle time sck high/low level width so output delay time from sck sck cycle time sck high/low level width so output delay time from sck t kcy2 t kl2 t sik2 t ksi2 t kso2
m pd75p336 37 m pd75p336 m pd75p336 m pd75304b m pd75p336 symbol t kcy3 t kl3 t kh3 t sik3 t ksi3 t kso3 t ksb t sbk t sbl t sbh parameter sb0,1 setup time (to sck - ) sb0,1 hold time (from sck - ) sb0,1 output delay time from sck sb0,1 from sck - sck from sb0, 1 sb0,1 low level width sb0,1 high level width test conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w , c l = 100 pf * v dd = 4.5 to 6.0 v min. 1600 3800 t kcy3 /2-50 t kcy3 /2-150 150 t kcy3 /2 0 0 t kcy3 t kcy3 t kcy3 t kcy3 typ. max. 250 1000 unit ns ns ns ns ns ns ns ns ns ns ns ns sck cycle time sck high/low level width sbi mode (sck ... internal clock output (master)) * r l and c l are the sb0 and sb1 output line load resistance and load capacitance, respectively.
m pd75p336 38 m pd75p336 m pd75304b m pd75p336 sbi mode (sck ... external clock input (slave)) symbol t kcy4 t kl4 t kh4 t sik4 t ksi4 t kso4 t ksb t sbk t sbl t sbh parameter sb0,1 setup time (to sck - ) sb0,1 hold time (from sck - ) sb0,1 output delay time from sck sb0,1 from sck - sck from sb0, 1 sb0,1 low level width sb0,1 high level width test conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w , c l = 100 pf * v dd = 4.5 to 6.0 v min. 800 3200 400 1600 100 t kcy4 /2 0 0 t kcy4 t kcy4 t kcy4 t kcy4 typ. max. 300 1000 unit ns ns ns ns ns ns ns ns ns ns ns ns * r l and c l are the sb0 and sb1 output line load resistance and load capacitance, respectively. sck cycle time sck high/low level width
m pd75p336 39 m pd75p336 m pd75p336 m pd75304b m pd75p336 x1 input 1/f x t xl t xh v dd -0.5 v 0.4 v xt1 input 1/f xt t xtl t xth v dd -0.5 v 0.4 v 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ti0 1/f ti t til t tih ac timing test point(exculuding x1 and xt1 inputs) clock timings ti0 timing
m pd75p336 40 m pd75p336 m pd75304b m pd75p336 sck t kcy1 t kh1 t kl1 input data output data t sik1 t ksi1 t kso1 si so serial transfer timing 3-wired serial i/o mode: 2-wired serial i/o mode: t kso2 t kl2 t kh2 t kcy2 sck sb0,1 t sik2 t ksi2
m pd75p336 41 m pd75p336 m pd75p336 m pd75304b m pd75p336 t intl t inth int0,1,2,4 kr0-7 t rsl reset t ksb t sbl t sbh t sbk t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t ksb t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t sbk serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing
m pd75p336 42 m pd75p336 m pd75304b m pd75p336 data memory stop mode low supply voltage dat retention characteristics (ta = C40 to 85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage data retention supply current *1 release signal set time oscillation release by reset 2 17 /fx ms stabilization wait time *2 release by interrupt request *3 ms *1. current flng in the built-in pull-up resistor is not included. 2. the oscillation stabilization wait time is the time cpu operation is stopped to prevent unstable operation at start of oscillation. 3. depends on the basic interval timer mode register (btm) setting (table below). btm3 btm2 btm1 btm0 (figures in parentheses are for operation at fxx = 4.19 mhz) 0 00 2 20 /fxx (approx. 250 ms) 0 11 2 17 /fxx (approx. 31.3 ms) 1 01 2 15 /fxx (approx. 7.82 ms) 1 11 2 13 /fxx (approx. 1.95 ms) v dddr i dddr t srel t wait 0 m s waite time v dddr = 2.0 v 0.1 10 m a 2.0 6.0 v
m pd75p336 43 m pd75p336 m pd75p336 m pd75304b m pd75p336 stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request) stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal)
m pd75p336 44 m pd75p336 m pd75304b m pd75p336 d/c programing characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter input voltage high input voltage low input leakage current output voltage high output voltage low v dd power supply current v pp power supply current symbol v ih1 v ih2 v il1 v il2 v l1 v oh v ol i dd i pp test condition except x1, x2 x1, x2 except x1, x2 x1, x2 v in = v il or v ih i oh = C1 ma i ol = 1.6 ma md0 = v il , md1 = v ih min. 0.7v dd v dd -0.5 0 0 v dd -1.0 typ. max. v dd v dd 0.3v dd 0.4 10 0.4 30 30 unit v v v v m a v v ma ma *1. v pp must not exceed +13.5 v including overshoot. 2. v dd should be applied before v pp and cut after v pp . a/d programing characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) (1/2) typ. 1.0 symbol t as t mis t ds t ah t dh t df t vps t vds t pw *1 t as t oes t ds t ah t dh t df t vps t vcs t pw test condition min. 2 2 2 2 2 0 2 2 0.95 max. 130 1.05 unit m s m s m s m s m s m s m s m s ms parameter address setup time *2 (to md0 ) md1 setup time (to md0 ) data setup time (to md0 ) address hold time *2 (from md0 - ) data hold time (from md0 - ) data output float delay time from md0 - v pp setup time (to md3 - ) v dd setup time (to md3 - ) initial program pulse width * 1. symbol of the corresponding m pd27c256. 2. the internal address signal is incremented (+1) at the rising edge of the forth x1 input. the signal is not connected to pins.
m pd75p336 45 m pd75p336 m pd75p336 m pd75304b m pd75p336 a/d programing characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) (2/2) typ. symbol t opw t mos t dv t m1h t m1r t pcr t xh, t xl fx t i t m3s t m3h t m3sr t dad t had t m3hr t dfr min. 0.95 2 2 2 10 0.125 2 2 2 2 0 2 max. 21.0 1 4.19 2 130 2 *1 t opw t ces t dv t oeh t or ? ? ? ? ? ? ? t acc t oh ? ? parameter additional program pulse width md0 setup time (to md1 - ) data output delay time from md0 md1 hold time (from md0 - ) md1 recover time (from md0 ) program conuter reset time x1 input high/low width x1 input frequency initial mode set time md3 setup time (to md1 - ) md3 hold time (to md1 ) md3 setup time (to md0 ) data output delay time from address *2 data output hold time from address *2 md3 hold time (from md0 - ) data output float delay time from md3 test condition md0 = md1 = v il t m1h + t m1r 3 50 m s program memory read program memory read program memory read program memory read program memory read *1. symbol of the corresponding m pd27c256. 2. the internal address signal is incremented (+1) at the rising edge of the fourth x1 input. the signal is not connected to pins. unit ms m s m s m s m s m s m s mhz m s m s m s m s m s m s m s m s
m pd75p336 46 m pd75p336 m pd75304b m pd75p336 program memory write timing mode: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data output data output v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 md1 md2 md3 t vps t vds t xh t xl t i t dv t m3sr t had t dad t m3hr t dfr t pcr program memory read timing mode: v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md2 md3 md0 md1 t vps t vds t i t ds t oh t dv t df t pw t m1r t m0s t ds t opw t xh t xl t dh t ah t as t pcr t m1s t m1h t m3s t m3h data input data input data output data input ? ? ? ? ? ? ? ? ?
47 m pd75p336 6. package information h a m f b 60 61 40 k l 80 pin plastic qfp ( 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 55? n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
48 m pd75p336 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0?.2 0.551 +0.009 ?.008 b 12.0?.2 0.472 +0.009 ?.008 c 12.0?.2 0.472 +0.009 ?.008 d 14.0?.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009?.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.05 0.041 q 0.05?.05 0.002?.002 r 55? 55? +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
49 m pd75p336 7. recommended soldering conditions this product should be soldered and mounted under the conditions in the table below. for detail of recommended soldering conditions, refer to the information document "surface mount technology manual" (iei-1207) . for soldering methods and conditions other than those recommended below, contact our salesman. table 7-1 soldering conditions (1) m pd75p336gc-3b9 : 80-pin plastic qfp ( 14mm) recommended condition symbol solderring method solderring conditions solder bath temperature: 260 c. max., duration: 10 sec. max., number of times: once, time limit: 2 days * (thereafter 20 hours prebaking required at 125 c) preheat temperature: 120 c max. (package surface temperature) wave soldering ws60-202-1 package peak temperature: 230 c, duration: 30 sec. max., (at 210 c or above), number of times: once, time limit: 2 days * (thereafter 20 hours prebaking required at 125 c) infrared reflow package peak temperature: 215 c, duration: 40 sec. max., (at 200 c or above), number of times: once, time limit: 2 days * (thereafter 20 hours prebaking required at 125 c) vps reflow pin part temperature: 300 c or below, duration: 3 sec. max. (per device side) pin part heating ir30-202-1 vp15-202-1 (2) m pd75p336gk-be9 : 80-pin plastic tqfp (fine pitch) ( 12mm) recommended condition symbol solderring method solderring conditions package peak temperature: 235 c, duration: 30 sec. max., (at 210 c or above), number of times: once, time limit: 1 day * (thereafter 10 hours prebaking required at 125 c) infrared reflow package peak temperature: 215 c, duration: 40 sec. max., (at 200 c or above), number of times: once, time limit: 1 day * (thereafter 10 hours prebaking required at 125 c) vps reflow pin part temperature: 300 c or below, duration: 3 sec. max. (per device side) pin part heating ir35-101-1 vp15-101-1 * for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65 % rh. note use of more than one soldering method should be avoided (except in the case of pin part heating). h
m pd75p336 50 m pd75p336 m pd75p336 m pd75304b m pd75304b m pd75p336 item name m pd75336 m pd75328 appendix a. list of functions main system clock subsystem clock cmos input cmos input/output cmos output n-ch open-drain input/output 8 20 8 same as at left (but no pull-up resistor) 44 75x-high end 16256 (mask rom) 16256 (prom) 768 4 bits 8 4 banks 0.95 m s, 1.91 m s, 3.81 m s, 15.3 m s (at 4.19 mhz operation) 122 m s (at 32.768 khz operation) internal pull-up resistor specifiable by software dual function as segment pins max.20 4 segment drive, variable duty: static, 1/2, 1/3, 1/4 ? 8-bit resolution 8-ch (successive approximation type) ? low-voltage operation capability: v dd = 2.7 to 6.0 v ? basic interval timer 1 ? timer/event counter 2 ? watch timer 1 ? nec standard serial interface (sbi) ? clocked serial interface external: 3 internal: 4 external: 1 internal: 1 f , 524khz, 262khz, 65.5khz (at 4.19mhz operation) 2khz, 4khz, 32khz transfer, addition/subtraction, increment/decrement, comparison v dd = 2.7 - 6.0 v 80-pin plastic qfp ( 14 mm) 80-pin plastic tqfp (fine pitch) ( 12mm) m pd75p336 8 (10 v withstand voltage, mask option pull-up capability) 8 (10 v, withstand voltage mask option pull-up capability) 75x-standard 8064 (mask rom) 512 4 bits 8 1 bank 0.95 m s, 1.91 m s, 15.3 m s (at 4.19 mhz operation) ? 8-bit resolution 6-ch (successive approxima- tion type) ? low-voltage operation capability: v dd = 3.5 to 6.0 v ? basic interval timer 1 ? timer/event counter 1 ? watch timer 1 external: 3 internal: 3 external: 1 internal: 1 2khz transfer m pd75p328 m pd75p336 cpu core rom (bytes) ram ( 4 bits) general registers instruction cycle input/ output ports lcd controller/driver a/d converter timer/counter serial interface vectored interrupt test input clock output (pcl) buzzer output (buz) 8-bit data processing operating voltage package on-chip prom product h
m pd75p336 51 m pd75p336 m pd75p336 m pd75p336 m pd75304b m pd75304b m pd75p336 appendix b. development tools the following support tools are available for system development using the m pd75p336. language processor ordering code (product name) m s5a13ra75x m s5a10ra75x m s7b10ra75x supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc host machine pc-9800 series ibm pc/at ? os ms-dos? ver. 3.30 to ver. 5.00a * pc dos? (ver. 3.1) prom programmer which enables a single-chip microcomputer with on-chip prom to be programmed in stand-alone mode or by operations from a host machine by connection of the supplied board and a separately available programmer adapter. typical proms from 256k bits to 4m bits can also be programmed. ordering code (product name) m s5a13pg1500 m s5a10pg1500 m s7b10pg1500 supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc host machine pc-9800 series ibm pc/at software hardware ms-dos ver. 3.30 to ver. 5.00a * pc dos (ver. 3.1) os prom write tools remarks assembler operation is only guaranteed for the host machines and operating systems quoted above. pa-75p328gc pa-75p336gk prom program adapter for the m pd75p336gk, used connect to the pg-1500. prom programmer adapter for the m pd75p336gc, used connected to the pg-1500. controls the pg-1500 on the host machine, with the pg-1500 and host machine connected via a serial or parallel interface. ra75x relocatable assembler pg-1500 pg-1500 controller * the task-swap function is provided with ver.5.00/5.00a, but the function cannot be used with this software. remarks pg-1500 controller operation is only guaranteed for the host machines and operating systems quoted above. h h
m pd75p336 52 m pd75p336 m pd75p336 m pd75304b m pd75304b m pd75p336 debugging tools ie-75000-r *1 ie-75000-r-em ep-75338gc-r the ie-75000-r is an in-circuit emulator which corresponds to the 75x series. for m pd75p336 development the ie-75000-r is used in conjunction with an emulation probe. efficient debugging is possible by connection to a host machine and prom programmer. emulation board for the ie-75000-r and ie-75001-r. incorporated in the ie-75000-r. used in conjunction with the ie-75000-r or ie-75001-r to perform m pd75p336 evaluation. the ie-75001-r is an in-circuit emulator which corresponds to 75x series. for m pd75p336 development the ie-75001-r is used in conjunction with an emulation board ie-75000-r-em *2 and emulation probe. efficient debugging is possible by connection to a host machine and prom programer. emulation probe for m pd75p336gc. used connect with the ie-75000-r or ie-75001-r, ie-75000-r- em. an 80-pin lcc socket (ev-9200gc-80) is also available to simplify connection to the user system. ie-75001-r emulation probe for m pd75336gk. used connected with the ie-75000-r or ie-75001-r, ie-75000-r- em. an 80-pin conversion adapter (ev-9500gk-80 is also available to simplify connection to the user system. supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc connects the ie-75000-r or ie-75001-r to the host machine via by rs-232-c and contronix i/f and controls the ie-75000-r or ie-75001-r on the host machine. ev-9200g-80 ep-75336gk-r ie control program hardware software *1. maintenance product 2. ie-75000-r-em sold sparately 3. the task-swap function is provided with ver.5.00/5.00a, but the function cannot be used with this software. remarks operations of the ie control program is only guaranteed for the host machines and operating systems quoted above. os ms-dos ver. 3.30 to ver. 5.00a *3 pc dos (ver. 3.1) ev-9500gk-80 host machine pc-9800 series ibm pc/at ordering code (product name) m s5a13ie75x m s5a10ie75x m s7b10ie75x h
m pd75p336 53 m pd75p336 m pd75p336 m pd75p336 m pd75304b m pd75304b m pd75p336 development tools configuration h user system ep-75336gc-r ep-75336gk-r emulation probe pd75p336gc pruducts incorporating prom in-circuit emulator ie-75000-r prom programmer pg-1500 programmer adapter pa-75p328gc relocatable assembler ie control program pg-1500 controller host machine pc-9800 series ibm pc/at (symbolic debugging possible) centronics i/f rs-232-c + ie-75001-r *1 ie-75000-r-em *2 m pd75p336gk m pa-75p336gk *1. the ie-75001-r does not incorporate the ie-75000-r-em (available separately.) 2. ev-9200gc-80 ev-9500gk-80
m pd75p336 54 m pd75p336 m pd75p336 m pd75304b m pd75304b m pd75p336
m pd75p336 55 m pd75p336 m pd75p336 m pd75p336 m pd75304b m pd75304b m pd75p336
[memo] m pd75p336 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 ms-dos ? is a trademark of microsoft corporation. pc dos ? and pc/at ? is a trademark of ibm corporation.

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