iso150 dual, isolated, bi-directional digital coupler l replaces high-performance optocouplers l data rate: 80m baud, typ l low power consumption: 25mw per channel, max l two channels, each bi-directional, programmable by user l partial discharge tested: 2400vrms l creepage distance of 16.5mm (dip) l low cost per channel l plastic dip and soic packages l digital isolation for a/d, d/a conversion l isolated uart interface l multiplexed data transmission l isolated parallel to serial interface l test equipment l microprocessor system interface l isolated line receiver l ground loop elimination features applications channel 2 channel 1 side a side b g a d 2a r/t 2a v sa d 1a r/t 1a d 2b v sb r/t 2b d 1b g b r/t 1b description the iso150 is a two-channel, galvanically isolated data coupler capable of data rates of 80mbaud, typi- cal. each channel can be individually programmed to transmit data in either direction. data is transmitted across the isolation barrier by coupling complementary pulses through high voltage 0.4pf capacitors. receiver circuitry restores the pulses to standard logic levels. differential signal transmis- sion rejects isolation-mode voltage transients up to 1.6kv/ m s. iso150 avoids the problems commonly associated with optocouplers. optically isolated couplers require high current pulses and allowance must be made for led aging. the iso150s bi-cmos circuitry oper- ates at 25mw per channel. iso150 is available in a 24-pin dip package and in a 28-lead soic. both are specified for operation from C40?c to 85?c. ? 1993 burr-brown corporation pds-1213b printed in u.s.a. august, 1994 international airport industrial park ? mailing address: po box 11400 ? tucson, az 85734 ? street address: 6730 s. tucson blvd. ? tucson, az 85706 tel: (520) 746-1111 ? twx: 910-952-1111 ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate product info: (800) 548-6132 sbos032
2 ? iso150 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. specifications t a = +25 c, v s = +5v unless otherwise noted. iso150ap, au notes: (1) all devices receive a 1s test. failure criterion is 3 5 pulses of 3 5pc. (2) the voltage rate-of-change across the isolation barrier that can be sustained without data errors. (3) logic inputs are hct-type and thresholds are a function of power supply voltage with approximately 0.4v hystersissee text. (4) supply current measured with both tranceivers set for the indicated mode. supply current varies with data ratesee typical curves. (5) calculated from the maximum pulse width distortion (pwd), where data rate = 0.3/pwd. (6) propagation time measured from v in = 1.5v to v o = 2.5v. (7) the difference in propagation time of channel a and channel b in any combination of transmission directions. (8) the difference between progagation time of a rising edge and a falling edge. parameter condition min typ max units isolation parameters rated voltage, continuous 60hz 1500 vrms partial discharge, 100% test (1) 1s, 5pc 2400 vrms creepage distance (external) dipp package 16 mm soicu package 7.2 mm internal isolation distance 0.10 mm isolation voltage transient immunity (2) 1.6 kv/ m s barrier impedance >10 14 || 7 w || pf leakage current 240vrms, 60hz 0.6 m arms dc parameters logic output voltage, high, v oh i oh = 6ma v s C1 v s v low, v ol i ol = 6ma 0 0.4 v logic output short-circuit current source or sink 30 ma logic input voltage, high (3) 2v s v low (3) 0 0.8 v logic input capacitance 5pf logic input current <1 na power supply voltage range (3) 3 5 5.5 v power supply current (4) transmit mode dc 0.001 100 m a 50mbaud 14 ma receive mode dc 7.2 10 ma 50mbaud 16 ma ac parameters data rate, maximum (5) c l = 50pf 50 80 mbaud data rate, minimum dc propagation time (6) c l = 50pf 20 27 40 ns propagation delay skew (7) c l = 50pf 0.5 2 ns pulse width distortion (8) c l = 50pf 1.5 6 ns output rise/fall time, 10% to 90% c l = 50pf 9 14 ns mode switching time receive-to-transmit 13 ns transmit-to-receive 75 ns temperature range operating range C40 85 c storage C40 125 c thermal resistance, q ja 75 c/w
? 3 iso150 absolute maximum ratings storage temperature ......................................................... C40 c to +125 c supply voltages, v s ...................................................................... C0.5 to 6v transmitter input voltage, v i ............................................. C0.5 to v s + 0.5v receiver output voltage, v o ............................................. C0.5 to v s + 0.5v r/t x inputs ......................................................................... C0.5 to v s + 0.5v isolation voltage dv/dt, v iso ............................................................ 500kv/ m s d x short to ground ...................................................................... continuous junction temperature, t j .................................................................... 175 c lead temperature (soldering, 10s) ..................................................... 260 c 1.6mm below seating plane (dip package) ......................................... 300 c package information (1) package drawing model package number iso150ap 24-pin single-wide dip 243-1 iso150au 28-lead soic 217-2 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix d of burr-brown ic data book. pin configuration top view dip 24
23
22
15
14
13 1
2
3
10
11
12 d 1a
r/t 1a
v sa
g b
r/t 1b
d 1b d 2a
r/t 2a
g a
v sb
r/t 2b
d 2b top view soic pin descriptions name function d 1a data in or data out for transceiver 1a. r/t 1a held low makes d 1a an input pin. r/t 1a receive/transmit switch controlling transceiver 1a. v sa +5v supply pin for side a which powers transceivers 1a and 2a. g b ground pin for transceivers 1b and 2b. r/t 1b receive/transmit switch controlling transceiver 1b. d 1b data in or data out for transceiver 1b. r/t 1b held low makes d 1b an input pin. d 2b data in or data out for transceiver 2b. r/t 2b held low makes d 2b an input pin. r/t 2b receive/transmit switch controlling d 2b . v sb +5v supply pin for side b which powers transceivers 1b and 2b. g a ground pin for transceivers 1a and 2a. r/t 2a receive/transmit switch controlling transceiver 2a. d 2a data in or data out for transceiver 2a. r/t 2a held low makes d 2a in input pin. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with ap- propriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 28
27
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17
16
15 1
2
3
12
13
14 d 1a
r/t 1a
v sa
g b
r/t 1b
d 1b d 2a
r/t 2a
g a
v sb
r/t 2b
d 2b
4 ? iso150 typical performance curves t a = +25 c, v s = +5v unless otherwise noted. supply current per channel
vs temperature temperature (?) ?0 6
5
4
3
2
1 ?0 ?0 0 20 40 60 80 100 120 140 supply current (ma) v s = 5.0v v s = 3.0v normalized rise/fall time vs temperature 1.6 1.5 1.4 1.3 1.2 1.1 1.0 .9 ?0 ?0 ?0 0 20 40 60 80 100 120 140 temperature (?) relative t r , t f
c l = 50pf normalized to average
of many devices
at 25? +1 s
? s supply current per channel
vs supply voltage 5 4 3 2 1 12345 6 supply voltage, v s (v) supply current (ma) c l = 15pf receive mode transmit mode 0 f = 1mhz = 2mbaud power consumption per channel vs frequency frequency (hz) 100k 1m 10m 100m power (mw) supply current (ma) 50
40
30
20
10
0 10
8
6
4
2
0 receive
transmit no load
one channel note:
baud rate = 2 ?frequency typical rise and fall times vs capacitive load
vs supply voltage 100 80 60 40 20 0 0 100 200 300 400 500 capacitive load (pf) t r , t f (ns) v s = 3.0v v s = 5.0v t r t f t f t r propagation delay vs supply voltage 45 40 35 30 25 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage, v s (v) propagation delay (ns) low to high high to low pulse width distortion
? 5 iso150 typical performance curves (cont) t a = +25 c, v s = +5v unless otherwise noted. isolation voltage vs frequency 10k 2.1k 1k 100 10 1 1k 10k 100k 1m 10m 100m frequency (hz) peak isolation voltage (v) max dc
rating degraded
performance pulse width distortion
vs temperature temperature (?) ?0 5
4
3
2
1
0 ?0 ?0 0 20 40 60 80 100 120 140 pulse width distortion, pwd (ns) v s = 5.0v
c l = 50pf output voltage vs logic input voltage 5 4 3 2 1 0 0.5 1.0 1.5 2.0 v in (v) v out (v) propagation delay vs temperature 60 50 40 30 20 10 0 ?0 ?0 ?0 0 20 40 60 80 100 120 140 temperature (?) propagation delay, t pd (ns) v s = 3.0v v s = 5.0v c l = 50pf logic input threshold voltage
vs supply voltage 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply voltage, v ss (v) v in (v) v t low , ?0? v t high , 125? isolation leakage current vs frequency 100m 10m 1m 100 10 1 100n 1 10 100 1k 10k 100k 1m frequency (hz) leakage current (arms) v iso = 240vrms v iso = 1500vrms
6 ? iso150 typical performance curves (cont) t a = +25 c, v s = +5v unless otherwise noted. isolation barrier data is transmitted by coupling complementary logic pulses to the receiver through two 0.4pf capacitors. these capaci- tors are built into the iso150 package with faraday shield- ing to guard against false triggering by external electrostatic fields. the integrity of the isolation barrier of the iso150 is verified by partial discharge testing. 2400vrms, 60hz, is applied across the barrier for one second while measuring any tiny discharge currents that may flow through the barrier. these current pulses are produced by localized ionization within the barrier. this is the most sensitive and reliable indicator of barrier integrity and longevity, and does not damage the barrier. a device fails the test if five or more current pulses of 5pc or greater are detected. figure 1. basic operation diagram. conventional isolation barrier testing applies test voltage far in excess of the rated voltage to catastrophically break down a marginal device. a device that passes the test may be weakened, and lead to premature failure. applications information figure 1 shows the iso150 connected for basic operation. channel 1 is configured to transmit data from side b to a. channel 2 is set for transmission from side a to b. the r/t pins for each of the four transceivers are shown connected to the required logic level for the transmission direction shown. the transmission direction can be controlled by logic signals applied to the r/t pins. channel 1 and 2 can be independently controlled for the desired transmission direction. typical insulation resistance vs temperature 10 16 10 15 10 14 10 13 10 12 10 11 10 10 0 20 40 60 80 100 120 140 160 180 temperature (?) isolation resistance ( w ) notes: (1) power supplies and grounds on side a and side b are isolated. (2) recommended bypass: 0.1 m f in parallel with 1nf. data in +5v (1) +5v (1) (1) (1) (2) (1) (1) (2) channel 2 data out channel 1 data out channel 2 data in channel 1 (transmit)
(transmit)
(receive) (receive) channel 2 channel 1 side a side b g a d 2a r/t 2a d 2b v sb r/t 2b d 1b g b r/t 1b v sa d 1a r/t 1a
? 7 iso150 logic levels a single pin serves as a data input or output, depending on the mode selected. logic inputs are cmos with thresholds set for ttl compatibility. the logic threshold is approxi- mately 1.3v with 5v supplies and with approximately 400mv of hysteresis. input logic thresholds vary with the power supply voltage. drive the logic inputs with signals that swing the full logic voltage swing. the iso150 will use somewhat greater quiescent current if logic inputs do not swing within 0.5v of the power supply rails. in receive mode, the data output can drive 15 standard ls-ttl loads. it will also drive cmos loads. the output drive circuits are cmos. power supply separate, isolated power supplies must be connected to side a and side b to provide galvanic isolation. nominal rated supply voltage is 5v. operation extends from 3v to 5.5v. power supplies should be bypassed close to the device pins on both sides of the isolation barrier. the v s pin for each side powers the transceivers for both channel 1 and 2. the specified supply current is the total of both transceivers on one side, both operating in the indicated mode. supply current for one transceiver in transmit mode and one in receive mode can be estimated by averaging the specifications for transmit and receive operation. supply current varies with the data transmission ratesee typical curves. power-up state the iso150 transmits information across the barrier only when the input-side data changes logic state. when a trans- ceiver is first programmed for receive mode, or is powered- up in receive mode, its output is initialized high. subse- quent changes of data applied to the input side will cause the output to properly reflect the input side data. signal loss the iso150s differential-mode signal transmission and careful receiver design make it highly immune to voltage across the isolation barrier (isolation-mode voltage). rapidly changing isolation-mode voltage can cause data errors. as the rate of change of isolation voltage is increased, there is a very sudden increase in data errors. approximately 50% of iso150s will begin to produce data errors with isolation- mode transients of 1.6kv/ m s. this may occur as low as 500v/ m s in some devices. in comparison, a 1000vrms, 60hz isolation-mode voltage has a rate of change of approximately 0.5v/ m s. still, some applications with large, noisy isolation-mode voltage can produce data errors by causing the receiver output to change states. after a data error, subsequent changes in input data will produce correct output data. propagation delay and skew logic transitions are delayed approximately 27ns through the iso150. some applications are sensitive to data skew the difference in propagation delay between channel 1 and channel 2. skew is less than 2ns between channel 1 and channel 2. applications using more than one iso150 must allow for somewhat greater skew from device to device. since all devices are tested for delay times of 20ns min to 40ns max, 20ns is the largest device-to-device data skew. mode changes the transmission direction of a channel can be changed on the fly by reversing the logic levels at the channels r/t pins on both side a and side b. approximately 75ns after the transceiver is programmed to receive mode its output is initialized high, and will respond to subsequent input-side changes in data. standby mode quiescent current of each transceiver circuit is very low in transmit mode when input data is not changing (1na typi- cal). to conserve power when data transmission is not required, program both side a and b transceivers for trans- mit mode. input data applied to either transceiver is ignored by the other side. high speed data applied to either trans- ceiver will increase quiescent current. circuit layout the high speed of the iso150 and its isolation barrier require careful circuit layout. use good high speed logic layout techniques for the input and output data lines. power supplies should be bypassed close to the device pins on both sides of the isolation barrier. use low inductance connec- tions. ground planes are recommended. maintain spacing between side 1 and side 2 circuitry equal or greater than the spacing between the missing pins of the iso150 (approximately 16mm for the dip version). sockets are not recommended.
8 ? iso150 data
(i/o) de/re +5v "1"
(+5v) re d1 r0 a b bus +5v +5v de ltc1485 channel 2 channel 1 side a side b g a d 2a r/t 2a d 2b v sb r/t 2b d 1b g b r/t 1b v sa d 1a r/t 1a
figure 2. isolated rs-485 interface.
? 9 iso150 figure 3. iso150 and ads7807 is used to reduce circuit noise in a mixed signal application. 28
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10
9
14
19
18 1
3
2
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5
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7
8
25
26
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20 14
11
10
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13 15
1
2
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7
9 14
11
10
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13 15
1
2
3
4
5
6
7
9 v in v cc1 50k w 50k w 33.2 w 200 w 100 w 1m w +2.2? +2.2? r1 in r2 in agnd 1 cap ref agnd 2 sb/btc ext/int pwrd refd cs tag v dig
vana
busy
r/c
byte
d0
d1
d2
d3
d4
d5
d6
d7
dgnd
sdata
sclk 100 w 100 w byte
100 w 100 w 100nf 10? 100nf 6.8? 1 w 1 w v cc1 +5v
v cc1 +5v
v cc2 +5v
v cc2 +5v
v cc1 +5v d 2a r/t 2a g a v sb r/t 2b d 2b d 1a r/t 1a v sa g b r/t 1b d 1b iso150 iso150 busy ser srclk srclr rclk g qa
qb
qc
qd
qe
qf
qg
qh
qh u2 r/c u3 high byte enable low byte enable v cc2 ser srclk srclr rclk g qa
qb
qc
qd
qe
qf
qg
qh
qh 74ls595 74ls595
d 2a r/t 2a g a v sb r/t 2b d 2b d 1a r/t 1a v sa g b r/t 1b d 1b v cc1 = v cc2 = +5v
isolated supplies ads7807 +5v
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated
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