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GT-48001A switched ethernet controller for 10basex preliminary revision 1.6 12/29/97 please contact galileo technology for possible updates before finalizing a design. features www.galileot.com support@galileot.com tel: +1-408.367.1400 fax: +1-408.367.1401 ? single-chip, low cost, switched ethernet controller - provides packet switching functions between 8 on- chip ethernet ports and the pci expansion port - switch expansion via 1gbps pci bus ? galnet architecture family member - advanced distributed switching architecture - connects seamlessly to other galnet family devices - gt-48002a 100basex and gt-48003 100vg- anylan devices available ? incorporates eight 802.3 compliant ethernet ports - 10mbps half-duplex or full-duplex 20mbps ethernet for each port - serial mode selectable per port: 10base-t, 10base-fl, aui, and nrz synchronous ? all digital logic on-chip for each port - media access control (mac) - manchester encoder/decoder - link integrity, partition - automatic polarity detection and correction - dual 32-byte fifos for receive and transmit - 7 leds for link status, receive, transmit, collision, forward unknown packets, port sniffer, and half/full duplex - crc generation for cpu generated packets ? high-performance distributed switching engine - performs forwarding and filtering at full wire speed - 14,880 packets/sec on each ethernet port - flexible software or hardware intervention in packet routing decisions ? supports store and forward switching approach - low last-bit in to first-bit out delay - allows bridging between higher/lower speed interfaces (fast ethernet, atm, wan) ? advanced address recognition - intelligent address recognition mechanism enables forwarding rate at full wire speed - self-learning mechanism - supports up to 8k unicast addresses and unlimited multicast/broadcast addresses - broadcast storm rate filtering ? direct support for packet buffering - glueless interface to 1 or 2mbyte of 60ns edo dram - up to 1k buffers, 1536-bytes each, dynamically allocated to the receive and pci ports ? pci rev 2.1 interface for switch expansion and management cpu connection - up to 10 GT-48001A devices per pci bus without pci-to-pci bridging - up to 32 galnet devices in a single switch - standard cpu connection for management - simple interface to other networking interfaces (atm, fddi, etc.) ? extensive network management support - repeater mib and pci counters - address aging support - hardware assist for spanning tree algorithm - rmon station-to-station connectivity matrix - cpu access to address table - ability to define static addresses - monitoring (sniffer) mode ? hp-ease packet sampling management technology - takes snapshots of packets at programmable intervals - allows for the implementation of hp-ease or sampled rmon with low-cost cpus ? 208 pin pqfp package dma transmit receive collision forwarding unknown sniffer half/full duplex status switching engine pci bus data address control pci bus controller self-learning & address recognition engine dram controller frame controller g al n et controller 802.3 mac manchester endec tx/rx interface port 0 802.3 mac manchester endec tx/rx interface port 1 802.3 mac manchester endec tx/rx interface port 2 802.3 mac manchester endec tx/rx interface port 3 802.3 mac manchester endec tx/rx interface port 4 802.3 mac manchester endec tx/rx interface port 5 802.3 mac manchester endec tx/rx interface port 6 802.3 mac manchester endec tx/rx interface port 7 rmon fifo control control pci counters 8 x mib counters pci address table statistics counters configuration registers intervention mode control packet buffers serial switching g al n et sniffer control miscellaneous 8 x led control tx rx fifo fifo tx rx fifo fifo tx rx fifo fifo tx rx fifo fifo tx rx fifo fifo tx rx fifo fifo tx rx fifo fifo tx rx fifo fifo dma
GT-48001A switched ethernet controller 2 revision 1.6 contents 1. functional overview .......................................................................................................... .6 1.1 the galnet switching architecture .......................................................................................... ................ 6 1.2 ethernet ports ............................................................................................................. ............................. 6 1.3 address recognition ........................................................................................................ ........................ 7 1.4 cpu packet routing ......................................................................................................... ....................... 7 1.5 intervention mode .......................................................................................................... ........................... 7 1.6 network management features ................................................................................................ ............... 7 1.7 dram interface ............................................................................................................. ........................... 7 1.8 pci interface .............................................................................................................. .............................. 7 2. pin information .............................................................................................................. ...... 8 2.1 logic symbol ............................................................................................................... ............................. 8 2.2 pin functions and assignment .............................................................................................. .................. 9 3. operational overview ....................................................................................................... 13 3.1 enabling/disabling the GT-48001A ........................................................................................... .............13 3.2 basic operation ............................................................................................................ ..........................13 3.3 address learning ........................................................................................................... ........................14 3.4 packet buffering ........................................................................................................... ..........................14 3.5 packet forwarding .......................................................................................................... .......................14 3.6 the galnet protocol ........................................................................................................ .......................14 3.7 terminology ................................................................................................................ ............................14 4. mac address learning process...................................................................................... 16 4.1 address recognition ........................................................................................................ ......................16 4.2 recovery process ........................................................................................................... .......................16 4.3 address aging .............................................................................................................. ..........................17 4.4 static addresses ........................................................................................................... .........................17 4.5 address recognition failure ................................................................................................ ..................17 5. GT-48001A buffers and queues ...................................................................................... 18 5.1 receive buffer threshold programming ....................................................................................... .........19 6. packet forwarding ............................................................................................................ 20 6.1 forwarding a unicast packet to a local port ................................................................................ .........20 6.2 forwarding a unicast packet to a port in a different galnet device .....................................................20 6.3 forwarding a multicast packet .............................................................................................. .................21 6.3.1 local ports ............................................................................................................... ...............21 6.3.2 between galnet devices .................................................................................................... ....21 6.3.2.1 cpu disabled .........................................................................................................21 6.3.2.2 cpu enabled ..........................................................................................................21 6.4 forwarding a packet to the cpu directly .................................................................................... ...........22 6.5 forwarding a packet from the cpu to a galnet device ........................................................................ 24 6.6 crc generation ............................................................................................................. ........................25 6.7 tx watchdog timer .......................................................................................................... ......................25 7. device table operation .................................................................................................... 26 7.1 automatic device table initialization ...................................................................................... ................26 7.2 manual device table initialization ......................................................................................... .................26 7.3 programming device numbers ................................................................................................. .............26
GT-48001A switched ethernet controller revision 1.6 3 8. unicast intervention mode ................................................................................................ 27 8.1 unicast intervention mode address space .................................................................................... ........ 28 9. address table ................................................................................................................ .... 29 10. galnet messaging protocol .............................................................................................. 31 10.1 galnet protocol region .................................................................................................... ..................... 31 10.2 galnet messages between devices ........................................................................................... .......... 33 10.2.1 new_address message between galnet devices ............................................................ 33 10.2.2 buffer_request message between galnet devices ...................................................... 34 10.2.3 start_of_packet message between galnet devices ..................................................... 34 10.2.4 packet_transfer message between galnet devices .................................................... 35 10.2.5 end_of_packet message between galnet devices ......................................................... 35 10.3 galnet messages between a galnet device and a cpu ...................................................................... 36 10.3.1 new_address message (galnet to cpu) ......................................................................... 36 10.3.2 new_address message (cpu to galnet) ......................................................................... 37 10.3.3 buffer_request message (galnet to cpu) ................................................................... 38 10.3.4 buffer_request message (cpu to galnet) ................................................................... 38 10.3.5 start_of_packet message (galnet to cpu).................................................................. 39 10.3.6 start_of_packet message (cpu to galnet).................................................................. 39 10.3.7 packet_transfer message (galnet to cpu 16 block buffer)........................................ 40 10.3.8 packet_transfer message (galnet to cpu in unicast intervention mode)................... 41 10.3.9 packet_transfer message (cpu to galnet) ................................................................. 41 10.3.10 end_of_packet message (galnet to cpu 16 block buffer)............................................. 42 10.3.11 end_of_packet message (galnet to cpu in unicast intervention mode) ....................... 42 10.3.12 end_of_packet message (cpu to galnet) ...................................................................... 43 11. pci bus operation ........................................................................................................... .. 44 11.1 pci configuration header registers ........................................................................................ ............. 44 11.2 accessing dram and internal registers through the pci interface ...................................................... 44 11.3 pci bandwidth/performance issues .......................................................................................... ............ 44 11.4 plug-and-play considerations in pci systems ............................................................................... ....... 45 11.5 unused pci bus in stand-alone systems ..................................................................................... ........ 45 11.6 pci bus arbiter in multiple galnet device systems ......................................................................... ..... 45 12. ethernet interfaces ......................................................................................................... ... 46 12.1 media access control (mac) ................................................................................................ ................ 46 12.2 illegal frames ............................................................................................................ ............................ 46 12.3 selecting the duplex mode ................................................................................................. ................... 46 12.3.0.1 packet transmission .............................................................................................. 46 12.4 backoff algorithm options ................................................................................................. .................... 46 12.5 manchester encoder/decoder ................................................................................................ ............... 46 12.6 link integrity and auto polarity detector ................................................................................. .............. 47 12.7 data blinder .............................................................................................................. ............................. 47 12.8 inter-packet gap (ipg) .................................................................................................... ...................... 47 12.9 partition mode ............................................................................................................ ............................ 47 12.9.1 enabling partition mode .................................................................................................. ....... 47 12.9.2 entering partition state................................................................................................. .......... 47 12.9.3 exiting from partition state ............................................................................................. ........ 47 12.10 back-pressure ............................................................................................................ ............................ 48 12.11 vlan tagging support ..................................................................................................... ..................... 48 12.12 serial modes ............................................................................................................. ............................. 48 12.12.1 signal polarity in specific serial modes ................................................................................ .48 12.12.2 10baset mode ............................................................................................................ ........... 48
GT-48001A switched ethernet controller 4 revision 1.6 12.12.2.1 generating the required 10baset signals ............................................................49 12.12.2.2 pol output/auto-polarity in 10baset ......................................................................50 12.12.3 10basefl mode........................................................................................................... ...........51 12.12.4 aui mode ............................................................................................................. ................52 12.12.4.1 txd pins .............................................................................................................. ...52 12.12.4.2 auilinkup............................................................................................................. ..52 12.12.4.3 setting daddr[6] on reset ......................................................................................52 12.12.5 synchronous mode ........................................................................................................ .........53 13. network management support ........................................................................................ 55 13.1 repeater mib and pci counters ............................................................................................ ...............55 13.2 station-to-station connectivity matrix .................................................................................... ................55 13.2.1 data structure format.................................................................................................... .........56 13.3 monitoring (sniffer) mode ................................................................................................. ......................57 13.4 spanning tree support ..................................................................................................... .....................57 13.5 broadcast storm filtering ................................................................................................. ......................57 14. hp-ease packet sampling technology ......................................................................... 58 14.1 hp ease technology overview ............................................................................................... .............58 14.2 ease functionality on the GT-48001A ....................................................................................... ...........59 14.3 ease_register ............................................................................................................. ...........................59 14.4 ease interrupts ........................................................................................................... ...........................59 14.5 sampled packet indication ................................................................................................. ....................60 14.6 error source indications .................................................................................................. .......................61 14.7 enabling/disabling ease functionality ..................................................................................... .............62 14.8 interaction with other GT-48001A features ................................................................................. .........62 15. dram interface and usage .............................................................................................. 63 16. led support ................................................................................................................. ..... 63 16.1 led indications interface description ..................................................................................... ................63 16.2 led serial interface description ......................................................................................... ..................63 16.3 detailed led signal description ....................................................................................... .................64 16.3.1 primary port status led ................................................................................................. .......64 16.3.1.1 primary port status led (mode 0): (ledmode input is low) ..............................64 16.3.1.2 status led blink timing (mode 0) ..........................................................................64 16.3.1.3 primary port status led (mode 1): (ledmode input is high)..............................65 16.3.2 transmit data in progress ................................................................................................ .......66 16.3.3 receive data in progress ................................................................................................. .......66 16.3.4 collision active ......................................................................................................... ...............66 16.3.5 full/half duplex ......................................................................................................... ..............66 16.3.6 receive buffer full...................................................................................................... ............66 16.3.7 forwarding of unknown packets enabled................................................................................66 16.3.8 the port is configured as sniffer ........................................................................................ .....66 16.3.9 link fail state .......................................................................................................... ...............66 16.3.10 partition state......................................................................................................... .................66 16.4 led signals timing type ................................................................................................... ....................66 16.4.1 static led signals ....................................................................................................... ...........66 16.4.2 dynamic internal signals: ................................................................................................ .......66 16.4.3 table of internal activities/status driven via the led interface.............................................66 17. interrupts.................................................................................................................. .......... 69
GT-48001A switched ethernet controller revision 1.6 5 18. reset configuration ........................................................................................................ 6 9 18.1 configuration pins ........................................................................................................ ......................... 69 18.2 configuration input timings ............................................................................................... .................... 69 19. switch expansion ............................................................................................................ .. 70 20. development tools........................................................................................................... .71 20.1 evaluation platforms ...................................................................................................... ........................ 71 20.2 verilog models ............................................................................................................ ........................... 71 20.3 reference designs ......................................................................................................... ....................... 71 20.4 complimentary products .................................................................................................... ................... 71 21. register tables ............................................................................................................. ..... 72 21.1 internal control registers ................................................................................................ ...................... 73 21.2 pci configuration registers ............................................................................................... ................... 86 21.3 register modification restrictions ........................................................................................ ................. 89 22. pinout for 208 pin pqfp (sorted by number) ................................................................. 90 22.1 package/pin drawing ....................................................................................................... ..................... 92 23. dc characteristics - preliminary/subject to change ........................................ 93 23.1 absolute maximum ratings .................................................................................................. ................. 93 23.2 recommended operating conditions .......................................................................................... .......... 93 23.3 dc electrical characteristics over operating range ........................................................................ .... 93 23.4 thermal data .............................................................................................................. ........................... 94 24. ac timing - preliminary/subject to change....................................................... 95 25. functional waveforms ...................................................................................................... 98 25.1 pci read/write cycle ...................................................................................................... ...................... 98 26. packaging ................................................................................................................... ...... 100 27. document history ............................................................................................................ 101
GT-48001A switched ethernet controller 6 revision 1.6 1. functional overview the GT-48001A is a high-performance, low-cost, switched ethernet controller that provides packet switching functions between eight on-chip 10/20mbps ethernet ports and the 1gbps pci backplane. the GT-48001A uses the innovative galnet switching architecture to allow expansion to additional ethernet, fast ethernet and 100vg-anylan ports. the GT-48001A is backwards compatible with the gt-48001- the industrys first single-chip ethernet switch. 1.1 the galnet switching architecture the galnet switching architecture is based on a proprietary messaging protocol using the industry standard pci bus as a medium. galnet devices are designed to connect seamlessly allowing packets to be switched between devices without processor intervention (see figure 1). each galnet device acts as an intelligent agent, sharing information between all other devices in the system. for example, when one galnet device learns a new address, it automatically updates all other galnet devices via the new_address message. galnet messages are defined as write-only (request/response) in order to achieve the maximum bandwidth from the pci bus. the galnet architecture family currently consists of three products: the GT-48001A (eight ports of 10basex), the gt- 48002a (two ports of 100basex), and the gt-48003 (two ports of 100vg-anylan). in addition, galileo technology provides a number of other complementary pci interface products for popular microprocessors. 1.2 ethernet ports the GT-48001A integrates eight ethernet ports. each port works at 10mbps (half-duplex) or 20mbps (full-duplex) and includes the media access control (mac), manchester encoder/decoder, link integrity logic, auto polarity logic and led interface. the GT-48001As ethernet ports are compliant with both the 802.3 and ethernet specifications. physical media such as 10base-t, 10base-5, 10base-2 and 10base-fl are supported. figure 1: typical 16-port 10-mbps plus 2-port 100-mbps unmanaged switch implementation notes: 1) required phy circuitry and magnetics not shown 2) pci bus arbiter is typically implemented in a pal 3) edo drams per device are not shown req/gnt pair pci bus GT-48001A 8-port 10basex switch 8 10basex ports GT-48001A 8-port 10basex switch 8 10basex ports gt-48002a 2-port 100basex switch 2 100basex ports pci bus arbiter req/gnt pair
GT-48001A switched ethernet controller revision 1.6 7 1.3 address recognition each GT-48001A in a system can recognize up to 8,000 different unicast mac addresses and unlimited multicast/ broadcast mac addresses. an intelligent address recognition mechanism enables filtering and forwarding packets at full ethernet wire speed. hardware assist for address aging and static addresses is also included. the GT-48001A provides an address self-learning mechanism. each device has a private address table located in its dram array. as the GT-48001A learns new addresses, it updates all address tables in the system via the galnet mes- saging protocol. 1.4 cpu packet routing the GT-48001A has the capability to automatically forward certain packets to the cpu for routing including: ? unicast packets with a destination address tagged for the cpu ? multicast packets ? unknown packets (packets with mac addresses that have not been recognized) this gives the system designer the flexibility to decide how to handle such packets in a managed system. 1.5 intervention mode the GT-48001A incorporates an enhanced feature called intervention mode . this feature permits software or hardware intervention in the packet routing decision mechanisms for unicast packets. when intervention mode is selected for a mac address, the GT-48001A sends the packet to the system cpu instead of switching it as usual. this capability can be used for many functions including: layer 3 routing, security, virtual lan support, filtering and management. 1.6 network management features the GT-48001A provides comprehensive management capabilities enabling the switch oem to implement a wide range of network management features. for oems offering rmon capability, the GT-48001A provides per-port statis- tics counters and pci traffic counters. in addition, the GT-48001A provides station-to-station connectivity matrix infor- mation and the ability to select a port to work in monitoring (sniffer) mode. also included in the GT-48001A is a unique packet sampling capability invented by the hewlett-packard company called hp-ease (embedded advanced sampling environment.) each port has the ability to take snapshots of packet data at programmable intervals. these samples are forwarded to the management cpu for processing. the samples can be used to implement hp-ease compatible messages for openview environments, or to create custom manage- ment information bases such as statistical rmon. since packets are sampled using this technology, much less local processing is required over standard rmon implementations. source addresses of every errored packet are also sent to the cpu allowing switch oem to support error counters in rmon host and matrix groups. also included in the GT-48001A is hardware assistance for address aging and bridge spanning tree algorithms. 1.7 dram interface each galnet device in the system requires its own, separate edo dram buffer space. the dram is used to store the incoming/outgoing packets as well as the address table and other device data structures. the interface to edo dram is glueless; all signals needed to control edo devices are included. for more information, see section 15. 1.8 pci interface switch expansion and access to internal management features is possible with the GT-48001As pci interface. the GT-48001A can be either a master initiating a pci bus operation or a target responding to a pci bus operation. up to ten GT-48001A devices can reside on the same pci bus, forwarding packets from one port to the other without cpu intervention. 1 by using pci-to-pci bridge devices, the switch can be expanded to up to 32 devices (256 ports). the pci bus may also used to connect to an optional cpu for management, or to connect other high speed lan adapt- ers such as atm and fddi. 1. ten devices is the physical limit of the pci specification. please refer to the pci bus section of this data sheet for perfo rmance limita- tions.
GT-48001A switched ethernet controller 8 revision 1.6 2. pin information 2.1 logic symbol rst* clk req* gnt* perr* serr* devsel* stop* frame* par trdy* irdy* ad[31:0] cbe[3:0]* ddata[31:0] ras[1:0]* cas* we* txen[7:0] (2) txd[7:0] (3) txddel[7:0] (3) crs/rxen[7:0] rxd[7:0] rxlp/coll[7:0] GT-48001A idsel pol[7:1]/auilinkup[7:1] daddr[8:0] (1) dram serial 32 4 int* interface 9 sclk/synclk20 8 8 8 8 8 8 7 leddata ledstb ledclk miscellaneous interface interfaces pci interface 32 2 rstqueue* endev* chipsel* pol[0]/auilinkup[0] (1) - pins sampled at reset to establish device number and dram parameters (3) - pins sampled at reset to establish serial mode operation per port (2) - pins sampled at reset to establish half/full duplex mode per port scan* tristate* ledmode limit4 diswd* skipinit* disbufthr*
GT-48001A switched ethernet controller revision 1.6 9 2.2 pin functions and assignment symbol type description pci bus interface rst* i reset: active low. rst* must be asserted for at least 10 pci clock cycles. when in the reset state, all pci output pins are tristated and all open drain sig- nals are floated. following rst* deassertion, the GT-48001A clears the internal buffers and initializes the address table in the dram. the address table initial- ization takes 165,000 clk cycles to complete. any incoming packets during the address table initialization, are ignored. clk i clock: provides the timing for the GT-48001A internal units. all functional units except for the serial interfaces use this clock.clk also provides timing for pci bus transactions. the clock frequency is 30-33mhz. req* o bus request: asserted by the GT-48001A to indicate to the pci bus arbiter that this device requires mastership of the bus. gnt* i bus grant: indicates to the GT-48001A that access to the pci bus is granted. perr* i/o parity error: asserted when a data parity error is detected on the pci bus. serr* o system error: asserted by the GT-48001A when an address parity error is detected on the pci bus. the GT-48001A asserts serr* two cycles after the failing address. this output features an open-collector driver. idsel i initialization device select: asserted by a pci bus master to gain access to the GT-48001As configuration header during configuration read/write transac- tions. devsel* i/o device select: asserted by the target of the current pci access. when the GT-48001A is a bus master, it expects the target to assert devsel* within 5 bus cycles, confirming the access. if the target does not assert devsel* within the required bus cycles, the GT-48001A aborts the cycle. as a target, the gt- 48001a asserts devsel* as a medium speed pci device (two cycles after the assertion of frame*). stop* i/o stop: indicates that the current target is requesting the bus master to stop the current transaction. as a master, the GT-48001A responds to the assertion of stop* by either disconnecting, retrying, or aborting. as a target, the gt- 48001a asserts stop* to force a retry. frame* i/o cycle frame: asserted by the GT-48001A to indicate the beginning and dura- tion of a master transaction. frame* is asserted to indicate the beginning of the cycle. while frame* is asserted, data transfer continues. frame* is deasserted to indicate that the next data phase is the final data phase transaction. frame* is monitored when the GT-48001A acts as a target, to detect a configuration or memory transaction. par i/o parity: calculated by the GT-48001A as an even parity bit for the ad[31:0] and cbe[3:0]* lines. trdy* i/o target ready: indicates the target agents ability to complete the current data phase of the transaction. a data phase is completed on any clock when both trdy* and irdy* are asserted. wait cycles are inserted until both irdy* and trdy* are asserted together. irdy* i/o initiator ready: indicates the bus masters ability to complete the current data phase of the transaction. a data phase is completed on any clock when both trdy* and irdy* are asserted. wait cycles are inserted until both irdy* and trdy* are asserted together.
GT-48001A switched ethernet controller 10 revision 1.6 ad[31:0] i/o address/data: 32-bit multiplexed pci address and data lines. during the first clock of the transaction, ad[31:0] contains a physical byte address (32 bits). during subsequent clock cycles, ad[31:0] contains data. cbe[3:0]* i/o bus command/byte enable: during the address phase of the pci transac- tion, cbe[3:0]* provide the bus command. during the data phase, cbe[3:0]* provide byte enables, which determine which bytes carry valid data. int* o interrupt request line: int* is asserted by the GT-48001A when one (or more) of the bits in the interrupt cause register is set. this output features an open-collector driver. dram interface ddata[31:0] i/o dram data: 32-bit edo dram data bus. these signals connect directly to the data input/output pins of the dram devices. daddr[8:0] i/o dram multiplexed address bus: in normal operation, daddr[8:0] contain the dram multiplexed row/column address. during reset, these multi- plexed pins are sampled by the GT-48001A to indicate the device number and the dram parameters (see reset configuration section). values are determined by connecting pull-up/pull-down resistors. the device number and the dram size are read by the cpu from the status register. ras[1:0]* o row address strobes: dram row address strobes. ras[0]* is used for bank 0. ras[1]* is used for bank 1. cas* o column address strobe: dram column address strobe. the GT-48001A always accesses 32-bit values and does not require a separate cas* for each byte. we* o write enable: dram write enable. chipsel* o fifo chip select: chipsel* asserted by the GT-48001A when a packets des- tination port(s), byte count, destination address and source address are read from the dram. this information can be stored in an external fifo and accessed by the management cpu for station-to-station connectivity matrix information. ethernet interfaces txen[7:0] (fdx) i/o transmit enable: txen envelopes the transmitted packet. during reset, this multiplexed input indicates the port mode operation: pull-up for full duplex, pull-down for half duplex (see reset configuration section). txd[7:0] (sermode0) i/o transmit data: in normal operation, txd drives the transmitted data. during reset, this multiplexed input pin behaves as sermode0, which together with txddel (sermode1) indicate the port mode of operation based on pull-up/ pull-down resistors connected to them (see reset configuration section). txddel[7:0] (sermode1) i/o transmit data delayed: in normal operation, txddel outputs the transmitted data delayed. txddel follows the txd signal by 50nsec. during reset, this multiplexed input pin behaves as sermode1, which together with txd (sermode0) indicate the port mode of operation based on pull-up/ pull-down resistors connected to them (see reset configuration section). crs/rxen[7:0] i/o carrier sense/receive enable: in 10base-t, 10base-fl and aui, this output pin indicates the carrier sense. in sync mode, this input pin envelopes the receive packet. rxd[7:0] i receive data: rxd is the received serial bitstream from the ethernet wire. symbol type description
GT-48001A switched ethernet controller revision 1.6 11 rxlp/coll[7:0] i receive link pulses/collision: this multiplexed pin carries the receive link pulses in 10base-t. in aui mode, it indicates collision. pol[7:1]/ auilinkup[7:1] i/o polarity/aui link status: indicates the line polarity of ports 7:1 in 10base-t mode (output). in aui mode, the auilinkup[7:1] pins of the GT-48001A are used as inputs to indicate the link status which can be driven by the phy. when the respective auilinkup[7:1] pin is a 1, the port has established link. when the respective auilinkup[7:1] pin is a 0, the link has failed on that port. pol[0]/auilinkup[0]/ synclk10 i/o polarity/aui link status/synchronous clock 10: indicates the polarity of port 0 in 10base-t mode (output). in aui mode, the auilinkup[0] pin of the GT-48001A are used as an input to indicate the link status which can be driven by the phy. when auilinkup[0] pin is a 1, port 0 has established link. when auilinkup[0] pin is a 0, the link has failed on port 0. in synchronous mode, this input pin carries the 10mhz synchronous clock. sclk/synclk20 i 80mhz serial clock/synchronous clock 20: used to recover the receive clock and to generate the the internal transmit clocks. in synchronous mode, this pin carries the 20mhz synchronous clock. miscellaneous interface pins leddata o led data: led indicators (link status, receive, transmit, collision, unknown, port sniffer, and half/full duplex) of each port. the data is shifted out in 128 bit long frames using the ledclk and ledstb pins. ledstb o led strobe: indicates the beginning of valid data frame on the leddata pin. ledclk o led clock: ledclk frequency is 1 mhz. during rst* assertion, ledclk fre- quency is 10 mhz. this pin is used to clock the serial data out. ledmode i led mode: when the ledmode pin is low, the led mode is compatible with the gt-48001. when high, the GT-48001A enters led mode 1. see the led interface section for a detailed description. rstqueue* i reset transmit queues: when asserted, all internal transmit and receive queues are cleared. all GT-48001A state machines are moved to their initial state. endev* i enable device: enables serial and pci ports. when asserted low, all serial ports and the pci port are active. when deasserted, the ports and the pci are disabled (see section 3.1). symbol type description
GT-48001A switched ethernet controller 12 revision 1.6 scan* i scan: this pin together with tristate* indicate the GT-48001A mode of opera- tion as follows: factory test modes are reserved and are not to be used in-system. failure to observe this restriction could result in damage to the device. tristate* i tri-state: this pin together with scan* indicate the GT-48001A mode of oper- ation as described above. diswd* i disable watchdog timer: active low. diswd* controls the enabling (high) or disabling (low) of the tx watchdog timer on all ports. disbufthr* i buffer threshold: active low. this pin externally enables or disables the buffer threshold. when high, the buffers allocated to the ports and the pci are limited to the number written in the rx buffer threshold register. when low, the buffers are dynamically allocated to the ports and the pci bus (i.e. there is no limitation on the buffers allocation.) limit4 i backoff algorithm: this pin selects the number of retransmit attempts after a collision will occur before the back-off alogorithm is restarted. when low, 16 retransmit attempts after a collision must occur before the back-off alogorithm is restarted (802.3 standard). when high, 4 retransmit attempts after a colli- sion must occur before the back-off alogorithm is restarted (more aggressive.) enelscrub* enable empty list scrubing: for testing purposes only. must be pulled high. skipinit* i skip initialization stage: active low. this pin controls the initialization stage of the GT-48001A. when asserted, the GT-48001A skips the initializa- tion stage (clearing the address table which is stored in the dram), upon the deassertion of rst*. this pin is typically used for testing and the default state is to pull this pin high. symbol type description scan* tristate* mode 1 1 normal operation 0 1 factory test mode (reserved) 1 0 the GT-48001A drives all out- puts and i/o pins to high imped- ance. 0 0 factory test mode (reserved)
GT-48001A switched ethernet controller revision 1.6 13 3. operational overview the galnet architecture family of switching devices has been defined as an extensible, scalable architecture for the switching of packetized data. the galnet architecture family currently supports ethernet (GT-48001A), fast ethernet (gt-48002a), and 100vg-anylan (gt-48003.) galileo technology will extend the innovative galnet family to include other communications standards including wan in the near future. all galnet architecture family devices act as distributed intelligent agents within a switching system. each galnet device makes switching decisions independent of other devices in the system, and can communicate information regarding the network to all other agents. this distributed processing approach is a significant performance improve- ment over switching architectures that rely on centralized switching engines or single-point address recognition devices. unlike centralized resource approaches, galnet designs can actually add packet processing capability as additional ports are added. the galnet architecture family uses a store-and-forward switching approach. store-and-forward was chosen for the following reasons: ? store-and-forward switches allow switching between differing speed media (e.g. 10basex and 100basex.) such switches require the large elastic buffers that are provided by the edo dram arrays. ? store-and-forward switches improve overall network performance by acting as a network cache, effectively buffering packets during times of heavy congestion. ? store-and-forward switches prevent the forwarding of corrupted packets by analyzing the frame check sequence (fcs) before forwarding to the destination port. a typical unmanaged galnet architecture system is extremely simple to implement as shown in figure 1 on page 6. no cpu is needed as each galnet device is intelligent and capable of sharing network information and packet data auton- omously. a cpu may be added to provide network management capability. 3.1 enabling/disabling the GT-48001A ports of the GT-48001A can be enabled and disabled depending on the combination of: ? an external hardware pin, endev* (low - device enabled, high - device disabled) ? enabledevice, bit 27 of the global control register (0 - device status based on endev*, 1 - device enabled) ? porten, bit 0 of each port control register, (0 - port disabled, 1 - port enabled) when a port is disabled, no packets will be received or transmitted from the serial ports or the pci bus. even though ports are disabled, another pci master can read from and write to the GT-48001As registers. see table 1 for enabling or disabling ports of the GT-48001A. table 1: enabling/disabling ports of the GT-48001A 3.2 basic operation the basic operation of the GT-48001A is quite simple. the GT-48001A receives incoming packets from the ethernet wire, searches in the address table for the destination mac address and then forwards the packet to the appropriate port. the destination port can be either be local (one of the GT-48001As ports) or in a different GT-48001A device that endev* pin enabledevice bit porten bit port status low 0 0 disabled low 0 1 enabled low 1 0 disabled low 1 1 enabled high 0 0 disabled high 0 1 disabled high 1 0 disabled high 1 1 enabled
GT-48001A switched ethernet controller 14 revision 1.6 resides on the same pci bus. if the destination address is not found, the GT-48001A treats the packet as a multicast packet and forward the packet to all ports of all devices in the system specified to forward unknown packets. the GT-48001A automatically learns the port number of attached network devices by examining the source mac address of all incoming packets. if the source address is not found in the GT-48001As address table, the device adds it to the table (with an indication of on which port the address resides). the GT-48001A then notifies other galnet devices in the system of the new address via a new_address message. 3.3 address learning the GT-48001A can learn up to 8k unique mac addresses. addresses are stored in the address table located in dram. the address table is managed automatically by the GT-48001A (i.e. a new address is automatically added to the address table). the GT-48001As address learning process is outlined in section 4. the address table includes information regarding target port, aging status, static/dynamic status, and flags to force processor intervention. the management cpu has the ability to insert, remove or modify the entries. 3.4 packet buffering incoming packets are buffered in the dram array. these buffers provide elastic storage for transferring data between low-speed and high-speed segments. the packet buffers are managed automatically by the GT-48001A. 3.5 packet forwarding once an address has been learned, and the packet is buffered, it must be forwarded. the packet forwarding mecha- nism for the GT-48001A is handled automatically based on the destination address. optionally, the cpu can be involved in unicast packet forwarding decisions by using intervention mode. if a cpu is utilized for system manage- ment functions, multicast packets will be forwarded to the cpu for forwarding decisions. 3.6 the galnet protocol the GT-48001A uses a proprietary inter-chip communication protocol on the pci bus known as the galnet protocol messages. the protocol consists of five groups of messages: new_address, buffer_request, start_of_packet, packet_transfer, and end_of_packet. all galnet messages are write-only . for example, a GT-48001A may request a buffer location in another galnet device by writing a buffer_request message to the target device. the target device responds by writing a start_of_packet message to the requesting GT-48001A. read transactions are strictly avoided since they tend to stall the pci bus, thereby wasting precious bandwidth. 3.7 terminology it is important to understand the basic terminology used to describe the galnet architecture family before getting into the detailed description. table 2 explains the terms used throughout this document. table 2: terminology term definition address table the address table is a data structure in the GT-48001As dram that con- tains all learned mac addresses, and routing information associated with those addresses. source address the source address (sa) is the mac address from which a received packet was sent. destination address the destination address (da) is the mac address to which a received packet was sent.
GT-48001A switched ethernet controller revision 1.6 15 device number each galnet device in a system (including the cpu, if any) has a specific device number. there are 32 possible device numbers. port number each ethernet port on a galnet device has an associated port number. the galnet device associates port numbers with the mac addresses located on those ports. table 2: terminology term definition
GT-48001A switched ethernet controller 16 revision 1.6 4. mac address learning process the GT-48001A has a self-learning mechanism for learning the mac addresses of attached ethernet devices in real time. the GT-48001A searches for the source address (sa) of an incoming packet in the address table and acts as follows: if the sa was not found in the address table (a new address), the GT-48001A waits until the end of the packet (non errored packet) and updates the address table. it also notifies the other GT-48001A devices and the cpu by sending a separate new_address message to each galnet device on the pci bus. if a cpu is enabled in the system (bit 10 of the global control register, 0x140028), the new_address message can optionally be forwarded to the cpu (bit 7 in the global control register, 0x140028). this message contains the new mac address, the device number and the port number. the new_address message format sent from one galnet device to another is described in section 10.2.1. the new_address message that is sent to the cpu is of a different format and is described in section 10.3.1. in addi- tion, the GT-48001A asserts int* to notify the cpu that the address table was modified. 1. if the sa was found, the GT-48001A compares all fields of the new_address message to the entry in the address table. if any fields differ (and the static bit in the address table is 0 1 ), the GT-48001A updates the entry with the new information in the new_address message and notifies the other GT-48001A devices and the cpu. if the device and port numbers are equal, the packet is not switched (i.e. this packet was destined for a device on the same network segment and does not require forwarding.) 2. if the sa was found in the address table, the aging bit is set. this is done to indicate to the aging software that this address was accessed recently. 4.1 address recognition the GT-48001A forwards the incoming packets to the appropriate port(s) according to destination address (da) as fol- lows: 1. if the da is a unicast address and the address was found in the address table, the GT-48001A acts as follows: ? if the port number and the device number are equal to the port/device on which the packet was received, the packet is discarded. ? if the port number is different, but the device number is equal, the packet is forwarded to the appropriate local port. ? if the device number is different, the packet is forwarded to the appropriate GT-48001A device via the pci bus. 2. if the da is a unicast address and the address was not found (unknown), the GT-48001A acts as if it the unknown packet is a multicast packet and forwards it to ports and the devices that have been programmed to receive unknown packets (bit 4 in the command register). 3. if the da is a multicast address, the packet is forwarded to all the local ports (except for the port in which the packet was received). it is also forwarded to all the other devices via the pci bus. this procedure is outlined in section 6.3. 4.2 recovery process the purpose of the recovery process is to guarantee that address tables entries in all the devices correlate. when the packet is unknown, the source GT-48001A sends a new_address message to all the devices. each device searches its own address table for the new address. more than one device can find the address, but only one device owns this address (the device number written in the address table is equal to its own device number). this particu- lar device updates the source GT-48001As address table with the new address (by in turn sending it a new_address message). 1. static address table entries cannot be modified, as described in section 4.4.
GT-48001A switched ethernet controller revision 1.6 17 4.3 address aging the GT-48001A includes hardware support for address aging, which requires the use of a cpu to be implemented. the GT-48001A gives an indication to the cpu of the relative age of an address by setting the aging bit in the address table when it receives a packet. the cpu reads the aging bit each aging period (the default from the 802.12d specification is 300 seconds) and clears the bit. if in the next period, the bit remains clear, the cpu knows that this sta- tion didn't transmit any packet in this period of time and the address can be removed from the table. note that the aging bit is set only in the GT-48001A device that received the packet; other GT-48001As in the system are not notified since, by definition, the receiving device owns the address. the only time the GT-48001A will delete an entry by itself is when a user changes the location of a station. the gt- 48001a will then automatically learn the new location of the station the next time the station sends a packet. 4.4 static addresses the GT-48001A includes support for static mac addresses. ieee 802.1d chapter 3.9.1: "static entries may be added to and removed from the filtering database under explicit management control. they are not automatically removed by any timeout mechanism". this means that when an address is selected to be static, it will not be removed from the address table during aging. during normal address recognition, if an address is static, the GT-48001A will not update its address table parameters and will not send a new_address message over the pci (if the address has changed ports.) 4.5 address recognition failure it is possible that an address recognition cycle will fail when more than 8k addresses have already been entered into the address table. in the case of an address recognition failure the packet will be treated as unknown and forwarded to all ports. an interrupt is also generated to the cpu (if any.) address recognition failures are not fatal and do not need to be handled (e.g. designers of unmanaged systems need not worry about them.) managed systems may want to clean the address table of old addresses when such a failure occurs (see section 4.4).
GT-48001A switched ethernet controller 18 revision 1.6 5. GT-48001A buffers and queues the GT-48001A incorporates nine transmit queues for the 8 ethernet ports and the pci bus port, and one common receive buffer area (see figure 2.) the receive buffers as well as the transmit queues are located in the dram along with the address table. dram address mapping in the GT-48001A is shown in table 3. the GT-48001A data struc- ture components are the following: ? receive buffer - a common rx buffer area for all ports. the buffer is divided into 304 or 992 blocks (depend- ing on the dram size) of 1.5kbytes (1536 bytes) each. each block contains the entire packet. ? rx empty list - a list of 304 or 992 bits. each bit contains the status of its appropriate receive block in the dram (empty or occupied). ? tx descriptors - a set of 9 transmit descriptor rings. each ring contains 1024 descriptors. the descriptor size is one 32-bit word and contains the block address divided by 0x600 (1.5k), the byte count and the packet type (multicast or unicast). ? read/write pointers - 9 pairs of pointers to the transmit descriptors. figure 2: GT-48001A buffers and queues read pointer write pointer 21 byte count blk addr 10 9 0 frame #0 frame #1 frame #2 rx buffer (for all ports and pci) tx descriptors: 1024 x 9 rx empty list dram GT-48001A m/u 20 frame #n
GT-48001A switched ethernet controller revision 1.6 19 table 3: GT-48001A dram address mapping 5.1 receive buffer threshold programming the number of receive buffers allocated to each port of the GT-48001A is controlled by the rxbufthr field in the rx buffer threshold register and the disbufthr* pin. the default value is 29 buffers per port for 1mb dram and 79 buffers per port for 2mb dram. if the buffer threshold is disabled (by clearing the bufthren bit in the global control register or the disbufthr* pin is held low) the GT-48001A dynamically allocates the buffers to the 8 ethernet ports and the pci bus port. in other words, there are no limits on each buffers allocation. the rx buffer threshold value can be used to tune performance during development. see table 4 for rx buffer threshold settings. if a received packet overflows the rx buffer allowance, then that packet will be discarded and the dropped packets counter will be incremented. the overflow of the rx buffer threshold is also indicated by the receive buffer full led in the serial and parallel led interfaces (rx buffer threshold must be enabled). table 4: setting the rx buffer threshold memory description 1mbyte 2mbyte rx buffers 304 buffers for 1mbyte 992 buffers for 2 mbyte 0x00000 - 0x71fff 0x00000 - 0x171fff pci tx descriptor 0x77000 - 0x088fff 0x177000 - 0x188fff pci rx descriptor 0x89000 - 0x94fff 0x189000 - 0x194fff reserved 4kbytes 0x95000 - 0x095fff 0x195000 - 0x195fff tx descriptor 0x096000 - 0x09ffff 0x196000 - 0x19ffff address table 0xa0000 - 0xfffff 0x1a0000 - 0x1fffff disbufthr* pin bufthren bit result high 1 receive buffer size is limited to the value of rxbufthr high 0 dynamic receive buffer allocation low 1 dynamic receive buffer allocation low 0 dynamic receive buffer allocation
GT-48001A switched ethernet controller 20 revision 1.6 6. packet forwarding the following sections describe the procedures for forwarding packets in the following situations: ? a unicast packet to a local port in the same galnet device (section 6.1) ? a unicast packet between galnet devices (section 6.2) ? a multicast packet to local ports in the same galnet device (section 6.3.1) ? a multicast packet between galnet devices in a system without a cpu (section 6.3.2.1) ? a multicast packet between galnet devices in a system with a cpu (section 6.3.2.2) ? a packet destined for the cpu, multicast, or unicast packet from a galnet device to the cpu (section 6.4) ? a unicast/multicast packet from the cpu to a galnet device (section 6.5) 6.1 forwarding a unicast packet to a local port the sequence for forwarding a unicast packet to a local port (port in the same GT-48001A) is as follows: 1. the incoming packet is fed to the rx fifo (there is an 8x32-bit rx fifo per port) and is transferred to an empty block in the receive buffer area of dram. 2. in parallel, an address recognition cycle is performed for both the da and the sa. the GT-48001A uses the das corresponding port number to queue the packet to the appropriate local port. 3. at the end of an error-free packet transfer, packet information is written to the appropriate ports transmit descriptor. this information includes the byte count and the receive buffer block address which is pointed to by the write pointer. 4. the write pointer of the outgoing ports transmit descriptor is incremented. the target galnet device transmits whenever the write pointer is not equal to the read pointer. 5. at the end of the packet transmit process, the target galnet device increments the read pointer and clears the appropriate bit in the empty list. 6.2 forwarding a unicast packet to a port in a different galnet device the sequence for forwarding a unicast packet to a port in a different galnet device located on the pci bus is as fol- lows: 1. the incoming packet is fed to the rx fifo and is transferred to an empty block in the receive buffer area of dram. 2. in parallel, an address recognition cycle is performed for both the da and the sa. the GT-48001A uses the das corresponding port number and device number to queue the packet to the appropriate galnet device and port. 3. at the end of an error-free packet transfer, packet information is written to the pcis transmit descriptor. this infor- mation includes the byte count and receive buffer block address which is pointed to by the write pointer. when the pcis transmit descriptors write pointer is not equal to the read pointer, the source galnet device sends a buffer_request message (section 10.2.2) to the appropriate target galnet device indicating that there is a packet for transmission across the pci bus. 4. the target galnet device receives this message and allocates a buffer in its dram. this target device then sends a start_of_packet message (section 10.2.3) back to the source GT-48001A indicating it is ready to receive the packet. 5. the source GT-48001A transfers the packet with the packet_transfer message (section 10.2.4) using pci master operations in multiple eight 32-bit bursts. the packet is buffered in the receive buffer area of the target devices dram. after the entire packet has been transmitted, the source GT-48001A performs an additional write transaction by sending the end_of_packet message (section 10.2.5) indicating completion of the packet transfer. this message contains the byte count, the target port number, the rx block address, and the packet
GT-48001A switched ethernet controller revision 1.6 21 type. the source GT-48001A also clears the appropriate bit in its empty list. 6. some packet information included in the end_of_packet message is written to the appropriate transmit descriptor in the target device. this information includes the byte count and the receive buffer address which is pointed to by the write pointer. 7. the write pointer of the outgoing ports transmit descriptor is incremented. the target galnet device transmits whenever the write pointer is not equal to the read pointer. 8. at the end of the packet transmit process, the target galnet device increments the read pointer and clears the appropriate bit in the empty list. 6.3 forwarding a multicast packet the GT-48001A forwards multicast packets to all local ports and devices using the same mechanism as described for unicast packets. the GT-48001A has the ability to forward multicast packets to a management cpu for intervention routing, if desired. 6.3.1 local ports for local ports in the same device, the packet is queued to all transmit ports except for the port which the packet arrived and the packet is transferred with the same procedure outlined in section 6.1 to each port. 6.3.2 between galnet devices forwarding multicast packets to other galnet devices is handled differently depending if a cpu is disabled or enabled in the system or not. 6.3.2.1 cpu disabled systems which do not utilize a cpu (bit 10 of the global control register, 0x140028, is not set) will automatically for- ward multicast packets to all of the local ports and devices with the following procedure: 1. the incoming packet is fed to the rx fifo and is transferred to an empty block in the receive buffer area of dram. 2. in parallel, an address recognition cycle is performed for the sa. the da marks this packet as a multicast packet. at the end of a good packet transfer, packet is forwarded to all of the local ports according to section 6.3.1. this multicast packet is also forwarded to the other galnet devices in the system with the same procedure as forward- ing a unicast packet from one device to another. this procedure is outlined in section 6.2. there is a single, sepa- rate, multicast packet transfer from the source GT-48001A to each of the galnet devices in the system. bit 21 of data 0 of the buffer_request message (section 10.2.2) will be set to indicate this is a multicast packet. 6.3.2.2 cpu enabled systems which utilize a cpu (bit 10 of the global control register, 0x140028, is set), will always have multicast pack- ets forwarded to the cpu. this allows the cpu to intervene, if necessary, and redirect or update the multicast packet before forwarding. control of forwarding multicast packets to all of the ports is set by bit 22 of the global control regis- ter. the default setting is to forward all multicast packets to all of the ports in the system as well as the cpu. if this bit is set, multicast packets will go only to the cpu. assuming bit 22 is not set and all multicast packets are forwarded to the cpu as well as all of the ports, the procedure for handling multicast packets is as follows: 1. the incoming packet is fed to the rx fifo and is transferred to an empty block in the receive buffer area of dram.
GT-48001A switched ethernet controller 22 revision 1.6 2. in parallel, an address recognition cycle is performed for both the da and the sa. the da marks this packet as a multicast packet. at the end of a good packet transfer, packet is forwarded to all of the local ports according to sec- tion 6.3.1. this multicast packet is also forwarded to the other galnet devices in the system with the same proce- dure as forwarding a unicast packet from one device to another. this procedure is outlined in section 6.2. there is a single, separate, multicast packet transfer from the source GT-48001A to each of the galnet devices in the sys- tem. bit 21 of data 0 of the buffer_request message (section 10.2.2) will be set to indicate this is a multicast packet. 3. packet information is also written to the pcis transmit descriptor which instructs the GT-48001A to send this multi- cast packet to the cpu. this multicast packet is then forwarded directly to the cpu with the procedure outlined in section 6.4. again, if bit 22 is set, all multicast packets will only be forwarded to the cpu and not to the local ports, nor other ports of other galnet devices. the cpu can then decide to what ports the multicast packet should be sent to. only one packet needs to be sent to each galnet device and each device will automatically forward the packet only to the ports that the cpu tagged for that specific multicast packet. these ports are tagged in bits [29:22] of the end_of_packet message. 6.4 forwarding a packet to the cpu directly systems which utilize a cpu (bit 10 of the global control register, 0x140028, is set) will forward certain packets directly to the management cpus memory. these packets include: ? unicast packets destined for the cpu (device number in the address table is equal to the cpu number) ? multicast packets ? unknown packets (if set by bit 6 in the global control register, 0x140028) ? bpdu messages ? sniffer packets when the cpu is the target sniffer ? ease packets the GT-48001A contains two pointers to a sixteen block buffer area in the cpus memory space. the registers are called the cpu base address (cba) and cpu base address shadow (cbas.) these registers are physically located at the same address in the GT-48001A (0x140034). the first write to this register updates the cba register, the second write updates the shadow register (cbas). figure 3 shows the data structure in the cpu memory.
GT-48001A switched ethernet controller revision 1.6 23 figure 3: cpu memory data structure the data structure components are the following: ? cpu base address register (cba) 1 - a register that points to the beginning of a sixteen block area in cpu memory. ? cpu base address shadow register (cbas) - a second register that holds a pointer to a second sixteen block area in the cpu main memory. the value in the shadow register propagates into the base address reg- ister after sixteen packets are transferred to the main memory. ? buffer area - the cpu buffer area consists of 16 blocks of 2kbytes each. the first word (word #0) of each block contains the sniffer indication [31], ease indication [23:15], source port number [14:12], byte count (bits [11:1]), and the valid bit (bit 0). these bits are written as the end_of_packet (section 10.3.10) mes- sage transferred from the source GT-48001A to the cpu at the end of a valid packet transfer. words 1 to 7 are left empty for user purposes. the communication between the GT-48001A and the cpu follows this sequence: 1. upon initialization, cpu updates the cba (1st write to 0x140034). 2. following the initial write to the cba, the cpu updates the cbas (2nd write to 0x140034). 3. GT-48001A transfers 16 packets to the cpu main memory and asserts the int* at the end of each packet transfer. 4. the cpu must count sixteen interrupts and then update the shadow register in the GT-48001A (write to 0x140034). also, the bufwrap interrupt can be checked instead of counting sixteen interrupts. in other words, the cpu must update 0x140034 once after 16 packets have been transferred from the GT-48001A to the cpu. this single word write after sixteen packets have been transferred to the cpu are to update the shadow register only. 1. assuming cba and cbas have already been written to, any writes to 0x140034 will update the cbas register only. in other word s, cba can only be updated on the first write, and after 16 packets have been written to the cpu where the cba will take the valu e of the cbas. block #1 block #2 block #16 0 1 2 3 n-1 n 31 0 word#8, base address register byte#32 GT-48001A cpu memory base address shadow s 31 ease 23 15 sp 14 12 bc v 11 1 0 word#0, byte#0
GT-48001A switched ethernet controller 24 revision 1.6 steps 3-4 are repeated. the packet transfer to the cpu is done as follows: 1. the incoming packet is fed to the rx fifo and is transferred to an empty block in the receive buffer area of dram. 2. in parallel, an address recognition cycle is performed for both the da and the sa. if the packet is resolved to be a packet of the type listed at the beginning of this section, packet information is written to the pcis transmit descrip- tor. this information includes the byte count and receive buffer block address which is pointed to by the write pointer. when the pcis transmit descriptors write pointer is not equal to the read pointer, the source GT-48001A sends the packet directly to the appropriate block in the cpu main memory with the packet_transfer (section 10.3.7) message using pci master operations in multiple eight 32-bit bursts. the data is entered starting at the 8th word (33rd byte) of the next free block. words 1 to 7 are left empty for user purposes. the address of this packet transfer is based upon the cba. 3. at the end of the packet transfer, the source GT-48001A sends the end_of_packet message (section 10.3.10) to the first word of the block (word #0). it also sends an interrupt via int* to the cpu, increments the read pointer, and clears the appropriate bit in its empty list. the cpu now has the packet buffered in its buffer area. this gives the cpu the ability to intervene in the packets rout- ing or to modify the contents of the packet. 6.5 forwarding a packet from the cpu to a galnet device the sequence for forwarding a packet from the cpu to a port in a galnet device is the same for unicast and multicast packets. the procedure is as follows: 1. the cpu sends a buffer_request message (section 10.3.4) to the appropriate target galnet device indicat- ing that there is a packet ready for transmission across the pci bus. 2. the target galnet device receives this message and allocates a buffer in its dram. this target device then sends a start_of_packet message (section 10.3.5) back to the cpu indicating it is ready to receive the packet. this start_of_packet message is sent to a cpu buffer location indicated by the start packet base address regis- ter (0x140038). this address points to a cpu buffer area that can hold up to 32 start_of_packet messages. the cpu must poll this structure to know when a target GT-48001A is ready to receive a packet, and to what address the packet should be sent. if the byte count field in the start_of_packet message is 0, then the cpu should not write the packet_transfer message nor the end_of_packet message to the device. this indi- cates that either the buffers are full in the target galnet device, or that the link is down on the target port. 3. the cpu transfers the packet with the packet_transfer message (section 10.3.9) using pci master opera- tions in multiple eight 32-bit bursts. the packet is buffered in the receive buffer area of the target devices dram. after the entire packet has been transmitted, the cpu performs an additional write transaction by sending the end_of_packet message (section 10.3.12) indicating completion of the packet transfer. this message con- tains the byte count, the target port number, the rx block address, and the packet type. it also includes a bit which commands the GT-48001A to generate crc for this out-going packet or not. if the packet is a multicast packet, the packet will only be forwarded to the ports tagged in bits [29:22] of the end_of_packet message (the cpu should never write 1 to bits 29:22 that had 0 in in the same bits of the start_of_packet mes- sage.) 4. some packet information included in the end_of_packet message is written to the appropriate transmit descriptor in the target device. this information includes the byte count and the receive buffer address which is pointed to by the write pointer. 5. the write pointer of the outgoing ports transmit descriptor is incremented. the target galnet device transmits whenever the write pointer is not equal to the read pointer. 6. at the end of the packet transmit process, the target galnet device increments the read pointer and clears the appropriate bit in the empty list.
GT-48001A switched ethernet controller revision 1.6 25 6.6 crc generation as mentioned in section 6.5, the GT-48001A also includes a crc generator for packets sent out by the cpu. the crc generator enhances system performance by implementing the cpu intensive packet crc calculation in hard- ware. note that crc generation is not required for packets transferred between galnet devices, since the crc is already appended to these packets. crc generation for cpu generated packets is enabled through the encrc bit in the global control register (bit 29). in addition, the cpu must set the gencrc bit in the end_of_packet (section 10.3.12) message sent to the gt- 48001a at the completion of forwarding the packet. 6.7 tx watchdog timer the GT-48001A includes a transmit watchdog timer for each transmit queue. the default value of the timer is 630 msec; the range is 105 to 1575 msec in steps of 105 msec. the timer measures the time between the transmission of two consecutive outgoing packets. when the timer expires, the GT-48001A clears the appropriate used blocks and sends an interrupt to the cpu via int*. the transmit watchdog timer prevents transmission problems on one port from blocking traffic to other ports. in man- aged systems, the timers also provide a mechanism to notify the cpu of a possible system problem. the tx watchdog timer can be externally disabled by holding the diswd* pin low. the default is to leave the tx watchdog timer enabled (diswd* high.)
GT-48001A switched ethernet controller 26 revision 1.6 7. device table operation the galnet architecture supports a maximum of 32 devices per system. each device needs to know of the existence of all other galnet devices in the system in order to communicate information and packet data. the device table is a 32- bit register that uses a single bit for each possible device number to indicate its presence/absence in the system. 7.1 automatic device table initialization upon reset, each GT-48001A in the system sets all of its device table bits to 1. this is essentially a guess by the GT-48001A that all device numbers are in use. in a system with any pci device that is not a galnet device (cpu, graphics card, etc.), it recommended that the cpu initialize the device table before the galnet device is enabled (or before packet transmission starts). specific device table bits are cleared, and the corresponding device numbers are logically eliminated from the sys- tem, by: ? the receipt of a pci master abort when the GT-48001A attempts to access the corresponding device number ? management cpu programming device table cleaning is handled automatically by each device upon receipt of the first unknown packet following a reset. this process discovers all other galnet devices in the system without processor intervention: 1. the GT-48001A receives the first good packet from any ethernet port and places it in the buffer area in dram. 2. since the address table is cleared (immediately following reset) the packet must be forwarded to all ports, including those located on other galnet devices. 3. the GT-48001A attempts to allocate a buffer in all 31 possible additional galnet devices in the system. this is done by issuing 31 buffer_request messages- one to every possible device in the system. 4. each buffer_request message that fails due to a pci master abort results in the corresponding device num- ber bit being cleared in the device table. a pci master abort only occurs when there is no target device at the requested address (i.e. the target device doesnt exist.) 7.2 manual device table initialization alternatively, the cpu can notify each GT-48001A of the existence of the galnet devices. this is done by setting the by setting bit 2 in the global control register (devtabmod.) in this mode, the cpu is responsible for notifying the gt- 48001a of the existence of all gt-4800x devices in the system. the cpu does this by writing the appropriate values to each device table. manual mode must be used when there are multiple pci buses in the system separated via pci-to-pci bridges. 7.3 programming device numbers the device number for each galnet device is set after reset by the values on the daddr[4:0] pins. the device num- ber can be changed by writing the new device number to [26:22] of the dram/internal register base address register at 0x010. typically, once the number of a device has been changed, the device table of all devices in the system will also need to be updated.
GT-48001A switched ethernet controller revision 1.6 27 8. unicast intervention mode the GT-48001A supports a powerful feature called intervention mode for unicast packets. intervention in unicast traffic is optional per mac address. each entry in the address table includes an intervention bit for the destination address (bit 62) and the source address. when an intervention mode bit is set, the GT-48001A will not forward the packet auto- matically to the destination device. instead, the galnet device will send a buffer_request message (section 10.3.3) to cpu memory. the buffer_request messages will be sent to the buffer area in the cpu main memory which contains 256 entries of dual 32-bit words. the location of this cpu memory is specified by the cpu intervention base address at 0x140048. the buffer area is pointed to by this base address register and a shadow register at this same offset. the buffer_request message includes information about the routing of the packet (source and tar- get port/device numbers). the cpu then has the option to: ? discard the packet ? forward the packet to a specific device ? request the packet be transferred to cpu buffer memory figure 4 shows a unicast packet transfer using intervention mode. figure 4: unicast packet transfer with intervention the sequence illustrated is as follows: 1. the incoming packet is fed to the rx fifo and transferred to an empty block in the receive buffer area of dram. 2. if a corresponding intervention bit is set, the device sends a buffer_request message (section 10.3.3) to the cpus intervention base address. the buffer_request includes the source port and the source buffer address the cpu then has the following options: 1. discard the packet. ? the cpu sends a start_of_packet message (section 10.3.6) to the source device with the byte count field cleared with all 0s (arrow #3). 2. forward the packet to a port in the same device cpu pci bus GT-48001A dram GT-48001A dram 1 23 5 6 4 7 dram messages packets
GT-48001A switched ethernet controller 28 revision 1.6 ? the cpu sends a buffer_request (section 10.2.2) to back to the same device where the target device number is equal to the source device number. the correct port number is also specified. this buffer_request is of the same format that is used between galnet devices (arrow #2). ? the packet is then sent out on a port of same source device as specified by the cpu. 3. forward the packet to a different device. ? the cpu sends a buffer_request (section 10.2.2) to the destination device. this buffer_request is of the same format that is used between galnet devices and uses the source device number as the source device instead of the cpu device number (arrow #4). ? the target device allocates a buffer and sends a start_of_packet message (section 10.2.3) to the source device (arrow #5). ? the source device transfers the packet with the packet_transfer message (section 10.2.4) followed by an end_of_packet message (section 10.2.5) to the target device (arrow #6). 4. take the packet. ? the cpu sends a start_of_packet message (section 10.3.6) back to the source galnet device. the tar- get device in this message is the cpu number. the source GT-48001A device transfers the packet with the packet_transfer message (section 10.3.8) using pci master operations in multiple eight 32-bit bursts. the first data word of the packet will be written to the second word of the buffer. the first word is left empty for the end_of_packet message. note: unicast packets tagged for intervention mode are not forwarded to the same buffer space that is specified by the cpu buffer base address (cba) at offset 0x140034). ? at the end of the packet transfer, the source GT-48001A sends the end_of_packet message (section 10.3.11) to the first word of the buffer. it also sends an interrupt via int* to the cpu, and clears the appropriate bit in its empty list. the cpu buffer now contains the packet whose destination address was marked for intervention. the cpu can per- form a number of functions with the packet including layer 3 routing, security, virtual lan support, filtering and manage- ment. after the cpu has modified the packet, the packet can be transferred to the appropriate target galnet device with the procedure outlined in section 6.5. 8.1 unicast intervention mode address space prior to the cpu receiving unicast packets tagged for intervention mode, an address space for galnet devices to for- ward packets to must be allocated. this address space should reside in the galnet protocol region (see section 10.1). therefore, this buffer region will have a similar address to a galnet device. the buffer address format is shown in table 5. table 5: buffer address for unicast intervention mode packets pci bits description address [31:27] [26:22] [21] [20:0] galnet protocol region cpu device number (bits [12:8] in 0x140030) 1 (dram) dram location
GT-48001A switched ethernet controller revision 1.6 29 9. address table the GT-48001As address table resides in the local dram array. figure 5 shows the address table structure. the address table structure occupies approximately 320kbytes and is entirely controlled and initialized by the GT-48001A. following reset, the GT-48001A initializes the address table by setting all valid bits in the table to 0. every new address that is learned has its entrys valid bit set to 1. in order to remove an address entry from the table, only the skip bit should be set to 1 (the valid bit should not be modified). modifications to the address table are normally made through galnet protocol message requests by the cpu. it is possible to access the address table directly, however, this mode is not recommended. please contact galileo if you feel your application requires direct address table access.
GT-48001A switched ethernet controller 30 revision 1.6 figure 5: address table format 8k addr[0:47] dev# 51 1 0 2 50 58 port# st 55 56 1 a sk v 3 59 r m id is 63 62 61 60 address table bits description bit description v valid: indicates this entry is taken or previously was taken 0 - not valid 1 - valid sk skip - indicates if this entry is currently being used 0 - active entry, do not skip 1 - inactive entry, overwriting this entry is allowed a aging - this bit is used for the aging process 0 - cleared by the cpu 1 - set by the GT-48001A upon receiving a packet from the station corresponding to this entry addr 48 bit mac address dev# device number - 5 bit galnet device number indicating which of a maximum of 32 devices in the system is associated with this address. port# port number - 3 bit port number indicating which of the eight ports in a GT-48001A is asso- ciated with this address. r reserved st static - indicates whether an entry can be modified or not 0 - the entry can be modified 1 - the entry is static, the dev# and port# cannot be modified m multiple - meaningful when bit st is set 0 - forward this packet only to the destination port 1 - forward this packet to all ports (as unknown) id intervention for destination addresses 0 - dont activate intervention mode for this address as a destination 1 - activate intervention mode is intervention for source addresses 0 - dont activate intervention mode for this address as a source 1 - activate intervention mode
GT-48001A switched ethernet controller revision 1.6 31 10. galnet messaging protocol the galnet messaging protocol is comprised of the messages passed over the pci bus between ? galnet family members ? a galnet family member and a cpu .the messages are encoded in both the address and the data phases of the pci transfers. five groups of messages that are currently defined: new_address, buffer_request, start_of_packet, packet_transfer, and end_of_packet. galnet messages are write-only (request/response). for example, a galnet device that needs to transfer data to another galnet chip starts the transfer by requesting a buffer (buffer_request) from the target. the target responds with an address to which the packet should be transferred to (start_of_packet). the galnet messaging protocol allows messages to be interleaved. for example, a device may send out multiple buffer_request messages to other devices before receiving a start_of_packet message reply. write only messaging was used since it better utilizes pci bus bandwidth. reads on the pci bus tend to stall the bus, and the reading device thereby degrading overall system performance. please note that there are subtle differences in the galnet message format when transferring messages between devices (section 10.2) and between a device and a cpu (section 10.3). 10.1 galnet protocol region all galnet devices in a system must reside within a single 128mbyte region in the pci memory address space known as the galnet protocol region (gpr). the base address of the gpr is set in bits 31:27 of the dram/internal base address register at offset 0x10 in the GT-48001As pci configuration header. 1 all galnet devices in a system must have the same value in this field. galnet devices default to a value of 00001 in the gpr bits following reset. each galnet device in the system occupies a separate 4mbyte slice of the galnet protocol region. this slice is decoded by the device number field in the dram/internal base address register (bits 26:22). the individual devices address space is further divided by the dram/register bit (bit 21). this bit determines whether an access to a target device is directed to the dram array or to the registers. 1. offset 0x10 in the pci configuration register is known as base address register 0 for standard pci devices.
GT-48001A switched ethernet controller 32 revision 1.6 figure 6: galnet protocol region and address decoding pci address space galnet protocol region (128mbytes) device o device 1 devices 2-30 device 31 bits 31 - 27 bits 26 - 22 gpr base addr device # internal registers dram array bit 21 dram/regs bits 20 - 0 dram or register address inside device 1 pci bus address
GT-48001A switched ethernet controller revision 1.6 33 10.2 galnet messages between devices the five groups of galnet messages as described in the sections below are sent from one galnet device to another. the data format for all galnet messages is little-endian , which is the pci standard. 10.2.1 new_address message between galnet devices a message sent from one galnet device to another to alert of a new address. the new_address message may also be posted as a 'question' to other galnet devices during the recovery pro- cess (see section 4.2 on page 16). the indication is via the address unknown/new address bit (bit 29). if bit 29 is clear, then the new_address message is a 'question'. when bit 29 is set, the message indicates a 'real' address to put into the target devices address tables. the new_address message must be transferred in a burst of three words over the pci. table 6: new_address message between galnet devices pci bits description address [31:27] [26:22] [21] [20:18] [17:0] galnet protocol region target device number 0 (internal registers) 100 (new_address message) 0 data 0 [31:3] [2] [1] [0] mac address [19:47] aging skip valid data 1 [31] [30] [29] [28] [27] [26:24] [23:19] [18:0] 1 static address unknown/new address multiple 0 port number device number mac address [0:18] data 2 [24] [25] intervention mode for destination address intervention mode for source address
GT-48001A switched ethernet controller 34 revision 1.6 10.2.2 buffer_request message between galnet devices a message sent from a source galnet device to a target galnet device to request a buffer. 10.2.3 start_of_packet message between galnet devices a message from a target galnet device to the source galnet device which contains the empty receive buffer address. the start_of_packet message must be transferred in a burst of two words over the pci. table 7: buffer_request message between galnet devices pci bits description address [31:27] [26:22] [21] [20:18] [17:13] [12:0] galnet protocol region target device number 0 (internal registers) 101 (buffer_request message) source device number 0 data 0 [31] [30] [29:28] [27:25] [24:22] [21] [20:10] [9:0] sniffer (0-sniffer type message) unknown (0-unknown message) 0 source port number target port number multicast/unicast (0-unicast) byte count source buffer address (divided by 0x600) table 8: start_of_packet message between galnet devices pci line description address [31:27] [26:22] [21] [20:18] [17:0] galnet protocol region source device number 0 (internal registers) 110 (start_of_packet message) 0 data 0 [31] [30] [29:22] [21] [20:10] [9:0] sniffer (0 - sniffer type message) 0 target port number (1bit per each port; bit 22 - port 0, bit 23 - port 1 etc.) multicast/unicast (0-unicast) byte count target buffer address (divided by 0x600) data 1 [31:18] [17:15] [14:5] [4:0] 0 source port number source buffer address (divided by 0x600) target device number
GT-48001A switched ethernet controller revision 1.6 35 10.2.4 packet_transfer message between galnet devices a burst of up to 8 32-bit words from the source galnet device to the target galnet device which contains the packet. the packet_transfer message can be transferred using any burst size over the pci. the galnet device uses a burst of 8 words. 10.2.5 end_of_packet message between galnet devices a message from the source galnet device to the target galnet device which indicates the end of the packet. table 9: packet_transfer message between galnet devices pci line description address [31:27] [26:22] [21] [20:0] galnet protocol region target device number 1 (dram) dram location data 0 [31:0] data 0 ---- ---- ---- ---- data 7 [31:0] data 7 table 10: end_of_packet message between galnet devices pci line description address [31:27] [26:22] [21] [20:18] [17:0] galnet protocol region target device number 0 (internal registers) 111 (end_of_packet message) 0 data 0 [31] [30] [29:22] [21] [20:10] [9:0] crc (0 - do not append, 1 - append) always 0, galnet never appends crc 0 target port number (1bit per each port; bit 22 - port 0, bit 23 - port 1 etc.) multicast/unicast (0-unicast) byte count target buffer address (divided by 0x600)
GT-48001A switched ethernet controller 36 revision 1.6 10.3 galnet messages between a galnet device and a cpu when a management cpu is used in a galnet switch system, bit 10 (cpuen) of the global control register, 0x140028, must be set. the five groups of galnet messages described in the sections below are sent from one galnet device to a cpu and from a cpu to a galnet device. 10.3.1 new_address message (galnet to cpu) a message from a galnet device to the cpu that contains information about a new mac address. bit 7 (forwnewadd) of the global control register (0x140028) must be set. table 11: new_address message (galnet to cpu) the new_address message must be transferred in a burst of two words over the pci from a galnet device to the cpu. pci bits description address [31:8] [7:3] [2:0] new_address base address (offset: 0x14003c) offset counter (32 total entries) 000 data 0 [31:3] [2] [1] [0] mac address [19:47] 1 0 0 data 1 [31] [30] [29] [28] [27] [26:24] [23:19] [18:0] 1 reserved address unknown/new address (0 - unknown, 1 - new address message) reserved reserved port number device number mac address [0:18]
GT-48001A switched ethernet controller revision 1.6 37 10.3.2 new_address message (cpu to galnet) a message from the cpu to a galnet device that contains information about a new mac address. table 12: new_address message (cpu to galnet) the new_address message must be transferred in a burst of three words over the pci. data 2 must be sent when sending the new_address message. after every new_address message sent by the cpu, a dummy new_address message (with a non existing mac address) should be sent with data2 cleared (all 0s). the dummy mac address can be all zeros or another mac address that doesn't exist in the network. pci bits description address [31:27] [26:22] [21] [20:18] [17:0] galnet protocol region target device number 0 (internal registers) 100 (new_address message) 0 data 0 [31:3] [2] [1] [0] mac address [19:47] aging skip valid (should always be 1) data 1 [31] [30] [29] [28] [27] [26:24] [23:19] [18:0] 1 static address unknown/new address (0 - unknown, 1 - new address message) multiple 0 port number device number mac address [0:18] data 2 [24] [25] intervention mode for destination address intervention mode for source address
GT-48001A switched ethernet controller 38 revision 1.6 10.3.3 buffer_request message (galnet to cpu) a message from the source galnet device to the target cpu to request a buffer . this message is only used when a unicast packets destination address is marked for intervention mode and will be forwarded to the cpu buffer. table 13: buffer_request message (galnet to cpu) the buffer_request message must be transferred in a burst of two words over the pci. 10.3.4 buffer_request message (cpu to galnet) a message from the source cpu to the target galnet device to request a buffer . table 14: buffer_request message (cpu to galnet) pci bits description address [31:11] [10:3] [2:0] cpu intervention base address (0ffset: 0x140048) offset counter (256 total entries) 000 data 0 [31] [30] [29:28] [27:25] [24:22] [21] [20:10] [9:0] sniffer (0-sniffer type message) unknown (0-unknown destination address) 0 source port number target port number multicast/unicast (0-unicast) byte count source buffer address (divided by 0x600) data 1 [31:29] [28:24] [23:0] 0 target device number 0 pci bits description address [31:27] [26:22] [21] [20:18] [17:13] [12:0] galnet protocol region target device number 0 (internal registers) 101 (buffer_request message) source cpu device number (bits [12:8] in 0x140030) 0 data 0 [31] [30] [29:28] [27:25] [24:22] [21] [20:10] [9:0] sniffer (0-sniffer type message) unknown (0-unknown destination address) 0 reserved target port number multicast/unicast (0-unicast) byte count reserved
GT-48001A switched ethernet controller revision 1.6 39 10.3.5 start_of_packet message (galnet to cpu) a message from a target galnet device to the cpu which contains the target buffer address. table 15: start_of_packet message (galnet to cpu) the start_of_packet message must be transferred in a burst of two words over the pci. 10.3.6 start_of_packet message (cpu to galnet) a message from the target cpu to the source galnet device which contains the empty buffer address. this message will only be sent when the galnet devices needs to forward a unicast packet to the cpu via intervention mode. table 16: start_of_packet message (cpu to galnet) the start_of_packet message must be transferred in a burst of two words over the pci. pci bits description address [31:8] [7:3] [2:0] start_of_packet base address (0x140038) offset counter (32 total entries) 000 data 0 [31] [30] [29:22] [21] [20:10] [9:0] sniffer (0 - sniffer type message) 0 target port number (1bit per each port; bit 22 - port 0, bit 23 - port 1 etc.) multicast/unicast (0-unicast) byte count target buffer address (divided by 0x600) data 1 [31:0] 0 pci bits description address [31:27] [26:22] [21] [20:18] [17:0] galnet protocol region source device number 0 (internal registers) 110 (start_of_packet message) 0 data 0 [31] [30] [29:22] [21] [20:10] [9:0] sniffer (0 - sniffer type message) 0 reserved multicast/unicast (0-unicast) byte count target buffer address (divided by 0x600) data 1 [31:18] [17:15] [14:5] [4:0] 0 source port number source buffer address (divided by 0x600) target cpu device number (bits [12:8] in 0x140030)
GT-48001A switched ethernet controller 40 revision 1.6 10.3.7 packet_transfer message (galnet to cpu 16 block buffer) a burst of up to 8 32-bit words from the source galnet device to the target cpu buffer which contains the packet. this message is used when the galnet device forwards one of the following packets directly to the cpu 16 block buffer: ? unicast packets destined for the cpu (device number in the address table is equal to the cpu number) ? multicast packets ? unknown packets (if set by bit 6 in the global control register, 0x140028) ? bpdu messages ? sniffer packets when the cpu is the target sniffer ? ease packets the data is entered starting at the 8th word (33rd byte) of the next free block. words 1 to 7 are left empty for user pur- poses. the address of this packet transfer is based upon the cpu buffer base address. table 17: packet_transfer message (galnet to cpu) the packet_transfer message can be transferred using any burst size over the pci. the galnet device uses a burst of 8 words. pci bits description address [31:15] [14:11] [10:2] [1:0] cpu buffer base address (0x140034) offset counter (16 total blocks) address within the buffer 0 data 0 [31:0] data 0 ---- ---- ---- ---- data 7 [31:0] data 7
GT-48001A switched ethernet controller revision 1.6 41 10.3.8 packet_transfer message (galnet to cpu in unicast intervention mode) a burst of up to 8 32-bit words from the source galnet device to the target cpu buffer which contains the unicast packet whose address is tagged for intervention mode. the first data word of the packet will be written to second word of the buffer. the first word is left empty for the end_of_packet message. table 18: packet_transfer message (galnet to cpu) the packet_transfer message can be transferred using any burst size over the pci. the galnet device uses a burst of 8 words. 10.3.9 packet_transfer message (cpu to galnet) a burst of up to 8 32-bit words from the source cpu buffer to the target galnet device which contains the packet. table 19: packet_transfer message (cpu to galnet) the packet_transfer message can be transferred using any burst size over the pci. it is recommended to use a burst of 8 words. pci bits description address [31:27] [26:22] [21] [20:0] galnet protocol region cpu device number (bits [12:8] in 0x140030) 1 (dram) dram location data 0 [31:0] data 0 ---- ---- ---- ---- data 7 [31:0] data 7 pci bits description address [31:27] [26:22] [21] [20:0] galnet protocol region target device number 1 (dram) dram location data 0 [31:0] data 0 ---- ---- ---- ---- data 7 [31:0] data 7
GT-48001A switched ethernet controller 42 revision 1.6 10.3.10 end_of_packet message (galnet to cpu 16 block buffer) a message from the source galnet device to the cpu which indicates the end of the packet. this message is used when the galnet device forwards one of the following packets directly to the cpu 16 block buffer: ? unicast packets destined for the cpu (device number in the address table is equal to the cpu number) ? multicast packets ? unknown packets (if set by bit 6 in the global control register, 0x140028) ? bpdu messages ? sniffer packets when the cpu is the target sniffer ? ease packets the end_of_packet message is written to the first word of the buffer. table 20: end_of_packet message (galnet to cpu 16 block buffer) 10.3.11 end_of_packet message (galnet to cpu in unicast intervention mode) a message from the source galnet device to the cpu which indicates the end of a unicast packet transfer to the cpu in intervention mode. the end_of_packet message is written to the first word of the buffer. table 21: end_of_packet message (galnet to cpu in unicast intervention mode) pci bits description address [31:15] [14:11] [10:0] cpu buffer base address (0x140038) offset counter (16 total blocks) 0 (always to the first word) data 0 [31] [30:24] [23:16] [15] [14:12] [11:1] [0] sniffer packet reserved ease sample (port0, bit 16; port7, bit 23) ease sample is an original packet to cpu source channel number byte count valid bit pci bits description address [31:27] [26:22] [21] [20:0] galnet protocol region cpu device number (bits [12:8] in 0x140030) 1 (dram) 0 (always to the first word) data 0 [31] [30:24] [23:16] [15] [14:12] [11:1] [0] sniffer packet reserved ease sample (port0, bit 16; port7, bit 23) ease sample is an original packet to cpu source channel number byte count valid bit
GT-48001A switched ethernet controller revision 1.6 43 10.3.12 end_of_packet message (cpu to galnet) a message from the source cpu to the target galnet device which indicates the end of the packet. table 22: end_of_packet message (cpu to galnet) pci bits description address [31:27] [26:22] [21] [20:18] [17:0] galnet protocol region target device number 0 (internal registers) 111 (end_of_packet message) 0 data 0 [31] [30] [29:22] [21] [20:10] [9:0] crc (0 - do not append, 1 - append) 0 target port number (1bit per each port; bit 22 - port 0, bit 23 - port 1 etc.) multicast/unicast byte count target buffer address (divided by 0x600)
GT-48001A switched ethernet controller 44 revision 1.6 11. pci bus operation the GT-48001A can act as either a master initiating a pci bus operation, or as a target responding to a pci bus oper- ation. the GT-48001A is enabled to both master the pci bus and respond to memory accesses after reset. the GT-48001A has two sets of internal registers that are accessible through the pci interface. internal control regis- ters for the GT-48001A are memory mapped and accessible through standard pci read/write operations. pci control registers are accessible through pci configuration cycles. 11.1 pci configuration header registers the GT-48001As pci configuration registers are located in the standard pci configuration header locations. access to these registers is through pci configuration reads/writes with the idsel signal asserted. pci configuration registers control pci functions and return pci information (device/vendor id, etc.) 11.2 accessing dram and internal registers through the pci interface all GT-48001A internal control registers and the local dram are mapped into pci memory space. the GT-48001A looks at pci address bits 31:22 to determine if it is the target for the current cycle. this results in a decode region of 4mbytes per GT-48001A. bit 21 of the address is used by the GT-48001A to subdecode on-chip between accesses to dram and accesses to the internal registers. bits 20:0 are used to select a specific register or memory location. reg- ister addresses given in this document refer to the value of bits 20:0 in the pci address. the GT-48001A expects data in little-endian format, as is required by the pci specification. the GT-48001A acts as a medium speed decide device, returning devsel* in 2 clocks. 11.3 pci bandwidth/performance issues the pci bus has an ideal maximum bandwidth of just under 132mbytes/sec (about 1 gigabit per second.) in systems with many galnet devices the bandwidth available on the pci bus can become a performance limitation. there are several factors that reduce the maximum achievable bus bandwidth: ? aggressiveness of the pci arbiter. for example, the use of hidden arbitration can save cycles between adja- cent access and improve overall bandwidth. simpler arbiters will degrade bandwidth as cycles that could be used for data transfer are used for arbitration. ? the galnet protocol does involve some overhead when compared to raw data transfer. while performance in any given system is impossible to estimate due to design differences, galileo technology has determined the theoretical maximum pci bus loading for each 10-mbps port (see table 23.) the bandwidth numbers shown in this table take into account overhead for the galnet protocol, as well as overhead for the pci bus itself (arbi- tration, clocks/transfer, etc.) table 23 makes the following worst-case assumptions: ? packets are being received and transmitted at full wire speed (14,880 pps for 64-byte packets) in full-duplex ? all ports are fully loaded ? all packets must be routed across the pci bus (not switched between ports in the same device.) 1. maximum number of ports to guarantee 0% packet loss at worst case loading conditions. table 23: pci bandwidth estimates packet length maximum pci bandwidth required per 10-mbps port maximum number of 10-mbps ports per pci bus 1 64 2.08 mbytes/s 63 128 1.70 mbytes/s 78 256 1.50 mbytes/s 88 512 1.41 mbytes/s 94 1024 1.36 mbytes/s 97
GT-48001A switched ethernet controller revision 1.6 45 11.4 plug-and-play considerations in pci systems in plug-and-play systems, when the bios writes 0xffff.ffff to the internal/dram base address register during ini- tialization, the GT-48001A will return 0xffc0.0000 when read back indicating the GT-48001A is requesting 4 mbytes of pci address space. designers who wish to use more than one GT-48001A in a plug and play environment must relocate the multiple GT-48001As into the same 128mbyte region (the galnet protocol region.) an alternative solution is to isolate the GT-48001As on a secondary pci bus through a pci-to-pci bridge device with address remapping capability. 11.5 unused pci bus in stand-alone systems single-chip stand-alone applications do not require use of the pci bus. the pci bus pins must be connected as shown in table 24 to insure proper operation when not using the pci bus. all pull-up and pull-down resistors should have a value of 4.7k w . be sure to have your own reset and 33.0 mhz clock on-board. all other pci bus signals can remain unconnected. 11.6 pci bus arbiter in multiple galnet device systems all galnet systems that use more than one device will require a pci bus arbiter. the arbiter examines the bus request signals from each device and determines which device is granted the bus. galileo provides reference designs for pci bus arbiters (implemented in inexpensive pals) on our website. it is important to note that individual systems may have different arbiter design requirements. for example, if your sys- tem has several GT-48001A devices and a single gt-48002a (100-mbps switch) it may make sense to give higher pri- ority to the higher-speed 100basex interfaces. table 24: pin strapping requirements for unused pci signals pin name strapping devsel* pulled up to vcc stop* pulled up to vcc par* no connect perr* pulled up to vcc frame* pulled up to vcc irdy* pulled up to vcc trdy* pulled up to vcc gnt* pulled down to gnd idsel* pulled down to gnd serr* no connect req* no connect int* no connect ad[31:0] no connect cbe[3:0] no connect
GT-48001A switched ethernet controller 46 revision 1.6 12. ethernet interfaces the GT-48001A incorporates all the required digital circuitry to interface to 10base-t, 10base-5, 10base-2, 10base- fl, and nrz synchronous media. eight ethernet ports are integrated in the GT-48001A and only a small amount of external logic is needed to implement the standard physical interfaces. 12.1 media access control (mac) the GT-48001A operates in half-duplex or full-duplex modes. in half-duplex mode, the GT-48001A checks that there is no competitor for the network bus before transmission. in addition to listening for a clear line before transmitting, the GT-48001A handles collisions in a pre-determined way. if two nodes attempt to transmit at the same time, the signals collide and the data on the line is garbled. the GT-48001A listens while it is transmitting, and it can detect a collision. if a collision is detected, the GT-48001A transmits a jam pattern and then delays its re-transmission for a random time period determined by the backoff algorithm. in full-duplex mode, the GT-48001A transmits unconditionally. 12.2 illegal frames the GT-48001A will discard all illegal frames and increment the appropriate error mib counters. examples include: runts (less than 64 bytes), oversize (greater than 1518 or 1522 bytes), and bad fcs (bad crc.) 12.3 selecting the duplex mode each port can be selected to be in half- or full-duplex mode independently. following reset the port mode is set by the state sampled on the txen[x] pin. this value can be overridden in each ports port control register. 12.3.0.1 packet transmission if the col (collision) signal is not asserted, there is a major difference between full and half duplex mode when trans- mitting packets. in half duplex mode, the port complies with the "carrier sense" part of the csma/cd protocol, which means that a pending transmission will always start only after the programmed interframe gap has expired following the last of the following two events: 1. end of receive activity -and- 2. end of previous transmission in full duplex mode, a pending transmission will always start after the programmed interframe gap has expired follow- ing the end of previous transmission. any receive activity is ignored. 12.4 backoff algorithm options the GT-48001A implements the truncated exponential backoff algorithm defined by the 802.3 standard. aggressive- ness of the backoff algorithm used by all of the ports is controlled by the limit4 pin. limit4 controls the number of con- secutive packet collisions that will occur before the consequtive collision counter is reset. when limit4 is low, the gt- 48001a resets the collision counter after 16 consecutive retransmit trials, restarts the backoff algorithm, and continues to try and retransmit the frame. a packet which is endlessly colliding on re-transmits will continue to be re-transmitted forever, only changing backoff intervals. the GT-48001A supports port partitioning on consecutive collisions, a mode which must be enabled by the cpu. the retransmission is done from the data already stored in the dram. in the case of a successful transmission, the GT-48001A is ready to transmit any other frames queued in its transmit fifo within the minimum ipg of the link. when limit4 is high, the GT-48001A will reset its collision counter and restarts the backoff algorithm after 4 consecu- tive transmit trials. this results in the GT-48001A being more aggressive in acquiring the media following a collision. this will result in better overall switch throughput (less packet loss) in standardized tests. limit4 can be toggled during switch operation. 12.5 manchester encoder/decoder the manchester encoder receives clocked data from the transmit engine and uses an internal 20mhz clock (80mhz divided by 4) to provide the manchester-encoded data to the physical interface. the manchester decoder uses the 80mhz clock to recover the receive clock and to sample the incoming data.
GT-48001A switched ethernet controller revision 1.6 47 12.6 link integrity and auto polarity detector the GT-48001A implements the link integrity test as specified in the ieee 802.3 10base-t and 10base-fl supple- ments. the GT-48001A generates the link integrity signals on ports configured to either 10base-t and 10base-fl modes. in addition, the GT-48001A provides an auto polarity method for 10base-t, to switch the polarity of the data going into the mac layer accordingly. the default, value is auto-polarity enabled. 12.7 data blinder the data blinder field (datablind in the serial parameters register) sets the period of time during which the port does not look at the wire to decide to transmit (inhibit time.) the default value is 6.4us. 12.8 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the default (from the standard) is 9.6us for 10mbps ethernet and 960nsec for 100-mbps fast ethernet. note that the ipg can be made smaller or larger than the ethernet standards by programming. making the ipg smaller can improve test scores at the cost of ethernet com- patibility (a trick used by many vendors during head-to-head magazine tests.) we do not recommend this mode of operation, however, as it violates ieee standards. ipg is programmable in the serial parameters register. 12.9 partition mode a port enters partition mode when more than 32 consecutive collisions are seen on the port. when in partition mode, the port continues to transmit but it will not receive. the paen bit in the corresponding port control register is set when a port is partitioned. a port is returned to normal operation mode when a good packet is seen on the wire. 12.9.1 enabling partition mode partition is enabled (for all ports) by setting the enable bit in the GT-48001A control register. the default value is par- tition disabled for all ports. you must have a cpu in the system to enable partition mode, there is no pin strapping option. 12.9.2 entering partition state when partition is enabled, a port will enter partition state when either of the following two situations occur: ? the port detects a collision on every one of 32 consecutive retransmit attempts of the same packet. ? the port detects a single collision which occurs for more than 2048 bit times (i.e. most likely to occur in aui mode). while in partition state: ? if the interrupt is not masked, the GT-48001A will issue an interrupt to the cpu upon entering partition state, and will set the partition bit of that port in the interrupt cause register. ? the port will continue to transmit its pending packet, regardless of the collision detection, and will not follow the usual backoff algorithm. additional packets pending for transmission, will be transmitted, while ignoring the internal collision indication. this frees the port's transmit buffers which would otherwise be filled up at the expense of the other ports' buffers. the assumption is that partition is a system failure situation (bad connec- tor/cable/station), thus losing the transmitted packets is a small price to pay vs. the cost of halting the 8-port switch by filling up all of its buffers. ? the partition indication is available via the led interface (both the status led - blinking twice, and a dedicated led - on constantly). 12.9.3 exiting from partition state the port will exit from partition state, following the end of a successful packet transmission. a successful packet trans- mission will be declared, if no collisions were detected on the first 512 bits of the transmission. if the interrupt is not masked, the GT-48001A will issue an interrupt to the cpu upon exiting from partition state, and will clear the partition bit of that port in the interrupt cause register.
GT-48001A switched ethernet controller 48 revision 1.6 12.10 back-pressure back-pressure is not supported by the GT-48001A. back-pressure can greatly deteriorate real network throughput in favor of better standardized test scores. back-pressure works is by "jamming" an entire network segment when the switch cannot accept new transmissions. this blocks all traffic, including traffic between nodes on the same network segment (like blocking local phone calls when the long distance circuits are busy.) simply dropping packets is a better solution for overall network throughput, although this is not reflected in some simplistic standardized tests. (dropped packets are detected by higher-layer protocols and regenerated.) 12.11 vlan tagging support the GT-48001A will receive and transmit ethernet frames up to 1522 bytes in length, thereby accommodating the stan- dard vlan tagging bytes (four extra bytes.) bytes longer than 1522 are discarded as over-size frames. vlan tagging support is disabled by default. 12.12 serial modes each ethernet port can operate in one of four seral modes: 10baset, 10basefl, aui, or synchronous. the serial mode is set after reset by the state of the txddel/txd pins for each port. these values can be overridden in the port control register. 12.12.1 signal polarity in specific serial modes the polarity (active high or low) of the txen (output), rxen (input/output) and coll (input) signals depend on the serial mode for which the GT-48001A is configured (see table 25.) 12.12.2 10baset mode table 25: signal polarity by serial mode serial mode signal 10baset i/o 10basef i/o aui i/o txen high o high o high o crs high o high o high o rxlp/coll link pulse i connect 1 i coll-10 mhz i table 26: 10baset ethernet interface pin descriptions pin name i/o 10baset mode functionality sclk i 80 mhz 80 mhz clock. rxd i rxd receive data: manchester encoded data. rxlp i rxd_lp link pulses - this pin carries the link pulses. crs o crs carrier sense: indicates presence on received packet. (pre- amble to soi) pol o pol indicates the polarity. 1 - positive polarity; 0 - negative polar- ity. when auto-polarity is enabled, the pol output reflects the polarity of the soi symbol at the end of a valid incoming packet. auto-polarity is enabled by default for the GT-48001A. auto-polarity is disabled by default for the gt-48001.
GT-48001A switched ethernet controller revision 1.6 49 12.12.2.1 generating the required 10baset signals the gt-48001/1a drives txd,txddel and txen outputs (ttl levels). these signals are used to generate the required 10baset pre-distrotion transmit signals. txddel reflects the value of txd, delayed by 50ns. there are two cases which differ according to the last transmitted bit for the end of packet transmission as shown in figure 7. figure 7: 10baset signals txd o txd transmit data: manchester encoded data. whenever data is not being transmitted, the idle signal, tp_idl, is transmitted via the txd. the tp_idl is a 100 ns wide positive pulse, once every 13msec. following a packet, the first tp_idl pulse is transmitted within 13msec to 26msec from the soi of the packet. txddel o txddel transmit data delayed: txd delayed by 50ns. txen o txen transmit enable. indicates that the data is present on txd and txd_dl lines. table 26: 10baset ethernet interface pin descriptions pin name i/o 10baset mode functionality txen txd 50ns 50ns 100ns txddel 10baset link pulse transmission txen txd txddel 10baset end of packet transmission, last data bit is '0' 50ns 100 ns 50ns 250ns txen txd txddel 10baset end of packet transmission, last data bit is '1' 50ns 100 ns 300ns 50ns
GT-48001A switched ethernet controller 50 revision 1.6 the pre-distortion signal is generated using 4 exclusive-or (xor) gates (74ac86) as non-inverting and inverting buff- ers and a set of standard summing resistors typically used in 10bt filters/transformers. txd, txddel and txen are connected to the xor gates as follows: ? txd is connected to xor1/in1 and xor2/in1 ? txddel is connected to xor3/in1 and xor4/in1 ? txen is connected to xor2/in2 and xor3/in2 ? xor2/in2 and xor4/in2 are connected to ground the xor gates outputs provide the signals shown in table 25. the connection to the summing resistors is shown in figure 8. figure 8: summing resistor setup this connection is described in the gt-48001/1a serial interface application note located in the library section of the www site (http://www.galileot.com). 12.12.2.2 pol output/auto-polarity in 10baset the default value for the GT-48001A is to have the auto-polarity function enabled. the default value for the gt- 48001(non-a), is to have the auto-polarity function disabled. the pol output, in a 10base-t configured port, should be connected in a manner that prevents the assertion of link pulses at the gt-48001/1a rxlp input when the detected polarity (indicated by the pol output) does not match the correct polarity of the rxd pair. pol = 1 matches a correct rxd pair connection; pol = 0 matches a crossed rxd pair. such connection is specified in galileo's 10base-t application note. a crossed rxd pair will prevent the gt-48001/1a from seeing the link pulses which in turn cause the port to enter link-test-fail state. as a result, the pol output will start to toggle, remaining at 0 or 1 for ~0.5 seconds. once the pol reaches a state in which link-pulses are decoded and asserted at the gt-48001/1a rxlp input, the port will exit from link-test-fail and the pol output will stabilize. if the user does not connect the pol out - table 27: xor gate outputs signal name xor gate output value when txen = 0 (no transmit) value when txen =1 (transmit) buffer type txd+ xor1 txd txd non-inverting txp- xor3 txddel inverted txddel inverting txd- xor2 txd inverted txd inverting txp+ xor4 txddel txddel non-inverting r1 r2 r3 r4 r5 to filter and txp to filter and txn r1 = r3 = 61.9 ohm +/- 1% r2 = r4 = 422 ohm +/- 1% r5 = 1.21 kohm +/- 1% txd+ txp- txd- txp+
GT-48001A switched ethernet controller revision 1.6 51 put as described above, it is probable that after exiting from link-test-fail, the pol state will not match the actual rxd pair wiring e.g. the rxd pair is correct but pol = 0. since the received packet is inverted internally when pol = 0, the received packets will be rejected due to bad crc. the incoming packets may correct the polarity, thus resolving this temporary problem, as described below. when the auto-polarity function is enabled, every received packet, which is of valid length (512 data bits or more), and did not experience a collision, is used to update the internal polarity indication (which is driven externally through pol output). this is done by sampling the start of tp_idl symbol found at the end of the packet. (start of tp_idl is defined in fig 14-10 in the 802.3 std). if a positive polarity minimum size packet is received (e.g. a 64 byte packet through cor- rect rxd pair connection), and pol = 0, then the start frame delimiter (sfd) which follows the preamble will not be detected since the data is internally inverted. it is probable that a bit string matching the sfd pattern will be found as part of the packet data content, but this packet will be regarded as too short and will not update the polarity state (as noted earlier). longer packet are more probable to correct the polarity. once a packet corrects the polarity to pol = 1, any further packets will be received correctly. 12.12.3 10basefl mode table 28: 10basefl ethernet interface pin descriptions pin name i/o 10basef mode functionality sclk i 80 mhz 80 mhz clock. rxd i rxd receive data: manchester encoded data. link integrity test is performed on this input whenever there is no incoming packet. the link test function monitors the existence of a valid opt_idl (1 mhz periodic pulse). at the absence of the opt_idl, the port will enter link test fail (ltf) state. rxlp i unused should be connected to logic high crs o crs carrier sense: indicates presence on received packet (pre- amble to soi). pol o nc txd o txd transmit data: manchester encoded data. whenever data is not being transmitted, the idle signal, opt_idl, is transmitted via the txd. the opt_idl is a periodic pulse waveform of fre- quency 1 mhz. following a packet and the soi, the opt_idl starts with a logic high. txddel o txddel transmit data delayed: txd delayed by 50ns. txen o txen transmit enable. always high
GT-48001A switched ethernet controller 52 revision 1.6 12.12.4 aui mode 12.12.4.1 txd pins when the GT-48001A is in aui mode, the default value of txd pins in an idle state (i.e. when the GT-48001A is not transmitting) is 1. the default value of the txd pins of the gt-48001 in a idle state is 0. 12.12.4.2 auilinkup in aui mode, the auilinkup[7:0] pins of the GT-48001A are used as inputs to indicate the link status which can be driven by the phy. when the respective auilinkup[7:0] pin is a 1, the port has established link. when the respective auilinkup[7:0] pin is a 0, the link has failed on that port. the port will enter a link-test-fail state in which it performs similarly to a 10baset port in the link-test-fail state. this includes: 1. the port will ignore incoming packets 2. the port will not transmit packets 3. packets will not be forwarded to the port from the pci nor other ports on the same GT-48001A 4. the led interface will indicate link-test-fail state for the port 5. since the transmission are halted, the mib counters for the port will reflect the true wire activity 12.12.4.3 setting daddr[6] on reset a: the ieee ethernet spec defines the beginning of the interframe-gap after both transmission and carrier-sense have stopped. to comply with the ethernet mac specification, the gt-48001 and GT-48001A, start measuring the inter- frame-gap after both transmission and carrier-sense have stopped. the external tranceiver loopback function (loop back of txd transmission back to the rxd input), defines the period of time from the end of gt-48001/GT-48001A transmission, and the end of the carrier-sense (which is deasserted following the end of loop-back on rxd). effectively, the interframe-gap is increased relative to the programmed/default value ipg due to the loop-back. this prevents the GT-48001A from meeting full-wire speed transmissions, unless daddr[6] is low. when daddr[6] is low, t he inter- packet gap will restart at the end of txen, ignoring any loopback of txd back to rxd. this will enable the GT-48001A port to meet full-wire speed transmissions. when daddr[6] is high the inter-packet gap will restart when there is no transmit or receive activity (gt-48001 compatible). table 29: aui interface pin descriptions pin name i/o aui mode functionality sclk i 80 mhz 80 mhz clock. rxd i rxd receive data: manchester encoded data. rxlp i coll collision detect: active high. a collision is indicated by the cso signal (10 mhz signal). crs o crs carrier sense: indicates presence on received packet (pre- amble to soi). pol[0] i auilinkup[0] this pin carries the link status driven from the external phy. pol[7:1] i auilinkup[7:1] these pins carries the link status driven from the external phy. txd o txd transmit data. txddel o nc do not drive this pin. txen o txen transmit enable: indicates that the data is present on txd and txd_dl lines.
GT-48001A switched ethernet controller revision 1.6 53 12.12.5 synchronous mode synchronous mode allows an external device to drive or receive an nrz encoded bitstream directly to/from the gt- 48001a. the interface is similar to the mii interface defined for 100mbps fast ethernet. this mode is particularly useful when interfacing to motorola embedded controllers such as the mpc860 and 68360 family. notice: to use sync mode, all ports must be configured for sync mode. see section 18. figure 9 illustrates the relationship that must be observed for the synclk20 and synclk10 clock inputs when the gt- 48001a is in synchronous mode. notice that the rising edge of synclk10 should match the falling edge of synclk20. figure 9: synclk20 relationship to synclk10 table 30: synchronous ethernet interface pin descriptions pin name i/o sync mode functionality sclk i synclk20 20 mhz clock. rxd i rxd* receive data: active low. the decoded nrz data input. synchronous to synclk10s rising edge. rxlp i coll* collision detect: active low. synchronous to synclk20s ris- ing edge. this pin must be pulled high for full duplex opera- tion. crs i rxdv* receive data valid: active low. indicates that the data present on the rxd* is valid. synchronous to synclk10s ris- ing edge. pol[0] i synclk10 10 mhz transmit/receive clock. this clock serves as the receive and transmit clock for all 8 ports. there is no separate clock for each port. pol[7:1] o nc do not drive this pin. txd o txd* transmit data: active low. the nrz transmitted data output. driven from synclk10s falling edge. txddel o nc do not drive this pin. txen o txen* transmit enable: active low. indicates that the data present on the txd* is valid. driven from synclk10s falling edge. synclk20 synclk10
GT-48001A switched ethernet controller 54 revision 1.6 figure 10: synchronous mode transmit waveforms figure 11: synchronous mode receive waveforms table 31: synchronous mode transmit timings pin min delay max delay clock edge txd* 5ns 25ns synclk10 falling txen* 5ns 25ns synclk10 falling table 32: synchronous mode receive timings pin min setup min hold clock edge rxd* 5ns 5ns synclk10 rising rxdv* 5ns 5ns synclk10 rising coll* 5ns 5ns synclk20 rising synclk10 txen* txd* synclk10 rxdv* rxd*
GT-48001A switched ethernet controller revision 1.6 55 13. network management support the GT-48001A supports the following management features: ? hp-ease packet sampling technology ? repeater mib and pci counters ? station-to-station connectivity matrix ? port monitoring (sniffer) mode this section describes the mib counter, connectivity matrix and port mirroring functions. the hp-ease functions are described in the following section. 13.1 repeater mib and pci counters the GT-48001A incorporates a full set of repeater mib counters for each ethernet port, as well as counters for activity on the pci interface. counters are accessed by the management cpu through the pci interface. the repeater mib counters include the following: ? bytes received ? multicast bytes received ? broadcast bytes received ?bytes sent ? frames received ? multicast frames received ? broadcast frames received ? frames sent ? collision ? late collision ? crc and alignment error ? jabber ? frame too short ? frame too long ? bad bytes received (crc error, frame too long) the global pci counters are: ? pci frames received ? pci frames sent please see the register description section for more information on the repeater mib and pci counters. 13.2 station-to-station connectivity matrix the GT-48001A provides a mechanism to record the destination port(s), destination mac address, source mac address and the byte count of all the forwarding packets in an external fifo for rmon station-to-station (sts) con- nectivity matrix support. the fifo is connected to the drams data lines and controlled directly by the GT-48001A. the GT-48001A asserts the chipsel* pin, and reads the packet routing, byte count, the destination address and source address. figure 12 is a timing diagram which shows the relationship between the assertion of chipsel*, dram control signals and dram data lines for a one word burst read of rmon data. figure 10 shows a multiple word burst read of rmon data. an application note giving detailed information about hooking up a fifo to the 48001a for station- to-station connectivity support is located on galileos website (http://www.galileot.com).
GT-48001A switched ethernet controller 56 revision 1.6 figure 12: chipsel* timing, 1 word burst read figure 13: chipsel* timing, 3 word burst read 13.2.1 data structure format figure 14 shows the format of the sts data structure. the first word includes information about the destination port(s) for this packet indicated by the first 8 bits. this word is useful for multicast packets only and is read back by the gt- 48001a by a one word burst read. the next word is the byte count and the type of packet, indicated by bit 21 (1 = mul- ticast, 0 = unicast), also read back by the GT-48001A with a one word burst read. the third fourth and fifth word includes the destination address and the source address read back by the GT-48001A with a three word burst read. the assertion of this data is indicated by chipsel*, a dedicated output pin. please note that the assertion of the chipsel* does not necessarily happen in consecutive cycles. in other words, the rmon data is not read back by the GT-48001A in three consecutive bursts. t1 = GT-48001A clk to signal delay (2 to 17ns) t2 = dram access time from cas* (0 to 15ns) valid data . t1 t1 t1 t1 t1 t1 t2 t3 0ns 50ns 100ns 150ns 200ns clk (33 mhz) ras* cas* chipsel* ddata t3 = dram turn off delay from ras* (3 to 15ns) t1 = GT-48001A clk to signal delay (2 to 17ns) t2 = dram access time from cas* (15ns max) t3 = dram turn off delay from ras* (3 to 15ns) valid valid valid data t1 t1 t1 t1 t1 t1 t2 t4 t3 0ns 100ns 200ns clk (33 mhz) ras* cas* chipsel* ddata t4 = data output hold after cas* low (5 min)
GT-48001A switched ethernet controller revision 1.6 57 figure 14: station-to-station connectivity matrix data structure 13.3 monitoring (sniffer) mode the cpu can program the GT-48001A to work in monitoring mode for one of the eight ethernet ports. in monitoring mode, the GT-48001A sends all receive (including local traffic) and transmit packets to the cpu or to a port in one of the GT-48001A devices which was assigned to be the sniffer. the packets that are forwarded to the sniffer are not necessarily in a linear time order. monitoring mode is enabled by setting bit 4 in the port control register. the target sniffer is written into the cpu and sniffer numbers register. only one port in each GT-48001A device can work in monitoring mode at a time. 13.4 spanning tree support the GT-48001A provides the hardware assistance for bridge spanning tree algorithm implementation. the spanning tree algorithm itself is performed by a management cpu. the GT-48001A includes a spanen bit in the global control register and additional spanen bits in each of the 8 port control registers. table 33 summarizes the hardware assistance for the spanning tree algorithm. note 1 : the GT-48001A does not learn mac addresses during the spanning tree learning stage (it is learning the bridge topology while in this mode.) the GT-48001A only learns mac addresses in the forward mode. note 2 : the cpu can send bpdu messages to a port of the GT-48001A which is disabled. the mechanism to send bpdus from the cpu to a locked port is to send a buffer_request message like the format shown in section 10.3.4, but with the lsb bits of the address as 0x58, instead of 0x0. this buffer_request message will cause the GT-48001A to allocate a buffer regardless of the state of that port. 13.5 broadcast storm filtering excessive broadcast packets (broadcast storms) can be filtered in a managed switch by setting the filbroad bit in the port control register. broadcast packets can be re-enabled once the loops causing the broadcast storm are eliminated via the spanning tree algorithm. table 33: spanning tree enable bit definition spanen (global) spanen (port) logic state remarks 0 x port enable no spanning tree. treat bpdus as regular multicast. 1 1 blocking, listening, learning transfer bpdus to cpu. all receive/transmit packets are rejected, except bpdu messages from the cpu. address learning disabled. 1 0 forward transfer bpdu to the cpu. accept all packets. address learning enabled. byte count dest. addr[16:47] src. addr[32:47] dest. addr[0:15] src. addr[0:31] . 20 10 0 31 word0 word1 word2 word3 word4 ports routed to 7 type 21
GT-48001A switched ethernet controller 58 revision 1.6 14. hp-ease packet sampling technology hewlett-packards embedded advanced sampling environment (hp-ease) is supported directly by custom hardware in the GT-48001A device. hp-ease provides many of the management functions that rmon provides, but at a greatly reduced implementation cost. with the GT-48001A device, the switch oem has the freedom to implement rmon, sampled rmon, ease, or any of the above. the hp-ease functionality is best understood using the familiar stack model, as shown in figure 15. an hp-ease agent running on the management cpu, combines samples of packets passing through the switch, with snapshots of the mib counters and forwards these to a management console through snmp trap messages. this approach is dif- ferent from rmon, as rmon keeps all data within the switch until polled by the management console. the gt- 48001a provides the hardware packet sampling portion of the hp-ease protocol. this capability can be used to imple- ment a true hp-ease compliant product, or as a method to implement sampled management such as statistical rmon. figure 15: hp-ease stack a system implementing hp-ease provides network management functions similar to rmon. however, a network device (or cpu) implementing hp-ease is not required to have the extensive cpu or memory resources needed to fully implement all groups of rmon. ease significantly reduces the requirement for these resources by statistically sampling data on network segments while rmon requires the processing of every network event. the philosophy of ease is to off-load the intelligence and processing power required for network monitoring to the network management station rather than the network device. 14.1 hp ease technology overview a system with hp ease provides network management functions similar to rmon. however, a network device (or cpu) implementing hp ease is not required to have the extensive cpu or memory resources needed to fully implement all groups of rmon. ease significantly reduces the requirement for these resources by statistically sampling data on network segments. rmon requires the processing of every network event. the philosophy of ease is to off-load the intelligence and processing power required for network monitoring to the network management station rather than the network device. h/w packet sampling (built into GT-48001A) software on management processor sample control sample processing counter processing snmp encapsulation snmp agent management station
GT-48001A switched ethernet controller revision 1.6 59 hp ease sampling requires a counter for each network segment. this counter indicates the number of packets to be skipped before a sample is taken. when the counter reaches zero, the next packet on the network segment is captured by the network device. software then truncates the sampled packet, to some small fixed length, and appends a snap- shot of specific mib counters for that segment. the counter snapshot does not have to be taken simultaneously with the sample. software may introduce a delay of some milliseconds after the packet is sampled by hardware, however minimizing this delay makes ease more accurate. the newly created datagram is sent off to the network management station as an snmp trap. the network management station records the sample and counters in a database, and uses the information to obtain traffic load estimates, top talker matrices, high-level protocol flows, and other useful sets of information. after the sample has been taken, the cpu loads the count-down counter with the next skip count to capture the next sampled packet. the skip count is a random value loaded by software. ease software in the network device must keep track of the last receive error sources and the associated error condi- tions. the network device keeps track of errors associated with received packets and informs the cpu of the source address (sa) of these error packets. 14.2 ease functionality on the GT-48001A support for ease sampling is directly integrated in the GT-48001A chip, but requires the presence of a cpu in order to function, for enabling the ease support as well as the sample packet processing. each GT-48001A chip supports eight network segments (one per each port) as well as a pci system bus. sampling will occur only on the network segments, and sampled packets will be sent to the cpu via the pci system bus. sampling is not performed on the pci bus. it may, however, be performed on packets received from the pci bus, but only as a function of the counters for the desti- nation ports (i.e. packets entering the GT-48001A via the pci bus and being transmitted through one or more ports). there is no counter for the pci interface itself. only good packets of valid length are sampled. all other packets are not sampled and do not affect the skip count. all counters and registers implemented in the GT-48001A chip in order to support ease functionality, may be accessed by the cpu from the pci system bus. 14.3 ease_register a register is defined for each external port supported on the GT-48001A device. this register is used by the cpu to load the internal count down counter, described above, with a random skip count. the count-down counter is 15 bits in length and is used to actually determine when a sample is to be made. the GT-48001A implements a shadow register for each of the ease_registers. the shadow register address is the same address as the ease_register address. after a value has been written to the ease_register it is transferred to an internal 1 word deep fifo (the shadow register) or directly to the actual count-down counter if that counter is currently idle and empty. if the value can not be transferred to the count-down counter, the value will be held in the ease_register shadow register until space becomes available (i.e. a sample has been taken). if the ease_register shadow register was written and the cpu does attempt to write a new value, the new value will silently replace the existing value. if the ease_register is empty at the time a new value needs to be loaded into the internal counter or the shadow register, the GT-48001A will simply wait, indefinitely, for the cpu to write a value into ease_register. in this situation, ease is effectively disabled on that port. ease (8 registers), offset: 0x040228 - 0x040244 14.4 ease interrupts a status bit indicating the full/empty status of the ease_register for each external port supported on the GT-48001A, is maintained as part of the interrupt cause register. when a value is moved from the ease_register into an internal counter or shadow register, a bit is reset in the interrupt cause register indicating that the ease_register is now empty. bits field name function initial value 14:0 ease_register value loaded to the internal count-down counter of port 0 0x0 31:15 - reserved. -
GT-48001A switched ethernet controller 60 revision 1.6 setting this bit should also generate a processor interrupt. the interrupt cause register may be read to determine the state of the ease_registers, and may be written to clear the interrupt condition described above. it is possible for the cpu to mask the interrupt condition as well as clear the interrupt condition. the GT-48001A implements a mask bit in the interrupt mask register for each ease status bit in the interrupt cause register. masking and clearing the interrupts are executed in a way that is consistent with the other interrupts supported by the GT-48001A. ease interrupt cause register, offset: 0x050 ease interrupt mask register, offset: 0x054 14.5 sampled packet indication sampled packets are copied into the cpus receive buffers using the same mechanism as normal receive packets. the only difference, from the cpus point of view, is that the GT-48001A will put an indication in the first word of the receive buffer which identifies the packet as a sample. the sample indication bits specify which ports on the particular gt- 48001a the sample is associated with. it is possible for a single sample to be associated with more than one port at a time. for example, a broadcast packet flooded to all ports may be sampled on several ports if each of their skip counters had previously been decremented to zero. each GT-48001A device operates independently, so it is possible for the cpu to receive the same sample from different GT-48001A devices. for example, a broadcast packet flooded to all ports in the system may be sampled by several GT-48001As at the same time. each sample will result in a separate copy of the packet being sent to the cpu. it is also possible to sample a packet which would normally be received by the cpu. in this case, only a single copy of the packet can be sent to the cpu. the cpu should be responsible for determining if a sampled packet should also be accepted as a normal receive packet. in the case where a normally received packet is also a sample from multiple GT-48001A bits field name function initial value 0 easereg0empty ease_register of port 0 is empty 0x0 1 easereg1empty ease_register of port 1 is empty 0x0 2 easereg2empty ease_register of port 2 is empty 0x0 3 easereg3empty ease_register of port 3 is empty 0x0 4 easereg4empty ease_register of port 4 is empty 0x0 5 easereg5empty ease_register of port 5 is empty 0x0 6 easereg6empty ease_register of port 6 is empty 0x0 7 easereg7empty ease_register of port 7 is empty 0x0 8 errorsasent error_source message sent to cpu 0x0 [31:9] n/a always write with 0x0 0x0 bits field name function initial value 8:0 maskbits mask the cpu interrupt line for the appropriate bits in the interrupt cause register. 0x0 [31:9] n/a always write with 0x0 0x0
GT-48001A switched ethernet controller revision 1.6 61 devices (e.g. a broadcast packet), the GT-48001A must provide an indication which allows the cpu to avoid processing duplicate packets. this indication is provided by the GT-48001A which actually received the packet from an external link. an additional bit in the packet header indicates that the sample packet was originally received from an external link to the cpu as opposed to the pci system bus. other GT-48001A devices which sampled the flooded packet only because it was received from the pci interface and is being transmitted on a port whose internal counter was decremented to zero will not have this indication. these samples are pure samples and the cpu will know that it should not process the packet as a normally received packet. the first word in each 2k block holding the packet to cpu contains the following bits: ? sniffer (bit 31) (active high) ? n/a (bits [30:24]) ? ease sample for port 7 (bit 23) (active high) ? ease sample for port 6 (bit 22) (active high) ? ease sample for port 5 (bit 21) (active high) ? ease sample for port 4 (bit 20) (active high) ? ease sample for port 3 (bit 19) (active high) ? ease sample for port 2 (bit 18) (active high) ? ease sample for port 1 (bit 17) (active high) ? ease sample for port 0 (bit 16) (active high) ? ease sample is an original packet to cpu (bit 15) (active high) ? source channel number (bit [14:12], bit 14 is msb) ? byte count (bits [11:1], bit 11 is msb) ? valid bit (bit 0, active high) these parameters are written at the end of the packet transfer. 14.6 error source indications ease software in the network device must keep track of the last receive error sources and the associated error condi- tions. the GT-48001A informs the cpu of error source conditions by writing the error_source message to a new error_source buffer area in cpu memory. operations in the error_source buffer area are similar to those in the new_address, start_of_packet and intervention buffer areas. there is an error_source base address reg- ister in the GT-48001A in which the cpu writes a pointer to the error_source buffer area. the error_source buffer area is able to hold 32 entries. two types of errors are defined for this procedure: fcs error and frames too long. when the GT-48001A receives a packet with any of the above conditions, it will generate and write an error_source message to the cpus buffer area. the error_source message will contain the 48-bit source address of the error packet, the source port number and an indication of the error type. the cpu may poll the error_source buffer area for new messages. however, the GT-48001A includes a separate bit in the interrupt cause register which indicates that the GT-48001A has written an error_source message into the cpus memory. an appropriate mask bit is defined in the interrupt mask reg- ister. cpu error source base address, offset: 0x140050 error_source : the data written by the GT-48001A device to the error_source messages buffer area that contains bits field name function initial value 31:8 errorsourcebaseadd contains a pointer to the cpu error_source area. the area includes 32 entries (2 32-bit words each) for the GT-48001As error_source messages. 0x0 7:0 - reserved. must be 0x0 when written. -
GT-48001A switched ethernet controller 62 revision 1.6 information about an error source address. the data format is as follows: 14.7 enabling/disabling ease functionality an explicit hp ease enable/disable bit is provided in the global control register for the GT-48001A device. when hp ease is disabled using this bit, no ease samples nor error source messages are sent to the cpu. hp ease packet sampling can be disabled on a port anytime the internal counter can not be reloaded with a new skip count because the cpu has not provided any new values via the ease_register. interrupt conditions generated by an empty ease_register can be masked by appropriate bits in the ease_full_mask and/or interrupt cause registers. 14.8 interaction with other GT-48001A features some GT-48001A features are incompatible with hp ease, and will require that hp ease be disabled. in most cases, it can be the responsibility of software to assure that hp ease is disabled when used with other GT-48001A features. ? broadcast intervention mode : hp ease is independent of broadcast intervention mode. ? unicast intervention mode: hp ease should be disabled when using this mode. ? sniffer mode : hp ease should be disabled on the GT-48001A device which one of its ports has been config- ured to work in monitoring mode (e.g. that ports rx and tx traffic are sent to the sniffer). ? rmon station-to-station matrix : hp ease is independent of the station-to-station matrix feature. ? spanning tree support : hp ease may only be enabled on GT-48001A which has its ports configured in the forwarding state. if the global spanning tree enable bit is set and the port is blocked, listening or learning, hp ease should not be enabled. if the global spanning tree enable bit is clear or the port is in the forwarding state, hp ease can be enabled. it can be the responsibility of software to assure that ease is enabled cor- rectly when used with spanning tree features. ? address learning : hp ease in no way impacts the learning process of the GT-48001A device. ? led serial interface : ease packet sample indications are accessible via the serial led interface mainly for debug purpose. leddata bit # 125: ease sample indication for port 0. leddata bit # 126: ease sample indica- tion for port 1. (leddata bit#1 is the bit on which ledstb is high). the led circuit implements a monostable stretching function to enable viewing these dynamic signals. pci bits description address [31:8] [7:3] [2:0] errorsourcebaseadd offset pointer to entry 000 data 0 [31:3] [2] [1] [0] mac address [19:47] 1 - late collision error 1 - fcs error 1 - over count error data 1 [31:27] [26:24] [23:19] [18:0] reserved port # (bit 26 is msb) device# (bit 23 is msb) mac address [0:18]
GT-48001A switched ethernet controller revision 1.6 63 15. dram interface and usage the GT-48001A includes direct support for edo drams. the performance of edo satisfies the required bandwidth for data transfer, address recognition and tx descriptor fetch/update. the dram interface is entirely glueless. all accesses are performed as 32-bits. the dram interface is designed for 60ns edo drams and all timings are guaran- teed to work with these devices. refresh is performed automatically by the GT-48001A. please refer to the galileo-6q evaluation platform schematics for an example of edo dram design with the GT-48001A. the GT-48001A requires about 300kbytes of the dram for the address table and other private data structures. the remainder is used for packet buffers. following power-up or system reset, the GT-48001A device creates the mac address table in dram, and initializes all locations in the table to indicate that invalid entries exist in all locations. galileo recommends using dram with 256k x 16 configuration. when using this configuration, 2 dram chips are required for 1 mbyte, and 4 dram chips are required for 2 mbytes. if 1 mbyte is selected, ras0* should be con- nected to 2 dram chips while ras1* should be left unconnected. if 2 mbytes is selected, ras0* will control the first 1mb bank, while ras1* will activate the second 1mb bank. ddata[31:0], daddr[8:0], cas*, and we* should be connected to both banks. using 1 or 2 mbytes of dram is entirely up to the architect. 2mbytes increases the size of the rx buffer space as shown in table 3. this performance advantage must be weighed against the cost of additional memory. 16. led support the GT-48001A supplies a serial bit stream designed to drive status leds for each port, as well as for overall system information. over 80 internal signals are available through the 3-wire led port. galileo also provides reference designs and example pal equations in the led interface application note available on our website. 16.1 led indications interface description table 34 shows the data accessible on the led indications serial interface for each of the GT-48001A ports. 16.2 led serial interface description the led serial interface consists of three outputs: ? ledclk : ledclk is the primary timebase of the led indications interface. it is a 50% duty cycle free running clock at a fixed frequency of 1 mhz. ledclk is active when rst* is asserted. ledclk frequency during rst* is 10 mhz. ? ledstb : ledstb (active high) indicates the beginning of the data frame. ledstb is activated for a duration of one ledclk cycle once every 128 ledclk cycles, starting from rst* deactivation. this signal marks the begin- ning of the 128 bit long led data frame. ledstb transitions occur 200 ns after ledclk rising edge. table 34: led signals available data description symbolic signal name type primary port status led primary_port_status n/a transmit data in progress transmit dynamic receive data in progress receive dynamic collision active collision dynamic full/half duplex full_duplex static receive buffer full rx_buffer_full dynamic forwarding of unknown packets enabled unknown_enable static the port is configured as sniffer port_is_sniffer static link fail state link_test_fail static partition state partition static
GT-48001A switched ethernet controller 64 revision 1.6 ? leddata : the internal signals are multiplexed on the leddata output for every data frame. ledstb activation signals the presence of data bit #1 (out of 128 bits) on the leddata output. leddata transitions occur 200 ns after ledclk rising edge. all internal signals accessible via leddata are active high internally and are inverted on the leddata output (i.e. when an internal signal is active, the data bit on the leddata output will be low). for example: if port#0 transmits data, the internal_event_transmit[0] signal is active high and the corresponding bit #9 in the leddata serial stream is low. the timings for the led serial interface are shown in figure 16, below. figure 16: led serial interface timings 16.3 detailed led signal description 16.3.1 primary port status led port status led indicates the port status in two operation modes selectable via the ledmode input pin. when a port is disabled (via the port control register port enable bit or via the endev* input), the link detection circuits are stopped. this means that the link test led and the internal indications of the link (such as those in the status regis- ter) once the port is enabled, the link detection circuits are enabled. in the case of no link pulses, the link test fail indi - cation will be indicated after the timeout period of 150ms. this means that the earliest time any valid link indication (via registers or led interface) is at least 150ms. 16.3.1.1 primary port status led (mode 0): (ledmode input is low) in this mode, the port status led provides the following information if port is disabled port status led is off; else if link integrity test failed port status led blinks once; else if partition state detected port status led blinks twice; else everything is ok (port status led is on) 16.3.1.2 status led blink timing (mode 0) link integrity test failed - status led blinks once every 5 seconds. primary status bit is active for 420 ms every 5 seconds ledclk 1us 200ns 200ns ledstb leddata
GT-48001A switched ethernet controller revision 1.6 65 figure 17: primary status led timing (link test fails) partition, status led blinks twice * primary status bit is activated twice every 5 seconds for 420 ms each time, with a period of 1.26 seconds between two consecutive activations. figure 18: primary status led timing (port partitioned) 16.3.1.3 primary port status led (mode 1): (ledmode input is high) in this mode, the port status led initially displays the port link status information (indication type a) and then switches to reflect the port traffic (transmit or receive) activity (indication type b). the switching between the two types of indi- cations is as follows: indication type a: the port status led indicates the port link status for a period of about 3 to 3.5 seconds (active - link test passes, inactive - link test fails) following any of the events below: 1) rst* deassertion 2) transition between link test fail to link test pass following this time period, the port status led will switch to indication type b. in the case that the link test fails, the port status led will remain inactive and will not switch to indication type b. indication type b: the port status led indicates the port traffic (transmit or receive) activity which is a logical or of the transmit and receive dynamic signals. the "monostable" function is applied to this indication type so the led can be viewed for a period of about 200 ms per each traffic activity. the port status led will switch to indication type a on the following cas- es: 1) rst* assertion 2) transition from link test pass to link test fail 420ms 5s link intergity test fails: primary status led blinks 420ms every 5sec 420ms 5s port partitioned: primary status led twice for 420ms every 5sec 420ms 1.26 sec
GT-48001A switched ethernet controller 66 revision 1.6 16.3.2 transmit data in progress this signal indicates the port is transmitting data. 16.3.3 receive data in progress this signal indicates port receive activity. 16.3.4 collision active this signal indicates the port collision event detected by the port. 16.3.5 full/half duplex this signal indicates the port duplex: active - full duplex, inactive - half duplex. 16.3.6 receive buffer full in order for this led to be active, rx buffer threshold must be enabled (see table 4). this signal indicates the port re- ceive buffer status: active - the buffer exceeds it's programmed threshold, inactive otherwise. 16.3.7 forwarding of unknown packets enabled this signal indicates the port mode of forwarding unknown packets: active - forwarding unknown packets enabled, in- active otherwise. 16.3.8 the port is configured as sniffer this signal indicates if the port mode is configured as a monitor port: active - port is a source sniffer, inactive otherwise. 16.3.9 link fail state this signal indicates the port link status: active - link is down, inactive - link is up. 16.3.10 partition state this signal indicates the port partition status: active - port entered partition state, inactive otherwise. 16.4 led signals timing type 16.4.1 static led signals these signals are stable for relatively long time periods. the led indication directly reflects their current value. 16.4.2 dynamic internal signals: these signals are typically active for short time periods. in order to be visible through the led indication interfaces, the GT-48001A includes a "monostable" function per each of these dynamic signals so they can be viewed on the led in- dication output for a period of about 200 ms. 16.4.3 table of internal activities/status driven via the led interface the following table defines a bit by bit description of the internal signals driven through the led indications serial inter- face. the bit number (bit#) refers to the activation of ledstb. ledstb is active for bit# 1. reserved bits contents is not defined (i.e. can be either high or low).
GT-48001A switched ethernet controller revision 1.6 67 table 35: led signals bit number signal bit number signal 0 primary_port_status[0] (as per ledmode input) 32 transmit[3] 1 primary_port_status[1] (as per ledmode input) 33 receive[3] 2 primary_port_status[2] (as per ledmode input) 34 collision[3] 3 primary_port_status[3] (as per ledmode input) 35 rx_buffer_full[3] 4 primary_port_status[4] (as per ledmode input) 36 unknown_enable[3] 5 primary_port_status[5] (as per ledmode input) 37 port_is_sniffer[3] 6 primary_port_status[6] (as per ledmode input) 38 full_duplex[3] 7 primary_port_status[7] (as per ledmode input) 39 -reserved- 8 transmit[0] 40 transmit[4] 9 receive[0] 41 receive[4] 10 collision[0] 42 collision[4] 11 rx_buffer_full[0] 43 rx_buffer_full[4] 12 unknown_enable[0] 44 unknown_enable[4] 13 port_is_sniffer[0] 45 port_is_sniffer[4] 14 full_duplex[0] 46 full_duplex[4] 15 -reserved- 47 -reserved- 16 transmit[1] 48 transmit[5] 17 receive[1] 49 receive[5] 18 collision[1] 50 collision[5] 19 rx_buffer_full[1] 51 rx_buffer_full[5] 20 unknown_enable[1] 52 unknown_enable[5] 21 port_is_sniffer[1] 53 port_is_sniffer[5] 22 full_duplex[1] 54 full_duplex[5] 23 -reserved- 55 -reserved- 24 transmit[2] 56 transmit[6] 25 receive[2] 57 receive[6] 26 collision[2] 58 collision[6] 27 rx_buffer_full[2] 59 rx_buffer_full[6] 28 unknown_enable[2] 60 unknown_enable[6] 29 port_is_sniffer[2] 61 port_is_sniffer[6] 30 full_duplex[2] 62 full_duplex[6] 31 -reserved- 63 -reserved-
GT-48001A switched ethernet controller 68 revision 1.6 64 transmit[7] 80 partition[0] 65 receive[7] 81 partition[1] 66 collision[7] 82 partition[2] 67 rx_buffer_full[7] 83 partition[3] 68 unknown_enable[7] 84 partition[4] 69 port_is_sniffer[7] 85 partition[5] 70 full_duplex[7] 86 partition[6] 71 -reserved- 87 partition[7] 72 link_test_fail[0] 88-127 -reserved- 73 link_test_fail[1] 74 link_test_fail[2] 75 link_test_fail[3] 76 link_test_fail[4] 77 link_test_fail[5] 78 link_test_fail[6] 79 link_test_fail[7] table 35: led signals bit number signal bit number signal
GT-48001A switched ethernet controller revision 1.6 69 17. interrupts the GT-48001A signals interrupts to a management cpu via the pci inta# pin. interrupts are maskable through the interrupt mask register and the interrupt source is determined through the interrupt cause register. the interrupt mask register defaults to masking all interrupts. a 0 in the appropriate bit means that particular interrupt will be masked. a 1 in the appropriate bit means that particular interrupt will not be masked. the default is that all interrupts are masked. interrupts are cleared by writing 0 to the corresponding bit in the interrupt cause register. writing 1 to a bit in the cause register has no effect. 18. reset configuration the GT-48001A uses several pins as configuration inputs to set certain parameters following a reset. the definition of the configuration pins changes immediately after reset to their usual function. 18.1 configuration pins configuration pins must be pulled up or down externally at reset to select the desired operational parameter. the rec- ommended value of the pull-up/down resistors is 4.7k ohms. table 36 shows the configuration pins for the GT-48001A. 18.2 configuration input timings the configuration inputs have two timing requirements: ? setup/hold time to clock (as any synchronous input) ? setup of at least 10 clock cycles before reset de-assertion (rising edge). you can guarantee these parameters by using resistors to strap the configuration pins and delaying reset de-asser- tion until least 10 clock cycles after the clock is stable. table 36: reset pin strapping options pin configuration function daddr[4:0] device number daddr[5] dram size 0- 1- 2mbyte 1mbyte daddr[6] aui mode 0- 1- the inter-packet gap will restart at the end of txen, ignoring any loopback of txd back to rxd. this mode is compatible with the gt-48001. the inter-packet gap will restart when there is no transmit or receive activity. daddr[8] dram type 0- 1- reserved edo txen/fdx[7:0] half/full duplex mode per port 0- 1- half duplex full duplex txddel[7:0],txd[7:0] serial mode per port (note that the logic order is txddel/txd) 00- 01- 10- 11- 10base-t 10base-fl aui sync (all ports must be configured as 11 to use sync mode)
GT-48001A switched ethernet controller 70 revision 1.6 19. switch expansion figure 19 shows how a gt-4800x switch may be expanded beyond the pci physical limit of 10 loads. multiple gt- 48001a devices are connected to a local pci bus. the pci buses are connected via pci-to-pci bridges. these devices are being used to filter the traffic between multiple pci buses, and therefore to increase the effective aggregate bandwidth in the switch. the local traffic between GT-48001A devices in one pci bus is not forwarded to the other gt- 48001a devices. only the traffic between GT-48001A devices in different pci buses crosses the bridges.such an implementation requires a cpu to initialize the bridges. figure 19: switch expansion via pci-to-pci bridges GT-48001A pci-to-pci bridge GT-48001A GT-48001A pci-to-pci bridge GT-48001A cpu pci bus pci bus pci bus 8 ports 2 ports 8 ports 100basetx 2 ports 100basetx
GT-48001A switched ethernet controller revision 1.6 71 20. development tools galileo technology and a number of third party vendors offer development tools for the GT-48001A. vendors wishing to join galileos third party developers program should contact galileos ethernet marketing group (ethernet@gali- leot.com.) 20.1 evaluation platforms galileo provides the galileo-6q evaluation platform for the GT-48001A. galileo-6q is a full sized pci card that includes a single GT-48001A with 8 10baset ports. galileo-6 can be used stand-alone, or plugged into a pci backplane, includ- ing the galileo-4pb passive backplane. the galileo-6q can be easily combined with the galileo-7 100baset evalua- tion board for the gt-48002a, allowing mixed 10/100-mbps switched to be prototyped rapidly. 20.2 verilog models galileo provides verilog models for all components, including the GT-48001A. please contact your local sales repre- sentative for pricing information. 20.3 reference designs several reference designs are available for the GT-48001A. full schematics and design information are avaible for the galileo-6 board on our website. other reference designs are available (including a 24-port i960 processor based switch designed by intel). check our website periodically for updates. 20.4 complimentary products galileo manufactures a line of cpu core logic chips for mips processors that incorporate pci interfaces. the gt- 64010a provides all core logic functions for 64-bit bus mips processors: r4600, r4650, r4700 and r5000. for the 32- bit bus r4640, galileo offers the gt-64011. information on both devices is available on our website.
GT-48001A switched ethernet controller 72 revision 1.6 21. register tables the GT-48001A incorporates the required pci configuration registers, command registers and various counters for management purposes. the GT-48001A can work in stand-alone mode, in which there is no requirement for cpu inter- vention (a system with no cpu) in which case the default values of the control registers are used. the actual address of an internal register is the sum of the GT-48001A base address and the particular registers off- set. the cpu defines the base address by writing to the internal registers base address register in the pci configura- tion area. register map description offset internal control registers global control 0x140028 port control 0 0x040200 port control 1 0x040204 port control 2 0x040208 port control 3 0x04020c port control 4 0x040210 port control 5 0x040214 port control 6 0x040218 port control 7 0x04021c status 0x14002c cpu and sniffer numbers 0x140030 interrupt cause 0x044 interrupt mask 0x048 ease interrupt cause register 0x50 ease interrupt mask register 0x54 serial parameters 0x040220 rx buffers threshold 0x040224 cpu buffer base address 0x140034 cpu start of packet base address 0x140038 cpu new address base address 0x14003c cpu intervention base address 0x140048 device table 0x40 timeout counter 0x04c port 0 counter block 0x040000 - 0x040038 port 1 counter block 0x040040 - 0x040088 port 2 counter block 0x040080 - 0x0400b8 port 3 counter block 0x0400c0 - 0x0400f8 port 4 counter block 0x040100 - 0x040138 port 5 counter block 0x040140 - 0x040178 port 6 counter block 0x040180 - 0x0401b8 port 7 counter block 0x0401c0 - 0x0401f8
GT-48001A switched ethernet controller revision 1.6 73 21.1 internal control registers global control, offset: 0x140028 pci global counters 0x140040 -0x140044 pci configuration device and vendor id 0x000 status and command 0x004 class code and revision id 0x008 header type, latency timer, cache line 0x00c internal/dram base address register 0x010 interrupt pin and line 0x03c bits field name function initial value 0 dislearnpro disable learning process. 0 - learning process is enabled 1 - learning process is disabled. the GT-48001A will not learn any new addresses from the ethernet ports 0x0 1 rmonen rmon enable. 0 - rmon disabled 1 - the GT-48001A enters the rmon mode (station- to-station connectivity matrix) and asserts the chipsel* pin when it reads the packets byte count and source and destination addresses from the dram 0x0 2 devtabmod device table mode. 0 - the GT-48001A updates the appropriate bits in the table upon master abort 1 - the cpu updates the device table 0x0 3 - reserved. 0x1 4 dramarbpri dram arbiter priority. this bit indicates the dram arbitration scheme of the four GT-48001A internal units as follows: 0 - 1) frame control unit, 2) switching core unit, 3) pci and interpci control units in round robin scheme. 1- 1) frame control unit, 2) switching core unit, 3) interpci control unit, 4) pci control unit 0x0 5 descarbpri descriptor control arbiter priority. this bit indicates the descriptor control arbitration scheme as follows: 0 -round robin between the pci side and the 8 ether- net ports. the 8 ports have equal priority. 1- pci has higher priority than the 8 ports. the priority is: pci, port 0; pci, port 1;......pci, port 7; pci, port 0... 0x1 description offset
GT-48001A switched ethernet controller 74 revision 1.6 6 forwunk forward unknown packets. it defines whether the GT-48001A will forward unknown packets to the cpu or not. 0 - do not forward 1 - forward 0x0 7 forwnewadd forward new address. it defines whether the GT-48001A will forward new address messages to the cpu or not. 0 - do not forward 1 - forward 0x0 8 recen recovery enable. it defines whether the recovery process is enabled or not. 0 - disabled 1 - enabled 0x1 9 sniftyp sniffer type. this bit indicates the sniffer type. the sniffer can be a cpu or a dedicated port in one of the GT-48001A devices which was assigned to be the sniffer. 0 - cpu type 1 - GT-48001A type 0x1 10 cpuen cpu enable. this bit indicates that there is a cpu in the system. 0 - cpu does not exist 1 - cpu exists 0x0 11 rmontopci rmon to pci enable. meaningful only when rmonen bit is set. 0 - the GT-48001A reads the da/sa of the packet that is forwarded only to the local ports. 1 - the GT-48001A reads the da/sa of the packet that is forwarded to the local ports and the pci. 0x0 19:12 - reserved. 0x0 20 bufthren buffer threshold enable. 0 - there is no limitation on the buffers allocation (other than physical memory size.) 1 - the buffers allocated to the ports and the pci are limited to the number which is written in the rx buffers threshold register. this bit is meaningful only when disbufthr* pin is dis- abled. 0x1 21 - reserved. 0x0 22 forwmulti forward multicast. 0 - the GT-48001A forwards multicast packets to all the ports. 1 - multicast packets forwarded only to the cpu. 0x0 bits field name function initial value
GT-48001A switched ethernet controller revision 1.6 75 23 paren partition enable. when more than 32 collisions occur while transmit- ting, the GT-48001A enters the partition mode. it waits for the first good packet from the wire, and then goes back to normal mode. under partition mode it continues transmitting, but not receiving. 0 - normal mode 1- partition mode 0x0 24 spanen spanning tree enable. 0 - the bpdu (bridge protocol data unit) packets are treated as multicast packets, and therefore are for- warded to all ports. 1 - the GT-48001A forwards bpdu packets only to the cpu. 0x0 25 enease ease sampling enable/disable. 0 - ease sampling disabled. 1 - ease sampling enabled. 0x0 26 mibctrmode 0 - mib counters reflect forwarded packets only. 1 - mib counters reflect local and forwarded packets. note: a local packet is a packet which is destined to a station on the same port and is not switched. 0x0 27 enabledevice used to enable or disable the GT-48001A. this bit along with endev* (external hardware pin) as well as enport (bit 0 of the port control register) enables or disables the port/device. see table 1, enabling/disabling ports of the GT-48001A, on page 13. 0x0 28 rstqueues reset queues. used to reset the transmit and receive queues via software. 0 - the tx and rx queues of the GT-48001A are reset according to rstqueue*. 1 - reset the tx and rx queues immeidately. 0x0 29 crcgenen used to enable or disable the crc generation during transmit of cpu generated packets to the gt- 48001a. 0 - crc generation is disabled 1 - crc generation is enabled . 0x0 30 mibclrmode mib counter clear-on-read mode 0 - mib counters will be cleared after they have been read. 1 - mib counters will not cleared after they have been read. 0x0 31 reserved this bit is reserved and must be written to 0. 0x0 bits field name function initial value
GT-48001A switched ethernet controller 76 revision 1.6 port control (8 registers), offset: 0x040200 - 0x04021c note: modifying bits [13:1] of any port control register must be preceeded by disabling that port via bit[1], the endev* input or bit[27] of the global control register (enabledevice). bits field name function initial value 0 porten port enable. 0 - port is disabled 1 - port is enabled 0x1 1 fulldx half/full duplex. 0 - port works in half-duplex mode 1 - port works in full-duplex mode txen (at reset) 3:2 sermode serial mode. these bits indicate the serial mode. the logic order at reset is txddel/txd=[3:2]. 00 - 10base-t 01 - 10base-fl 10 - aui 11 - synchronous txddel/txd (at reset) 4 monmode monitoring mode. 0 - port works in normal mode 1 - port works in monitoring mode; all rx and tx pack- ets are sent to the sniffer 0x0 6:5 reserved reserved. 0x0 7 autopol auto-polarity disable. enable/disable auto-polarity detection function. 0 - disable 1 - enable GT-48001A 0x1 gt-48001 0x0 9:8 reserved reserved. 0x0 10 filbroad filter broadcast. 0 - broadcast packets are forwarded to all ports. 1 - the GT-48001A discards broadcast packets. 0x0 11 forwunk forward unknown. 0 - unknown packets are forwarded. 1 - the GT-48001A does not forward unknown pack- ets to this port. 0x0 12 spanen spanning tree enable. meaningful only when spanen bit in the global con- trol register is set. 0 - all packets are accepted. 1 - the GT-48001A discards all incoming/outgoing packets except for bpdu packets. 0x0 13 vtagen virtual lan tagging packet extension enable 0 - accept packets up to 1518 bytes in length 1 - accept packets up to 1522 bytes in length 0x0
GT-48001A switched ethernet controller revision 1.6 77 status, offset: 0x14002c (read-only) bits field name function initial value 4:0 devnum device number. indicates the GT-48001A number chosen by the designer. daddr[4:0] (at reset) 5 dramsize dram size. indicates the dram size. 0- 2mbyte 1- 1mbyte daddr[5] (at reset) 6 port0par port0 partition. this bit indicates the port 0 partition status. 0 - no partition (normal mode) 1 - partition 0x0 7 port0ltf port0 link test fail. this bit indicates the port 0 link test status. 0 - link test pass 1 - link test fail 0x0 8 port1par port1 partition. this bit indicates the port 1 partition status. 0 - no partition (normal mode) 1 - partition 0x0 9 port1ltf port1 link test fail. this bit indicates the port 1 link test status. 0 - link test pass 1 - link test fail 0x0 10 port2par port2 partition. this bit indicates the port 2 partition status. 0 - no partition (normal mode) 1 - partition 0x0 11 port2ltf port2 link test fail. this bit indicates the port 2 link test status. 0 - link test pass 1 - link test fail 0x0 12 port3par port3 partition. this bit indicates the port 3 partition status. 0 - no partition (normal mode) 1 - partition 0x0 13 port3ltf port3 link test fail. this bit indicates the port 33 link test status. 0 - link test pass 1 - link test fail 0x0 14 port4par port4 partition. this bit indicates the port 4 partition status. 0 - no partition (normal mode) 1 - partition 0x0 15 port4ltf port4 link test fail. this bit indicates the port 4 link test status. 0 - link test pass 1 - link test fail 0x0
GT-48001A switched ethernet controller 78 revision 1.6 cpu and sniffer numbers, offset: 0x140030 16 port5par port5 partition. this bit indicates the port 5 partition status. 0 - no partition (normal mode) 1 - partition 0x0 17 port5ltf port5 link test fail. this bit indicates the port 5 link test status. 0 - link test pass 1 - link test fail 0x0 18 port6par port6 partition. this bit indicates the port 6 partition status. 0 - no partition (normal mode) 1 - partition 0x0 19 port6ltf port6 link test fail. this bit indicates the port 6 link test status. 0 - link test pass 1 - link test fail 0x0 20 port7par port7 partition. this bit indicates the port 7 partition status. 0 - no partition (normal mode) 1 - partition 0x0 21 port7ltf port7 link test fail. this bit indicates the port 7 link test status. 0 - link test pass 1 - link test fail 0x0 bits field name function initial value 4:0 snifdevnum sniffer device number. these bits specify the sniffer device number chosen by the designer. the same value should be pro- grammed to all GT-48001A/GT-48001A devices shar- ing the same pci bus. 0x0 7:5 snifportnum sniffer port number. these bits specify the sniffer port number chosen by the designer. the same value should be programmed to all GT-48001A/gt-48002a devices sharing the same pci bus. 0x0 12:8 cpudevnum cpu device number. these bits specify the device number of the cpu as chosen by the designer. this number must not be the same as any other galnet device is the system. the same value should be programmed to all GT-48001A/ gt-48002a devices sharing the same pci bus. the corresponding bit for the cpudevnum value should be set in the device table (offset 0x40) for all gt- 48001a/gt-48002a devices sharing the same pci bus. 0x0 bits field name function initial value
GT-48001A switched ethernet controller revision 1.6 79 interrupt cause, offset: 0x044 bits field name function initial value 0 reserved reserved 0x0 1 newadd new address. this bit is set by the GT-48001A when a new address is received. 0x0 2 txend tx end of packet. this bit is set by the GT-48001A upon transferring a end_of_packet message to the cpu main mem- ory. 0x0 3 rxstart rx start of packet. this bit is set by the GT-48001A upon sending a start_of_packet message to the cpu. 0x0 4 addrrecf address recognition failed. this bit is set by the GT-48001A when the address recognition cycle fails (due to a large number of mac addresses). 0x0 5 flushtxq flush tx queue. this bit is set by the GT-48001A when one of the tx queues is flushed due to the watchdog timer. 0x0 6 mastrdpar master read parity. this bit is set by the GT-48001A upon master read parity error on the pci. 0x0 7 mastwrpar master write parity. this bit is set by the GT-48001A upon master write error on the pci. 0x0 8 addpar address parity. this bit is set by the GT-48001A upon address parity error on the pci. 0x0 9 mastabort master abort. the this bit is set by the GT-48001A upon master abort on pci. 0x0 10 tarabort target abort. this bit is set by the GT-48001A upon target abort on the pci. 0x0 11 linkchange link state change. this bit is set by the GT-48001A upon a change in the link state (down->up, up->down) for any pin. 0x0 12 part partition. this bit is set by the GT-48001A upon entering parti- tion state in one of the ports. 0x0 13 bufwrap buffer wrap-around. this bit is set by the GT-48001A upon transferring 16 packets to the cpu main memory. 0x0
GT-48001A switched ethernet controller 80 revision 1.6 interrupt mask, offset: 0x048 serial parameters, offset: 0x040220 rx buffers threshold, offset: 0x040224 14 interv intervention. this bit is set by the GT-48001A upon transferring a buffer_request message in intervention mode. 0x0 15 intervwrap intervention wrap-around. this bit is set by the GT-48001A upon transferring 256 buffer_request messages in intervention mode. 0x0 bits field name function initial value 15:0 maskbits mask to the cpu interrupt line for the appropriate bits in the interrupt cause register. the default is to mask all interrupts. 0 - mask interrupt 1 - do not mask interrupt 0x0000 bits field name function initial value 17:0 - reserved. 0x1e104 24:18 ipgdata inter-packet gap (ipg) data. the step is 100ns (1 bit-time). the default value is 96 decimal (9.6 m s). note that the ipg during jam varies between 1 bit-time and 128 bit-times. 096d 31:25 datablind data blinder. datablind is the inhibit time. the time the GT-48001A port does not look at the line to decide to transmit.the range is 0 to 96 in 100ns increments. the default is 64 decimal (6.4us). 064d bits field name function initial value 3:0 txwattim tx watchdog timer. the default is 630msec; the range is 105msec to 1575msec, in steps of 105msec. (0x0 has no mean- ing, illegal condition.) 0x6 (630 ms) 8:4 reserve reserved. 0x04 bits field name function initial value
GT-48001A switched ethernet controller revision 1.6 81 cpu buffer base address, offset: 0x140034 note: when reading the cpu buffer base address register (0x140034), the address will be read out 1 bit shifted left. cpu start_of_packet base address, offset: 0x140038 cpu new_address base address, offset: 0x14003c 12:9 rxbufthr receive buffer threshold. these bits determine the threshold of the receive buff- ers. meaningful only when the bufthren bit in the glo- bal control register is set. the step is 10. the number of buffers is programmed value * 10 + 9. the value varies between 9 (0x0) and 159 (0xf). the default is 29 (0x2) for 1mb dram and 79 (0x7) for 2mb dram. GT-48001A 0x2 (29) w/ 1m dram 0x7 (79) w/ 2m dram gt-48001 0x3 (39) w/ 1m dram 0x7 (79) w/ 2m dram 18:13 - reserved. during writes to this register, bits 18:13 must be written to their default values. 0x1 (1mb dram) 0x13 (2mb dram) bits field name function initial value 31:15 baseadd contains a pointer to the cpu buffer area 0x0 14:0 reserve reserved. must be 0x0 when written. - bits field name function initial value 31:8 stbaseadd contains a pointer to the cpu start_of_packet area. the area includes 32 entries (2 32-bit words each) for the GT-48001As start_of_packet messages. 0x0 7:0 reserve reserved. must be 0x0 when written. - bits field name function initial value 31:8 nabaseadd contains a pointer to the cpu new_address area. the area includes 32 entries (2 32-bit words each) for the GT-48001As new_address messages. 0x0 7:0 reserve reserved. must be 0x0 when written. - bits field name function initial value
GT-48001A switched ethernet controller 82 revision 1.6 cpu intervention base address, offset: 0x140048 device table, offset: 0x40 time out counter, offset: 0x4c bits field name function initial value 31:11 intbaseadd contains a pointer to the cpu buffer_request area for unicast packets that are marked for interven- tion. the area includes 256 entries (2 32-bit words each) for the GT-48001As buffer_request messages. 0x0 10:0 reserve reserved. must be 0x0 when written. - bits field name function initial value 31:0 devtab GT-48001A device table. each bit represents a gt- 48001a device in the system. 0xffffffff bits field name function initial value 7:0 timeout0 specifies in pci clock units the number of clocks the GT-48001A holds the pci bus before the generation of retry termination. used for the first data transfer. 0x0f (16 clocks) 15:8 timeout1 specifies in pci clock units the number of clocks the GT-48001A holds the pci bus before the generation of retry termination. used for data transfers following the first data. 0x07 (8 clocks) 23:16 retrycounter specifies the number of retries the GT-48001A attempts to do in the pci before aborting the transac- tion. value of 0x0 disable this counter (unlimited retries). 0xff (256 times)
GT-48001A switched ethernet controller revision 1.6 83 port mib counters (8 blocks), offset: 0x040000 - 0x0401fc the cpu must read all of the mib counters during initialization in order to reset the counters to 0. all counters are 32- bits. the counters will only be reset to 0 if mibclrmode (bit 30 of the global control register) is set to 0 (default). if mibclrmode bit is 1, reading the mib counters will have no effect. the cpu must access the counters using single datum transactions (burst reads/writes are not allowed.) table 37 lists definitions for terms used in the counter descriptions. table 37: definitions used in counter descriptions term definition packet data section all data bytes in the packet following the sfd until the end of the packet packet data length the number of data bytes in the packet data section data octet a single byte from the packet data section received good packet a received packet which is not rejected and enters the switching core to be trans- mitted later received good uni- cast packet a received packet which is not rejected and enters the switching core to be trans- mitted later, with destination address which is a unicast address received good multi- cast packet a received packet which is not rejected and enters the switching core to be trans- mitted later, with destination address which is a multicast address received good broadcast packet a received packet which is not rejected and enters the switching core to be trans- mitted later, with destination address which is a broadcast address transmitted good packet any transmitted packet from the GT-48001A dropped packet a received packet which is ignored due to lack of available receive buffers (port is in buffer_full state) local packet a received packet whose destination address is mapped to the receiving port rejected packet a received packet which is not forwarded due to error such as bad crc, rx error event, invalid size (too short or too long). mibctrmode bit 26, mibctrmode, of the global control register (offset 0x140028) vtagen bit 13, vtagen, of the port control register (offset 0x040200-0x04021c) maxframesize 1518 for vtagen = 0 (default) or 1522 for vtagen = 1
GT-48001A switched ethernet controller 84 revision 1.6 table 38: port mib counters address for port 0 counter name function initial value 0x040000 bytrec mibctrmode = 0: the total number of data octets for all received good unicast packets which are forwarded to the switching core for transmission. mibctrmode = 1: the total number of data octets for all received good unicast packets which are forwarded to the switching core for transmission and for local and dropped packets. - 0x040004 mulbytrec mibctrmode = 0: the total number of data octets for all received good multicast packets which are forwarded to the switching core for transmission. mibctrmode = 1: the total number of data octets for all received good multicast packets which are forwarded to the switching core for transmission and for local and dropped packets. - 0x040008 broadbytrec mibctrmode = 0: the total number of data octets for all received good broadcast packets which are forwarded to the switching core for transmission. mibctrmode = 1: the total number of data octets for all received good broadcast packets which are forwarded to the switching core for transmission and for local and dropped packets. - 0x04000c bytsent the total number of data octets for all transmitted good packets. - 0x040010 frarec mibctrmode = 0: the total number of all received good uni- cast packets which are forwarded to the switching core for transmission. mibctrmode = 1: the total number of all received good uni- cast packets which are forwarded to the switching core for transmission and for local and dropped packets. - 0x040014 mulfrarec mibctrmode = 0: the total number of all received good mul- ticast packets which are forwarded to the switching core for transmission. mibctrmode = 1: the total number of all received good mul- ticast packets which are forwarded to the switching core for transmission and for local and dropped packets. - 0x040018 broadfrarec mibctrmode = 0: the total number of all received good broadcast packets which are forwarded to the switching core for transmission. mibctrmode = 1: the total number of all received good broadcast packets which are forwarded to the switching core for transmission and for local and dropped packets. - 0x04001c frasent the total number of all transmitted good packets. - 0x040020 coll the total number of collisions that have been detected up to 512 bits of the transmitted/received packet data length. - 0x040024 latecoll the total number of collisions has been detected after trans- mitted/received packet data length exceeded 512 bits. -
GT-48001A switched ethernet controller revision 1.6 85 0x040028 crcaligerr the total number of received packets with valid packet data length between 64 and maxframesize bytes inclusive that had bad crc and which a collision did not occur. - 0x04002c jabber the total number of received packets with packet data length greater than maxframesize bytes that had bad crc, with or without occuring collisions. - 0x040030 frashort the total number of received packets (not including packets with collision) that: - packet data length is less than 64 bytes -or- - packet without sfd and were less than 552 bits in length. - 0x040034 fralong the total number of received packets with valid crc and packet data length greater than maxframesize. - 0x040038 badbytrec the total number of data octets in all received packets with bad crc and frame too long conditions (jabber and over- size packets). - 0x04003c droppedpkts this counter should be incremented once for every received packet which which is not transferred to the switching core to due lack of a available receive buffer. - 0x040040 beginning of the mib counter structure for port 1. the above structure repeats every 0x40 bytes for the remaining ports. table 38: port mib counters address for port 0 counter name function initial value
GT-48001A switched ethernet controller 86 revision 1.6 pci global counters, offset: 0x140040 - 0x140044 the cpu must read all counters during initialization in order to reset the counters to 0. all counters are 32-bits. 21.2 pci configuration registers the gt- 48001a contains the required pci configuration registers. these registers are accessed from the pci. device and vendor id, pci offset: 0x0 (read only) status and command, pci offset: 0x4 table 39: pci mib counters address counter name function initial value 0x140040 pcifrarec good frames received from the pci 0x0 0x140044 pcifrasent good frames sent to the pci 0x0 bits field name function initial value 15:0 venid vendor id. provides the manufacturer of the pci device. for the GT-48001A this is galileos pci ven- dor id (0x11ab.) 0x11ab 31:16 devid provides the unique gt- 48001a device id number 0x4801 bits field name function initial value 1 memen memory enable. controls the GT-48001As response to memory accesses. 0 - disable, the GT-48001A will ignore all memory accesses on the pci bus. 1 - enable, the GT-48001A will respond to memory accesses on the pci bus. 0x1 2 masen master enable. controls the GT-48001As ability to act as a master on the pci bus. 0 - disable 1 - enable 0x1 4 memwrinv memory write and invalidate. controls the GT-48001As ability to generate memory write and invalidate commands on the pci bus. 0 - disable 1 - enable 0x0 5 reserved reserved. read only. 0x0 6 paren parity enable. controls the GT-48001As ability to respond to parity errors on the pci. 0 - disable 1 - enable 0x0
GT-48001A switched ethernet controller revision 1.6 87 class code and revision id, offset: 0x008 (read-only) 8 syserren system error enable. controls the GT-48001As ability to assert the serr* pin. 0 - disable 1 - enable 0x0 22:9 reserve reserved. read only. 0x0 23 tarfastbb target fast back-to-back. this indicates that the GT-48001A is capable of accepting fast back-to-back transactions on the pci bus. read-only bit. 0x1 24 datapardet data parity detected. this bit is set by the GT-48001A when it detects a data parity error during a master operation. this bit is cleared by writing 1 to it. 0x0 26:25 devseltim device select timing. these bits indicate the GT-48001As devsel* timing. the GT-48001As devsel* timing is always set at medium (01), as defined in the pci specification. read only. 0x1 28 tarabort target abort. this bit is set upon target abort. this bit is cleared by writing 1 to it. 0x0 29 mastabort master abort. this pin is set upon master abort. this bit is cleared by writing 1 to it. 0x0 30 syserror system error. this pin is set upon system error. this bit is cleared by writing 1 to it. 0x0 31 detparerr detected parity error. this pin is set upon detection of parity error (in both master and slave operations). this bit is cleared by writing 1 to it. 0x0 bits field name function initial value 7:0 revid revision id. indicates the GT-48001A revision number. GT-48001A 0x10 gt-48001 0x00 23:16 subclass subclass. indicates the GT-48001A subclass (0x0 - ethernet). 0x0 31:24 baseclass base class. indicates the GT-48001A base class (0x2 - network device). 0x2 bits field name function initial value
GT-48001A switched ethernet controller 88 revision 1.6 header type, latency timer, cache line, offset: 0x00c for more information on these fields, please refer to the pci specification. internal register/dram base address register, offset: 0x010 note: this register has special behavior in a plug and play environment (see section 11.4 on page 45). the device number can be changed in this register after reset (see section 7.3 on page 26). interrupt pin and line, offset: 0x03c bits field name function initial value 7:0 cacheline cache line. specifies the GT-48001As cache line size (size=8). read only. 0x7 15:8 lattimer latency timer. specifies in units of pci bus clocks the value of the latency timer of the GT-48001A. default is 256 cycles (0xff). 0xff 23:16 headtype header type. specifies the layout of bytes 10 hex through 3f hex. 0x0 bits field name function initial value 21:0 - these bits are cleared. 0x0 21 dramaccess 0 - access internal registers 1 - access dram array 0x0 26:22 devnum device number. these bits specify the galnet device number. daddr[4:0] at reset 31:27 baseadd galnet protocol region (gpr) base address. these bits set the base address for the galnet proto- col region. all galnet devices in a system must have the same gpr base address (see text.) 0x1 bits field name function initial value 7:0 intline interrupt line. provides interrupt line routing information. 0x0 15:8 intpin interrupt pin. indicates which interrupt pin the GT-48001A uses. the GT-48001A uses inta in the pci slot. 0x1
GT-48001A switched ethernet controller revision 1.6 89 21.3 register modification restrictions below are two registers for which the port should be disabled before bits are modified by the cpu. note that all ports must be disabled before modifying the bits in the serial parameters register. table 40: port control register bit modification restrictions (offset 0x040200 - 0x04021c) bit # bit name must disable port? 0porten n/a 1fulldx no 3:2 sermode yes 4monmode no 6:5 reserved- do not modify n/a 7 autopol no 9:8 reserved- do not modify n/a 10 filbroad no 11 forwunk no 12 spanen no 13 vtagen yes table 41: serial parameters register bit modification restrictions (offset 0x040220) bit # bit name must disable all ports? 17:0 reserved- do not modify n/a 24:18 ipgdata yes 31:25 datablind yes
GT-48001A switched ethernet controller 90 revision 1.6 22. pinout for 208 pin pqfp (sorted by number) pin # signal name pin # signal name pin # signal name 1 ad[4] 36 ddata[5] 71 crs/rxen[6] 2 ad[3] 37 ddata[4] 72 pol[6]/auilinkup[6] 3 ad[2] 38 ddata[3] 73 txen[6] 4 ad[1] 39 ddata[2] 74 txd[6] 5 ad[0] 40 ddata[1] 75 txddel[6] 6 ddata[31] 41 ddata[0] 76 rxd[5] 7 ddata[30] 42 vdd 77 rxlp/coll[5] 8 ddata[29] 43 vss 78 crs/rxen[5] 9 ddata[28] 44 cas* 79 pol[5]/auilinkup[5] 10 ddata[27] 45 we* 80 txen[5] 11 ddata[26] 46 ras[1]* 81 txd[5] 12 ddata[25] 47 ras[0]* 82 txddel[5] 13 ddata[24] 48 chipsel* 83 rxd[4] 14 ddata[23] 49 daddr[8] 84 rxlp/coll[4] 15 ddata[22] 50 daddr[7] 85 crs/rxen[4] 16 ddata[21] 51 daddr[6] 86 pol[4]/auilinkup[4] 17 ddata[20] 52 daddr[5] 87 txen[4] 18 ddata[19] 53 daddr[4] 88 txd[4] 19 ddata[18] 54 daddr[3] 89 txddel[4] 20 vdd 55 daddr[2] 90 vdd 21 vss 56 daddr[1] 91 sclk/synclk20 22 ddata[17] 57 daddr[0] 92 vss 23 ddata[16] 58 vdd 93 vdd 24 vdd 59 vss 94 vss 25 vss 60 rxd[7] 95 rxd[3] 26 ddata[15] 61 rxlp/coll[7] 96 rxlp/coll[3] 27 ddata[14] 62 crs/rxen[7] 97 crs/rxen[3] 28 ddata[13] 63 pol[7]/auilinkup[7] 98 pol[3]/auilinkup[3] 29 ddata[12] 64 txen[7] 99 txen[3] 30 ddata[11] 65 txd[7] 100 txd[3] 31 ddata[10] 66 txddel[7] 101 txddel[3] 32 ddata[9] 67 vdd 102 rxd[2] 33 ddata[8] 68 vss 103 rxlp/coll[2] 34 ddata[7] 69 rxd[6] 104 crs/rxen[2] 35 ddata[6] 70 rxlp/coll[6] 105 pol[2]/auilinkup[2]
GT-48001A switched ethernet controller revision 1.6 91 106 txen[2] 141 limit4 176 ad[17] 107 txd[2] 142 vdd 177 ad[16] 108 txddel[2] 143 vss 178 cbe[2]* 109 rxd[1] 144 int* 179 frame* 110 rxlp/coll[1] 145 rst* 180 vss 111 crs/rxen[1] 146 vdd 181 vdd 112 pol[1]/auilinkup[1] 147 clk 182 irdy* 113 txen[1] 148 vss 183 trdy* 114 txd[1] 149 gnt* 184 devsel* 115 txddel[1] 150 req* 185 stop* 116 rxd[0] 151 vss 186 perr* 117 rxlp/coll[0] 152 vdd 187 vss 118 crs/rxen[0] 153 ad[31] 188 vdd 119 pol[0]/auilinkup[0]/ synclk10 154 ad[30] 189 serr* 120 txen[0] 155 ad[29] 190 par 121 txd[0] 156 ad[28] 191 cbe[1]* 122 txddel[0] 157 vss 192 ad[15] 123 vdd 158 vdd 193 ad[14] 124 vss 159 ad[27] 194 vss 125 endev* 160 ad[26] 195 ad[13] 126 rstqueue* 161 ad[25] 196 ad[12] 127 vss 162 ad[24] 197 ad[11] 128 vss 163 cbe[3]* 198 ad[10] 129 vss 164 idsel 199 ad[9] 130 diswd* 165 vss 200 vss 131 enelscrub* 166 vdd 201 vdd 132 skipinit* 167 ad[23] 202 ad[8] 133 scan* 168 ad[22] 203 cbe[0]* 134 tristate* 169 ad[21] 204 ad[7] 135 vss 170 ad[20] 205 ad[6] 136 ledclk 171 ad[19] 206 ad[5] 137 leddata 172 vss 207 vss 138 ledstb 173 vdd 208 vdd 139 ledmode 174 vss 140 disbufthr* 175 ad[18] pin # signal name pin # signal name pin # signal name
GT-48001A switched ethernet controller 92 revision 1.6 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 daaddr[5] daaddr[6] daaddr[7] daaddr[8] chipsel* ras[0]* ras[1]* we* cas* vss vdd ddata[0] ddata[1] ddata[2] ddata[3] ddata[4] ddata[5] ddata[6] ddata[7] ddata[8] ddata[9] ddata[10] ddata[11] ddata[12] ddata[13] ddata[14] ddata[15] vss vdd ddata[16] ddata[17] vss vdd ddata[18] ddata[19] ddata[20] ddata[21] ddata[22] ddata[23] ddata[24] ddata[25] ddata[26] ddata[27] ddata[28] ddata[29] ddata[30] ddata[31] ad[0] ad[1] ad[2] ad[3] ad[4] pol[2] txen[2] txd[2] txddel[2] rxd[1] rxlp/coll[1] crs/rxen[1] pol[1] txen[1] txd[1] txddel[1] rxd[0] rxlp/coll[0] crs/rxen[0] pol[0] txen[0] txd[0] txddel[0] vdd vss endev* rstqueue* vss vss vss diswd* enelscrub* skipinit* scan* tristate* vss ledclk leddata ledstb ledmode disbufthr* limit4 vdd vss int* rst* vdd clk vss gnt* req* vss vdd ad[31] ad[30] ad[29] ad[28] 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 crs/rxen[2] rxlp/coll[2] rxd[2] txddel[3] txd[3] txen[3] pol[3] crs/rxen[3] rxlp/coll[3] rxd[3] vss vdd vss sclk/synclk20 vdd txddel[4] txd[4] txen[4] pol[4] crs/rxen[4] rxlp/coll[4] rxd[4] txddel[5] txd[5] txen[5] pol[5] crs/rxen[5] rxlp/coll[5] rxd[5] txddel[6] txd[6] txen[6] pol[6] crs/rxen[6] rxlp/coll[6] rxd[6] vss vdd txddel[7] txd[7] txen[7] pol[7] crs/rxen[7] rxlp/coll[7] rxd[7] vss vdd daddr[0] daddr[1] daddr[2] daddr[3] daddr[4] 157 158 159 160 161 162 153 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 vss vdd ad[27] ad[26] ad[25] ad[24] cbe[3]* idsel vss vdd ad[23] ad[22] ad[21] ad[20] ad[19] vss vdd vss ad[18] ad[17] ad[16] cbe[2]* frame* vss vdd irdy* trdy* devsel* stop* perr* vss vdd serr* par cbe[1]* ad[15] ad[14] vss ad[13] ad[12] ad[11] ad[10] ad[9] vss vdd ad[8] cbe[0]* ad[7] ad[6] ad[5] vss vdd 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 pinout of 208 lead qfp for the GT-48001A alileo ? GT-48001A-p-x 22.1 package/pin drawing
GT-48001A switched ethernet controller revision 1.6 93 23. dc characteristics - preliminary/subject to change 23.1 absolute maximum ratings 23.2 recommended operating conditions 23.3 dc electrical characteristics over operating range (tc=0-70 c; vdd=+5v, +/-5%) symbol parameter min. max. unit vdd supply voltage -0.3 6.5 v vi input voltage -0.3 vdd+0.3 v vo output voltage -0.3 vdd+0.3 v io output current 24 ma iik input protect diode current +-20 ma iok output protect diode current +-20 ma tc operating case temperature 0 70 c tstg storage temperature -40 125 c esd 2000 v symbol parameter min. typ. max. unit vdd supply voltage 4.75 5.25 v vi input voltage 0 vdd v vo output voltage 0 vdd v tc case operating temperature 0 70 c cin input capacitance 7.2 pf cout output capacitance 7.2 pf symbol parameter test condition min. typ. max. unit vih input high level guaranteed logic high level 2.0 vdd + 0.5v v vil input low level guaranteed logic low level -0.5 0.8 v voh output high voltage ioh = 2 ma ioh = 4 ma ioh = 8 ma ioh = 12 ma ioh = 16 ma ioh = 24 ma 2.4 v vol output low voltage iol = 2 ma iol = 4 ma iol = 8 ma iol = 12 ma iol = 16 ma iol = 24 ma 0.4 v
GT-48001A switched ethernet controller 94 revision 1.6 note: pullup/pulldown resistors are 45kohm minimum, 65kohm typical, 80kohm maximum. 23.4 thermal data table 42 shows the package thermal data for the GT-48001A. galileo recommends the use of heatsink for most sys- tems, especially those with little or no airflow. please check with galileo if you are in doubt as to thermal considerations for your system. 1. operating the device for extended periods of time at the maximum junction temperature may cause permanent damage to this device, resulting in functional or reliability type failures. iih input high current +-1 ua iil input low current +-1 ua iozh high impedance output current +-1 ua iozl high impedance output current +-1 ua vh input hysteresis vdd = 4.5v vdd = 5.0v vdd = 5.5v 0.52 0.54 0.56 0.60 0.61 0.62 mv icc operating current vdd = 5.25v f=33mhz 600 ma table 42: 208 pqfp thermal data parameter definition value q ja thermal resistance: junction to ambient, 0 ft/s airflow 22.5 c/w q jc thermal resistance: junction to case, 0 ft/s airflow 5 c/w t j operating junction temperature 100c t j maximum junction temperature 1 125c symbol parameter test condition min. typ. max. unit
GT-48001A switched ethernet controller revision 1.6 95 24. ac timing - preliminary/subject to change (tc= 0-70 o c; vdd= +5v, +/- 5%) notes: 1. all delays, setup, and hold times are referred to clk rising edge, unless stated otherwise. 2. all outputs are specified for 50pf load. 3. all inputs and all outputs also refer to i/o signal behavior. figure 20: serial clock waveform (sclk) symbol signals description min max unit clk system clock 30 33 mhz clk rise/fall time (pci specification rev. 2.1) 1 4 v/ns rst*, frame*, irdy*, trdy*, devsel*, stop*, perr*, par, int* ad[31:0], cbe[3:0]*, gnt*, idsel, req*, serr* see pci specification rev. 2.1. t1 sclk rise time 2 ns t2 sclk fall time 2 ns sclk frequency stability +/- 50 ppm t3 daddr[8:0], ddata[31:0], cas*, ras*, we*, chipsel* delay from clock rising or falling edge 2 17 ns t4 ddata[31:0], rst- queue*, endev* setup 10 ns t5 ddata[31:0], rst- queue*, endev* hold 1 ns t6 ddata[31:0] float delay 2 18 ns t7 ddata[31:0] drive delay 2 12 ns sclk voh vol t1 t2
GT-48001A switched ethernet controller 96 revision 1.6 figure 21: output delay from rising edge figure 22: input setup and hold figure 23: output delay from clock t3 min clk output t3 max valid t4 t5 clk input t3 min t3 max clk output
GT-48001A switched ethernet controller revision 1.6 97 figure 24: output float and drive delay clk valid valid output t6 t7
GT-48001A switched ethernet controller 98 revision 1.6 25. functional waveforms figure 25: edo dram read figure 26: edo dram write 25.1 pci read/write cycle the GT-48001A uses standard pci read and write cycles. the longest burst that is executed by at GT-48001A device is eight words. rc0c1c2c3 d0 d3 d2 d1 clk daddr[8:0] ras* cas* we* ddata[31:0] data sampled at arrow tip rc0 c3 c2 c1 d3 d2 d1 d0 clk daddr[8:0] ras* cas* we* ddata[31:0]
GT-48001A switched ethernet controller revision 1.6 99 figure 27: pci cycle waveform ad0d1 d7 d6 d5 d4 d3 d2 c be=0 clk req* gnt* ad[31:0] cbe*[3:0] frame* devsel* irdy* trdy* stop*
GT-48001A switched ethernet controller 100 revision 1.6 26. packaging figure 28: 208 lead pqfp package outline table 43: 208 pqfp package dimensions millimeters symbol min. nom. max. a 1 0.05 0.25 0.50 a 2 3.17 3.32 3.47 b 0.10 0.20 0.30 c 0.10 0.15 0.20 d 27.90 28.00 28.10 e 27.90 28.00 28.10 e0.50 hd 30.35 30.60 30.85 he 30.35 30.60 30.85 l 0.45 0.60 0.75 l 1 1.30 y0.08 q0 7 a 1 he e hd d b a 2 l l 1 0.08(0.003) m y e c
GT-48001A switched ethernet controller revision 1.6 101 27. document history table 44: document history document type rev. number date comments preliminary rev. 1.0 1/30/97 first revision of preliminary revision for gen- eral distribution. preliminary rev. 1.1 2/18/97 the following were revised: message forwarding, galnet messages, uni- cast intervention mode description preliminary rev. 1.2 4/4/97 added/revised sections: enabling/disabling device, dram, serial interface, interrupts, spanning tree, hp ease registers, rx buffer threshold, mib counter descriptions, theta ja and theta jc values preliminary rev. 1.3 4/28/97 revised sections: serial interface removed: synchronous mode preliminary rev. 1.4 7/17/97 revised sections: enabling/disabling device, theta ja and theta jc values, default register values, cpu to galnet new_address message re-added: sychronous mode preliminary rev. 1.5 8/19/97 revised sections: rxbuffer threshold enable led, forwarding packets direct to the cpu preliminary rev. 1.6 12/29/97 revised sections: corrected plug and play memory size response in section 11.4 to 0xffc0.0000 (4 megabytes), added synchronous mode tim- ings and additional info, coll* input for syn- chronous mode is referenced to synclk20, not synclk10 as shown in the 1.5 datasheet, added table of bits that cannot be modified without disabling the port, phone number changed (we moved!).

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