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ds05-50224-1e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & fcram cmos 64m ( 16) page flash memory & 32m ( 16) mobile fcram tm mb84vp23481fk -70 n n n n features ? power supply voltage of 2.7 v to 3.1 v ? high performance 25 ns maximum page read access time, 65 ns maximum random access time (flash) 20 ns maximum page read access time, 70 ns maximum random access time (fcram) ? operating temperature C30 c to +85 c ? package 65-ball fbga (continued) n n n n product lineup *: both v cc f and v cc r must be the same level when either part is being accessed. n n n n pac k ag e flash fcram supply voltage (v) v cc f* = 3.0 v v cc r* = 3.0 v max random address access time (ns) 65 70 max page address access time (ns) 25 20 max ce access time (ns) 65 70 max oe access time (ns) 25 40 65-ball plastic fbga (bga-65p-m01) +0.1 v C0.3 v +0.1 v C0.3 v
mb84vp23481fk -70 2 (continued) flash memory ? simultaneous read/write operations (dual bank) ? flexbank tm * 1 bank a: 8 mbit (8 kb 8 and 64 kb 15) bank b: 24 mbit (64 kb 48) bank c: 24 mbit (64 kb 48) bank d: 8 mbit (8 kb 8 and 64 kb 15) ?8 words page ? compatible with jedec-standard commands uses same software commands as e 2 proms ? minimum 100,000 program/erase cycles ? sector erase architecture eight 8 kbytes, a hundred twenty-six 64 kbytes, eight 8 kbytes sectors. any combination of sectors can be concurrently erased. also supports full chip erase ? dual boot block sixteen to 8kbytes boot block sectors, eight at the top of the address range and eight at the bottom of the address range ? hiddenrom region 256 byte of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ?wp /acc input pin at v il , allows protection of outermost 2 4 k words on both ends of boot sectors, regardless of sector pro- tection/unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance ? embedded erase tm * 2 algorithms automatically preprograms and erases the chip or any sector ? embedded program tm * 2 algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, the device automatically switches itself to low power mode ? program suspend/resume suspends the program operation to allow a read in another byte ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? new sector protection persistent sector protection password sector protection ? please refer to mbm29qm64df datasheet in detailed function (continued)
mb84vp23481fk -70 3 (continued) fcram tm * 3 ? power dissipation operating : 30 ma max standby : 100 m a max ?power down mode sleep : 10 m a max 4m partial : 45 m a max 8m partial : 55 m a max 16m partial: 70 m a max ? power down control by ce2r ? byte write control: lb (dq 7 to dq 0 ), ub (dq 15 to dq 8 ) ? 8 words page access capability *1: flexbank tm is a trademark of fujitsu limited, japan. *2: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. *3: mobile fcram tm is a trademark of fujitsu limited, japan.
mb84vp23481fk -70 4 n n n n pin assignment (top view) marking side (bga-65p-m01) d8 a 13 d7 a 9 d6 a 20 d5 ry/by d4 a 18 d3 a 5 d2 a 2 d9 a21 f8 n.c f7 dq 6 dq 1 f3 v ss f2 a 0 f9 a 16 g8 dq 15 g7 dq 13 g6 dq 4 g5 dq 3 g4 dq 9 g3 oe g2 cef g9 n.c e8 a 14 e7 a 10 e4 a 17 e3 a 4 e2 a 1 e9 n.c. h8 dq 7 h7 dq 12 h6 vccr h5 vccf h4 dq 10 h3 dq 0 h2 ce1r h9 vss j8 dq 14 j7 dq 5 j6 n.c j5 dq 11 j4 dq 2 j3 dq 8 k9 n.c. k2 n.c. k1 n.c. k10 n.c. c8 a 12 c7 a 19 c6 ce2r c5 reset c4 ub c3 a 6 c2 a 3 c9 a 15 b8 a 11 b7 a 8 b6 we b5 wp/acc b4 lb b3 a 7 a9 n.c. b1 n.c. a10 n.c. a2 n.c. a1 n.c. f4
mb84vp23481fk -70 5 n n n n pin description pin name input/ output description a 20 to a 0 i address inputs (common) a 21 i address input (flash) dq 15 to dq 0 i/o data inputs/outputs (common) ce f i chip enable (flash) ce 1r i chip enable (fcram) ce2r i chip enable (fcram) oe i output enable (common) we i write enable (common) ry/by o ready/busy output (flash) open drain output ub i upper byte control (fcram) lb i lower byte control (fcram) reset i hardware reset pin/sector protection unlock (flash) wp /acc i write protect / acceleration (flash) n.c. no internal connection v ss power device ground (common) v cc f power device power supply (flash) v cc r power device power supply (fcram)
mb84vp23481fk -70 6 n n n n block diagram v ss v cc r 64 m bit page reset flash memory we 32 m bit fcram ce f a 21 to a 0 oe ce 1r v ss v cc f a 21 to a 0 a 20 to a 0 dq 15 to dq 0 ry/by lb ub wp /acc ce2r dq 15 to dq 0 dq 15 to dq 0
mb84vp23481fk -70 7 n n n n device bus operations legend: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance. see n dc characteristics for voltage levels. *1 : other operations except for indicated this column are inhibited. *2 : do not apply for two or more states of the following conditions at the same time; ce f = v il ce 1r = v il and ce2r = v ih *3 : should not be kept fcram output disable condition longer than 1 m s. *4 : we can be v il if oe is v il , oe at v ih initiates the write operations. *5 : it is also used for the extended sector group protections. *6 : fcram power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of power down program. please refer to power down program in fcram characteristics part. *7 : oe can be v il during write operation if the following conditions are satisfied; 1) write pulse is initiated by ce 1r (refer to ce 1r controlled write timing), or cycle time of the previous operation cycle is satisfied. 2) oe stays v il during write cycle. *8 : can be either v il or v ih but must be valid before read or write. *9 : protect outer most 2x8k bytes (4 words) on both ends of the boot block sectors. operation* 1, * 2 ce fce 1r ce2r oe we lb ub a 21 to a 0 dq 7 to dq 0 dq 15 to dq 8 reset wp /acc* 9 full standby h h h x x x x x high-z high-z h x output disable* 3 hl hhhxx x* 8 high-z high-z h x lh read from flash* 4 lhhlhxxvalidd out d out hx write to flash l h h h l x x valid d in d in hx read from fcram h l h l h ll valid d in d in hx hl high-z d in lh d in high-z fcram no read h l h l h h h valid high-z high-z h x write to fcram h l h h* 7 l ll valid d in d in hx hl high-z d in lh d in high-z fcram no write h l h h* 7 l h h valid high-z high-z h x flash temporary sector group unprotection* 5 xx xxxxx x x x v id x flash hardware reset x h h x x x x x high-z high-z l x flash boot block sector write protection xx xxxxx x x x x l fcram power down* 6 xx lxxxx x x x x x
mb84vp23481fk -70 8 n n n n absolute maximum ratings *1 minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C1.0 v for periods of up to 5 ns. maximum dc voltage on input or i/o pins is v cc f + 0.3 v or v cc r + 0.3v. during voltage transitions, input or i/o pins may overshoot to v cc f + 2.0 v or v cc r + 1.0 v for periods of up to 5 ns. *2: minimum dc input voltage on reset pin is C0.5 v. during voltage transitions reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc f) does not exceed +9.0 v. maximum dc input voltage on reset pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3: minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot vss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C30 +85 c voltage with respect to ground all pins except reset , wp /acc * 1 v in , v out C0.3 v cc f + 0.3 v v cc r + 0.3 v v cc f/v cc r supply * 1 v cc f, v cc rC0.3 +3.3v reset * 2 v in C0.5 + 13.0 v wp /acc * 3 v in C0.5 +10.5 v parameter symbol value unit min max ambient temperature t a C30 +85 c v cc f/v cc r supply voltages v cc f, v cc r +2.7 +3.1 v
mb84vp23481fk -70 9 n n n n dc characteristics (continued) parameter sym- bol conditions value unit min typ max input leakage current i li v in = v ss to v cc f, v cc r C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc f, v cc r, output disable C1.0 +1.0 m a reset inputs leakage current (flash) i lit v cc f = v cc f max, reset = 12.5 v 35 a wp /acc acceleration program cur- rent (flash) i lia v cc f = v cc f max, wp /acc = v acc max 20 ma flash v cc active current * 1, * 6 (initial/random read) i cc1 f ce f = v il , oe = v ih , f = 10 mhz 45 ma ce f = v il , oe = v ih , f = 5 mhz 20 ma flash v cc active current * 2 i cc2 fce f = v il , oe = v ih 25ma flash v cc current (page mode) * 9, * 6 i cc3 fce f = v il , oe = v ih , f = 40 mhz 10 ma flash v cc active current* 5, * 6 (read-while-program) i cc4 fce f = v il , oe = v ih 45ma flash v cc active current* 5, * 6 (read-while-erase) i cc5 fce f = v il , oe = v ih 45ma flash v cc active current* 5, * 6 (erase-suspend-program) i cc6 fce f = v il , oe = v ih 25ma flash v cc current (standby) * 6 i sb1 f v cc f = v cc f max,ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc =v cc f 0.3 v 1 5a flash v cc current (standby, reset) * 6 i sb2 fv cc f = v cc f max, reset = v ss 0.3 v 1 5 a flash v cc current (automatic sleep mode)* 3 i sb3 f v cc f = v cc f max, ce f= v ss 0.3 v, reset = v cc f 0.3 v, v in = v cc f 0.3 v or v ss f 0.3 v 1 5a fcram v cc active current * 6, * 8 i cc1 r v cc r = v cc r max, ce 1r = v il , ce2r = v ih, v in = v ih or v il , i out = 0 ma* 7 t rc / t wc =min 30 ma i cc2 r t rc / t wc =1 m s 3 fcram v cc page read current * 6, * 8 i cc3 r v cc r = v cc r max, v in = v ih or v il , ce 1r = v il , ce2r = v ih, i out = 0 ma * 7 , t prc =min 10ma fcram v cc standby current * 6, * 8 i sb1 r v cc r = v cc r max, v in < 0.2v or > v cc r C 0.2v ce 1r > v cc r C 0.2v, ce2r > v cc rC 0.2v 100 m a fcram v cc power down current * 6, * 8 i ddps r v cc r = v cc r max, ce2r < 0.2v, v in = v ih or v il sleep 10 m a i ddp4 r4m partial45 m a i ddp8 r8m partial55 m a i ddp16 r16m partial70 m a
mb84vp23481fk -70 10 (continued) *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: applicable for only v cc f applying. *5: embedded algorithm (program or erase) is in progress. (@5 mhz) *6: v cc indicates lower of v cc f or v cc r. *7: fcram characteristics are measured after following power-up timing. *8: i out depends on the output load conditions. *9: address except a 2 , a 1 and a 0 are fixed. parameter sym- bol conditions value unit min typ max input low level v il C0.3 v cc 0.2 * 6 v input high level v ih v cc 0.8 * 6 v cc + 0.2 * 6 v voltage for sector protection, and temporary sector unprotection (reset ) * 4 v id 11.5 12 12.5 v voltage for wp /acc sector protection/unprotection and program acceleration * 4 v acc 8.5 9.0 9.5 v output low voltage level v ol fv cc f = v cc f min, i ol =4.0 ma flash 0.4v v ol rv cc r = v cc r min, i ol =1.0ma fcram 0.4v output high voltage level v oh f v cc f = v cc f min, i oh =C2.0 ma flash 2.4 v v oh r v cc r = v cc r min, i oh =C0.5 ma fcram 2.4 v flash low v cc f lock-out voltage v lko 2.3 2.4 2.5 v
mb84vp23481fk -70 11 n n n n ac characteristics ?ce timing ? timing diagram for alternating ram to flash ? flash characteristics please refer to n 64 m paeg flash memory characteristics for mcp. ? fcram characteristics please refer to n 32 m fcram characteristics for mcp. parameter symbol condition value unit jedec standard min max ce recover time t ccr 0ns ce hold time t chold 3ns ce 1r high to we invalid time for standby entry t chwx 10ns ce f t ccr t ccr ce 1r ce2r t ccr t ccr we t chwx t chold
mb84vp23481fk -70 12 n n n n 64 m paeg flash memory characteristics for mcp 1. flexible sector-erase architecture on flash memory ? sixteen 4k words, and one hundred twenty-six 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. sector architecture sa31 : 64kb (32kw) sa30 : 64kb (32kw) sa29 : 64kb (32kw) sa28 : 64kb (32kw) sa27 : 64kb (32kw) sa26 : 64kb (32kw) sa25 : 64kb (32kw) sa24 : 64kb (32kw) sa23 : 64kb (32kw) sa22 : 64kb (32kw) sa21 : 64kb (32kw) sa20 : 64kb (32kw) sa19 : 64kb (32kw) sa18 : 64kb (32kw) sa17 : 64kb (32kw) sa16 : 64kb (32kw) sa15 : 64kb (32kw) sa14 : 64kb (32kw) sa13 : 64kb (32kw) sa12 : 64kb (32kw) sa11 : 64kb (32kw) sa10 : 64kb (32kw) sa9 : 64kb (32kw) sa8 : 64kb (32kw) sa7 : 8kb (4kw) sa6 : 8kb (4kw) sa5 : 8kb (4kw) sa4 : 8kb (4kw) sa3 : 8kb (4kw) sa2 : 8kb (4kw) sa70 : 64kb (32kw) sa69 : 64kb (32kw) sa68 : 64kb (32kw) sa67 : 64kb (32kw) sa66 : 64kb (32kw) sa65 : 64kb (32kw) sa64 : 64kb (32kw) sa63 : 64kb (32kw) sa62 : 64kb (32kw) sa61 : 64kb (32kw) sa60 : 64kb (32kw) sa59 : 64kb (32kw) sa58 : 64kb (32kw) sa57 : 64kb (32kw) sa56 : 64kb (32kw) sa55 : 64kb (32kw) sa54 : 64kb (32kw) sa53 : 64kb (32kw) sa52 : 64kb (32kw) sa51 : 64kb (32kw) sa50 : 64kb (32kw) sa49 : 64kb (32kw) sa48 : 64kb (32kw) sa47 : 64kb (32kw) sa46 : 64kb (32kw) sa45 : 64kb (32kw) sa44 : 64kb (32kw) sa43 : 64kb (32kw) sa42 : 64kb (32kw) sa41 : 64kb (32kw) sa40 : 64kb (32kw) sa39 : 64kb (32kw) sa38 : 64kb (32kw) sa37 : 64kb (32kw) sa36 : 64kb (32kw) sa35 : 64kb (32kw) sa34 : 64kb (32kw) sa33 : 64kb (32kw) sa32 : 64kb (32kw) sa1 : 8kb (4kw) sa0 : 8kb (4kw) bank a bank b 070000h 078000h 060000h 068000h 050000h 058000h 040000h 048000h 030000h 038000h 020000h 028000h 010000h 018000h 007000h 008000h 005000h 006000h 003000h 004000h 001000h 002000h 000000h sa102 : 64kb (32kw) sa101 : 64kb (32kw) sa100 : 64kb (32kw) sa99 : 64kb (32kw) sa98 : 64kb (32kw) sa97 : 64kb (32kw) sa96 : 64kb (32kw) sa95 : 64kb (32kw) sa94 : 64kb (32kw) sa93 : 64kb (32kw) sa92 : 64kb (32kw) sa91 : 64kb (32kw) sa90 : 64kb (32kw) sa89 : 64kb (32kw) sa88 : 64kb (32kw) sa87 : 64kb (32kw) sa86 : 64kb (32kw) sa85 : 64kb (32kw) sa84 : 64kb (32kw) sa83 : 64kb (32kw) sa82 : 64kb (32kw) sa81 : 64kb (32kw) sa80 : 64kb (32kw) sa79 : 64kb (32kw) sa78 : 64kb (32kw) sa77 : 64kb (32kw) sa76 : 64kb (32kw) sa75 : 64kb (32kw) sa74 : 64kb (32kw) sa73 : 64kb (32kw) 3fffffh sa141 : 8kb (4kw) sa140 : 8kb (4kw) sa139 : 8kb (4kw) sa138 : 8kb (4kw) sa137 : 8kb (4kw) sa136 : 8kb (4kw) sa135 : 8kb (4kw) sa134 : 8kb (4kw) sa133 : 64kb (32kw) sa132 : 64kb (32kw) sa131 : 64kb (32kw) sa130 : 64kb (32kw) sa129 : 64kb (32kw) sa128 : 64kb (32kw) sa127 : 64kb (32kw) sa126 : 64kb (32kw) sa125 : 64kb (32kw) sa124 : 64kb (32kw) sa123 : 64kb (32kw) sa122 : 64kb (32kw) sa121 : 64kb (32kw) sa120 : 64kb (32kw) sa119 : 64kb (32kw) sa118 : 64kb (32kw) sa117 : 64kb (32kw) sa116 : 64kb (32kw) sa115 : 64kb (32kw) sa114 : 64kb (32kw) sa113 : 64kb (32kw) sa112 : 64kb (32kw) sa111 : 64kb (32kw) sa110 : 64kb (32kw) sa109 : 64kb (32kw) sa108 : 64kb (32kw) sa107 : 64kb (32kw) sa106 : 64kb (32kw) sa105 : 64kb (32kw) sa104 : 64kb (32kw) sa103 : 64kb (32kw) sa72 : 64kb (32kw) sa71 : 64kb (32kw) bank c bank d 3ff000h 3fe000h 3fd000h 3fc000h 3fb000h 3fa000h 3f9000h 0f0000h 0f8000h 0e0000h 0e8000h 0d0000h 0d8000h 0c0000h 0c8000h 0b0000h 0b8000h 0a0000h 0a8000h 090000h 098000h 088000h 080000h 170000h 178000h 160000h 168000h 150000h 158000h 140000h 148000h 130000h 138000h 120000h 128000h 110000h 118000h 100000h 108000h 1f0000h 1f8000h 1e0000h 1e8000h 1d0000h 1d8000h 1c0000h 1c8000h 1b0000h 1b8000h 1a0000h 1a8000h 190000h 198000h 188000h 180000h 270000h 278000h 260000h 268000h 250000h 258000h 240000h 248000h 230000h 238000h 220000h 228000h 210000h 218000h 208000h 2f0000h 2f8000h 2e0000h 2e8000h 2d0000h 2d8000h 2c0000h 2c8000h 2b0000h 2b8000h 2a0000h 2a8000h 290000h 298000h 288000h 280000h 370000h 378000h 360000h 368000h 350000h 358000h 340000h 348000h 330000h 338000h 320000h 328000h 310000h 318000h 300000h 308000h 3f0000h 3f8000h 3e0000h 3e8000h 3d0000h 3d8000h 3c0000h 3c8000h 3b0000h 3b8000h 3a0000h 3a8000h 390000h 398000h 388000h 380000h 200000h 1fffffh word mode word mode
mb84vp23481fk -70 13 ? flexbank tm architecture ? example of virtual banks combination note : when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for example, suppose that erasing is taking place at both bank a and bank b, neither bank a nor bank b is read out (they would output the sequence flag once they were selected.) meanwhile the system would get to read from either bank c or bank d. bank splits bank 1 bank 2 volume combination volume combination 1 8 mbit bank a 56 mbit remainder (bank b, c, d) 2 24 mbit bank b 40 mbit remainder (bank a, c, d) 3 24 mbit bank c 40 mbit remainder (bank a, b, d) 4 8 mbit bank d 56 mbit remainder (bank a, b, c) bank splits bank 1 bank 2 volume combination sector size volume combination sector size 18 mbit bank a 8 8 kbyte/4 kword + 15 64 kbyte/32 kword 56 mbit bank b + bank c + bank d 8 8 kbyte/4 kword + 111 64 kbyte/32 kword 216 mbit bank a + bank d 16 8 kbyte/4 kword + 30 64 kbyte/32 kword 48 mbit bank b + bank c 96 64 kbyte/32 kword 3 24 mbit bank b 48 64 kbyte/32 kword 40 mbit bank a + bank c + bank d 16 8 kbyte/4 kword + 78 64 kbyte/32 kword 432 mbit bank a + bank b 8 8 kbyte/4 kword + 63 64 kbyte/32 kword 32 mbit bank c + bank d 8 8 kbyte/4 kword + 63 64 kbyte/32 kword
mb84vp23481fk -70 14 ? simultaneous operation * : by writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. note: bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks, bank a, bank b, bank c and bank d. bank address (ba) meant to specify each of the banks. case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mb84vp23481fk -70 15 ? sector address tables (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0000000000 000000h to 000fffh sa1 0000000001 001000h to 001fffh sa2 0000000010 002000h to 002fffh sa3 0000000011 003000h to 003fffh sa4 0000000100 004000h to 004fffh sa5 0000000101 005000h to 005fffh sa6 0000000110 006000h to 006fffh sa7 0000000111 007000h to 007fffh sa8 0000001xxx 00 8000h to 00ffffh sa9 0000010xxx 010000h to 017fffh sa10 0000011xxx 01 8000h to 01ffffh sa11 0000100xxx 020000h to 027fffh sa12 0000101xxx 02 8000h to 02ffffh sa13 0000110xxx 030000h to 037fffh sa14 0000111xxx 03 8000h to 03ffffh sa15 0001000xxx 040000h to 047fffh sa16 0001001xxx 04 8000h to 04ffffh sa17 0001010xxx 050000h to 057fffh sa18 0001011xxx 05 8000h to 05ffffh sa19 0001100xxx 060000h to 067fffh sa20 0001101xxx 06 8000h to 06ffffh sa21 0001110xxx 070000h to 077fffh sa22 0001111xxx 07 8000h to 07ffffh
mb84vp23481fk -70 16 (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa23 0010000xxx 080000h to 087fffh sa24 0010001xxx 08 8000h to 08ffffh sa25 0010010xxx 090000h to 097fffh sa26 0010011xxx 09 8000h to 09ffffh sa27 0010100xxx 0a0000h to 0a7fffh sa28 0010101xxx 0a 8000h to 0affffh sa29 0010110xxx 0b0000h to 0b7fffh sa30 0010111xxx 0b 8000h to 0bffffh sa31 0011000xxx 0c0000h to 0c7 fffh sa32 0011001xxx 0c 8000h to 0cffffh sa33 0011010xxx 0d0000h to 0d7 fffh sa34 0011011xxx 0d 8000h to 0dffffh sa35 0011100xxx 0e0000h to 0e7fffh sa36 0011101xxx 0e 8000h to 0effffh sa37 0011110xxx 0f0000h to 0f7fffh sa38 0011111xxx 0f 8000h to 0fffffh sa39 0100000xxx 100000h to 107fffh sa40 0100001xxx 10 8000h to 10ffffh sa41 0100010xxx 110000h to 117fffh sa42 0100011xxx 11 8000h to 11ffffh sa43 0100100xxx 120000h to 127fffh sa44 0100101xxx 12 8000h to 12ffffh sa45 0100110xxx 130000h to 137fffh sa46 0100111xxx 13 8000h to 13ffffh sa47 0101000xxx 140000h to 147fffh sa48 0101001xxx 14 8000h to 14ffffh sa49 0101010xxx 150000h to 157fffh sa50 0101011xxx 15 8000h to 15ffffh sa51 0101100xxx 160000h to 167fffh sa52 0101101xxx 16 8000h to 16ffffh sa53 0101110xxx 170000h to 177fffh sa54 0101111xxx 17 8000h to 17ffffh sa55 0110000xxx 180000h to 187fffh sa56 0110001xxx 18 8000h to 18ffffh sa57 0110010xxx 190000h to 197fffh sa58 0110011xxx 19 8000h to 19ffffh sa59 0110100xxx 1a0000h to 1a7fffh sa60 0110101xxx 1a 8000h to 1affffh sa61 0110110xxx 1b0000h to 1b7fffh sa62 0110111xxx 1b 8000h to 1bffffh sa63 0111000xxx 1c0000h to 1c7 fffh sa64 0111001xxx 1c 8000h to 1cffffh sa65 0111010xxx 1d0000h to 1d7 fffh sa66 0111011xxx 1d 8000h to 1dffffh sa67 0111100xxx 1e0000h to 1e7fffh sa68 0111101xxx 1e 8000h to 1effffh sa69 0111110xxx 1f0000h to 1f7fffh sa70 0111111xxx 1f 8000h to 1fffffh
mb84vp23481fk -70 17 (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa71 1000000xxx 200000h to 207fffh sa72 1000001xxx 20 8000h to 20ffffh sa73 1000010xxx 210000h to 217fffh sa74 1000011xxx 21 8000h to 21ffffh sa75 1000100xxx 220000h to 227fffh sa76 1000101xxx 22 8000h to 22ffffh sa77 1000110xxx 230000h to 237fffh sa78 1000111xxx 23 8000h to 23ffffh sa79 1001000xxx 240000h to 247fffh sa80 1001001xxx 24 8000h to 24ffffh sa81 1001010xxx 250000h to 257fffh sa82 1001011xxx 25 8000h to 25ffffh sa83 1001100xxx 260000h to 267fffh sa84 1001101xxx 26 8000h to 26ffffh sa85 1001110xxx 270000h to 277fffh sa86 1001111xxx 27 8000h to 27ffffh sa87 1010000xxx 280000h to 287fffh sa88 1010001xxx 28 8000h to 28ffffh sa89 1010010xxx 290000h to 297fffh sa90 1010011xxx 29 8000h to 29ffffh sa91 1010100xxx 2a0000h to 2a7fffh sa92 1010101xxx 2a 8000h to 2affffh sa93 1010110xxx 2b0000h to 2b7fffh sa94 1010111xxx 2b 8000h to 2bffffh sa95 1011000xxx 2c0000h to 2c7 fffh sa96 1011001xxx 2c 8000h to 2cffffh sa97 1011010xxx 2d0000h to 2d7 fffh sa98 1011011xxx 2d 8000h to 2dffffh sa99 1011100xxx 2e0000h to 2e7fffh sa1001011101xxx 2e 8000h to 2effffh sa1011011110xxx 2f0000h to 2f7fffh sa1021011111xxx 2f 8000h to 2fffffh sa1031100000xxx 300000h to 307fffh sa1041100001xxx 30 8000h to 30ffffh sa1051100010xxx 310000h to 317fffh sa1061100011xxx 31 8000h to 31ffffh sa1071100100xxx 320000h to 327fffh sa1081100101xxx 32 8000h to 32ffffh sa1091100110xxx 330000h to 337fffh sa1101100111xxx 33 8000h to 33ffffh sa1111101000xxx 340000h to 347fffh sa1121101001xxx 34 8000h to 34ffffh sa1131101010xxx 350000h to 357fffh sa1141101011xxx 35 8000h to 35ffffh sa1151101100xxx 360000h to 367fffh sa1161101101xxx 36 8000h to 36ffffh sa1171101110xxx 370000h to 377fffh sa1181101111xxx 37 8000h to 37ffffh
mb84vp23481fk -70 18 (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa1191110000xxx 380000h to 387fffh sa1201110001xxx 38 8000h to 38ffffh sa1211110010xxx 390000h to 397fffh sa1221110011xxx 39 8000h to 39ffffh sa1231110100xxx 3a0000h to 3a7fffh sa1241110101xxx 3a 8000h to 3affffh sa1251110110xxx 3b0000h to 3b7fffh sa1261110111xxx 3b 8000h to 3bffffh sa1271111000xxx 3c0000h to 3c7 fffh sa1281111001xxx 3c 8000h to 3cffffh sa1291111010xxx 3d0000h to 3d7 fffh sa1301111011xxx 3d 8000h to 3dffffh sa1311111100xxx 3e0000h to 3e7fffh sa1321111101xxx 3e 8000h to 3effffh sa1331111110xxx 3f0000h to 3f7fffh sa1341111111000 3f8000h to 3f8fffh sa1351111111001 3f9000h to 3f9fffh sa1361111111010 3fa000h to 3fa fffh sa1371111111011 3fb000h to 3fb fffh sa1381111111100 3fc000h to 3fcfffh sa1391111111101 3fd000h to 3fdfffh sa1401111111110 3fe000h to 3fe fffh sa1411111111111 3ff000h to 3f ffffh
mb84vp23481fk -70 19 ? sector group addresses sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0000000000 sa0 sga1 0000000001 sa1 sga2 0000000010 sa2 sga3 0000000011 sa3 sga4 0000000100 sa4 sga5 0000000101 sa5 sga6 0000000110 sa6 sga7 0000000111 sa7 sga8 00000 01 xxx sa8 to sa10 10 11 sga9 00001 xxxxx sa11 to sa14 sga10 00010 xxxxx sa15 to sa18 sga11 00011 xxxxx sa19 to sa22 sga12 00100 xxxxx sa23 to sa26 sga13 00101 xxxxx sa27 to sa30 sga14 00110 xxxxx sa31 to sa34 sga15 00111 xxxxx sa35 to sa38 sga16 01000 xxxxx sa39 to sa42 sga17 01001 xxxxx sa43 to sa46 sga18 01010 xxxxx sa47 to sa50 sga19 01011 xxxxx sa51 to sa54 sga20 01100 xxxxx sa55 to sa58 sga21 01101 xxxxx sa59 to sa62 sga22 01110 xxxxx sa63 to sa66 sga23 01111 xxxxx sa67 to sa70 sga24 10000 xxxxx sa71 to sa74 sga25 10001 xxxxx sa75 to sa78 sga26 10010 xxxxx sa79 to sa82 sga27 10011 xxxxx sa83 to sa86 sga28 10100 xxxxx sa87 to sa90 sga29 10101 xxxxx sa91 to sa94 sga30 10110 xxxxx sa95 to sa98 sga31 10111 xxxxx sa99 to sa102 sga32 11000 xxxxx sa103 to sa106 sga33 11001 xxxxx sa107 to sa110 sga34 11010 xxxxx sa111 to sa114 sga35 11011 xxxxx sa115 to sa118 sga36 11100 xxxxx sa119 to sa122 sga37 11101 xxxxx sa123 to sa126 sga38 11110 xxxxx sa127 to sa130 sga39 11111 00 xxx sa131 to sa133 01 10 sga40 1111111000 sa134 sga41 1111111001 sa135 sga42 1111111010 sa136 sga43 1111111011 sa137 sga44 1111111100 sa138 sga45 1111111101 sa139 sga46 1111111110 sa140 sga47 1111111111 sa141
mb84vp23481fk -70 20 ? flash memory autoselect codes *1:sector group can be protected by sector group protection, extended sector group protection and new sector protection (ppb protection). outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:a read cycle at address (ba) 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh type a 21 to a 12 a 6 a 5 a 4 a 3 a 2 a 1 a 0 code (hex) manufactures code ba v il xxv il v il v il v il 04h device code ba v il xxv il v il v il v ih 227eh extended device code *2 ba v il xxv ih v ih v ih v il 2215h ba v il xxv ih v ih v ih v ih 2201h sector group protection *1 sector group addresses v il v ih v ih v ih v il v ih v il 01h *1
mb84vp23481fk -70 21 ? flash memory command definitions (continued) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data read/reset * 1 2 xxxh f0h ra rd read/reset * 1 4555haah2aah55h555hf0hrard autoselect 3 555h aah 2aah 55h (ba) 555h 90h program 4555haah2aah55h555ha0hpapd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h program/erase suspend 1 bab0h program/erase resume 1 ba30h set to fast mode 3555haah2aah55h555h20h fast program * 2 2 xxxh a0h pa pd reset from fast mode * 2 2 ba 90h xxxh f0h* 6 extended sector group protection* 3 4 xxxh 60h sga 60h sga 40h sga sd query * 4 1 (ba) 55h 98h hiddenrom entry3555haah2aah55h555h88h hiddenrom program * 5 4 555h aah 2aah 55h 555h a0h (hra) pa pd hiddenrom exit * 5 4 555h aah 2aah 55h (hrba) 555h 90hxxxh00h hiddenrom protect * 5 6 555h aah 2aah 55h 555h 60h opbp 68h opbp 48h xxxh rd(0) password program * 7 4 555h aah 2aah 55h 555h 38h xx0hpd0 xx1hpd1 xx2hpd2 xx3hpd3 password unlock 7 555h aah 2aah 55h 555h 28h xx0h pd0 xx1h pd1 xx2h pd2 xx3h pd3 password verify 4 555h aah 2aah 55h 555h c8h pwa pwd
mb84vp23481fk -70 22 (continued) legend: ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector ba = bank address rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. sga = sector group address to be protected. set sector group address and (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 1, 1, 1, 0, 1, 0) sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hiddenrom area (000000h to 00007fh) hrba = bank address of the hiddenrom area (a 21 = a 20 = a 19 = v il ) rd(0) = dq 0 data, rd(1) = dq 1 data. ppb lock bit is read on dq 1 and ppb or dpb are read on dq 0 . if set, dq 0 /dq 1 =1. if cleared, dq 0 /dq 1 =0. opbp = (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 1, 1, 0, 1, 0) sla = address of the sector to be locked. set sector address (sa) and either a 6 = 1 for unlocked or a 6 = 0 for locked pwa/pwd = password address/password data pl = (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 0, 1, 0, 1, 0) spml = (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 1, 0, 0, 1, 0) wp = (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 1, 1, 1, 0, 1, 0) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data password mode locking bit program 6 555h aah 2aah 55h 555h 60h pl 68h pl 48h xxh rd(0) persistent protec- tion mode locking bit program 6 555h aah 2aah 55h 555h 60h spml 68h spml 48h xxh rd(0) ppb program 6 555h aah 2aah 55h 555h 60h sa+wp 68h sa+wp 48h xxh rd(0) ppb verify 4 555h aah 2aah 55h 555h 90h sa+x02 rd(0) all ppb erase * 8 6 555h aah 2aah 55h 555h 60h sa+wp 60h sa+wp 40h xxh rd(0) ppb lock bit set 3555haah2aah55h555h78h ppb lock bit verify 4 555h aah 2aah 55h 555h 58h sa rd(1) dpb write 4555haah2aah55h555h48hsax1h dpb erase 4555haah2aah55h555h48hsax0h dpb verify 4 555h aah 2aah 55h 555h 58h sa rd(0)
mb84vp23481fk -70 23 *1: both of these reset commands are equivalent. *2: this command is valid during fast mode. *3: this command is valid while reset = v id . *4: the valid addresses are a 6 to a 0 . *5: this command is valid during hiddenrom mode. *6: the data 00h is also acceptable. *7: data before fourth cycle also need to be programmed repearting from first cycle to third cycle. *8: rd(0) of the sixth cycle shows ppb erase status. when rd(0) is "1", programming must be repeated from the beginning of first cycle to the fourth cycle; both fifth and the sixth validate full completion of erase. notes : address bits a 21 to a 11 = x = h or l for all address commands except for pa, sa, ba, sga, opbp, sla, pwa, pl, spml, wp. bus operations are defined in " n device bus operations". the system should generate the following address patterns: 555h or 2aah to addresses a 10 to a 0 both read/reset commands are functionally equivalent, resetting the device to the read mode. command combinations not described in command definitions table are illegal.
mb84vp23481fk -70 24 2. ac characteristics ? read only operations characteristics parameter symbol condition value* unit jedec standard min max read cycle time t avav t rc 65ns address to output delay t avqv t acc ce f = v il oe = v il 65ns page read cycle time t prc 25ns page address to output delay t pacc ce f = v il oe = v il 25ns chip enable to output delay t elqv t ce oe = v il 65ns output enable to output delay t glqv t oe 25 ns chip enable to output high-z t ehqz t df 25 ns output enable to output high-z t ghqz t df 25 ns output hold time from address, ce f or oe , whichever occurs first t axqx t oh 4ns reset pin low to read mode t ready 20 ns * : test conditions: output load:v cc f =2.7 v to 3.1 v:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to v cc f timing measurement reference level input: 0.5 v cc f output: 0.5 v cc f
mb84vp23481fk -70 25 ? write (erase/program) operations (continued) parameter symbol value unit jedec standard min typ max write cycle time t avav t wc 65 ns address setup time t avwl t as 0ns address setup time to oe low during toggle bit polling t aso 12 ns address hold time t wlax t ah 45 ns address hold time from ce f or oe high during toggle bit polling t aht 0ns data setup time t dvwh t ds 35 ns data hold time t whdx t dh 0ns output enable hold time read t oeh 0ns toggle and data polling 10 ns ce high during toggle bit polling t ceph 20 ns oe high during toggle bit polling t oeph 20 ns read recover time before write t ghwl t ghwl 0ns read recover time before write t ghel t ghel 0ns ce setup time t elwl t cs 0ns we setup time t wlel t ws 0ns ce hold time t wheh t ch 0ns we hold time t ehwh t wh 0ns write pulse width t wlwh t wp 35 ns ce pulse width t eleh t cp 35 ns write pulse width high t whwl t wph 30 ns ce pulse width high t ehel t cph 30 ns word programming operation t whwh1 t whwh1 6s sector erase operation* 1 t whwh2 t whwh2 0.5 s v cc setup time t vcs 50 s rise time to v acc * 2 t vaccr 500 ns
mb84vp23481fk -70 26 (continued) *1 : this does not include the preprogramming time. *2 : this timing is for accelerated program operation. parameter symbol value unit jedec standard min typ max recover time from ry/by t rb 0ns reset pulse width t rp 500 ns reset high level period before read t rh 200 ns program/erase valid to ry/by delay t busy 90 ns delay time from embedded output enable t eoe 65 ns erase time-out time t tow 50 ns erase suspend transition time t spd 20 ns
mb84vp23481fk -70 27 ? read operation timing diagram we oe ce f t df t ce t oe outputs address address stable high-z output valid high-z t oeh t acc t rc t oh
mb84vp23481fk -70 28 ? page read operation timing diagram same page addresses we oe cef a 21 to a 3 a 2 to a 0 output t rc t ce t acc aa ab ac ad ae af ag ah t prc t prc t oe t oeh t pacc t pacc t pacc high-z t oh t oh t oh t oh t oh t oh t oh t oh da db dc dh t df t prc t prc t prc t prc t prc t pacc t pacc t pacc dd de df t pacc dg
mb84vp23481fk -70 29 ? hardware reset/read operation timing diagram address cef reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh
mb84vp23481fk -70 30 ?alternate we controlled program operation timing diagram notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. t ch t wp t whwh1 t wc t ah ce f oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df
mb84vp23481fk -70 31 ?alternate ce controlled program operation timing diagram notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce f 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd
mb84vp23481fk -70 32 ? chip/sector erase operation timing diagram * : sa is the sector address for sector erase. v cc f ce f oe address data we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 30h for sector erase 30h
mb84vp23481fk -70 33 ?data polling during embedded algorithm operation timing diagram t oeh t oe t whwh1 or 2 cef oe t eoe we data t df t ch t ce high-z high-z dq 7 = valid data dq 6 to dq 0 valid data dq 7 * dq 7 dq 6 to dq 0 data dq 6 to dq 0 = output flag * : dq 7 = valid data (the device has completed the embedded operation).
mb84vp23481fk -70 34 ? ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling (the device has completed the embedded operation). t dh t oe t ce cef we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph
mb84vp23481fk -70 35 ? bank-to-bank read/write timing diagram cef dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2
mb84vp23481fk -70 36 ?dq 2 vs. dq 6 ?ry/by timing diagram during program/erase operation timing diagram enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 we toggle dq 2 and dq 6 with oe note : dq 2 is read from the erase-suspended sector. cef ry/by we rising edge of the last we signal t busy entire programming or erase operations
mb84vp23481fk -70 37 ? reset , ry/by timing diagram t rp t rb t ready ry/by we reset
mb84vp23481fk -70 38 ? temporary sector group unprotection timing diagram unprotection period t vlht t vlht t vcs t vlht t vidr program command sequence v cc f v id v ih we ry/by cef reset
mb84vp23481fk -70 39 ? extended sector group protection timing diagram sgax : sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = 250 m s (min) v cc f we oe cef reset t wc t wc t vlht t vidr t vcs time-out sgax sgax sgay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 2 , a 0 a 5 , a 4 , a 3 , a 1
mb84vp23481fk -70 40 ? accelerated program timing diagram v ih acc v cc f cef we t vlht program command sequence t vlht t vcs t vaccr v acc t vlht acceleration period
mb84vp23481fk -70 41 3. erase and programming performance note typical erase conditions t a = + 25c, v cc f = 2.9 v typical program conditions t a = + 25c, v cc f = 2.9 v, data = checker parameter limits unit comments min typ max sector erase time 0.5 2.0 s excludes programming time prior to erasure word programming time 6 100 s excludes system-level overhead chip programming time 25.2 95 s excludes system-level overhead erase/program cycle 100,000 cycle
mb84vp23481fk -70 42 n n n n 32 m fcram characteristics for mcp 1. power down (32m page mode fcram) ? power down (32m page mode fcram) the power down is to enter low power idle state when ce2r stays low. the 32m page mode fcram has four power down mode, sleep, 4m partial, 8m partial, and 16m partial. these can be programmed by series of read/write operation. each mode has following features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2r is brought to low for power down. it is not required to program to sleep mode after power-up. ? power down program sequence (32m page mode fcram) the program requires total 6 read/write operation with unique address and data. between each read/write operation requires that device be in standby mode. following table shows the detail sequence. the first cycle is to read from most significant address (msb). the second and third cycle are to write back the data (rda) read by first cycle. if the third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. the forth and fifth cycle is to write the data key for program. the data of forth cycle must be all 0s and data of fifth cycle is a data key for mode selection. if the forth cycle is written into different address, the program is also cancelled. the last cycle is to read from specific address key for mode selection. the both data key written by fifth cycle and address key must be the same mode for proper programming. once this program sequence is performed from a partial mode to other partial mode, the write data may be lost. so, it should perform this program prior to regular read/write operation if partial mode is used. mode data retention retention address sleep (default) no n/a 4m partial 4m bit 00000h to 3ffffh 8m partial 8m bit 00000h to 7ffffh 16m partial 16m bit 00000h to fffffh cycle # operation address data 1st read 1fffffh (msb) read data (rda) 2nd write 1fffffh rda 3rd write 1fffffh rda 4th write 1fffffh 0000h 5th write 1fffffh data key 6th read address key read data (rdb)
mb84vp23481fk -70 43 ? address key (32m page mode fcram) the address key has following format. ? data key (32m page mode fcram) the data key has following format. the upper byte of data code may be ignored and it is just for recommendation to write 0s to upper byte for future compatibility. mode address a 20 a 19 a 18 to a 0 binary sleep (default) 1 1 1 1fffffh 4m partial 0 1 1 0fffffh 8m partial 1 0 1 17ffffh 16m partial 0 0 1 07ffffh mode data dq 15 to dq 8 dq 7 to dq 2 dq 1 dq 0 sleep (default) 0 0 1 1 4m partial 0 0 1 0 8m partial 0 0 0 1 16m partial 0 0 0 0
mb84vp23481fk -70 44 2. ac characteristics ? read operation (32m page mode fcram) *1 : maximum value is applicable if ce 1r is kept at low without change of address input of a 20 to a 3 . if needed by system operation, please contact local fujitsu representative for the relaxation of 1 m s limitation. *2 : address should not be changed within minimum t rc . *3 : the output load 30 pf. *4 : the output load 5 pf without any other load. *5 : applicable to a 20 to a 3 when ce 1r is kept at low. *6 : applicable only to a 2 , a 1 and a 0 when ce 1r is kept at low for the page address access. *7 : in case page read cycle is continued with keeping ce 1r stays low, ce 1r must be brought to high within 4 m s. in other words, page read cycle must be closed within 4 m s. *8 : applicable when at least two of address inputs among applicable are switched from previous state. *9 : t rc (min) and t prc (min) must be satisfied. parameter symbol value unit remarks min max read cycle time t rc 70 1000 ns *1, *2 ce 1r access time t ce 70ns*3 oe access time t oe 40ns*3 address access time t aa 70ns*3, *5 lb / ub access time t ba 30ns*3 page address access time t paa 18ns*3, *6 page read cycle time t prc 25 1000 ns *1, *6, *7 output data hold time t oh 5ns*3 ce 1r low to output low-z t clz 3ns*4 oe low to output low-z t olz 0ns*4 lb / ub low to output low-z t blz 0ns*4 ce 1r high to output high-z t chz 20ns*4 oe high to output high-z t ohz 20ns*4 lb / ub high to output high-z t bhz 20ns*4 address setup time to ce 1r low t asc C5 ns address setup time to oe low t aso 10 ns address invalid time t ax 10ns*5, *8 page address invalid time t axp 10ns*6, *8 address hold time from ce 1r high t chah C5 ns *9 address hold time from oe high t ohah C5 ns ce 1r high pulse width t cp 15 ns
mb84vp23481fk -70 45 ? write operation (32m page mode fcram) *1 : maximum value is applicable if ce 1r is kept at low without any address change. if the relaxation is needed by system operation, please contact local fujitsu representative for the relaxation of 1 m s limitation. *2 : minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wrc , t wr or t br ). *3 : write pulse is defined from high to low transition of ce 1r, we , or lb / ub , whichever occurs last. *4 : write recovery is defined from low to high transition of ce 1r, we , or lb / ub , whichever occurs first. *5 : applicable to any address change when ce 1r stays low. *6 : if oe is low after minimum t ohcl , read cycle is initiated. in other word, oe must be brought to high within 5ns after ce 1r is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. *7 : if oe is low after new address input, read cycle is initiated. in other word, oe must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met. parameter symbol value unit notes min max write cycle time t wc 70 1000 ns *1, *2 address setup time t as 0ns*2 ce 1r write pulse width t cw 45 ns *3 we write pulse width t wp 45 ns *3 lb / ub write pulse width t bw 45 ns *3 ce 1r write recovery time t wrc 15 ns *4 we write recovery time t wr 15 1000 ns *4 lb / ub write recovery time t br 15 1000 ns *4 data setup time t ds 20 ns data hold time t dh 0ns address invalid time after write t axw 10ns*5 oe high to ce 1r low setup time for write t ohcl C5 ns *6 oe high to address setup time for write t oes 0ns*7 lb and ub write pulse overlap t bwo 20 ns ce 1r high pulse width t cp 15 ns
mb84vp23481fk -70 46 ? power down parameters (32m page mode fcram) *1 : applicable also to power-up. *2 : applicable when 4m, 8m, and 16m partial mode is programmed. ? other timing parameters (32m page mode fcram) *1 : some data might be written into any address location if t chwx (min) is not satisfied. *2 : the input transition time (t t ) at ac testing is 5 ns as shown in below. if actual t t is longer than 5 ns, it may violate ac specification of some timing parameters. ? ac test conditions (32m page mode fcram) parameter symbol value unit remarks min max ce2r low setup time for power down entry t csp 10 ns ce2r low hold time after power down entry t c2lp 70 ns ce 1r high hold time following ce2r high after power down exit [sleep mode only] t chh 300 m s*1 ce 1r high hold time following ce2r high after power down exit [not in sleep mode] t chhp 1 m s*2 ce 1r high setup time following ce2r high after power down exit t chs 0ns parameter symbol value unit remarks min max ce 1r high to oe invalid time for standby entry t chox 10 ns ce 1r high to we invalid time for standby entry t chwx 10 ns *1 ce 1r high hold time following ce2r high after power-up t chh 300 m s input transition time t t 125ns*2 description symbol test setup value unit remarks input high level v ih v cc rv input low level v il v ss v input timing measurement level v ref v cc r 0.5 v input transition time t t between v il and v ih 5ns
mb84vp23481fk -70 47 ? read timing #1 (basic timing) (32m page fcram) note : ce2r and we must be high for entire read cycle. t ce valid data output address ce 1r dq (output) oe t chz t rc t clz t chah t cp address valid t asc t asc t ohz t oh t bhz lb / ub t oe t ba t blz t olz
mb84vp23481fk -70 48 ? read timing #2 (oe & address access) (32m page fcram) note : ce2r and we must be high for entire read cycle. t aa valid data output address ce 1r dq (output) lb / ub t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe t ax low t aa t ohah t aso
mb84vp23481fk -70 49 ? read timing #3 (lb / ub byte access) (32m p a g e fcram ) note : ce2r and we must be high for entire read cycle. t aa valid data output address ce 1r, oe dq 7 to dq 0 (output) ub t bhz t ba t rc t blz address valid valid data output t bhz t oh lb t ax low t ba t ax dq 15 to dq 8 (output) t blz t ba t blz t oh t bhz t oh valid data output
mb84vp23481fk -70 50 ? read timing #4 (page address access after ce 1r cont r o l access) (32m p a g e fcram ) note : ce2r, and we must be high for entire read cycle. valid data output (normal access) address (a 2 to a 0 ) ce 1r dq (output) oe t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t asc t paa address (a 20 to a 3 ) address valid lb / ub t paa t oh t prc t paa t prc t oh address valid address valid t rc
mb84vp23481fk -70 51 ? read timing #5 (random and p a g e a d dress access) (32m p a g e fcram ) note : ce2r, and we must be high for entire read cycle. either or both lb and ub must be low when both ce 1r and oe are low. valid data output (normal access) address (a 2 to a 0 ) ce 1r dq (output) oe t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa address (a 20 to a 3 ) address valid lb / ub t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso
mb84vp23481fk -70 52 ? write timing #1 (basic timing) (32m page fcram) note : ce2r must be high for write cycle. t as valid data input address ce 1r dq (input) we t dh t ds t wc t wrc t wp t cw lb , ub t as t bw address valid t as t as t br oe t ohcl t as t as t wr
mb84vp23481fk -70 53 ? write timing #2 (we control) (32m page fcram) note : ce2r must be high for write cycle. t as address we ce 1r t wc t wr t wp lb , ub address valid t as t wr t wp valid data input dq (input) t dh t ds oe t oes t ohz t wc valid data input t dh t ds low address valid t ohah
mb84vp23481fk -70 54 ? write timing #3-1 (we / lb / ub byte write control) (32m page fcram) note : ce2r must be high for write cycle. t as address we ce 1r t wc t br t wp lb address valid t as t br t wp valid data input dq 7 to dq 0 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq 15 to dq 8 (input)
mb84vp23481fk -70 55 ? write timing #3-2 (we / lb / ub byte write control) (32m page fcram) note : ce2r must be high for write cycle. t as address we ce 1r t wc t wr t bw lb address valid t as t wr t bw valid data input dq 7 to dq 0 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq 15 to dq 8 (input)
mb84vp23481fk -70 56 ? write timing #3-3 (we / lb / ub byte write cont r o l) (32m p a g e fcram) note : ce2r must be high for write cycle. t as address we ce 1r t wc t br t bw lb address valid t as t br t bw valid data input dq 7 to dq 0 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq 15 to dq 8 (input)
mb84vp23481fk -70 57 ? write timing #3-4 (we / lb / ub byte write cont r o l) (32m p a g e fcram) note : ce2r must be high for write cycle. t as address we ce 1r t wc t br t bw lb address valid t as t br t bw dq 7 to dq 0 (input) t dh t ds ub t wc t dh t ds low address valid dq 15 to dq 8 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo
mb84vp23481fk -70 58 ? read / write timing #1-1 (ce 1r cont r o l) (32m p a g e fcram) note : write address is valid from either ce 1r or we of last falling edge. read data output address ce 1r dq we t wc t cw oe t ohcl ub , lb t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh
mb84vp23481fk -70 59 ? read / write timing #1-2 (ce 1r / we / oe control) (32m page fcram) note : oe can be low fixed in write operation under ce 1r control rd -wr -rd operation. read data output address ce 1r dq we t wc t wp oe t ohcl ub , lb t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
mb84vp23481fk -70 60 ? read / write timing #2 (oe , we control) (32m page fcram) note : ce 1r can be tied to low for we and oe controlled operation. when ce 1r is tied to low, output is exclusively controlled by oe . read data output address ce 1r dq we t wc t wp oe ub , lb t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah
mb84vp23481fk -70 61 ? read / write timing #3 (oe , we , lb , ub control) (32m page fcram) note : ce 1r can be tied to low for we and oe controlled operation. when ce 1r is tied to low, output is exclusively controlled by oe . read data output address ce 1r dq we t wc t bw oe ub , lb t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes
mb84vp23481fk -70 62 ? power-up timing (32m page fcram) note : the t chh specifies after v cc r reaches specified minimum level and applicable both ce 1r and ce2r. ? p o wer d o wn ent r y and exit timin g note : this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power-down program was not performed prior to this reset. ? standby entry timing after read or write (32m page fcram) note : both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce 1r low to high transition. ce 1r v cc r v cc r min 0v ce2r t chh t csp ce 1r power down entry ce2r t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z t chox ce 1r oe we active (read) standby active (write) standby t chwx
mb84vp23481fk -70 63 ? power down program timing (32m page fcram) *1 : the all address inputs must be high from cycle #1 to #5. the address key must confirm the format specified in n 32 m fcram characteristics for mcp 1. power down program timing (32 m page fcram) . if not, the operation and data are not guaranteed. *2 : the data key must confirm the format specified in n 32 m fcram characteristics for mcp 1. power down program timing (32 m page fcram) . if not, the operation and data are not guaranteed. *3 : after t cp following cycle #6, the power down program is completed and returned to the normal operation. address ce 1r dq* 3 we t rc oe lb , ub rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp t cp * 4 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda 00 key* 3 rdb
mb84vp23481fk -70 64 n n n n pin capacitance note: test conditions t a = + 25c, f = 1.0 mhz n n n n handling of package please handle this package carefully since the sides of package create acute angles. n n n n caution the high voltage (v id ) cannot apply to address pins and control pins except reset . exception is when autoselect and sector group protect function are used, then the high voltage (v id ) can be applied to reset . without the high voltage (v id ) , sector group protection can be achieved by using extended sector group protection command. parameter symbol condition value unit min typ max input capacitance c in v in = 0 ? 11.0 14.0 pf output capacitance c out v out = 0 ? 12.0 16.0 pf control pin capacitance c in2 v in = 0 ? 14.0 16.0 pf wp /acc pin capacitance c in3 v in = 0 ? 21.5 26.0 pf
mb84vp23481fk -70 65 n n n n ordering information mb84vp23481 fk -70 pbs device number/description 64mega-bit (2m 16-bit + 2m 16-bit) dual operation page flash memory 3.0v-only read, program, and erase 32mega-bit(2m 16-bit) mobile fcram package type pbs = 65-ball fbga speed option device revision
mb84vp23481fk -70 66 n n n n package dimension 65-ball plastic fbga (bga-65p-m01) dimensions in mm (inches) note : the values in parentheses are reference values. c 2001 fujitsu limited b65001s-c-1-2 9.00 0.10(.354 .004) 9.00 0.10 (.354 .004) index-mark area 0.10(.004) 0.39 0.10 (.015 .004) (stand off) .047 C .004 +.006 C 0.10 +0.15 1.19 (seated height) a b c d e f g h j k 1 2 3 4 5 6 7 8 9 10 65- ? .018 C .002 +.004 C 0.05 +0.10 65- ? 0.45 m 0.08(.003) 0.20(.008) sa s s 0.80(.031) 0.40(.016) ref ref 0.80(.031) ref ref 0.40(.016) a b sa s 0.10(.004) b s 0.20(.008) b index ball
mb84vp23481fk -70 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0311 ? fujitsu limited printed in japan

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