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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. ADV7330 multiformat 11-bit t riple dac video encoder purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. simplified functional block diagram clkin h sync_i/p vsync_i/p b lank_i/p y7?y0 c7?c0 timing generator pll o v e r s a m p l i n g i 2 c interface d e m u x standard definition control block color control brightness dnr gamma programmable filters sd test pattern high definition control block hd test pattern color control adaptive filter ctrl sharpness filter programmable rgb matrix 11-bit dac 11-bit dac 11-bit dac ADV7330 features high definition input formats 8-bit or 16-bit (4:2:2) parallel ycrcb compliant with: smpte 293m (525p) bta t-1004 edtv2 525p itu-r bt.1358 (525p/625p) itu-r bt.1362 (525p/625p) smpte 274m (1080i) at 30 hz and 25 hz smpte 296m (720p) other high definition formats using async timing mode high definition output formats yprpb progressive scan (eia-770.1, eia-770.2) yprpb hdtv (eia 770.3) rgb, rgbhv cgms-a (720p/1080i) macrovision rev 1.1 (525p/625p) cgms-a (525p) standard definition input formats ccir-656 4:2:2 8-bit or 16-bit parallel input standard definition output formats composite ntsc m/n composite pal m/n/b/d/g/h/i, pal-60 smpte 170m ntsc compatible composite video itu-r bt.470 pal compatible composite video s-video (y/c) euroscart rgb component yprpb (betacam, mii, smpte/ebu n10) macrovision rev 7.1.l1 cgms/wss closed captioning general features programmable dac gain control sync outputs in all modes on-board voltage reference three 11-bit precision video dacs 2-wire serial i 2 c interface, open drain configuration dual i/o supply 2.5 v/3.3 v operation analog and digital supply 2.5 v on-board pll 64-lead lqfp package lead (pb) free product applications sd/ps dvd recorders/players sd/prog scan/hdtv display devices sd/hdtv set top boxes general description the adv 7330 is a high speed, digital-to-analog encoder on a single monolithic chip. it includes three high speed video d/a converters with ttl compatible inputs. the ADV7330 has separate 8-bit or 16-bit input ports that accept data in high definition or standard definition video format. for all standards, external horizontal, vertical, and blanking signals or eav/sav timing codes control the inser- tion of appropriate synchronization signals into the digital data stream and therefore the output signal.
rev. b ? ADV7330 detailed features high definition programmable features (720p/1080i) 2 oversampling (148.5 mhz) internal test pattern generator (color hatch, black bar, flat field/frame) fully programmable ycrcb to rgb matrix gamma correction programmable adaptive filter control programmable sharpness filter control cgms-a (720p/1080i) programmable features (525p/625p) 8 oversampling internal test pattern generator (color hatch, black bar, flat frame) individual y and prpb output delay gamma correction programmable adaptive filter control fully programmable ycrcb to rgb/matrix undershoot limiter macrovision rev 1.1 (525p/625p) cgms-a (525p) standard definition programmable features 16 oversampling internal test pattern generator (colorbars, black bar) controlled edge rates for sync, active video individual y and prpb output delay gamma correction digital noise reduction (dnr) multiple chroma and luma filters luma-ssaf filter with programmable gain/attenuation prpb ssaf separate pedestal control on component and composite/s-video outputs vcr ff/rw sync mode macrovision rev 7.1.l1 cgms/wss closed captioning standards directly supported frame clk resolution rate (hz) input (mhz) standard 720 480 29.97 27 itu-r bt.656 720 576 25 27 itu-r bt.656 720 483 59.94 27 smpte 293m 720 480 59.94 27 bta t-1004 720 576 50 27 itu-r bt.1362 1280 720 60 74.25 smpte 296m 1920 1080 30 74.25 smpte 274m 1920 1080 25 74.25 smpte 274m * other standards are supported in async timing mode. * smpte 274m-1998: system no. 6 detailed functional block diagram sd/ps/hd pixel input clkin hsync vsync blank y cb cr test pa ttern sharpness and adaptive filter cont luma and chroma filters f sc modulation rol y color cr color cb color 4:2:2 to 4:4:4 deinter- leave deinter- leave y cb cr test pattern dnr gamma color control sync insertion clock control and pll uv ssaf v u ps 8 hdtv 2 rgb matrix sd 16 cgms wss 2 over- sampling dac dac dac timing generator
rev. b ADV7330 ? table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 simplified functional block diagram . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 detailed functional block diagram . . . . . . . 2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 dynamic specifications . . . . . . . . . . . . . . . . . . . . . 5 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . 11 thermal characteristics . . . . . . . . . . . . . . . . . . 11 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pin function descriptions . . . . . . . . . . . . . . . . . 12 mpu port description . . . . . . . . . . . . . . . . . . . . . . . 13 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 subaddress register (sr7?r0) . . . . . . . . . . . . . . . . . . . 14 input configuration . . . . . . . . . . . . . . . . . . . . . . . 27 standard definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 progressive scan or hdtv mode . . . . . . . . . . . . . . . . . . 27 progressive scan at 27 mhz (dual edge) or 54 mhz . . . 27 output configuration . . . . . . . . . . . . . . . . . . . . . 28 timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 hd async timing mode . . . . . . . . . . . . . . . . . . . . . . . . . 29 hd timing reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 sd real-time control, subcarrier reset, timing reset . 31 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 sd vcr ff/rw sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 vertical blanking interval . . . . . . . . . . . . . . . . . . . . . . . . . 33 sd subcarrier frequency registers . . . . . . . . . . . . . . . . . 33 square pixel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 filter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 hd sinc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 sd internal filter response . . . . . . . . . . . . . . . . . . . . . . . 35 typical performance characteristics . . . . . . . . . . . . . . . . . . 36 color controls and rgb matrix . . . . . . . . . . . 40 hd y level, cr level, cb level . . . . . . . . . . . . . . . . . . . 40 hd rgb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 sd luma and color control . . . . . . . . . . . . . . . . . . . . . . 40 sd hue adjust value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 sd brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 sd brightness detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 programmable dac gain control . . . . . . . . . . 42 gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 hd sharpness filter control and adaptive filter control . . . . . . . . . . . . . . . . . . . 44 hd sharpness filter mode . . . . . . . . . . . . . . . . . . . . . . . 44 hd adaptive filter mode . . . . . . . . . . . . . . . . . . . . . . . . 44 hd sharpness filter and adaptive filter application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 adaptive filter control application . . . . . . 46 sd digital noise reduction . . . . . . . . . . . . . . . . . . . . . . . 47 coring gain border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 coring gain data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 dnr threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 border area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 block size control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 dnr input select control . . . . . . . . . . . . . . . . . . . . . . . . 48 dnr mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 block offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sd active video edge . . . . . . . . . . . . . . . . . . . . . . . . 48 sav/eav step edge control . . . . . . . . . . . . . . . . . 48 board design and layout considerations . 50 dac termination and layout considerations . . . . . . . . 50 video output buffer and optional output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 pc board layout considerations . . . . . . . . . . 51 supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . 52 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . 52 appendix 1?opy generation management system . . . . . . . . . . . . . . . . . . . . . . 53 hd cgms data registers 2? . . . . . . . . . . . . . . . . . . . . 53 sd cgms data registers 2? . . . . . . . . . . . . . . . . . . . . . 53 hd cgms data registers . . . . . . . . . . . . . . . . . . . . . . . 53 function of cgms bits . . . . . . . . . . . . . . . . . . . . . . . . . . 53 appendix 2?d wide screen signaling . . . . . . 55 appendix 3?d closed captioning . . . . . . . . . . 56 appendix 4?est patterns . . . . . . . . . . . . . . . . . . 57 appendix 5?d timing modes . . . . . . . . . . . . . . . 60 mode 0 (ccir-656)?lave option . . . . . . . . . . . . . . . . 60 mode 0 (ccir-656)?aster option . . . . . . . . . . . . . . . 61 mode 1?lave option . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 mode 1?aster option . . . . . . . . . . . . . . . . . . . . . . . . . 63 mode 2?lave option . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mode 2?aster option . . . . . . . . . . . . . . . . . . . . . . . . . 65 mode 3?aster/slave option . . . . . . . . . . . . . . . . . . . . . 66 appendix 6?d timing . . . . . . . . . . . . . . . . . . . . . . 67 appendix 7?ideo output levels . . . . . . . . . . . 68 hd yprpb output levels . . . . . . . . . . . . . . . . . . . . . . . . 68 rgb output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 yprpb output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 appendix 8?ideo standards . . . . . . . . . . . . . . . 74 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 76
rev. b ? ADV7330?pecifications parameter min typ max unit conditions static performance 1 (with no oversampling ratio) resolution 11 bits integral nonlinearity 1.5 lsb differential nonlinearity 2 , +ve 0.5 lsb differential nonlinearity 2 , ?e 1.0 lsb digital outputs output low voltage, v ol 0.4 [0.4] 3 vi sink = 3.2 ma output high voltage, v oh 2.4 [2.0] 3 vi source = 400 a three-state leakage current 1.0 av in = 0.4 v, 2.4 v three-state output capacitance 2 pf digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 v input leakage current 3 av in = 2.4 v input capacitance, c in 2pf analog outputs full-scale output current 4.1 4.33 4.6 ma output current range 4.1 4.33 4.6 ma dac to dac matching 1.0 % output compliance range, v oc 0 1.0 1.4 v output capacitance, c out 7pf voltage reference internal reference range, v ref 1.15 1.235 1.3 v external reference range, v ref 1.15 1.235 1.3 v v ref current 4 10 a power requirements normal power mode i dd 5 170 190 6 ma sd (16 ) 110 ma ps (8 ) 95 ma hdtv (2 ) i dd_io 1.0 ma i aa 7, 8 24 28 ma sleep mode i dd 200 a i aa 10 a i dd_io 250 a power supply rejection ratio 0.01 %/% notes 1 oversampling disabled. static dac performance will be improved with increased oversampling ratios. 2 dnl measures the deviation of the actual dac output voltage step from the ideal. for +ve dnl, the actual step value lies above the ideal step value; for ?e dnl, the actual step value lies below the ideal step value. 3 value in brackets for v dd_io = 2.375 v to 2.75 v. 4 external current required to overdrive internal v ref . 5 i dd , the circuit current, is the continuous current required to drive the digital core. 6 guaranteed maximum by characterization. 7 i aa is the total current required to supply all dacs including the v ref circuitry and the pll circuitry. 8 all dacs on. specifications subject to change without notice. (v aa = 2.375 v to 2.625 v, v dd = 2.375 v to 2.625 v; v dd_io = 2.375 v to 3.6 v, v ref = 1.235 v, r set = 3040 , r load = 300 . all specifications t min to t max (0 c to 70 c), unless otherwise noted.)
rev. b ADV7330 ? dynamic specifications parameter min typ max unit conditions progressive scan mode luma bandwidth 12.5 mhz chroma bandwidth 5.8 mhz snr 65.6 db luma ramp unweighted 72 db flat field full bandwidth hdtv mode luma bandwidth 30 mhz chroma bandwidth 13.75 mhz standard definition mode hue accuracy 0.4 degrees color saturation accuracy 0.4 % chroma nonlinear gain 1.2 %r eferenced to 40 ire chroma nonlinear phase ?.2 degrees chroma/luma intermodulation 0 % chroma/luma gain inequality 97.0 % chroma/luma delay inequality ?.1 ns luminance nonlinearity 0.5 % chroma am noise 84 db chroma pm noise 75.2 db differential gain 0.20 % ntsc differential phase 0.15 degrees ntsc snr 59.1 db luma ramp 77.7 db flat field full bandwidth specifications subject to change without notice. (v aa = 2.375 v to 2.625 v, v dd = 2.375 v to 2.625 v; v dd_io = 2.375 v to 3.6 v, v ref = 1.235 v, r set = 3040 , r load = 300 . all specifications t min to t max (0 c to 70 c), unless otherwise noted.)
rev. b ? ADV7330 timing specifications (v aa = 2.375 v to 2.625 v, v dd = 2.375 v to 2.625 v; v dd_io = 2.375 v to 3.6 v, v ref = 1.235 v, r set = 3040 , r load = 300 . all specifications t min to t max (0 c to 70 c), unless otherwise noted.) parameter min typ max unit conditions mpu port 1 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period, the fi rst clock is generated setup time (start condition), t 4 0.6 sr elevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s reset low time 100 ns analog outputs analog output delay 2 7ns output skew 1 ns clock control and pixel port 3 f clk 27 mhz progressive scan mode f clk 81 mhz hdtv mode/async mode clock high time, t 9 40 % of one clk cycle clock low time, t 10 40 % of one clk cycle data setup time, t 11 1 2.0 ns data hold time, t 12 1 2.0 ns sd output access time, t 13 15 ns sd output hold time, t 14 5.0 ns hd output access time, t 13 14 ns hd output hold time, t 14 5.0 ns pipeline delay 4 63 clk cycles sd (2 , 16 ) 76 clk cycles sd component mode (16 ) 35 clk cycles ps (1 ) 41 clk cycles ps (8 ) 36 clk cycles hd (2 , 1 ) notes 1 guaranteed by characterization. 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of the dac output full-scale transition. 3 data: c [9:0]; y [9:0], s[9:0]. control: hsync_i/p , vsync_i/p , blank_i/p , hsync_o/p , vsync_o/p , blank_o/p . 4 sd, ps = 27 mhz, hd = 74.25 mhz. specifications subject to change without notice.
rev. b ADV7330 ? t 9 t 11 clkin t 10 t 12 cb0 cr0 cb2 cr2 cb4 cr4 hsync_i/p vsync_i/p blank_i/p control inputs y0 y1 y2 y3 y4 y5 y7?y0 c7?c0 t 14 hsync_o/p vsync_o/p blank_o/p control outputs t 13 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time figure 1. hd/ps 4:2:2 input mode (hd: input mode 010) (ps: input mode 001) clkin y7?y0 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time t 11 t 12 t 13 t 14 t 11 t 12 t 9 t 10 cb0 y0 y1 crxxx yxxx cr0 hsync_i/p vsync_i/p blank_i/p control inputs hsync_o/p vsync_o/p blank_o/p control outputs figure 2. ps 4:2:2 1 8-bit interleaved at 27 mhz hsync/vsync input mode (input mode 100)
rev. b ? ADV7330 clkin y7?y0 * y0, cb, sequence as per subaddress 01h bit 1 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time t 11 t 12 t 13 t 14 t 11 t 12 t 9 t 10 3ff 00 xy cb0 * y0 cr0 y1 00 hsync_o/p vsync_o/p blank_o/p control outputs figure 3. ps 4:2:2 1 8-bit interleaved at 27 mhz eav/sav input mode (input mode 100) clkin y7?y0 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time t 9 t 10 t 11 t 12 t 13 t 14 cb0 y0 cr2 y1 cbxxx cbxxx hsync_i/p vsync_i/p blank_i/p control inputs hsync_o/p vsync_o/p blank_o/p control outputs figure 4. ps 4:2:2 1 8-bit interleaved at 54 mhz hsync/vsync i/p mode (input mode 011) clkin y7?y0 control outputs t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time 3ff 00 00 xy cb0 y0 cr0 y1 t 11 t 12 t 13 t 14 t 9 t 10 figure 5. ps 4:2:2 1 8-bit interleaved at 54 mhz eav/sav input mode (input mode 011)
rev. b ADV7330 ? y7?y0 clkin t 9 t 11 t 14 t 13 t 10 t 12 cb y cr ycby in master/slave mode in slave mode hsync_i/p vsync_i/p blank_i/p control inputs hsync_o/p vsync_o/p blank_o/p control outputs figure 6. 8-bit sd pixel input mode (input mode 000) y7?y0 clkin t 9 t 11 t 14 t 13 t 10 t 12 c7?c0 y0 cb0 y1 cr0 y2 cb2 y3 cr2 in master/slave mode in slave mode hsync_i/p vsync_i/p blank_i/p control inputs hsync_o/p vsync_o/p blank_o/p control outputs figure 7. 16-bit sd pixel input mode (input mode 000) h sync_i/p vsync_i/p b lank_i/p y7?y0 y0 y1 y2 y3 c7?c0 cb0 cr0 cr1 cb1 b a a = 16 clk cycles for 525p a = 12 clk cycles for 626p a = 44 clk cycles for 1080i @ 30hz, 25hz a = 70 clk cycles for 720p as recommended by standard b (min) = 122 clk cycles for 525p b (min) = 132 clk cycles for 625p b (min) = 236 clk cycles for 1080i @ 30hz, 25hz b (min) = 300 clk cycles for 720p figure 8. hd 4:2:2 input timing diagram
rev. b ?0 ADV7330 h sync_i/p b lank_i/p vsync_i/p y7?y0 cb y cr y b a a = 32 clk cycles for 525p a = 24 clk cycles for 626p as recommended by standard b (min) = 244 clk cycles for 525p b (min) = 264 clk cycles for 625p figure 9. ps 4:2:2, 1 8-bit interleaved input timing diagram y7?y0 cb y cr y pal = 264 clk cycles ntsc = 244 clk cycles * selected by address 44h bit 7 pal = 24 clk cycles ntsc = 32 clk cycles b lank_i/p h sync_i/p vsync_i/p figure 10. sd timing input for timing mode 1 t 3 t 1 t 6 t 2 t 7 t 5 sda sclk t 3 t 4 t 8 figure 11. mpu port timing diagram
rev. b ADV7330 ?1 ordering guide model temperature range package description package option ADV7330kst 0 c to 70 cl ow profile quad flat package st-64-2 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7330 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 v aa to agnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +3.0 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +3.0 v v dd_io to gnd_io . . . . . . . . . . . . . . . . . . . . ?.3 v to +4.6 v digital input voltage to dgnd . . . . ?.3 v to v dd_io + 0.3 v v aa to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v dgnd to gnd_io . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v agnd to gnd_io . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v ambient operating temperature (t a ) . . . . . . . . 0 c to 70 c storage temperature (t s ) . . . . . . . . . . . . . . 65 c to +150 c infrared reflow soldering (20 secs) . . . . . . . . . . . . . . . . 260 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. thermal characteristics jc = 11 c/w ja = 47 c/w the ADV7330 is a pb-free, environmentally friendly product. it is manufactured using the most up-to-date materials and processes. the coating on the leads of each device is 100% pure sn electro- plate. t he device is suitable for pb-free applications, and is able to withstand surface-mount soldering at up to 255 c ( 5 c). in addition, it is backward compatible with conventional snpb soldering processes. this means that the electroplated sn coating can be soldered with sn/pb solder pastes at conventional reflow temperatures of 220 c to 235 c.
rev. b ?2 ADV7330 pin function descriptions pin number mnemonic i/o function 11, 57 dgnd g digital ground. 2, 3, 14, 15, test0?est14 i not used, tie to dgnd. 51?5, 58?3 40 agnd g analog ground. 32 clkin i pixel clock input for hd (74.25 mhz only, ps (27 mhz), sd (27 mhz)). 36 comp o com pensation pin for dacs. connect 0.1 f capacitor from comp pin to v aa . 39 dac a o cvbs/green/y analog output. 38 dac b o chroma/blue/pb analog output. 37 dac c o luma/red/pr analog output. 25 blank_i/p iv ideo blanking control signal. for hd and ps, this input is active high. for sd input, this input is active low. 23 hsync_i/p iv ideo horizontal sync control signal. 24 vsync_i/p iv ideo vertical sync control signal. 4?, 12, 13 y7?0 i sd or progressive scan/hdtv input port for y data. input port for interleaved progressive scan data. the lsb is set up on pin y0. 16?8, 26?0 c7?0 i 8-bit sd/progressive scan/hdtv input port. the lsb is set up on pin c0. 33 reset it his input resets the on-chip timing generator and sets the ADV7330 into the default register setting. reset is an active low signal. 35 r set ia 3040 ? resistor must be connected from this pin to agnd and is used to control the amplitudes of the dac outputs. 22 sclk i i 2 c port serial interface clock input. 21 sda i/o i 2 c port serial data input/output. 20 alsb i ttl address input. this signal sets up the lsb of the i 2 c address. when this pin is tied low, the i 2 c filter is activated, which reduces noise on the i 2 c interface. 1v dd_io pp ower supply for digital inputs and outputs. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd_io test0 test1 y0 y1 y2 y3 y4 y5 v dd dgnd y6 y7 test2 test3 c0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 c1 c2 i 2 c alsb sda sclk hsync_i/p vsync_i/p blank_i/p c3 c4 c5 c6 c7 rtc_scr_tr clkin 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 blank_o/ p test16 v ref test15 nc nc nc = no connect nc v aa agnd dac a dac b dac c comp r set ext_lf reset 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 gnd_io test14 test13 test12 test11 test10 test9 dgnd v dd test8 test7 test6 test5 test4 hsync_o/ p vsync_o/p pin 1 identifier ADV7330 top view (not to scale)
rev. b ADV7330 ?3 mpu port description the ADV7330 supports a 2-wire serial (i 2 c compatible) micro- processor bus driving multiple peripherals. this bus operates in an open drain configuration. two inputs, serial data (sda) and serial clock (scl), carry information between any devices connected to the bus. each slave device is recognized by a unique address. the ADV7330 has four possible slave ad- dresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 12. the lsb sets either a read or write operation. logic 1 corresponds to a read operation, while logic 0 corresponds to a write operation. a1 is set by setting the alsb pin of the ADV7330 to logic 0 or logic 1. when alsb is set to 1, there is greater input band- width on the i 2 c lines, which allows high speed data transfers on this bus. when alsb is set to 0, there is reduced input bandwidth on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal controller. this mode is recommended for noisy systems. 1 1 0 1 0 1 a1 x address control set up by alsb read/write control 0 write 1 read figure 12. ADV7330 slave address = d4h to control the various devices on the bus, the following proto- col must be followed. first the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda, while scl remains high. this indicates that an address/ data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the periph- eral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is when the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master will write information to the peripheral. a logic 1 on the lsb of the first byte means that the master will read information from the peripheral. the ADV7330 acts as a standard slave device on the bus. the d ata on the sda pin is eight bits long, supporting the 7-bit a ddresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. there is a subaddress auto-increment facility. this allows data to be written to or read from registers in ascending subaddress sequence, starting at any valid subaddress. a d ata transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. pin function descriptions (continued) pin number mnemonic i/o function 10, 56 v dd pd igital power supply. 41 v aa pa nalog power supply. 45, 47 test15, test16 o not used, do not connect. 34 ext_lf i external loop filter for the internal pll. 31 rtc_scr_tr i multifunctional input: real-time control (rtc) input, timing reset input, subcarrier reset input. 48 blank_o/p o video blanking control signal. for hd and ps, this input is active high. for sd input, this output is active low. 50 hsync_o/p ov ideo horizontal sync control signal. 49 vsync_o/p ov ideo vertical sync control signal. 19 i 2 ci this input pin must be tied high (v dd_io ) for the ADV7330 to interface over the i 2 c port. 64 gnd_io digital input/output ground. 42 C 44 nc no connect. 46 v ref i/o optional external voltage reference input for dacs or voltage reference output (1.235 v). terminology sd standard definition video, conforming to itu-r bt.601/656. hd high definition video, such as progressive scan or hdtv. ps progressive scan video, conforming to smpte 293m, itu-r bt.1358, bta t-1004edtc2, bta1362 hdtv high definition television video, conforming to smpte 274m or smpte 296m. ycrcb sd, ps, or hd component digital video. yprpb sd, ps, or hd component analog video.
rev. b ?4 ADV7330 sdata sclock start adrr r/ w ack subaddress ack data ack stop 1?7 8 9 s 1?7 8 9 1?7 89 p figure 13. bus data transfer write sequence read sequence s slave addr a(s) subaddr a(s) data a(s) data a(s) p s slave addr a(s) subaddr a(s) s slave addr a(s) data data a(m) a (m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master lsb = 0 lsb = 1 figure 14. write and read sequence stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given scl high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7330 will not issue an acknowledge and will return to the idle condition. if in auto-increment mode the user exceeds the highest subaddress, the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be output until the master device issues a no acknowledge. this indicates the end of a read. a no acknowl- edge condition is when the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will not be loaded into any subaddress register, a no acknowledge will be issued by the ADV7330, and the part will return to the idle condition. before writing to the subcarrier frequency registers, it is a require- ment that the ADV7330 reset at least once after power-up. the four subcarrier frequency registers must be updated starting with subcarrier frequency register 0 through subcarrier frequency register 3. the subcarrier frequency will not update until the last subcarrier frequency register byte has been received by the ADV7330. figure 13 illustrates an example of data transfer for a write sequence and the start and stop conditions. figure 14 shows bus write and read sequences. register access the mpu can write to or read from all of the registers of the ADV7330 except the subaddress registers that are write-only registers. the subaddress register determines which register the next read or write operation accesses. all communications with the part go through the bus start with an access to the subaddress register. then a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the following tables describe the functionality of each register. all registers can be read from as well as written to, unless other- wise stated. subaddress register (sr7?r0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place.
rev. b ADV7330 ?5 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting register reset values (shaded) 00h power mode sleep mode. with this control enabled, the current consumption is reduced to ? level. all dacs and the internal pll cct are disabled. i 2 c registers can be read from and written to in sleep mode. 0 sleep mode off fch 1 sleep mode on pll and oversampling control. this control allows the internal pll cct to be powered down and the over- sampling to be switched off. 0 pll on 1 pll off dac c. power on/off. 0 dac c off 1 dac c on dac b. power on/off. 0 dac b off 1 dac b on dac a. power on/off. 0 dac a off 1 dac a on xxx reserved 01h input mode 0d isabled 1e nabled clock edge 0 cb clocked on rising edge 1y clocked on rising edge reserved 0 reserved 0 in p ut mode 0 0 0 sd in p ut 38h 001 ps input 010 hdtv input 011 ps 54 mhz in p ut 100 ps 27 mhz input 101 reserved 110 reserved 111 reserved reserved 0 only for ps dual- edge clk mode only for ps interleaved input at 27 mhz bta t-1004 or bt 1362 compatibility.
rev. b ?6 ADV7330 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 02h mode register 0 reserved 00 zero must be written to these bits 20h test pattern black bar 0 disabled 1 enabled rgb matrix 0 disable programmable rgb matrix 1 enable programmable rgb martix sync on rgb 1 0no s y nc 1 sync on all rgb outputs rgb/yuv output 0 rgb component out p uts 1y uv component out p uts sd sync 0 no sync output 1 output sd syncs on hsync_o/p , vsync_o/p , blank_o/p hd sync 0n o sync output 1 output hd syncs on hsync_o/p , vsync_o/p , blank_o/p 03h rgb matrix 0 xx lsb for gy 03h 04h rgb matrix 1 x x lsb for rv f0h xx lsb for bu xx lsb for gv xx lsb for gu 05h rgb matrix 2 x x x x x x x x bit 9? for gy 4eh 06h rgb matrix 3 x x x x x x x x bit 9? for gu 0eh 07h rgb matrix 4 x x x x x x x x bit 9? for gv 24h 08h rgb matrix 5 x x x x x x x x bit 9? for bu 92h 09h rgb matrix 6 x x x x x x x x bit 9? for rv 7ch 0ah xx xx xx xx reserved 0bh dac a,b,c output level 2 positive gain to dac output voltage 0 0 0 0 0 0 0 0 0% 00h 00 00 00 01 0.018% 00 00 00 10 0.036% 00 11 11 11 7.382% 01 00 00 00 7.5% negative gain to dac output voltage 1 1 0 0 0 0 0 0 ?.5% 11 00 00 01 ?.382% 10 00 00 10 ?.364% . 11 11 11 11 ?.018% 0ch reserved 00h 0dh reserved 00h 0eh reserved 00h 0fh reserved 00h 11h, bit 2 must also be enabled notes 1 for more detail, refer to appendix 7. 2 for more detail on the programmable output levels, refer to the programmable dac gain control section.
rev. b ADV7330 ?7 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 10h hd mode register 1 hd output standard 0 0 eia770.2 output 00h 01 eia770.1 output 10 output levels for full input ran g e 11 reserved hd input control signals 0 0 hsync , vsync , blank 01 eav/sav codes 10 async timing mode 11 reserved hd 625p 0 525p 1 625p hd 720p 0 1080i 1 720p hd blank polarity 0 blank active high 1 blank active low hd macrovision for 525p/625p 0 macrovision off 1 macrovision on 11h hd mode register 2 hd pixel data valid 0 pixel data valid off 00h 1 pixel data valid on 0 reserved hd test pattern enable 0 hd test pattern off 1 hd test pattern on hd test pattern hatch/field 0 hatch 1 field/frame hd vbi open 0 disabled 1 enabled hd undershoot limiter 0 0 disabled 01 ?1 ire 10 ? ire 11 ?.5 ire hd sharpness filter 0 disabled 1 enabled
rev. b ?8 ADV7330 notes 1 when set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. wh en set to 1, the field/line counters are free running and wrap around when external sync signals indicate so. sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 12h hd mode register 3 000 0 clk cycle 00h 00 11 clk cycle 010 2 clk c y cles 01 13 clk cycles 100 4 clk cycles 00 0 0 clk cycle 00 1 1 clk cycle 01 0 2 clk c y cles 01 13 clk cycles 10 0 4 clk c y cles hd cgms 0 disabled 1 enabled hd cgms crc 0 disabled 1 enabled 13h hd mode register 4 hd cr/cb sequence 0 cb after falling edge of hsync 4ch 1 cr after falling edge of hsync reserved 00 must be written to this bit. reserved 0 0 must be written to this bit. sinc filter on dac a, b, c 0 disabled 1 enabled reserved 0 0 must be written to this bit. hd chroma ssaf 0 disabled 1 enabled reserved 1 hd double buffering 0 disabled 1 enabled 14h hd mode register 5 hd timing reset xa low-high-low transition resets the internal hd timing counters. 00h 00 30 hz/2200 total samples/line 01 25 hz/2640 total samples/line reserved 00 0 0 must be written to these bits. hd vsync/field input 0 field input 1 vsync input lines/frame 1 0 update field/line counter 1 field/line counter free running 15h hd mode register 6 reserved 0 0 must be written to this bit. 00h hd rgb input 0 disabled 1 enabled hd sync on prpb 0 disabled 1 enabled hd color dac swap 0 dac e = pr; dac f = pb 1 dac e = pb ; dac f = pr hd gamma curve a/b 0 gamma curve a 1 gamma curve b hd gamma curve enable 0 disabled 1 enabled hd adaptive filter mode 0 mode a 1 mode b hd adaptive filter enable 0 disabled 1 enabled hd y delay with respect to falling edge of hsync hd color delay with respect to falling edge of hsync 1080i frame rate
rev. b ADV7330 ?9 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 16h hd y level 1 xxxxx xx x y color value a0h 17h hd cr level 1 xx xx xx xx cr color value 80h 18h hd cb level 1 xxxxx xx x cb color value 80h 19h reserved 00h 1ah reserved 00h 1bh reserved 00h 1ch reserved 00h 1dh reserved 00h 1eh reserved 00h 1fh reserved 00h 20h hd sharpness filter hd sharpness filter gain value a 00 00 gain a = 0 00h gain 0 00 1 gain a = +1 .. .. .. .. 01 11 gain a = +7 10 00 gain a = ? .. .. .. .. 11 11 gain a = ? hd sharpness filter gain value b 00 00 gain b = 0 0 00 1 gain b = +1 .. .. .. .. . 0 11 1 gain b = +7 10 00 gain b = ? .. .. .. .. .. 11 11 gain b = ? 21h hd cgms data 0 hd cgms data bits 0 0 0 0 c19 c18 c17 c16 cgms 19?6 00h 22h hd cgms data 1 hd cgms data bits c15 c14 c13 c12 c11 c10 c9 c8 cgms 15? 00h 23h hd cgms data 2 hd cgms data bits c7 c6 c5 c4 c3 c2 c1 c0 cgms 7? 00h 24h hd gamma a hd gamma curve a data points x x x x x x x x a0 00h 25h hd gamma a hd gamma curve a data points x x x x x x x x a1 00h 26h hd gamma a hd gamma curve a data points x x x x x x x x a2 00h 27h hd gamma a hd gamma curve a data points x x x x x x x x a3 00h 28h hd gamma a hd gamma curve a data points x x x x x x x x a4 00h 29h hd gamma a hd gamma curve a data points x x x x x x x x a5 00h 2ah hd gamma a hd gamma curve a data points x x x x x x x x a6 00h 2bh hd gamma a hd gamma curve a data points x x x x x x x x a7 00h 2ch hd gamma a hd gamma curve a data points x x x x x x x x a8 00h 2dh hd gamma a hd gamma curve a data points x x x x x x x x a9 00h 2eh hd gamma b hd gamma curve b data points x x x x x x x x b0 00h 2fh hd gamma b hd gamma curve b data points xxxxxxxxb1 00h 30h hd gamma b hd gamma curve b data points x x x x x x x x b2 00h 31h hd gamma b hd gamma curve b data points xxxxxxxxb3 00h 32h hd gamma b hd gamma curve b data points x x x x x x x x b4 00h 33h hd gamma b hd gamma curve b data points x x x x x x x x b5 00h 34h hd gamma b hd gamma curve b data points xxxxxxxxb6 00h 35h hd gamma b hd gamma curve b data points x x x x x x x x b7 00h 36h hd gamma b hd gamma curve b data points xxxxxxxx b8 00h 37h hd gamma b hd gamma curve b data points x x x x x x x x b9 00h notes 1 for the internal test pattern only.
rev. b ?0 ADV7330 sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 38h hd adaptive filter hd adaptive filter gain 1 00 00 gain a = 0 00h gain 1 value a 00 01 gain a = +1 .. .. .. .. 01 11 gain a = +7 10 00 gain a = ? .. .. .. .. 11 11 gain a = ? hd adaptive filter gain 1 00 00 gain b = 0 value b 00 01 gain b = +1 .. .. .. .. . 01 11 gain b = +7 10 00 gain b = ? .. .. .. .. .. 11 11 gain b = ? 39h hd adaptive filter hd adaptive filter gain 2 00 00 gain a = 0 00h gain 2 value a 00 01 gain a = +1 .. .. .. .. 01 11 gain a = +7 10 00 gain a = ? .. .. .. .. 11 11 gain a = ? hd adaptive filter gain 2 00 00 gain b = 0 value b 00 01 gain b = +1 .. .. .. .. . 01 11 gain b = +7 10 00 gain b = ? .. .. .. .. .. 11 11 gain b = ? 3ah hd adaptive filter hd adaptive filter gain 3 00 00 gain a = 0 00h gain 3 value a 00 01 gain a = +1 .. .. .. .. 01 11 gain a = +7 10 00 gain a = ? .. .. .. .. 11 11 gain a = ? hd adaptive filter gain 3 00 00 gain b = 0 value b 00 01 gain b = +1 .. .. .. .. . 01 11 gain b = +7 10 00 gain b = ? .. .. .. .. .. 11 11 gain b = ? 3bh hd adaptive filter hd adaptive filter threshold a xx xx xx xx threshold a 00h threshold a value 3ch hd adaptive filter hd adaptive filter threshold b xx xx xx xx threshold b 00h threshold b value 3dh hd adaptive filter hd adaptive filter threshold c xx xx xx xx threshold c 00h threshold c value
rev. b ADV7330 ?1 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 3eh reserved 00h 3fh reserved 00h 40h sd mode register 0 sd standard 0 0 ntsc 00h 01 pal b, d, g, h, i 10 pal m 11 pal n sd luma filter 0 0 0 lpf ntsc 00 1 lpf pal 01 0 notch ntsc 01 1 notch pal 100 ssaf luma 101 luma cif 110 luma qcif 111 reserved sd chroma filter 0 0 0 1.3 mhz 00 1 0.65 mhz 01 0 1.0 mhz 01 1 2.0 mhz 10 0 reserved 10 1 chroma cif 11 0 chroma qcif 11 1 3.0 mhz 41h reserved 00h 42h sd mode register 1 sd prpb ssaf 0 disabled 08h 1 enabled sd dac output 1 0 refer to the output configuration 1 section sd dac output 2 0 refer to the output configuration 1 section sd pedestal 0 disabled 1 enabled sd square pixel 0 disabled 1 enabled sd vcr ff/rw sync 0 disabled 1 enabled sd pixel data valid 0 disabled 1 enabled sd sav/eav step edge control 0 disabled 1 enabled 43h sd mode register 2 sd pedestal yprpb output 0 no pedestal on yprpb 00h 1 7.5 ire pedestal on yprpb sd output levels y 0 y = 700 mv/300 mv 1 y = 714 mv/286 mv sd output levels prpb 0 0 700 mv p-p (pal); 1000 mv p-p (ntsc) 01 700 mv p-p 10 1000 mv p-p 11 648 mv p-p sd vbi open 0 disabled 1 enabled sd cc field control 0 0 cc disabled 01 cc on odd field only 10 cc on even field only 11 cc on both fields reserved 0 reserved
rev. b ?2 ADV7330 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 44h sd mode register 3 sd vsync-3h 0 disabled 00h 1 vsync = 2.5 lines (pal) vsync = 3 lines (ntsc) sd rtc/tr/scr * 00 genlock disabled 01 subcarrier reset 10 timing reset 11 rtc enabled sd active video length 0 720 pixels 1 710 (ntsc)/702 (pal) sd chroma 0 chroma enabled 1 chroma disabled sd burst 0 enabled 1 disabled sd color bars 0 disabled 1 enabled sd dac swap 0 dac b = luma dac c = chroma 1 dac b = chroma dac c = luma 45h reserved 00h 46h reserved 00h 47h sd mode register 4 sd prpb scale 0 disabled 00h 1 enabled sd y scale 0 disabled 1 enabled sd hue adjust 0 disabled 1 enabled sd brightness 0 disabled 1 enabled sd luma ssaf gain 0 disabled 1 enabled reserved 0 0 must be written to this bit. reserved 0 0 must be written to this bit. reserved 0 0 must be written to this bit. 48h sd mode register 5 reserved 00 must be written to this bit. reserved 00 must be written to this bit. sd double buffering 0 disabled 1 enabled sd input format 0 8-bit input 1 16-bit input reserved 0 0 must be written to this bit. sd digital noise reduction 0 disabled 1 enabled sd gamma control 0 disabled 1 enabled sd gamma curve 0 gamma curve a 1 gamma curve b 49h sd mode register 6 sd undershoot limiter 0 0 disabled 00h 01 ?1 ire 10 ? ire 11 ?.5 ire reserved 00 must be written to this bit. sd black burst output on dac luma 0 disabled 1 enabled sd chroma delay 0 0 disabled 01 4 clk cycles 10 8 clk cycles 11 reserved reserved 0 0 must be written to this bit. reserved 0 0 must be written to this bit. * see figure 23, rtc timing and connections.
rev. b ADV7330 ?3 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 4ah sd timing register 0 sd slave/master mode 0s lave mode 08h 1 master mode sd timing mode 00 mode 0 01 mode 1 10 mode 2 11 mode 3 sd blank input 0 enabled 1dis abled sd luma delay 00 no delay 01 2 clk cycles 10 4 clk cycles 11 6 clk cycles sd min. luma value 0 40 ire 1 7. 5 ire sd timing reset x 0 0 0 0 0 0 0 a low-high-low transition will reset the internal sd timing counters. 4bh sd timing register 1 sd hsync width 0 0 t a = 1 clk cycle 00h 01t a = 4 clk cycles 10 t a = 16 clk cycles 11t a = 128 clk cycles sd hsync to vsync delay 0 0 t b = 0 clk cycle 01 t b = 4 clk cycles 10 t b = 8 clk cycles 11 t b = 18 clk cycles sd hsync to vsync rising x 0 t c = t b edge delay (mode 1 only) x1 t c = t b + 32 ? vsync width (mode 2 only) 00 1 clk cycle 01 4 clk cycles 10 16 clk cycles 11 128 clk cycles hsync to pixel data adjust 0 0 0 clk cycles 01 1 clk cycle 10 2 clk cycles 11 3 clk cycles 4ch sd f sc register 0 xx xx xx xx subcarrier frequency bit 7? 16h 4dh sd f sc register 1 xx xx xx xx subcarrier frequency bit 15? 7ch 4eh sd f sc register 2 xx xx xx xx subcarrier frequency bit 23?6 f0h 4fh sd f sc register 3 xx xx xx xx subcarrier frequency bit 31?4 21h 50h sd f sc phase xx xx xx xx subcarrier phase bit 9? 00h 51h sd closed captioning extended data on even fields xx xx xx xx extended data bit 7? 00h 52h sd closed captioning extended data on even fields xx xx xx xx extended data bit 15? 00h 53h sd closed captioning data on odd fields xx x xx x xx data bit 7? 00h 54h sd closed captioning data on odd fields xx xx xx xx data bit 15? 00h 55h sd pedestal register 0 pedestal on odd fields 17 16 15 14 13 12 11 10 setting any of these bits to 1 00h 56h sd pedestal register 1 pedestal on odd fields 25 24 23 22 21 20 19 18 will disable pedestal on the 00h 57h sd pedestal register 2 pedestal on even fields 17 16 15 14 13 12 11 10 line number indicated by the 00h 58h sd pedestal register 3 pedestal on even fields 25 24 23 22 21 20 19 18 bit settings. 00h line 313 line 314 line 1 t b h sync vsync t a t c figure 15. timing register 1 in pal mode
rev. b ?4 ADV7330 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 59h sd cgms/wss 0 sd cgms data 19 18 17 16 cgms data bits c19-c16 00h sd cgms crc 0 disabled 1 enabled sd cgms on odd fields 0 disabled 1 enabled sd cgms on even fields 0 disabled 1 enabled sd wss 0 disabled 1 enabled 5ah sd cgms/wss 1 sd cgms/wss data 13 12 11 10 9 8 cgms data bits c13?8 or wss data bits c13?8 00h 15 14 cgms data bits c15?14 00h 5bh sd cgms/wss 2 sd cgms/wss data 7 6 5 4 3 210 cgms/wss data bits c7?0 00h 5ch sd lsb register sd lsb for y scale value xx sd y scale bit 1? sd lsb for u scale value x x sd u scale bit 1? sd lsb for v scale value x x sd v scale bit 1? sd lsb for f sc phase x x subcarrier phase bits 1? 5dh sd y scale ri sd y scale value x x x x x x x x sd y scale bit 7? 00h 5eh sd v scale ri sd v scale value x x x x x x x x sd v scale bit 7? 00h 5fh sd u scale ri sd u scale value x x x x x x x x sd u scale bit 7? 00h 60h sd hue register sd hue adjust value x x x x x x x x sd hue adjust bit 7? 00h 61h sd brightness value x x x x x x x sd brightness bit 6? 00h sd blank wss data 0 disabled line 23 1 enabled 62h sd luma ssaf sd luma ssaf gain/attenuation 00 0 000004 db 00h 00 0 001100 db 00 0 011004 db 63h sd dnr 0 coring gain border 0000no gain 00h 0001 +1/16 (?/8) in dnr 0010 +2/16 (?/8) modes the 0011 +3/16 (?/8) values in the 0100 +4/16 (?/8) parentheses apply. 0101 +5/16 (?/8) 0110 +6/16 (?/8) 0111 +7/16 (?/8) 1000 +8/16 (?) coring gain data 00 00 no gain 00 01 +1/16 (?/8) 00 10 +2/16 (?/8) 00 11 +3/16 (?/8) 01 00 +4/16 (?/8) 01 01 +5/16 (?/8) 01 10 +6/16 (?/8) 01 11 +7/16 (?/8) 10 00 +8/16 (?) 64h sd dnr 1 dnr threshold 0 000000 00h 0 000011 1 1111062 1 1111163 border area 02 pixels 14 pixels block size control 0 8 pixels 1 16 pixels sd brightness/ w ss
rev. b ADV7330 ?5 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 65h sd dnr 2 dnr input select 0 0 1 filter a 00h 01 0f ilter b 01 1f ilter c 1 0 0 filter d dnr mode 0 dnr mode 1 dnr sharpness mode dnr block offset 0 000 0 pixel offset 0 001 1 pixel offset 1 110 14 pixel offset 1 111 15 pixel offset 66h sd gamma a sd gamma curve a data points x x x x x x x x a0 00h 67h sd gamma a sd gamma curve a data points x x x x x xxx a1 00h 68h sd gamma a sd gamma curve a data points x x x x x xxx a2 00h 69h sd gamma a sd gamma curve a data points x x x x x xxx a3 00h 6ah sd gamma a sd gamma curve a data points x x x x x x x x a4 00h 6bh sd gamma a sd gamma curve a data points x x x x x x x x a5 00h 6ch sd gamma a sd gamma curve a data points x x x x x xxx a6 00h 6dh sd gamma a sd gamma curve a data points x x x x x xxx a7 00h 6eh sd gamma a sd gamma curve a data points x x x x x x x x a8 00h 6fh sd gamma a sd gamma curve a data points x x x x x x x x a9 00h 70h sd gamma b sd gamma curve b data points x x x x x x x x b0 00h 71h sd gamma b sd gamma curve b data points x x x x x xxx b1 00h 72h sd gamma b sd gamma curve b data points x x x x x xxx b2 00h 73h sd gamma b sd gamma curve b data points x x x x x x x x b3 00h 74h sd gamma b sd gamma curve b data points x x x x x x x x b4 00h 75h sd gamma b sd gamma curve b data points x x x x x x x x b5 00h 76h sd gamma b sd gamma curve b data points x x x x x xxx b6 00h 77h sd gamma b sd gamma curve b data points x x x x x xxx b7 00h 78h sd gamma b sd gamma curve b data points x x x x x x x x b8 00h 79h sd gamma b sd gamma curve b data points x x x x x x x x b9 00h 7ah sd brightness detect sd brightness value x xxx x xx x read-only 7bh field count register field count xx x read-only reserved 0 0 must be written to this bit. reserved 0 0 must be written to this bit. reserved 0 0 must be written to this bit. revision code xx read-only 7c reserved 00h
rev. b ?6 ADV7330 sr7 sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 7dh reserved 7eh reserved 7fh reserved 80h macrovision mv control bits x xx xx xx x 00h 81h macrovision mv control bits x xx xx xx x 00h 82h macrovision mv control bits x x x x x x x x 00h 83h macrovision mv control bits x x x x x x x x 00h 84h macrovision mv control bits x x x x x x x x 00h 85h macrovision mv control bits x xx xx xx x 00h 86h macrovision mv control bits x xx xx xx x 00h 87h macrovision mv control bits x x x x x x x x 00h 88h macrovision mv control bits x x x x x x x x 00h 89h macrovision mv control bits x xx xx xx x 00h 8ah macrovision mv control bits x xx xx xx x 00h 8bh macrovision mv control bits x xx xx xx x 00h 8ch macrovision mv control bits x x x x x x x x 00h 8dh macrovision mv control bits x x x x x x x x 00h 8eh macrovision mv control bits x xx xx xx x 00h 8fh macrovision mv control bits x xx xx xx x 00h 90h macrovision mv control bits x x x x x x x x 00h 91h macrovision mv control bits x 00h 00000 00 0 must be written to these bits.
rev. b ADV7330 ?7 input configuration note that the ADV7330 defaults to progressive scan 54 mhz mode on power-up. address(01h): input mode = 011 standard definition address(01h): input mode = 000 the 8-bit multiplexed input data is input on pins y7?0, with y0 being the lsb. input standards supported are itu-r bt.601/656. in 16-bit input mode the y pixel data is input on pins y7?0 and crcb data on pins c7?0. input sync signals are optional and are input on the vsync_i/p , hsync_i/p , and blank_i/p pins. mpeg2 decoder vsync_i/p hsync_i/p blank_i/p clkin y[7:0] 27mhz 3 8 ycrcb ADV7330 figure 16. sd input mode progressive scan or hdtv mode address(01h): input mode 001 or 010, respectively ycrcb progressive scan, hdtv, or any other hd ycrcb data can be input in 4:2:2. in 4:2:2 input mode, the y data is input on pins y7?0 and the crcb data on pins c7?0. if the ycrcb data does not conform to smpte 293m (525p), itu-r bt.1358m (625p), smpte 274m (1080i), smpte 296m (720p), or bta t-1004/1362, the async timing mode must be used. ADV7330 mpeg2 decoder vsync_i/p hsync_i/p blank_i/p clkin c[7:0] y[7:0] interlaced to progressive ycrcb 8 cbcr 8 y 3 27mhz figure 17. progressive scan input mode progressive scan at 27 mhz (dual edge) or 54 mhz address(01h): input mode 100 or 111, respectively ycrcb progressive scan data can be input at 27 mhz or 54 mhz. the input data is interleaved onto a single 8-bit bus and is input on pins y7?0. when a 27 mhz clock is supplied, the data is clocked in on the rising and falling edge of the input clock and clock edge [address 01h, bit 1] must be set accordingly. the following figures show the possible conditions. y7?y0 3ff 00 00 xy cb0 y0 cr0 y1 clkin figure 18a. cb data on rising edge?lock edge address 01h bit 1 should be set to 0 y7?y0 3ff 00 00 xy y0 cb0 y1 cr0 clkin figure 18b. y data on rising edge?lock edge address 01h bit 1 should be set to 1 with a 54 mhz clock, the data is latched on every rising edge. pixel input data 3ff 00 00 xy cb0 y0 cr0 y1 clkin figure 18c. input sequence in ps bit interleaved mode (eav/sav) ADV7330 mpeg2 decoder vsync_i/p hsync_i/p blank_i/p clkin y[7:0] interlaced to progressive ycrcb 8 ycrcb 3 27mhz or 54mhz figure 19. 1 8-bit ps at 27 mhz or 54 mhz
rev. b ?8 ADV7330 table i provides an overview of possible input configurations. table i. input configurations input input input register format total bits video pins subaddress setting itu-r 8 4:2:2 ycrcb y7?0 01h 00h bt.656 48h 00h 16 4:2:2 y y7?0 01h 00h ycrcb c7?0 48h 08h ps 8 (27 mhz clock) 4:2:2 ycrcb y7?0 10h 40h 13h 40h 8 (54 mhz clock) 4:2:2 ycrcb y7?0 10h 30h 13h 40h 16 4:2:2 y y7?0 01h 10h crcb c7?0 13h 40h hdtv 16 4:2:2 y y7?0 01h 20h crcb c7?0 13h 40h output configuration tables ii and iii show which output signals are assigned to the dacs when according control bits are set. table iii. output configuration in hd/ps mode hd input rgb/yprpb output hd color swap format 02h, bit 5 15h, bit 3 dac a dac b dac c ycrcb 4:2:2 1 0 y pb pr ycrcb 4:2:2 1 1 y pr pb ycrcb 4:2:2 0 0 g b r ycrcb 4:2:2 0 1 g r b table ii. output configuration in sd mode rgb/yprpb output sd dac output 1 sd dac output 1 sd dac swap 02h, bit 5 42h, bit 2 42h, bit 1 44h, bit 7 dac a dac b dac c 0000gbr 0001gbr 00 10 cvbs luma chroma 00 11 cvbs chroma luma 01 00 cvbs b r 01 01 cvbs b r 01 10 g luma chroma 01 11 g chroma luma 1000ypbpr 1001ypbpr 10 10 cvbs luma chroma 10 11 cvbs chroma luma 11 00 cvbs pb pr 11 01 cvbs pb pr 11 10 y luma chroma 11 11 y chroma luma
rev. b ADV7330 ?9 timing modes hd async timing mode [subaddress 10h, bit 3,2] for any input data that does not conform to the standards select- able in input mode, subaddress 10h, asynchronous timing mode can be used to interface to the ADV7330. timing control signals for hsync, vsync, and blank have to be programmed by the user. macrovision and programmable oversampling rates are not avail- able in async timing mode. in async mode, the pll must be turned off [subaddress 01h, bit 1 = 1]. clk active video programmable input timing analog output ab cd 81 66 66 243 1920 horizontal sync e hsync_i/p vsync_i/p blank_i/p set address 10h, bit 6 to 1 figure 20a. async timing mode?rogramming input control signals for smpte 295m compatibility active video 0 1 horizontal sync ab c d e clk hsync_i/p vsync_i/p blank_i/p set address 10h, bit 6 to 1 analog output figure 20b. async timing mode?rogramming input control signals for bilevel sync signals figures 20a and 20b show an example of how to program the ADV7330 to accept a different high definition standard other than smpte 293m, smpte 274m, smpte 296m, or itu-r bt.1358. the following truth table must be followed when programming the control signals in async timing mode. for standards that do not require a tri-sync level, blank_i/p must be tied low at all times.
rev. b ?0 ADV7330 table iv. async timing mode truth table reference in hsync_i/p vsync_i/p blank_i/p * figures 20a and 20b 1 0 0 0 or 1 50% point of falling edge of tri-level horizontal sync signal a 00 1 0 or 1 25% point of rising edge of tri-level horizontal sync signal b 0 1 0 or 1 0 50% point of falling edge of tri-level horizontal sync signal c 10 or 1 0 1 50% start of active video d 10 or 1 1 0 50% end of active video e * when async timing mode is enabled, blank_i/p (pin 25) becomes an active high input. blank_i/p is set to active low at address 10h, bit 6. hd timing reset [address 14h, bit 0] a timing reset is achieved in setting the hd timing reset control bit at address 14h from 0 to 1. in this state, the horizontal and vertical counters will remain reset. when this bit is set back to 0, the internal counters will commence counting again. pll must be powered off by this mode. the minimum time the pin has to be held high is one clock cycle, otherwise this reset signal might not be recognized. this timing reset applies to the hd timing counters only.
rev. b ADV7330 ?1 sd real-time control, subcarrier reset, timing reset [subaddress 44h, bit 2,1] together with the rtc_scr_tr pin and sd mode register 3 [address 44h, bit 1,2], the ADV7330 can be used in timing reset mode, subcarrier phase reset mode, or rtc mode. a timing reset is achieved in a low-to-high transition on the rtc_scr_tr pin (pin 31). in this state, the horizontal and vertical counters will remain reset. on releasing this pin (set to low), the internal counters will commence counting again, the field count will start on field 1, and the subcarrier phase will also be reset. the minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. this timing reset applies to the sd timing counters only. in subcarrier phase reset, a low-to-high transition on the rtc_scr_tr pin (pin 31) will reset the subcarrier phase to zero on the field following the subcarrier phase reset when the sd rtc/tr/scr control bits at address 44h are set to 01. display no timing reset applied timing reset applied start of field 4 or 8 f sc phase = field 4 or 8 f sc phase = field 1 timing reset pulse 307 310 307 1 2 3 4 5 6 7 21 313 320 display start of field 1 figure 21. timing reset timing diagram no f sc reset applied f sc phase = field 4 or 8 307 310 313 320 display start of field 4 or 8 f sc reset applied f sc reset pulse f sc phase = field 1 307 310 313 320 display start of field 4 or 8 figure 22. subcarrier reset timing diagram this reset signal will have to be held high for a minimum of one clock cycle. since the field counter is not reset, it is recommended that the reset signal be applied in field 7 [pal] or field 3 [ntsc]. the reset of the phase will then occur on the next field, i.e., field 1 being lined up correctly with the internal counters. the field count register at address 7bh can be used to identify the number of the active field. in rtc mode, the ADV7330 can be used to lock to an external video source. the real-time control mode allows the ADV7330 to automatically alter the subcarrier frequency to compensate for line length variations. when the part is connected to a device that outputs a digital data stream in the rtc format (such as an adv7183a video decoder, see figure 23), the part will auto- matically change to the compensated subcarrier frequency on a line by line basis. this digital data stream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is two clock cycles long. 00h should be written into all four subcarrier frequency registers when this mode is used.
rev. b ?2 ADV7330 lcc1 gll p17?p10 composite video e.g., vcr or cable clkin rtc_scr_tr dac a dac b dac c y7?y0 rtc low h/l transition count start 128 time slot: 01 13 0 14 bits subcarrier phase 14 21 19 f sc pll increment 1 valid sample invalid sample 8/line locked clock 6768 4 bits reserved 0 sequence bit 2 reset bit 3 reserved 5 bits reserved ADV7330 video decoder adv7183a notes 1 f sc pll increment is 22 bits long, value loaded into ADV7330, f sc dss register is f sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the ADV7330. 2 sequence bit. pal: 0 = line normal, 1 = line inverted. ntsc: 0 = no change. 3 reset bit. reset ADV7330 dss. figure 23. rtc timing and connections xxxxxx xxxxxx off digital timing signals suppressed valid video timing active reset digital timing dacs a, b, c pixel data valid figure 24. reset timing sequence reset sequence a reset is activated with a high-to-low transition on the reset pin (pin 33) according to the timing specifications. the ADV7330 will revert to the default output configuration. figure 24 illustrates the reset sequence timing. sd vcr ff/rw sync [subaddress 42h, bit 5] in dvd record applications where the encoder is used with a decoder, the vcr ff/rw sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes. in fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields are reached. in rewind mode, this sync signal usually occurs after the total number of lines/fields are reached. conventionally this means that the output video will have corrupted field signals, one generated by the incoming video and one generated when the internal lines/field counters reach the end of a field. when the vcr ff/rw sync control is enabled [subaddress 42h, bit 5], the lines/field counters are updated according to the incoming vsync signal, and the analog output matches the incoming vsync signal. this control is available in all slave timing modes except slave m ode 0.
rev. b ADV7330 ?3 vertical blanking interval the ADV7330 accepts input data that contains vbi data (such as cgms, wss, vits) in sd and hd modes. for smpte 293m (525p) standards, vbi data can be inserted on lines 13 to 42 of each frame, or lines 6 to 43 for the itu-r bt .1358 [625p] standard. for sd ntsc, this data can be present on lines 10 to 20; in pal, on lines 7 to 22. if vbi is disabled [address 11h, bit 4 for hd; address 43h, bi t4 for sd], vbi data is not present at the output and the entire vbi is blanked. these control bits are valid in all master and slave modes. in slave mode 0, if vbi is enabled, the blanking bit in the eav/sav code is overwritten; it is possible to use vbi in this timing mode as well. in slave mode 1 or 2, the blank control bit must be set to enabled [address 4ah, bit 3] to allow vbi data to pass through the ADV7330; otherwise, the ADV7330 automatically blanks the vbi to standard. if cgms is enabled and vbi disabled, the cgms data will nevertheless be available at the output. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data ( hanc) 4 clock 4 clock 272 clock 1280 clock 4 clock 4 clock 344 clock 1536 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y figure 25. eav/sav embedded timing field pixel data pal = 44 clock cycles ntsc = 44 clock cycles pal = 136 clock cycles ntsc = 208 clock cycles cb y cr y h sync b lank figure 26. active pixel timing sd subcarrier frequency registers [subaddress 4ch?fh] four 8-bit wide registers are used to set up the subcarrier frequency. the value of these registers is calculated using the following equation: subcarrier frequency register subcarrier frequencyvalue in one video line mhz clk cycles in one video line = # #27 2 32 for example, ntsc mode, subcarrier frequencyvalue = ? ? ? ? ? ? = 227 5 1716 2 569408542 32 . subcarrier register value = 21f07c1eh sd f sc register 0: 1eh sd f sc register 1: 7ch sd f sc register 2: f0h sd f sc register 3: 21h refer to the mpu port description section for details on how to access the subcarrier frequency registers. square pixel timing [register 42h, bit 4] in square pixel mode, the timing diagrams in figures 25 and 26 apply.
rev. b ?4 ADV7330 filter section table v shows an overview of the programmable filters available on the ADV7330. hd sinc filter frequency ( mhz ) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 filter 27. hd sinc filter enabled frequency ( mhz ) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 figure 28. hd sinc filter disabled table v. selectable filters of the ADV7330 filter subaddress sd luma lpf ntsc 40h sd luma lpf pal 40h sd luma notch ntsc 40h sd luma notch pal 40h sd luma ssaf 40h sd luma cif 40h sd luma qcif 40h sd chroma 0.65 mhz 40h sd chroma 1.0 mhz 40h sd chroma 1.3 mhz 40h sd chroma 2.0 mhz 40h sd chroma 3.0 mhz 40h sd chroma cif 40h sd chroma qcif 40h sd uv ssaf 42h hd chroma input 13h hd sinc filter 13h hd chroma ssaf 13h
rev. b ADV7330 ?5 table vi. internal filter specifications pass-band ripple 3 db bandwidth filter (db) 1 (mhz) 2 luma lpf ntsc 0.16 4.24 luma lpf pal 0.1 4.81 luma notch ntsc 0.09 2.3/4.9/6.6 luma notch pal 0.1 3.1/5.6/6.4 luma ssaf 0.04 6.45 luma cif 0.127 3.02 luma qcif monotonic 1.5 chroma 0.65 mhz monotonic 0.65 chroma 1.0 mhz monotonic 1 chroma 1.3 mhz 0.09 1.395 chroma 2.0 mhz 0.048 2.2 chroma 3.0 mhz monotonic 3.2 chroma cif monotonic 0.65 chroma qcif monotonic 0.5 notes 1 pass-band ripple refers to the maximum fluctuations from the 0 db response in the pass band, measured in (db). the pass band is defined to have 0 (hz) to fc (hz) frequency limits for a low-pass filter, 0 (hz) to f1 (hz) and f2 (hz) to infinity for a notch filter, where fc, f1, f2 are the ? db points. 2 3 db bandwidth refers to the ? db cutoff frequency. frequency (mhz) 0 gain (db) ?10 ?30 ?50 ?60 ?20 ?40 6 5 4 3 2 1 0 extended uv filter mode figure 29. uv ssaf filter sd internal filter response [subaddress 40h; subaddress 42, bit 0] the y filter supports several different frequency responses includ- ing two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost/attenuation, a cif response, and a qcif response. the uv filter supports several different frequency responses including six low-pass responses, ac if response, and a qcif response, as can be seen in the t ypical performance characteristics graphs on the following pages. if sd ssaf gain is enabled, there is the option of 12 responses in the range of ? db to +4 db [subaddress 47, bit 4]. the desired response can be chosen by the user by programming the correct value via the i 2 c [subaddress 62h]. the variation of frequency responses can be seen in the typical performance characteristics graphs on the following pages. in addition to the chroma filters listed in table vi, the ADV7330 contains an ssaf filter specifically designed for and applicable to the color difference component outputs, u and v. this filter has a cutoff frequency of about 2.7 mhz and ?0 db at 3.8 mhz, as can be seen in figure 29. this filter can be controlled with address 42h, bit 0. if this filter is disabled, the selectable chroma filters shown in table vi can be used for the cvbs or chroma signal.
rev. b ?6 ADV7330?ypical performance characteristics frequency (mhz) prog scan pr/pb response. linear interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 tpc 1. ps?v (8 oversampling filter (linear)) frequency (mhz) prog scan pr/pb response. ssaf interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 tpc 2. ps?v (8 oversampling filter (ssaf)) frequency (mhz) y response in ps oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 tpc 3. ps? (8 oversampling filter) frequency (mhz) y pass band in ps oversampling mode gain (db) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?3.0 12 246810 0 tpc 4. ps? (8 oversampling filter (pass band)) frequency (mhz) pr/pb response in hdtv oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 140 20 40 60 80 100 120 0 tpc 5. hdtv?v (2 oversampling filter) frequency (mhz) y response in hdtv oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 140 20 40 60 80 100 120 0 tpc 6. hdtv? (2 oversampling filter)
rev. b ADV7330 ?7 frequency ( mhz ) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 7. luma ntsc low-pass filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 8. luma pal low-pass filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 9. luma ntsc notch filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 10. luma pal notch filter frequency (mhz) y response in sd oversampling mode gain (db) 0 ?50 ?80 0204 06080 100 120 140 160 180 200 ?10 ?40 ?60 ?70 ?20 ?30 tpc 11. y-16 oversampling filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 12. luma ssaf filter up to 12 mhz
rev. b ?8 ADV7330 frequency (mhz) 4 01234 7 magnitude (db) 2 ?2 ?6 ?8 ?12 0 ?4 5 ?10 6 tpc 13. luma ssaf filter?rogrammable responses frequency ( mhz ) 01234 7 magnitude (db) 5 4 2 1 ?1 3 5 0 6 tpc 14. luma ssaf filter?rogrammable gain frequency ( mhz ) 01234 7 magnitude (db) 1 0 ?2 ?3 ?5 ?1 5 ?4 6 tpc 15. luma ssaf filter?rogrammable attenuation frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 16. luma cif lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 17. luma qcif lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 18. chroma 3.0 mhz lp filter
rev. b ADV7330 ?9 frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 19. chroma 2.0 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 20. chroma 1.3 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 21. chroma 1.0 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 22. chroma 0.65 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 23. chroma cif lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 24. chroma qcif lp filter
rev. b ?0 ADV7330 color controls and rgb matrix hd y level, cr level, cb level [subaddress 16h?8h] three 8-bit wide registers at addresses 16h, 17h, 18h are used to program the output color of the internal hd test pattern genera- tor, whether it is the lines of the cross hatch pattern or the uniform field test pattern. they are not functional as color controls on external pixel data input. for this purpose, the rgb matrix is used. the standard used for the values for y and the color difference signals to obtain white, black, and the saturated primary and complementary colors conforms to the itu-r bt.601-4 standard. table vii shows sample color values to be programmed into the color registers when output standard selection is set to eia 770.2. table vii. sample color values for eia770.2 output standard selection sample color y value cr value cb value white 235 (eb) 128 (80) 128 (80) black 16 (10) 128(80) 128 (80) red 81 (51) 240 (f0) 90 (5a) green 145 (91) 34 (22) 54 (36) blue 41 (29) 110 (6e) 240 (f0) yellow 210 (d2) 146 (92) 16 (10) cyan 170 (aa) 16 (10) 166 (a6) magenta 106 (6a) 222 (de) 202 (ca) hd rgb matrix [subaddress 03h?9h] when the programmable rgb matrix is disabled [address 02h, bit 3], the internal rgb matrix takes care of all ycrcb to yprpb or rgb scaling according to the input standard programmed into the device. when the programmable rgb matrix is enabled, the color components are converted according to the 1080i standard [smpte 274m]: yrgb cb b y cr r y '. '. '. ' '[./( . )](' ') '[./( . )](' ') =++ =? ? =? ? 0 2126 0 7152 0 0722 05 10 0722 05 10 2126 this is reflected in the preprogrammed values for gy = 138bh, gu = 93h, gv = 3b, bu = 248h, rv = 1f0. if another input standard is used, the scale values for gy, gu, gv, bu, and rv have to be adjusted according to this input standard. the user must consider that the color component con- version might use different scale values. for example, smpte 293m uses the following conversion: yrgb cb b y cr r y '. '. '. ' '[./( . )](' ') '[./( . )](' ') =++ =? ? =? ? 0 299 0 587 0 114 05 1 0 114 05 1 0 299 the programmable rgb matrix can be used to control the hd output levels in cases where the video output does not confirm to standards due to altering the dac output stages such as termination resistors. the programmable rgb matrix is used for external hd data and is not functional when the hd test pattern is enabled. programming the rgb matrix the rgb matrix should be enabled [address 02h, bit 3], the output should be set to rgb [address 02h, bit 5], sync on prpb should be disabled [address 15h, bit 2], and sync on rgb is optional [address 02h, bit 4]. gy at addresses 03h and 05h controls the output levels on the green signal, bu at 04h and 08h the blue signal output levels, and rv at 04h and 09h the red output levels. to control yprpb output levels, yprpb output should be enabled [address 02h, bit 5]. in this case, gy [address 05h; address 03, bit 0?] is used for the y output, rv [address 09h; address 04, bit 0?] is used for the pr output, and bu [address 08h; address 04h, bit 2?] is used for the pb output. if rgb output is selected, the rgb matrix scaler uses the fo llowing equations: ggyygu pb gv bgyy bu pb rgyyrv =++ =+ =+ pr pr if yprpb output is selected, the following equations are used: ygyy ubupb vrv = = = pr on power-up, the rgb matrix is programmed with default values. table viii. rgb matrix default values address default 03h 03h 04h f0h 05h 4eh 06h 0eh 07h 24h 08h 92h 09h 7ch when the programmable rgb matrix is not enabled, the ADV7330 automatically scales ycrcb inputs to all standards supported by this part. sd luma and color control [subaddresses 5ch, 5dh, 5eh, 5fh] sd y scale, sd cr scale, and sd cb scale are 10-bit wide control registers to scale the y, u, and v output levels. each of these registers represents the value required to scale the u or v level from 0.0 to 2.0, and the y level from 0.0 to 1.5 of its initial level. the value of these 10 bits is calculated using the following equation: yu or v scalar value scale factor ,, = 512 for example: scale factor = 1.18 y, u, or v scalar value = 1.18 512 = 665.6 y, u, or v scalar value = 665 ( rounded to the nearest integer ) y, u, or v scalar value = 1010 0110 01 b address 5ch, sd lsb register = 15h address 5dh, sd y scale register = a6h address 5eh, sd v scale register = a6h address 5fh, sd u scale register = a6h
rev. b ADV7330 ?1 sd hue adjust value [subaddress 60h] the hue adjust value is used to adjust the hue on the composite and chroma outputs. these eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. the ADV7330 provides a range of 22.5 incre- ments of 0.17578125 . for normal operation (zero adjustment), this register is set to 80h. ffh and 00h represent the upper and lower limits (respectively) of adjustment attainable. (hue adjust) [ ] = 0.17578125 (hcrd?28), for positive hue adjust value. for example, to adjust the hue by +4 , write 97h to the hue adjust value register: 4 0 17578125 128 105 97 . * ? ? ? ? ? ? += = dh * rounded to the nearest integer to adjust the hue by ? , write 69h to the hue adjust value register: ? ? ? ? ? ? ? += = 4 0 17578125 128 105 69 . * dh * rounded to the nearest integer sd brightness control [subaddress 61h] the brightness is controlled by adding a programmable setup level onto the scaled y data. this brightness level may be added onto the scaled y data. for ntsc with pedestal, the setup can vary from 0 ire to 22.5 ire. for ntsc without pedestal and pal, the setup can vary from ?.5 ire to +15 ire. the brightness control register is an 8-bit wide register. seven bits of this 8-bit register are used to control the brightness level. this brightness level can be a positive or negative value. for example: standard: ntsc with pedestal. to add +20 ire brightness level, write 28h to address 61h, sd brightness. [] [ [[ ] ]] sd brightnessvalue h irevalue h hhh = = = = 2 015631 20 2 015631 40 31262 28 . .. standard: pal. to add ? ire brightness level, write 72h to address 61h, sd brightness. irevalue b bh [] = [] = [] = [] = [] = 2 015631 72 015631 14 109417 0001110 0001110 1110010 72 . .. into twos complement table ix. brightness control values * setup setup level in level in setup ntsc with ntsc no level in sd pedestal pedestal pal brightness 22.5 ire 15 ire 15 ire 1eh 15 ire 7.5 ire 7.5 ire 0fh 7.5 ire 0 ire 0 ire 00h 0 ire ?.5 ire ?.5 ire 71h * values in the range of 3fh to 44h might result in an invalid output signal. sd brightness detect [subaddress 7ah] the ADV7330 allows monitoring of the brightness level of the incoming video data. brightness detect is a read-only register. double buffering [subaddress 13h, bit 7; subaddress 48h, bit 2] double-buffered registers are updated once per field on the falling edge of the vsync signal. double buffering improves the overall performance since modifications to register settings will not be made during active video, but take effect on the start of the active video. double buffering can be activated on the following hd registers: hd gamma a and gamma b curves, and hd cgms registers. double buffering can be activated on the following sd registers: sd gamma a and gamma b curves, sd y scale, sd u scale, sd v scale, sd brightness, sd closed captioning, and sd macrovision bits 5?. ntsc without pedestal no setup value added positive setup value added 100 ire 0 ire negative setup value added ?7.5 ire +7.5 ire figure 30. examples of brightness control values
rev. b ?2 ADV7330 in case b, the video outpu t signal is reduced. the absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. the overall gain of the signal is reduced from the reference signal. the range of this feature is specified for 7.5% of the nominal output from the dacs. for example, if the output current of the dac is 4.33 ma, the dac tune feature can change this output current from 4.008 ma (?.5%) to 4.658 ma (+7.5%). the reset value of the vid_out_ctrl registers is 00h nominal dac output current. table x is an example of how the output current of the dacs varies for a nominal 4.33 ma output current. table x. dac current register 0ah or 0bh (ma) % gain 0100 0000 (40h) 4.658 7.5000 0011 1111 (3fh) 4.653 7.3820 0011 1110 (3eh) 4.648 7.3640 ... ... ... ... ... ... 0000 0010 (02h) 4.43 0.0360 0000 0001 (01h) 4.38 0.0180 0000 0000 (00h) 4.33 0.0000 (i 2 c reset value, nominal) 1111 1111 (ffh) 4.25 ?.0180 1111 1110 (feh) 4.23 ?.0360 ... ... ... ... ... ... 1100 0010 (c2h) 4.018 ?.3640 1100 0001 (c1h) 4.013 ?.3820 1100 0000 (c0h) 4.008 ?.5000 programmable dac gain control dacs a, b, and c are controlled by reg 0b. the i 2 c control registers will adjust the output signal gain up or down from its absolute level. case b 700mv 300mv negative gain programmed in dac output level registers, subaddress 0ah, 0bh case a gain programmed in dac output level registers, subaddress 0ah, 0bh 700mv 300mv figure 31. programmable dac gain?ositive and negative gain in case a, the video output signal is gained. the absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. the overall gain of the signal is increased from the reference signal.
rev. b ADV7330 ?3 gamma correction [subaddress 24h?7h for hd, subaddress 66h?9h for sd] gamma correction is available for sd and hd video. for each standard there are 20 8-bit wide registers. they are used to program the gamma correction curves a and b. hd gamma curve a is programmed at addresses 24h?dh, hd gamma curve b at 2eh?7h. sd gamma curve a is programmed at addresses 66h?fh, sd gamma curve b at addresses 70h?9h. generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the crt). it can also be applied wher ever nonlinear processing is used. gamma correction uses the function signal signal out in = () where = gamma power factor. gamma correction is performed on the luma data only. the user has the choice to use two different curves, curve a or curve b. at any one time, only one of these curves can be used. the response of the curve is programmed at 10 predefined locations. in changing the values at these locations, the gamma curve can be modified. between these points, linear interpolation is used to generate intermediate values. considering the curve to have a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, 224. locations 0, 16, 240, and 255 are fixed and cannot be changed. location 0 0 50 100 150 200 250 300 50 100 150 200 250 0.5 signal input gamma corrected amplitude signal output gamma correction block output to a ramp input figure 32. signal input (ramp) and signal output for gamma 0.5 for the length of 16 to 240, the gamma correction curve has to be calculated as follows: yx = where: y = gamma corrected output x = linear input signal = gamma power factor to program the gamma correction registers, the seven values for y have to be calculated using the following formula: y x n n = ? () ? ? ? ? ? ? ? ? ? () + ? () 16 240 16 240 16 16 where: x (n?6) = value for x along x-axis at points n = 24, 32, 48, 64, 80, 96, 128, 160, 192 or 224 y n = value for y along the y-axis, which has to be written into the gamma correction register for example: y 24 = [(8 / 224) 0.5 224] + 16 = 58 * y 32 = [16 / 224) 0.5 224] + 16 = 76 * y 48 = [(32 / 224) 0.5 224] + 16 = 101 * y 64 = [(48 / 224) 0.5 224] + 16 =120 * y 80 = [(64 / 224) 0.5 224] + 16 =136 * y 96 = [(80 / 224) 0.5 224] + 16 = 150 * y 128 = [(112 / 224) 0.5 224] + 16 = 174 * y 160 = [(144 / 224) 0.5 224] + 16 = 195 * y 192 = [(176 / 224) 0.5 224] + 16 = 214 * y 224 = [(208 / 224) 0.5 224] + 16 = 232 * * rounded to the nearest integer the gamma curves in figure 32 and 33 are examples only; any user defined curve is acceptable in the range of 16?40. location 0 0 50 100 150 200 250 300 50 100 150 200 250 gamma corrected amplitude gamma correction block to a ramp input for various gamma values 0.3 0.5 1.5 1.8 signal input figure 33. signal input (ramp) and selectable gamma output curves
rev. b ?4 ADV7330 frequency (mhz) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 filter a response (gain ka) frequency (mhz) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 filter b response (gain kb) frequency (mhz) magnitude response (linear scale) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 024681012 input signal: step frequency response in sharpness filter mode with ka = 3 and kb = 7 sharpness and adaptive filter control block figure 34. sharpness and adaptive filter control block hd sharpness filter control and adaptive filter control [subaddress 20h, 38h?dh] there are three filter modes available on the ADV7330: sharp- ness filter mode and two adaptive filter modes. hd sharpness filter mode to enhance or attenuate the y signal in the frequency ranges shown in the figures below, the following register settings must be used: hd sharpness filter must be enabled and hd adaptive filter enable must be set to disabled. to select one of the 256 individual responses, the according gain values for each filter, which range from ? to +7 , must be pro- grammed into the hd sharpness filter gain register at address 20h. hd adaptive filter mode the hd adaptive filter threshold a, b, c registers, the hd adaptive filter gain 1, 2, 3 registers, and the hd sharpness filter gain register are used in adaptive filter mode. to activate the adaptive filter control, hd sharpness filter must be enabled and hd adaptive filter gain must be enabled. the derivative of the incoming signal is compared to the three programmable threshold values: hd adaptive filter threshold a, b, c. the recommended threshold range is from 16?35, although any value in the range of 0?55 can be used. the edges can then be attenuated with the settings in hd adaptive filter gain 1, 2, 3 registers and hd sharpness filter gain register. according to the settings of the hd adaptive filter mode con- trol, there are two adaptive filter modes available: 1. mode a is used when adaptive filter mode is set to 0. in this case, filter b (lpf) will be used in the adaptive filter block. also, only the programmed values for gain b in the hd sharpness filter gain, hd adaptive filter gain 1, 2, 3 are applied when needed. the gain a values are fixed and cannot be changed. 2. mode b is used when adaptive filter gain is set to 1. in this mode a cascade of filter a and filter b is used. both settings for gain a and gain b in the hd sharpness filter gain, hd adaptive filter gain 1, 2, 3 become active when needed.
rev. b ADV7330 ?5 f e d a b c 1 r4 r2 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 9.99978ms r2 r1 1 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 9.99978ms figure 35. hd sharpness filter control with different gain settings for hs sharpness filter gain value hd sharpness filter and adaptive filter application examples hd sharpness filter application the hd sharpness filter can be used to enhance or attenuate the y video output signal. the following register settings were used to achieve the results shown in the figures below. input data was generated by an external signal source. table xi. register reference in address setting figure 35 00h fch 01h 10h 02h 20h 10h 00h 11h 81h 20h 00h a 20h 08h b 20h 04h c 20h 40h d 20h 80h e 20h 22h f the effect of the sharpness filter can also be seen when using the internally generated cross hatch pattern. table xii. address register setting 00h fch 01h 10h 02h 20h 10h 00h 11h 85h 20h 99h in toggling the sharpness filter enable bit [address 11h, bit 8], it can be seen that the line contours of the crosshatch pattern change their sharpness.
rev. b ?6 ADV7330 adaptive filter control application figures 36 and 37 show a typical signal to be processed by the adaptive filter control block. : 692mv @: 446mv : 332ns @: 12.8ms figure 36. input signal to adaptive filter control : 692mv @: 446mv : 332ns @: 12.8ms figure 37. output signal after adaptive filter control the following register settings were used to obtain the results shown in figure 37, i.e., to remove the ringing on the y signal. input data was generated by an external signal source. table xiii. address register setting 00h fch 01h 10h 02h 20h 10h 00h 11h 81h 15h 80h 20h 00h 38h ach 39h 9ah 3ah 88h 3bh 28h 3ch 3fh 3dh 64h all other registers are set as normal. when changing the adaptive filter mode to mode b [address 15h, bit 6], the following output can be obtained: : 674mv @: 446mv : 332ns @: 12.8ms figure 38. output signal from adaptive filter control the adaptive filter control can also be demonstrated using the internally generated crosshatch test pattern and toggling the adaptive filter control bit [address 15h, bit 7]. table xiv. address register setting 00h fch 01h 10h 02h 20h 10h 00h 11h 85h 15h 80h 20h 00h 38h ach 39h 9ah 3ah 88h 3bh 28h 3ch 3fh 3dh 64h
rev. b ADV7330 ?7 sd digital noise reduction [subaddress 63h, 64h, 65h] dnr is applied to the y data only. a filter block selects the high frequency, low amplitude components of the incoming signal [dnr input select]. the absolute value of the filter output is compared to a programmable threshold value ['dnr threshold control]. there are two dnr modes available: dnr mode and dnr sharpness mode. in dnr mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. a programmable amount [coring gain border, coring gain data] of this noise signal will be subtracted from the original signal. in dnr sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. otherwise, if the level exceeds the threshold now being identified as a valid signal, a fraction of the signal [coring gain border, coring gain data] will be added to the original signal in order to boost high frequency components and to sharpen the video image. in mpeg systems, it is common to process the video information in blocks of 8 pixels 8 pixels for mpeg2 systems, or 16 pixels 16 pixels for mpeg1 systems [block size control]. dnr can be applied to the resulting block transition areas, which are known to contain noise. generally, the block transition area contains two pixels. it is possible to define this area to contain four pixels [border area]. block size control border area block offset coring gain data coring gain border gain dnr control filter output > threshold? input filter block filter output < threshold dnr out + + main signal path add signal above threshold range from original signal dnr sharpness mode noise signal path y data input block size control border area block offset coring gain data coring gain border gain dnr control filter output < threshold? input filter block filter output > threshold dnr out main signal path subtract signal in threshold range from original signal dnr mode noise signal path y data input ? + figure 39. dnr block diagram it is also possible to compensate for variable block positioning or differences in ycrcb pixel timing with the use of the dnr block offset. the digital noise reduction registers are three 8-bit wide registers. they are used to control the dnr processing. coring gain border [address 63h, bits 3?] these four bits are assigned to the gain factor applied to border areas. in dnr mode, the range of gain values is 0 to 1 in increments of 1/8. this factor is applied to the dnr filter output, which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter output, which lies above the threshold range. the result is added to the original signal. coring gain data [address 63h, bits 7?] these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode, the range of gain values is 0 to 1 in increments of 1/8. this factor is applied to the dnr filter output, which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter output, which lies above the threshold range. the result is added to the original signal. oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo dnr27 ? dnr24 = 01h offset caused by variations in input timing apply border coring gain apply data coring gain figure 40. dnr block offset control dnr threshold [address 64h, bits 5?] these six bits are used to define the threshold value in the range of 0 to 63. the range is an absolute value. border area [address 64h, bit 6] in setting this bit to a logic 1, the block transition area can be defined to consist of four pixels. if this bit is set to a logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (n tsc) 8 8 pixel block 8 8 pixel block 2 pixel border data figure 41. dnr border area
rev. b ?8 ADV7330 block size control [address 64h, bit 7] this bit is used to select the size of the data blocks to be processed. setting the block size control function to a logic 1 defines a 16 pixel 16 pixel data block and a logic 0 defines an 8 pixel 8 pixel data block, where one pixel refers to two clock cycles at 27 mhz. dnr input select control [address 65h, bit 2?] three bits are assigned to select the filter that is applied to the incoming y data. the signal that lies in the pass band of the selected filter is the signal that will be dnr processed. figure 42 shows the filter responses selectable with this control. filter c filter b filter a filter d frequency (hz) 0 012 3 456 0.2 0.4 0.6 magnitude 0.8 1.0 figure 42. dnr input select dnr mode control [address 65h, bit 4] this bit controls the dnr mode selected. a logic 0 selects dnr mode, a logic 1 selects dnr sharpness mode. dnr works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. in dnr mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. the threshold is set in dnr register 1. when dnr sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. the overall effect is that the signal will be boosted (similar to using extended ssaf filter). block offset control [address 65h, bits 7?] four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. consider the coring gain positions fixed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. sd active video edge [subaddress 42h, bit 7] when the active video edge is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled in such a way that maximum transitions on these pixels are not possible. the scaling factors are 1/8, 1/2, and 7/8. all other active video passes through unprocessed. sav/eav step edge control the ADV7330 has the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing. an algorithm monitors sav and eav and governs when the edges are too fast. the result will be reduced ringing at the start and end of active video for fast transitions. subaddress 42h, bit 7 = 1 enables this feature. 100 ire 0 ire 100 ire 12.5 ire 87.5 ire 0 ire 50 ire luma channel with ac tive video edge disabled luma channel with a ctive video edge enabled figure 43. example for active video edge functionality
rev. b ADV7330 ?9 volts 024 f2 l135 6810 12 ire:flt ?50 0 0 50 100 0.5 figure 44. address 42h, bit 7 = 0 volts 02 ?2 4 6 8 10 12 f2 l135 ire:flt ?50 0 50 100 0 0.5 figure 45. address 42h, bit 7 = 1
rev. b ?0 ADV7330 board design and layout considerations dac termination and layout considerations the ADV7330 contains an on-board voltage reference. the v ref pin is normally terminated to v aa through a 0.1 f capacitor when the internal v ref is used. alternatively, the ADV7330 can be used with an external v ref (ad1580). the rset resistors connected between the r set pin and agnd are used to control the full-scale output current and therefore the dac voltage output levels. for full-scale output, r set m ust have a value of 3040 ? . the r set values should not be changed. r load has a value of 300 ? for full-scale output. video output buffer and optional output filter output buffering on all three dacs is necessary in order to drive output devices, such as sd or hd monitors. analog devices produces a range of suitable op amps for this application, such as the ad8061. more information on line driver buffering circuits is given in the relevant op amp data sheets. an optional analog reconstruction low-pass filter (lpf) may be required as an anti-imaging filter if the ADV7330 is connected to a device that requires this filtering. the filter specifications vary with the application. table xv. external filter requirements cutoff frequency attenuation application oversampling (mhz) ?0 db @ (mhz) sd 2 >6.5 20.5 sd 16 >6.5 209.5 ps 1 >12.5 14.5 ps 8 >12.5 203.5 hdtv 1 >30 44.25 hdtv 2 >30 118.5 table xvi shows possible output rates from the ADV7330. table xvi. input mode pll output address 01h, bit 6? address 00h, bit 1 rate sd off 27 mhz (2 ) on 216 mhz (16 ) ps off 27 mhz (1 ) on 216 mhz (8 ) hdtv off 74.25 mhz (1 ) on 148.5 mhz (2 ) 560 600 3 4 1 22pf 600 dac output 75 bnc output 10 h 560 figure 46. example for output filter for sd, 16 oversampling 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?30 ?60 ?90 ?120 ?150 ?180 ?210 ?240 1m 10m 100m gain (db) frequency (hz) circuit frequency response 1g group delay (sec) phase (deg) magnitude (db) 21n 18n 15n 12n 9n 6n 3n 0 24n figure 47. filter plot for output filter for sd, 16 oversampling
rev. b ADV7330 ?1 560 3 4 1 6.8pf 600 6.8pf 600 dac output 75 bnc output 4.7 h 560 figure 48. example output filter for ps, 8 oversampling 82pf 33pf 75 dac output 220nh 470nh 500 3 4 1 bnc output 500 300 3 4 1 75 figure 49. example output filter for hdtv, 2 oversampling 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1m 10m 100m 1g frequency (hz) circuit frequency response magnitude (db) group delay (sec) phase (deg) gain (db) 320 240 160 80 0 ?80 ?160 ?240 480 400 14n 12n 10n 8n 6n 4n 2n 0 18n 16n figure 50. filter plot for output filter for ps, 8 oversampling 0 ?50 ?40 ?30 ?20 480 360 240 120 0 ?120 ?240 18n 15n 12n 9n 6n 3n 0 ?10 ?60 1m 10m 100m 1g frequency (hz) circuit frequency response phase (deg) magnitude (db) gain (db) group delay (sec) figure 51. example for output filter hdtv, 2 oversampling pc board layout considerations the ADV7330 is optimally designed for low noise performance, both radiated and conducted noise. to complement the excellent noise performance of the ADV7330, it is imperative that great care be given to the pc board layout. the layout should be optimized for lowest noise on the ADV7330 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and agnd, v dd and dgnd, and v dd_io and gnd_io pins should be kept as short as possible to minimized inductive ringing. it is recommended that a 4-layer printed circuit board is used with power and ground planes separating the layer of the signal carrying traces of the components and solder-side layer. com- ponent placement should be carefully considered in order to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry. there should be a separate analog ground plane and a separate digital ground plane. power planes should encompass a digital power plane and an analog power plane. the analog power plane should contain the dacs and all associated circuitry, v ref circuitry. the digital power plane should contain all logic circuitry. the analog and digital power planes should be individually con- nected to the common power plane at one single point through a suitable filtering device, such as a ferrite bead. dac output traces on a pcb should be treated as transmission lines. it is recommended that the dacs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). the dac termi- nation resistors should be placed as close as possible to the dac outputs and should overlay the pcb? ground plane. as well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry. to avoid crosstalk between the dac outputs, it is recommended to leave as much space as possible between the tracks of the individual dac output pins. the addition of ground tracks between outputs is also recommended. supply decoupling noise on the analog power plane can be further reduced by the use of decoupling capacitors. optimum performance is achieved by the use of 10 nf and 0.1 f ceramic capacitors. each group of v aa , v dd , or v dd_io pins should be individually decoupled to ground. this should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. a 1 f tantalum capacitor is recommended across the v aa supply in addition to 10 nf ceramic capacitor. see figure 52.
rev. b ?2 ADV7330 digital signal interconnect the digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the ADV7330 should be avoided to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane. analog signal interconnect the ADV7330 should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. for optimum performance, the analog outputs should each be source and load terminated, as shown in figure 52. the termination resistors should be as close as possible to the ADV7330 to minimize reflections. for optimum performance, it is recommended that all decoupling and external components relating to ADV7330 be located on the same side of the pcb and as close as possible to the ADV7330. any unused inputs should be tied to ground. 5k v dd_io 5k v dd_io comp 36 v aa 41 v dd v dd_io 1 ADV7330 i 2 c 19 hsync_o/p 50 vsync_o/p 49 blank_o/p 48 hsync_i/p 23 vsync_i/p 24 blank_i/p 25 reset 33 clkin 32 ext_lf 34 unused inputs should be grounded c0?c7 y0?y7 v aa 4.7 f + 4.7k 820pf 3.9nf v aa gnd_ io 64 agnd 40 dgnd 2, 11, 14, 15, 51?55, 57?63 i 2 c bus 10nf 0.1 f 10nf 0.1 f 10, 56 v dd_io v dd 10nf 1 f v aa + 0.1 f power supply decoupling for each power supply group v aa v dd_io dac a 39 300 cvbs/green/y dac b 38 300 luma/blue/pb dac c 37 300 chroma/red/pr v ref 46 100nf 1.1k v aa recommended external ad1580 for optimum performance sclk 22 100 sda 21 alsb 20 r set 35 3040 selection here determines device address 5k v dd_io 680 5k 100 figure 52. ADV7330 circuit layout
rev. b ADV7330 ?3 appendix 1?opy generation management system hd cgms data registers 2? [subaddress 21h, 22h, 23h] hd cgms is available in 525p mode only, conforming to ?gms-a eia-j cpr1204-1, transfer method of video id information using vertical blanking interval (525p system), march 1998? and iec61880, 1998, video systems (525/60) video and accompanied data using the vertical blanking interval- analog interface. when hd cgms is enabled [subaddress 12h, bit 6 = 1], cgms data is inserted on line 41. the hd cgms data registers are to be found at address 21h, 22h, 23h. sd cgms data registers 2? [subaddress 59h, 5ah, 5bh] the ADV7330 supports copy generation management system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can be transmitted only when the ADV7330 is configured in ntsc mode. the cgms data is 20 bits long; the function of each of these bits is as shown below. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit; see figure 54. hd cgms data registers [subaddress 12h, bit 6] the ADV7330 supports copy generation management system (cgms) in hdtv mode (720p and 1080i) in accordance to eiaj cpr-1204-2. the hd cgms data registers are to be found at addresses 21h, 22h, and 23h. 720p system cgms data is applied to line 24 of the luminance vertical blanking interval. 1080i system cgms data is applied to line 19 and also on line 582 of the luminance vertical blanking interval. cgms crc functionality if sd cgms crc [address 59h, bit 4] or ps/hd cgms crc [subaddress 12h, bit 7] is set to logic 1, the last six bits, c19?14, w hich comprise the 6-bit crc check sequence, are calculated aut omatically on the ADV7330 based on the lower 14 bits (c0c 13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if sd cgms crc [address 59h, bit 4] or ps/hd cgms crc [subaddress 12h, bit 7] is set to logic 0, all 20 bits (c0?19) are output directly from the cgms registers (no crc calcu- lated, must be calculated by the user). function of cgms bits word 0? bits; word 1? bits; word 2? bits; crc 6 bits; crc polynomial = x 6 + x + 1 (preset to 111111). table xvii. bit function word0 1 0 b1 aspect ratio 16:9 4:3 b2 display format letterbox normal b3 undefined word0 b4, b5, b6 identification information about video and other signals (e.g., audio) word1 b7, b8, b9, b10 identification signal incidental to word 0 word2 b11, b12, b13, b14 iden tification signal and information in ci dental to word 0
rev. b ?4 ADV7330 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 crc sequence 21.2 s 0.22 s 22t ref 5.8 s 0.15 s 6t 0mv ?300mv 70% 10% t = 1/(f h 33) = 963ns f h = horizontal scan frequency t 30ns + 700mv bit1 bit2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bit20 figure 53. ps cgms waveform c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 crc sequence 49.1 s 0.5 s ref 11.2 s 0 ire ?40 ire +70 ire +100 ire 2.235 s 20ns figure 54. sd cgms waveform crc sequence c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 ref 4t 3.128 s 90ns 17.2 s 160ns 22 t t = 1/(f h 1650/58) = 781.93ns f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% + 700mv bit1 bit2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bit20 figure 55. hdtv 720p cgms waveform c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 crc sequence ref 4t 4.15 s 60ns 22.84 s 210ns 22 t t = 1/(f h 2200/77) = 1.038 s f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% + 700mv bit1 bit2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bit20 figure 56. hdtv 1080i cgms waveform
rev. b ADV7330 ?5 w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 active video r un-in se quence st art c ode 500mv 11.0 s 38.4 s 42.5 s figure 57. wss waveform diagram bit description bit 0?it 2 aspect ratio/format/position bit 3 odd parity check of bit 0 to bit 2 b0, b1, b2 b3 aspect ratio format position 00 01 4:3 full format n/a 10 00 14:9 letterbox center 01 00 14:9 letterbox top 11 01 16:9 letterbox center 00 10 16:9 letterbox top 10 11 >16:9 letterbox center 01 11 14:9 full format center 11 1 0 16:9 n/a n/a b4 0c amera mode 1f ilm mode b5 0 standard coding 1m otion adaptive color plus bit description b6 0n o helper 1m odulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0n o surround sound information 1 surround sound mode b12 reserved b13 reserved table xviii. function of wss bits appendix 2?d wide screen signaling [subaddress 59h, 5ah, 5bh] the ADV7330 supports wide screen signaling (wss) conform- ing to the standard. wss data is transmitted on line 23. wss data can be transmitted only when the ADV7330 is configured in pal mode. the wss data is 14 bits long, and the function of each of these bits is shown in table xvii. the wss data is preceded by a run-in sequence and a start code (see figure 57). if sd wss [address 59h, bit 7] is set to logic 1, it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 s from the falling edge of hsync ) is available for the insertion of video. it is possible to blank the wss portion of line 23 with subaddress 61h, bit 7.
rev. b ?6 ADV7330 appendix 3?d closed captioning [subaddress 51h?4h] the ADV7330 supports closed captioning conforming to the standard television synchronizing waveform for color transmis- sion. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by a logic 1 start bit. sixteen bits of data follow the start bit. these consist of two 8-bit bytes, seven data bits and one odd parity bit. the data for these bytes is stored in the sd closed captioning registers (address 53h?4h). the ADV7330 also supports the extended closed captioning operation, which is active during even fields and is encoded on scan line 284. the data for this operation is stored in the sd closed captioning registers (address 51h?2h). all clock run-in signals and timing to support closed captioning on lines 21 and 284 are generated automatically by the ADV7330. all pixel inputs are ignored during lines 21 and 284 if closed captioning is enabled. fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the ADV7330 uses a single buffering method. this means that the closed captioning buffer is only one byte deep; therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. the data must be loaded one line before (line 20 or line 283) it is output on lines 21 and 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which in turn will load the new data (two bytes) every field. if no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling . it is also important to load control codes, all of which are double bytes on line 21 or a tv will not recognize them. if there is a message like ?ello world?that has an odd number of characters, it is important to pad it out to even in order to get ?nd of caption?2-byte control code to land in the same field. s t a r t p a r i t y p a r i t y d0?d6 d0?d6 10.5 s 0.25 s 12.91 s 7 cycles of 0.5035mhz clock run-in reference color burst (9 cycles) frequency = f sc = 3.579545mhz amplitude = 40 ire 50 ire 40 ire 10.003 s 27.382 s 33.764 s byte 1 byte 0 two 7-bit + parity ascii characters (data) figure 58. closed captioning waveform, ntsc
rev. b ADV7330 ?7 appendix 4?est patterns the ADV7330 can generate sd and hd test patterns. ch2 200mv m 10.0 sa ch2 1.20v t 30.6000 s 2 t figure 59. ntsc color bars ch2 200mv m 10.0 sa ch2 1.21v t 30.6000 s 2 t figure 60. pa0l color bars ch2 100mv m 10.0 s ch2 even t 1.82380ms 2 t figure 61. ntsc black bar (?1 mv, 0 mv, +3.5 mv, +7 mv, +10.5 mv, +14 mv, +18 mv, +23 mv) ch2 100mv m 10.0 s ch2 even t 1.82600ms 2 t figure 62. pal black bar (?1 mv, 0 mv, +3.5 mv, +7 mv, +10.5 mv, +14 mv, +18 mv, +23 mv) ch2 200mv m 4.0 s ch2 even t 1.82944ms 2 t figure 63. 525p hatch pattern ch2 200mv m 4.0 s ch2 even t 1.84208ms 2 t figure 64. 625p hatch pattern
rev. b ?8 ADV7330 ch2 200mv m 4.0 s ch2 even t 1.82872ms 2 t figure 65. 525p field pattern ch2 200mv m 4.0 s ch2 even t 1.84176ms 2 t figure 66. 625p field pattern ch2 100mv m 4.0 s ch2 even t 1.82936ms 2 t figure 67. 525p black bar (?5 mv, 0 mv, +7 mv, +14 mv, +21 mv, +28 mv, +35 mv) ch2 100mv m 4.0 s ch2 even t 1.84176ms 2 t figure 68. 625p black bar (?5 mv, 0 mv, +7 mv, +14 mv, +21 mv, +28 mv, +35 mv)
rev. b ADV7330 ?9 the following register settings are used to generate a sd ntsc cvbs output on dac a: register subaddress setting 00h 10h 40h 10h 42h 40h 44h 40h 4ah 08h all other registers are set to normal/default. for pal cvbs output on dac a, the same settings are used except that subaddress = 40h and register setting = 11h. the following register settings are used to generate an sd ntsc black bar pattern output on dac a: register subaddress setting 00h 10h 02h 04h 40h 10h 42h 40h 44h 40h 4ah 08h all other registers are set to normal/default. for pal black bar pattern output on dac a, the same settings are used except that subaddress = 40h and register setting = 11h. the following register settings are used to generate a 525p hatch pattern on dac a: register subaddress setting 00h 10h 01h 10h 10h 40h 11h 05h 16h a0h 17h 80h 18h 80h all other registers are set to normal/default. for 625p hatch pattern on dac a, the same register settings are used except that subaddress = 10h and register setting = 50h. for a 525p black bar pattern output on dac a, the same settings are used as above except that subaddress = 02h and register setting = 24h. for 625p black bar pattern output on dac a, the same settings are used as above except that subaddress = 02h and register setting = 24h; and subaddress = 10h and register setting = 50h.
rev. b ?0 ADV7330 appendix 5?d timing modes [subaddress 4ah] mode 0 (ccir-656)?lave option (timing register 0 tr0 = x x x x x 0 0 0) the ADV7330 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pat- tern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. vsync_o/p , hsync_o/p , and blank_o/p (if not used) pins should be tied high during this mode. blank output is available. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data ( hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc /pal m system pal system y (525 lines/60hz) (625 lines/50hz) figure 69. sd slave mode 0
rev. b ADV7330 ?1 mode 0 (ccir-656)?aster option (timing register 0 tr0 = x x x x x 0 0 1) the ADV7330 generates h, v, and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir656 standard. the h bit is output on hsync_o/p , the v bit is output on blank_o/p , and the f bit is output on vsync_o/p pin. 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank figure 70. sd master mode 0 (ntsc) 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 figure 71. sd master mode 0 (pal)
rev. b ?2 ADV7330 mode 1?lave option (timing register 0 tr0 = x x x x x 0 1 0) in this mode, the ADV7330 accepts horizontal sync and odd/ even field signals. a transition of the field input when hsync_i/p is low indicates a new frame i.e., vertical retrace. the blank_i/p signal is optional. when the blank_i/p input is disabled, the ADV7330 automatically blanks all normally blank lines as per ccir-624. hsync is applied to the hsync_i/p pin, blank to the blank_i/p pin, and field to the vsync_i/p pin. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field field h sync_i/p b lank_i/p h sync_i/p b lank_i/p field figure 73. sd slave mode 1 (ntsc) analog video h f v figure 72. sd master mode 0, data transitions
rev. b ADV7330 ?3 mode 1?aster option (timing register 0 tr0 = x x x x x 0 1 1) in this mode, the ADV7330 can generate horizontal sync and odd/even field signals. a transition of the field output when hsync_o/p is low indicates a new frame i.e., vertical retrace. the blank signal is optional. pixel data is latched on the rising clock edge following the timing signal transitions. hsync is output on the hsync_o/p pin, blank on the blank_o/p pin, and field on the vsync_o/p pin. 622 623 624 625 1234 5 67 21 22 23 display vertical blank odd field even field field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 h sync_o/p b lank_o/p h sync_o/p b lank_o/p field figure 74. sd slave mode 1 (pal) field pixel data pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y h sync_o/p b lank_o/p figure 75. sd timing mode 1?dd/even field transitions master/slave
rev. b ?4 ADV7330 mode 2?lave option (timing register 0 tr0 = x x x x x 1 0 0) in this mode, the ADV7330 accepts horizontal and vertical sync signals. a coincident low transition of both hsync_i/p and vsync _i/p inputs indicates the start of an odd field. a vs ync _i/p low transition when hs ync _i/p is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the ADV7330 automatically blanks all normally blank lines as per ccir-624. hsync is input on the hsync _i/p pin, blank on the blank _i/p pin, and vsync on the vsync _i/p pin. 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h sync_i/p b lank_i/p vsync_i/p h sync_i/p b lank_i/p vsync_i/p figure 76. sd slave mode 2 (ntsc) 622 623 624 625 1234 5 67 21 22 23 display vertical blank odd field even field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 h sync_i/p b lank_i/p vsync_i/p h sync_i/p b lank_i/p vsync_i/p figure 77. sd slave mode 2 (pal)
rev. b ADV7330 ?5 mode 2?aster option (timing register 0 tr0 = x x x x x 1 0 1) in this mode, the ADV7330 can generate horizontal and vertical sync signals. a coincident low transition of both hsync_o/p and vsync_o/p out puts indicates the start of an odd field. a vsync_o/p low transition when hsync_o/p is high indicates the start of an even field. hsync is output on the hsync_o/p pin, blank on the blank_o/p pin, and vsync on the vsync_o/p pin. pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y pixel data h sync_o/p b lank_o/p vsync_o/p figure 78. sd timing mode 2?ven to odd field transition master/slave pal = 864 clock/2 ntsc = 858 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y cb h sync_o/p b lank_o/p vsync_o/p figure 79. sd timing mode 2?dd to even field transition master/slave
rev. b ?6 ADV7330 mode 3?aster/slave option (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the ADV7330 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync_i/p is high indicates a new frame, i.e., vertical retrace. the blank_i/p signal is optional. when the blank_i/p input is disabled, the ADV7330 automatically blanks all nor mally blank lines as per ccir-624. hsync is interfaced on hsync_i/p , blank on blank_i/p , vsync on vsync_i/p . 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field h sync_i/p b lank_i/p h sync_i/p b lank_i/p field field figure 80. sd timing mode 3 (ntsc)
rev. b ADV7330 ?7 622 623 624 625 1234 5 67 21 22 23 display vertical blank odd field even field h sync_i/p b lank_i/p h sync_i/p b lank_i/p field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field field display 320 figure 81. sd timing mode 3 (pal) appendix 6?d timing vertical blanking interval display 1124 1125 1 2 5 6 7 8 21 4 3 20 22 560 field 1 field 2 vertical blanking interval display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 h sync_i/p vsync_i/p h sync_i/p vsync_i/p figure 82. 1080i hsync and vsync input timing
rev. b ?8 ADV7330 appendix 7?ideo output levels hd yprpb output levels input code 940 64 eia-770.2, standard for y output voltage 300mv 700mv 700mv ctv v ctv v 960 64 eia-770.2, standard for pr/pb output voltage 512 figure 83. eia 770.2 standard output signals (525p/625p) 782mv 714mv 286mv 700mv ctv v ctv v input code 940 64 eia-770.1, standard for y output voltage 960 64 eia-770.1, standard for pr/pb output voltage 512 figure 84. eia 770.1 standard output signals (525p/625p) 300mv input code 940 64 eia-770.3, standard for y output voltage 700mv ctv v 700mv 600mv ctv v 960 64 eia-770.3, standard for pr/pb output voltage 512 figure 85. eia 770.3 standard output signals (1080i, 720p) 300mv 300mv 700mv 700mv ctv v ctv v input code 1023 64 y?output levels for full i/p selection output voltage 1023 64 pr/pb?output levels for full i/p selection output voltage input code figure 86. output levels for full i/p selection
rev. b ADV7330 ?9 300mv 300mv 300mv 700mv 700mv 550mv 550mv 700mv 550mv figure 87. hd rgb output levels 300mv 0mv 300mv 0mv 300mv 0mv 700mv 550mv 700mv 550mv 700mv 550mv figure 88. hd rgb output levels?gb sync enabled 300mv 300mv 300mv 700mv 700mv 550mv 550mv 700mv 550mv figure 89. sd rgb output levels?gb sync disabled 300mv 0mv 300mv 0mv 300mv 0mv 700mv 550mv 700mv 550mv 700mv 550mv figure 90. sd rgb output levels?gb sync enabled rgb output levels
rev. b ?0 ADV7330 yprpb output levels 160mv 220mv white yellow cyan green magenta red blue black 60mv 110mv 280mv 332mv figure 91. u levels?tsc 160mv 220mv white yellow cyan green magenta red blue black 60mv 110mv 280mv 332mv figure 92. u levels?al 1000mv white yellow cyan green magenta red blue black 1260mv 140mv 2000mv 2150mv 900mv figure 93. u levels?tsc 1000mv white yellow cyan green magenta red blue black 1260mv 140mv 2000mv 2150mv 900mv figure 94. u levels?al white yellow cyan green magenta red blue black 300mv figure 95. y levels?tsc white yellow cyan green magenta red blue black 300mv figure 96. y levels?al
rev. b ADV7330 ?1 ?50 0 f1 l76 0 10 20 30 40 50 s 60 50 0.5 100 volts ire:flt apl = 44.5% 525 line ntsc slow clamp to 0.00v at 6.77 s precision mode off synchronous sync = a frames selected 1 2 0 figure 97. ntsc color bars 75% volts 0 noise reduction: 15.05db apl needs sync-source! 525 line ntsc no filtering slow clamp to 0.00v at 6.72 s s precision mode off synchronous sync = b frames selected 1 2 10 20 f1 l76 30 40 50 60 ire:flt 50 ?50 0 0.4 0.2 0 ?0.2 ?0.4 figure 98. ntsc chroma
rev. b ?2 ADV7330 volts noise reduction: 15.05db apl = 44.3% 525 line ntsc no filtering slow clamp to 0.00v at 6.72 s s precision mode off synchronous sync = source frames selected 1 2 10 20 f2 l238 30 40 50 60 ire:flt 50 0 0 0.4 0.2 0.6 0 ?0.2 figure 99. ntsc luma volts noise reduction: 0.00db apl = 39.1% 625 line ntsc no filtering slow clamp to 0.00v at 6.72 s s precision mode off synchronous sound-in-sync off frames selected 1 2 3 4 10 020 l608 30 40 50 60 0.4 0.2 0.6 0 ?0.2 figure 100. pal color bars 75%
rev. b ADV7330 ?3 apl needs sync = source 625 line pal, no filtering slow clamp to 0.00v at 6.72 s s no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 10 20 30 40 50 60 0 0.5 ?0.5 figure 101. pal chroma volts apl needs sync = source 625 line pal, no filtering slow clamp to 0.00v at 6.72 s s no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 10 020 l575 30 40 50 60 70 0 0.5 figure 102. pal luma
rev. b ?4 ADV7330 f v h * f f 272t 4t * 1 4t 1920t eav code sav code digital active line 4 clock 4 clock 2112 2116 2156 2199 0 44 188 192 2111 0 0 0 0 0 0 0 0 f f f v h * c b c r c r y y * fvh = fvh and parity bits sav/eav: line 1?562: f = 0 sav/eav: line 563?1125: f = 1 sav/eav: line 1?20; 561?583; 1124?1125: v = 1 sav/eav: line 21?560; 584?1123: v = 0 for a field rate of 30hz: 40 samples for a field rate of 25hz: 480 samples input pixels analog waveform sample number smpte274m digital horizontal blanking ancillary data (optional) or blanking code 0 h datum figure 103. eav/sav input data timing diagram?mpte 274m y eav code ancillary data (optional) sav code digital active line 719 723 736 799 853 0 * fvh = fvh and parity bits sav: line 43?525 = 200h sav: line 1?42 = 2ac eav: line 43?525 = 274h eav: line 1?42 = 2d8 4 clock 4 clock 857 719 0 h datum digital horizontal blanking 0 0 0 0 0 0 0 0 c b c r c r y y f v h * smpte293m input pixels analog waveform sample number f f f f f v h * figure 104. eav/sav input data timing diagram?mpte 293m appendix 8?ideo standards
rev. b ADV7330 ?5 vertical blank 522 523 524 525 12567891213141516424344 active video active video figure 105. smpte 293m (525p) vertical blank active video active video 622 623 624 625 1 2 5 6 7 8 9 12 13 10 11 43 44 45 4 figure 106. itu-r bt.1358 (625p) 747 748 749 750 1 2 5 6 7 8 26 27 25 744 745 4 display 3 vertical blanking interval figure 107. smpte 296m (720p) display 1124 1125 1 2 5 6 7 8 21 4 3 20 22 560 field 1 display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 field 2 vertical blanking interval vertical blanking interval figure 108. smpte 274m (1080i)
rev. b c03750??/04(b) ?6 ADV7330 outline dimensions 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc 10.00 bsc sq 12.00 bsc sq pin 1 1.60 max seating plane 0.75 0.60 0.45 view a 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bcd revision history location page 7/04?ata sheet changed from rev. a to rev. b. changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5/04?ata sheet changed from rev. 0 to rev. a. changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 change to mode register 0, sd sync and hd sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 removed footnote 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 change to hd mode register 5, bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 removed footnote 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 change to register 43h, bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 change to figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 change to equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 changes to figures 105 and 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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