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high performance products 1 www.semtech.com revision 1/december 3, 2001 an1001 EPIC family product line system considerations most system designs are on a continuous path toward higher integration, with greater proprietary intellectual con- tent per ic, as a means to: improve overall system performance enhance system functionality differentiate one?s product from the competition. as a result, the number of applications for discrete logic is diminishing. however, the need for low level integration will never completely disappear. some functions cannot be integrated because: technology limitations: different functions may require diverse process technologies, which frequently cannot be integrated onto one die. practical pc board considerations: it may be difficult, or impossible, to place many large scale integration ics in the perfect location. it may therefore be necessary to distribute certain functions using small scale integration solutions. frequency considerations process geometries continue to shrink rapidly, enabling faster circuit operation. frequencies that were leading edge and highly impractical years ago are now quite common. this higher speed operation has yielded tremendous ben- efits in overall system performance. however, it has also created new problems that existing glue logic and ssi components are ill-suited to resolve. more specifically, as frequencies increase, the amount of timing variation that can be tolerated in multiple paths becomes smaller. historically, clock generation was treated carefully, with much attention paid to distributing a clean and stable clock signal throughout a system. data signals, on the other hand, were considered less important. as long as adequate setup and hold times at the destination were maintained, little more was required. in this example, the ics responsible for distributing the clock and data signals may suffer several nanoseconds of variation due to: 1) tpd: part to part 2) tpd: channel to channel (within a part) 3) tpd+/-: different propagation delays for a positive vs. negative transition 4) tr/f: rise / fall time mismatches 5) tpd vs. frequency, duty cycle, and pattern 6) tpd vs. environmental changes, particularly temperature and supply voltage 7) transmission line imperfections and mismatches. adding up all these error terms yields the total timing uncertainty. but as long as the relationship (total error) + ts + thold t holds true, the system will still function properly. a worst case system level error of several nanoseconds (~3 ns) is quite reasonable using multiple instances of most standard components. with a setup and hold time of ~2 ns each, a 100 mhz system works with several nanoseconds of margin. total error + ts + thold = ~3 ns + ~2 ns + ~2 ns 7 ns 10 ns general information data data example a: clk d clk t hol d ts f = 100mhz t = 10ns
2 www.semtech.com high performance products revision 1/december 3, 2001 an1001 general information (con?d) in in * c lk c lk* s el* s e l out0 out0* d d * q q * out1 out1* out2 out2* out3 out3* out4 out4* 0 1 however, consider a 500 mhz example. example b: f = 500 mhz, t = 2 ns, ts = 500 ps, thold = 500 ps this situation leaves only 1 ns for all remaining sources of timing error. using the same clock and data distribu- tion components, with a total error of ~3 ns, the sys- tem no longer functions. total error+ ts+ thold = ~3 ns+.5 ns + .5 ns 2 ns! there is no longer adequate setup and hold time. to address applications where e very pi coseconds c ounts, semtech offers the EPIC product line, consist- ing of three product families - the 15xx, 19xx, and 44xx. all three product families are optimized for high speed clock and data distribution applications in terms of: speed accuracy integration functionality speed and accuracy the EPIC product line is extremely fast and accurate. all three families operate up to 3 ghz while maintain- ing timing accuracy. all EPIC products have very accurate, tight, stable, and repeatable timing characteristics. the EPIC product line is designed to minimize any timing errors associated with: 1) part to part variation 2) channel to channel variation 3) rise / fall time mismatches 4) positive vs. negative transition propagation delays 5) changes in duty cycle, pattern, or frequency 6) environmental changes (voltage and temperature). functionality and integration the EPIC product lines support unusually high levels of integration via three techniques: 1) packaging - the 5 mm x 5 mm tqfp package has a very small footprint with very low pin inductance. 2) functional integration - each part can perform sev- eral functions traditionally implemented with distinct ics: a) level translation (wide voltage range input capability: ecl, pecl, and double swing output options) b) resynchronization (flip-flop and mux integrated) c) fanout (1:5, 1:9 available) d) synchronous enable / disable 3) on-chip terminations - the inclusion of current sources and resistors integrates many space con- suming passive components typically placed on the pcb. for further ecl/pecl termination techniques, refer to the applcation note an1003. the 15xx and 19xx product families are designed to buffer a high speed signal, resynchronize it (if required), and then distribute multiple identical versions of this signal to multiple destinations. sk15xx functional block diagram sk15xx, sk19xx functionality semtech ?EPIC family? product line
3 www.semtech.com high performance products revision 1/december 3, 2001 an1001 in in * c lk c lk* s el* s e l ou t 0 ou t 0 * ou t 1 ou t1* ou t 2 ou t2* ou t 3 ou t 3 * ou t 4 ou t4* ou t 5 ou t 5 * ou t 6 ou t 6 * ou t 7 ou t7* ou t 8 ou t 8 * d d * q q * 0 1 asychronous operation when used asychronously (sel = 1), in is a synchronous enable and clk is the input signal. with in = 1, clk passes directly and continuously to all output pins. with in = 0, all outputs will transition to a logical 0 (q = low, q* = high) after the next falling edge of clk. the outputs will remain low until after a falling edge of clk while in = 1. in is designed to allow signals to be enabled and dis- abled synchronously, with no glitches or runt pulses at the output during enable / disable transition time. the following truth table summarizes the 15xx and 19xx operation. sk15xx / 19xx truth table 15xx / 19xx default condition chart default conditions it is good practice to tie all unused inputs to a known, stable, and a valid voltage level. however, several sig- nals have internal pull up or pull down resistors and therefore, have a known state when left floating. the following chart summarizes the default conditions on the 15xx and 19xx inputs. l a n g i s e t a t s t l u a f e d e d o m * n i / n iw o l / h g i hd e l b a n e * l e s / l e sw o l / h g i hn o i t a r e p o s u o n o r h c n y s a * k l c / k l c l a n r e t n i o n s r o t s i s e r t a o l f t o n o d synchronous operation (sel = 0) asynchronous operation (w / synchronous enable) (sel = 1) clk in in = synchronous enable clk = data out <0-8> out <0-4> out <0-8> out <0-4> clk in in = data clk = clock sk15xx, sk19xx functionality (con ? d) sk19xx functional block diagram l e s n i k l c ) > 4 - 0 < , > 8 - 0 < ( t u o s t n e m m o c 0 0 0 1 0 1 n o i t a r e p o s u o n o r h c n y s . t u p n i a t a d a e k i l s n o i t c n u f n i f o e g d e g n i l l a f n o n o i t i s n a r t s t u p t u o . k l c 1 1 1 1 0 1 0 1 . n o i t a r e p o s u o n o r h c n y s a k l c , e l b a n e s u o n o r h c n y s a s i n i r o ( > 8 - 0 < t u o o t y l t c e r i d s e s s a p . > 4 - 0 < 10 0 > 8 - 0 < t u o . n o i t a r e p o s u o n o r h c y s a n o y l s u o n o r h c n y s w o l o g ) > 4 - 0 < r o ( . k l c f o e g e d g n i l l a f
4 www.semtech.com high performance products revision 1/december 3, 2001 an1001 input signal level conditions: sk15xx/sk19xx sk15xx, sk19xx functionality (con ? d) vcc vee 1.3v 3.3v or 5.2v 700 mv figure a: input swing figure b: output swing vcc vee 4.5v or 5.2v 1.9v 1.4v vcc vee 1.3v 3.3v or 5.2v 350 mv at destination (double termination) vil vil vih vih vcc vee min. 0.2v min. 2.0v figure c: output swing these devices accept a wide range of input levels. the input levels can be as low as 200 mv and as high as 4.3v peak-to-peak. refer to the data sheet for specific input levels.(see figure a for more de- tail.) output signal level conditions: figure b shows output signal levels for the following devices: sk1500, sk1503, sk1525/sk1900, sk1903, sk1925. figure d: output swing figure d shows output signal levels for the following devices: sk1502, sk1504, sk1527, sk1529/ sk1902, sk1904, sk1927, sk1929 figure c shows output signal levels for sk1501/ sk1901.
5 www.semtech.com high performance products revision 1/december 3, 2001 an1001 figure e: output swing vgg vee 7 00 mv 1.3v figure f: output swing vgg vee 1.3v 350 mv at destination (double termination) sk15xx, sk19xx functionality (con ? d) figure e shows output signal levels for sk1528, sk1530/ sk1928, sk1930. figure f shows output signal levels for the following de- vices: sk1526/sk1926.
6 www.semtech.com high performance products revision 1/december 3, 2001 an1001 every input and output is fully differential. single-ended operation is permitted, but overall accuracy may be infe- rior to a fully differential topology. all inputs are also wide voltage differential compliant, al- lowing a variety of input swings to come directly into the in 0 in 0* in1 in1* c l k in2 in2* in 3 in 3* ou t 0 ou t 0* ou t 1 ou t1 * ou t 2 ou t2 * ou t 3 ou t 3* d 1 0 1 0 1 0 d d* 1 0 c lk * s el * s e l en en* sk44xx functional block dia g ram sk44xx functionality the 44xx family has similar functionality to the 15xx and 19xx families, only the 44xx is designed for 1:1 buffer applications rather than fanout applications. asychronous buffer when used asynchronously (sel = 1), in ? in3 pass directly to out0 - out3. clk has no function. en is an asynchronous output enable common to all four outputs. s y nchronous operatio n as y nchronous operatio n out in clk sel en ou t in sel en differential inputs / outputs n e l e s > 3 - 0 < n i k l c > 3 - 0 < t u o s t n e m m o c 0xxx0 d e l b a s i d 11 0 x 0 n o i t a r e p o s u o n o r h c n y s a s e s s a p > 3 - 0 < n i > 3 - 0 < t u o o t y l t c e r i d 10 0 1 0 1 n o i t a r e p o s u o n o r h c n y s sychronous buffer when used synchronously (sel = 0), in0 ? in3 pass data inputs to the flip-flops, all clocked on the rising edge of the clk. en is an asynchronous output en- able common to all four outputs. the following truth table summarizes the 44xx opera- tion.
7 www.semtech.com high performance products revision 1/december 3, 2001 an1001 the 50 double termination output structure is opti- mized for applications with the following characteristics: a) series (or source) termination and parallel termination b) point to point routing of a different signal c) 50 transmission lines in this environment, the double termination output of- fers the smallest footprint solution for accurate signal distribution. note: the double termination output does not function correctly without a 100 termination resistor at the destination. 3) 50 source termination part. no translator is required for most (virtually all) different standard digital technologies. there is no headroom requirement on the inputs on a digital high vs. vcc or a digital low vs. vee. this is important because it allows the EPIC families to share a vcc and vee with a cmos asic and receive rail-to- rail swings without having any functional or perfor- mance degradations. sk44xx truth table differential inputs / outputs (con?d) the open emitter is the standard ecl output. it is flex- ible in that it supports point to point routing or daisy chain lines, a wide range of transmission line character- istic impedances, and a variety of termination schemes. refer to an1003 for ecl/pecl signal termination tech- niques. there are four basic output structures supported by the EPIC product line. each configuration is opti- mized for a specific transmission line topology in order to allow the maximum level of overall system level performance and integration. default conditions it is good practice to tie all unused inputs to a known, stable, valid voltage level. however, several signals have internal pull up or pull down resistors and, there- fore, have a known state when left floating. the fol- lowing chart summarizes the default conditions on the 44xx inputs. q q* l a n g i s e t a t s t l u a f e d e d o m * n i / n i l a n r e t n i o n s r o t s i s e r t a o l f t o n o d * k l c / k l c l a n r e t n i o n s r o t s i s e r t a o l f t o n o d * l e s / l e sw o l / h g i h s u o n o r h c n y s a n o i t a r e p o * n e / n ew o l / h g i he v i t c a s t u p t u o output configuration options 1) open emitter 2) double termination q zo 6 ma q* rext r t = 2* zo rext zo 6 ma q z o = 50 ? 50 ? 50 ? q* z o = 50 ? 8 ma 8 ma
8 www.semtech.com high performance products revision 1/december 3, 2001 an1001 the 50 source (or series) termination output struc- ture is optimized for applications with the following char- acteristics: a) point-to-point routing of differential signals (al though, it functions for single-ended applica- tions with q* left disconnected) b) 50 transmission lines this output configuration does not require any termi- nation resistor at the destination. in fact, it does not require any external components at all. it is suitable for high-speed data and clock distribu- tion, where double termination is not required. note: the source terminated output also works in the double termination environment. however, as a source termination it requires internal 8ma current source, and double termina- tion requires only 6ma, additional power is consumed with no corresponding performance gain. q zo 6 ma q* rext r t = 2* zo rext zo 6 ma 4) internal current sink (double termination) this output structure is a modified version of the 50 double termination output. accordingly, it is used in applications that require: 1) point-to-point routing of a differential signal 2) series and parallel termination. however, as the series termination resistors are not on-chip, this output should be selected in two specific cases: a) non-50 transmission lines. use appropriate external resistors to match the line impedance. b) ultra high fidelity applications, in situations where the source impedance and line imped ance must match extremely close, precision the 44xx family supports two distinct input options for the in<0-3> signals. 1) high impedance in in* this configuration is a standard high impedance input. it is flexible in that it can be used in: a) multiple destination (display chain), as well as point-to-point applications b) transmission line environments of a wide range of characteristic impedances (with the appropriate external termination scheme, see an1003) c) single-ended applications (with the appropriate vbb brought into clk*). 2) 100 termination in in* 100 ? input configuration options output configuration options (con?d)
9 www.semtech.com high performance products revision 1/december 3, 2001 an1001 input configuration options (con?d) the internal 100 parallel termination is optimized to provide superior integration and performance in appli- cations that require: a) differential signals b) point-to-point routing c) 50 transmission line environment. the inclusion of the termination resistors integrates four components normally implemented with off-chip discrete components, thus saving considerable pc board real estate. input signal level conditions: sk44xx vcc vee 1.3v 3.3v or 5.2v 700 mv figure h: output swing vcc vee 4.5v or 5.2v 1.9v 1.4v figure i: output swing vcc vee 1.65v 3.3v or 5.2v 350 mv at destination (double termination) figure j: output swing output signal level conditions figure g: input swing vil vil vih vih vcc vee min. 0.2v min. 2.0v these devices accept a wide range of input levels. the input levels can be as low as 200 mv and as high as 4.3v peak-to-peak. refer to the data sheet for spe- cific input levels. (see figure g for more detail.) figure h shows output signal levels for the following devices: sk4400, sk4410, sk4425, sk4435. figure i shows output signal levels for the following devices: sk4401, sk4411. figure j shows output signal levels for the following devices: sk4404, sk4414, sk4426, sk4430, sk4439, sk4440. figure k: output swing vgg vee 700 mv 1.3v figure k shows output signal levels for sk4436.
10 www.semtech.com high performance products revision 1/december 3, 2001 an1001 the junction temperature may be predicted by the equa- tion: t j = t a + ja * p d however, t j of any EPIC product will vary over a wide range, depending on the environment. the power con- sumption is a function of the total supply voltage (vcc - vee) and the particular output configuration (open emitter, series termination) selected. thermal resis- tance ja , is heavily dependent upon the particular cool- ing technique used. not all parts may be used reliable for all cooling schemes or power supply conditions. the EPIC prod- uct line is optimized to provide the most integration and performance for environments using either liquid (or cold plate) cooling, or air flow >300 lfpm. how- ever, the 15xx, 19xx and 44xx families all have sev- eral low power options which can be used with little or no forced cooling. the actual ja will be different for each particular envi- ronment. however, estimates of typical ja performance in several common cooling environments are provided. liquid cooling in the liquid cooling environment there is no airflow. all cooling is achieved via conduction through the top of the package into a cold plate as well as though the lead frame down into the power planes inside of the printed circuit board. thermal analysis die t j 19xx, 15xx, 44xx thermal compound air gap pad power plane pc board power plane cold plate t a heat flow vias the following assumptions are made: 1) the part is soldered to a multilayer pc board with internal power planes 2) the part is attached directly to the cold plate on the top side of the package. orthogonal air flow orthogonal air flow is an environment where cold air flows directly down to the top of the package. in this case, cooling is achieved via convection as the cold air absorbs the heat at the top of the package and carries the heat out on the side, as well as via conduction through the lead frame down into the power planes in- side the printed circuit board. this cooling scheme pro- duces the lowest thermal resistance for any air cooled scheme. the flowing assumptions are made: 1) the part is soldered to a multilayer pc board with internal power planes 2) no heat sink. in this environment, ja , 30 o c / watt.
11 www.semtech.com high performance products revision 1/december 3, 2001 an1001 thermal analysis (con?d) a j w o l f r i a m p f l 0 0 3 > m p f l 0 0 1 m p f l 0 5 transverse air flow this is a common technique where cooled air is forced along the top of the pc board. cooling is achieved via convection, as the cold air passing over the top of the package absorbs the heat and carries it away, as well as via conduction through the lead frame down into the power planes inside the printed circuit board. the following assumptions are made: 1) the part is soldered to a multilayered pc board with internal power planes 2) laminar air flow. die t j 19xx, 15xx, 44xx air gap pad vi as power plane pc board power plane heat flow in this environment: j a w o l f r i a 0 4 o w / cm p f l 0 0 3 > 0 0 1m p f l 0 5m p f l orthogonal air flow die t j 19xx, 15xx, 44x x air gap pad vi as power plane pc board power plane heat flow high pressure air
12 www.semtech.com high performance products revision 1/december 3, 2001 an1001 translation summary table y g o l o n h c e t n o i t a n i t s e d / e c r u o s t u o n a f d e r i u q e r s l e v e l y l p u s d e d n e m m o c e r m o r fo t5 : 19 : 11 : 1c c ve e vg g v , l t g , l t t , l c e v 8 . 1 / v 5 . 2 / v 3 . 3 l c e p v l , l t t v l , s o m c l t t1 0 5 11 0 9 11 0 4 4v 3 . 3 +v . 2 -a / n , l t g , l t t , l c e p v l v 8 . 1 / v 5 . 2 / v 3 . 3 l t t v l , s o m c l c e , 8 2 5 1 , 6 2 5 1 0 3 5 1 , 8 2 9 1 , 6 2 9 1 0 3 9 1 , 0 3 4 4 , 6 2 4 4 0 4 4 4 , 6 3 4 4 v 3 . 3 +v 3 . 3 -v 0 , l t g , l t t , l c e p v l v 8 . 1 / v 5 . 2 / v 3 . 3 l t t v l , s o m c l t t v l l t g , 8 2 5 1 , 6 2 5 1 0 3 5 1 , 8 2 9 1 , 6 2 9 1 0 3 9 1 , 0 3 4 4 , 6 2 4 4 0 4 4 4 , 6 3 4 4 v 3 . 3 + - r o v 2 - v 3 . 3 v 2 + s o m c v 8 . 1 , l t g , l t t v ll c e , 8 2 5 1 , 6 2 5 1 0 3 5 1 , 8 2 9 1 , 6 2 9 1 0 3 9 1 , 0 3 4 4 , 6 2 4 4 0 4 4 4 , 6 3 4 4 v 2 +v 3 . 3 -v 0 , l t g , l t t , l c e s o m c v 8 . 1 / v 5 . 2 / v 3 . 3 l c e p , 7 2 5 1 , 5 2 5 1 9 2 5 1 , 7 2 9 1 , 5 2 9 1 9 2 9 1 , 9 2 4 4 , 5 2 4 4 9 3 4 4 , 5 3 4 4 v 3 . 3 +v 3 . 3 -a / n contact information division headquarters 10021 willow creek road san diego, ca 92131 phone: (858) 695-1808 fax: (858) 695-2633 marketing group 1111 comstock street santa clara, ca 95054 phone: (408) 566-8776 fax: (408) 727-8994 semtech corporation high-performance products division

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