KS32C6100 risc microcontroller technical summary 1- 1 preliminary overview samsung ? s ks32c61 00 16/32-bit risc microcontroller provide s a cost -effective and high-performance microcontroller solution for laser beam printers (lbp) with pcl/pdl interpreters. to accelerate rast er image generation, the ks32c61 00 directly processes scanned image data for the laser printer engine. an ou tstanding feature of the ks32c61 00 is its cpu core, a 16/ 32-bit risc processor (arm7 tdmi ) designed by advanced risc machines, ltd. the arm7 tdmi core is a low-power, general-purpose, microprocessor macro- cell that was developed for use in application-specific and customer-specific integrated circuits. its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. the ks32c61 00 was developed using the arm7 tdmi core, 0.5 - m standard cells, and a data path compiler. most of the on-chip function blocks were designed using a hdl synthesizer. the ks32c61 00 has been fully verified in samsung s asic test environment. by providing a complete set of common system peripherals, the ks32c61 00 minimizes overall system costs and eliminates the need to configure additional components. the main integrated on-chip function blocks which are described in this document include: ? rom/sram /dram controller ? 4kbyte instruction /data cache ? three -channel dma controller ? uart/s er ial io ? parallel port interface controller (ppic) ? five 16-bit timers including tone generator and watch dog timer ? printer interface controller (pifc) ? graphic engine unit (geu) ? image functional unit including image expander, i mage rotator, vis and halftoner ? programmable i/o ports ? interrupt controller
KS32C6100 risc microcontroller technical summary 1- 2 preliminary features architecture ? completely integrated system for embedded applications, especially laser beam printers ? fully 16/ 32-bit risc architecture ? efficient and powerful arm7 tdmi cpu core ? 4-kbyte instruction/data cache ? external bus master mode support ? cost-effective jtag-based debug solution unified cache ? 4-kbyte unified cache ? 2-way set-associative configuration ? two non-cacheable data regions can be specified ? cache disable by software ? four-word depth write buffer system manager ? 256-mbyte virtually addressable space support ? 8 -bit, 16 -bit, or 32 -b it external bus support for rom, sram, dram, and external i/o ? separate address and control signals specially for dram access, and cas before ras refresh, dram self-refresh, fast page and edo dram access modes support ? progra mmable memory bank size and location definition to provide a flexible memory map. ? progra mmable memory access times ( 2 to 7 wait ing cycles) ? cost -effective memory -to-peripheral interface dma ? three -channel general-purpose dma controller ? me mory-to-memory, serial port - to /from- memory, parallel port-to/from- memory data transfers without cpu intervention ? run-len gth compression/decompression support for memory-to-memory data transfer in cdma channel ? initiated by software, peripherals or external dma request ? increment or decrement of source or de stination addresses, and 8-bit (byte) , 16-bit(half-word) or 32-bit (word) data transfer support uart /sio ? two-channel sio with dma-based or interrupt- based operat ion; supports 5-bit, 6-bit, 7-bit, or 8- bit serial data transmit/receive ? programmable baud rates ? loop back mode for testing ? infra -red (ir) tx/rx support parallel port interface controller ? dma-based or interrupt-based operation ? support ieee standard 1284 communication modes (compatibility mode, nibble mode, byte mode, and ecp mode) ? hardware support for rle data compression or decompression in ecp mode ? automatic hardware handshaking for forward or reverse data transfers in compatibility and ecp modes. timer/tone generator/watch dog timer ? five programmable 16-bit timers , including one tone generator and one watch dog timer ? watch dog timer output s upport for system reset ? interva l mode or toggle mode operation support for tone generator graphic engine unit (geu) ? hardware support for up to 256 bit block t ransfer ( bitblt) operations ? x-y coordinates support for source, pattern and destination data ? scanline transfer support to reduce image storage requirements ? source or pattern flipping ? band fault check support image functional block ? two and three-times image expanding function support ? 90/270 degree rotation support for 16x16 data block ? variable image scaling operation support ? halftoning operation support for gray-level image conversion
KS32C6100 risc microcontroller technical summary 1- 3 preliminary printer interface controller ? cost -effective, high-performance dma-based interface to the printer engine ? dedicate d dma for fast data transfers between page memory and the printer engine ? consecutive zero string (blank data) output for banded bit maps (no memory access required) ? queuing operation to facilitate smooth switching among data blocks of banded page memory ? pixel chopping mode support for lbp toner save ? dot shrinking mode support for fine-edged images printing ? video data/boundary polarity defining support ? two to four-times image expanding support i/o ports ? 16 programmable i/o ports ? each port pin can be configured individually as input, output, or i/o for a dedicated signal interrupts ? 27 interrupt sources (2 external interrupts included) ? normal or fast interrupt modes (irq, fiq) operating voltage range ? 4.75 to 5.25 volts operating frequency ? up-to 33mhz package type ? 208 -pin qfp
KS32C6100 risc microcontroller technical summary 1- 4 preliminary block diagram interrupt controller cpu (arm7tdmi) bus router uart/ serial i/o printer interface controller t i m e r 0 , 1 timers parallel port interface d m a 0 , 1 d m a 0 , 1 dma address decoder a d d r d a t a c n t r graphic engine unit i/o port controller system manager system bus controller bus arbitration bus interface rom/sram/dram controller image functional block i/d cache (4-kb) lbus figure 1-1. ks32c61 00 block diagram
KS32C6100 risc microcontroller technical summary 1- 5 preliminary pin assignments figure 1-2. ks32c61 00 pin assignments k s 3 2 c 6 1 0 0 2 0 8 q f p ( t o p v i e w ) g n d p a d g n d p p i p p d 0 p p d 1 p p d 2 p p d 3 p p d 4 p p d 5 p p d 6 p p d 7 n s e l e c t i n n s t r o b e n a u t o f d n i n i t i a l n a c k b u s y s e l e c t p e r r o r n f a u l t v d d p p i v d d p a d v d d c o r e e x t m r e q e x t m a c k e x t m n d l g n d p a d g n d c o r e n s c s n e c s 0 n e c s 1 n e c s 2 n e c s 3 n w e 0 n w e 1 n w e 2 n w e 3 n o e g n d p a d g n d c o r e x a 0 0 x a 0 1 x a 0 2 x a 0 3 x a 0 4 x a 0 5 v d d p a d x a 0 8 x a 0 9 x a 1 0 g n d p a d x a 0 6 x a 0 7 g n d p a d g n d c o r e x d 2 4 x d 2 3 x d 2 2 x d 2 1 x d 2 0 x d 1 9 x d 1 8 v d d p a d x d 1 7 x d 1 5 x d 1 6 x d 1 4 x d 1 3 x d 1 2 g n d p a d x d 1 1 x d 1 0 x d 0 9 x d 0 8 x d 0 7 x d 0 6 x d 0 5 v d d c o r e x d 0 4 x d 0 3 x d 0 2 x d 0 1 x d 0 0 n r c s 3 n r c s 2 n r c s 1 g n d c o r e g n d p a d n r c s 0 x a 2 3 x a 2 1 x a 2 2 x a 2 0 x a 1 9 x a 1 8 v d d c o r e v d d p a d x a 1 7 x a 1 6 x a 1 5 x a 1 4 x a 1 3 x a 1 2 x a 1 1 g n d p a d g n d c o r e c o m c l k g n d p a d c n p b s y c n p m s g c n e b s y c n e m s g v c l k 0 v c l k 1 n e n g p r q v d d p a d n e n g h s y n c v d d c o r e n c p u p s y n c n e n g r e a d y n c p u p r i n t v i d e o _ o u t g n d p a d g p i o 0 0 g p i o 0 1 g p i o 0 2 g p i o 0 3 g p i o 0 4 g p i o 0 5 g p i o 0 6 g p i o 0 7 v d d p a d v d d p a d g p i o 0 8 g p i o 0 9 g p i o 1 0 g p i o 1 1 g p i o 1 2 g p i o 1 3 g p i o 1 4 g p i o 1 5 g n d c o r e n r e s e t n r s t o t n r s t t m o d e n b k 0 h w v d d c o r e v d d p a d c l k s e l t d i t d o t m s g n d p a d m c l k g n d p a d t c k u c l k g n d p a d g n d c o r e s i o _ r x d s i o _ t x d r x d t x d d t r d s r n s w r 1 n s r d 1 n s w r 0 n s r d 0 v d d c o r e v d d p a d d a 1 2 d a 1 1 d a 1 0 d a 0 9 d a 0 8 d a 0 7 d a 0 6 g n d p a d d a 0 5 d a 0 4 d a 0 3 d a 0 2 d a 0 1 d a 0 0 n r a s 5 n r a s 4 n r a s 3 n r a s 2 n r a s 1 n r a s 0 n c a s 0 g n d c o r e g n d p a d n c a s 1 n c a s 2 n c a s 3 n d o e n d w e v d d p a d x d 3 1 x d 3 0 x d 2 7 x d 2 6 x d 2 5 g n d p a d x d 2 9 x d 2 8 1 5 6 1 5 7 2 0 8 1 5 2 5 3 1 0 4 1 0 5
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