View RSC-4128_2030182.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RSC-4128 speech recognition processor data sheet ? 2004 sensory inc. p/n 80-0206-j 1 general description the RSC-4128 represents sensory?s next generation speech and analog i/o mixed signal processor. the RSC-4128 is designed to bring advanced speech i/o features to cost sensitive embedded and consumer products. based on an 8-bit microcontroller, the rsc- 4128 integrates speech-optimized digital and analog processing blocks into a single chip solution capable of accurate speech recognition; high quality, low data-rate compressed speech; and advanced music. products can use one or all features in a single application. the RSC-4128 supports sensory speech? 7 technology, which includes advanced speech algorithms that add features and improve performance. capable of running both new hmm and enhanced neural network technologies, accuracy in all kinds of noise is dramatically improved. new speaker verification technology is perfect for voice password security applications that must work in noisy environments. new high quality compressed speech technology reduces data rates by 5 times. new 8 voice midi-compatible music includes drum tracks, effectively increasing instruments beyond 8. simultaneous music and speech rounds out the sensory speech? 7 technology. the RSC-4128 also supports the revolutionary capability of creating speaker independent recognition sets by simply typing in the desired recognition vocabulary! a few keystrokes creates a recognition set in seconds without the wait or cost of recording sessions to train the recognizer, speeding time to sales. a new and unique audio wakeup feature listens while the RSC-4128 is in power down mode. when an audio event such as a clap or whistle occurs, audio wakeup will wakeup the RSC-4128 for speech or application tasks. audio wakeup is perfect for battery applications that require continuous listening and long battery life. in addition to improved recognition performance, the RSC-4128 provides further on-chip integration of features. a complete speech i/o application can be built with as few additional parts as a clock crystal, speaker, microphone, and few resistors and capacitors. moreover, the RSC-4128 provides an unprecedented level of cost effective system-on-chip (soc) integration, enabling many applications that require dsp and/or audio processing. the RSC-4128 may be used as a general-purpose mixed signal processor platform for custom algorithms, technologies and applications. features full range of sensory speech? 7 capabilities enhanced word spotting capability (10 si or 4 sd words) in parallel noise robust speaker independent, dependent & continuous listening recognition speaker verification (svws) ? noise robust voice biometric security high quality, 3.7-7.8 kbps speech synthesis & sound effects with sensory ?sx? synthesis technology 8 voice midi-compatible music synthesis coincident with speech; drum track feature enables additional voices voice record & playback audio wakeup from sleep integrated single-chip solution 8-bit microcontroller romless, 128kbyte and 256kbyte rom options 16 bit adc, 10 bit dac and microphone pre-amplifier independent, programmable digital filter engine 4.8 kbytes total ram (256bytes ?user? application ram) five timers (3 gp, 1 watchdog, 1 multi tasking) twin-dma, vector math accelerator, and multiplier built-in analog comparator unit (4 inputs) external memory bus: 20-bit address(1mbyte), 8-bit data on chip storage for sd, sv, templates (10 templates) code security through no rom dump capability uses low cost 3.58mhz crystal (internal pll) low emi design for fcc and ce requirements 24 configur able i/o lines with 10 ma (typical) outputs fully nested interrupt structure with up to 8 sources optional real time clock long battery life 2.4 ? 3.6v operation 12ma (typical) operating current at 3v 2 low power modes; 1 a typical sleep current full suite of quick & powerful tools quick text-to-si (t2si) text entry to build noise robust si recognition sets ? low cost & push-button ? no recording! quick synthesis for push-button speech compression integrated development environment, c compiler, debugger & in circuit emulator from phyton, inc.
RSC-4128 data sheet 2 p/n 80-0206-j ? 2004 sensory inc. table of contents general de scripti on ............................................................................................................ ............................................................ 1 RSC-4128 ov erview .............................................................................................................. ......................................................... 4 speech tec hnologie s ............................................................................................................ ......................................................... 5 speech recognition............................................................................................................. ..................................................................................5 speaker verification........................................................................................................... ....................................................................................5 speech and music synthesis..................................................................................................... ............................................................................5 record and playback............................................................................................................ .................................................................................5 RSC-4128 arch itectu re .......................................................................................................... ......................................................... 6 reference sc hemati cs........................................................................................................... ......................................................... 8 using the RSC-4128 ............................................................................................................. ........................................................ 10 instruction set ................................................................................................................ ......................................................................................10 stack .......................................................................................................................... ..........................................................................................11 register ram................................................................................................................... ....................................................................................11 l1 vector accelerator/multiplier ............................................................................................... ............................................................................12 power and wakeup control ....................................................................................................... ..........................................................................12 general purpose i/o ............................................................................................................ ................................................................................13 memory addressing .............................................................................................................. ...............................................................................14 wait states.................................................................................................................... .......................................................................................17 on-chip rom .................................................................................................................... ..................................................................................18 oscillators .................................................................................................................... ........................................................................................18 clocks ......................................................................................................................... .........................................................................................19 timers/counters ................................................................................................................ ..................................................................................20 interrupts..................................................................................................................... .........................................................................................23 analog input ................................................................................................................... ......................................................................................25 audio wakeup................................................................................................................... ...................................................................................26 microphones .................................................................................................................... ....................................................................................27 reset.......................................................................................................................... ..........................................................................................28 digital-to-analog-converter (dac) output....................................................................................... ....................................................................28 pulse width modulator (pwm) analog output...................................................................................... ...............................................................30 comparator unit................................................................................................................ ...................................................................................31 instruction set opcodes and timi ng deta ils ..................................................................................... ............................................ 33 move group instructions ........................................................................................................ ............................................................................33 rotate group instructions ...................................................................................................... ..........................................................................34 branch group instructions ...................................................................................................... .........................................................................34 arithmetic/logical group instructions .......................................................................................... ..............................................................34 miscellaneous group instructions ............................................................................................... .................................................................35 special functions regi sters (sfrs) summary..................................................................................... ........................................ 36 dc characte ristics ............................................................................................................. ........................................................... 38 a.c. characteristics (ext ernal memory accesses)................................................................................ ........................................ 38 timing di agrams................................................................................................................ ........................................................... 39 absolute maxi mum rati ngs ....................................................................................................... ................................................... 39 package op tions ................................................................................................................ .......................................................... 40 die pad ring................................................................................................................... .............................................................. 43 RSC-4128 die bondi ng pad loca tions ............................................................................................. ............................................ 44
data sheet RSC-4128 3 p/n 80-0206-j ? 2004 sensory inc. mechanical data ................................................................................................................ ........................................................... 45 ordering in formati on........................................................................................................... .......................................................... 48 the interactive speec h? produc t line ........................................................................................... ............................................. 49
RSC-4128 data sheet 4 p/n 80-0206-j ? 2004 sensory inc. RSC-4128 overview the RSC-4128 is a member of the interactive speech? line of products from sensory. it features a high- performance 8-bit microcontroller with on-chip adc, dac, preamplifier, ram, rom (except on rom-less version), and optimized audio processing blocks. the RSC-4128 is designed to bring a high degree of integration and versatility into low-cost, powe r-sensitive applications. vari ous functional units have been integrated onto the cpu core in order to reduce total system cost and increase system reliability. the RSC-4128 operates in tandem with sensory speech? 7 firmware, an ultra compact suite of recognition and synthesis technologies. this reduced so ftware footprint enables, for example, products with over 150 seconds of compressed speech, multiple speaker dependent and independent vocabularies, speaker verification, and all application code built into the RSC-4128 as a single ch ip solution. revolutionary text-to-speaker-independent (t2si) technology allows the creation of si recognition sets by simply entering text. the cpu core embedded in the RSC-4128 is an 8-bit, vari able-length-instruction microcontroller. the instruction set is similar to the 8051 microcontroll er, and has a variety of addressing mode, mov and 16 bit instructions. the RSC-4128 processor avoids the limitat ions of dedicated a, b, and dptr registers by having completely symmetrical sources and destinat ions for all instructions. the RSC-4128 provides a high level of on-chip features an d special dsp engines, providing a very cost effective mixed signal platform for general-purpose applications and development of custom algorithms. the full suite of industry standard tools for easy product development makes the RSC-4128 an ideal platform for consumer electronics. RSC-4128 block diagram internal rom space (0k, 128k or 256k) 4.8k sram w atchdog timer timers (3) rsc general purpose microcontroller vector accelerator with twin dma dac pwm adc digital filters audio wakeup agc comparators (4 input) low battery detection pre-amp and gain control rsc-4x series e xternal m em ory interface 8-bit data, 20-bit address general purpose i/o 3 x 8-bit ports (24 i/o) dac out speaker out microphone 3.58 mhz oscillator or resonator 32 k h z o scillato r(o ption al)
data sheet RSC-4128 5 p/n 80-0206-j ? 2004 sensory inc. speech technologies speech recognition the RSC-4128 is designed to support hmm (hidden markov modeling) as well as neural network technologies provided in sensory speech? 7 firmware, to perform speaker independent (si) speech recognition. speaker independent recognition requires on-chip or off-chip rom to store the words to be recognized. speaker dependent (sd) recognition requires programmabl e memory to store personalized speech templates. this programmable memory may be on- chip sram or off-ch ip serial eeprom, flash memory, or sram. the RSC-4128 has several additional speech re cognition features as described below: speaker independent recognition requires no user training. the rs c-4128 can recognize up to 20 words in an active set (number of sets is limited only by internal rom or external memory size). te xt-to-si (t2si) recognition, based on hmm technology, allows creation of si recognition sets in seconds by simply typing in the vocabulary desired, with no costs or delays associated with recording and training the recognizer. speaker dependent recognition allows the user to create names fo r products or customize vocabularies. up to 100 words can be recognized in an active set (number of sets is limited only by internal rom or external memory size). the RSC-4128 can store up to 10 sd words in on-chip sram. continuous listening allows the chip to continuously listen for a spec ific trigger word. with this feature, a product ?activates? when a specific word is spoken, framed by qui et before and after. continuous listening provides the lowest false fire rate for trigger words. word spotting allows the chip to continuously recognize for up to 10 si or 5 sd words at a time. in word spotting mode, the word(s) to be recognized may be spoken in the middle of speech. speaker verification the RSC-4128 also supports sensory?s speaker verification (sv) technology ? the most successful biometric security on the market. after a speaker trains the chip on a specific word or words, the chip is able to identify whether a particular word is spoken by the original speaker. the RSC-4128 can store up to 10 sv templates on- chip, or more with external programmable memory. speech and music synthesis the RSC-4128 provides high-quality spee ch synthesis using state-of-the-a rt frequency domain techniques in sensory?s new ?sx? synthesis technology. typical data rates for sx are approximately 6000 bits per second. one may select various data rates from approximately 3.7 to 7.8kbps to manage speech quality versus allotted memory. speech, music and sound effects may also be pro duced using the RSC-4128 8 bit, 58kbps or 4 bit, 30kbps compression technologies. the RSC-4128 provides high-quality, eight -voice, wave table music synthesis which allows multiple, simultaneous instruments for harmonizing. the RSC-4128 uses a midi-like system to generate mu sic. one or more of the eight voices may be speech playback instead of music. one or mo re of the eight voices may be a drum track comprising multiple drums. in effect, th is allows the number of simultaneous instruments to exceed 8. speech and music synthesis requires on-c hip or off-chip rom to store data for synthesis playback. easy to use tools allow the developer to record and compress their own voice talents and create with the push of a button, or to create their own midi scores and instruments. record and playback the RSC-4128 can perform speech record and playback (s ometimes called ?voice memo?) at various compression levels depending on the quantity and quality of playback desi red. data rates less than 14,000 bits per second are achievable while maintaining very high quality reproduc tion. the record and playback technology also performs silence removal to improve sound quality and reduce memory requirements.
RSC-4128 data sheet 6 p/n 80-0206-j ? 2004 sensory inc. RSC-4128 architecture the RSC-4128 is a highly integrated speech and analog i/o mixed signal processor that combines: 8-bit microcontroller with enhanced instructions and interr upt control, superior register architecture, independent digital filter engine and ?l1? vector math accelerator on-chip rom and ram (4.8 kbytes), and the ability to address off-chip ram, rom, eprom or flash. input microphone preamp and 16 bit analog-to-digital c onverter (adc) for speech and audio/analog input 10 bit digital-to-analog converter (dac), and 10 bit pulse width modulator (pwm) to directly drive a speaker or other analog device low power audio wakeup from power down mode, when a sele cted audio event, such as clap or whistle, occurs the RSC-4128 has 20-bit address and 8-bit data busses for interfacing with external memory. it includes an -xm input pin capable of enabling or disabling the internal rom. note: neither the -xm input pin nor the extended memory busses are available on 64-lead lqfp packaged versions of the RSC-4128 with internal rom. these are available on the die and 100 lqfp versions. three bi-directional ports provide 24 configurable, general-purpose i/o pins to communicate with or control external devices with a variety of source and sink currents. up to 4 of these i/o may be used as programmable analog comparator inputs. 16 may be used as i/o wakeup. the RSC-4128 has a high frequency (14.32 mhz) clock as well as a low frequency (32,768 hz) clock. the processor clock can be selected from either source, with a selectable divider value. the device performs speech recognition when running at 14.32 mhz. the rsc- 4128 also supports programmable wait states to allow the use of slower memory. osc1 is a very low-cost 3.58 mhz crystal oscillator wh ich is used by a 4x pll to generate the 14.32mhz clock. the osc2 oscillator provides the options of using an external crysta l or its own internal rc devices (no external components required for the internal rc mode). there are three programmable, general-purpose 8-bit counte rs / timers ? timers 1 and 3 are derived from osc1, and timer2 from osc2. there is also a watchdog ti mer that may be used to exit an undesired condition in program flow, and multi-tasking timer to allow chip operations to share resources in parallel. RSC-4128 internal block diagram
data sheet RSC-4128 7 p/n 80-0206-j ? 2004 sensory inc. a single chip speech i/o solution may be created with the RSC-4128. an external microphone passes an audio signal to the preamplifier and adc to convert the incoming speech signal into digital data. speech features are extracted using the digital filter engine. the microcontro ller cpu processes these speech features using speech recognition algorithms in firmware, with the help of the ?l1? vector accelerator and enhanced instruction set. the resulting speech recognition results may be used to cont rol the consumer product application code, or to output speech or audio in the form of a dialog with the user of the consumer product. if desired, the output speech or audio signal from the RSC-4128 is generat ed by a dac for external amplificatio n into a speaker, or a pwm capable of directly driving a speaker at typica l consumer product volumes. a typica l product will require about $0.30 - $1.00 (in high volume) of additional components, in addition to the RSC-4128. the RSC-4128 also provides a very cost effective mixed signal platfo rm for general-purpose applications and development of custom algorithms. a typical general purpose application will require about $0.30 - $0.50 (in high volume) of additional components, in addition to the RSC-4128.
RSC-4128 data sheet 8 p/n 80-0206-j ? 2004 sensory inc. reference schematics schematic 1-1: RSC-4128, utilizing on-chip rom and optional external serial data memory ls1 speaker avdd c19 .1 c15 .1 c20 1uf c11 .1 r3 1.2k vdd flash c3 2.2uf c9 .1 bt1 3v avdd p1.4 vdd c1 2.2uf p1.4 c16 .1 r2 100 vdd y1 3.58mhz p0.1 jp1 recommended diagnostic output port 1 2 3 4 c14 .1 r1 100k c6 12pf p0.1 c8 .1 optional vdd vdd flash vdd c17 .1 c5 .1 c12 2.2uf x1 microphone vdd c13 .1 vdd c7 12pf c4 .1 c2 .1 vdd c18 100uf d1 1n4148 u2 rsc-4x with onchip rom 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p0.0 d7 d6 pdn d5 d4 gnd x01 xi1 vdd -xm xo2 xi2 d3 d2 p2.7 d1 d0 gnd vdd p2.6 m1 p2.5 brkpt -reset dacout avss vcm micin2 micin1 ampcom vref avdd nc p2.4 p2.3 nc p2.2 gnd p2.1 p2.0 gnd vdd -rdf -wrd -rdr -wrc a19 a18 test pllen a17 p1.7 a16 p1.6 gnd vdd a15 p1.5 a14 p1.4 a13 p1.3 a12 p1.2 a11 p1.1 a10 gnd vdd a9 p1.0 a8 a7 p0.7 nc p0.6 a6 nc p0.5 a5 nc p0.4 a4 nc gnd pwm0 pwm1 vdd nc a3 p0.3 nc a2 p0.2 a1 nc p0.1 a0 nc vdd u1 at45db011b 1 2 3 4 5 6 7 8 si sck -rst -cs -wp vcc gnd so c10 .1
data sheet RSC-4128 9 p/n 80-0206-j ? 2004 sensory inc. schematic 1-2: RSC-4128, utilizing external code and data memory a15 a16 tsop u1 sst29ve010(tsop) 20 19 18 17 16 15 14 13 3 2 31 1 12 4 5 11 10 30 32 7 21 22 23 25 26 27 28 29 8 24 6 9 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 ce oe we o0 o1 o2 o3 o4 o5 o6 o7 vcc gnd nc nc d4 u2 rsc-4000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p0. 0 d7 d6 pdn d5 d4 gnd x01 xi1 vdd -xm xo2 xi2 d3 d2 p2. 7 d1 d0 gnd vdd p2. 6 m1 p2. 5 brkp t -re set da cout avss vcm micin2 micin1 ampcom vref avdd nc p2.4 p2.3 nc p2.2 gnd p2.1 p2.0 gnd vdd -rdf -wrd -rdr -wrc a19 a18 test pll en a17 p1. 7 a16 p1. 6 gnd vdd a15 p1. 5 a14 p1. 4 a13 p1. 3 a12 p1. 2 a11 p1. 1 a10 gnd vdd a9 p1. 0 a8 a7 p0. 7 nc p0.6 a6 nc p0.5 a5 nc p0.4 a4 nc gnd pwm0 pwm1 vdd nc a3 p0.3 nc a2 p0.2 a1 nc p0.1 a0 nc vdd bt1 3v c2 .1 a9 a13 c15 .1 c7 12pf avdd a7 d6 c16 .1 d7 y1 3.58mhz a10 a11 a12 a13 d6 a14 c12 2.2uf d2 a7 a1 d0 a4 a2 pdn a13 a4 a14 c6 .1 c3 2.2uf a10 c17 .1 d5 d7 u3 27c010 (dip ) 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 1 31 13 14 15 17 18 19 20 21 32 16 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 ce oe vpp pgm o0 o1 o2 o3 o4 o5 o6 o7 vcc gnd a11 d3 pdn a14 d1 c4 .1 d1 a16 vdd a12 c8 12pf p0.1 a6 a8 vdd vdd a2 d0 jp1 recommended diagnostic output port 1 2 3 4 avdd d1 a4 ls1 sp ea k e r d4 vdd a[16:0] vdd d2 d6 a15 c1 2.2uf a8 a15 dip d7 a3 a5 d[7:0] r2 100 a5 c10 .1 c5 .1 vdd a12 a1 p1. 4 d4 c9 .1 a0 a3 r1 100k c11 .1 a9 a0 vdd x1 mi cr opho ne pdn d2 a5 c19 .1 a9 vdd d5 p1. 4 a0 c21 .1 d0 a6 d3 c20 1uf c13 .1 a2 d5 c14 .1 c18 100uf vdd a10 a7 r3 1.2k a16 d1 1n4148 a8 a11 p0. 1 a6 a3 a1 d3
RSC-4128 data sheet 10 p/n 80-0206-j ? 2004 sensory inc. using the RSC-4128 creating applications using the RSC-4128 requires the dev elopment of electronic circuitry, software code, and speech/music data files. software code for the RSC-4128 can be developed using a complete suite of RSC-4128 development tools including in-circuit emulator, c compile r, and ?push button? tools for speech recognition and synthesis data files. sensory provides fr ee design reviews of customer applicat ions to assist in the speech dialog and speech i/o design. sensory also offers applicatio n development services. for more information about development tools and services, please contact sensory. when using the RSC-4128 macro blocks such as the afe, digital filters, l1, etc, for purposes other than as intended in the sensory speech 7 technology modules, in ap plications that will also use sensory speech 7, care must be taken to avoid conflicts that may cause adve rse impact on functionality. contact sensory technical support for help in avoiding these conflicts. instruction set the instruction set for the RSC-4128 has 60 instructions comprising 13 move, 7 rotate, 11 branch, 22 arithmetic, and 7 miscellaneous instructions. all instructions are 3 bytes or fewer and no instruction requires more than 10 clock cycles (plus wait states) to execute. (see ?i nstruction set opcodes and timing details? for detailed descriptions) flags the ?flags? register (register ff) has bi ts that are set/cleared by arithmetic/l ogical instructions, a trap enable bit set under program control, a read- only stack overflow bit cleared at power on and set by stack wrap around, and the global interrupt enable bit: 0ffh r/w ?flags? bit 7: carry bit 6: zero (set = 1 when result of arith/log instruction is 0) bit 5: sign (set = 1 when result of arith/log instruction has msb high) bit 4: trap bit 3: stkoflo (read-only, initializ ed to 0, set to 1 on stack overflow) bit 3: stkfull (read-only, initialized to 0, set to 1 on stack full) bit 1: (unused) bit 0: gie (global interrupt enable) note: the ?trap? bit must be left written as ?0?. flags hold the ?flagshold? register (register cf) stores the ?flags? value when an interrupt occurs. unlike previous rsc chips, the RSC-4128 processor has read/write access to ?flagsho ld? for multi-tasking purposes. since the ?flags? register is restored from the ?flagshold? regist er upon return from interrupt, the ?stkof lo? and ?stkfull? bits are omitted from the ?flagshold? register to prevent inadvertent clearing of these bits. 0cfh r/w ?flagshold? bit 7: carry bit 6: zero bit 5: sign bit 4: trap bit 3: (unused ? reads 0) bit 2: (unused ? reads 0) bit 1: (unused ? reads 0) bit 0: gie note: the ?trap? bit must be left written as ?0?. see the discussion in ?interrupts? section relating to the value of ?gie? stored in the ?flagshold? register when an interrupt occurs during execution of an instruction that clears the ?gie? bit.
data sheet RSC-4128 11 p/n 80-0206-j ? 2004 sensory inc. stack there is a 16-level, 16-bit stack for saving the program counter for subroutine calls and interrupt requests. the stack pointer wraps around on overflow or underflow. when the stack read and write pointers indicate that stack overflow has occurred, the ?stkoflo? bi t in the ?flags? register is set. once set, this bit can only be cleared by a processor reset. the bit may be tested by software, but it performs no other function. when the stack read and write pointers indicate that stack is full, the ?stkfull? bit in the ?flags? register is set. this bit will be reset once the stack is not full. stack pointers the 16-level stack has two 4-bit pointers, stack write and stack read. they are normally written by the processor upon execution of a ?call? instruction or an interrupt. the stack also has a 6-bit index register ?stkndx? (register f6) and an 8-bit data port register ?stkdata? (register f7) that are used to access the stack contents as bytes in a register file under program c ontrol. the contents of the stack location selected by the ?s tkndx? register may be read or written by the processor via mov instructions at the ?stkdata? register. the stack register index must be written first, then the stack data can be read. the stack read and write pointers (4 bits each) are also mapped to addresses accessible via the stack register index. stack contents accessed by value in stack register index (?stkndx?, register f6) 00h stack0 lo 08h stack4 lo 10h stack8 lo 18h stackc lo 01h stack0 hi 09h stack4 hi 11h stack8 hi 19h stackc hi 02h stack1 lo 0ah stack5 lo 12h stack9 lo 1ah stackd lo 03h stack1 hi 0bh stack5 hi 13h stack9 hi 1bh stackd hi 04h stack2 lo 0ch stack6 lo 14h stacka lo 1ch stacke lo 05h stack2 hi 0dh stack6 hi 15h stacka hi 1dh stacke hi 06h stack3 lo 0eh stack7 lo 16h stackb lo 1eh stackf lo 07h stack3 hi 0fh stack7 hi 17h stackb hi 1fh stackf hi 20- 2fh (unused) 30- 3dh (unused) 3eh stackwriteptr (4bits only) 3fh stackreadptr (4bits only) register ram the RSC-4128 has a total physical register ram space of 896 bytes, divided into 14 banks of 64 bytes each. there is an additional 64 bytes of special function register s (sfrs). two of the regist er ram banks are directly addressed as unbanked memory, and the other 12 banks are banked. addressing 896 bytes requires an addres s width of 10 bits. (architecturally , an 11 bit address is implemented to allow for future increases in the register ram). logical re gister space addresses are 8 bits only (256 bytes), so 5 bank select bits in the ?bank? register (register fc) are used so to access the full 896 bytes. the 256 byte logical register space map is divided into 4 different 64 byte sections: 000h-03fh unbanked register ram 040h-07fh unbanked register ram 080h-0bfh banked register ram 0c0h-0ffh sfrs bits [4:0] of the ?bank? register deter mine which physical bank of 64 bytes is logically mapped to addresses 080h- 0bfh. when an address falls in the logically mapped range of 080h-0bfh, the lower 6 bits of the address (64 byte address) are used directly and the bank se lect bits are used as the upper 5 bits of the 11-bit physical register ram address. when the address falls below the logically mappe d range of 080h-0bfh, the lower 8 bits of the address are used directly to address the unbank ed register ram. when the address falls in the logically mapped range for the sfrs (0c0h-0ffh) the sfrs are addressed, not the register ram.
RSC-4128 data sheet 12 p/n 80-0206-j ? 2004 sensory inc. mapping of logical addresses 080h-0 bfh (?bank? register fc is used) register fc [4:0] physical ram memory register fc [4:0] physical memory 00h 00-3fh 08h 200-23fh 01h 40-7fh 09h 240-27fh 02h 80-bfh 0ah 280-2bfh 03h c0-ffh 0bh 2c0-2ffh 04h 100-13fh 0ch --- (unimplemented) 05h 140-17fh 0dh --- (unimplemented) 06h 180-1bfh 0eh --- (unimplemented) 07h 1c0-1ffh 0fh --- (unimplemented) note: if a value other than those indicated above is used for the ?bank? register, an undefined state will result. see the ?special functions registers summa ry? for details on the contents of sfrs. l1 vector accelerator/multiplier a variety of macros are provided by sensory that manipulate the l1 vector accelerator to provide signed and unsigned multiplication functions. see the ?sensory speec h 7 technology library manual? for information on these macros and their application. the l1/multiplier unit may be independently powered down by programming the register d6.bit 4 to ?0? (?clkext? register, ?l1clk_on? bit). digital filter the RSC-4128 has a digital filter engine capable of dividing up a frequency range into several smaller ranges. it is also capable of reporting characteristics of each r ange to the RSC-4128 processor. the configuration of the digital filter engine and access to signal characteristics generated are enabled by technology modules which are available from sensory ?technology support? upon request. power and wakeup control the typical active supply current is realized when operatin g with a main clock rate of 14.32 mhz at 3v and all i/o configured to the high-z state. lowering clock frequenc y reduces active power consumption, although sensory speech 7 technology typically r equires a 14.32 mhz clock. two supply current power-down modes are available ? sleep and idle modes. in sleep mode everything is stopped, and only an i/o event can initiate a wake-up. in idle mode osc2 and timer2 continue to run, and an audio wakeup, i/o wakeup or timer2 interrupt reque st caused by overflow can generate a wake-up. sleep mode is entered by setting register e8.bit7=1 (?ckctl? regist er; ?pdn? bit), register e8.bit0=1 (?osc1_off?) and register e8.bit1=0 (osc2 off). idle mode is entered by setting register e8.bit7=1, r egister e8.bit1=1 (?osc2_on?) and register e8.bit0=1. setting register e8.b it7=1 (?pdn?) freezes the processor, but does not insure that the dac, audio wakeup, and the pwm are placed in the lowest poss ible current-consumption state. software control must power these blocks down prior to setting ?pdn? to ?1?, according to the procedures indicated in ?dac?, ?audio wakeup?, and ?pulse width modulator analog output? sections. the ?sensory speech 7 technology library manual? provides sample code for achieving the lowest cu rrent-consumption state for sleep and idle modes. the state of ?pdn? bit may be observed externally on the pdn pi n (see pin definitions in ?package options? section) and used to control power down of circuitry external to the RSC-4128, if desired. note: gpio (ports 0,1 & 2) should be put in input mode and a known state (e.g. light pull-up) whenever possible to conserve power, and especially in powerdown m ode to achieve the specified minimum supply current consumption. the external memory interface (a[19:0] , d[7:0], -rdr, -wrc, -rdf and ?wrd) automatically goes into a high-z state and is pulled up by a 100 kohm internal re sistor when the ?pdn? bit is set, to conserve current. register e8 contains both the ?pdn? bi t and the processor clock selector (bit2) . the clock selector bit determines whether the 14.32 clock (?fast clock?) or the 32khz clock (? slow clock?) will be used at wakeup time, independent of what clock rate was being used before or during power down mode. this allows the processor clock after wakeup
data sheet RSC-4128 13 p/n 80-0206-j ? 2004 sensory inc. to be the same or different from the processor clock used when the power-down flag was set. (see ?clock? section for complete explanation) to minimize power consumption, most operational blocks on the chip also hav e individual power controls that may be selectively enabled or disabled by the programmer. wakeup from powerdown note that a wakeup event does not cause a reset. the pr ocessor, which was "frozen" when register e8.bit7 was set, will be restarted without loss of context. a reset of the chip will also cancel a power down mode, but with a corresponding loss of processor context. wakeup events terminate a power-down state. in sleep mode, only an i/o wakeup event can initiate a wake-up. in idle mode, an audio wakeup, i/o wakeup or timer2 interr upt request caused by overflow can generate a wakeup. an i/o wakeup is enabled by setting the bit(s) high in regist ers e9 or ea corresponding to the desired i/o pin(s) to be used for wakeup. e9 controls p0 wakeup enable and ea controls p1 wakeup enable. the polarity of the wakeup event is controlled by putting the appropriate port pin in input mode and writing the appropriate bit in the output register for that pin to the desired polarity. (s ee ?general purpose i/o? section for complete explanation) when the value on the wakeup pin equals the value in the output register a wakeup will occur. a t2 wakeup is enabled by setting register e8.bit6 high. then an overflow of timer t2 will generate an interrupt request, which in turn will trigger a wake up event. note that the timer2 ?irq? bit (register fe.bit1) must be cleared prior to powering down to allow the wakeup interrupt r equest to occur. (the ?timers/ counters? section describes how timer t2 is configured) an audio wakeup is generated by special circuitry that can detect several classes of sounds, even while in power- down mode. when the class of sound selected by the progra mmer is detected by this circuitry a wakeup event will occur. (see the ?audio wakeup? section for more information) general purpose i/o the RSC-4128 has 24 general-purpose i/o pins (p0.0-p0.7 , p1.0-p1.7, p2.0-p2.7). each pin can be programmed as an input with weak pull-up (~200k ? equivalent device); input with strong pull-up (~10k ? equivalent device); input without pull-up, or as an output with sufficient drive to light an led. (see ?dc characteristics? section for i/o electrical characteristics.) this is accomplished by prog ramming combinations of 48 bits of configuration registers assigned to the i/o pins. two control registers, a and b, are us ed to control the nature of inputs and ou tputs for each port. registers e6 (?p0ctla?) and e7 (?p0ctlb?), e2 (?p1ctla?) and e3 (?p1ctlb? ), and de (?p2ctla?) and df (?p2ctlb?), are the control registers a and b for ports p0, p1 and p2, respectively . each port pin?s i/o configuration may be controlled independently by the state of it?s co rresponding bits in these registers. control registers a and b together determine the function of the port pins as follows: b bit a bit port pin function 0 0 input - weak pull-up 0 1 input - strong pull-up 1 0 input - no pull-up 1 1 output (for example, if register e7.bit 4 is set high, and register e6.bit 4 is low, then pin p0.4 is an input without a pull-up device.) after reset, pins p0.0-p0.7, p1.0-p1.7, and p2.5-p2.7 are se t to be digital inputs with weak pull-ups, and pins p2.0- p2.4 are configured as analog input pins with no pull-ups. being reset as an input and lightly pulled to a known
RSC-4128 data sheet 14 p/n 80-0206-j ? 2004 sensory inc. (high) state ensures minimum power consumption as a def ault beginning. sixteen of these pins (ports p0 and p1) can also be configured as inputs to control io wakeup events. (see ?power and wa keup control? section). p2.0, p2.1, p2.3, and p2.4 can be configured as comparat or inputs. p2.2 can be configured as a comparator reference. some or all of p2.0-p2.4 can be configured as di gital inputs by the use of t he ?cmpctl? register (register d4) bits[2:0] (see ?comparator unit? section) note: when configuring p2.0-p2.4 as digital inputs the associated weak pull-up should be selected as shown above. p0.0 and p0.2 can be configured as external interrupts (see ?interrupts? section). p0.1 can be configured in input mode as a gate for an external event co unter. (see ?timers/counters? section) registers e5 (?p0in?) and e4 (?p0out?), e1(?p1in?) and e0 (?p1out?), and dd (?p2in?) and dc (?p2out?), provide paths for data input and data output on p0, p1 and p2, respec tively. the input registers are actually buffers which record the value at the ports at the time they are read. the output registers latch the data written to them and express it on the ports when the ports are configured as an output. following is a summary of the general purpose i/o control registers: register 0dch read/write p2[0:7] (port 2) output register. cleared by reset. 0ddh read port 2 input. 0deh read/write port 2 control register a. cleared by reset. 0dfh read/write port 2 control regist er b. bits[7:5] cleared by reset. bits[4:0] set by reset 0e0h read/write p1[0:7] (port 1) output register. cleared by reset. 0e1h read port 1 input. 0e2h read/write port 1 control register a. cleared by reset. 0e3h read/write port 1 control register b. cleared by reset. 0e4h read/write p0[0:7] (port 0) output register. cleared by reset. 0e5h read port 0 input. 0e6h read/write port 0 control register a. cleared by reset. 0e7h read/write port 0 control register b. cleared by reset. gpio during powerdown gpio should be put in input mode and a known state (e.g. li ght pull-up) whenever possible to conserve power, and especially in powerdown mode to achieve the specified minimum supply current consumption. memory addressing the rsc4128 can address up to 2mbytes with a combinat ion of 128kbytes of default internal rom and/or optional external rom, ram or flash memories, without additional decoding circuitry . this is accomplished with 16 address outputs, a[15:0], and up to 4 extended addr ess outputs a[19:16]. there are two different memory spaces of up to 1mbbyte each: constant/code space and data space. (?constant? space is referred to as ?const? space in assembly and c-data space in c) data space can be r ead or written. constant/code space is typically read-only. the RSC-4128 includes an external memory interface that allows connection with memory devices for storage of speaker-dependent speech recognition templates, audio record/playback data storage, extended durations of speech and music synthesis beyond the storage capabilitie s of on chip rom, and code storage for the rsc4000 romless version. thirty-four (34) pins are used to provide a parallel bus interface between the processor and external rom, eprom, sram, or flash, for die and 100lq fp-packaged versions. an example of this parallel bus usage is provided in the reference schematic 1-2. the RSC-4128 external memory interface has been improved for atd-type memories. the external address lines remain stable during instruction cycles that access internal ram or rom. the ?rdr and ?rdf signals go high when not actively reading. the condition of the external data lines is weak pull-up when not accessing t he external bus. (see ?dc characteristics? section for bus electrical characteristics.)
data sheet RSC-4128 15 p/n 80-0206-j ? 2004 sensory inc. one may also interface to serial memory devices for storage and retrieval of speech data, by using the serial drivers for rom, flash, eeprom, etc. provided in the se nsory speech 7 technology library. the serial memory option is useful for applications of the rsc4128 packaged in a 64lqfp (which lacks the external parallel bus) for which speech or music data exceed the storage capacity of on chip rom. using serial rom, flash or eeprom may result in a simpler, smaller pcb layout and lower ov erall system cost. the specific i/o used by the serial interface are configurable. (see the ?sensory speech 7 technology library manual? for more information). an example of the optional use of external serial flash is provided in reference schematic 1-1. constant/code space when reading, constant/code space can be either internal to the chip or external. typical uses of this space are for code storage, and si recognition set and/or compressed s peech constant data storage. when the ?xm input pin is held low, constant/code space is external to the chip when reading and ?rdr is the read str obe. when the ?xm pin is high, constant/code space reads are always inter nal to the chip, and are limited to the physical size of the internal rom. when writing, ?wrc is the write str obe regardless of the state of the ?xm pin. writing to constant/code space requires the movc instruction, which is limited to the first 128kbytes of constant/code space. when reading constant/code space, an application can acce ss up to 1mbyte. however, only the first 128kbytes can be used by the processor for pr ogram instructions (code). the movc instruction can only read these first 128kbytes. these first 128kbytes are partitioned into 64k byte banks, called code bank 0 and code bank 1. (note: code using both banks up to 128 kbytes must provide ?mirror? code in both banks for routines such as interrupt service, etc, with protoc ols to track bank identity.) the movx instruction can read the full 1mbyte. however, the movc is more efficient for reading constants within the current code bank. the entire 1mbyte of constant/code space can be read with the following conditions. the upper addresses a[19:16] are generated from bits[3:0] of ex tended addressing register (register d2): 1) the movx instruction is used to read and bi t 4 (?rw?) of extended addressing register (register d2) is programmed to ?0?. the first 128kbytes (addresses 00000h-1ffffh; code banks 0 & 1) can be accessed in two additional ways. for these two cases, addresses a[19:17] are forced to zero by the rsc4x, and a[16] is gener ated from bit 5 (?cb1?) of the extended addressing register. a ?0? in ?cb1? sele cts code bank 0 and a ?1? selects code bank 1: 2) the processor fetches instructions from the active code bank. 3) the movc instruction is used to read from or write to the active code bank. data space data space is always external to the chip and can be up to 1mbyte. typical uses of this space are for storage of sd recognition template data and/or recorded audio data, and frequently the data is volatile. ?rdf is the read strobe and ?wrd is the write strobe. a special bit in the extended addressing register must be set high to allow the processor to read from the data space using the movx instruction. when the ?rw? bit (bit 4 of register d2) is set, the movx instruction reads from the data space. when writing to data space, the movx instruction generates a ?wrd strobe, re gardless of the state of the ?rw? bit. data space can be accessed in two ways. for both case s, upper addresses a[19:16] are generated from bits [3:0] of extended addressing register: 1) the movx instruction is used to read and bit 4 (?rw?) of extended addressing register (register d2) is programmed to ?1?. 2) the movx instruction is used to write.
RSC-4128 data sheet 16 p/n 80-0206-j ? 2004 sensory inc. extended address register 0d2h r/w extadd bit [7:6] (unused) bit 5 cb1 0: movc reads/writes and processor fetches access addresses 00000h-0ffffh of constant/code space (code bank 0) 1: movc reads/writes and processor fetches access addresses 10000h-1ffffh of constant/code space (code bank 1) cleared on reset. bit 4 rw 0: movx reads access constant/code space 1: movx reads access data space cleared on reset. bits [3:0] ?eda? bits ? extended address bits [19:16] used by movx to generate addresses bits a[19:16] of data and/or constant/code space. cleared on reset. the programming of the extended addressi ng register(?extadd?) is independent of whether the rom is external or internal. that is, an external rom mirrors an internal rom exactly. this allows products to be developed with external rom and masked with the same binary in an internal rom part. note: unlike the rsc-3x, the last 256 bytes of data spac e are not allocated for internal processor functions. all internal processor functions are mapped to the sfr area of register space, leaving all data space addresses potentially accessible as external memory. there are 8 data bus lines. these pins are bi-directional: they are normally inputs except when there is an external write to code space or data space. these pins, d[ 7:0], have weak pull-up devices (~100k ohm) to keep them from floating when no device is driving the data bus. external memory inte rface control signals there are 4 active low read/write strobes for reading from and writing to external constant/code space or data space: -rdr, -wrc, -rdf, -w rd. to support cost effective software development for large memory spaces the external memory strobes are differ ent from earlier rsc chips. the ?rdr signal replaces the previous ?rdc signal and the ?rdf signal replaces the previous ?rdd signal. the ?xm pin replaces the previous ?xml and ?xmh pins on earlier rsc devices. the ?wrc signal an d the ?wrd signal are the same as in previous rsc chips. (see ?dc characteristics? section for electrical characteristics.) the 20-bit extended address for a memory-reference instruct ion or a code fetch may be directed to the internal rom, or it may be directed to an external rom or flash. the address is always an external address if: 1) the instruction is movx read and the ?rw? bit is set, or 2) the instruction is movx write, or 3) the ?xm pin is low, or 4) the instruction is a movc write otherwise the address is internal. the ?xm pin is an active low input pin that disables inte rnal rom when pulled low, and forces the use of external memory for constant/code space. write acce sses to constant/code space (movc write; ? wrc active) are always directed off-chip. the -xm pin has a weak pull- up device (~10k ohm) to enable the internal rom when no connection is made to this pin. at the end of reset -xm is sampled and, if pulled low externally, the internal 10k ohm pull-up device is disabled.
data sheet RSC-4128 17 p/n 80-0206-j ? 2004 sensory inc. the ?rdr signal goes low when the ?xm pin is held low and either 1) the chip executes an instruction fetch, or 2) the chip executes a movc read instruction, or 3) the chip executes a movx read instruction and the ?rw? bit is zero. this active low signal is used to enable an external rom or other external memory containing both executable code and fixed, read-only data. the ?rdf signal goes low when the chip executes a movx read instruction and the ?rw? bit is set to 1. this active low signal is used to read an external flash or other exter nal memory that is used sole ly for the purpose of data space, either read-only fixed dat a or read-write dynamic data. the ?wrd signal goes low when the processor executes a movx write instruction. the ?wrc signal goes low when the processor executes a movc write instruction. these signals do not depend on the contents of the extended address register or the ?xm signal, since a write by definition cannot be done to internal rom. external memory interface during powerdown the external memory interface (a[19:0], d[7:0], -rdr, -wrc, -rdf and ?wrd) automat ically goes into a high-z state and is pulled up by a 100 kohm internal resistor when the ?pdn? bit is set, to conserve current. one output, pdn, is active high when RSC-4128 is powered -down. this pin can be co nnected to the (active low) chip enable pins of external memory devices to r educe power consumption during RSC-4128 power-down. wait states general control of wait states is managed by register fc.bits[7:5] (? bank? register). these bits are set to a value of 7 on reset, defaulting to slower memory. an initializati on routine may be used to configure for faster memory. access of external rom space is always controlled by t hese wait state bits. internal rom space and all external r/w space accesses may also controlled by these bits, unl ess otherwise selected by bits in the clock extension register (register d6, ?clkext?) the internal rams always operate with zero wait states. register d6 provides for extended contro l of some clocks derived from osc1 for producing additional timer scaling or specialized wait states. when bit 5 is set, it overri des the ?bank? register cont rol of wait states during movx instructions which access external read/write memory (regist er d2.bit4=1), and forces a fi xed value of 4 wait states (nominal 350ns access). when bit 7 is set, it overrides t he ?bank? register control of wait states during internal rom accesses and forces zero wait states. using th ese controls, various memory access speeds may be accommodated within one application. bit 5 0: certain movx * instructions use the wait state di visor in register fc.bits[7:5] 1:certain movx * use fixed 4 wait states (nominal 350nsec access) cleared by reset bit 6 0: mt timer clock is disabled 1: mt timer clock i s enabled cleared by reset bit 7 0: accesses to internal rom use the wa it state divisor set in register 0fch[7:5] 1: accesses to internal rom use selected clk (no wait states) cleared by reset. * movx accessing external read-write memory (?rw?; register d2.bit4=1).
RSC-4128 data sheet 18 p/n 80-0206-j ? 2004 sensory inc. instruction opcode operand 1 operand 2 description bytes cycles +cycles/ waitstate mov 10 dest source register to register 3 5 3 mov 11 @dest source register to register-indirect 3 5 3 mov 12 dest @source register-indirect to register 3 6 3 mov 13 dest #immed immediate data to register 3 4 3 movc 14 dest @source code space to register 3 7 4 movc 15 @dest source regist er to code space 3 8 4 movx 16 dest @source data space to register 3 7 4* movx 17 @dest source register to data space 3 8 4* pop 18 dest @++source register to register data stack pop (source pre- incremented) 3 10 3 push 19 @dest-- source register to register data stack push (dest post- decremented) 3 9 3 movy 1a dest @source ramy to register, indirect 3 7 3 movy 1b @dest source register to ramy, indirect 3 7 3 movd 1c dest_pair source_pair register to register, direct, 16-bit mov 3 7 3 * movx instructions will have the number of wait states sele cted by register fc.bits[7: 5], unless register d2.bit4 and register d6.bit5 are set, in which case t he number of wait states is fixed at 4. on-chip rom the RSC-4128 includes integrated on-chip rom. this ro m is enabled when the ?xm pin is tied , or pulled high by it?s own internal pullup resistor. this rom space can combine both code and data. rom code security feature the RSC-4128 has only one external memory enable pin (-xm ), designed to prevent configuring code space for both internal and external memory. th is discourages executing external code that reads internal code via the movc instruction and dumps it externally. in this way, a substantial measure of security is provided for the developer?s application code. oscillators two independent oscillators in the RSC-4128 provide a high-frequency oscillator (osc1), and a 32 khz time- keeping and power-saving oscillator (osc2) . the oscillator characteristics are: osc freq pll pins sources 1 3.58 mhz 4x xi1 xo1 crystal ceramic resonator lc 2 32768 hz n/a xi2 xo2 crystal internal rc
data sheet RSC-4128 19 p/n 80-0206-j ? 2004 sensory inc. osc1 osc1 is enabled by programming register e8.bit0 to ?0?, which is the reset state for this bit. this bit is also programmed to ?0? during a wakeup event, enabling osc1, if register e8.bit2 is programmed to ?0?. (see ?power and wakeup control? section) in this case, a 10-20 millisec ond delay will be forced to allow osc1 to reach stable oscillation. osc1 must run at 3.58 mhz when using the sensory speech 7 technologies, but may be slower if the RSC-4128 is used as a general purpose platform for other applications. when osc1 is disabled, the pll which generates the 14.32mhz clock (clk1) is also disabled. osc2 osc2 is enabled by programming register e8.bit1 to ?1?. the reset state for th is bit is ?0?, so this oscillator is disabled by reset. osc2 will be enabled during a wakeup event if regist er e8.bit2 is progra mmed to ?1?. (see ?power and wakeup control? section) no delay will be forced, as osc2 is assumed to be running during idle mode. the osc2 source may be set to an external 32 khz crystal by programming regist er ef.bit2 to ?0? (note: register ef.bit7 must be ?0? to enable writing ef.bit2) the external 32khz crystal should be used when accurate timing and/or time-keeping is essential. in this mode, osc2 is capable of achieving errors as low as 20ppm, depending on the quality of the crystal and crystal circuit design. a typical value for the crystal bias capacitors is 27pf, but this will vary depending on the crystal quality and stray capacitance inherent in the application board layout. the osc2 source may be set to an on-chip rc by programming register ef.bit2 to ?1? (note: register ef.bit7 must be ?0? to enable writing ef.bit2). when using the on-chi p rc, no external components are required for osc1. the on-chip rc value will vary due to process, temperature an d supply voltage variations, so this oscillator frequency will vary by +/- 30%. the on-chip rc mode should be used for low power modes where timing is not critical and minimum system cost is important. oscillator stabilization when exiting sleep mode (see ?pow er and wakeup control? section) osc1 will have a forced 10-20millisecond delay for stabilization if it is enabled. if osc2 is enabl ed, it may require several seconds to stabilize, after which the rsc4128 will begin running. therefore, for fast response out of sleep mode osc1 should be enabled. clocks the RSC-4128 uses a fully static co re ? the processor can be stopped (by removing the clock source) and restarted without causing a reset or losing contents of internal registers. dynamic operation is guaranteed from ~1khz to 14.32 mhz. fast clock the 3.58 mhz osc1 frequency is quadrupled by an on-chi p pll to produce a 14.32 mhz internal clock (clk1). creating the internal clock in this way avoids an expensi ve high frequency crystal, substantially reducing overall system cost. when used as the processor clock (see bel ow), the 14.32 mhz internal clock creates internal ram cycles of 70 nsec duration, and internal or exte rnal code/data memory cy cles of 140 nsec duration . careful design may allow operation with memories having access times as slow as 140 nsec. slow clock osc2 generates an internal clock (c lk2) with an equivalent frequency to osc2. when used as the processor clock (see below), the ram access cycles are one clk2 cycle and code/data access cycles are two clk2 cycles. processor clock either clk1 or clk2 can be selected as the processor cloc k (pclk) on the fly by changi ng the value of register e8.bit2. the reset state defaults to clk1. (note: it is po ssible to select a disabled clock as the processor clock. it is the responsibility of the programmer not to select a clock until the corresponding o scillator has been enabled and allowed to stabilize.) power savings may result by usin g clk2 when the processor is a lower activity mode and using clk1 when in a higher activity mode. if the use of an external clock driver is desir ed, the output of that driver should be connected to the xi1 pin.
RSC-4128 data sheet 20 p/n 80-0206-j ? 2004 sensory inc. after source selection, the processor clock can be divided-down in order to limit power consumption. register e8.bits 4 and 3 determine the divisor: e8.bit4 e8.bit3 processor clock divisor 0 0 1/2 0 1 1/1 (reset default) 1 0 1/8 1 1 1/256 a processor clock divisor of 1/1 is typically required for sensory speech 7 technology. the processor clock is gated by the wake-up delay and also gated by ?pdn?=0 (register e8.bit7), in such a way that the processor is stopped in a zero-pow er state with no loss of context. other system clocks the following functional clocks are generated from osc1: clk1, the digital filter clock, the analog front end (afe) master clock, the l1 clock, timer1 clock, timer3 cloc k, and the multi-task timer cloc k. the timer2 clock and the watchdog timer clock are generated from osc2. (see each bl ock?s section for clocking details) all clocks except the timer2 and audio wakeup clocks are gated with the pdn = 0, to assure they are disabled during idle and sleep modes. timer2 and a udio wakeup can run during id le mode to produce a t2 wakeup or audio wakeup. (see ?power and wakeup control? section) timers/counters four programmable timers and one fixed timer in the rsc-41 28 provide a variety of timing/counting options. timers 1, 2, 3 and the multi-tasking timer can all generate in terrupts upon overflow. (s ee ?interrupts? section) timers 1 and 3 each of timer1 (t1) and timer3 (t3) consists of an 8- bit reload value register, an 8-bit up-counter, and a 4-bit decoded prescaler register. each is clocked by clk1 divi ded by 16. the reload register is readable and writeable by the processor. the counter is readable with precau tion taken against a counter change in the middle of a read. note: if the processor writes to the count er, the data is ignored. instead, the act of writing to the counter causes the counter to preset to the reload register value. when the timer overflows from ffh, a puls e is generated that sets regi ster fe.bit 0 (?irq? regist er; t1 bit) or register fe. bit 4(t3 bit). the width of the pulse is the pre-scaled counter clock period. instead of overflowing to 00, the counter is automatically reloaded on each overflow. for example, if the reload value is 0fah, the counter will count as follows: 0fah, 0fbh, 0fch, 0fdh, 0f eh, 0ffh, 0fah, 0fbh etc. the overflow pulse is generated during the period after the counter value reaches 0ffh. a separate 4-bit decoded prescaler regist er is between the clock source and the up-counter for each of t1 and t3. the 4bits represent the power of 2 used to divide the timer cl ock before applying it to the up-counter. for example, a prescaler value of 0 passes the timer clock directly throug h (divides by 2^0 = 1). a prescaler value of 5 divides the timer clock by 2^5 = 32.
data sheet RSC-4128 21 p/n 80-0206-j ? 2004 sensory inc. prescaler value divisor prescaler value divisor 0000 1 1000 256 0001 2 1001 512 0010 4 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 the resolution of t1 and t3 is 8 bits, but the range is 23 bi ts. the longest interval that can be timed by t1 or t3 is 2^15*256 clocks = 9.3 seconds. the 4-bit prescaler for t1 is in the clock extensions register , (register d6.bits[3:0]). the 4-bit prescaler for t3 is in the timer3 control register (register d9.bits[3:0]). in addition to its timing capability, t3 can also be configured as a counter of external events. in this configuration it uses either the rising or falling edge of a signal applied to i/o pin p0.1. the selected transition is internally synchronized to clk1. the maximum external count rate for t3 is 447khz. the timer3 control register contains the counting/timing optio ns for t3. the register is write-only. bits[6:4] provide configuration control. bit6 bit5 bit4 timer source configuration x 0 0 t3clk timer 0 0 1 t3clk timer gated by p0.1 low 1 0 1 t3clk timer gated by p0.1 high 0 1 x p0.1 count p0.1 events, rising edge 1 1 x p0.1 count p0.1 events, falling edge bit 7 0: disable t3 and prescaler from counting/timing 1: enable t3 cleared by reset. bit 6 0: use rising edge for external event counting use low state on pin p0.1 for timer gating 1: use falling edge for external event counting use high state on pin p0.1 for timer gating cleared by reset bit 5 0: use internal t3clk for source (timing) 1: use external events on pi n p0.1 for source (counting) cleared by reset bit 4 0: normal operation 1: t3 is gated by pin p0.1 according to bit6 cleared by reset. bit 3:0 encoded prescaler for t3. (see prescaler table above). cleared by reset.
RSC-4128 data sheet 22 p/n 80-0206-j ? 2004 sensory inc. t1 and t3 can generate interrupts upon overflow by setti ng register fd.bit0=1 and bit4=1, respectively. (see ?interrupts? section) timer2 timer2 (t2) is clocked by clk2 divided by 128. the overflow pulse from t2 can cause an interrupt request which in turn will cause a t2 wake-up from power-down, if register e8.bit6=1. (see ?power and wakeup control? section). note that the timer2 ?irq? bit (regist er fe.bit1) must be cleared prior to powering down to allow the wakeup interrupt request to occur. t2 can also generate a standard interrupt request by setting register fd.bit1=1. (see ?interrupts? section) timers 1, 2 and 3 timer reload and counter registers all are cleared to zero on reset. register addr t1r ebh read/write timer1 counter reload (2's complement of period) t1v ech read timer1 current counter value write force load of timer1 counter from reload register t2r edh read/write timer2 counter reload (2's complement of period) t2v eeh read timer2 current counter value write force load of timer2 counter from reload register t3r dah read/write timer3 counter reload (2's complement of period) t3v dbh read timer3 current counter value write force load of timer3 counter from reload register multi-task timer the multi-tasking (mt) timer is intended to count a fi xed interval of 858.1 microseconds. this provides a ?heartbeat? for multi-tasking in the sensory speech 7 tech nology library. other applications may find this useful for similar purposes. this interval is obtained by dividing t he clk1 rate, when running at 14.32 mhz, by a fixed factor of 12288. there is no configurab ility to the mt timer. one bit in the cl ock extension register (d6.bit6) enable this timer?s clock. the mt timer overflow can generate an inte rrupt by setting register fd.b it7=1. (see ?interrupts? section) watchdog timer due to static electricity, voltage glitches, or other envi ronmental conditions (or program bugs!), a software program can begin to operate incorrectly. the watchdog timer provides protection from such errant operation. the watchdog timer (wdt) unit comprises two control bi ts in the system control register (d5), a special instruction, two status bits, and a 17-bit counter. t he counter, driven by osc2, produces a toggle rate of approximately 4 seconds at the 17 th bit. a 2-bit decoded mux in the ?sysctl? register (register d5) allows selecting the wdt timeout pulse from bit 9, 13, 15, or 17 of the counter. this selection sets the timeout in the range of approximately 15.6 msec to 4 seconds. the accuracy of these times will depend on whether the osc2 source is a 32 khz crystal or the on-chip rc. the wdt is enabled by register fb .bit4=1. this bit can only be set by exec ution of the ?wdc? instruction. this bit is cleared by reset, so the wdt is disabled by reset. th e bit is also cleared when e8.b it7=1 (pdn), so the wdt is disabled in either sleep or idle mode. it is not automa tically re-enabled on wake up. program control cannot write to register fb.bit4 to enable or di sable the wdt. that is, fb.bit4 is a re ad-only bit for normal register access instructions. since the wdt needs osc2 for its operat ion, once the wdc instru ction has been executed and register fb.bit4=1 to enable the wdt, osc2 cannot be disabled by program ming register e8.bit1 =0 unless the ?pdn? bit (register e8.bit7) is also set simultaneously. this allows disabling the wdt only when entering a power down mode and is intended to reduce the probability of a ccidental software disabling of the wdt in active mode.
data sheet RSC-4128 23 p/n 80-0206-j ? 2004 sensory inc. executing the wdc instruction clears the wdt counter, sets register fb.b it4=1, clears register fb.bit5=0 (wd_timed-out), and starts a new timeout period. the os c2 oscillator may also be enabled by executing the wdc instruction. if the oscillator is stopped, executing this inst ruction also sets register e8.bit1=1 to enable osc2. in this case, timing will not begin until the oscillator is active. once the wdt is started, software must execute the wdc in struction at a rate faster than the timeout period. otherwise the watchdog circuit sets the ?watch dog tim ed out? bit (register fb.bit5) and generates a timed out reset, which resets the RSC-4128. a timed out reset di sables the wdt. (see ?reset ? section) software in the reset routine can detect that the wdt timed out (fb.bit5=1 ), since that is preserved during the timed out reset. placing the chip in sleep or idle mode disables the wdt operation. timer powerdown some timers have independent power down control, while others may only be powered down by turning off their clock source, setting the ?pdn? bit, or resetting. it is not re quired for the application to do this for full chip power down, as long as it complies with directions in the ?power and wakeup control? section. however, one may choose to reduce power consumption in active mode by turning off individual timers. timer 3 and mt timer may be independently powered down by setting the register d9.bit 7 to ?0? (?t3ctl? register, ?t3_on? bit) and register d6.bit 6 to ?0? (?clk ext? register, ?mtclk_on? bit), respectively. timer 1, timer 2 and the wdt require special circum stances to powerdown, whic h are appropriate for their application. see their respective descriptions for more detail. interrupts the RSC-4128 allows for 8 interrupt request sources, as selected by software. all are asynchronous positive edge activated except the two external requests, which have programmable e dges. each has its own mask bit and request bit in the ?imr? and ?irq? registers respectively. there is a global interrupt enable flag in the ?flags? registers. the ?imr? and ?irq? bits are listed below wi th the RSC-4128 interrupt source shown in parenthesis: 0fdh ?imr? bit 7: 1= enable interrupt request #7 (overflow of mt timer) bit 6: 1= enable interrupt request #6 (edge of p0.2) bit 5: 1= enable interrupt request #5 (b lock end)(reserved for technology code) bit 4: 1= enable interrupt request #4 (overflow of timer3) bit 3: 1= enable interrupt request #3 (edge of p0.0) bit 2: 1= enable interrupt request #2 (filter end marker)(reserved for technology code) bit 1: 1= enable interrupt request #1 (overflow of timer2) bit 0: 1= enable interrupt request #0 (overflow of timer1) 0feh ?irq? bit 7: 1=interrupt request #7 (overflow of mt timer) bit 6: 1= interrupt request #6 (edge of p0.2) bit 5: 1=interrupt request #5 (block end)(reserved for technology code) bit 4: 1= interrupt request #4 (overflow of timer3) bit 3: 1= interrupt request #3 (edge of p0.0) bit 2: 1= interrupt request #2 (filter end marker)(reserved for technology code) bit 1: 1= interrupt request #1 (overflow of timer2) bit 0: 1= interrupt request #0 (overflow of timer1)
RSC-4128 data sheet 24 p/n 80-0206-j ? 2004 sensory inc. if an ?irq? bit is set high and the corresponding ?imr? bit is set high and the global interrupt enable (?gie?; register ff.bit0) bit is set high, an interrupt will occur. interr upts may be nested if software handles saving and restoring the ?flagshold? register (register cf). th e ?flags? register is copied to the ?flagshold? register and then the global interrupt enable is cleared, preventing subsequent interrupt s until the iret instruction is executed. the iret instruction will restore the ?flags? regi ster from the ?flagshold? register. the global interrupt enable bit in the ?flags? register must not be re-enabled during the period af ter an interrupt has been acknowledged and before an iret instruction has been executed unle ss interrupt nesting is desired. if an interrupt occurs during an instruction that clears the global interrupt enable bit (typically the cli instruction) the value of the ?gie? bit will be 0 upon completion of the in terrupt service routine and return from interrupt to the instruction following the one that clear ed the ?gie? bit. (note: this is a ch ange from the operation of the rsc-364.) the ?flagshold? register is accessible under program c ontrol at address cf in order to improve multi-tasking operation. external interrupts may be enabled on pins p0.0 (1 st external interrupt request) and p0.2 (2 nd external interrupt request), by setting register fd.bit3=1 and register fd.bit 6=1, respectively. the polarity of the edges to trigger an external interrupt request for p0.0 and are controlled by register d5.bits[1:0]. setting d5.bit0=0 will cause a positive going edge on p0.0 to generate and interrupt and d5.bit0=1 will cause a negative going edge to generate an interrupt. the same controls for p0.2 are possible with d5.bit1. the corresponding external ?irq? flag will be set if the transition matches the interrupt edge control bit. note: if p0.0 or p0.2 are configured as outputs, writing to those outputs can trigger exte rnal interrupt requests if the proper edge polarities occur. the user must be careful to avoid this, unless it is intended to use this as a way of generating interrupt requests under internal software control. an interrupt is disabled by writing a zero to the corresponding bit in the imr r egister (register 0fdh). however, an active interrupt request can still be pending. to be certai n that an interrupt does not happen, you should clear the interrupt request flag in the irq register (register 0feh) as well. for example: ; disable timer 1 interrupt cli and imr,#0feh ; mask new interrupt requests mov irq,#0feh ; clear any pending interrupt request sti for each interrupt, execution begins at a different address: interrupt #0 address 04h (overflow of timer 1) interrupt #1 address 08h (overflow of timer 2) interrupt #2 address 0ch (filter end marker)(reserved for technology code) interrupt #3 address 10h (edge of p00) interrupt #4 address 14h (overflow of timer 3) interrupt #5 address 18h (block end)(reserved for technology code) interrupt#6 address 1ch (edge of p02) interrupt#7 address 20h (overflow of mt timer) the interrupt vector is generated as a 20-bit address. t he low 16 bits are derived from the execution table above, and the high 4 bits are selected as a normal code fetch as described in the ?memory addressing? section. specifically, the ?cb1? bit is not touched by the interrupt. if the corresponding mask register bit is clear, the ?irq? bi t will not cause an interrupt. however, it can be polled by reading the ?irq? register.
data sheet RSC-4128 25 p/n 80-0206-j ? 2004 sensory inc. ?irq? bits can be cleared by writing a ?0? to the corresponding bi t at register fe (the ?irq? register). ?irq? bits cannot be set by writing to register fe. writing a ?1? to that register is a no-op. the ?irq? bits must be cleared within the interrupt handler by an explicit write to the ?irq? register rather than by an implicit interrupt acknowledge. please note: clear interrupts this way ? mov irq, #bitmask ; correct not this way ? and irq, #bitmask ; incorrect the ?and? instruction is not atomic. the ?and? instruction is a read-modify-write action. if an interrupt occurs during an ?and irq? operation the interrupt will be cleared before it is seen, possibly disabling the interrupt until the system is reset. because one cannot directly set or clear bits in the ?irq? register, use ?mov irq? as a safe, effective and atomic way to clear bits in the ?irq? register. use it the way you would use an ?and? instruction to operate on other registers. note: bit2 and bit5 of the ?irq? register should always be written as ?1? when clearing other ?irq? bits, to avoid conflicts with the technology code use of these bits. in idle mode, timer2 continues to operate even when the rest of the RSC-4128 is powered-down. an overflow from timer2 will set the corresponding ?irq? flag even when th ere is no clock input to the processor. note that the timer2 ?irq? bit (register fe.bit1) must be cleared prior to powering down to allow the wakeup interrupt request to occur. this may also lead to normal interrupt processing on ce the processor is active, if the timer 2 ?imr? bit is set (register fd.bit1). this interrupt response is un ique from, and may be in addition to, the t2 wakeup. analog input the analog front end (afe) for the RSC-4128 consists of a prea mplifier with gain control, a 16-bit analog-to-digital converter, digital decimator and channel filters, and associated references. a single analog input can be processed through the afe. all of this circuitry can be powered down to cons erve battery life by programming register ef.bit0 to ?0?. setting this bit to ?1? powers up the circuitr y, requiring a settling time of approximately 10milliseconds. the analog front end (afe) performs analog to digital c onversions on a low-level signals, which may be derived from an electret microphone. the microphone signal is am plified by a preamp that prov ides four levels of gain, which are selected by programming register d5.bits[4:3]. full-scale output for the four settings corresponds to input signals of 100, 50, 25, and 12.5 millivolts vpeak-peak, as shown in the table below. gain input referred noise max input signal ?sysctl? bits[4:3] vrms mvp-p mvrms 00 5.2* 100 35.4 01 4.9* 50 17.7 10 4.6* 25 8.8 11 4.4 12.5 4.4 input signals higher than specified will produce a saturated full scale output with no wrap around. a line level audio input must be attenuated to the range shown above for use with the afe.
RSC-4128 data sheet 26 p/n 80-0206-j ? 2004 sensory inc. digital transfer functions lowpass response detail of passband attenuation frequency min max below 8 khz 0 1.18 9.395 khz 3 db 20 khz 87.82 above 20 khz 53 note: a 1uf capacitor should be connected to ampcom and tied to gnd, a 2.2uf should be connected to vcm and tied to gnd, and a 0.1uf capacitor should be connected to vref and tied to gnd. failure to connect this capacitors will substantially degrade adc performance, and sensory speech 7 technology. a/d conversion the amplified signal is processed by a delta-sigma a/d conv erter that provides a 1-bit over-sampled digital signal. this digital stream is filtered and decimated to produce 16-bit samples at the fixed rate of 18,636 samples per second. the 16 bit signal will have about 12.5 bits of dynam ic range, with about 10 bits above the noise level. these samples are then provided to the RSC-4128 digital f ilter unit formatted as si gned two?s-complement 16-bit values. the samples are stored in the digital filter input registers ?adcsamplehi? (register f5) and ?adcsamplelo? (register f4). note: using the afe for general purposes other than as intended in sensory speech 7 technology modules may conflict with sensory speech 7. such conflicts may adversely impact sensory speech 7 functionality and/or the functionality of the general purpose app lication. care should be taken to av oid such conflicts. contact sensory technical support for help in this area. audio wakeup the audio wakeup unit is an analog/digital circuit that can be configured to wakeup from one of four specific audio events: 1) two handclaps, or any two sharp, closely spaced sounds 2) three handclaps, or any three sharp, closely spaced sounds 3) a whistle 4) any ?loud? sound above a specified amplitude, with duration options of 1 or 2 seconds
data sheet RSC-4128 27 p/n 80-0206-j ? 2004 sensory inc. because it is intended to ?listen? continuously at very low power levels, the audio wakeup unit must detect each of these events without any processor interaction. the pr ocessor configures and enables the unit under program control before going into idle mode. audio wakeup is not available in sleep mode because the unit requires the clk2 signal. the detection signal from the audio wakeup unit can trigger a wakeup event, which starts the processor and allows further audio processing. the proces sor inputs to the audio wakeup are an enable signal and control signals to select for which sound to listen. s ee schematic 1-3 for details on this implementation. schematic 1-3 c2 2.2uf (px.n is any available port i/o pin) r2 1.2k vdd gnd bt1 3v 1 2 avss vref r1 100 c5 100 -> 220uf example using one microphone for normal operation only mk1 microphone 1 2 c2 2.2uf r1 100 gnd rsc-4x vdd vref vdd c1 .1 avss micin1 c5 100 -> 220uf avdd c7 .1 c3 1uf px.n avdd mk1 microphone 1 2 c4 .1 ampcom gnd c8 .1 c3 1uf vcm (px.n is any available port i/o pin) micin2 c4 .1 r2 1.2k avdd example 1 vdd c6 .1 avdd ampcom avss rsc-4x example using one microphone for both audio wakeup and normal operation c7 .1 vdd c6 .1 avdd micin1 micin2 vcm c1 .1 px.n the RSC-4128 sensory speech 7 library contains routines fo r detecting each of the four audio events listed above. these routines also manage powerdown appropriately. see the ?s ensory speech 7 technology library manual? for reference code to invoke these routines. microphones a single electret microphone may be used both for the analog front-end input (for recognition purposes) and as the sound source for the audio wakeup unit. the current consumption and frequency response requirements are different for the two uses, so two microphone input pads ar e provided: micin1 for the normal recognition input to the analog front-end, and micin2 for the audio wakeup a nalog front end. a common microphone ground is used for both the normal recognition analog front-end and the audio wakeup analog front end. during normal recognition and audio wakeup operation, t he microphone would typically be powered from a source with an impedance in the range of 1-3 kohms. if bot h the normal recognition and audio wakeup front ends are used, they must be isolated from each other by capa citors and may share one microphone and microphone bias circuit. the switching of the microphone input source is un der program control. see schematic 1-3 for details on this implementation. the recommended value for the microphone filter capacitor (labeled ?c5? in schematic 1-3) is in the range of 100uf-220uf. using a capacitor at the upper end of this range will reduce low frequency noise. low frequency noise on the microphone input typically won?t affect recogniti on, but could affect the quality of speech playback when using record and playback technology in an applic ation. (see the ?sensory speech 7 technology library
RSC-4128 data sheet 28 p/n 80-0206-j ? 2004 sensory inc. manual? for more information on record and playback) typical low frequency noise sources include 60 hz hum, ?motor boating? or cyclical fluctuatio ns in the system power supply from ?sa gging? due to flash writes during speech recording, and led blinking during recording of speech. all of these effects are reduced in speech playback by using a capacitor closer to 220uf. note: see design notes - ?microphone housing? and ?sel ecting microphone? on the rsc-4x demo/evaluation cd. improper microphone circuit and/or enclosure des ign will result in poor recognition performance. reset an external reset is generated by applying a low conditi on for at least two clock cycles on -reset, an active low schmitt trigger input. the output of the schmitt trigger pass es through a 10 nsec glitch blocking circuit, followed by an asynchronous flip-flop. the output of the flip-flop generates active high reset throughout RSC-4128. the internal reset state is held for 20 msec (when clocked by a 14.32 mhz pclk). the purpose is to allow the oscillator to stabilize and the pll to lock before enabli ng the processor and the other RSC-4128 circuits. external reset clears the global interrupt enable flag an d begins execution at address 0h. the special function registers will be cleared, set, or left as-is, as detailed in the ?special function registers summary? section. watchdog timeout reset a special watchdog timeout reset is produced if the wa tchdog timer is enabled and the watchdog counter times out. the only difference between the watchdog timeout reset and an ordinary reset is that the ?wd_timed? bit in the ?sysstat? register (registe r fb.bit5) is preserved as ?1? for a watchdog timeout reset digital-to-analog-converter (dac) output the dac consists of an r-2r network with 10 bits of resolution and an output impedance of approximately 11 kohms. an external amplifier is required to drive a sp eaker when using the dac. the specifications of that amplifier will determine the best choice of speaker impedance and the resulting volume. the 10-bit resolution corresponds to an analog volta ge range between 0v and vdd minus 1 lsb (represented as ?vdd-?). at vdd=3v, one lsb of the r-2r network corresponds to about 3 mv. for example: r2r value dac output; vdd=3v 000h = 0v 0.000v 001h = 0v+ 0.003v 200h = vdd/2 1.500v 3ffh = vdd- 2.997v there are two dac output modes, full-sc ale and half-scale. in full-scale mode the output voltage swings between 0v and vdd-; in half-scale mode the output swings between vdd/4 and 3vdd/4 minus 1 lsb (roughly vdd/2 +/- vdd/4). values written into the dac hold register and ce rtain analog control register bi ts are converted into analog voltages. the dac hold register (?dac?; register fa) presents an 8-bit signed value to the dac unit. in full-scale mode, the 8 most significant bits are driven by the dac hold register and the 2 least significant bits are driven by the lsb1 and lsb0 bits in the analog control register (?anctl?; register ef.bits[5:4]). th is results in a total output range of ?512 to +511. in half-scale mode the 8 middle bits of are dr iven by the dac hold register, the most significant bit is generated automatically by sign extension, and the least signifi cant bit is driven by bit lsb1 in the analog control register. this gives a total output range of ?256 to +255. the half-scale mode is enabled by setting the mode bit (d2a_half) equal to ?1? in register ef.bit3. the tables below show a selection of values and the resulting output voltage. note: register ef.bit7 (?-anctlen?) must be ?0? in the value being written to register ef, when writing ef.bit2.
data sheet RSC-4128 29 p/n 80-0206-j ? 2004 sensory inc. full-scale mode (output range 0v to vdd- 1 lsb) decimal dac hold analog cntrl di gital input analog voltage output equivalent reg[7:0] (hex) [5:4] (b inary) general 0-3v (approx) -512 80h 00 000h 0v 0.000v -511 80h 01 001h 0v+ 1 lsb 0.003v -510 80h 10 002h 0.006v -509 80h 11 003h 0.009v -508 81h 00 004h 0.012v -2 ffh 10 1feh -1 ffh 11 1ffh vdd/2- 1 lsb 1.497v 0 00h 00 200h vdd/2 1.500v +1 00h 01 201h vdd/2+ 1lsb 1.503v +2 00h 10 202h +3 00h 11 203h +4 01h 00 204h +510 7fh 10 3feh 2.994v +511 7fh 11 3ffh vdd- 1lsb 2.997v the translation in full-scale mode is: r2r[9] = dac[7] inverted r2r[8:2] = dac[6:0] r2r[1:0] = anctl[5:4] half-scale mode (output range vdd/4 to 3vdd/4- 1 lsb) decimal dac hold analog cntrl di gital input analog voltage output equivalent reg[7:0] (hex) [5:4] (binary) general 0-3v (approx) -256 80h 0x 100h vdd/4 0.750v -255 80h 1x 101h vdd/4+ 1 lsb 0.753v -254 81h 0x 102h 0.756v -253 81h 1x 103h 0.759v -252 82h 0x 104h 0.762v -2 ffh 0x 1feh -1 ffh 1x 1ffh vdd/2- 1lsb 1.497v 0 00h 0x 200h vdd/2 1.500v +1 00h 1x 201h vdd/2+ 1lsb 1.503v +2 01h 0x 202h +3 01h 1x 203h +4 02h 0x 204h +254 7fh 0x 2feh 2.244v +255 7fh 1x 2ffh 3vdd/4-1 lsb 2.247v the translation in half-scale mode is: r2r[9] = dac[7] inverted r2r[8:1] = dac[7:0] r2r[0] = anctl[5] dac power control the dac has no explicit power control. it is turned off (p laced into lowest current mode) by loading the value 80h into the dac hold register, and 0 into the lsb1 and lsb0 bits of the analog control regist er (register ef.bits[5:4]). note: register ef.bit7 (?-anctl? must be ?0? in the value being written to register ef, when writing ef.bits[5:0].
RSC-4128 data sheet 30 p/n 80-0206-j ? 2004 sensory inc. pulse width modulator (pwm) analog output the pwm consists of circuitry to regulate the width of a pulse supplied to one of two outputs, pwm0 and pwm1, over a period of programmable duration. one or the othe r of the two outputs is held at ground and the other is driven with a pulse of programmable duration, giving ?p ush-pull? drive. both outputs have ?low shoot-thru? transistors to reduce radiated emi. once programmed, the pwm produces outputs co ntinuously until register values are changed. the pwm has both 8 and 10 bit modes. the pwm control register (?pwmctl?; register d7) contains the pwm on/off control (bit0), the sample period (b its[3:2]), sample size sele ction controls (bit5), and the two least-significant bits of the 10-bit output value (bits[7:6]). the sample si ze defaults to 8 bits, with register d7.bit5=0 (?tenbits?). a sample size of 10 bits is se lected by setting ?tenbits? =1. the pwm output impedance is approximately 11 ohms. of the standard speaker impedances available, an 8 ohm speaker will provide optimal volume when driven by the pwm. the pwm contains two counters. the data value counte r is programmed with the value programmed in the ?pwmdata? register (register d8) in 8-bit mode. in 10 -bit mode the data value counter uses ?pwmdata? and appends bits[7:6] of ?pwmctl? as the least significant two bi ts to create a 10 bit value. output data always lags input by one pwm sample period. the sample period counter is fixed and counts to 128. the prescaler in the pwm control register (register d7.bits[3:2] ) determines the clock for both the dat a value counter and the sample period counter. the prescaler divides the 14. 3 mhz clock by 4,6, or 7, resulting in a pwm frequency of 27.9 khz, 18.6khz and 15.97 khz, respectively. the pwm restarts every samp le period, at which time either pwm0 or pwm1 pulses high. the selected signal pulses high for a duration deter mined by the data value and then returns low. the non- selected signal remains low. the pulsed output selection is controlled by the sign of the data. when bit 7 of the ?pwmdata? register is 0, pwm0 pulses high while pwm1 re mains 0. when bit 7 of the ?pwmdata? register is 1, pwm1 pulses high while pwm0 remains low. when the data value in ?pwmdata? is 0, both signals remain low. when the sample period count selected by programming bi ts[3:2] of the ?pwmctl? register d7.bit has been reached, the pwm restarts. the pwm hardware sample period and the software data value updating must be synchronized to avoid aliasing. the following table shows the rates and pulse durations obtained for 8-bit mode (?tenbits? programmed to ?0?) software note: ?full scale? output for all prescaler values is obtained by setting the data value to 7fh, so 8-bit signed data can be output at any of the th ree rates without amplitude adjustment. pwm timing for ?tenbits?=0 item prescaler=4 prescaler=6 prescaler=7 nsec/clock (period clock) 280 420 490 clk1 clocks per period 512 768 896 nsec/clock (sample clock) 280 420 490 pwm frequency 27.9 khz 18.6 khz 15.97 khz pulse for data=01 4 h / 508 l 6 h / 762 l 7 h / 889 l pulse for data=7f 508 h / 4l 762 h / 6 l 889 h / 7 l for 10-bit mode (?tenbits? programmed to ?1?), the sample period counter counts a full 7- bits (128 counts), exactly as when tenbits is 0. the 14.3 mhz clock is divided by the prescaler value and supplied to the sample period counter. the data value counter is clocked by the 14.3 clock divided by 2 for prescaler values 6 or 7, and is clocked directly by the 14.3 mhz clock when the prescaler val ue is 4. table yy shows the rates and pulse durations obtained with tenbits set to 1. software note: ?full scale? output is obtained with a differen t data value for each prescaler value. only prescaler=4 supports a full 9- bit count (512), so true 10-bit signed data can be output only with prescaler=4. otherwise the amplitudes mu st be adjusted to have maximum amplitude of 447 (prescaler=7) or 383 (prescaler=6). see ?additional c onsiderations using the pwm for 10-bit data? below.
data sheet RSC-4128 31 p/n 80-0206-j ? 2004 sensory inc. pwm timing for tenbits=1 item prescaler=4 prescaler=6 prescaler=7 nsec/clock (period ctr) 280 420 490 clk1 clocks per period 512 768 896 nsec/clock (data ctr) 70 140 140 pwm frequency 27.9 khz 18.6 khz 15.97 khz pulse for data=001 1 h / 511 l 2 h / 766 l 2 h / 894 l pulse for data=17f 383 h / 129 l 766 h / 2 l 766 h / 130 l pulse for data=1bf 447 h / 65 l -- n/a -- 894 h / 2 l pulse for data=1ff 511 h / 1 l -- n/a -- -- n/a -- additional considerations using the pwm for 10-bit data the 14.3 mhz clk1 clock rate of the RSC-4128 is not fast enough to provide pwm synchronization with 10-bit 8khz or 9.3 khz data. to understand this, consider a pwm rate of 8 khz (125 microsec). to output 10 bits (9 bits plus sign) during this interval, a source must provide 51 2 clocks, giving a source rate of 125000/512 = 244 nsec. the clk1 period is 70 nsec, so the relationship between the source clock and clk1 is 244/70 = 3.5, which is not an integer. so the source clock cannot be derived simply from clk1. the RSC-4128 application developer should address this issu e by using a ?near-10-bit? resolution, as follows. the tenbits bit is set in the ?pwmctl? register, and the prescaler is programmed to 7 to produce a pwm frequency of 15.98 khz (62.57 microseconds). during this interval t here will be 62570/70 = 894 clk1 clocks, or 894/2 (=447) data counter clocks. the number 447 thus represents t he largest possible count that can be loaded into the data value counter. the range of allowable values is from ?447 to +447. any larger value would produce the same output of the pwm pulse ?on? for the entire duration of th e pwm period. thus 447 represents ?full scale? of the pwm. if all 10-bit data values are then scaled to a maximu m of +/-447, the pwm will provide full-scale swing and (close-enough) synchronization at 8 khz. the actual number of bits in the data is log2(447 ? (-447)) = 9.8 bits. the developer must ensure that the value programmed in t he data value counter must not exceed the range of ?447 to +447. sensory speech 7 provides pwm output utilit ies for speech and music that manage the pwm for the developer, if so desired. (see ?sensory speech 7 technology library manual?) pwm powerdown the pwm may be independently powered down by programmin g the register d7.bit 0 to ?0? (?pwmctl? register, ?pwm_on? bit). when the pwm is off, the pwm outputs pw m0 and pwm1 are in a high -z state and pulled up by internal 10k resistors. the pwm must be explicitly tur ned off before setting ?pdn? equal to 1 to achieve the lowest powerdown current. comparator unit the comparator unit consists of 2 analog comparators designated ?a? and ?b?, a programmable voltage reference, selection circuitry, and two registers ? the comparator c ontrol register (?cmpctl?) and the comparator reference (?cmpref?). register ?cmpctl? configures the comparator unit and provides the digital comparator outputs. bits [2:0] are used to select from one of eight co mparator configurations, in which some or all of p2.0-p2.4 may be analog or digital inputs. (see ?RSC-4128 comparator unit? figure; ?a ? denotes analog input and ?d? denotes digital input) bits [3:0] are read-write. register ?cmpref? controls the comparator referenc e voltage. the unit can provide level information under software control about 4 external analog signals. all ex ternal signals connected to the comparator inputs must be between vss and vdd.
RSC-4128 data sheet 32 p/n 80-0206-j ? 2004 sensory inc. each comparator has two analog inputs, designated ?+? and ?-?, and one digital output. when the analog voltage on the ?+? input is greater than the analog voltage on the ?-? input, the digital output is a high level. this is indicated by a ?1? in the ?cmpctl? register (register d4) bits 7 & 6 for comparators a and b, respectively. when the analog voltage on the ?+? input is less than the analog voltage on the ?-? input, the digital output is a low level. th is is indicated by a ?0? in the ?cmpctl? register (register d4 ) bits 7 & 6 for comparators a and b, respectively. bits 7 and 6 are the comparator outputs and are ?read-only? by the processor. each comparator can be separately enabled or disabled. when a comparator is disabled, both inputs are isolated from any circuitry common to both comparators, the inputs are grounded, and the comparator power is turned off. comparator multiplexing each comparator ?+? input has an analog multiplexer that selects between one of two external signals. when bit3 of ?cmpctl? is programmed to ?0?, comparator input a+ is multiplexed to p2.0 and input b+ is multiplexed to p2.1. when bit3 of ?cmpctl? is programmed to ?1?, comparator input a+ is multiplexed to p2.3 and input b+ is multiplexed to p2.4. the ?-? inputs of both comparators are connected together. this common ?-? input can be multiplexed to either an external comparator reference signal input through p2.2, or the comparator reference voltage (crv). comparator reference voltage the internal comparator reference voltage (crv) is deriv ed from a multi-tap resistive divider and a 4-bit analog multiplexer. register ?cmpref? controls the comparat or reference voltage. the power for the comparator reference voltage is provided by unregulated vdd. this m eans that the crv will track external voltages referenced from the system supply, giving consistent comparisons as the system supply drops. power to the crv is gated by decoding the comparator confi guration. the voltage select value in ?cmp ref? bits[3:0] selects one of 16 outputs of an analog multiplexer connected to 16 equally spaced taps . the comparator reference voltage covers the range from 0.15*vdd to 0.90*vdd in steps of 0.05*vdd and is given by 0.15*v dd + (d3[3:0]/20)*vdd. in some configurations the comparator control register can be set up once and simply read thereafter. in many configurations it will be necessary to switch the input multiplexers and/ or re-program the reference voltage repeatedly. these multiplexing and selection operations w ill have settling times of approximately 10 microseconds. when the ?pdn? bit is set for idle or sleep mode the entire comparator unit is powered down, but the contents of the ?cmpctl? and ?cmpref? registers ar e preserved. when the RSC-4128 wakes up the comparators resume normal operation. a a p2.0 a p2.3 b a p2.1 a p2.4 a p2.2 cmpctl=010 a a p2.0 a p2.3 b d p2.1 d p2.4 a p2.2 off cmpctl=100 a a p2.0 a p2.3 b a p2.1 a p2.4 d p2.2 ivref cmpctl=001 a d p2.0 d p2.3 off b a p2.1 a p2.4 a p2.2 cmpctl=110 cmpctl=101 a d p2.0 d p2.3 off b a p2.1 a p2.4 d p2.2 ivref a a p2.0 a p2.3 b d p2.1 d p2.4 d p2.2 ivref off cmpctl=011 a a p2.0 a p2.3 b a p2.1 a p2.4 off off a p2.2 cmpctl=000 a d p2.0 d p2.3 b d p2.1 d p2.4 off off d p2.2 cmpctl=111 RSC-4128 comparator unit
data sheet RSC-4128 33 p/n 80-0206-j ? 2004 sensory inc. instruction set opcodes and timing details the RSC-4128 instruction set has 60 instructions comprising 13 move, 7 rotate/shift, 11 jump /branch, 13 register arithmetic, 9 immediate arithmetic, and 7 miscellaneous inst ructions. all instructions are 3 bytes or fewer, and no instruction requires more than 10 clock cy cles (plus wait states) to execute. the column ?cycles? indicates the number of clock cycles required for ea ch instruction when operating with ze ro wait states. wait states may be added to lengthen all accesses to external addresses or to the internal rom (but not internal sram). the column ?+cycles/waitstate? shows the number of additional cycles added for each addi tional wait state. opcodes are in hex. move group instructions register-indirect instructions accessing code ( movc ), data ( movx ), technology ( movy ) or register ( mov ) space locations use an 8-bit operand (?@source? or ?@dest?) to de signate an sram register pointer to the 16-bit target address. the ?source? or ?dest? indirect pointer regist er must be at an even address un less it is a 8-bit pointer (indirect mov ). the low byte of the target address is contained at the pointer address, a nd the high byte of the target address is contained at the pointer address+1. unless the flags register is the destination, the carry, sign, and zero flags are not affected by mov instructions. instruction opcode operand 1 operand 2 description bytes cycles +cycles/waitstate mov 10 dest source register to register 3 5 3 mov 11 @dest source register to register-indirect 3 5 3 mov 12 dest @source register-indirect to register 3 6 3 mov 13 dest #immed immediate data to register 3 4 3 movc 14 dest @source code space to register 3 7 4 movc 15 @dest source register to code space 3 8 4 movx 16 dest @source data space to register 3 7 4* movx 17 @dest source register to data space 3 8 4* pop 18 dest @++source register to register data stack pop (source pre- incremented) 3 10 3 push 19 @dest-- source register to register data stack push (dest post- decremented) 3 9 3 movy 1a dest @source ramy to register, indirect 3 7 3 movy 1b @dest source register to ramy, indirect 3 7 3 movd 1c dest_pair source_pair register to register, direct, 16-bit mov 3 7 3 * if register d6.bit 5=1 (movx_4ws) and exte rnal read/write memory is selected by setting the ?rw? bit (register d2.bit4), movx instructions have four additional wait states.
RSC-4128 data sheet 34 p/n 80-0206-j ? 2004 sensory inc. rotate group instructions rotate group instructions apply only directly to register sp ace sram locations. the carry flag is affected by these instructions, but the sign and zero flags are unaffected. instruction opcode operand 1 operand 2 description bytes cycles +cycles/waitstate rl 30 dest - rotate left, c set from b7 2 5 2 rr 31 dest - rotate right, c set from b0 2 5 2 rlc 32 dest - rotate left through carry 2 5 2 rrc 33 dest - rotate right through carry 2 5 2 shl 34 dest - shift left, c set from b7, b0=0 2 5 2 shr 35 dest - shift right, c set from b0, b7=0 2 5 2 sar 36 dest - shift right arithmetic, c set from b0, b7 duplicated 2 5 2 branch group instructions the branch instructions use direct address values rather than offsets to define the target address of the branch. this implies that binary code containing branches is not relocatable. however, object code produced by the rsc- 4128 assembler contains address references that are resolved at link time, so .obj modules are relocatable. the indirect jump instruction uses an 8-bit operand (?@dest?) to designate an sram register pointer to the 16-bit target address. the ?dest? pointer register must be at an even address. the low byte of the target address is contained at the pointer address, and t he high byte of the target address is contained at the pointer address+1. instruction opcode operand 1 operand 2 description bytes cycles +cycles/waitstate jc 20 dest low dest high jump on carry = 1 3 3 3 jnc 21 dest low dest high jump on carry = 0 3 3 3 jz 22 dest low dest high jump on zflag = 1 3 3 3 jnz 23 dest low dest high jump on zflag = 0 3 3 3 js 24 dest low dest high jump on sflag = 1 3 3 3 jns 25 dest low dest high jump on sflag = 0 3 3 3 jmp 26 dest low dest high jump unconditional 3 3 3 call 27 dest low dest high direct subroutine call 3 3 3 ret 28 - - return from call 1 2 1 iret 29 - - return from interrupt 1 2 1 jmpr 2a @dest - jump indirect 2 4 2 arithmetic/logical group instructions arithmetic and logical group instructions apply only to register space sram locations. the results of the instruction are always written directly to the sram ?dest? register. the exceptions are tm and cp instructions, which do not write the result to the ?dest? register and only update the flags regist er based on the operation?s outcome. all but the increment and decrement instructio ns have both register s ource and immediate source forms. in each of the following instructions the sign and zero flags are updated based on the result of the operation. the carry flag is updated by the arithmetic operations (a dd, adc, sub, subc, cp, inc, dec) but it is not affected by the logical operations (and, tm, or, xor). note: the carry is set high by sub, cp, subc and dec when a borrow is generated.
data sheet RSC-4128 35 p/n 80-0206-j ? 2004 sensory inc. instruction opcode operand 1 operand 2 description bytes cycles +cycles/waitstate and 40 dest source logical and 3 6 3 tm 41 dest source like and, destination register unchanged 3 6 3 or 42 dest source logical or 3 6 3 xor 43 dest source exclusive or 3 6 3 sub 44 dest source subtract 3 6 3 cp 45 dest source like sub, destination register unchanged 3 6 3 subc 46 dest source subtract w/carry 3 6 3 add 47 dest source add 3 6 3 adc 48 dest source add w/carry 3 6 3 inc 49 dest - increment 2 5 2 dec 4a dest - decrement 2 5 2 and 50 dest #immed logical and 3 5 3 tm 51 dest #immed like and, destination register unchanged 3 5 3 or 52 dest #immed logical or 3 5 3 xor 53 dest #immed exclusive or 3 5 3 sub 54 dest #immed subtract 3 5 3 cp 55 dest #immed like sub, destination register unchanged 3 5 3 subc 56 dest #immed subtract w/carry 3 5 3 add 57 dest #immed add 3 5 3 adc 58 dest #immed add w/carry 3 5 3 incd 69 dest_pair & source_pair - register pair 16-bit increment 2 8 2 cpd 66 dest_pair source_pair 16-bit compare 3 10 3 miscellaneous group instructions instruction opcode operand 1 operand 2 description bytes cycles +cycles/waitstate nop 00 - - no operation 1 2 1 clc 01 - - clear carry 1 2 1 stc 02 - - set carry 1 2 1 cmc 03 - - complement carry 1 2 1 cli 04 - - disable interrupts 1 2 1 sti 05 - - enable interrupts 1 2 1 wdc 06 - - enable/restart watchdog timer 1 2 1
RSC-4128 data sheet 36 p/n 80-0206-j ? 2004 sensory inc. special functions registers (sfrs) summary address r/w name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff r/w flags ***** 0000 0000 carry zero sign trap stkoflo stkfull --- gie fe r/w irq * 0000 0000 mttimer p0.2 block timer3 p0.0 endmark timer2 timer1 fd r/w imr **** 0000 0000 mttimer p0.2 block timer3 p0.0 endmark timer2 timer1 fc r/w bank 1110 0000 ws2 ws1 ws0 (bank4) bank3 bank2 bank1 bank0 fb w reserved r sysstat 0000 0000 0 brownout wd_timed wd_on 0 0 fastclk 0 fa r/w dac 0000 0000 dh7 dh6 dh5 dh4 dh3 dh2 dh1 dh0 f9 r/w reserved f8 r/w reserved f7 r/w stkdata 0000 0000 stdk7 stkd6 stkd5 stkd4 stkd3 stkd2 stkd1 stkd0 f6 r/w stkndx 0000 0000 0 0 stkind5 stkind4 stkind3 stkind2 stkind1 stkind0 f5 w reserved r adcsamplehi 0000 0000 adc15 adc14 adc13 adc12 adc11 adc10 adc09 adc08 f4 w reserved r adcsamplelo 0000 0000 adc07 adc06 adc05 adc04 adc03 adc02 adc01 adc00 f3 r/w reserved f2 r/w reserved f1 w reserved r reserved f0 r/w reserved ef w anctl *** 0000 0000 -anctlen 0 lsb1 lsb0 d2a_half rc_osc2 0 afe_on r 0000 0000 -anctlen 0 lsb1 lsb0 d2a_half rc_osc2 0 afe_on ee w t2v ** 0000 0000 x x x x x x x x r 0000 0000 t2v7 t2v6 t2v5 t2v4 t2v3 t2v2 t2v1 t2v0 ed r/w t2r 0000 0000 t2r7 t2r6 t2r5 t2r4 t2r3 y2r2 t2r1 t2r0 ec w t1v ** 0000 0000 x x x x x x x x r 0000 0000 t1v7 t1v6 t1v5 t1v4 t1v3 t1v2 t1v1 t1v0 eb r/w t1r 0000 0000 t1r7 t1r6 t1r5 t1r4 t1r3 t1r2 t1r1 t1r0 ea r/w wake1 0000 0000 w1.7 w1.6 w1.5 w1.4 w1.3 w1.2 w1.1 w1.0 e9 r/w wake0 0000 0000 w0.7 w0.6 w0.5 w0.4 w0.3 w0.2 w0.1 w0.0 e8 r/w ckctl **** 0000 1000 pdn t2wake fclk_on clk_div1 clk_div0 slow_pclk osc2_on osc1_off e7 r/w p0ctlb 0000 0000 ctlb0.7 ctlb0.6 ctlb0.5 ctlb0.4 ctlb0.3 ctlb0.2 ctlb0.1 ctlb0.0 e6 r/w p0ctla 0000 0000 ctla0.7 ctla0.6 ctla0.5 ctla0.4 ctla0.3 ctla0.2 ctla0.1 ctla0.0 e5 r p0in xxxx xxxx pin0.7 pin0.6 pin0.5 pin0.4 pin0.3 pin0.2 pin0.1 pin0.0 e4 r/w p0out 0000 0000 pout0.7 pout0.6 pout0.5 pout0.4 pout0.3 pout0.2 pout0.1 pout0.0 e3 r/w p1ctlb 0000 0000 ctlb1.7 ctlb1.6 ctlb1.5 ctlb1.4 ctlb1.3 ctlb1.2 ctlb1.1 ctlb1.0 e2 r/w p1ctla 0000 0000 ctla1.7 ctla1.6 ctla1.5 ctla1.4 ctla1.3 ctla1.2 ctla1.1 ctla1.0 e1 r p1in xxxx xxxx pin1.7 pin1.6 pin1.5 pin1.4 pin1.3 pin1.2 pin1.1 pin1.0 e0 r/w p1out 0000 0000 pout1.7 pout1.6 pout1.5 pout1.4 pout1.3 pout1.2 pout1.1 pout1.0 df r/w p2ctlb 0000 0000 ctlb2.7 ctlb2.6 ctlb2.5 ctlb2.4 ctlb2.3 ctlb2.2 ctlb2.1 ctlb2.0 de r/w p2ctla 0000 0000 ctla2.7 ctla2.6 ctla2.5 ctla2.4 ctla2.3 ctla2.2 ctla2.1 ctla2.0 dd r p2in xxxx xxxx pin2.7 pin2.6 pin2.5 pin2.4 pin2.3 pin2.2 pin2.1 pin2.0 dc r/w p2out 0000 0000 pout2.7 pout2.6 pout2.5 pout2.4 pout2.3 pout2.2 pout2.1 pout2.0 db w t3v ** 0000 0000 x x x x x x x x r 0000 0000 t3v7 t3v6 t3v5 t3v4 t3v3 t3v2 t3v1 t3v0 da r/w t3r 0000 0000 t3r7 t3r6 t3r5 t3r4 t3r3 t3r2 t3r1 t3r0 d9 w t3ctl 0000 0000 t3_on polarity p0.1_src t3_gated t3_ps3 t3_ps2 t3_ps1 t3_ps0 d8 r/w pwmdata 0000 0000 pwmd09 pwmd08 pwmd07 pwmd06 pwmd05 pwmd04 pwmd03 pwmd02 d7 r/w pwmctl 0000 0000 pwmd01 pwmd00 tenbits 0 period1 period0 0 pwm_on d6 r/w clkext **** 0000 0000 rom_0ws mtclk_on movx_4ws l1clk_on t1_ps3 t1_ps2 t1_ps1 t1_ps0 d5 r/w sysctl 0000 0000 wd_ps1 wd_ps0 brnout_on afe_g1 afe_g0 0 p02edge p00edge d4 w cmpctl 1100 0000 1 1 0 0 mux_sel ccs2 ccs1 ccs0 r 1100 0000 compa+ compb+ 0 0 mux_sel ccs2 ccs1 ccs0 d3 r/w cmpref 0000 0000 0 0 0 0 crv03 crv02 crv01 crv00 d2 r/w extadd 0000 0000 0 0 cb1 rw eda19 eda18 eda17 eda16 d1 r/w reserved d0 r/w reserved cf r/w flagshold ***** 0000 0000 carry zero sign trap 0 0 0 gie ce w awcctl 0000 0000 pwrl 0 thrh2 thrh1 thrh0 thrl2 thrl1 thrl0
data sheet RSC-4128 37 p/n 80-0206-j ? 2004 sensory inc. address r/w name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r 0000 0000 pwrl detect thrh2 thrh1 thrh0 thrl2 thrl1 thrl0 cd w reserved r reserved cc reserved cb reserved ca reserved c9 reserved c8 reserved reserved c7 reserved c6 reserved c5 reserved c4 reserved c3 reserved reserved c2 reserved reserved c1 reserved reserved c0 reserved reserved reset: ?x? = unknown/don?t care, ? - ? = not implemented * only ?0? can be written to ?irq? bits. ?1? is a ?nop? for the bit to which it is written. when using sensory speech technol ogy, always write ?1? to ?block? and ?endmark? in the ?irq? register to avoi d conflicting with technology code control of these bits. ** write value is ignored and reload register value is written instead. *** -anctlen (bit7) of values written to t he ?anctl? register must be ?0? to enable writ ing the other bits in the value to ?anc tl?. **** when using sensory speech technology, ?fclk_on?, ?l1clk_on?, and ?block? and ?endmark? in the ?imr? register should be lef t at the values programmed by the technology code. a read-modify-write action should be used to modify the registers to avoid changing t hese bits. ***** ?trap? must always be written as ?0? in the ?flags? and ?flagshold? registers
RSC-4128 data sheet 38 p/n 80-0206-j ? 2004 sensory inc. dc characteristics operating conditions (t o = 0c to +70c, v dd = 2.4v ? 3.6v) symbol parameter min typ max units test conditions v il input low voltage -0.1 0.75 v v ih input high voltage 0.8*vdd vdd+0.3 v i il input leakage current <1 10 a v ss data sheet RSC-4128 39 p/n 80-0206-j ? 2004 sensory inc. timing diagrams note that the -rdr signal does not necessarily pulse for every read from co de space, but may stay low for multiple cycles. address -rdf (-rdr) data -wrc (-wrd) trlrh trlav travdv trhdx twlwh address tavwl talrax talwax twdvav twhqx data external read timing external write timing absolute maximum ratings any pin to gnd: -0.1v to +4.0v storage temperature: -65c to +150c operating temperature: -40c to +85c soldering temperature: 260c for 10 sec power dissipation: 1 w warning : stressing the RSC-4128 beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability.
RSC-4128 data sheet 40 p/n 80-0206-j ? 2004 sensory inc. package options the RSC-4128 can be purchased in 100-lead lqfp or 64 le ad lqfp packages, or in unpackaged die. when using an in circuit emulator (ice) on dice applications, a cob bonding pad ring equivalent to a 100-lead lqfp footprint is advised for easy ice adapter attachment. die 1 29 30 52 53 82 100 RSC-4128 (100 pad die) logo 64-lead lqfp RSC-4128 (64-lead lqfp) 17 18 19 20 21 22 23 24 32 dacout avss vcm micin2 micin1 micgnd vref avdd test 25 26 27 28 29 30 31 p2.4 p2.3 p2.2 p2.1 p2.0 gnd vdd p0.7 nc p1.0 vdd gnd p1.1 nc p1.2 p1,3 p1.4 p1.5 pllen 48 47 46 45 44 43 42 41 40 39 38 33 vdd 37 gnd p1.6 p1.7 36 35 34 64 63 62 61 60 59 58 57 56 55 54 53 nc p0.1 nc p0.2 p0.3 nc vdd pwm1 pwm0 gnd nc p0.4 52 51 50 49 p0.5 nc p0.6 nc p0.0 nc pdn gnd xo1 xi1 vdd xo2 xi2 p2.7 nc gnd 1 2 3 4 5 6 7 8 9 10 11 12 vdd p2.6 p2.5 reset_ 13 14 15 16 100-lead lqfp RSC-4128 (100-lead lqfp) 75 74 73 72 71 70 69 68 67 66 65 60 59 58 57 56 55 54 53 64 63 62 61 52 51 26 27 28 29 30 31 32 33 41 42 43 44 45 34 35 36 37 38 39 40 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 81 nc a0 p0.1 nc a1 p0.2 a2 nc p0.3 a3 nc vdd a5 88 87 86 85 84 83 82 pwm1 pwm0 gnd nc a4 p0.4 nc 80 79 78 77 76 p0.5 nc a6 p0.6 nc 1 2 3 4 5 6 7 8 9 10 11 12 20 13 14 15 16 17 18 19 21 22 23 24 25 p0.0 d7 d6 pdn d5 d4 gnd xo1 xi1 vdd -xm xo2 vdd xi2 d3 d2 p2.7 d1 d0 gnd p2.6 reserved p2.5 reserved -reset dacout avss vcm micin2 micin1 ampcom vref avdd nc p2.1 p2.0 gnd vdd p2.4 p2.3 nc p2.2 gnd -rdf -wrd -rdr -wrc a19 a18 test p0.7 a7 a8 p1.0 a9 vdd gnd a10 p1.1 a11 p1.2 a14 p1.5 a15 vdd gnd p1.6 a16 p1.7 a12 p1.3 a13 p1.4 a17 pllen die pad # 64 lqfp pin # 100 lqfp pin # pin name description signal type 1 1 1 p0.0 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 2 2=nc 2 d7 external data bus (no connect for 64-lead lqfp) i/o, 100k pull-up; high-z 3 - 3 d6 external data bus i/o, 100k pull-up; high-z 4 3 4 pdn power down (active high when powered down) output 5 - 5 d5 external data bus i/o, 100k pull-up; high-z 6 - 6 d4 external data bus i/o, 100k pull-up; high-z 7 4 7 gnd ground gnd 8 4 7 gnd ground gnd 9 5 8 xo1 oscillator 1 output output 10 6 9 xi1 oscillator 1 input input 11 7 10 vdd supply voltage pwr 12 7 10 vdd supply voltage pwr 13 - 11 -xm external memory enable (active lo w) input, 10k pull-up resistor 14 8 12 xo2 oscillator 2 output output 15 9 13 xi2 oscillator 2 input input 16 - 14 d3 external data bus i/o, 100k pull-up; high-z 17 - 15 d2 external data bus i/o, 100k pull-up; high-z 18 10 16 p2.7 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 19 11=nc 17 d1 external data bus (no connect for 64-lead lqfp) i/o, 100k pull-up; high-z 20 - 18 d0 external data bus i/o, 100k pull-up; high-z 21 12 19 gnd ground gnd 22 12 19 gnd ground gnd 23 13 20 vdd supply voltage pwr 24 13 20 vdd supply voltage pwr 25 14 21 p2.6 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 26 - 22 reserved do not use do not use 27 15 23 p2.5 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 28 - 24 reserved do not use do not use 29 16 25 -reset reset (active low) input, 100k pull-up resistor 30 17 26 dacout dac output analog out 31 18 27 avss analog ground (a) gnd 32 19 28 vcm common mode reference analog 33 20 29 micin2 microphone input for audio wakeup analog in 34 21 30 micin1 microphone input analog in
data sheet RSC-4128 41 p/n 80-0206-j ? 2004 sensory inc. die pad # 64 lqfp pin # 100 lqfp pin # pin name description signal type 35 22 31 ampcom amplifier input common analog in 36 23 32 vref voltage reference analog out 37 24 33 avdd analog supply voltage (a) pwr - 34 nc not connected 38 25 35 p2.4 general purpose i/o or comparator input i/o, 10k or 200k pull-up resistor; high-z 39 26 36 p2.3 general purpose i/o or comparator input i/o, 10k or 200k pull-up resistor; high-z - - 37 nc not connected 40 27 38 p2.2 general purpose i/o or comparator refer ence i/o, 10k or 200k pull-up resistor; high-z 41 - 39 gnd ground gnd 42 28 40 p2.1 general purpose i/o or comparator input i/o, 10k or 200k pull-up resistor; high-z 43 29 41 p2.0 general purpose i/o or comparator input i/o, 10k or 200k pull-up resistor; high-z 44 30 42 gnd ground gnd 45 31 43 vdd supply voltage pwr 46 - 44 -rdf external data read strobe (active low) output, 100k pull-up resistor; high-z 47 - 45 -wrd external data write strobe (active low) output, 100k pull-up resistor; high-z 48 - 46 -rdr external code read strobe (active low) output, 100k pull-up resistor; high-z 49 - 47 -wrc external code write strobe (active low) output, 100k pull-up resistor; high-z 50 - 48 a19 external memory address bus out put, 100k pull-up resistor; high-z 51 - 49 a18 external memory address bus out put, 100k pull-up resistor; high-z 52 32 50 test test mode input, 10k pull-down resistor 53 33 51 pllen pll enable input, 100k pull-up resistor 54 - 52 a17 external memory address bus out put, 100k pull-up resistor; high-z 55 34 53 p1.7 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 56 - 54 a16 external memory address bus out put, 100k pull-up resistor; high-z 57 35 55 p1.6 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 58 36 56 gnd ground gnd 59 36 56 gnd ground gnd 60 37 57 vdd supply voltage pwr 61 37 57 vdd supply voltage pwr 62 - 58 a15 external memory address bus out put, 100k pull-up resistor; high-z 63 38 59 p1.5 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 64 - 60 a14 external memory address bus out put, 100k pull-up resistor; high-z 65 39 61 p1.4 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 66 - 62 a13 external memory address bus out put, 100k pull-up resistor; high-z 67 40 63 p1.3 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 68 - 64 a12 external memory address bus out put, 100k pull-up resistor; high-z 69 41 65 p1.2 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 70 42=nc 66 a11 external memory address bus (nc for 64-lead lqfp) output, 100k pull-up resistor; high-z 71 43 67 p1.1 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 72 - 68 a10 external memory address bus out put, 100k pull-up resistor; high-z 73 44 69 gnd ground gnd 74 44 69 gnd ground gnd 75 45 70 vdd supply voltage pwr 76 45 70 vdd supply voltage pwr 77 - 71 a9 external memory address bus out put, 100k pull-up resistor; high-z 78 46 72 p1.0 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 79 - 73 a8 external memory address bus out put, 100k pull-up resistor; high-z 80 47=nc 74 a7 external memory address bus (nc for 64-lead lqfp) output, 100k pull-up resistor; high-z 81 48 75 p0.7 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z - 49=nc 76 nc not connected 82 50 77 p0.6 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 83 - 78 a6 external memory address bus (nc for 64-lead lqfp) output, 100k pull-up resistor; high-z - 51=nc 79 nc not connected 84 52 80 p0.5 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 85 - 81 a5 external memory address bus out put, 100k pull-up resistor; high-z - - 82 nc not connected 86 53 83 p0.4 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 87 - 84 a4 external memory address bus (nc for 64-lead lqfp) output, 100k pull-up resistor; high-z - 54=nc 85 nc not connected 88 55 86 gnd ground gnd 89 55 86 gnd ground gnd 90 56 87 pwm0 pulse width modulator output 0 output; 10k pull-up resistor; high-z 91 57 88 pwm1 pulse width modulator output 1 output; 10k pull-up resistor; high-z 92 58 89 vdd supply voltage pwr 93 58 89 vdd supply voltage pwr - 59=nc 90 nc not connected 94 - 91 a3 external memory address bus (nc for 64-lead lqfp) output, 100k pull-up resistor; high-z
RSC-4128 data sheet 42 p/n 80-0206-j ? 2004 sensory inc. die pad # 64 lqfp pin # 100 lqfp pin # pin name description signal type 95 60 92 p0.3 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z - - 93 nc not connected 96 - 94 a2 external memory address bus out put, 100k pull-up resistor; high-z 97 61 95 p0.2 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 98 - 96 a1 external memory address bus (nc for 64-lead lqfp) output, 100k pull-up resistor; high-z - 62=nc 97 nc not connected 99 63 98 p0.1 general purpose i/o that can act as a ?wake- up? input i/o, 10k or 200k pull-up resistor; high-z 100 - 99 a0 external memory address bus (nc for 64-lead lqfp) output, 100k pull-up resistor; high-z - 64=nc 100 nc not connected
data sheet RSC-4128 43 p/n 80-0206-j ? 2004 sensory inc. die pad ring a0 p0.1 a1 p0.2 a2 p0.3 a3 vdd vdd pwm1 pwm0 gnd gnd a4 p0.4 a5 p0.5 a6 p0.6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 p0.0 1 81 p0.7 d7 2 80 a7 d6 3 79 a8 pdn 4 78 p1.0 d5 5 77 a9 d4 6 76 vdd gnd 7 75 vdd gnd 8 74 gnd xo1 9 73 gnd xi1 10 72 a10 vdd 11 71 p1.1 vdd 12 70 a11 -xm 13 69 p1.2 xo2 14 68 a12 xi2 15 67 p1.3 d3 16 66 a13 d2 17 65 p1.4 p2.7 18 64 a14 d1 19 63 p1.5 d0 20 62 a15 gnd 21 61 vdd gnd 22 60 vdd vdd 23 59 gnd vdd 24 58 gnd p2.6 25 57 p1.6 reserved 26 56 a16 p2.5 27 55 p1.7 reserved 28 54 a17 -reset 29 53 pllen 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 dacout avss vcm micin2 micin1 ampcom vref avdd p2.4 p2.3 p2.2 gnd p2.1 p2.0 gnd vdd -rdf -wrd -rdr -wrc a19 a18 test
RSC-4128 data sheet 44 p/n 80-0206-j ? 2004 sensory inc. RSC-4128 die bonding pad locations pad # padname x (um) y (um) pad # padname x (um) y (u m) pad # padname x (um) y (um) pad # padname x (um) y (um) 1 p0.0 95 4564 30 dacout 447 95 53 pllen 2965 368 82 p0.6 2694 4880 2 d7 95 4412 31 avss 542 95 54 a17 2965 516 83 a6 2599 4880 3 d6 95 4260 32 vcm 637 95 55 p1.7 2965 665 84 p0.5 2504 4880 4 pdn 95 4107 33 micin2 732 95 56 a16 2965 813 85 a5 2409 4880 5 d5 95 3955 34 micin1 827 95 57 p1.6 2965 961 86 p0.4 2314 4880 6 d4 95 3803 35 ampcom 922 95 58 gnd 2965 1110 87 a4 2219 4880 7 gnd 95 3651 36 vref 1017 95 59 gnd 2965 1291 88 gnd 2124 4880 8 gnd 95 3498 37 avdd 1112 95 60 vdd 2965 1446 89 gnd 2029 4880 9 xo1 95 3346 38 p2.4 1364 95 61 vdd 2965 1681 90 pwm0 1792 4880 10 xi1 95 3251 39 p2.3 1459 95 62 a15 2965 1831 91 pwm1 1366 4880 11 vdd 95 3063 40 p2.2 1554 95 63 p1.5 2965 1972 92 vdd 1128 4880 12 vdd 95 2858 41 gnd 1649 95 64 a14 2965 2104 93 vdd 1033 4880 13 -xm 95 2729 42 p2.1 1744 95 65 p1.4 2965 2237 94 a3 938 4880 14 xo2 95 2605 43 p2.0 1839 95 66 a13 2965 2366 95 p0.3 843 4880 15 xi2 95 2510 44 gnd 1934 95 67 p1.3 2965 2481 96 a2 748 4880 16 d3 95 2376 45 vdd 2029 95 68 a12 2965 2596 97 p0.2 653 4880 17 d2 95 2238 46 -rdf 2124 95 69 p1.2 2965 2708 98 a1 558 4880 18 p2.7 95 2095 47 -wrd 2219 95 70 a11 2965 2817 99 p0.1 463 4880 19 d1 95 1943 48 -rdr 2314 95 71 p1.1 2965 3061 100 a0 368 4880 20 d0 95 1790 49 -wrc 2409 95 72 a10 2965 3194 21 gnd 95 1667 50 a19 2504 95 73 gnd 2965 3358 22 gnd 95 1434 51 a18 2599 95 74 gnd 2965 3513 23 vdd 95 1282 52 test 2694 95 75 vdd 2965 3678 24 vdd 95 1129 76 vdd 2965 3827 25 p2.6 95 964 77 a9 2965 3975 26 reserved 95 825 78 p1.0 2965 4123 27 p2.5 95 672 79 a8 2965 4272 28 reserved 95 520 80 a7 2965 4420 29 -reset 95 368 81 p0.7 2965 4568 notes: 1. coordinates are in microns (um), rounded to nearest um. 2. coordinates are of the center of the bonding pad opening (70um). 3. coordinate (0,0) is the lower left corner of the die. 4. die size with scribe and seal ring is 3060 um x 4975 um. 5. no external die substrate tie is required. however, a substrate tie to ground is preferred.
data sheet RSC-4128 45 p/n 80-0206-j ? 2004 sensory inc. mechanical data lqfp 100 plasticquad flatpack (14x14x1.4 mm)
RSC-4128 data sheet 46 p/n 80-0206-j ? 2004 sensory inc. dimension in mm dimension in inch symbol min nom max min nom max a - - 1.60 - - 0.063 a1 0.05 - 0.15 0.002 - 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 b1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 - 0.20 0.004 - 0.008 c1 0.09 - 0.16 0.004 - 0.006 d 15.85 16.00 16.15 0.624 0.630 0.636 d1 13.90 14.00 14.10 0.547 0.551 0.555 e 15.85 16.00 16.15 0.624 0.630 0.636 e1 13.90 14.00 14.10 0.547 0.551 0.555 0.50 bsc 0.20 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 bsc r1 0.08 - - 0.003 - - r2 0.08 - 0.20 0.003 - 0.008 s 0.20 - - 0.008 - - 0o 3.5o 7o 0o 3.5o 7o 1 0o - - 0o - - 2 12o typ 12o typ 3 12o typ 12o typ notes: a. all linear dimensions are in millimeters. b. this drawing is subjec t to change without notice. c. falls within jedec ms-026 bbc
data sheet RSC-4128 47 p/n 80-0206-j ? 2004 sensory inc. lqfp 64 plasticquad flatpack (10x10x1.4 mm)
RSC-4128 data sheet 48 p/n 80-0206-j ? 2004 sensory inc. dimension in mm dimension in inch symbol min nom max min nom max a - - 1.60 - - 0.063 a1 0.05 - 0.15 0.002 - 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 b1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 - 0.20 0.004 - 0.008 c1 0.09 - 0.16 0.004 - 0.006 d 12.00 bsc 0.472 bsc d1 10.00 bsc 0.394 bsc e 12.00 bsc 0.472 bsc e1 10.00 bsc 0.394 bsc 0.50 bsc 0.20 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 bsc r1 0.08 - - 0.003 - - r2 0.08 - 0.20 0.003 - 0.008 s 0.20 - - 0.008 - - 0o 3.5o 7o 0o 3.5o 7o 1 0o - - 0o - - 2 12o typ 12o typ 3 12o typ 12o typ notes: d. all linear dimensions are in millimeters. e. this drawing is subjec t to change without notice. f. falls within jedec ms-026, bbc ordering information part shipping p/n description RSC-4128 die (rom specific) tested, singulated RSC-4128 die in waffle pack RSC-4128 64lqfp (rom specific) RSC-4128 64 pin 10 x 10 x 1.4 mm lqfp RSC-4128 100lqfp (rom specific) RSC-4128 100 pin 14 x 14 x 1.4 mm lqfp
1991 russell ave., santa clara, ca 95054 tel: (408) 327-9000 fax: (408) 727-4748 ? 2004 sensory, inc. all rights reserved. sensory is registered by the u.s. patent and trademark office. all other trademarks or registered trademarks are the property of their respective owners. www.sensoryinc.com the interactive speech? product line the interactive speech line of ics and software was developed to ?bring life to products? thr ough advanced speech recognition a nd audio technology. the interactive speech produc t line was designed for consumer telephony pr oducts and cost-sensitiv e consumer elect ronic applications such as home electronics, per sonal security, and personal communication. the product line includes award-winning rsc series general-purpose microcontro llers and tools, sc series of speech microcontro llers, plus a line of easy-to-implement chips that can be pin-configured or controlled by an external host microcontroller. sensory?s software technologies run on a variety of microcon trollers and dsps. rsc microcontrollers and tools the rsc product line contains low-cost 8-bit speech- optimized microcontrollers des igned for use in consumer electronics. all members of the rsc family are fully in tegrated and include a/d, pre-amplifier, d/a, rom, and ram circuitry. the rsc family can perform a full range of speech/audio functions includi ng speech recognition, speaker verification, speech and music synthesis, and voice record/playback. the family is supported by a complete suite of evaluation tools and development kits. svc microcontrollers and tools the svc product line combines text-dependent s peaker verification password biometrics with low-cost 8-bit microcontrollers des igned for use in consumer electronics. all members of the svc fam ily are fully integrated for speech applications and include a/d, p re- amplifier, d/a, rom, and ram circuitry. the svc family perf orms noise robust speaker verifica tion password security functions and speech synthesis. the family is supported by a comp lete suite of evaluation tools and development kits. sc microcontrollers and tools the sc-6x product line feature the highest quality speech synthesis ics at the lowest data rate in the industry. the line incl udes a 12.32 mips processor for high-quality low data-rate speech compression and midi music synthesis, with plenty of power left over for o ther processor and control functions. members of the sc-6x line can store as much as 37 minutes of speech on chip and include as mu ch as 64 i/o pins for external interfacing. integrating this broad range of features onto a single chip enables developers to cre ate products with high quality, long duration speech at very competitive price points. application specific standard products (assps) voice direct? ii provides inexpensive speaker-depen dent speech recognition and speech synt hesis. this easy-to-use, pin- configurable chip requires no custom programming and can rec ognize up to 15 words in 4 pin-programmable modes. ideal for speaker-dependent command and control of household consumer pr oducts, voice direct ? ii is part of a complete product line that includes the ic, module, and voice direct ? ii speech recognition kit. voice extreme? simplifies the creation of fully custom speech-enabl ed products by offering developers the capability of programming the chip in a high-level c-lik e language. program code, speech data, and even record and playback information can be stored on a single off-chip flash memory. based on sensory' s rsc-364 speech processor, voice extreme includes a highly efficient on-chip code interpreter, and is supported by a comprehensive suite of low-cost development tools. software and technology voice activation? micro footprint software provi des advanced speech technology on a va riety of microcontroller and dsp platforms. a flexible design with a br oad range of technologies allows manufacturers to easily integrate speech functionality into consumer electronic products. fluent speech? small footprint software recognizes up to 50,000 words; offers animated speech with the ability to automate enunciation and articulation; performs text-to-speech synthesis in either male or female voices; provides noise and echo cancellation, performs word spotting fo r natural language usage; offers telephone bar ge-in; and provides continuous digit recognition. important notices reasonable efforts have been made to verify the accuracy of in formation contained herein, however no guarantee can be made of accuracy or applicability. sensory reserves the right to change any specification or description contained herein.

▲Up To Search▲

Price & Availability of RSC-4128

	To Download RSC-4128 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .