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buk95/9608-55a trenchmos? logic level fet rev. 03 6 may 2002 product data 1. description n-channel enhancement mode ?eld-effect power transistor in a plastic package using trenchmos? technology, featuring very low on-state resistance. product availability: buk9508-55a in sot78 (to-220ab) BUK9608-55A in sot404 (d 2 -pak). 2. features n trenchmos? technology n q101 compliant n 175 c rated n logic level compatible. 3. applications n automotive and general purpose power switching: u 12 v and 24 v loads u motors, lamps and solenoids. 4. pinning information [1] it is not possible to make connection to pin 2 of the sot404 package. table 1: pinning - sot78 and sot404, simpli?ed outline and symbol pin description simpli?ed outline symbol 1 gate (g) sot78 (to-220ab) sot404 (d 2 -pak) 2 drain (d) [1] 3 source (s) mb mounting base; connected to drain (d) mbk106 12 mb 3 13 2 mbk116 mb s d g mbb076
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 2 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. 5. quick reference data 6. limiting values [1] current is limited by power dissipation chip rating [2] continuous current is limited by package. table 2: quick reference data symbol parameter conditions typ max unit v ds drain-source voltage (dc) - 55 v i d drain current (dc) t mb =25 c; v gs = 5 v - 125 a p tot total power dissipation t mb =25 c - 253 w t j junction temperature - 175 c r dson drain-source on-state resistance t j =25 c; v gs =5v; i d =25a 6.8 8 m w t j =25 c; v gs = 4.5 v; i d =25a - 8.5 m w t j =25 c; v gs = 10 v; i d = 25 a 6.4 7.5 m w table 3: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage (dc) - 55 v v dgr drain-gate voltage (dc) r gs =20k w -55v v gs gate-source voltage (dc) - 15 v i d drain current (dc) t mb =25 c; v gs =5v; figure 2 and 3 [1] - 125 a [2] -75a t mb = 100 c; v gs =5v; figure 2 [2] -75a i dm peak drain current t mb =25 c; pulsed; t p 10 m s; figure 3 - 503 a p tot total power dissipation t mb =25 c; figure 1 - 253 w t stg storage temperature - 55 +175 c t j junction temperature - 55 +175 c source-drain diode i dr reverse drain current (dc) t mb =25 c [1] - 125 a [2] -75a i drm peak reverse drain current t mb =25 c; pulsed; t p 10 m s - 503 a avalanche ruggedness e ds(al)s non-repetitive drain-source avalanche energy unclamped inductive load; i d =75a; v ds 55 v; v gs =5v; r gs =50 w ; starting t mb =25 c - 670 mj
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 3 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. v gs 3 4.5 v fig 1. normalized total power dissipation as a function of mounting base temperature. fig 2. continuous drain current as a function of mounting base temperature. t mb =25 c; i dm single pulse. fig 3. safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03na19 0 40 80 120 0 50 100 150 200 t mb ( c) p der (%) 03ni52 0 50 100 150 25 50 75 100 125 150 175 200 t mb (oc) i d (a) capped at 75 a due to package p der p tot p tot 25 c () ----------------------- 100 % = 03ni50 1 10 10 2 10 3 10 -1 1 10 10 2 v ds (v) i d (a) dc 100 ms 10 ms limit r dson = v ds /i d 1 ms t p = 10 s 100 s capped at 75 a due to package
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 4 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. 7. thermal characteristics 7.1 transient thermal impedance table 4: thermal characteristics symbol parameter conditions min typ max unit r th(j-mb) thermal resistance from junction to mounting base figure 4 - - 0.59 k/w r th(j-a) thermal resistance from junction to ambient sot78 vertical in still air - 60 - k/w sot404 mounted on a printed circuit board; minimum footprint - 50 - k/w fig 4. transient thermal impedance from junction to mounting base as a function of pulse duration. 03ni51 single shot 0.2 0.1 0.05 0.02 10 -3 10 -2 10 -1 1 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 1 t p (s) z th(j-mb) (k/w) d = 0.5 t p t p t p t t d =
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 5 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8. characteristics table 5: characteristics t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit static characteristics v (br)dss drain-source breakdown voltage i d = 0.25 ma; v gs =0v t j =25 c55--v t j = - 55 c50--v v gs(th) gate-source threshold voltage i d = 1 ma; v ds =v gs ; figure 9 t j =25 c 1 1.5 2 v t j = 175 c 0.5 - - v t j = - 55 c - - 2.3 v i dss drain-source leakage current v ds = 55 v; v gs =0v t j =25 c - 0.05 10 m a t j = 175 c - - 500 m a i gss gate-source leakage current v gs = 10 v; v ds = 0 v - 2 100 na r dson drain-source on-state resistance v gs =5v; i d =25a; figure 7 and 8 t j =25 c - 6.8 8 m w t j = 175 c--16m w v gs = 4.5 v; i d =25a - - 8.5 m w v gs =10v; i d = 25 a - 6.4 7.5 m w dynamic characteristics q g(tot) total gate charge v gs =5v; v dd =44v; i d =25a; figure 14 -92-nc q gs gate-to-source charge - 11 - nc q gd gate-to-drain (miller) charge - 43 - nc c iss input capacitance v gs =0v; v ds =25v; f = 1 mhz; figure 12 - 4551 6021 pf c oss output capacitance - 760 900 pf c rss reverse transfer capacitance - 500 687 pf t d(on) turn-on delay time v dd = 30 v; r l = 1.2 w ; v gs =5v; r g =10 w -40-ns t r rise time - 175 - ns t d(off) turn-off delay time - 280 - ns t f fall time - 167 - ns l d internal drain inductance from drain lead 6 mm from package to centre of die - 4.5 - nh from contact screw on mounting base to centre of die sot78 - 3.5 - nh from upper edge of drain mounting base to centre of die sot404 - 2.5 - nh l s internal source inductance from source lead to source bond pad - 7.5 - nh
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 6 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. source-drain diode v sd source-drain (diode forward) voltage i s = 25 a; v gs =0v; figure 15 - 0.85 1.2 v t rr reverse recovery time i s =75a;di s /dt = - 100 a/ m s v gs = - 10 v; v ds =25v -70-ns q r recovered charge - 170 - nc table 5: characteristics continued t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit t j =25 c; t p = 300 m st j =25 c; i d =25a fig 5. output characteristics: drain current as a function of drain-source voltage; typical values. fig 6. drain-source on-state resistance as a function of gate-source voltage; typical values. t j =25 c a=r dson /r dson(25 c) fig 7. drain-source on-state resistance as a function of drain current; typical values. fig 8. normalized drain-source on-state resistance factor as a function of junction temperature. 03ni47 0 100 200 300 400 0246810 v ds (v) i d (a) 10 6 8 label is v gs (v) 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.2 2.4 03ni46 5 6 7 8 9 0 5 10 15 v gs (v) r dson (m w ) 03ni48 5 10 15 20 0 100 200 300 400 i d (a) r dson (m w ) v gs = 3 v 3.2 v 3.4 v 3.6 v 3.8 v 4 v 5 v 10 v 03ne89 0 0.5 1 1.5 2 -60 0 60 120 180 t j ( c) a
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 7 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. i d = 1 ma; v ds =v gs t j =25 c; v ds =v gs fig 9. gate-source threshold voltage as a function of junction temperature. fig 10. sub-threshold drain current as a function of gate-source voltage. t j =25 c; v ds =25v v gs = 0 v; f = 1 mhz fig 11. forward transconductance as a function of drain current; typical values. fig 12. input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03aa33 0 0.5 1 1.5 2 2.5 -60 0 60 120 180 t j ( o c) v gs(th) (v) max typ min 03aa36 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 0123 v gs (v) i d (a) max typ min 03ni44 0 20 40 60 80 100 120 0 20406080 i d (a) g fs (s) 03ni49 0 2000 4000 6000 8000 10000 12000 10 -2 10 -1 1 10 10 2 v ds (v) c (pf) c iss c oss c rss
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 8 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. v ds =25v t j =25 c; i d =25a fig 13. transfer characteristics: drain current as a function of gate-source voltage; typical values. fig 14. gate-source voltage as a function of turn-on gate charge; typical values. v gs =0v fig 15. reverse diode current as a function of reverse diode voltage; typical values. 03ni45 0 20 40 60 80 100 01234 v gs (v) i d (a) t j = 175 oc t j = 25 oc 03ni43 0 1 2 3 4 5 0 20406080100 q g (nc) v gs (v) v dd = 14 v v dd = 44 v 03ni42 0 20 40 60 80 100 0.0 0.3 0.6 0.9 1.2 v sd (v) i s (a) t j = 175 oc t j = 25 oc
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 9 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. 9. package outline fig 16. sot78 (to-220ab). references outline version european projection issue date iec jedec eiaj sot78 sc-46 3-lead to-220ab d d 1 q p l 123 l 1 (1) b 1 e e b 0 5 10 mm scale plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead to-220ab sot78 dimensions (mm are the original dimensions) a e a 1 c note 1. terminals in this zone are not tinned. q l 2 unit a 1 b 1 d 1 e p mm 2.54 qq a b d c l 2 max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.7 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 l 1 (1) e l 00-09-07 01-02-16 mounting base
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 10 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 17. sot404 (d 2- pak). unit a references outline version european projection issue date iec jedec eiaj mm a 1 d 1 d max. e el p h d q c 2.54 2.60 2.20 15.80 14.80 2.90 2.10 11 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 0 2.5 5 mm scale plastic single-ended surface mounted package (philips version of d 2 -pak); 3 leads (one lead cropped) sot404 e e e b d 1 h d d q l p c a 1 a 13 2 mounting base 99-06-25 01-02-12
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 11 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. 10. soldering dimensions in mm. fig 18. re?ow soldering footprint for sot404. handbook, full pagewidth msd057 solder lands solder resist occupied area solder paste 10.50 7.40 7.50 1.50 1.70 10.60 1.20 1.30 1.55 5.08 10.85 0.30 2.15 8.35 2.25 4.60 0.20 3.00 4.85 7.95 8.15 8.075 8.275 5.40 1.50
philips semiconductors buk95/9608-55a trenchmos? logic level fet product data rev. 03 6 may 2002 12 of 14 9397 750 09573 ? koninklijke philips electronics n.v. 2002. all rights reserved. 11. revision history table 6: revision history rev date cpcn description 03 20020506 - product data (9397 750 09573); supersedes product data of buk9508_9608-55a_2 of 4 of september 2000. modi?cations: ? the format of this speci?cation has been redesigned to comply with philips semiconductors new presentation and information standard. ? thermal resistance ?gure lowered (j-mb) section 7 . this has a knock on effect on the devices current and power handling capabilities (see section 5 and section 6 ). ? maximum gate-source voltage increased from 10 to 15 v ( section 6 ). ? switching speeds re-measured in dynamic characteristics section 8 .
9397 750 09573 philips semiconductors buk95/9608-55a trenchmos? logic level fet ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 03 6 may 2002 13 of 14 9397 750 09573 philips semiconductors buk95/9608-55a trenchmos? logic level fet ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 03 6 may 2002 13 of 14 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 12. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. 13. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 14. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 15. trademarks trenchmos is a trademark of koninklijke philips electronics n.v. data sheet status [1] product status [2] de?nition objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be publish ed at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a.
? koninklijke philips electronics n.v. 2002. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 6 may 2002 document order number: 9397 750 09573 contents philips semiconductors buk95/9608-55a trenchmos? logic level fet 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 pinning information . . . . . . . . . . . . . . . . . . . . . . 1 5 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 6 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 thermal characteristics. . . . . . . . . . . . . . . . . . . 4 7.1 transient thermal impedance . . . . . . . . . . . . . . 4 8 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 12 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13 13 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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