description hewlett-packards ina-32063 is a silicon rfic amplifier that offers excellent gain and output power for applications to 3.0 ghz. packaged in an ultraminiature sot-363 package, it requires half of the board space of a sot-143 package. the ina-32063 offers wide bandwidth and good linearity and 17 db gain with a modest supply current. with its input and output matched internally to 50 w , the ina-32063 is a simple to use gain block that is suitable for numerous applications. the ina-32063 is fabricated using hps 30 ghz C fmax, isosat? silicon-bipolar process that uses nitride, self-alignment, submicrometer lithography, trench isolation, ion implantation, and polyimide intermetal dielec- tric and scratch protection to achieve superior performance, uniformity and reliability. 3.0 ghz wideband silicon rfic amplifier technical data ina-32063 surface mount sot-363 (sc-70) package pin connections and package marking simplified schematic output
& v d gnd 1 32 gnd 2 gnd 1 input 1 2 3 6 5 4v d note: package marking provides orientation and identification. features ? 17 db gain at 1.9 ghz ? +3 dbm p 1 db at 1.9 ghz ? single +3v supply ? unconditionally stable applications ? lo buffer and driver amplifier for cellular, cordless, special mobile radio, pcs, ism, wireless lan, dbs, tvro, and tv tuner input v d output & v d gnd1 gnd2
2 thermal resistance [2] : q jc = 170 c/w notes: 1. operation of this device above any one of these limits may cause permanent damage. 2. t c = 25 c (t c is defined to be the temperature at the package pins where contact is made to the circuit board) ina-32063 electrical specifications , t c = 25 c, z o = 50 w ,v d = 3 v symbol parameters and test conditions units min. typ. max. std. dev. [4] |s 21 | 2 gain in 50 w system f = 0.9 ghz db 16.8 f = 1.9 ghz 15.5 [3] 17.8 0.39 f = 2.4 ghz 18.2 nf 50 noise figure f = 1.9 ghz db 4.4 0.21 p 1db output power at 1 db gain compression f = 0.9 ghz dbm 3.6 f = 1.9 ghz 4.8 f = 2.4 ghz 4.0 ip 3 output third order intercept point f = 0.9 ghz dbm 15.3 f = 1.9 ghz 14.4 f = 2.4 ghz 11.5 vswr in input vswr f = 0.1 C 2.4 ghz 1.1:1 vswr out output vswr f = 0.1 C 2.4 ghz 1.6:1 i d device current ma 20 25 [3] 1.1 notes: 3. guaranteed specifications are 100% tested in production. 4. standard deviation number is based on measurement of a large number of parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification. absolute maximum ratings absolute symbol parameter units maximum [1] v d device voltage, v 6.0 rf output to ground p in cw rf input power dbm +7.0 t j junction temperature c 150 t stg storage temperature c -65 to 150
3 ina-32063 typical performance, t c = 25 c, z o = 50 w , v d = 3 v 5 25 15 20 10 0 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5 gain (db) frequency (ghz) figure 1. gain vs. frequency and voltage. noise figure (db) frequency (ghz) figure 2. noise figure vs. frequency and voltage. p 1 db (dbm) frequency (ghz) figure 3. output power for 1 db gain compression vs. frequency and voltage. gain (db) frequency (ghz) figure 4. gain vs. frequency and temperature. noise figure (db) frequency (ghz) figure 5. noise figure vs. frequency and temperature. figure 6. output power for 1 db gain compression vs. frequency and temperature. 2.7 v
3.0 v
3.3 v 5 25 15 20 10 0 1.0 0.5 1.5 2.0 3.0 2.5 0 -40 c
+25 c
+85 c 1.0 0.5 1.5 2.0 2.5 3.5 6 0 2.7 v
3.0 v
3.3 v -2 8 0 3.0 2.7 v
3.0 v
3.3 v p 1 db (dbm) frequency (ghz) -40 c
+25 c
+85 c vswr frequency (ghz) figure 7. input and output vswr vs. frequency. 0 4 vswr in
vswr out i d (ma) v d (v) figure 8. supply current vs. voltage and temperature. 0 02 1345 4.5 5 4 5.5 2 4 0 6 2 4 0 6 3 6.5 5 5.5 6 3.5 4 4.5 35 20 25 30 5 10 15 0 -40 c
+25 c
+85 c -40 c
+25 c
+85 c figure 9. third order intercept point, ip 3 vs. frequency and temperature. ip 3 (dbm) frequency (ghz) 6 18 10 14 8 0 16 12 3 1 2 0.5 2.5 1.5 -40 c
+25 c
+85 c -2 8 0 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5
4 ina-32063 typical scattering parameters [5] , t c = 25 c, z o = 50 w ,v d = 3.0 v freq. s 11 s 21 s 12 s 22 k ghz mag ang db mag ang db mag ang mag ang factor 0.1 0.034 19 16.5 6.72 -4 -26.8 0.046 3 0.215 -5 1.68 0.2 0.034 30 16.5 6.71 -9 -27.9 0.040 0 0.230 -6 1.89 0.3 0.039 35 16.6 6.73 -13 -27.7 0.041 -3 0.227 -7 1.84 0.4 0.043 41 16.6 6.75 -17 -28.3 0.039 -10 0.238 -8 1.91 0.5 0.053 53 16.6 6.78 -22 -28.3 0.038 -7 0.226 -8 1.96 0.6 0.054 49 16.7 6.80 -26 -28.0 0.040 -10 0.218 -9 1.87 0.7 0.059 49 16.7 6.85 -30 -28.5 0.038 -12 0.223 -12 1.94 0.8 0.065 50 16.8 6.90 -35 -28.9 0.036 -13 0.224 -16 2.02 0.9 0.072 49 16.8 6.94 -39 -29.1 0.035 -12 0.220 -21 2.05 1.0 0.080 47 16.9 7.00 -44 -29.2 0.035 -11 0.215 -25 2.03 1.1 0.084 48 17.0 7.09 -48 -29.1 0.035 -13 0.211 -29 2.06 1.2 0.090 46 17.1 7.16 -53 -29.3 0.034 -15 0.211 -33 2.10 1.3 0.096 45 17.2 7.23 -58 -29.5 0.033 -15 0.206 -40 2.07 1.4 0.101 46 17.3 7.32 -62 -29.8 0.033 -15 0.205 -47 2.10 1.5 0.107 45 17.4 7.40 -67 -29.9 0.032 -14 0.204 -55 2.11 1.6 0.109 43 17.5 7.48 -72 -29.6 0.033 -16 0.194 -63 2.04 1.7 0.108 41 17.6 7.59 -77 -29.9 0.032 -19 0.193 -68 2.07 1.8 0.110 38 17.7 7.69 -83 -30.1 0.031 -20 0.194 -77 2.10 1.9 0.113 36 17.8 7.79 -88 -30.5 0.030 -22 0.197 -85 2.13 2.0 0.118 32 17.9 7.88 -94 -30.6 0.029 -23 0.198 -94 2.17 2.1 0.121 26 18.0 7.98 -100 -30.8 0.029 -25 0.206 -101 2.13 2.2 0.129 20 18.1 8.03 -106 -31.1 0.028 -27 0.214 -111 2.17 2.3 0.138 13 18.1 8.06 -112 -31.3 0.027 -29 0.220 -120 2.22 2.4 0.151 6 18.2 8.09 -119 -31.5 0.027 -31 0.225 -128 2.20 2.5 0.163 -1 18.2 8.09 -125 -31.6 0.026 -34 0.232 -135 2.26 2.6 0.175 -7 18.1 8.04 -132 -32.0 0.025 -37 0.242 -143 2.33 2.7 0.189 -13 18.0 7.96 -138 -32.3 0.024 -42 0.247 -151 2.42 2.8 0.199 -19 17.9 7.84 -145 -32.8 0.023 -46 0.250 -160 2.53 2.9 0.208 -26 17.8 7.73 -152 -33.3 0.022 -51 0.250 -166 2.67 3.0 0.216 -33 17.6 7.56 -158 -33.6 0.021 -56 0.249 -173 2.84 3.1 0.224 -40 17.3 7.36 -165 -34.2 0.019 -63 0.246 180 3.20 3.2 0.234 -48 17.1 7.16 -171 -35.1 0.018 -70 0.239 173 3.46 3.3 0.243 -57 16.8 6.92 -177 -35.8 0.016 -78 0.229 168 4.02 3.4 0.254 -64 16.5 6.67 176 -36.7 0.015 -86 0.220 163 4.44 3.5 0.266 -71 16.1 6.39 170 -37.1 0.014 -97 0.212 157 4.95 3.6 0.280 -77 15.8 6.13 165 -38.3 0.012 -110 0.196 151 6.00 3.7 0.292 -83 15.4 5.86 159 -38.8 0.011 -121 0.182 146 6.84 3.8 0.301 -88 14.9 5.58 154 -39.0 0.011 -130 0.170 142 7.18 3.9 0.309 -92 14.5 5.32 149 -38.3 0.012 -142 0.156 136 6.90 4.0 0.317 -97 14.1 5.07 144 -37.6 0.013 -152 0.139 131 6.69 4.1 0.323 -101 13.7 4.84 139 -36.5 0.015 -160 0.124 125 6.08 4.2 0.327 -105 13.3 4.61 134 -35.3 0.017 -166 0.110 120 5.64 4.3 0.328 -109 12.9 4.39 130 -34.0 0.020 -173 0.095 112 5.05 4.4 0.331 -113 12.4 4.19 126 -32.8 0.023 -178 0.079 101 4.61 4.5 0.333 -117 12.0 3.99 122 -31.7 0.026 177 0.065 88 4.30 4.6 0.334 -122 11.6 3.81 118 -30.7 0.029 172 0.052 68 4.04 4.7 0.337 -126 11.2 3.63 114 -29.8 0.032 168 0.041 42 3.85 4.8 0.338 -130 10.8 3.47 110 -29.0 0.036 165 0.031 15 3.59 4.9 0.342 -134 10.4 3.31 106 -28.0 0.040 162 0.022 -5 3.39 5.0 0.347 -137 10.0 3.17 103 -27.2 0.044 159 0.013 -17 3.22 note: 5. reference plane per figure 15 in applications information section.
5 ina-32063 applications information introduction the ina-32063 is a +3 volt silicon rfic amplifier that is designed with a two stage internal network to provide a broadband gain and 50 w input and output impedance. with a typical +4.8 dbm p -1 db compressed output power at 1900 mhz, for only 20 ma supply current. the broad bandwidth, ina-32063, is well suited for amplifier applications in mobile communication systems. a feature of the ina-32063 is a positive gain slope over the 1C2.5 ghz range that is useful in many satellite-based tv and datacom systems. in addition to use in buffer and driver amplifier applications in the cellular market, the ina-32063 will find many applications in battery operated wireless communication systems. operating details the ina-32063 is a voltage-biased device that operates from a +3 volt power supply with a typical current drain of 20 ma. all bias regulation circuitry is integrated into the rfic. figure 10 shows a typical imple- mentation of the ina-32063. the supply voltage for the ina-32063 must be applied to two terminals, the v d pin and the rf output pin. rf
output rf
input v d c bypass c out c block 32 rfc gnd2 gnd1 gnd1 figure 10. basic amplifier application. the v d connection to the ampli- fier is rf bypassed by placing a capacitor to ground near the v d pin of the amplifier package. the power supply connection to the rf output pin is achieved by means of a rf choke (inductor). the value of the rf choke must be large relative to 50 w in order to prevent loading of the rf output. the supply voltage end of the rf choke is bypassed to ground with a capacitor. if the physical layout permits, this can be the same bypass capacitor that is used at the v d terminal of the amplifier. blocking capacitors are normally placed in series with the rf input and the rf output to isolate the dc voltages on these pins from circuits adjacent to the amplifier. the values for the blocking and bypass capacitors are selected to provide a reactance at the lowest frequency of operation that is small relative to 50 w . example layout for 50 w output amplifier an example layout for an ampli- fier using the ina-32063 with 50 w input and 50 w output is shown in figure 11. rf output
and v d gnd 1 rf input gnd 1 gnd 2 50 50 figure 11. rf layout. this example uses a microstripline design (solid groundplane on the backside of the circuit board). the circuit board material is 0.031-inch thick fr-4. plated through holes (vias) are used to bring the ground to the topside of the circuit where needed. the performance of ina-32063 is sensitive to ground path inductance. the two-stage design creates the possibility of a feedback loop being formed through the ground returns of the stages, gnd 1 and gnd 2. gnd 1 gnd 2 via figure 12. ina-32063 potential ground loop. gnd 1 gnd 2 via via figure 13. ina-32063 suggested layout. at least one ground via should be placed adjacent to each ground pin to assure good rf grounding. multiple vias are used to reduce the inductance of the path to ground and should be placed as close to the package terminals as practical. the effects of the potential ground loop shown in figure 12 may be observed as a peaking in the gain versus frequency response, an increase in input vswr, or even as return gain at the input of the ina-32063. figure 14 shows an assembled amplifier. the +3 volt supply is fed directly into the v d pin of the
6 ina-32063 and into the rf output pin through the rf choke (rfc). capacitor c3 provides rf bypass- ing for both the v d pin and the power supply end of the rfc. capacitor c4 is optional and may be used to add additional bypass- ing for the v d line. a well-by- passed v d line is especially necessary in cascades of ampli- fier stages to prevent oscillation that may occur as a result of rf feedback through the power supply lines. for this demonstration circuit, the value chosen for the rf choke was 120 nh (coilcraft 1008cs-221, toko ll2012 -f or equivalent). all of the blocking and bypass capacitors are 100 pf. the gap in the output transmis- sion line was bridged using copper foil cut to size. these values provide excellent amplifier performance from under 50 mhz through 2.4 ghz. larger values for the choke and capacitors can be used to extend the lower end of the bandwidth. since the gain of the ina-32063 extends down to dc, the frequency response of the amplifier is limited only by the values of the capacitors and choke. a convenient method for making rf connection to the demonstra- tion board is to use a pcb mount- ing type of sma connector (johnson 142-0701-881, or equivalent). these connectors can be slipped over the edge of the pcb and the center conductor soldered to the input and output lines. the ground pins of the connectors can be soldered to the ground plane on the backside of board. pcb materials typical choices for pcb material for low cost wireless applications are fr-4 or g-10 with a thickness of 0.025 (0.635 mm) or 0.031inches (0.787 mm) a thick- ness of 0.062 inches (1.574 mm) is the maximum that is recom- mended for use with this particu- lar device. the use of a thicker board material increases the inductance of the plated through vias used for rf grounding and may deteriorate circuit perfor- mance. adequate grounding is needed not only to obtain maxi- mum amplifier performance but also to reduce any possibility of instability. phase reference planes the positions of the reference planes used to measure s-param- eters for this device are shown in figure 15. as seen in the illustra- tion, the reference planes are located at the point where the package leads contact the test circuit. reference
planes test circuit figure 15. phase reference planes. sot-363 pcb layout the ina-32063 is packaged in the miniature sot-363 (sc-70) surface mount package. a pcb pad layout for the sot-363 package is shown in figure 16 (dimensions are in inches). this layout provides ample allowance for package placement by auto- mated assembly equipment without adding pad parasitics that could impair the high frequency performance of the ina-32063. the layout that is shown with a nominal sot-363 package foot- print superimposed on the pcb pads for reference. c2 rfc c1 c3 c4 v d ina-3xx63 demo board 32 figure 14. assembled amplifier.
7 0.026 0.075 0.016 0.035 figure 16. pcb pad layout for ina-32063 (dimensions in inches). statistical parameters several categories of parameters appear within this data sheet. parameters may be described with values that are either minimum or maximum, typical, or standard deviations. the values for parameters are based on compre- hensive product characterization data, in which automated mea- surements are made on a large number of parts taken from 3 non-consecutive process lots of semiconductor wafers. the data derived from product character- ization tends to be normally distributed, e.g., fits the standard bell curve. parameters considered to be the most important to system perfor- mance are bounded by minimum or maximum values. for the ina-32063, these parameters are: power gain (|s21| 2 ) and the device current (i d ). each of these guaranteed parameters is 100% tested. values for most of the parameters in the table of electrical specifications that are described by typical data are the mathematical mean ( m ), of the normal distribution taken from the characterization data. for parameters where measurements or mathematical averaging may not be practical, such as s-parameters or noise param- eters and the performance curves, the data represents a nominal part taken from the center of the characterization distribution. typical values are intended to be used as a basis for electrical design. to assist designers in optimizing not only the immediate circuit using the ina-32063, but to also optimize and evaluate trade-off that affect a complete wireless system, the standard deviation ( s ) is provided for many of the electrical specifications param- eters (at 25 c) in addition to the mean. the standard deviation is a measure of the variability about the mean. it will be recalled that a normal distribution is completely described by the mean and standard deviation. standard statistics tables or calculations provide the probabil- ity of a parameter falling between any two values, usually symmetri- cally located about the mean. referring to figure 17 for ex- ample, the probability of a parameter being between 1 s is 68.3%; between 2 s is 95.4%; and between 3 s is 99.7%. 68% 95% 99% parameter value mean
( ), typ -3 s -2 s -1 s +1 s +2 s +3 s
figure 17. normal distribution. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-363 package, will reach solder reflow temperatures faster than those with a greater mass. the ina-32063 has been qualified to the time-temperature profile shown in figure 18. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evapo- rating solvents from the solder paste. the reflow zone briefly elevates the temperature suffi- ciently to produce a reflow of the solder. the rates of change of temperature for the ramp-up and cool down zones are chosen to be low enough to not cause deforma- tion of the board or damage to components due to thermal shock. for more information on mount- ing considerations for packaged microwave semiconductors
8 time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat
zone cool down
zone reflow
zone 120 180 240 300 figure 18. surface mount assembly profile. please refer to hewlett-packard application note an-a006. these parameters are typical for a surface mount assembly process for the ina-32063. as a general guideline, the circuit board and components should only be exposed to the minimum temperatures and times necessary to achieve a uniform reflow of solder. electrostatic sensitivity rfics are electrostatic discharge (esd) sensitive devices. although the ina-32063 is robust in design, permanent damage may occur to these devices if they are sub- jected to high-energy electrostatic discharges. electrostatic charges as high as several thousand volts (which readily accumulate on the human body and on test equip- ment) can discharge without detection and may result in degradation in performance or failure. electronic devices may be subjected to esd damage in any of the following areas: ? storage & handling ? inspection & testing ? assembly ? in-circuit use the ina-32063 is an esd class 1 device. therefore, proper esd precautions are recommended when handling, inspecting, and assembling these devices to avoid damage. for more information on electro- static discharge and control refer to hewlett-packard application note an-a004r.
9 package dimensions outline 63 (sot-363/sc-70) ina-32063 part number ordering information part number devices per container container INA-32063-BLK 100 tape strip in antistatic bag ina-32063-tr1 3,000 7" reel ina-32063-tr2 10,000 13" reel 2.20 (0.087)
2.00 (0.079) 1.35 (0.053)
1.15 (0.045) 1.30 (0.051)
ref. 0.650 bsc (0.025) 2.20 (0.087)
1.80 (0.071) 0.10 (0.004)
0.00 (0.00) 0.25 (0.010)
0.15 (0.006) 1.00 (0.039)
0.80 (0.031) 0.20 (0.008)
0.10 (0.004) 0.30 (0.012)
0.10 (0.004) 0.30 ref. 10 0.425 (0.017)
typ. dimensions are in millimeters (inches)
tape dimensions and product orientation for outline 63 www.hp.com/go/rf for technical assistance or the location of your nearest hewlett-packard sales office, distributor or representative call: americas/canada: 1-800-235-0312 or 408-654-8675 far east/australasia: call your local hp sales office. japan: (81 3) 3335-8152 europe: call your local hp sales office. data subject to change. copyright ? 1998 hewlett-packard co. printed in u.s.a. 5967-5769e (5/98) p p 0 p 2 f w c d 1 d e a 0 8 max. t 1 (carrier tape thickness) t t (cover tape thickness) 5 max. b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.24 0.10 2.34 0.10 1.22 0.10 4.00 0.10 1.00 + 0.25 0.088 0.004 0.092 0.004 0.048 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.255 0.013 0.315 0.012 0.010 0.0005 carrier tape cavity to perforation
(width direction) cavity to perforation
(length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape 32 32
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