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information furnished by analog devices is be lieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or oth- erwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. t el: 781/329-4700 www.analog.com fa x: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. adp3168 * 6-bit programmable 2-, 3-, 4-phase synchronous buck controller * pa tent pending features selectable 2-, 3-, or 4-phase operation at up to 1 mhz per phase 10 mv worst-case differential sensing error over te m perature logic-level pwm outputs for interface to external high power drivers ac tive current balancing between all output phases built-in power good/crowbar blanking supports on-the-fly vid code changes 6-bit digitally programmable 0.8375 v to 1.6 v output programmable short-circuit protection with programmable latch-off delay applications desktop pc power supplies for: next generation intel ? processors vrm modules functional block diagram pwm2 fb pwm3 pwm4 sw1 cssum cscomp sw2 sw3 sw4 csref pwm1 adp3168 vid4 vid3 vid2 vid1 vid5 vid0 fbrtn gnd en delay ilimit pwrgd comp vcc rt rampadj crowbar current limit 2-, 3-, 4-phase driver logic en set reset reset reset reset oscillator cmp cmp cmp cmp current b alancing circuit delay uvlo shutdown and bias dac +150mv dac ?250mv csref precision reference soft- start vid dac en current limit circuit 19 11 12 15 10 28 13 14 26 8 25 24 23 17 18 22 21 20 16 1234 6 5 7 9 27 general description the adp3168 is a highly ef cient multiphase synchronous buck s witching regulator controller optimized for converting a 12 v main supply into the core supply voltage required by high per- formance intel processors. it uses an internal 6-bit dac to read a voltage identi cation (vid) code directly from the processor, which is used to set the output voltage between 0.8375 v and 1.6 v, and uses a multimode pwm architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for vr size and ef ciency. the phase relation- ship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. the adp3168 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. the adp3168 also provides accurate and reliable short- circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the- y output voltage changes requested by the cpu. adp3168 is speci ed over the commercial temperature range of 0? to 85? and is available in a 28-lead tssop package. rev. a
?2? adp3168?specifications 1 (vcc = 12 v, fbrtn = gnd, t a = 0 c to 85 c, unless otherwise noted.) p arameter symbol conditions min typ max unit error amplifier output voltage range accuracy line regulation input bias current fbrtn current output current gain bandwidth product slew rate v comp v fb d v fb i fb i fbrtn i o(err) gbw (err) relative to nominal dac output, referenced to fbrtn, cssum = cscomp (figure 3) vcc = 10 v to 14 v fb forced to v out e 3% comp = fb c comp = 10 pf 0.5 e10 14 0.05 15.5 90 500 20 50 3.5 +10 17 120 v mv % a a a mhz v/s vid inputs input low voltage input high voltage input current, input voltage low input current, input voltage high pull-up resistance internal pull-up voltage vid transition delay time 2 no cpu detection turn-off delay time 2 v il(vid) v ih(vid) i il(vid) i ih(vid) r vid vid(x) = 0 v vid(x) = 1.25 v vid code change to fb change vid code change to 11111 to pwm going low 0.8 35 0.825 400 400 e20 15 60 1.00 0.4 e30 25 115 v v a a k w v ns ns oscillator frequency range 2 frequency variation output voltage rampadj output voltage rampadj input current range f osc f phase v rt v rampadj i rampadj t a = 25?c, r t = 250 k w , 4-phase t a = 25?c, r t = 115 k w , 4-phase t a = 25?c, r t = 75 k w , 4-phase r t = 100 k w to gnd rampadj e fb 0.25 155 1.9 e50 0 200 400 600 2.0 4 245 2.1 +50 100 mhz khz khz khz v mv a current sense amplifier offset voltage input bias current gain bandwidth product slew rate input common-mode range p ositioning accuracy output voltage range output current v os(csa) i bias(csa) gbw (csa) d v fb i cscomp cssum e csref, see test circuit 1 c cscomp = 10 pf cssum and csref see test circuit 2 i cscomp = 100 a e1.5 e50 0 e77 0.05 20 50 e80 500 +1.5 +50 3 e83 3.3 mv na mhz v/s v mv v a current balance circuit common-mode range input resistance input current input current matching v sw(x)cm r sw(x) i sw(x) d i sw(x) sw(x) = 0 v sw(x) = 0 v sw(x) = 0 v e600 20 4 e5 30 7 +200 40 10 +5 mv k w a % current limit comparator ilimit output voltage normal mode shutdown mode output current, normal mode current limit threshold voltage current limit setting ratio delay normal mode voltage delay overcurrent threshold latch-off delay time v ilimit(nm) v ilimit(sd) i ilimit(nm) v cl v delay(nm) v delay(oc) t delay en > 1.7 v, r ilimit = 250 k w en < 0.8 v, i ilimit = e100 a en > 1.7 v, r ilimit = 250 k w v csref e v cscomp , r ilimit = 250 k w v cl /i ilimit r delay = 250 k w , c delay = 4.7 nf 2.9 105 2.9 1.7 3 12 125 10.4 3 1.8 600 3.1 400 145 3.1 1.9 v mv a mv mv/a v v s notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design, not tested in production. specit cations subject to change without notice. rev. a
adp3168 ?3? p arameter symbol conditions min typ max unit soft-start output current, soft-start mode soft-start delay time i delay(ss) t delay(ss) during startup, delay < 2.8 v r delay = 250 k w , c delay = 4.7 nf vid code = 011111 15 20 350 25 a s enable input input low voltage input high voltage input current, input voltage low input current, input voltage high v il(en) v ih(en) i il(en) i ih(en) en = 0 v en = 1.25 v 0.8 e1 10 0.4 +1 25 v v a a power good comparator undervoltage threshold overvoltage threshold output low voltage po w er good delay time vid code changing vid code static crowbar trip point crowbar reset point crowbar delay time vid code changing vid code static v pwrgd(uv) v pwrgd(ov) v ol(pwrgd) v crowbar t crowbar relative to nominal dac output relative to nominal dac output i pwrgd(sink) = 4 ma relative to nominal dac output relative to fbrtn overvoltage to pwm going low e200 90 100 90 450 100 e250 150 225 250 200 150 550 250 400 e325 200 400 200 650 mv mv mv s ns mv mv s ns pwm outputs output voltage low output voltage high v ol(pwm) v oh(pwm) i pwm(sink) = 400 a i pwm(source) = 400 a 4.0 160 5.0 500 mv v supply dc supply current uvlo threshold voltage uvlo hysteresis v uvlo vcc rising 6.5 0.7 5 6.9 0.9 8 7.3 1.1 ma v v specit cations subject to change without notice. rev. a
adp3168 ?4? pin configuration adp3168 top view (not to scale) 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 26 27 19 18 17 16 15 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 128 absolute maximum ratings * vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +15 v fbrtn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v vid0evid5, en, delay, ilimit, cscomp, rt, pwm1epwm4, comp . . . . . . . . . . . . . . . . e0.3 v to +5.5 v sw1esw4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e5 v to +25 v all other inputs and outputs . . . . . . . . . e0.3 v to vcc + 0.3 v operating ambient temperature range . . . . . . . . 0?c to 85?c operating junction temperature . . . . . . . . . . . . . . . . . . . 125?c storage temperature range . . . . . . . . . . . . . . e65?c to +150?c junction to air thermal resistance (
adp3168 ?5? pin function descriptions pin no. mnemonic function 1e6 vid4evid0, vid5 voltage identit cation da c inputs. these six pins are pulled up to an internal reference, providing a logic 1 if left open. when in normal operation mode, the dac output programs the fb regulation voltage from 0.8375 v to 1.6 v. leaving vid4 through vid0 open results in the adp3168 going into a no cpu mode , shutting off its pwm outputs. 7fbrtn feedback return. vid da c and error amplit er refere nce for remote sensing of the output voltage. 8fb feedback inpu t. erro r amplit er inp ut for remote sensing of the output voltage. an external resistor between this pi n and the output voltage sets the no-load offset point. 9comp error amplit er outp ut and compensation point. 10 pwrgd p ower good outp ut. open-drain output that pulls to gnd when the output voltage is outside the proper operating range. 11 en p ower supply enab le input. pulling this pin to gnd disables the pwm outputs. 12 delay soft- start delay and curren t limit latch-off delay setting input. an external resistor and capacitor connected between this pi n and gnd set the soft-start ramp-up time and the overcurrent latch-off delay time. 13 rt frequency settin g resistor input. an external resistor connected between this pin and gnd sets the oscillator frequenc y of the device. 14 r a m pa dj pwm r amp cur r ent input. an external resistor from the converter input voltage to this pin sets the internal pwm ra mp. 15 il imit current limit se t point/enable output. an external resistor from this pin to gnd sets the current limit threshold of the converter. this pin is actively pulled low when the adp3168 en input is low or when vcc is below its uvlo threshold to signal to the driver ic that the driver high-side and low-side outputs should go low. 16 csr ef cur rent sense re ference voltage input. the voltage on this pin is used as the reference for the current sense amplit er an d the power good and crowbar functions. this pin should be connected to the common point of th e output inductors. 17 c ssum current sense summing no de. external resistors from each switch node to this pin sum the average inductor currents to measure the total output current. 18 cscomp current sense co mpensation point. a resistor and a capacitor from this pin to cssum determine the slope of the load line and the positioning loop response time. 19 gnd ground. al l internal biasing and the logic output signals of the device are referenced to this ground. 20e23 sw4esw1 current bala nce inputs. inputs for measuring the current level in each phase. the sw pins of unused phases should be left open. 24e27 pwm4epwm1 logic-leve l pwm outputs. each output is connected to the input of an external mosfet driver, such as th e adp3413 or adp3418. connecting the pwm3 and/or pwm4 outputs to gnd causes that phase to turn off, allowing the adp3168 to operate as a 2-, 3-, or 4 -phase controller. 28 vcc supply voltag e for the device. rev. a
?6? adp3168?typical performance characteristics 4 3 2 1 0 master clock frequency ? mhz r t val ue ? k 0 50 100 150 200 250 300 see equation 1 for frequencies not on this graph tpc 1. master clock frequency vs. r t 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 supply current ? ma master clock frequency ? mhz t a = 25 c 4-phase operation tpc 2. supply current vs. master clock frequency test circuits cssum 18 cscomp 17 28 vcc csref 16 gnd 19 39k 100nf 1k 1.0v adp3168 12v v os = cscomp ? 1v 40 t est circuit 1. current sense ampli er v os cssum 18 cscomp 17 28 vcc csref 16 comp 8 fb 9 gnd 19 200k 10k 200k 1.0v adp3168 v 12v 100nf v fb = fb v = 80mv ? fb v = 0mv t est circuit 2. positioning voltage + 250k 12v 1 f 100nf 100nf vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 28 27 26 21 24 23 22 17 18 19 15 16 20 25 20k adp3168 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj 1 2 3 4 8 10 12 14 5 6 7 9 11 13 1.25v 6-bit code 250k 1k 4.7nf t est circuit 3. closed-loop output voltage accuracy rev. a
adp3168 ?7? vid4 vid3 vid2 vid1 vid0 vid5 v out(nom) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 no cpu 0.8375 v 0.850 v 0.8625 v 0.875 v 0.8875 v 0.900 v 0.9125 v 0.925 v 0.9375 v 0.950 v 0.9625 v 0.975 v 0.9875 v 1.000 v 1.0125 v 1.025 v 1.0375 v 1.050 v 1.0625 v 1.075 v 1.0875 v 1.100 v 1.1125 v 1.125 v 1.1375 v 1.150 v 1.1625 v 1.175 v 1.1875 v 1.200 v 1.2125 v vid4 vid3 vid2 vid1 vid0 vid5 v out(nom) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.225 v 1.2375 v 1.250 v 1.2625 v 1.275 v 1.2875 v 1.300 v 1.3125 v 1.325 v 1.3375 v 1.350 v 1.3625 v 1.375 v 1.3875 v 1.400 v 1.4125 v 1.425 v 1.4375 v 1.450 v 1.4625 v 1.475 v 1.4875 v 1.500 v 1.5125 v 1.525 v 1.5375 v 1.550 v 1.5625 v 1.575 v 1.5875 v 1.600 v x = don?t care ta b le i. output voltage vs. vid code theory of operation the adp316 8 combines a multimode, t xed frequency pwm control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchron ous buck cpu core supply power converters. the internal 6 -bit vid dac conforms to intel?s vrd/vrm 10 specit cations. mult iphase operatio n is important for produc- ing th e high currents and low voltages demanded by today?s microprocessors. handli ng th e high currents in a single-phase converter would place high thermal demands on system compo- nents such as inductors and mosfets. the multimode control of the adp3168 ensures a stable, high performance topology for w during this de tection time. an y external pull-down resistance connected to the pwm pi n should be at least 25 k w to ensure prop er operation. the phas e detection is made during the t rst two cloc k cycles of the internal oscillator. after this time, if the pwm output is not grounded, the 5 k w resistance is removed and switches between 0 v and 5 v. if the pwm output was grounded, it remains off. rev. a
adp3168 ?8? the pwm outputs become logic-level devices once normal opera- tion starts. the detection is normal and is intended for driving external gate drivers such as the adp3418. since each phase is monitored independently, operation approaching 100% duty c ycle is possible. also, more than one output can be on at any gi v en time for overlapping phases. master clock frequency the clock frequency of the adp3168 is set with an external resistor connected from the rt pin to ground. the frequency fol- lows the graph in tpc 1. to determine the frequency per phase, the clock is divided by the number of phases in use. if pwm4 is g rounded, divide the master clock by 3 for the frequency of the remaining phases. if pwm3 and pwm4 are grounded, divide by 2. if all phases are in use, divide by 4. output voltage differential sensing the adp3168 combines differential sensing with a high accuracy vid dac and reference and a low offset error amplit er to main- tain a worst-case specit cation of 10 mv differential sensing error with a vid input of 1.6000 v over its full operating output v oltage and temperature range. the output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remote sense ground point. the internal vid dac and precision reference are referenced to fbrtn, which has a minimal current of 90 a to allow accurate remote sensing. the internal error amplit er compares the output of the dac to the fb pin to regu- late the output voltage. output current sensing the adp3168 provides a dedicated current sense amplit er (csa) to monitor the total output current for proper voltage positioning ve r sus load current and for current limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side mosfet. this amplit er can be con- t gured several ways, depending on the objectives of the system: w will make a substantial increase in phase current. increase each r sw value by small amounts to achieve balance, starting with the coolest phase t rst. v oltage control mode a high gain-bandwidth voltage mode error amplit er is used for the voltage-mode control loop. the control input voltage to the positive input is set via the vid 6-bit logic code, according to the v oltages listed in table i. this voltage is also offset by the droop v oltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplit er is the comp pin, which sets the termina- tion voltage for the internal pwm ramps. the negative input (fb) is tied to the output sense location with a resistor r b and is used for sensing and controlling the output v oltage at this point. a current source from the fb pin ? owi ng through r b is used for setting the no-load offset voltage from the vid voltage. the no-load voltage will be negative with respect to the vid dac. the main loop compensation is incorporated into the feedback network between fb and comp. rev. a
adp3168 ?9? soft-start the power-on ramp-up time of the output voltage is set with a capacitor and a resistor in parallel from the delay pin to g round. the rc time constant also determines the current limit latch-off time as explained in the following section. in uvlo or when en is a logic low, the delay pin is held at ground. after the uvlo threshold is reached and en is a logic high, the delay capacitor is charged up with an internal 20 a cur- rent source. the output voltage follows the ramping voltage on the delay pin, limiting the inrush current. the soft-start time depends on the values of vid dac and c dly , with a secondary effect from r dly . refer to the application information section for detailed information on setting c dly . when the pwrgd threshold is reached, the soft-start cycle is stopped and the delay pin is pulled up to 3 v. this ensures that the output voltage is at the vid voltage when the pwrgd signals to the system that the output voltage is good. if en is taken low or vcc drops below uvlo, the delay capacitor is reset to ground to be ready for another soft-start cycle. figure 1 shows a typical start-up sequence for the adp3168. figure 1. start-up waveforms, circuit of figure 5. channel 1?wrgd, channel 2? out , channel 3 high-side mosfet v gs , channel 4?ow-side mosfet v gs current limit, short circuit, and latch-off protection the adp3168 compares a programmable current limit set point to the voltage from the output of the current sense ampli er. the level of current limit is set with the resistor from the ilimit pin to ground. during normal operation, the voltage on ilimit is 3 v. the current through the external resistor is internally scaled to gi ve a current limit threshold of 10.4 mv/?. if the difference in v oltage between csref and cscomp rises above the current limit threshold, the internal current limit ampli er will control the internal comp voltage to maintain the average output current at the limit. after the limit is reached, the 3 v pull-up on the delay pin is disconnected, and the external delay capacitor is discharged through the external resistor. a comparator monitors the delay v oltage and shuts off the controller when the voltage drops below 1.8 v. the current limit latch-off delay time is therefore set by the rc time constant discharging from 3 v to 1.8 v. the ap plication information section discusses the selection of c dly and r dly . because th e controller continues to cycle the phases during the latch-off delay time, if th e short is removed before the 1.8 v threshold is reached, the cont roller wi ll return to normal opera- tion. th e recovery characteristic depends on the state of pwrgd. if th e output voltage is within the pwrgd window, the controller resumes normal operation. however, if a short circuit has caused the outp ut voltage to drop below the pwrgd threshold, a soft- start cycl e is in itiated. the latch-off function can be reset either by removing and reap- plying vcc to the adp3168 or by pulling the en pin low for a short time. to disable the short circuit latch-off function, the external resistor to ground should be left open, and a high value (>1 m w ) resistor should be connected from delay to vcc. this prevents the delay capacitor from discharging, so the 1.8 v threshold is never reached. the resistor will have an impact on the soft-start time because the current through it will add to the internal 20 a current source. figure 2. overcurrent latch-off waveforms, circuit of figure 4. channel 1?wrgd, channel 2? out , channel 3?scomp pin of adp31 68, channel 4 high-side mosfet vgs during startup, when the output voltage is below 200 mv, a secondary current limit is active. this is necessary because the v oltage swing of cscomp cannot go below ground. this sec- ondary current limit controls the internal comp voltage to the pwm comparators to 2 v. this will limit the voltage drop across the low-side mosfets through the current balance circuitry. there is also an inherent per-phase current limit that will protect individual phases in the case where one or more phases may stop functioning because of a faulty component. this limit is based on the maximum normal mode comp voltage. dynamic vid the adp3168 incorporates the ability to dynamically change the vid input while the controller is running. this allows the output v oltage to change while the supply is running and supplying cur- rent to the load. this is commonly referred to as vid on-the- y (otf). a vid otf can occur under either light load or heavy load conditions. the processor signals the controller by changing the vid inputs in multiple steps from the start code to the nish code. this change can be either positive or negative. rev. a
adp3168 ?10? when a vid input changes state, the adp3168 detects the change and ignores the dac inputs for a minimum of 400 ns. this pre- v ents a false code due to logic skew while the six vid inputs are changing. additionally, the t r st vid change initiates the pwrgd and crowbar blanking functions for a minimum of 250 s to prevent a false pwrgd or crowbar event. each vid change will reset the internal timer. figure 3 shows vid on-the-? y performance when the output voltage is stepping up and the output current is switching between minimum and maximum values, which is the worst-case situation. figure 3. vid on-the-fly waveforms, circuit of figure 5. vid change = 5 mv, 5 s per step, 50 steps, i out change = 5 a to 65 a po w er good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits speci ed in the speci- cations table based on the vid voltage setting. pwrgd will go low if the output voltage is outside of this speci ed range. pwrgd is blanked during a vid otf event for a period of 250 ? to prevent f alse signals during the time the output is changing. output crowbar as part of the protection for the load and output components of the supply, the pwm outputs will be driven low (turning on the low-side mosfets) when the output voltage exceeds the upper po w er good threshold. this crowbar action will stop once the output voltage has fallen below the release threshold of approxi- mately 450 mv. tu r ning on the low-side mosfets pulls down the output as the reverse current builds up in the inductors. if the output overvolt- age is due to a short of the high-side mosfet, this action will current limit the input supply or blow its fuse, protecting the microprocessor from destruction. output enable and uvlo the input supply (vcc) to the controller must be higher than the uvlo threshold and the en pin must be higher than its logic threshold for the adp3168 to begin switching. if uvlo is less than the threshold or the en pin is a logic low, the adp3168 is disabled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and holds the ilimit pin at ground. in the application circuit, the ilimit pin should be connected to the od d d d ooo d input voltage (v in ) = 12 v vid setting voltage (v vid ) = 1.500 v duty cycle (d) = 0.125 nominal output voltage at no load (v onl ) = 1.480 v nominal output voltage at 65 a load (v ofl ) = 1.3955 v static output voltage drop based on a 1.3 m w load line (r o ) from no load to full load (v d ) = v onl e v ofl = 1.480 v e 1.3955 v = 84.5 mv maximum output current (i o ) = 65 a maximum output current step ( d i o ) = 60 a number of phases (n) = 3 switching frequency per phase (f sw ) = 267 khz setting the clock frequency the adp3168 uses a t x ed-frequency control architecture. the frequency is set by an external timing resistor (r t ). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. with n = 3 for three phases, a clock frequency of 800 khz sets the switching frequency of each phase, f sw , to 267 khz, which represents a practical trade-off between the switching losses and the sizes of the output t lter components. tpc 1 shows that to achieve an 800 khz oscillator frequency, the correct value for r t is 249 k w . alternatively, the value for r t can be calculated using r nf pf m t sw = () - 1 583 1 15 . . w (1) where 5.83 pf and 1.5 m w are internal ic component values. f or good initial accuracy and frequency stability, a 1% resistor is rec ommended. rev. a
adp3168 ?11? enable * for a description of optional r sw resistors, see the theory of operation section. power good r lim 200k c dly 39nf r t 249k r dly 390k r a 16.9k c fb 33pf c a 390pf c cs1 2.2nf r b 1.33k c b 1.5nf r ph1 124k from cpu r r 383k c cs2 1.5nf r cs1 35.7k r ph3 124k r sw1 * r sw3 * r sw2 * r cs2 73.2k r ph2 124k u1 adp3168 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 3 1 4 5 2 6 10 14 7 8 9 11 12 13 26 25 24 28 27 19 22 21 20 23 15 18 17 16 c19 1 f r4 10 c20 33 f q8 ipd06n03l l4 600nh/1.6m bst in od vcc drvh sw pgnd drvl c15 4.7 f c18 4.7nf r3 2.2 r th 100k , 5% q9 ipd06n03l 1 2 3 8 7 6 45 u4 adp3418 d4 1n4148ws c17 4.7 f q7 ipd12n03l c16 100nf q5 ipd06n03l c12 100nf u3 adp3418 bst in od vcc drvh sw pgnd drvl c11 4.7 f d3 1n4148ws c14 4.7nf r2 2.2 q6 ipd06n03l 1 2 3 8 7 6 4 5 q2 ipd06n03l q3 ipd06n03l q4 ipd12n03l l3 600nh/1.6m c7 4.7 f c13 4.7 f 10 f 23mlcc around socket v cc(core) 0.8375v?1.6v 65a avg, 74a p k v cc(core) rtn 820 f/2.5v 8 fujitsu re series 8m esr (each) l2 600nh/1.6m c21 c28 c10 4.7nf r1 2.2 q1 ipd12n03l c8 100nf c9 4.7 f u2 adp3418 1 2 3 8 7 6 45 bst in od vcc drvh sw pgnd drvl ++ + d2 1n4148ws d1 1n4148ws v in 12v v in rtn l1 1.6 h c1 c6 470 f/16v 6 nichicon pw series ++ figure 4. 65 a intel pentium 4 cpu supply circuit, vrd 10 design rev. a
adp3168 ?12? soft-start and current limit latch-off delay times because the soft-start and current limit latch-off delay functions share the delay pin, these two parameters must be considered together. the t r st step is to set c dly for the soft-start ramp. this ramp is generated with a 20 a internal current source. the value of r dly will have a second order impact on the soft-start time because it sinks part of the current source to ground. however, as long as r dly is kept greater than 200 k w , this effect is minor. the v alue for c dly can be approximated using ca v r t v dly vid dly ss vid =- ? ? ? 20 2 m (2) where t ss is the desired soft-start time. assuming an r dly of 390 k w and a desired a soft-start time of 3 ms, c dly is 36 nf. the closest standard value for c dly is 39 nf. once c dly has been chosen, r dly can be calculated for the current limit latch-off time using r t c dly delay dly = 196 . (3) if the result for r dly is less than 200 k w , a smaller soft-start time should be considered by recalculating the equation for c dly , or a longer latch-off time should be used. in no case should r dly be less than 200 k w . in this example, a delay time of 8 ms gives r dly = 402 k w . the closest standard 5% value is 390 k w . inductor selection the choice of inductance for the inductor determines the ripple current in the inductor. less inductance leads to more ripple cur- rent, which increases the output ripple voltage and conduction losses in the mosfets but allows using smaller inductors and, for a specit ed peak-to-peak transient deviation, less total output capacitance. conversely, a higher inductance means lower ripple current and reduced conduction losses but requires larger induc- tors and more output capacitance for the same peak-to-peak transient deviation. in any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. i vd fl r vid sw = - () 1 (4) l vr nd fv vid o sw ripple - () () 1 (5) solving equation 5 for a 10 mv p-p output ripple voltage yields: l vm khz mv nh - () = 15 13 1 0375 267 10 456 .. . w if the resulting ripple voltage is less than that designed for, the induc tor can be made smaller until the ripple value is met. this will allow optimal transient response and minimum output decoup ling. the smallest possible inductor should be used to minimize the number of output capacitors. choosing a 600 nh inductor is a good starting point and gives a calculated ripple current of 8.2 a. the inductor should not saturate at the peak current of 25.8 a and should be able to handle the sum of the power dissipation caused by the average current of 22.7 a in the winding and core loss. another important factor in the inductor design is the dcr, which is used for measuring the phase currents. a large dcr will cause excessive power losses, while too small a value will lead to increased measurement error. a good rule is to have the dcr be about 1 to 1? times the droop resistance (r o ). our example uses an inductor with a dcr of 1.6 m w . designing an inductor once the inductance and dcr are known, the next step is to either design an inductor or t nd a standard inductor that comes as close as possible to meeting the overall design goals. it is also important to have the inductance and dcr tolerance speci- t ed to control the accuracy of the system. 15% inductance and 8% dcr (at room temperature) are reasonable tolerances that most manufacturers can meet. the t r st decision in designing the inductor is to choose the core material. there are several possibilities for providing low core loss at high frequencies. two examples are the powder cores (e.g., kool-m from magnetics, inc. or micrometals) and the gapped soft ferrite cores (e.g., 3f3 or 3f4 from philips). low fre- quency po wdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. the best choice for a core geometry is a closed-loop type such as a pot core, pq, u, or e core or toroid. a good compromise between price and performance is a core with a toroidal shape. there are many useful references for quickly designing a power inductor, such as magnetics design references magnetic designer software intusoft (www.intusoft.com) designing magnetic components for high-frequency dc-dc converters , by william t. mclyman, kg magnetics, inc., isbn 1883107008 selecting a standard inductor the companies listed below can provide design consultation and deliver power inductors optimized for high power applications upon request. po w er inductor manufacturers coilcraft (847)639-6400 www.coilcraft.com coiltronics (561)752-5000 www.coiltronics.com sumida electric company (510) 668-0660 www.sumida.com vishay intertechnology (402) 563-6866 www.vishay.com rev. a
adp3168 ?13? output droop resistance the design requires that the regulator output voltage measured at the cpu pins drops when the output current increases. the specit ed voltage drop corresponds to a dc output resistance (r o ). the output current is measured by summing together the voltage across each inductor and passing the signal through a low-pass t lter. this summer t lter is the cs amplit er cont gured with resistors r ph(x) (summers), and r cs and c cs (t lter). the output resistance of the regulator is set by the following equations, where r l is the dcr of the output inductors: r r r r o cs ph x l = () (6) c l rr cs lcs = (7) one has the ? exibility of choosing either r cs or r ph(x) . it is best to select r cs equal to 100 k w , and then solve for r ph(x) by rear- ranging equation 6. r r r r r m m kk ph x l o cs ph x () () = == 16 13 100 123 . . w w ww next, use equation 6 to solve for c cs . c nh mk nf cs = = 600 16 100 375 . . ww it is best to have a dual location for c cs in the layout so standard v alues can be used in parallel to get as close to the value desired. f or this example, choosing c cs to be 1.5 nf and 2.2 nf in parallel is a good choice. for best accuracy, c cs should be a 5% or 10% npo capacitor. the closest standard 1% value for r ph(x) is 124 k w . inductor dcr temperature correction with the inductor?s dcr being used as the sense element and copper wire being the source of the dcr, one needs to compensate for temperature changes of the inductor?s winding. fortunately, copper has a well known temperature coeft cient (tc) of 0.39%/?c. if r cs is designed to have an opposite and equal percentage change in resistance to that of the wire, it will cancel the temperature va ri a tion of the inductor?s dcr. due to the nonlinear nature of ntc thermistors, resistors r cs1 and r cs2 are needed (see figure 5) to linearize the ntc and produce the desired temperature tracking. cssum 18 cscomp place as close as possible to nearest inductor or low-side mosfet 17 csref 16 adp3168 c cs 1.8nf r cs1 r th r cs2 keep this path as short as possible and well away from switch node lines to switch nodes to v out sense r ph1 r ph3 r ph2 figure 5. temperature compensation circuit values the following procedure and expressions will yield values to use for r cs1 , r cs2 , and r th (the thermistor value at 25?) for a given r cs value. 1. select an ntc based on type and value. since we do not have a value yet, start with a thermistor with a value close to r cs . the ntc should also have an initial tolerance of better than 5%. 2. based on the type of ntc, nd its relative resistance value at two temperatures. the temperatures that work well are 50? and 90?. we will call these resistance values a (r th(50?) /r th(25?) ) and b (r th(90?) /r th(25?) ). note that the ntcs relative value is always 1 at 25?. 3. find the relative value of r cs required for each of these tem- peratures. this is based on the percentage change needed, which in this example is initially 0.39%/?. these are called r 1 (1/(1 + tc r 2 (1/(1 + tc r cs 1 , r cs 2 , and r th using: r ab r r a b r b a r abrb arab r a r a rr r rr cs cs cs cs th cs cs 2 12 2 1 12 1 21 2 21 11 11 1 1 1 1 1 1 1 = - () - - () +- () - () - - () - - () = - () - - - = - - (8) 5. calculate r th = r th k based on the ratio of the actual thermistor value used relative to the computed one: k r r th actual th calculated = () () (9) 6. finally, calculate values for r cs 1 and r cs 2 using equation 10: rrkr rr kkr cs cs cs cs cs cs 11 22 1 = =- () + () () (10) f or this example, r cs has been chosen to be 100 k w , so we start with a thermistor value of 100 k w . looking through available 0603 size thermistors, we t nd a vishay nths0603n01n1003jr ntc thermistor with a = 0.3602 and b = 0.09174. from these we compute r cs 1 = 0.3796, r cs 2 = 0.7195, and r th = 1.0751. solving for r th yields 107.51 k w , so we choose 100 k w , making k = 0.9302. finally, we t nd r cs 1 and r cs 2 to be 35.3 k w and 73.9 k w . choosing the closest 1% resistor values yields a choice of 35.7 k w and 73.2 k w . rev. a
adp3168 ?14? output offset intel?s speci? cation requires that at no load the nominal output voltage of the regulator be offset to a lower value than the nominal voltag e corresponding to the vid code. the offset is set by a constant current source ? owing o ut of the fb pin ( i fb ) and ? owing th rough r b . the value of r b can be found using equation 11: r vv i r vv a k b vid onl fb b = ? = ? = 15 1480 15 133 .. . ? (11) the closest standard 1% resistor value is 1.33 k w . c out selection the required output decoupling for the regulator is typically recommended by intel for various processors and platforms. one can also use some simple design guidelines to determine what is required. these guidelines are based on having both bulk and ceramic capacitors in the system. the ? r st thing is to select the total amount of ceramic capaci- tance. this is based on the number and type of capacitor to be used. the best location for ceramics is inside the socket, with 12 to 18 of size 1206 being the physical limit. others can be placed along the outer edge of the socket as well. combined ceramic values of 200 f to 300 f are recommended, usually made up of multiple 10 f or 22 f capacitors. select the number of ceramics and ? nd the total ceramic capacitance (c z ). next, there is an upper limit imposed on the total amount of bulk capacitance ( c x ) when one considers the vid on-the-? y voltage stepping of the output (voltage step v v in time t v with error of v err ) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step d i o : c li nr v c xmin o o vid z () ? ? ? ? ? ? ? ? (12) c l nk r v v t v v nkr l c where k n v v xmax o v vid v vid v o z err v () + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? =? ? ? ? ? ? ? 22 2 11 l (13) to meet the conditions of these expressions and transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is larger than c x(max) , the system will not meet the vid on-the-? y speci- ? cation and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). f or our example, 23 10 f 1206 mlc capacitors (c z = 230 f) w ere used. the vid on-the-? y step change is 250 mv in 150 s with a setting error of 2.5 mv. solving for the bulk capacitance yields c nh a m v f mf xmin () ? ? ? ? ? ? ? = 600 60 313 15 230 5 92 .. . ? c nh mv mv sv m mv nh f mf k x max () + ? ? ? ? ? ? ? ? ? ? ? ? ? ? = = 600 250 346 13 15 1 150 1 5 3 4 6 1 3 250 600 1 230 23 9 46 22 2 .(. ). ... . . ? ? where using eight 820 f a1-polys with a typical esr of 8 m w each yields c x = 6.56 mf with an r x = 1.0 m w. one last check should be made to ensure that the esl of the bulk capacitors ( l x ) is low enough to limit the initial high frequency transient spike. this is tested using lcr l f m ph xzo x ? ? = 2 2 230 1 3 389 (. ) ? (14) in this example, l x is 375 ph for the eight a1-polys capacitors, which satis? es this limitation. if the l x of the chosen bulk capaci- tor bank is too large, the number of capacitors must be increased. one should note that for this multimode control technique, all ceramic designs can be used as long as the conditions of equa- tions 11, 12, and 13 are satis? ed. po w er mosfets f or this example, the n-channel power mosfets have been selected for one high side switch and two low-side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . the minimum gate drive v oltage (the supply voltage to the adp3418) dictates whether standard threshold or logic-level threshold mosfets must be used. with v gate ~10 v, logic-level threshold mosfets (v gs(th) < 2.5 v) are recommended. the maximum output current i o determines the r ds(on) require- ment for the low-side (synchronous) mosfets. with the adp3168, currents are balanced between phases, thus the current in each low-side mosfet is the output current divided by the total num ber of mosfets ( n sf ). with conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous mosfet in terms of the ripple current per phase ( i r ) and average total output current ( i o ): pd i n ni n r sf o sf r sf ds sf =? () ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1 1 12 22 (15) knowing the maximum output current being designed for and the maximum allowed power dissipation, one can ? nd the required r ds(on) for the mosfet. for d-pak mosfets up to an am- bient temperature of 50oc, a safe limit for psf is 1 w to 1.5 w at 120oc junction temperature. thus, for this example (65 a maxi- mum), we ? nd r ds(sf) (per mosfet) < 8.7 m w . this r ds(sf) is also at a junction temperature of about 120oc, so we need to make sure we account for this w hen making this selection. for this example, we selected two lower side mosfets at 7 m w each at room temperature, which gives 8.4 m w at high temperature. rev. a
adp3168 ?15? another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feed- back to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous mosfets when the switch node goes high. also, the time to switch the synchronous mosfets off should not exceed the nonoverlap dead time of the mosfet driver (40 ns typical for the adp3418). the output impedance of the driver is about 2 w and the typical mosfet input gate resistances are about 1 w to 2 w , so a total gate capacitance of less than 6000 pf should be adhered to. since there are two mosfets in parallel, the input capacitance for each synchronous mosfet should be limited to 3000 pf. the high-side (main) mosfet has to be able to handle two main power dissipation components: conduction and switching losses. the switching loss is related to the amount of time it takes for the main mosfet to turn on and off, and to the current and v oltage that are being switched. basing the switching speed on the rise and fall time of the gate driver impedance and mosfet input capacitance, the following expression provides an approxi- mate value for the switching loss per main mosfet, where n mf is the total number of main mosfets: pf vi n r n n c smf sw cc o mf g mf iss () = 2 (16) here, r g is the total gate resistance (2 w for the adp3418 and about 1 w for typical high speed switching mosfets, making r g = 3 w ) and c iss is the input capacitance of the main mosfet. it is interesting to note that adding more main mosfets ( n mf ) does not really help the switching loss per mosfet since the additional gate capacitance slows switching. the best thing to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by the fol- lowing, where r ds(mf) is the on resistance of the mosfet: pd i n ni n r cmf o mf r mf ds mf () () = ? ? ? + ? ? ? ? ? ? ? ? 22 1 12 (17) t ypically, for main mosfets, the highest speed (low c iss ) device is preferred, but these usually have higher on resistance. select a device that meets the total power dissipation (about 1.5 w for a single d-pak) when combining the switching and conduc- tion losses. f or this example, an int neon ipd12n03l was selected as the main mosfet (three total; n mf = 3), with a c iss = 1460 pf (max) and r ds(mf) = 14 m w w (max at t j = 120?c). the synchronous mosfet c iss is less than 3000 pf, satisfying that requirement. solving for the power dissipation per mosfet at i o = 65 a and i r = 8.2 a yields 863 mw for each synchronous mosfet and 1.44 w for each main mosfet. these numbers work well considering there is usually more pcb area available for each main mos- fet versus each synchronous mosfet. one last thing to consider is the power dissipation in the driver for each phase. this is best described in terms of the q g for the mosfets and is given by the following, where q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet: p f n nq nq i v drv sw mf gmf sf gsf cc cc = + () + ? ? ? ? 2 (18) also shown is the standby dissipation factor ( i cc v cc ) for the driver. for the adp3418, the maximum dissipation should be less than 400 mw. for our example, with i cc = 7 ma, q gmf = 22.8 nc, and q gsf = 34.3 nc, we t nd 260 mw in each driver, which is below the 400 mw dissipation limit. see the adp3418 data sheet for more details. ramp resistor selection the ramp resistor ( r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. the following expression is used for determining the optimum value: r al ar c r nh mpf k r r ddsr r = = = 3 02 600 3542 5 381 . . w w (19) where a r is the internal ramp amplit er gain, a d is the current balancing amplit er gain, r ds is the total low-side mosfet on resistance, and c r is the internal ramp capacitor value. the closest standard 1% resistor value is 383 k w . the internal ramp voltage magnitude can be calculated using v adv rc f v v kpf khz v r r vid rrsw r = - () = - () = 1 02 1 0125 15 383 5 267 051 ... . w (20) the size of the internal ramp can be made larger or smaller. if it is made larger, stability and transient response will improve, bu t thermal balance will degrade. likewise, if the ramp is made smaller, thermal balance will improve at the sacrit ce of transient response and stability. the factor of three in the denominator of equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. comp pin ramp there is a ramp signal on the comp pin due to the droop volt- age and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input. v v nd nf c r rt r sw x o = - - () ? ? ? 1 21 (21) f or this example, the overall ramp signal is found to be 0.63 v. rev. a
adp3168 ?16? current limit set point to select the current limit set point, ? rst ? nd the resistor value for r lim . the current limit threshold for the adp3168 is set with a 3 v source ( v lim ) across r lim with a gain of 10.4 mv/a ( a lim ). r lim can be found using the following: r av ir lim lim lim lim o = (22) f or values of r lim greater than 500 k w , the current limit may be lower than expected, so some adjustment of r lim may be needed. here, i lim is the average current limit for the output of the sup- ply. for our example, choosing 120 a for i lim , we ? nd r lim to be 200 k w , for which we chose 200 k w as the nearest 1% value. the per-phase current limit described earlier has its limit deter- mined by the following: i vvv ar i phlim comp max r bias d ds max r ? ?? ? () () 2 (23) f or the adp3168, the maximum comp voltage ( v comp(max) ) is 3.3 v, the comp pin bias voltage ( v bias ) is 1.2 v, and the cur- rent balancing ampli? er gain ( a d ) is 5. using v r of 0.63 v and r ds(max) of 4.2 m w (low-side on resistance at 150c), we ? nd a per phase limit of 66 a. this limit can be adjusted by changing the ramp voltage v r , b ut make sure not to set the per-phase limit lower than the average per-phase current (i lim /n). there is also a per-phase initial duty cycle limit determined by dd vv v max comp max bias rt = ? () (24) f or this example, the maximum duty cycle is found to be 0.42. f eedback loop compensation design optimized compensation of the adp3168 allows the best pos- sible response of the regulator?s output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output imped- ance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (r o ). with the resistive output impedance, the output voltage will droop in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output decoupling. with the multimode feedback structure of the adp3168, the feedback compensation must be set to make the converter?s out- put impedance, working in parallel with the output decoupling, meet this goal. there are several poles and zeros created by the output inductor and decoupling capacitors (output ? lter) that need to be compensated for. a type-three compensator on the voltage feedback is adequate for proper compensation of the output ? lter. the expressions given in equations 25 to 29 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects (see the tuning procedure for the adp3168 section). the ? r st step is to compute the time constants for all of the poles and zeros in the system: rnrar rv v 2l 1nd v nc r v r m m m v v nh v mf m v eodds lrt vid rt xo vid e = + + + ? () = + + + ? () = 313 5 42 16 063 15 2 600 1 0 375 0 63 3656 13 15 37 .. .. . .. ... ?? ? ? . .9 m ? (25) tc rr' l r rr' r mf m m ph m m m m s ax o x o o x = ? () + ? =? () + ? = 656 13 06 375 13 13 06 10 479 ... . .. . . ?? ? ?? ? (26) trr'rc m m m mf s bx ox =+? () = + ? () = 10 06 13 656 197 ... . . ??? (27) t vl ar f vr v nh m khz v m s c rt dds sw vid e = ? ? ? ? ? ? ? = ? ? ? ? ? ? ? = 2 063 600 542 2 267 15 37 9 62 . . .. . ? ? (28) t ccr crrcr mf f m mf m m f m ns d xzo xo zo = ? () + = ? () + = 22 656 230 13 656 13 06 230 13 521 ' .(.) ... . ? ?? ? (29) where, for the adp3168, r ' is the pcb resistance from the bulk capacitors to the ceramics and where r ds is the total low side mosfet on resistance per phase. for this example, a d is 5, v rt equals 0.63 v, r ' is approximately 0.6 m w (assuming a 4-layer motherboard), and l x is 375 ph for the eight al-poly capacitors. rev. a
adp3168 ?17? the compensation values can then be solved using the following: c nr t rr c m s m k pf a oa eb a = = = 313 479 37 9 1 33 371 .. .. ? ?? (30) r t c s pf k a c a == = 62 371 16 7 . . ? (31) c t r . s . k nf b b b == = 197 133 148 ? . (32) c t r ns . pf fb d a == = 521 16 7 31 2 k . ? (33) choosing the closest standard values for these components yields cpfrkc nf c pf aa bfb == == 390 16 9 1 5 33 ,.,., ? figure 6 shows the typical transient response using the compen- sation values. figure 6. typical transient response for design example c in selection and input current di/dt reduction in continuous inductor current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n v out /v in and an amplitude of one-nth of the maximum output current. to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by idi nd ia a crms o crms = ? = ?= 1 1 0 125 65 1 30 125 1105 . . . (34) note that the capacitor manufacturer?s ripple current ratings are often based on only 2,000 hours of life. this makes it advisable to further derate the capacitor or choose a capacitor rated at a higher temperature than required. several capacitors may be placed in parallel to meet size or height requirements in the design. in this example, the input capacitor bank is formed by three 2,200 f, 16 v nichicon capacitors with a ripple current rating of 3.5 a each. to reduce the input current di/dt to a level below the recom- mended maximum of 0.1 a/s, an additional small inductor (l > 1 h @ 15 a) should be inserted between the converter and the supply bus. that inductor also acts as a ? lter between the converter and the primary power source. rr vv vv cs new cs old nl flcold nl flhot 22 () () = ? () ? () (35) 0 10 20 30 40 50 60 100 80 60 40 20 0 efficiency ? % output current ? a figure 7. ef ciency of the circuit of figure 4 vs. output current tuning procedure for the adp3168 1. build circuit based on compensation values computed from design spreadsheet. 2. hook up dc load to circuit, turn on, and verify operation. also check for jitter at no-load and full-load. dc loadline setting 3. measure output voltage at no-load (v nl ). verify that it is within tolerance. 4. measure output voltage at full-load cold (v flcold ). let board set for ~10 minutes at full-load and measure output (v flhot ). if there is a change of more than a couple of milliv olts, adjust r cs1 and r cs2 using equations 35 and 37. 5. repeat step 4 until cold and hot voltage measurements remain the same. 6. measure output voltage from no-load to full-load using 5 a steps. compute the loadline slope for each change and then av erage to get overall loadline slope (r omeas ). 7. if r omeas is off from r o by more than 0.05 m w , use the following to adjust the r ph values: rr r r ph new ph old omeas o () () = (36) 8. repeat steps 6 and 7 to check loadline and repeat adjustments if necessary. 9. once complete with dc loadline adjustment, do not change r ph , r cs1 , r cs2 , or r th for rest of procedure. 10. measure output ripple at no-load and full-load with scope and make sure it is within speci? cations. rev. a
adp3168 ?18? ac loadline setting 11. remove dc load from circuit and hook up dynamic load. 12. hook up scope to output voltage and set to dc coupling with time scale at 100 s/div. 13. set dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 14. measure output waveform (may have to use dc offset on scope to see waveform). try to use vertical scale of 100 mv/div or t ner. 15. this waveform should look something like figure 8. use the horizontal cursors to measure v acdrp and v dcdrp as shown. do not measure the undershoot or overshoot that happens immediately after the step. v acdrp v dcdrp figure 8. ac loadline waveform 16. if the v acdrp and v dcdrp are different by more than a couple of millivolts, use equation 38 to adjust c cs . y ou may need to parallel different values to get the right one since there are limited standard capacitor values available. (it is a good idea to have locations for two capacitors in the layout for this.) cc v v cs new cs old acdrp dcdrp () () = (38) 17. repeat steps 11 to 13 and repeat adjustments if necessary. once complete, do not change c cs for the rest of the procedure. 18. set dynamic load step to maximum step size (do not use a step size larger than needed) and verify that the output wave- form is square (which means v acdrp and v dcdrp are equal). note: make sure load step slew rate and turn-on are set for a slew rate of ~150 a/s to 250 a/s (for example, a load step of 50 a should take 200 ns to 300 ns) with no overshoot. some dynamic loads will have an excessive turn-on overshoot if a minimum current is not set properly. (this is an issue if using a vtt tool.) initial transient setting 19. with dynamic load still set at maximum step size, expand scope time scale to see 2 s/div to 5 s/div. the waveform may have two overshoots and one minor undershoot (see figure 9). here, v droop is the t nal desired value. v droop v tran1 v tran2 figure 9. transient setting waveform 20. if both overshoots are larger than desired, try making the adjustments described below. (note: if these adjustments do not change the response, you are limited by the output decoupling.) check the output response each time you make a change as well as the switching nodes (to make sure the response is still stable). a. make ramp resistor larger by 25% (r ramp ). b. for v tran1 , increase c b or increase switching frequency. c. for v tran2 , increase r a and decrease c a by 25%. 21. for load release (see figure 10), if v tranrel is larger than v tran1 (see figure 9), there is not enough output capaci- tance. you will either need more capacitance or have to make the in ductor values smaller. (if you change inductors, y ou will need to start the design over using the spreadsheet and this tuning procedure.) v droop v tranrel figure 10. transient setting waveform since the adp3168 turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. thus, you do not have to add headroom for ripple, allowing your load release v tranrel to be larger than v tran1 by the amount of r ipple and still meet speci cations. if v tran1 and v tranrel are less than the desired nal droop, this implies that capacitors can be removed. when removing capaci- tors, check the output ripple voltage as well to make sure it is still within speci cations. r rr rr r r rr r cs new cs old th c cs old th c cs old cs new cs old th c th c 2 125 12522 125 25 1 1 () () () () () () () () () () = + + - () - () - (37) rev. a
adp3168 ?19? layout and component placement the following guidelines are recommended for optimal perfor- mance of a switching regulator in a pc system. key layout issues are illustrated in figure 11. 12v connector input power plane thermistor output power plane cpu socket keep-out area keep-out area switch node planes keep-out area keep-out area figure 11. layout recommendations general recommendations for good results, a pcb with at least four layers is recom- mended. this should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input, and output power, and wide inter- connection traces in the rest of the power delivery current paths. keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m w at room temperature. whenever high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. if critical signal lines (including the output voltage sense lines of the adp3168) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. an analog ground plane should be used around and under the adp3168 as a reference for the components associated with the controller. this plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from ? o wing in it. the components around the adp3168 should be located close to the controller with short traces. the most important traces to keep short and away from other traces are the fb and cssum pins. refer to figure 11 for more details on layout for the cssum node. the output capacitors should be connected as close as poss ible to the load (or connector) that receives the power (e.g., a microprocessor core). if the load is distributed, the capacitors should also be distributed and generally in proportion to where the load tends to be more dynamic. avoid crossing any signal lines over the switching power path loop, described in the power circuitry section. po we r circuitry the switching power path should be routed on the pcb to encompass the shortest possible length in order to minimize radiated switching noise energy (i.e., emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise-related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets including all interconnecting pcb traces and planes. the use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. whenever a power dissipating component (e.g., a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on th e mounting pad and immediately surround- ing it , is recommended. two important reasons for this are improved curren t rating through the vias and improved thermal perf ormance from vias extended to the opposite side of th e pcb, where a plane can more readily transfer the heat to the air. make a mirror image of any pad being used to heatsink the mosfets on the opposite side of the pcb to achieve the best thermal dissipation to the air around the board. to further improve therma l performance, use the largest possib le pad area. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. signal circuitry the output voltage is sensed and regulated between the fb pin and the fbrtn pin, which connects to the signal ground at the load. to avoid differential mode noise pickup in the sensed signal, the loop area should be small. thus the fb and fbrtn traces should be routed adjacent to each other on top of the power ground plane back to the controller. the feedback traces from the switch nodes should be con- nected as close as possible to the inductor. the csref signal should be connected to the output voltage at the nearest inductor to the controller. rev. a
c03258?0?4/03(a) ?20? adp3168 outline dimensions 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 6.40 bsc pin 1 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ae coplanarity 0.10 revision history location page 4/03?data sheet changed from rev. 0 to rev. a. changes to speci? cations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 rev. a

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