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wirelessusb? lp 2.4ghz radio soc CYRF6936 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-16015 rev. *f revised july 18, 2006 1.0 features ? 2.4-ghz direct sequence spread spectrum (dsss) radio transceiver ? operates in the unlicensed worldwide industrial, scientific and medical (ism) band (2.400 ghz?2.483 ghz) ? 21ma operating current (transmit @ ?5 dbm) ? transmit power up to +4 dbm ? receive sensitivity up to ?97 dbm ? sleep current <1 a ? operating range: 10m+ ? dsss data rates up to 250 kbps, gfsk data rate of 1 mbps ? low external component count ? auto transaction sequencer (ats) - no mcu intervention ? framing, length, crc16, and auto ack ? power management unit (pmu) for mcu/sensor ? fast startup and fast channel changes ? separate 16-byte transmit and receive fifos ? autorate? - dynamic data rate reception ? receive signal strength indication (rssi) ? serial peripheral interface (spi ) control while in sleep mode ? 4-mhz spi microcontroller interface ? battery voltage monitoring circuitry ? supports coin-cell operated applications ? operating voltage from 1.8v to 3.6v ? operating temperature from 0 to 70c ? space saving 40-pin qfn 6x6 mm package 2.0 applications ? wireless keyboards and mice ? wireless gamepads ? remote controls ?toys ? voip and wireless headsets ? white goods ? consumer electronics ? home automation ? automatic meter readers ? personal health & entertainment 3.0 applications support see www.cypress.com for deve lopment tools, reference designs, and application notes. 4.0 functional description the CYRF6936 wirelessusb? lp radio is a second gener- ation member of cypress?s wirelessusb radio system-on- chip (soc) family. the CYRF6936 is interoperable with the first generation cywusb69xx devices. the CYRF6936 ic adds a range of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data rate options, and reduced crystal start-up, synthesizer settling and link turn-around times. figure 4-1. CYRF6936 simplified block diagram data interface and sequencer dsss baseband & framer spi synthesizer gfsk demodulator gfsk modulator irq ss sck miso mosi rf p rf n xtal xout block diagram rssi xtal osc power management l/d v reg v bat v dd rf bias rst v io pactl v cc gnd
CYRF6936 document #: 38-16015 rev. *f page 2 of 39 figure 5-1. CYRF6936, 40 qfn ? top vie 5.0 pin descriptions pin # name type default description 13 rf n i/o i differential rf signal to/from antenna 11 rf p i/o i differential rf signal to/from antenna 10 rf bias o o rf i/o 1.8v reference voltage 30 pactl i/o o control signal for external pa, t/r switch, or gpio 1 xtal i i 12-mhz crystal 29 xout i/o o buffered 0.75, 1.5, 3, 6 or 12 mhz clock, pactl , or gpio. tristates in sleep mode (recommend configure as gpio drive low). 25 sck i i spi clock 28 miso i/o z spi data output pin (master in slave out), or gpio (in spi 3-pin mode). tristates when spi 3pin=0 and ss deasserted. 27 mosi i/o i spi data input pin (master out slave in), or sdat 24 ss i i spi enable, active low assertion - enables and frames transfers. 26 irq i/o o interrupt output (configurable active high or low), or gpio 34 rst i i device reset. in ternal 10k-ohm pull-down resistor. active high, typically connect via 0.1- f capacitor to v bat 37 l/d o pmu inductor/diode connection 40 v reg pwr pmu boosted output voltage feedback 35 v dd pwr decoupling pin for 1.8v logic regulator, connect via 0.47- f capacitor to gnd 6, 8, 38 v bat pwr v bat = 1.8v to 3.6v. main supply. 3, 7, 16 v cc pwr v cc = 2.4v to 3.6v. typically connected to v reg 33 v io pwr i/o interface voltage, 1.8?3.6v 19 resv i must be connected to gnd 2, 4, 5, 9, 14, 15, 18, 17, 20, 21, 22, 23, 32, 36, 39, 31 nc nc recommend to connect to gnd 12 gnd gnd ground e-pad gnd gnd ground CYRF6936 40-lead qfn rf bias nc nc v bat v cc v bat xtal v cc nc nc v reg nc nc v bat l/d nc nc v io v dd rst rf n nc nc v cc nc nc resv nc gnd rf p nc ss sck irq / gpio mosi / sdat miso / gpio xout / gpio pactl / gpio nc nc 23 24 25 26 27 28 29 30 22 21 13 14 15 16 17 18 19 20 12 11 10 9 2 8 7 6 1 3 5 4 40 39 32 38 37 36 31 33 35 34 * e-pad bottom side CYRF6936 top view*
CYRF6936 document #: 38-16015 rev. *f page 3 of 39 6.0 functional overview the CYRF6936 ic provides a complete wirelessusb spi to antenna wireless modem. the so c is designed to implement wireless device links operating in the worldwide 2.4-ghz ism frequency band. it is intended for systems compliant with world-wide regulations covered by etsi en 301 489-1 v1.41, etsi en 300 328-1 v1.3.1 (europe), fcc cfr 47 part 15 (usa and industry canada) and telec arib_t66_march, 2003 (japan). the soc contains a 2.4-ghz 1-mbps gfsk radio transceiver, packet data buffering, packet framer, dsss baseband controller, received signal strength indication (rssi), and spi interface for data transfer and device configuration. the radio supports 98 discrete 1-mhz channels (regulations may limit the use of some of t hese channels in certain jurisdic- tions). the baseband performs dsss spreading/despre ading, start of packet (sop), end of packet (eop) detection and crc16 generation and checking. the baseband may also be configured to automatically transmit acknowledge (ack) handshake packets whenever a valid packet is received. when in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates enabling the implementation of mixed-rate systems in which different devices use different data rates. this also enables the implementation of dynamic data rate systems, which use high data ra tes at shorter distances and/or in a low-moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments. in addition, the CYRF6936 ic has a power management unit (pmu) which allows direct connection of the device to any battery voltage in the range 1.8v to 3.6v. the pmu conditions the battery voltage to provide the supply voltages required by the device, and may su pply external devices. data transmission modes the soc supports four different data transmission modes: ? in gfsk mode, data is tran smitted at 1 mbps, without any dsss. ? in 8dr mode, 8 bits are encoded in each derived code symbol transmitted. ? in ddr mode, 2-bits are encoded in each derived code symbol transmitted. (as in the cywusb6934 ddr mode). ? in sdr mode, 1 bit is encoded in each derived code symbol transmitted. (as in the cywusb6934 standard modes.) both 64-chip and 32-chip pseudo-noise (pn) codes are supported. the four data transmission modes apply to the data after the sop. in particular the length, data, and crc16 are all sent in the same mode. in general, lower data rates reduce packet error rate in any given environment. link layer modes the CYRF6936 ic device supports the following data packet framing features: sop ? packets begin with a 2-symbol start of packet (sop) marker. this is required in gfsk and 8dr modes, but is optional in ddr mode and is not supported in sdr mode; if framing is disabled then an sop event is inferred whenever two successive correlati ons are detected. the sop_code_adr code used for t he sop is different from that used for the ?body? of the packet, and if desired may be a different length. sop must be configured to be the same length on both sides of the link. length ? there are two options for detecting the end of a packet. if sop is enabled, then the length field should be enabled. gfsk and 8dr must enable the length field. this is the first 8-bits after the sop sy mbol, and is transmitted at the payload data rate. when the length field is enabled, an end of packet (eop) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the crc16 (when enabled?see below). the alternative to using the length field is to infer an eop condition from a config- urable number of successive non-correlations; this option is not available in gfsk mode and is only recommended to enable when using sdr mode. crc16 ? the device may be configured to append a 16-bit crc16 to each packet. the crc16 uses the usb crc polynomial with the added prog rammability of the seed. if enabled, the receiver will verify the calculated crc16 for the payload data against the received value in the crc16 field. the seed value for the crc16 calculation is configurable, and the crc16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data crc16 will be checked against both the configured and zero crc16 seeds. crc16 detects the following errors: ? any one bit in error ? any two bits in error (no matt er how far apart, which column, and so on) ? any odd number of bits in error (no matter where they are) ? an error burst as wide as the checksum itself figure 6-1 shows an example packet with sop, crc16 and lengths fields enabled, and figure 6-2 shows a standard ack packet. figure 6-1. example packet format p sop 1 sop 2 length crc 16 payload data preamble n x 16us 1st framing symbol* 2nd framing symbol* packet length 1 byte period *note:32 or 64us
CYRF6936 document #: 38-16015 rev. *f page 4 of 39 figure 6-2. example ack packet format packet buffers all data transmission and reception utilizes the 16-byte packet buffers?one for transmission and one for reception. the transmit buffer allows a complete packet of up to 16-bytes of payload data to be loaded in one burst spi transaction, and then transmitted with no further mcu intervention. similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. the CYRF6936 ic supports packets up to 255 bytes, however, actual maximum packet length will depend on accuracy of the clock on each end of the link and the data mode; interrupts are provided to allow an mcu to use the transmit and receive buffers as fifos. when transmitting a packet longer than 16 bytes, the mcu can load 16-bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. similarly, when receiving packets longer than 16 bytes, the mcu must fetch received data from the fifo periodically during packet reception to prevent it from overflowing. auto transaction sequencer (ats) the CYRF6936 ic provides automated support for trans- mission and reception of acknowledged data packets. when transmitting in transact ion mode, the device automati- cally: ? starts the crystal and synthesizer ? enters transmit mode ? transmits the packet in the transmit buffer ? transitions to receive mode and waits for an ack packet ? transitions to the transacti on end state when either an ack packet is received, or a timeout period expires similarly, when receiving in transaction mode, the device automatically: ? waits in receive mode for a valid packet to be received ? transitions to transmit mode, transmits an ack packet ? transitions to the transaction end state (receive mode to await the next packet, etc.) the contents of the packet buffers are not affected by the transmission or reception of ack packets. in each case, the entire packet transaction takes place without any need for mcu firmware action (providing packets of 16 bytes or less are used); to transmit data the mcu simply needs to load the data packet to be transmitted, set the length, and set the tx go bit. similarly, when receiving packets in trans- action mode, firmware simply needs to retrieve the fully received packet in response to an interrupt request indicating reception of a packet. backward compatibility the CYRF6936 ic is fully interoperable with the main modes of the first generation devic es. the 62.5-kbps mode is supported by selecting 32-chip ddr mode. similarly, the 15.675-kbps mode is supported by selecting 64-chip sdr mode. in this way, a suitably configured CYRF6936 ic device may transmit data to and/or receiv e data from a first generation device. disabling the sop, length, and crc16 fields is required for backwa rds compatibility. data rates by combining the pn code lengths and data transmission modes described above, the CYRF6936 ic supports the following data rates: ? 1000-kbps (gfsk) ? 250-kbps (32-chip 8dr) ? 125-kbps (64-chip 8dr) ? 62.5-kbps (32-chip ddr) ? 31.25-kbps (64-chip ddr) ? 15.625-kbps (64-chip sdr) 7.0 functional block overview 2.4-ghz radio the radio transceiver is a dual conversion low if architecture optimized for power and range/robustness. the radio employs channel-matched filters to achieve high performance in the presence of interference. an integrated power amplifier (pa) provides up to +4 dbm transmit power, with an output power control range of 34 db in 7 steps. the supply current of the device is reduced as the rf output power is reduced. p sop 1 sop 2 crc 16 pream ble n x 16us 1st fram ing sym bol* 2nd fram ing sym bol* crc field from received packet. 2 byte periods *note:32 or 64us table 7-1. internal pa output power step table pa setting typical output power (dbm) 7+4 60 5?5 4 ?13 3 ?18 2 ?24 1 ?30 0 ?35
CYRF6936 document #: 38-16015 rev. *f page 5 of 39 frequency synthesizer before transmission or rece ption may commence, it is necessary for the frequency synt hesizer to settle. the settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100- s. the ?fast channels? (<100- s settling time) are every 3 rd channel, starting at 0 up to and including 72 (i.e., 0,3,6,9??.69 & 72). baseband and framer the baseband and framer bloc ks provide the dsss encoding and decoding, sop generation and reception and crc16 generation and checking, as well as eop detection and length field. packet buffers and radio configuration registers packet data and configuration registers are accessed through the spi interface. all config uration registers are directly addressed through the address field in the spi packet (as in the cywusb6934). configuration registers are provided to allow configuration of dsss pn codes, data rate, operating mode, interrupt masks, in terrupt status, etc. spi interface the CYRF6936 ic has a spi interface supporting communi- cations between an application mcu and one or more slave devices (including the CYRF6936). the spi interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. the spi communications interface consists of slave select (ss ), serial clock (sck), and master out- slave in (mosi), master in-sla ve out (miso), or serial data (sdat). the spi communications is as follows: ? command direction (bit 7) = ?1? enables spi write trans- action. a ?0? enables spi read transactions. ? command increment (bit 6) = ?1? enables spi auto address increment. when set, the addres s field automatically incre- ments at the end of each data byte in a burst access, otherwise the same address is accessed. ? six bits of address. ? eight bits of data. the device receives sck from an application mcu on the sck pin. data from the application mcu is shifted in on the mosi pin. data to the application mcu is shifted out on the miso pin. the active-low slave select (ss ) pin must be asserted to initiate an spi transfer. the application mcu can initiate spi data transfers via a multi- byte transaction. the first byte is the command/address byte, and the following bytes are the data bytes as shown in figure 7-1 through figure 7-4 . the spi communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as desired. a burst transaction is terminated by deasserting the slave select (ss = 1). the spi communications interface single read and burst read sequences are shown in figure 7-2 and figure 7-3 , respec- tively. the spi communications interface single write and burst write sequences are shown in figure 7-4 and figure 7-5 , respec- tively. this interface may optionally be operated in a 3-pin mode with the miso and mosi functions combined in a single bidirec- tional data pin (sdat). when using 3-pin mode, user firmware should ensure that the mosi pin on the mcu is in a high- impedance state except when mosi is actively transmitting data. the device registers may be written to or read from 1 byte at a time, or several sequential register locations may be written/read in a single spi transaction using incrementing burst mode. in addition to single byte configuration registers, the device includes re gister files; register files are fifos written to and read from using non-incrementing burst spi transactions. the irq pin function may optionally be multiplexed onto the mosi pin; when this option is e nabled the irq function is not available while the ss pin is low. when using this configu- ration, user firmware should ensure that the mosi pin on the mcu is in a high impedance state whenever the ss pin is high. the spi interface is not dependent on the internal 12-mhz clock, and registers may theref ore be read from or written to while the device is in sleep mode, and the 12-mhz oscillator disabled. the spi interface and the irq and rst pins have a separate voltage reference pin (v io ), enabling the device to interface directly to mcus operating at voltages below the CYRF6936 ic supply voltage. table 7-2. typical range observed table environment typical range (meters) outdoor 30 office 20 home 15 note: range observed with cy4636 wirelessusb lp kbm v1.0 (keyboard)
CYRF6936 document #: 38-16015 rev. *f page 6 of 39 figure 7-1. spi transaction format figure 7-2. spi si ngle read sequence figure 7-3. spi incrementing burst read sequence figure 7-4. spi single write sequence figure 7-5. spi incrementing burst write sequence byte 1 byte 1+n bit # 7 6 [5:0] [7:0] bit name dir inc address data dir 0 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data to mcu dir 0 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data to mcu 1 cmd addr data to mcu 1+n sck mosi ss miso dir 1 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data from mcu dir 1 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data from mcu 1 d7 d6 d5 d4 d3 d2 d1 d0 data from mcu 1+n
CYRF6936 document #: 38-16015 rev. *f page 7 of 39 interrupts the device provides an interrupt (irq) output, which is config- urable to indicate the occurrence of various different events. the irq pin may be programmed to be either active high or active low, and be either a cmos or open drain output. a full description of all the available interrupts can be found in section 9.0 . the CYRF6936 ic features three sets of interrupts: transmit, receive, and system interrupts. these interrupts all share a single pin (irq), but can be independently enabled/disabled. the contents of the enable registers are preserved when switching between transmit and receive modes. if more than one interrupt is enabled at any time, it is necessary to read th e relevant status register to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, th e status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status re gister. it is therefore possible to use the devices without making use of the irq pin by polling the status register(s) to wait for an event, rather than using the irq pin. clocks a 12-mhz crystal (30-ppm or better) is directly connected between xtal and gnd without the need for external capac- itors. a digital clock out function is provided, with selectable output frequencies of 0.75-, 1.5- , 3-, 6-, or 12-mhz. this output may be used to clock an external microcontroller (mcu) or asic. this output is enabled by default, but may be disabled. below are the requirements for the crystal to be directly connected to xtal pin and gnd: ? nominal frequency: 12 mhz ? operating mode: fundamental mode ? resonance mode: parallel resonant ? frequency initial stability: 30 ppm ? series resistance: < 60 ohms ? load capacitance: 10 pf ? drive level: 10 w?100 w power management the operating voltage of the devic e is 1.8v to 3.6v dc, which is applied to the v bat pin. the device can be shutdown to a fully static sleep mode by writing to the frc end = 1 and end state = 000 bits in the xact_cfg_adr register over the spi interface. the device wil l enter sleep mode within 35- s after the last sck positive edge at the end of this spi trans- action. alternatively, the device may be configured to automat- ically enter sleep mode after completing packet transmission or reception. when in sleep mode, the on-chip oscillator is stopped, but the spi interface remains functional. the device will wake from sleep mode automatically when the device is commanded to enter transmit or receive mode. when resuming from sleep mode, there is a short delay while the oscillator restarts. the device may be configured to assert the irq pin when the oscillator has stabilized. the output voltage (v reg ) of the power management unit (pmu) is configurable to se veral minimum values between 2.4v and 2.7v. v reg may be used to provide up to 15 ma (average load) to external devices. it is possible to disable the pmu, and to provide an exte rnally regulated dc supply voltage to the device?s main supply in the range 2.4v to 3.6v. the pmu also provides a regulated 1.8v supply to the logic. the pmu has been designed to provide high boost efficiency (74?85% depending on input voltage, output voltage and load) when using a schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. however, reasonable efficiencies (69-82% depending on input voltage, output voltage and load) may be achieved when using low cost components such as sot23 diodes and 0805 inductors. the pmu also provides a conf igurable low battery detection function which may be read over the spi interface. one of seven thresholds between 1.8v and 2.7v may be selected. the interrupt pin may be configured to assert when the voltage on the v bat pin falls below the configured threshold. lv irq is not a latched event. battery monitoring is disabled when the device is in sleep mode. low noise amplifier (lna) and received signal strength indication (rssi) the gain of the receiver may be controlled directly by clearing the agc en bit and writing to the low noise amplifier (lna) bit of the rx_cfg_adr register. when the lna bit is cleared, the receiver gain is reduced by approximately 20 db, allowing accurate reception of very strong re ceived signals (for example when operating a receiver very close to the trans- mitter). approximately 30 db of receiver attenuation can be added by setting the attenuation (att) bit; this allows data reception to be limited to devices at very short ranges. disabling agc and enabling lna is recommended unless receiving from a device using external pa. when the device is in receive mode the rssi_adr register returns the relative signal strength of the on-channel signal power. when receiving, the device will automatically measure and store the relative strength of th e signal being received as a 5- bit value. an rssi reading is taken automatically when the sop is detected. in addition, a new rssi reading is taken every time the previous reading is read from the rssi_adr register, allowing the background rf energy level on any given channel to be easily measured when rssi is read when no signal is being received. a new reading can occur as fast as once every 12 s.
CYRF6936 document #: 38-16015 rev. *f page 8 of 39 8.0 application examples figure 8-1. recommended circuit for systems where v bat may fall below 2.4v. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a pcb: pdc-9265 keyboard interface power supply sdata issp sclk "-" xres "+" bind serial debug header layout j3 and j2.1 in a 0.100" spacing configuration e-pad must be soldered to ground. radio decoupling caps rf vco and vco buffer filter the power supply decoupling shown for vbat0 is a recommended cost effective configuration: c6=no load r2= 1ohm c7=10uf ceramic. for this configuration, it is required that c18 be installed. an alternate decoupling configuration is the following: c6=47uf ceramic r2=0ohm c7=.047uf. for this configuration, it is not required to load c18. for reference design part numbers, please refer to the bill of materials file 121-26504.xls. a 2-pin jumper installed from j3.1 to j2.1 enables the radio to power the processor. jumper removal is required when programming u2 to disconnect the radio from the miniprog 5v source. r1 is a zero ohm resistor that should be installed for production units only, following programming. ref-13288 *c lp keyboard c 11 thursday, april 13, 2006 title size document number rev date: sheet of cypress semiconductor ? 2005 miso mosi p1_1 sck p1_0 miso nss irq mosi clkout rst sck col16 col10 col17 col9 col13 p1_0 col15 col18 col12 col11 col14 nss p1_1 col5 col3 col2 col8 col1 col6 col7 col4 row5 row4 row6 row2 row7 row1 row8 row3 col7 col11 row4 row2 col1 col3 col8 col10 col14 row8 row3 col2 col6 row6 row5 col18 row1 col13 col16 col9 row7 col5 col4 col12 col15 col17 irq sw1 pactl evcc vcc vbat vbat vcc vbat vbat vcc evcc sot23 d1 bat400d 2 1 ind0402 l2 1.8 nh u2 cy7c60123-pvxc 30 16 17 18 29 28 26 25 19 23 12 5 7 24 10 20 43 21 42 22 6 34 35 36 37 38 39 40 41 13 14 15 31 32 33 27 44 11 9 8 4 1 2 3 46 47 48 45 p1_4 / sclk p0_7 p0_6 / tio1 p0_5 / tio0 p1_3 / ssel p1_2 p1_1 p1_0 p0_4 / int2 p0_0 / clkin p2_3 vdd1 p4_0 vss1 p2_5 p0_3 / int1 p4_3 p0_2 / int0 p4_2 p0_1 / clkout p4_1 p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 p2_2 p2_1 p2_0 p1_5 / smosi p1_6 / smiso p1_7 vdd2 vss2 p2_4 p2_6 p2_7 nc4 nc1 nc2 nc3 nc6 nc7 nc8 nc5 s1 sw pushbutton 1a 2a 1b 2b ind0603 l1 22 nh 0603 r1 no load j1 kb 26 pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 tv4 0402 c8 1 ufd 6.3v bh1 batt con 2xaa 1 2 3 pos neg1 neg2 0402 c11 0.047 ufd 0805 r2 1 1% l3 10 uh tv5 0805 c12 10 ufd 6.3v 0805 c7 10 ufd 6.3v 0402 c20 0.01 ufd 0402 c16 0.047 ufd j3 1 pin hdr 1 tv8 j2 5 pin hdr 1 2 3 4 5 0402 c17 0.1 ufd j4 3 pin hdr 1 2 3 0402 r3 47 tp2 tp1 0402 c13 0.047 ufd u1 CYRF6936 36 4 8 19 16 20 2 25 27 26 29 34 28 3 7 5 13 6 37 1 24 39 40 41 35 9 14 10 11 12 15 17 18 21 30 22 33 23 31 32 38 nc15 nc2 vbat2 resv vcc3 nc9 nc1 sck mosi irq xout rst miso vcc1 vcc2 nc3 rfn vbat1 l/d xtal ss nc16 vreg e-pad vdd nc4 nc5 rfbias rfp gnd1 nc6 nc7 nc8 nc10 pactl nc11 vio nc12 nc13 nc14 vbat0 0402 c3 2.0 pfd 0402 c1 15 pfd + e c18 100 ufd 10v 0402 c5 0.47 ufd 0402 c15 0.047 ufd tv7 tv6 ant1 wiggle 63 1 2 0402 c4 1.5 pfd y1 12 mhz crystal tv2 1210 c6 no load 0402 c10 0.047 ufd tv1 tv3 0402 c19 0.01 ufd 0402 c9 0.047 ufd
CYRF6936 document #: 38-16015 rev. *f page 9 of 39 figure 8-2. recommended bill of materials for systems where v bat may fall below 2.4v. bill of materials title lp rdk keyboard pca # 121-265 04 revision ** sch # ref-13288 revision *c date 3/17/2005 item qty cy part number reference description manufacturer mfr part number 1 1 na ant1 2.5ghz h-stub wiggle antenna for 63mil pcb na na 2 1 200-????? bh1 battery clips 2aa cell chicony kb chicony kbr0108 31 730-10012 c1 cap 15pf 50v ceramic npo 0402 panasonic ecj-0ec1h150j 4 1 730-11955 c3 cap 2.0 pf 50v ceramic npo 0402 kamet c0402c209c5gactu 51 730-11398 c4 cap 1.5pf 50v ceramic npo 0402 smd panasonic ecj-0ec1h1r5c 6 1 730-13322 c5 cap 0.47 uf 50v ceramic x5r 0402 murata grm155r60j474ke19d 7 2 730-13037 c12, c7 cap ceramic 10uf 6.3v x5r 0805 kamet c0805c106k9pactu 8 1 730-13400 c8 cap 1 uf 6.3v ceramic x5r 0402 panasonic ecj-0eb0j105m 9 6 730-13404 c9,c10,c11,c13,c15,c16 cap 0.047 uf 16v ceramic x5r 0402 avx 0402yd473kat2a 10 1 730-11952 c17 cap 0.1 uf 50v ceramic x5r 0402 kamet c0402c104k8pactu 11 1 710-13201 c18 cap 100uf 10v elect fc panasonic - ecg eeu-fc1a101s 12 2 730-10794 c20,c19 cap 10000pf 16v ceramic 0402 smd panasonic - ecg ecj-0eb1c103k 13 1 800-13317 d1 diode schottky 0.5a 40v sot23 diodes inc bat400d-7-f 14 1 na j1 pcb copper pads none 15 1 420-11496 j2 conn hdr brkway 5pos str au pcb amp division of tyco 103185-5 16 1 420-11964 j3 header 1 pos 0.230 ht modii .100cl amp/tyco 103185-1 17 1 800-13401 l1 inductor 22nh 2% fixed 0603 smd panasonic - ecg elj-re22ngf2 18 1 800-11651 l2 inductor 1.8nh +-.3nh fixed 0402 smd panasonic - ecg elj-rf1n8df 19 1 800-10594 l3 coil 10uh 1100ma choke 0805 newark 30k5421 20 1 630-11356 r2 res 1.00 ohm 1/8w 1% 0805 smd yageo 9c08052a1r00fkhft 21 1 610-13402 r3 res 47 ohm 1/16w 5% 0402 smd panasonic - ecg erj-2gej470x 22 1 800-13368 s1 lt switch 6mm 100gf h=7mm th panasonic - ecg evq-pac07k 23 1 CYRF6936-40lfc u1 ic, lp 2.4 ghz radio soc qfn-40 cypress semiconductor CYRF6936 rev a5 24 1 cy7c60123-pvxc u2 ic wireless encore ii controller ssop48 cypress semiconductor cy7c60123-pvxc 25 1 800-13259 y1 crystal 12.00mhz hc49 smd ecera gf-1200008 26 1 pdc-9265-*b pcb printed circuit board cypress semiconductor pdc-9265-*b 27 1 label1 serial number xxxxxx 28 1 label2 pca # 121-26504 ** no load components - do not instal l 29 1 730-13403 c6 cap 47uf 6.3v ceramic x5r 1210 panasonic ecj-4yb0j476m 30 1 630-10242 r2 res chip 0.0 ohm 1/10w 5% 0805 smd phycomp usa inc 9c08052a0r00jlhft 31 1 730-13404 c7 cap 0.047 uf 50v ceramic x5r 0402 avx 0402yd473kat2a 32 1 420-10921 j4 header 3pos fric strght mta 100 amp/tyco 644456-3 33 1 620-10519 r1 res zero ohm 1/16w 5% 0603 smd panasonic - ecg erj-3gey0r00v cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 page 1 of 1
CYRF6936 document #: 38-16015 rev. *f page 10 of 39 figure 8-3. recommended circuit for systems where v bat is 2.4v to 3.6v (pmu disabled). 5 5 4 4 3 3 2 2 1 1 d d c c b b a a pcb: pdc - 9263 "bind" power supply "connect/activity" e-pad must be soldered to ground. ref-13287 *a lp dongle ii c 11 wednesday, april 12, 2006 title size document number rev date: sheet of cypress semiconductor ? 2005 dp sw1 vbus dm nss sck miso mosi irq sw1 nled1 nled2 rst nled1 nled2 irq rst mosi sck nss miso 5v 5v vcc vcc 5v vcc vcc 5v u1 CYRF6936 36 4 8 19 16 20 2 25 27 26 29 34 28 3 7 5 13 6 37 1 24 39 40 41 35 9 14 10 11 12 15 17 18 21 30 22 33 23 31 32 38 nc15 nc2 vbat2 resv vcc3 nc9 nc1 sck mosi irq xout rst miso vcc1 vcc2 nc3 rfn vbat1 l/d xtal ss nc16 vreg e-pad vdd nc4 nc5 rfbias rfp gnd1 nc6 nc7 nc8 nc10 pactl nc11 vio nc12 nc13 nc14 vbat0 ind0402 l2 1.8 nh 0402 c9 0.047 ufd j1 usb a smt plug 1 2 3 4 5 6 vbus dm dp gnd s1 s2 0402 c1 15 pfd 0402 r1 zero d1 led green red 1 2 3 4 gr rd c c 0402 r2 620 ant1 wiggle 32 1 2 0402 c12 1500 pfd 0402 c10 0.047 ufd 0402 c3 2.0 pfd 0402 c7 0.047 ufd 0805 c13 4.7 ufd 0805 c14 2.2 ufd s1 sw ra push 1a 1b 2a 2b 0402 c6 0.047 ufd tv1 tv-20r y1 12 mhz crystal 0402 c11 0.047 ufd 0402 c4 1.5 pfd 0402 c8 0.047 ufd u2 cy7c63803-sxc 7 6 5 4 3 2 1 16 15 8 11 12 10 9 13 14 p0_0 p0_1 p0_2/int0 p0_3/int1 p0_4/int2 p0_5/tio0 p0_6/tio1 miso/p1_6 mosi/p1_5 vss vcc vreg dm/p1_1 dp/p1_0 ssel/p1_3 sclk/p1_4 0402 c5 0.47 ufd ind0603 l1 22 nh
CYRF6936 document #: 38-16015 rev. *f page 11 of 39 figure 8-4. recommended bill of materials for systems where v bat is 2.4v to 3.6v (pmu disabled). bill of materials title lp rdk dongle ii pca # 121-263 05 revision ** sch # ref-13287 revision *a dat e 3/24/2005 item qt y cy part numbe r reference description manufacture r mfr part number 1 1 na ant1 2.5ghz h-stub wiggle antenna for 32mil pcb na na 21 730-10012 c1 cap 15pf 50v ceramic npo 0402 panasonic ecj-0ec1h150j 3 1 730-11955 c3 cap 2.0 pf 50v ceramic npo 0402 kemet c0402c209c5gactu 41 730-11398 c4 cap 1.5pf 50v ceramic npo 0402 smd panasonic ecj-0ec1h1r5c 5 1 730-13322 c5 cap 0.47 uf 50v ceramic x5r 0402 murata grm155r60j474ke19d 66 730-13404 c6,c7,c8,c9,c10,c11 cap 0.047 uf 50v ceramic x5r 0402 avx 0402yd473kat2a 7 1 730-11953 c12 cap 1500pf 50v ceramic x7r 0402 kemet c0402c152k5ractu 8 1 730-13400 c13 cap ceramic 4.7uf 6.3v xr5 0805 kemet c0805c475k9pactu 9 1 730-12003 c14 cap cer 2.2uf 10v 10% x7r 0805 murata electronics north america grm21br71a225ka01l 10 1 800-13333 d1 led green/red bicolor 1210 smd liteon ltst-c155kgjrkt 11 1 420-13046 j1 conn usb plug type a pcb smt acon uar72-4n5j10 12 1 800-13401 l1 inductor 22nh 2% fixed 0603 smd panasonic - ecg elj-re22ngf2 13 1 800-11651 l2 inductor 1.8nh +-.3nh fixed 0402 smd panasonic - ecg elj-rf1n8df 14 1 610-10343 r1 res zero ohm 1/16w 0402 smd panasonic - ecg erj-2ge0r00x 15 1 610-13472 r2 res chip 620 ohm 1/16w 5% 0402 smd panasonic - ecg erj-2gej621x 16 1 200-13471 s1 switch lt 3.5mmx2.9mm 160gf smd panasonic - ecg evq-p7j01k 17 1 CYRF6936-40lfc u1 ic, lp 2.4 ghz radio soc qfn-40 cypress semiconductor CYRF6936 rev a5 18 1 cy7c63803-sxc u2 ic low-speed usb encore ii controller soic16 cypress semiconductor cy7c63803-sxc 19 1 800-13259 y1 crystal 12.00mhz hc49 smd ecera gf-1200008 20 1 pdc-9263-*b pcb printed circuit board cypress semiconductor pdc-9263-*b 21 1 label1 serial number xxxxxx 22 1 label2 pca # 121-26305 ** cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 page 1 of 1
CYRF6936 document #: 38-16015 rev. *f page 12 of 39 9.0 register descriptions all registers are read and writable, except where noted. registers may be written to or read from either individually or in seq uential groups. table 9-1. register map summary address mnemonic b7 b6 b5 b4 b3 b2 b1 b0 default [1] access [1] 0x00 channel_adr not used channel -1001000 -bbbbbbb 0x01 tx_length_adr tx length 00000000 bbbbbbbb 0x02 tx_ctrl_adr tx go tx clr txb15 irqen txb8 irqen txb0 irqen txberr irqen txc irqen txe irqen 00000011 bbbbbbbb 0x03 tx_cfg_adr not used not used data code length data mode pa setting --000101 --bbbbbb 0x04 tx_irq_status_adr os irq lv irq txb15 irq txb8 irq txb0 irq txberr irq txc irq txe irq -------- rrrrrrrr 0x05 rx_ctrl_adr rx go rsvd rxb16 irqen rxb8 irqen rxb1 irqen rxberr irqen rxc irqen rxe irqen 00000111 bbbbbbbb 0x06 rx_cfg_adr agc en lna att hilo fast turn en not used rxow en vld en 10010-10 bbbbb-bb 0x07 rx_irq_status_adr rxow irq sopdet irq rxb16 irq rxb8 irq rxb1 irq rxberr irq rxc irq rxe irq -------- brrrrrrr 0x08 rx_status_adr rx ack pkt err eop err crc0 bad crc rx code rx data mode -------- rrrrrrrr 0x09 rx_count_adr rx count 00000000 rrrrrrrr 0x0a rx_length_adr rx length 00000000 rrrrrrrr 0x0b pwr_ctrl_adr pmu en lvirq en pmu sen not used lvi th pmu outv 10100000 bbb-bbbb 0x0c xtal_ctrl_adr xout fn xsirq en no t used not used freq 000--100 bbb--bbb 0x0d io_cfg_adr irq od irq pol miso od xout od pact l od pactl gpio spi 3pin irq gpio 00000000 bbbbbbbb 0x0e gpio_ctrl_adr xout op miso op pactl op irq op xout ip miso ip pactl ip irq ip 0000---- bbbbrrrr 0x0f xact_cfg_adr ack en not used frc end end state ack to 1-000000 b-bbbbbb 0x10 framing_cfg_adr sop en sop len len en sop th 10100101 bbbbbbbb 0x11 data32_thold_adr not used not used not used not used th32 ----0100 ----bbbb 0x12 data64_thold_adr not used not used not used th64 ---01010 ---bbbbb 0x13 rssi_adr sop not used lna rssi 0-100000 r-rrrrrr 0x14 eop_ctrl_adr hen hint eop 10100100 bbbbbbbb 0x15 crc_seed_lsb_adr crc seed lsb 00000000 bbbbbbbb 0x16 crc_seed_msb_adr crc seed msb 00000000 bbbbbbbb 0x17 tx_crc_lsb_adr crc lsb -------- rrrrrrrr 0x18 tx_crc_msb_adr crc msb -------- rrrrrrrr 0x19 rx_crc_lsb_adr crc lsb 11111111 rrrrrrrr 0x1a rx_crc_msb_adr crc msb 11111111 rrrrrrrr 0x1b tx_offset_lsb_adr strim lsb 00000000 bbbbbbbb 0x1c tx_offset_msb_adr not used not used not used not used strim msb ----0000 ----bbbb 0x1d mode_override_adr rsvd rsvd frc sen frc awake not used not used rst 00000--0 wwwww--w 0x1e rx_override_adr ack rx rxtx dly man rxack frc rxdr dis crc0 dis rxcrc ace not used 0000000- bbbbbbb- 0x1f tx_override_adr ack tx frc pre rsvd man txack ovrd ack dis txcrc rsvd tx inv 00000000 bbbbbbbb 0x26 xtal_cfg_adr rsvd rsvd rsvd rsvd start dly rsvd rsvd rsvd 00000000 wwwwwww w 0x27 clk_override_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwww w 0x28 clk_en_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwww w 0x29 rx_abort_adr rsvd rsvd abort en rsvd rsvd rsvd rsvd rsvd 00000000 wwwwwww w 0x32 auto_cal_time_adr auto_cal_time 00000011 wwwwwww w 0x35 auto_cal_offset_adr auto_cal_offset 00000000 wwwwwww w 0x39 analog_ctrl_adr rsvd rsvd rsvd rsvd rsvd rsvd rx inv all slow 00000000 wwwwwww w register files 0x20 tx_buffer_adr tx buffer file -------- wwwwwww w 0x21 rx_buffer_adr rx buffer file -------- rrrrrrrr 0x22 sop_code_adr sop code file note 2 bbbbbbbb 0x23 data_code_adr data code file note 3 bbbbbbbb 0x24 preamble_adr preamble file note 4 bbbbbbbb 0x25 mfg_id_adr mfg id file na rrrrrrrr notes 1. b = read/write, r = read only, w = write only, - = not used, default value is undefined. 2. sop_code_adr default = 0x17ff9e213690c782. 3. data_code_adr default = 0x02f9939702fa5ce3012bf1db0132be6f. 4. preamble_adr default = 0x333302.
CYRF6936 document #: 38-16015 rev. *f page 13 of 39 mnemonic channel_adr address 0x00 bit 7 6 5 4 3 2 1 0 default - 1 0 0 1 0 0 0 read/write - r/w r/w r/w r/w r/w r/w r/w function not used channel bit 7 not used. bits 6:0 this field selects the channel. 0x00 sets 2400 mhz; 0x62 sets 2498 mhz. values above 0x62 are not valid. the default ch annel is a fast channel above the frequency typically used in non-overlappi ng wifi systems. any write to th is register will impact th e time it takes the sy nthesizer to settle. fast (100- s) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96 medium (180 ? s) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94 slow (270- s) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97 usable channels subjec t to regulation. mnemonic tx_length_adr address 0x01 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function tx length bits 7:0 this register sets the length of the packet to be transmi tted. a length of zero is valid, and will transmit a packet wi th sop, length and crc16 fields (if enabled), but no data field. packet lengths of more than 16 bytes will require that some data bytes be wri t- ten after transmission of the packet has begun. typically, length is updated prior to setting tx go. the maximum packet length for all packets is 40 bytes except for framed 64-ch ip ddr where the maximum packet length is 16 bytes. maximum packet length is limited by the delta between t he transmitter and receiver crys tals of 60-ppm or better. mnemonic tx_ctrl_adr address 0x02 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w function tx go tx clr txb15 irqen txb8 irqen txb0 irqen txberr irqen txc irqen txe irqen bit 7 start transmission. setting this bit triggers the transmission of a packet. writi ng a 0 to this flag has no effect. this b it is cleared automatically at the end of packet transmi ssion. the transmit buffer may be loaded either before or after setting this bit. if data is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth), the length of the sop code, the length of preamble, and the packet data rate. for example, if starting from idle mode on a fast channel in 8dr mode with 32 chip sop codes the time available is 100 s (synth start) + 32 s (preamble) + 64 s (sop length) + 32 s (length byte) = 228 s. if there are no bytes in the tx buffer at the end of transmission of the length field, a txberr irq will occur and transmission will abort. bit 6 clear tx buffer. writing a 1 to this register clears the transmit buffer. writing a 0 to this bit has no effect. the previ ous packet (16 or fewer bytes) may be retransmitted by setting tx go and not setting this bit. if a new transmit packet is to be loaded before/after the tx go bit has been set, then this bit should be set before loading a new transmit packet to the buffer. bit 5 buffer not full interrupt enable. see tx_irq_status_adr for description. bit 4 buffer half empty interrupt enable . see tx_irq_status_adr for description. bit 3 buffer empty interrupt enable. see tx_irq_status_adr for description. bit 2 buffer error interrupt enable. s ee tx_irq_status_adr for description. bit 1 transmission complete interrupt enable. txc irqen and t xe irqen must be set together. see tx_irq_status_adr for description. bit 0 transmit error interrupt enable. txc irqen and txe irqe n must be set together. see tx_irq_status_adr for descrip- tion.
CYRF6936 document #: 38-16015 rev. *f page 14 of 39 mnemonic tx_cfg_adr address 0x03 bit 7 6 5 4 3 2 1 0 default - - 0 0 0 1 0 1 read/write - - r/w r/w r/w r/w r/w r/w function not used not used data code length data mode pa setting bit 5 data code length. this bit selects the length of the data _code_adr code for the data portion of the packet. this bit is ignored when the data mode is set to gfsk. 1 = 64 chip codes. 0 = 32 chip codes. bits 4:3 data mode. this field sets the data transmission mode. 00 = 1-mbps gfsk. 01 = 8dr mode. 10 = ddr mode. 11 = sdr mode. it is recommended that firmware sets the all slow bit in register analog_ctrl_adr when using gfsk data rate mode. bits 2:0 pa setting. this field sets the transmit signal strength. 0 = ?30 dbm, 1 = ?25 dbm, 2 = ?20 dbm, 3 = ?15 dbm, 4 = ?10 db m, 5 = ?5 dbm, 6 = 0 dbm, 7 = +4 dbm. mnemonic tx_irq_status_adr address 0x04 bit 7 6 5 4 3 2 1 0 default - - - - - - - - read/write r r r r r r r r function os irq lv irq txb15 irq txb8 irq txb0 irq txberr irq txc irq txe irq the state of all irq status bits is vali d regardless of whether or not the irq is enabled. the irq output of the device is in i ts active state whenever one or more bits in this register is set and the corr esponding irq enable bit is also set. status bits are non-atomic (different flags may change value at different times in response to a single event). bit 7 oscillator stable irq status. this bit is set when the internal cr ystal oscillator has settled (synthesizer sequence start s). bit 6 low voltage interrupt status. this bit is set when the voltage on v bat is below the lvi threshold (see pwr_ctl_adr). this interrupt is automatically di sabled whenever the pmu is disabled. when enabled, this bit reflects the voltage on v bat . bit 5 buffer not full interrupt status. this bit is set wheneve r there are 15 or fewer bytes remaining in the transmit buffer. bit 4 buffer half empty interrupt status. this bit is set whenev er there are 8 or fewer bytes remaining in the transmit buffer. bit 3 buffer empty interrupt status. this bit is se t at any time that the transmit buffer is empty. bit 2 buffer error interrupt status. this irq is triggered by ei ther of two events: (1) when the transmit buffer (tx_buffer_adr) is empty and the number of bytes remaining to be transmitted is great er than zero. (2) when a byte is written to the transmit buff er and the buffer is already full. this irq is cleared by setting bit tx clr in tx_ctrl_adr. bit 1 transmission complete interrupt status. this irq is tri ggered when transmission is comp lete. if transaction mode is not enabled then this interrupt is triggered immediately after transmi ssion of the last bit of the crc16. if transaction mode is enabled, this interrupt is triggered at the end of a transacti on. reading this register clears this bit. txc irq and txe irq fl ags may change value at different times in response to a single ev ent. if transaction mode is enabled and the first read of this re gis- ter returns txc irq=1 and txe irq=0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of txe. there can be a case when this bit is not triggered when ack en = 1 and there is an error in transmission. if the first read of th is register returns txc irq = 1 and txe irq = 1 then the firmware must not execut e a second read to this register for a gi ven transaction. if an ack is received rxc irq and rxe irq may be asserted instead of txc irq and txe irq. bit 0 transmit error interrupt status. this irq is triggered w hen there is an error in transmission. this interrupt is only appl icable to transaction mode. it is triggered whenever no valid ack packet is received within the ack timeout period. reading this register clears this bit. see txc irq, above.
CYRF6936 document #: 38-16015 rev. *f page 15 of 39 mnemonic rx_ctrl_adr address 0x05 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w function rx go rsvd rxb16 irqen rxb8 irqen rxb1 irqen rxberr irqen rxc irqen rxe irqen bit 7 start receive. setting this bit caus es the device to transition to receive mode. if necessary, the crystal oscillator and synthesizer will start automatically after th is bit is set. firmware must nev er clear this bit. this bit must not be set again until after it self clears. the recommended method to exit receive mode when an error has occurred is to force end state and then dummy read all rx_count_adr bytes from rx_buffer_adr or poll rssi_adr.sop (bit 7) until set. see xact_cfg_adr and rx_abort_adr for description. bit 6 reserved. must be zero. bit 5 buffer full interrupt enable. s ee rx_irq_status_adr for description. bit 4 buffer half empty interrupt enable. see rx_irq_status_adr for description. bit 3 buffer not empty interrupt enable. rxb1 irqen must not be set when rxb8 irqen is set and vice versa. see rx_irq_status_adr for description. bit 2 buffer error interrupt enable. see rx_irq_status_adr for description. bit 1 packet reception complete interrupt e nable. see rx_irq_status_adr for description. bit 0 receive error interrupt enable. see rx_irq_status_adr for description.
CYRF6936 document #: 38-16015 rev. *f page 16 of 39 mnemonic rx_cfg_adr address 0x06 bit 7 6 5 4 3 2 1 0 default 1 0 0 1 0 - 1 0 read/write r/w r/w r/w r/w r/w - r/w r/w function agc en lna att hilo fast turn en not used rxow en vld en status bits are non-atomic (different flags may change va lue at different times in response to a single event). bit 7 automatic gain control (agc) enable. when this bit is se t, agc is enabled, and the lna is controlled by the agc circuit. when this bit is cleared the lna is cont rolled manually using the lna bit. typical app lications will clear this bit during init ializa- tion. it is recommended that this bit be cleared and bit 6 (lna) be set unless the device will be used in a system where it may receive data from a device using an exter nal pa to transmit signals at >+4 dbm. bit 6 low noise amplifier (lna) manual control. when agc en (bit 7) is cleared, this bit controls the state of the receiver lna; when agc en is set, this bit has no effec t. setting this bit enables the lna; clearing this bit disables the lna. device curren t in receive mode is slightly lower when the lna is disabled. typical ap plications will set this bit during initialization. bit 5 receive attenuator enable. setting th is bit enables the receiver attenuator. the receiver attenuator may be used to de-sen si- tize the receiver so that only very strong signals may be rece ived. this bit should only be se t when the agc en is disabled and the lna is manually disabled. bit 4 hilo. when fast turn en is set, this bit is used to se lect whether the device will use the high frequency for the channel selected, or the low frequency. 1 = hi; 0 = lo. when fast turn en is not enabled this also c ontrols the highlow bit to the receiver and should be left at the default value of 1 for high side receive injection. typical applic ations will clear this bit during initialization. bit 3 fast turn mode enable. when this bit is set, the hilo bit determines whether the device receives data transmitted 1mhz above the rx synthesizer frequency or 1 mhz below the receiver synthesiz er frequency. use of this mode allows for very fast turn-around, because the same synthesizer frequency may be used fo r both transmit and receive, t hus eliminating the synthe- sizer resettling period between transmit and receive. note that w hen this bit is set, and the hilo bit is cleared, received dat a bits are automatically inverted to compensate for the inversi on of data received on the ?image? frequency. typical applications will set this bit during initialization. bit 1 overwrite enable. when this bit is set, if an sop is detec ted while the receive buffer is not empty, then the existing con tents of receive buffer are lost, and the new packet is loaded into the rece ive buffer. when this bit is se t, the rxow irq is enabled. i f this bit is cleared, then the receive buffer may not be over-w ritten by a new packet, and whenever the receive buffer is not empty sop conditions are ignored, and it is not possible to rece ive data until the previously received packet has been com- pletely read from the receive buffer. bit 0 valid flag enable. when this bit is set, the receive buffer can store up to 8 by tes of data interleaved with valids (data0 , valids0, data1, valids1,...). typically, this bit is set only when in teroperability with first generat ion devices is desired. see rx_buffer_adr for more detail.
CYRF6936 document #: 38-16015 rev. *f page 17 of 39 mnemonic rx_irq_status_adr address 0x07 bit 7 6 5 4 3 2 1 0 default - - - - - - - - read/write r/w r r r r r r r function rxow irq sopdet irq rxb16 irq rxb8 irq rxb1 irq rxberr irq rxc irq rxe irq the state of all irq status bits is valid regardless of whether or not the irq is enabled. the irq output of the device is in i ts active state whenever one or more bits in this register is set and the corr esponding irq enable bit is also set. status bits are non-atomic (different flags may change value at different times in response to a single event ). in particular, standard error handling is only effective if the premature termination of a transmission due to an exception does not leave the device in an inconsistent state. bit 7 receive overwrite interrupt status. th is irq is triggered when the receive buffer is over-written by a packet being receiv ed before the previous packet has been read from the buffer. this bit is cleared by writing any val ue to this register. this condi tion is only possible when the rxow en bit in rx_cfg_adr is set. this bit must be writt en ?1? by firmware before the new packet may be read from the receive buffer. bit 6 start of packet detect. this bit is set whenever the start of packet symbol is detected. bit 5 receive buffer full interrupt status. this bit is set whenever the receive buffer is full, and cleared otherwise. bit 4 receive buffer half full interrupt status. this bit is se t whenever there are 8 or more bytes remaining in the receive buf fer. firmware must read exactly eight bytes when reading rxb8 irq. bit 3 receive buffer not empty interrupt stat us. this bit is set at any time that there are 1 or more bytes in the receive buffe r., and cleared when the receive buffer is empty. it is possible, in rare cases, that the last byte of a packet may remain in the buffe r even though the rxb1 irq flag has cleared. this can only happen on th e last byte of a packet and only if the packet data is being read out of the buffer while the packet is still being rece ived. the flag is trustworthy under all other conditions, and for all bytes prior to the last. when using rxb1 irq and unloading the pa cket data during reception, the user should be sure to check the rx_count_adr value after the rxc irq/rxe irq is set and unload the last remaining bytes if the number of bytes unloaded is less than the reported count, eventhough the rxb1 irq is not set. bit 2 receive buffer error interrupt status . this irq is triggered in one of two wa ys: (1) when the receive buffer is empty and there is an attempt to read data. (2) when the receive buffer is full and more data is received. this flag is cleared when rx go is s et and a sop is received. bit 1 packet receive complete interrupt status. this irq is tr iggered when a packet has been re ceived. if transaction mode is enabled, then this bit is not set until after transmission of the ack. if transaction mode is not enabled then this bit is set as soon as a valid packet is received. this bit is cleared when this register is read. rxc irq and rxe irq flags may change value at different times in response to a single event. there are cases when this bit is not triggered when ack en = 1 and there is an error in reception. therefore, firmware should examine rxc irq, rxe irq, and crc 0 to determine receive status. if the first read of this register returns rxc irq = 1 and rxe irq = 0 then fi rmware must execute a second read to this register to deter- mine if an error occurred by examining the status of rxe irq. if the first read of this register returns rxc irq = 1 and rxe ir q = 1 then the firmware must not execute a second read to this register for a given transaction. bit 0 receive error interrupt status. this irq is triggered when there is an error in reception. it is triggered whenever a pack et is received with a bad crc16, an unexpected eop is detected, a packet type (data or ack) mismatch, or a packet is dropped because the receive buffer is still not empty when the next pack et starts. the exact cause of the error may be determined by reading rx_status_adr. this bit is cleared when this register is read.
CYRF6936 document #: 38-16015 rev. *f page 18 of 39 mnemonic rx_status_adr address 0x08 bit 7 6 5 4 3 2 1 0 default - - - - - - - - read/write r r r r r r r r function rx ack pkt err eop err crc0 bad crc rx code rx data mode it is expected that firmware does not read this register until af ter rx go self clears. status bits are non-atomic (different f lags may change value at different times in response to a single event). bit 7 rx packet type. this bit is set when the received packe t is an ack packet, and cleared when the received packet is a stand ard packet. bit 6 receive packet type error. this bit is set when the pack et type received is what not was expected and cleared when the packet type received was as expected. for example, if a data packet is expected and an ack is received, this bit will be set. bit 5 unexpected eop. this bit is set when an eop is det ected before the expected data length and crc16 fields have been received. this bit is cleared when sop pattern for the next pa cket has been received. this includes the case where there are invalid bits detected in the length fiel d and the length field is forced to 0. bit 4 zero-seed crc16. this bit is set whenever the crc16 of the last received packet has a zero seed. bit 3 bad crc16. this bit is set when the crc 16 of the last received packet is incorrect. bit 2 receive code length. this bit indicates the data_code_adr code length used in the last correctly received packet. 1 = 64- chip code, 0 = 32-chip code. bits 1:0 receive data mode. these bits indicate the data mode of the last correctly received packet. 00 = 1-mbps gfsk 01 = 8dr 1 0 = ddr. 11 = not valid. these bits do not apply to unframed packets. mnemonic rx_count_adr address 0x09 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r r r r r r r r function rx count count bits are non-atomic (updated at different times). bits 7:0 this register contains the total number of payload byte s received during reception of t he current packet. after packet reception is complete, this register will match t he value in rx_length_adr unless there was a packet error. this register is cleared when rx_length_adr is automatically loaded, if length is enabled, after the sop. count should not be read when rx_go=1 during a transaction. mnemonic rx_length_adr address 0x0a bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r r r r r r r r function rx length length bits are non-atomic (different flags may change valu e at different times in response to a single event). bits 7:0 this register contains the length field which is updated with the reception of a new length field (shortly after start of packet detected). if there is an error in the received length field, 0x 00 is loaded instead, except when using gfsk datarate, and an error is flagged.
CYRF6936 document #: 38-16015 rev. *f page 19 of 39 mnemonic pwr_ctrl_adr address 0x0b bit 7 6 5 4 3 2 1 0 default 1 0 1 - 0 0 0 0 read/write r/w r/w r/w - r/w r/w r/w r/w function pmu en lvirq en pmu sen not used lvi th pmu outv bit 7 power management unit (pmu) enable. setting this bit enables the pmu. when the pmu is disabled, or if the pmu is enabled and the v bat voltage is above the value set in bits 1:0 of this register, the v reg pin is internally connected to the v bat pin. if the pmu is enabled and the v bat voltage is below the value set by pmu outv, then the pmu will boost the v reg pin to a voltage not less than the value set by pmu outv. bit 6 low voltage interrupt enable. setting this bit enables the lv irq interrupt. when this interrupt is enabled, if the v bat voltage falls below the threshold set by lvi th, then a low voltage in terrupt will be generated. the lvi is not available when the devi ce is in sleep mode. the lvi event on irq pin is autom atically disabled whenev er the pmu is disabled. bit 5 pmu sleep mode enable. if this bit is set, the pmu will continue to operate nor mally when the device is in sleep mode. if this bit is not set, then the pmu is disabled when the dev ice is in sleep mode. in this case, if v bat is below the pmu outv voltage and pmu en is set, when the device enters sleep mode the v reg voltage falls to the v bat voltage as the v reg capacitors dis- charge. bits 3:2 low voltage interrupt threshold. this field sets the voltage on v bat at which the lvi is triggered. 11 = 1.8v; 10 = 2.0v; 01 = 2.2v; 00 = pmu outv voltage. bits 1:0 pmu output voltage. this field sets the minimum output voltage of the pmu. 11 = 2.4v; 10 = 2.5v; 01 = 2.6v; 00 = 2.7v. when the pmu is active, the voltage output by the pmu on v reg will never be less than this voltage provided that the total load on the v reg pin is less than the specified maximum value, and the voltage in v bat is greater than the specified minimum value. mnemonic xtal_ctrl_adr address 0x0c bit 7 6 5 4 3 2 1 0 default 0 0 0 - - 1 0 0 read/write r/w r/w r/w - - r/w r/w r/w function xout fn xsirq en not used not used freq bits 7:6 xout pin function. this field sele cts between the different functions of the xo ut pin. 00 = clock frequency set by xout freq; 01 = active low pa control; 10 = radio data serial bit stre am. if this option is selected and spi is configured for 3-wir e mode then the miso pin will output a serial clock associated with this data stream; 11 = gpio. to disable this output, set to gpio mode, and set the gpio state in io_cfg_adr. bit 5 crystal stable interrupt enable. this bit enables the os irq interrupt. when enabled, this interrupt generates an irq even t when the crystal has stabilized after the dev ice has woken from sleep mode. this event is cleared by writing zero to this bit. bits 2:0 xout frequency. this field sets the frequency output on the xout pin when xout fn is set to 00. 0 = 12 mhz; 1 = 6 mhz, 2 = 3 mhz, 3 = 1.5 mhz, 4 = 0.75 mhz; other values are not defined.
CYRF6936 document #: 38-16015 rev. *f page 20 of 39 mnemonic io_cfg_adr address 0x0d bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function irq od irq pol miso od xout od pactl od pactl gpio spi 3pin irq gpio to use a gpio pin as an input, the output mode must be set to open drain, and a ?1? written to the corresponding output registe r bit. bit 7 irq pin drive strength. setting this bit configures the ir q pin as an open drain output. clearing this bit configures the irq pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 6 irq polarity. setting this bit configur es the irq signal polarity to be active hi gh. clearing this bit configures the irq signal polarity to be active low. bit 5 miso pin drive strength. setting this bit configures the miso pin as an open dr ain output. clearing this bit configures th e miso pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 4 xout pin drive strength. setting this bit configures the xout pin as an open dr ain output. clearing this bit configures th e xout pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 3 pactl pin drive strength. setting this bit configures the pactl pin as an open drain output. clearing this bit configures the pactl pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 2 pactl pin function. when this bit is set the pactl pin is available for use as a gpio. bit 1 spi mode. when this bit is cleared, the spi interface acts as a standard 4-wire spi slave in terface. when this bit is set, the spi interface operates in ?3-wire mode? combining miso and mosi on the same pin (sdat), and the miso pin is available as a gpio pin. bit 0 irq pin function. when this bit is cl eared, the irq pin is asserted when an irq is active; the polarity of this irq signal is con- figurable in irq pol. when this bit is se t, the irq pin is available for use as a gp io pin, and the irq function is multiplexed onto the mosi pin. in this case the irq signal state is presented on the mosi pin whenever the ss signal is inactive (high). mnemonic gpio_ctrl_adr address 0x0e bit 7 6 5 4 3 2 1 0 default 0 0 0 0 - - - - read/write r/w r/w r/w r/w r r r r function xout op miso op pactl op irq op xout ip miso ip pactl ip irq ip to use a gpio pin as an input, the output mode must be set to open drain, and a ?1? written to the corresponding output registe r bit. bit 7 xout output. when the xout pin is configured to be a gpio, the state of this bit sets the output state of the xout pin. bit 6 miso output. when the miso pin is configured to be a gpio, the state of this bit sets the output state of the miso pin. bit 5 pactl output. when the pactl pin is configured to be a gpio, the state of this bit sets the output state of the pactl pin. bit 4 irq output. when the irq pin is conf igured to be a gpio, the state of this bit sets the output state of the irq pin. bit 3 xout input. the state of this bit reflects the voltage on the xout pin. bit 2 miso input. the state of this bit reflects the voltage on the miso pin. bit 1 pactl input. the state of this bit reflects the voltage on the pactl pin. bit 0 irq input. the state of this bi t reflects the voltage on the irq pin.
CYRF6936 document #: 38-16015 rev. *f page 21 of 39 mnemonic xact_cfg_adr address 0x0f bit 7 6 5 4 3 2 1 0 default 1 - 0 0 0 0 0 0 read/write r/w - r/w r/w r/w r/w r/w r/w function ack en not used frc end end state ack to bit 7 acknowledge enable. when this bit is set, an ack packet is automatically transmi tted whenever a valid packet is received; in this case the device is considered to be in transaction mode. after transmission of the ack packet, the device automatically transitions to the end state. when this bi t is cleared, the device transit ions directly to the end state immediately after the end of packet transmission. this bit affe cts both transmitting and receiving devices. bit 5 force end state. setting this bit forces a transition to t he state set in end state. by setting the desired end state at t he same time as setting this bit the device ma y be forced to immediately transition from its current state to any other state. thi s bit is automatically cleared upon completion. firmware must never tr y to force end state while tx go is set, nor when rx go is set and a sop has already been received (packet reception already in progress). bits 4:2 transaction end state. this field defines the mode to which the device transitions af ter receiving or transmitting a pa cket. 000 = sleep mode; 001 = idle mode; 010 = synth mode (tx); 011 = synth mode (rx); 100 = rx mode. in normal use, this field will typically be set to 000 or 001 when the device is transmitting pack ets, and 100 when the device is receiving packets. note that when the device transitions to receive mode as an end state, the receiver must still be armed by setting rx go before the device can begin receiving data. if the system only support pack ets <=16 bytes then firmware should examine rxc irq and rxe irq to determine the status of the packet. if the system supports packets > 16 bytes ensure that end state is not sleep, force rxf=1, perform receive operation, force rxf= 0, and if necessary set end state back to sleep. bits 1:0 ack timeout. when the device is c onfigured for transaction mode, this field se ts the timeout period after transmission of a packet during which an ack must be correctly received in order to prevent a transmit error condition from being detected. this timeout period is expressed in terms of a number of sop_code _adr code lengths; if sop len is set, then the timeout period is this value multiplied by 64 s and if sop len is cleared then the timeout is this value multiplied by 32 s. 00 = 4x; 01 = 8x, 10 = 12x; 11 = 15x the sop_code_adr code length. ack_to must be set to greater than 30 + data code length (only for 8dr) + preamble length + sop code length (x2). mnemonic framing_cfg_adr address 0x10 bit 7 6 5 4 3 2 1 0 default 1 0 1 0 0 1 0 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w function sop en sop len len en sop th bit 7 sop enable. when this bit is set, eac h transmitted packet begins with a sop fiel d, and only packets beginning with a valid sop field will be received. if this bit is cleared, no sop field will be generated when a packet is transmitted, and packet rec ep- tion will begin whenever two succes sive correlations against the data_code_adr code are detected. bit 6 sop pn code length. when this bit is set the sop_code _adr code length is 64 chips. w hen this bit is cleared the sop_code_adr code length is 32 chips. bit 5 packet length enable. when this bit is set the 8-bit val ue contained in tx_length_adr is tr ansmitted immediately after the sop field. in receive mode, the 8 bits i mmediately following the sop field are interpreted as the length of the packet. when th is bit is cleared no packet length fi eld is transmitted. 8dr always sends the packet length field (len en setting is ignored). gfs k requires user set len en = 1. bits 4:0 sop correlator threshold. this is the receive data co rrelator threshold used when a ttempting to detect a sop symbol. th ere is a single threshold for the sop_code_a dr code. this threshold is applied independently to each of sop1 and sop2 fields. when sop len is set, all 5 bits of this fi eld are used. when sop len is cleared, the most significant bit is disregarded. typic al applications configure sop th = 04h fo r sop32 and sop th = 0eh for sop64.
CYRF6936 document #: 38-16015 rev. *f page 22 of 39 mnemonic data32_thold_adr address 0x11 bit 7 6 5 4 3 2 1 0 default - - - - 0 1 0 0 read/write - - - - r/w r/w r/w r/w function not used not used not used not used th32 bits 7:4 not used. bits 3:0 32 chip data pn code correlator threshold. this regi ster sets the correlator threshold used in dsss modes when data code length (see tx_cfg_adr) is set to 32. typical applications configure th32 = 05h. mnemonic data64_thold_adr address 0x12 bit 7 6 5 4 3 2 1 0 default - - - 0 1 0 1 0 read/write - - - r/w r/w r/w r/w r/w function not used not used not used th64 bits 7:5 not used. bits 4:0 64 chip data pn code correlator threshold. this regi ster sets the correlator threshold used in dsss modes when the data code length (see tx_cfg_adr) is set to 64. typical applications configure th64 = 0eh. mnemonic rssi_adr address 0x13 bit 7 6 5 4 3 2 1 0 default 0 - 1 0 0 0 0 0 read/write r - r r r r r r function sop not used lna rssi a received signal strength indicator (rssi) reading is taken aut omatically when an sop symbol is detected. in addition, an rssi reading is taken whenever rssi_adr is read. the contents of this register are not valid after the device is configured for receive mode un til either a sop symbol is detected, or the register is (re)read. the conversion can occur as often as once every 12- s. the approximate slope of the curve is 1.9 db/count, but is not guaranteed. if it is desired to measure the background rf signal strength on a channel before a packet has been received then the mcu shoul d perform a ?dummy? read of this register, the results of which should be di scarded. this ?dummy? read will cause an rssi measurement to be taken, and therefore subsequent readings of the register will yield valid data. bit 7 sop rssi reading. when set, this bit indicates that t he reading in the rssi field was taken when a sop symbol was detected. when cleared, this bit indicate s that the reading stored in the rssi fiel d was triggered by a previous spi read of th is register. bit 5 lna state. this bit indicates the lna state when the rssi reading was taken. when cleared, this bit indicates that the lna was disabled when the rssi reading was taken; if set this bi t indicates that the lna was enabled when the rssi reading was taken. bits 4:0 rssi reading. this field indicates the instantaneous str ength of the rf signal being received at the time that the rssi reading was taken. a larger value indicates a stronger signal. the signal strength measured is for the rf signal on the configured chan - nel, and is measured after the lna stage.
CYRF6936 document #: 38-16015 rev. *f page 23 of 39 mnemonic eop_ctrl_adr address 0x14 bit 7 6 5 4 3 2 1 0 default 1 0 1 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function hen hint eop if the len en bit is set, then the contents of this register hav e no effect. if the len en bit is cleared, then this register i s used to configure how an eop (end of packet) condition is detected. bit 7 eop hint enable. when set, this bit will cause an eop to be detected if no co rrelations have been detected for the number of symbol periods set by the hint field and the last two received bytes match the ca lculated crc16 for all previously received bytes. use of this mode reduces the chance of non-correlations in the middle of a packet from being detected as an eop con- dition. bits 6:4 eop hint symbol count. the minimum number of symbols of consecutive non-correlations at which the last two bytes are checked against the calculated crc16 to detect an eop condition. bits 4:0 eop symbol count. an eop conditi on is deemed to exist when the number of c onsecutive non-correlations is detected. mnemonic crc_seed_lsb_adr address 0x15 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function crc seed lsb the crc16 seed allows different devices to generate or recognize di fferent crc16s for the same payload data. if a transmitter a nd receiver use a randomly selected crc16 seed, the probability of correctl y receiving data intended for a different receiver is 1/65535, e ven if the other transmitter/receiver are using the same sop_code_adr codes and channel. bits 7:0 crc16 seed least significant byte. the lsb of the starting value of the crc16 calculation. mnemonic crc_seed_msb_adr address 0x16 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function crc seed msb bits 7:0 crc16 seed most significant byte. the ms b of the starting value of the crc16 calculation. mnemonic tx_crc_lsb_adr address 0x17 bit 7 6 5 4 3 2 1 0 default - - - - - - - - read/write r r r r r r r r function tx crc lsb bits 7:0 calculated crc16 lsb. the lsb of the crc16 that was calc ulated for the last transmitted packet. this value is only vali d after packet transmission is complete.
CYRF6936 document #: 38-16015 rev. *f page 24 of 39 mnemonic tx_crc_msb_adr address 0x18 bit 7 6 5 4 3 2 1 0 default - - - - - - - - read/write r r r r r r r r function tx crc msb bits 7:0 calculated crc16 msb. the msb of the crc16 that was calc ulated for the last transmitted pa cket. this value is only vali d after packet transmission is complete. mnemonic rx_crc_lsb_adr address 0x19 bit 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 read/write r r r r r r r r function rx crc lsb bits 7:0 received crc16 lsb. the lsb of the crc16 field extracted fr om the last received packet. this value is valid whether or not the crc16 field matched the calculated crc16 of the received packet. mnemonic rx_crc_msb_adr address 0x1a bit 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 read/write r r r r r r r r function rx crc msb bits 7:0 received crc16 msb. the msb of the crc16 field extracted from the last received packet. this value is valid whether or not the crc16 field matched the calculated crc16 of the received packet. mnemonic tx_offset_lsb_adr address 0x1b bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r r r r r r r function strim lsb bits 7:0 the least significant 8 bits of t he synthesizer offset value. this is a 12- bit 2?s complement signed number which may b e used to offset the transmit frequency of the device by up to 1.5 mh z. a positive value increases the transmit frequency, and a negativ e value reduces the transmit frequency. a val ue of +1 increases the transmit frequency by 732.6 hz; a value of ?1 decreases the transmit frequency by 732.6 hz. a value of 0x0555 increases the transmit frequency by 1 mhz; a value of 0xaab decreases the transmit frequency by 1 mhz. typically, this register is loaded with 0x55 during in itialization. typically this feature is used to avoid the need to change the synthesizer frequency when switching between tx and rx. as the if = 1 mhz the rx frequency is offset 1 mhz from the synthesizer frequency; therefore, trans mitting with a 1 mhz offset allo ws the same synthesizer fre- quency to be used for both transmit and receive. synthesizer offset has no effect on receive frequency.
CYRF6936 document #: 38-16015 rev. *f page 25 of 39 mnemonic tx_offset_msb_adr address 0x1c bit 7 6 5 4 3 2 1 0 default - - - - 0 0 0 0 read/write - - - - r/w r/w r/w r/w function not used not used not used not used strim msb bits 7:4 not used. bits 3:0 the most significant 4 bits of the synthesizer trim valu e. typically, this register is loaded with 0x05 during initiali zation. mnemonic mode_override_adr address 0x1d bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 - - 0 read/write w w w w w - - w function rsvd rsvd frc sen frc awake not used not used rst bits 7:6 reserved. must be zero. bit 5 manually initiate synthesizer. setting th is bit forces the synthesizer to start. clearing this bit has no effect. for this bit to operate correctly, the oscillator must be running before this bit is set. bits 4:3 force awake. force the device out of sleep mode. setti ng both bits of this field forc es the oscillator to keep running at all times regardless of the end state setting. clearing bo th of these bits disables this function. bits 2:1 not used. bit 0 reset. setting this bit forces a full reset of the device. clearing this bit has no effect. mnemonic rx_override_adr address 0x1e bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 - read/write r/w r/w r/w r/w r/w r/w r/w - function ack rx rxtx dly man rxack frc rxdr dis crc0 dis rxcrc ace not used this register provides the abi lity to over-ride some automat ic features of the device. bit 7 when this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the given channel when automatically entering receive mode. bit 6 when this bit is set and ack en is enabled, t he transmission of the ack packet is delayed by 20 s. bit 5 force expected packet type. when this bit is set, and the dev ice is in receive mode, the device is configured to receive a n ack packet at the data rate defined in tx_cfg_adr. bit 4 force receive data rate. when this bit is set, the receiver will ignore the data rate encoded in the sop symbol, and will receive data at the data rate defined in tx_cfg_adr. bit 3 reject packets with a zero-seed crc16. setting this bit causes the receiver to reject packets with a zero-seed, and accept only packets with a crc16 that matches the seed in crc_seed_lsb_adr and crc_seed_msb_adr. bit 2 the rx crc16 checker is disabled. if packets with crc16 enabled are received, the crc16 will be treated as payload data and stored in the receive buffer. bit 1 accept bad crc16. setting this bit c auses the receiver to accept packets with a crc16 that do not match the seed in crc_seed_lsb_adr and crc_seed_msb_adr. an ack is to be s ent regardless of the condition of the received crc16. bit 0 not used.
CYRF6936 document #: 38-16015 rev. *f page 26 of 39 mnemonic tx_override_adr address 0x1f bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function ack tx frc pre rsvd man txack ovrd ack dis txcrc rsvd tx inv this register provides the abi lity to over-ride some automat ic features of the device. bit 7 when this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the given channel when automatically entering transmit mode. bit 6 force preamble. when this bit is set, the device will transmit a continuous repetition of the preamble pattern (see preamble_adr) after tx go is set. this mode is useful for some regulatory approval procedures. firmware should set bit rst of mode_override_adr to exit this mode. bit 5 reserved. must be zero. bit 4 transmit ack packet. when this bit is set, the device sends an ack packet when tx go is set. bit 3 ack override. use tx_cfg_adr to determine the data rate and the crc16 used when transmitting an ack packet. bit 2 disable transmit crc16. when set, no crc16 fiel d is present at the end of transmitted packets. bit 1 reserved. must be zero. bit 0 tx data invert. when this bit is set the transmit bitstream is inverted. mnemonic xtal_cfg_adr address 0x26 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd rsvd rsvd start dly rsvd rsvd rsvd this register provides the abi lity to override some automat ic features of the device. bits 7:4 reserved. must be zero. bit 3 crystal startup delay. setting this bit, sets the crystal st artup delay to 150usec to handle warm restarts of the crystal. firmware must set this bit during initialization. bits 2:0 reserved. must be zero. mnemonic clk_override_adr address 0x27 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd this register provides the abi lity to override some automat ic features of the device. bits 7:2 reserved. must be zero. bit 1 force receive clock. streaming applic ations must set this bit during rece ive mode, otherwise this bit is cleared. bit 0 reserved. must be zero.
CYRF6936 document #: 38-16015 rev. *f page 27 of 39 mnemonic clk_en_adr address 0x28 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd this register provides the abi lity to override some automat ic features of the device. bits 7:2 reserved. must be zero. bit 1 force receive clock enable. streaming applic ations must set this bit during initialization. bit 0 reserved. must be zero. mnemonic rx_abort_adr address 0x29 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd abort en rsvd rsvd rsvd rsvd rsvd this register provides the abi lity to override some automat ic features of the device. bits 7:6 reserved. must be zero. bit 5 receive abort enable. typical applic ations will disrupt any pending receive by first setting this bit, otherwise this bit is cleared. bits 4:0 reserved. must be zero. mnemonic auto_cal_time_adr address 0x32 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 1 1 read/write w w w w w w w w function auto_cal_time this register provides the abi lity to override some automat ic features of the device. bits 7:0 auto cal time. firmware must write 3ch to this register during initialization. mnemonic auto_cal_offset_adr address 0x35 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function auto_cal_offset this register provides the abi lity to override some automat ic features of the device. bits 7:0 auto cal offset. firmware must writ e 14h to this register during initialization.
CYRF6936 document #: 38-16015 rev. *f page 28 of 39 mnemonic analog_ctrl_adr address 0x39 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd rsvd rsvd rsvd rsvd rx inv all slow this register provides the abi lity to override some automat ic features of the device. bits 7:2 reserved. must be zero. bit 1 receive invert. when set, the incoming receive data is inverted. firmware must set this bit when interoperability with fir st gen- eration devices is desired. bit 0 all slow. when set, the synth settling time for all channels is the same as fo r slow channels. it is recommended that firm ware set this bit when using gfsk data rate mode.
CYRF6936 document #: 38-16015 rev. *f page 29 of 39 register files files are written to or read from using non- incrementing burst read or write transacti ons. in most cases accessing a file may b e destructive; the file must be completely read/written, otherwis e the contents may be altered. when accessing file registers, th e bytes are presented to the bus least significant byte first. mnemonic tx_buffer_adr address 0x20 length 16 bytes r/w w default 0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx the transmit buffer is a fifo. writing to th is file adds a byte to the packet being s ent. writing more bytes to this file than the packet length in tx_length_adr will have no effect, and these by tes will be lost. the fifo accumulates dat a until it is reset via tx clr in tx_c trl_adr. a previously sent packet, of 16 bytes or less, can be transmitted if tx_go is set without resetting the fifo. the contents of t x_buffer_adr is not affected by the transmission of an auto ack. mnemonic rx_buffer_adr address 0x21 length 16 bytes r/w r default 0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx the receive buffer is a fifo. received bytes ma y be read from this file register at any time that it is not empty, but when rea ding from this file register before a packet has been completely received care must be taken to ensure that error packets (for example with bad crc 16) are handled correctly. when the receive buffer is configured to be overwritten by new packets (the alternative is for new packets to be discarded if t he receive buffer is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overw ritten by a newly received packet while this file register is being read. when the vld en bit in rx_cfg_adr is set, the bytes in this file register alternate?the first byte read is data, the second byt e is a valid flag for each bit in the first byte, the third byte is data, the four th byte valid flags, etc. in sdr and ddr modes the valid flag f or a bit is set if the correlation coefficient for the bit exceeded the correlator threshol d, and is cleared if it did not. in 8dr mode, the msb of a valid flags byte indicates whether or not the correlation coefficient of the corr esponding received symbol exceeded the threshold. the seven lsb s contain the number of erroneous chips received for the data. mnemonic sop_code_adr address 0x22 length 8 bytes r/w r/w default 0x17ff9e213690c782 when using 32 chip sop_code_adr codes , only the first four bytes of this register are used; in order to complete the file write process, these four bytes must be followed by four bytes of ?dummy? data. howeve r, a class of codes known as ?m ultiplicative codes? may be use d; there are 64 chip codes with good auto-correlation and cross-correlation pr operties where the least signifi cant 32 chips themselves have good auto- correlation and cross-correlation properties when used as 32-chip codes. in this case the same eight-byte value may be loaded i nto this file and used for both 32 chip and 64 chip sop symbols. when reading this file, all eight bytes must be read; if fewer t han eight bytes are read from the file, the contents of the fil e will have been rotated by the number of bytes read. this applies to writes, as well. recommended sop codes: 0x91ccf8e291cc373c 0x0fa239ad0fa1c59b 0x2ab18fd22ab064ef 0x507c26dd507ccd66 0x44f616ad44f6e15c 0x46ae31b646aecc5a 0x3cdc829e3cdc78a1 0x7418656f74198eb9 0x49c1df6249c0b1df 0x72141a7f7214e597
CYRF6936 document #: 38-16015 rev. *f page 30 of 39 mnemonic data_code_adr address 0x23 length 16 bytes r/w r/w default 0x02f9939702fa5ce3012bf1db0132be6f in gfsk mode, this file register is ignored. in 64-sdr mode, only the first eight bytes are used. in 32-ddr mode, only eight bytes are used. the format for these eight bytes: 0x00000000bbbbbbbb00000000aaaaaaaa, where ?0? represents unused locations. example: 0x00000000b2bb092b 00000000b86bc0dc; where ?b86bc0dc? represents aaaaaaaa, ?00000000? represents unused locations, ?b2bb092b? re presents bbbbbbbb, and ?00000000? represents unused locations. in 64-ddr and 8dr modes, all sixteen bytes are used. when reading this file, all sixteen bytes must be read; if fewer than sixteen bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. this applies to writes, as well. certain sixteen-byte sequences have been calc ulated that provide excellent auto-corre lation and cross-correlation properties, a nd it is recom- mended that such sequences be used; the default value of this r egister is one such sequence. in typical applications, all devic es use the same data_code_adr codes, and devices and systems are addressed by using different sop_code _adr codes; in such cases it may never be necessary to change the contents of this register from the default value. typical applications shoul d use the default code. mnemonic preamble_adr address 0x24 length 3 bytes r/w r/w default 0x333302 1st byte ? the number of repetitions of the preamble sequence that are to be transmitted. the preamble may be disabled by writi ng 0x00 to this byte. 2nd byte ? least significant eight chips of the preamble sequence 3rd byte ? most significant ei ght chips of the preamble sequence if using 64-sdr to communicate with cywusb69xx devices, set number of repetitions to four for optimum performance when reading this file, all three bytes must be read; if fewer than three bytes are read from the file, the contents of the fil e will have been rotated by the number of bytes read. this applies to writes, as well. mnemonic mfg_id_adr address 0x25 length 6 bytes r r default na to minimize ~190 a of current consumption (default), execute a ?dummy? single-byte spi write to this address with a zero data stage after the contents have been read. non-zero to enable reading of fuses. zero to disable reading fuses.
CYRF6936 document #: 38-16015 rev. *f page 31 of 39 10.0 absolute maximum ratings storage temperature .............. .............. ...... ?65c to +150c ambient temperature with powe r applied .. ?55c to +125c supply voltage on any power supply pin relative to v ss ?0.3v to +3.9v dc voltage to logic inputs [5] ................... ?0.3v to v io +0.3v dc voltage applied to outputs in high-z state .. ?0.3v to v io +0.3v static discharge voltage (digital) [6] ............................>2000v static discharge voltage (rf) [6] ................................. 1100v latch-up current......................................+200 ma, ?200 ma 11.0 operating conditions v cc .....................................................................2.4v to 3.6v v io ......................................................................1.8v to 3.6v v bat ....................................................................1.8v to 3.6v t a (ambient temperature under bias) ............. 0c to +70c ground voltage.................................................................. 0v f osc (crystal frequency)............................ 12mhz 30 ppm notes 5. it is permissible to connect voltages above v io to inputs through a series resistor limiting input current to 1 ma. ac timing not guaranteed. 6. human body model (hbm). 7. v reg depends on battery input voltage. 8. in sleep mode, the i/o interface voltage reference is v bat . 9. in sleep mode, v cc min. can go as low as 1.8v 10. includes current drawn while starting crystal, starting synthesizer, transmitting packet (including sop and crc16), changing to receive mode, and receiving ack handshake. device is in sleep except during this transaction. 11. isb is not guaranteed if any i/o pi n is connected to voltages higher than v io . 12.0 dc characteristics (t = 25 c, v bat = 2.4v, pmu disabled, f osc = 12.000000mhz) parameter description conditions min. typ. max. unit v bat battery voltage 0?70 c 1.8 3.6 v v reg [7] pmu output voltage 2.4v mode 2.4 2.43 v v reg [7] pmu output voltage 2.7v mode 2.7 2.73 v v io [8] v io voltage 1.8 3.6 v v cc v cc voltage 0?70 c 2.4 [9] 3.6 v v oh1 output high voltage condition 1 at i oh = ?100.0 a v io ? 0.2 v io v v oh2 output high voltage condition 2 at i oh = ?2.0 ma v io ? 0.4 v io v v ol output low voltage at i ol = 2.0 ma 0 0.45 v v ih input high voltage 0.7v io v io v v il input low voltage 0 0.3v io v i il input leakage current 0 < v in < v io ?1 0.26 +1 a c in pin input capacitance except xtal, rf n , rf p , rf bias 3.5 10 pf i cc (gfsk) [10] average tx icc, 1mbps, slow channel pa = 5, 2-way, 4-bytes/10 ms 0.87 ma i cc (32-8dr) [10] average tx icc, 250kbps, fast channel pa = 5, 2-way, 4-bytes/10 ms 1.2 ma i sb [11] sleep mode icc 0.8 10 a i sb [11] sleep mode icc pmu enabled 31.4 a idle i cc radio off, xtal active xout disabled 1.0 ma i synth i cc during synth start 8.4 ma tx i cc i cc during transmit pa = 5 (?5 dbm) 20.8 ma tx i cc i cc during transmit pa = 6 (0 dbm) 26.2 ma tx i cc i cc during transmit pa = 7 (+4 dbm) 34.1 ma rx i cc i cc during receive lna off, att on 18.4 ma rx i cc i cc during receive lna on, att off 21.2 ma boost eff pmu boost converter efficiency v bat = 2.5v, v reg = 2.73v, i load = 20 ma 81 %
CYRF6936 document #: 38-16015 rev. *f page 32 of 39 figure 13-1. spi timing parameter description conditions min. typ. max. unit i load_ext average pmu external load current v bat = 1.8v, v reg = 2.73v, 0?50 c, rx mode 15 ma i load_ext average pmu external load current v bat = 1.8v, v reg = 2.73v, 50?70 c, rx mode 10 ma 13.0 ac characteristics [12] table 13-1. spi interface [13] parameter description min. typ. max. unit t sck_cyc spi clock period 238.1 ns t sck_hi spi clock high time 100 ns t sck_lo spi clock low time 100 ns t dat_su spi input data set-up time 25 ns t dat_hld spi input data hold time 10 ns t dat_val spi output data valid time 0 50 ns t dat_val_tri spi output data tri-state (mosi from slave select deassert) 20 ns t ss_su spi slave select set-up time before first positive edge of sck [14] 10 ns t ss_hld spi slave select hold time afte r last negative edge of sck 10 ns t ss_pw spi slave select minimum pulse width 20 ns t sck_su spi slave select set-up time 10 ns t sck_hld spi sck hold time 10 ns t reset minimum rst pin pulse width 10 ns 12.0 dc characteristics (t = 25 c, v bat = 2.4v, pmu disabled, f osc = 12.000000mhz) (continued) sck nss mosi input miso mosi output t sck_hi t sck_lo t ss_su t sck_su t sck_cyc t ss_hld t sck_hld t dat_su t dat_hld t dat_val t dat_val_tri notes 12. ac values are not guaranteed if voltage on any pin exceed v io . 13. c load = 30 pf. 14. sck must start low at the time ss goes low, otherwise the success of spi transactions are not guaranteed.
CYRF6936 document #: 38-16015 rev. *f page 33 of 39 14.0 rf characteristics notes 15. subject to regulation. 16. exceptions f/3 & 5c/3. table 14-1. radio parameters parameter description cond itions min. typ. max. unit rf frequency range note 15 2.400 2.497 ghz receiver (t = 25c, v cc = 3.0v, f osc = 12.000000mhz, ber < 1e-3) sensitivity 125kbps 64-8dr ber 1e-3 ?97 dbm sensitivity 250-kbps 32-8dr ber 1e-3 ?93 dbm sensitivity cer 1e-3 ?80 ?87 dbm sensitivity gfsk ber 1e-3, all slow = 1 ?84 dbm lna gain 22.8 db att gain ?31.7 db maximum received signal lna on ?15 ?6 dbm rssi value for pwr in ?60 dbm lna on 21 count rssi slope 1.9 db/count interference performance (cer 1e-3) co-channel interference rejection carrier-to-interference (c/i) c = ?60 dbm 9 db adjacent (1 mhz) channel selectivity c/i 1 mhz c = ?60 dbm 3 db adjacent (2 mhz) channel selectivity c/i 2 mhz c = ?60 dbm ?30 db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = ?67 dbm ?38 db out-of-band blocking 30 mhz?12.75 mhz [16] c = ?67 dbm ?30 dbm intermodulation c = ?64 dbm, ? f = 5,10 mhz ?36 dbm receive spurious emission 800 mhz 100-khz resbw ?79 dbm 1.6 ghz 100-khz resbw ?71 dbm 3.2 ghz 100-khz resbw ?65 dbm transmitter (t = 25c, v cc = 3.0v) maximum rf transmit power pa = 7 +2 4 +6 dbm maximum rf transmit power pa = 6 ?2 0 +2 dbm maximum rf transmit power pa = 5 ?7 ?5 ?3 dbm maximum rf transmit power pa = 0 ?35 dbm rf power control range 39 db rf power range control step size seven steps, monotonic 5.6 db frequency deviation min pn code pattern 10101010 270 khz frequency deviation max pn code pattern 11110000 323 khz error vector magnitude (fsk error) >0 dbm 10 %rms occupied bandwidth ?6 dbc, 100-khz resbw 500 876 khz transmit spurious emission (pa = 7) in-band spurious second channel power (2 mhz) ?38 dbm in-band spurious third channel power (> 3 mhz) ?44 dbm
CYRF6936 document #: 38-16015 rev. *f page 34 of 39 non-harmonically related spurs (800mhz) ?38 dbm non-harmonically related spurs (1.6ghz) ?34 dbm non-harmonically related spurs (3.2ghz) ?47 dbm harmonic spurs (second harmonic) ?43 dbm harmonic spurs (third harmonic) ?48 dbm fourth and greater harmonics ?59 dbm power management (crystal pn# ecera gf-1200008) crystal start to 10ppm 0.7 1.3 ms crystal start to irq xsirq en = 1 0.6 ms synth settle slow channels 270 s synth settle medium channels 180 s synth settle fast channels 100 s link turn-around time gfsk 30 s link turn-around time 250 kbps 62 s link turn-around time 125 kbps 94 s link turn-around time <125 kbps 31 s max. packet length <60ppm crystal-to-crystal all modes except 64-ddr 40 bytes max. packet length <60ppm crystal-to-crystal 64-ddr 16 bytes table 14-1. radio parameters (continued) parameter description cond itions min. typ. max. unit
CYRF6936 document #: 38-16015 rev. *f page 35 of 39 15.0 typical operating characteristics [17] receiver sensitivity vs. frequency offset -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -150 -100 -50 0 50 100 150 crystal offset (ppm) receiver sensitivity (dbm) rx sensitivity vs. vcc (1mbps cer) -94 -92 -90 -88 -86 -84 -82 -80 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc receiver sensitivity (dbm) transmit power vs. vcc (pmu off) -14 -12 -10 -8 -6 -4 -2 0 2 4 6 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc output power (dbm) transmit power vs. temperature (vcc = 2.7v) -14 -12 -10 -8 -6 -4 -2 0 2 4 6 0204060 temp (deg c) output power (dbm) receiver sensitivity vs channel (3.0v, room temp) -95 -93 -91 -89 -87 -85 -83 -81 020406080 channel receiver sensitivity (dbm) carrier to interferer (narrow band, lp modulation) -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 -10 -5 0 5 10 channel offset (mhz) c/i (db) rssi vs. channel (rx signal = -70dbm) 0 2 4 6 8 10 12 14 16 18 0 20406080 channel rssi count typical rssi count vs input power 0 8 16 24 32 -120 -100 -80 -60 -40 -20 input power (dbm) rssi count transmit power vs. channel -14 -12 -10 -8 -6 -4 -2 0 2 4 6 0 20406080 channel output power (dbm) average rssi vs. temperature (rx signal = -70dbm) 12 13 14 15 16 17 18 19 0204060 temp (deg c) rssi count pa7 pa6 pa5 pa4 pa7 pa6 pa5 pa4 pa7 pa6 pa5 pa4 lna on lna off lna off att on gfsk ddr32 8dr64 gfsk cer ddr32 8dr32 cer 8dr32 rx sensitivity vs. temperature (1mbps cer) -94 -92 -90 -88 -86 -84 -82 -80 0204060 temp (deg c) receiver sensitivity (dbm) cer 8dr32 average rssi vs. vcc (rx signal = -70dbm) 10 11 12 13 14 15 16 17 18 19 20 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc rssi count note 17. with lna on, att off, above -2dbm erroneous rssi values may be read, cross-checking rssi with lna off/on is recommended for accurate readings.
CYRF6936 document #: 38-16015 rev. *f page 36 of 39 gfsk vs. ber (sop threshold = 5, c38 slow) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 -100 -80 -60 -40 -20 0 input power (dbm) %ber icc rx synth 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx synth 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa0 14 14.5 15 15.5 16 16.5 17 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa1 14 14.5 15 15.5 16 16.5 17 17.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa2 15 15.5 16 16.5 17 17.5 18 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa3 15.5 16 16.5 17 17.5 18 18.5 19 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa4 16.5 17 17.5 18 18.5 19 19.5 20 20.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) ber vs. data threshold (32-ddr) (sop threshold = 5, c38 slow) 0.00001 0.0001 0.001 0.01 0.1 1 10 -100 -95 -90 -85 -80 -75 -70 input power (dbm) %ber ber vs. data threshold (32-8dr) (sop threshold = 5, c38 slow) 0.00001 0.0001 0.001 0.01 0.1 1 10 -100 -95 -90 -85 -80 -75 -70 input power (dbm) %ber 0 1 3 6 0 thru 7 gfsk icc rx (lna off) 17 17.5 18 18.5 19 19.5 20 20.5 21 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc rx (lna on) 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v
CYRF6936 document #: 38-16015 rev. *f page 37 of 39 16.0 ac test loads and waveforms for digital pins figure 16-1. ac test loads and waveforms for digital pins 17.0 ordering information icc tx @ pa5 19.5 20 20.5 21 21.5 22 22.5 23 23.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa6 24.5 25 25.5 26 26.5 27 27.5 28 28.5 29 29.5 30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa7 32.5 33 33.5 34 34.5 35 35.5 36 36.5 37 37.5 38 38.5 39 39.5 40 40.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 3.3v 3.0v 2.7v 2.4v 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: v th thvenin equivalent rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 ? r2 937 ? r th 500 ? v th 1.4 v v cc 3.00 v v cc output r1 r2 ac test loads dc test load table 17-1. ordering information part number radio package name package type operating range CYRF6936-40lfxc transceiver 40 qfn 40 quad flat package no leads lead-free commercial
CYRF6936 document #: 38-16015 rev. *f page 38 of 39 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 18.0 package description figure 18-1. 40-pin lead-free qfn 6x6 mm ly40 the recommended dimension of the pcb pad size for the e- pad underneath the qfn is 3.5 mm 3.5 mm (width x length). this document is subject to change, and may be found to contai n errors of omission or changes in parameters. for feedback or technical support regarding cypress wirelessusb products plea se contact cypress at www. cypress.com. wi relessusb, psoc, and encore are trademarks of cypress semiconductor. all produ ct and company names mentioned in this document are the trademarks of their respective holders. 0.60[0.024] 5.70[0.224] 5.90[0.232] a c 1.00[0.039] max. n seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08[0.003] 0.50[0.020] 0.05[0.002] max. 2 (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 4.45[0.175] 6.10[0.240] 5.80[0.228] 4.55[0.179] 0.45[0.018] 0.20[0.008] r. dia. 0.28[0.011] 0.30[0.012] 0.60[0.024] 5.90[0.232] 5.80[0.228] 5.70[0.224] 6.10[0.240] 4.55[0.179] 4.45[0.175] top view bottom view side view e-pad (pad size vary by device type) 51-85190-**
CYRF6936 document #: 38-16015 rev. *f page 39 of 39 document history page description title: CYRF6936 wire lessusb? lp 2.4ghz radio soc document number: 38-16015 rev. ecn no. issue date orig. of change description of change ** 307437 see ecn tge new data sheet *a 377574 see ecn tge preliminary release? - updated section 1.0 - features - updated section 2.0 - applications - added section 3.0 - applications support - updated section 4.0 - functional descriptions - updated section 5.0 - pin description - added figure 5-1 - updated section 6.0 - functional overview - added section 7.0 - functional block overview - added section 9.0 - register descriptions - updated section 10.0 - absolute maximum ratings - updated section 11.0 - operating conditions - updated section 12.0 - dc characteristics - updated section 13.0 - ac characteristics - updated section 14.0 - rf characteristics - added section 16.0 - ordering information *b 398756 see ecn tge es-10 update- - changed part no. - updated section 9.0 - register descriptions - updated section 12.0 - dc characteristics - updated section 14.0 - rf characteristics *c 412778 see ecn tge es-10 update- - updated section 4.0 - functional descriptions - updated section 5.0 - pin descriptions - updated section 6.0 - functional overview - updated section 7.0 - functional block overview - updated section 9.0 - register descriptions - updated section 10.0 - absolute maximum ratings - updated section 11.0 - operating conditions - updated section 14.0 - rf characteristics *d 435578 see ecn tge - updated section 1.0 - features - updated section 5.0 - pin descriptions - updated section 6.0 - functional overview - updated section 7.0 - functional block overview - updated section 9.0 - register descriptions - added section 10.0 - recommended radio circuit schematic - updated section 11.0 - absolute maximum ratings - updated section 12.0 - operating conditions - updated section 13.0 - dc characteristics - updated section 14.0 - ac characteristics - updated section 15.0 - rf characteristics *e 460458 see ecn boo final data sheet - removed ?preliminary? notation *f 487261 see ecn tge - updated section 1.0 - features - updated section 5.0 - pin descriptions - updated section 6.0 - functional overview - updated section 7.0 - functional block overview - updated section 8.0 - application example - updated section 9.0 - register descriptions - updated section 12.0 - dc characteristics - updated section 13.0 - ac characteristics - updated section 14.0 - rf characteristics - added section 15.0 - typica l operating characteristics

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