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1 pf1076-02 E0C88F360 8-bit single chip microcomputer l evaluation chip with flash built-in l compatible with e0c88861/862/832/348/317/316/308 l on-board writing supported n description the E0C88F360 is a cmos 8-bit microcomputer composed of the core cpu e0c88 (model3), rewritable rom (flash), ram, dot-matrix type lcd driver, three types of timers and asynchronous/clock synchronous selectable serial interface. the E0C88F360 has a built-in large-capacity flash rom (60k 8 bits) and a ram (2k 8 bits), and is upper compatible with the e0c88861, e0c88862, e0c88832, e0c88348, e0c88317, e0c88316 and e0c88308. the E0C88F360 can be used as a mtp (multi-time programming) when develop- ing programs. n features l core cpu .............................................. e0c88 (model3) cmos 8-bit core cpu l osc1 oscillation circuit ......................... 32.768khz (typ.) crystal oscillation circuit l osc3 oscillation circuit ......................... 8.2mhz (max.) crystal/ceramic oscillation circuit l instruction set ........................................ 608 types (usable for multiplication and division instructions) l instruction execution time ..................... 0.244 sec/8.2mhz (for 2-clock instructions) l prom (flash eeprom) ...................... 61,440 8 bits supports serial- and parallel-programming method using the exclusive rom writer l ram ...................................................... 2k-byte ram 3,216-bit display memory l bus line ................................................. address bus : 19 bits (shared with output ports) data bus : 8 bits (shared with i/o ports) ce signal : 4 bits (shared with output ports) wr signal : 1 bit (shared with output port) rd signal : 1 bit (shared with output port) l input port ............................................... 10 bits (usable for evin and breq signal inputs) l output port ............................................ 9 bits (usable for buzzer, lcd control, fout, tout and back signal outputs) l i/o port .................................................. 8 bits (usable for serial i/o and analog comparator inputs) l serial interface ...................................... 1 ch. (8-bit clock synchronous or asynchronous system) l timer ..................................................... programmable timer (8 bits) : 2 ch. (usable as a 1-ch. 16-bit timer) clock timer (8 bits) : 1 ch. stopwatch timer (8 bits) : 1 ch. l lcd driver ............................................. dot-matrix type (supports 5 8 or 5 5 dot font) 51 segments 32 commons, 67 segments 16 or 8 commons lcd power supply circuit built-in (boostor type, 5 potentials) l sound generator ................................... envelope and volume control functions built-in l watchdog timer ..................................... built-in l analog comparator ............................... 2 ch. l a/d converter ........................................ 4 ch., 10-bit resolution, maximum error = 3lsb (not available if analog comparator is used) low voltage operation products preliminary preliminary
2 E0C88F360 l supply voltage detection (svd) circuit ... 16-level detection l external interrupt .................................. input port interrupt : 2 systems (3 types) l internal interrupt .................................... timer interrupt : 3 systems (9 types) serial interface interrupt : 1 system (3 types) a/d converter interrupt : 1 system (1 type) l power supply voltage ............................ normal mode : 2.4v to 5.5v (max. 4.2mhz) v d1 = 2.2v low-power mode : 1.8v * to 3.5v (max. 50khz) v d1 = 1.6v high-speed mode : 3.5v to 5.5v (max. 8.2mhz * )v d1 = 3.3v l current consumption ............................ E0C88F360 * e0c88862 (measured value) halt mode : 3a (typ., normal mode) 2a (typ., normal mode) run (32khz) : 18a (typ., normal mode) 10a (typ., normal mode) run (4mhz) : 2ma (typ., normal mode) 1.5ma (typ., normal mode) l package ................................................ qfp18-176pin (plastic) or chip * design objective n block diagram core cpu e0c88 interrupt controller system controller input port oscillator osc1, 2 osc3, 4 breq (k11) back (r51) reset/test reset test watchdog timer k00?07 k10 (evin) k11 (breq) i/o port serial interface external memory interface output port programmable timer /event counter clock timer stopwatch timer power generator v dd v ss v d1 v c1 ? c5 ca?e analog comparator /ad converter ram 2k byte evin (k10) p00?07 (d0?7) p14?17 p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) r00?07, r10?17, r20?22 (a0?7, a8?15, a16?18) r23, r24 (rd, wr) r30?33 (ce0?e3) r25, r26 (cl, fr) r27 (tout) r35?37 r50 (bz) r51 (back) sound generator lcd driver seg0?eg50 com16?om31 (seg66?eg51) com0?om15 xsprg rxd txd clkw sclk prom 60k byte prom programmer r34 (fout) * supply voltage detector * the prom block indicated with a dotted line differ from the e0c88xxx.
3 E0C88F360 n prom programmer and operating modes the biggest difference between the E0C88F360 and the e0c88xxx is that the E0C88F360 contains flash eeprom as the rom that allows the user to write data to it using the exclusive rom writer (universal rom writer ii). the E0C88F360 also has a built-in prom programmer that controls writing data to the prom. the following explains the prom programmer and the operating modes that are added for the programming operation. l configuration of prom programmer the configuration of the prom programmer is shown below. serial transfer controller prom programming control circuit parallel transfer controller rxd txd sclk address signal data signal control signal xsprg clkw prom programmer sub-address bus sub-data bus from/to exclusive prom writer the prom programmer supports serial programming for writing data received in serial transfer and parallel programming that uses a parallel transfer. the programming method will be described later. terminals the prom programmer uses the following input/output terminals. the following sections will explain handling the terminals in each operating mode. xsprg: prom serial programming mode setting terminal rxd: serial data receive terminal txd: serial data transmit terminal sclk: serial clock input/output terminal clkw: serial programming source clock (3.072 mhz) input terminal the parallel programming mode uses other terminals in addition to the terminals above. however, it is not neces- sary to switch the lines on the board, because the ic is programed by directly installing it to the exclusive prom writer (universal rom writer ii). l operating modes three operating modes are available in the E0C88F360: one is for normal operation and the others are for programming. 1) normal operation mode (normal mode/high-speed mode) 2) prom serial programming mode 3) prom parallel programming mode the operating mode is decided by the xsprg terminal setting at power on or initial reset. normal operation mode in this mode, the e0c88 core cpu and the peripheral circuits operate by the programmed prom. the cpu can enter this mode after the prom programming has finished. the prom bit data is set to "1" at shipment. therefore, the ic will not work even if the normal operation mode is set before programming.
4 E0C88F360 in the normal operation mode, set the terminals for the prom programmer as below. the board must be de- signed so that the terminal settings cannot be changed. xsprg: fix at a high level. rxd, sclk, clkw: open or fix at a high level. txd: open. prom serial programming mode the prom serial programming mode should be set when writing data to the prom using a serial transfer from the exclusive prom writer (universal rom writer ii). this mode will be used for the programming of chip products, because the programming can be done even when the ic has already been mounted on the board. to create data to be written to the prom, use the e0c88 assembler similar to the e0c88xxx. the following explains the procedure of prom serial programming. (1) set the required terminals for serial programming as follows: xsprg: set the terminal so that it will be fixed to a low level. (a switch should be provided on the target board to change the xsprg terminal level between high and low.) note : the xsprg terminal must be fixed at a low level in the programming mode and at a high level in the normal operation mode. changing the voltage level may damage the ic. rxd, txd, sclk: connect to the prom writer. clkw: connect to the prom writer. a 3.072 mhz clock will be supplied from the prom writer at program- ming. other terminals should be set as below. input port (k) and i/o port (p) terminals: fix at a high or low level. test terminal: fix at a high level. (2) turn the ic (user target board) power (+5 v) on. a power voltage must be supplied to the v dd and v ss terminals same as the regular operation so that the osc1 oscillation circuits operate normally. (3) turn the prom writer on. (4) controls the reset and xsprg terminals as shown below. reset xsprg prom writer power on 1? s 0.5? s start of serial programming mode 2? s (5) start up us88f360.exe or jp88f360.exe in the personal computer, then load the 88f360.frm file. this allows serial programming to begin. after setting this mode, data can be written to the exclusive prom writer (universal rom writer ii). refer to the "e0c88pxxx universal rom writer ii users manual" for the connection and operation of the prom writer. prom parallel programming mode in the prom parallel programming mode, the exclusive prom writer (universal rom writer ii) transfers data in parallel to the ic installed on the prom writer to write data to it. the terminal setting is done by the prom writer. thus there is no precaution on mode setting or board design. refer to the "e0c88pxxx universal rom writer ii users manual" for the operation of the prom writer. to create data to be written to the prom, use the e0c88 assembler the same as the e0c88xxx.
5 E0C88F360 n differences from the mask rom models l mask option the mask option items are fixed in the E0C88F360 as shown in the table below. mask option osc1 oscillation circuit osc3 oscillation circuit multiple key entry reset combination svd reset input port pull up resistor k00 k01 k02 k03 k04 k05 k06 k07 k10 k11 reset i/o port pull up resistor p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 output port specification r00 r01 r02 r03 r04 r05 r06 r07 r10 r11 r12 r13 r14 r15 r16 r17 lcd drive duty lcd power supply set 1 crystal oscillation (32.768 khz) cr oscillation not use not use with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor no resistor no resistor no resistor no resistor complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary 1/32 & 1/16 duty internal power supply (4.5 v) set 2 crystal oscillation (32.768 khz) crystal/ceramic oscillation not use not use with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor with resistor no resistor no resistor no resistor no resistor complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary 1/32 & 1/16 duty internal power supply (5.5 v)
6 E0C88F360 l power supply operating voltage range model E0C88F360 e0c88316 e0c88317 e0c88348 e0c88308 e0c88860 e0c88861 e0c88862 e0c88832 normal mode (v d1 = 2.2v) 2.4 to 5.5v 2.4 to 5.5v 2.4 to 5.5v 2.4 to 5.5v 2.4 to 5.5v 2.4 to 5.5v 2.4 to 5.5v 2.4 to 5.5v 2.4 to 5.5v high-speed mode (v d1 = 3.3v) 3.5 to 5.5v 3.5 to 5.5v 3.5 to 5.5v 3.5 to 5.5v 3.5 to 5.5v 3.5 to 5.5v 3.5 to 5.5v 3.5 to 5.5v 3.5 to 5.5v low-power mode (v d1 = 1.6v) * 1.8 to 3.5v 1.8 to 3.5v 1.8 to 3.5v 1.8 to 3.5v 1.8 to 3.5v 1.8 to 3.5v 1.8 to 3.5v 1.8 to 3.5v 1.8 to 3.5v * the minimum operating voltage (1.8v) in low-power mode is subject to change without notice. the E0C88F360 operation is guaranteed within the above voltage range. lcd drive voltage (v c1 Cv c5 ) lcd drive voltage v c1 v c2 v c3 v c4 v c5 type a (4.5 v) v c5 type b (5.5 v) condition * 1 * 2 * 3 * 4 * 5 lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh * 5 lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh min. 0.18v c5 0.39v c5 0.59v c5 0.80v c5 typ. 0.94 typ. 0.94 e0c883xx/888xx max. 0.22v c5 0.43v c5 0.63v c5 0.84v c5 typ. 1.06 typ. 1.06 min. 0.18v c5 0.39v c5 0.59v c5 0.80v c5 typ. 0.94 typ. 0.94 E0C88F360 max. 0.22v c5 0.43v c5 0.63v c5 0.84v c5 typ. 1.06 typ. 1.06 (unit: v) * 1: when a 1 m w load resistor is connected between v ss and v c1 * 2: when a 1 m w load resistor is connected between v ss and v c2 * 3: when a 1 m w load resistor is connected between v ss and v c3 * 4: when a 1 m w load resistor is connected between v ss and v c4 * 5: when a 1 m w load resistor is connected between v ss and v c5
7 E0C88F360 l initial reset E0C88F360 uses the initial reset signal as a trigger for setting either the normal operation mode or the program- ming mode. therefore, design the reset input circuit so that the ic will be reset for sure. when resetting the ic in the normal operation mode, make sure to fix the xsprg terminal at high level. l rom the E0C88F360 employs a flash eeprom for the internal rom. the rom has a capacity of 61,440 8 bits and is allocated to 000000hC00efffh. the flash eeprom can be rewritten up to 1,000 times. rewriting data is done at the user's own risk. l ram the built-in ram has a capacity of 2,048 words 8 bits and is allocated to 00f000hC00f7ffh. l oscillation circuit in the E0C88F360, only crystal oscillator is available for the osc1 oscillation circuit and either cr or crystal/ ceramic oscillator is available for the osc3 oscillation circuit. furthermore, pay attention to the difference on the oscillation start time according to the supply voltage. be sure to have enough margin especially for stabilizing the osc3 oscillation when controlling the peripheral circuit that uses the osc3 clock. l svd circuit the E0C88F360 has a built-in svd circuit. detection level level 1 ? level 0 level 2 ? level 1 level 3 ? level 2 level 4 ? level 3 level 5 ? level 4 level 6 ? level 5 level 7 ? level 6 level 8 ? level 7 level 9 ? level 8 level 10 ? level 9 level 11 ? level 10 level 12 ? level 11 level 13 ? level 12 level 14 ? level 13 level 15 ? level 14 min. typ. 0.92 typ. 0.88 e0c883xx/888xx typ. 1.82 2.00 2.18 2.36 2.54 2.72 2.90 3.08 3.26 3.45 3.65 3.85 4.05 4.25 4.50 max. typ. 1.08 typ. 1.12 (unit: v) min. typ. 0.92 typ. 0.88 e0c883f360 typ. 1.82 2.00 2.18 2.36 2.54 2.72 2.90 3.08 3.26 3.45 3.65 3.85 4.05 4.25 4.50 max. typ. 1.08 typ. 1.12 the mask option for reseting when low voltage is detected (available in the e0c88xxx) is not provided in the E0C88F360.
8 E0C88F360 l list of different specifications between E0C88F360 and e0c88xxx e0c88348 l 48kb 2kb 10 9 8 l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l 2.4 ~ 5.5v 3.5 ~ 5.5v 1.8 ~ 3.5v 30k ~ 50khz 30k ~ 50khz 30k ~ 50khz 30k ~ 4.1mhz 30k ~ 8.2mhz -40 ~ 85 c 18 a 1.0ma 1 a v d1 v d1 v dd v d1 16 levels 2 ch. r26/fr r51/back package qfp18-176pin qfp8-160pin qfp8-128pin qfp15-128pin number of additional pin for flash rom size ram size input port output port i/o port chip mode single chip extended 64k mcu mpu extended mcu 512k min. mpu extended mcu 512k max. mpu operating normal (v d1 = 2.2v) mode high-speed (v d1 = 3.3v) low-power (v d1 = 1.3v) mask rom osc1 crystal option select external cr crystal (with c g ) osc3 crystal ceramic cr external i/o (p) port with resistor pull-up gate direct input (k) port with resistor pull-up gate direct output (r) port complementary output spec. nch open drain lcd duty 1/32 & 1/16 1/8 lcd power type a (4.5v) type b (5.5v) external power source reset k0 port combination svd reset operating voltage normal high-speed low-power operating osc1 normal frequency high-speed low-power osc3 normal high-speed operating temperature power normal (5.5v, 32khz) current high-speed (5.5v, 1mhz) (max.) sleep mode (5.5v, normal mode) power cpu supply peripheral port osc prom svd analog comparator a/d converter r26 output port specification r51 output port specification e0c88316/317 l 16kb 2kb ? ? ? l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r26/fr r51/back e0c88308 l 8kb 256b 9 5 ? l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r26/fr r51/back e0c88862 l l 60kb 1.5kb ? 2 ? l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ? ? ? ? ? ? ? ? ? tbd tbd tbd ? ? ? v osc ? r26/tout r51/bz e0c88861 l l 60kb 1.5kb ? 2 ? l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ? ? ? ? ? ? ? ? ? tbd tbd tbd ? ? ? v d1 ? r26/tout r51/bz e0c88832 l l 32kb 1.5kb ? 2 ? l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ? ? ? ? ? ? ? ? ? tbd tbd tbd ? ? ? ? ? r26/tout r51/bz E0C88F360 l 5 pins 60kb 2kb 10 9 8 l l l l l l l l l l l l l l l l l l l ? ? ? * 1 ? ? ? ? ? -20 ~ 70 c 25 a 2.0ma 1 a ? ? ? ? v d1 ? 2 ch. 4 ch., 10 bits r26/fr/tout r51/back/bz e0c88p348 l l 5 pins 48kb 2kb 10 9 8 l l l l l l l l l l l l l 3.3 ~ 5.5v 4.5 ~ 5.5v ? ? ? 30k ~ 6mhz 0 ~ 70 c 12ma 15ma 1 a v dd v dd ? ? v dd 8 levels r26/fr r51/back l = available, = not available * 1: the E0C88F360 operating voltage range (1.8v to 3.5v) in low-power mode may be modified. notes: the pin assignment of the E0C88F360 is incompatible with the e0c883xx and e0c888xx. the table does not contain some different items. refer to the manuals of the E0C88F360 and the e0c88xxx.
9 E0C88F360 n summary of notes l notes related to the prom (1) the prom data bit is set to "1" at shipment. therefore, it must be programmed before operating the ic in the normal operation mode. (2) the prom data can be rewritten up to 1,000 times. (decrement the count every time the prom is erased and written.) (3) the circuit board should be designed so that the terminals can switch the input signals that differ between the prom serial programming mode and the normal operation mode. (4) the terminals for the prom programmer should be set correctly according to the operating mode and fixed so that they cannot be changed during operation. especially the xsprg terminal must be fixed at a low level in the programming mode, while they must be fixed at a high level in the normal operation mode. changing the voltage level may damage the ic. (5) if the operation of the E0C88F360 is unstable even though the writing and verification of the prom data was completed normally, write and verify the prom data without erasing the prom. (6) rewriting the prom is done at on the user's own risk. l notes on differences form the e0c883xx and e0c888xx be aware of the following notes when using the E0C88F360 as a development tool for the e0c883xx or e0c888xx. memory the E0C88F360 contains a rom and ram lager than most of all e0c883xx/e0c888xx models. when develop- ing an application, pay attention to the memory size. power supply the E0C88F360 is operable with a supply voltage within the range of 1.8 v to 5.5 v. be aware that as the supply voltage is different from the e0c883xx/e0c888xx the electrical characteristics differ. refer to electrical charac- teristics. initial reset note that the power-on reset time differs from the e0c883xx/e0c888xx because the supply voltage is different. oscillation circuit in the E0C88F360, a crystal oscillator can only be used for the osc1 oscillation circuit and a cr or crystal/ ceramic oscillator for the osc3 oscillation circuit. furthermore, pay attention to the difference on the oscillation start time according to the supply voltage. be sure there is enough margin especially for stabilizing the osc3 oscillation when controlling the peripheral circuit that uses the osc3 clock. lcd controller the lcd drive voltage range of the E0C88F360 is different from that of the e0c883xx/e0c888xx. check the electrical characteristic differences by referring to the E0C88F360 and e0c883xx/e0c888xx technical manuals before designing the lcd unit. moreover, note that because mask options are fixed, the lcd drive duty of the E0C88F360 is fixed at 1/32 or 1/16 duty. the internal lcd power supply can be selected either 4.5 v or 5.5 v. mask option in the E0C88F360, some mask options for the e0c883xx/e0c888xx are fixed. therefore, some optional func- tions cannot be used in the E0C88F360. check whether the functions are enabled or not in the E0C88F360 and e0c883xx/e0c888xx technical manuals. a/d converter and analog comparator note that the a/d converter and the analog comparator cannot be used at the same time.
10 E0C88F360 n electrical characteristics note: the electrical characteristics of the E0C88F360 are different from those of the e0c883xx/e0c888xx. the following characteristics should be used as reference values when using the E0C88F360 as a develop- ment tool. l absolute maximum rating item symbol unit value power voltage liquid crystal power voltage input voltage output voltage high level output current low level output current permitted loss operating temperature storage temperature v dd v c5 v i v o i oh i ol p d topr tstg v v v v ma ma ma ma mw c c -0.3 to +7.0 -0.3 to +7.0 -0.3 to v dd + 0.3 -0.3 to v dd + 0.3 -5 -20 5 20 200 -20 to 70 -65 to +150 note) note 1 2 condition 1 terminal total of all terminals 1 terminal total of all terminals 1 2 in case of plastic package. this rated value cannot insure the prom data holdin g function. (v ss =0v) l recommended operating conditions item symbol min. typ. max. unit condition operating power voltage (normal) operating power voltage (high-speed) operating power voltage (low-power) operating frequency (normal) operating frequency (high-speed) lcd power voltage capacitor between v d1 and v ss capacitor between v c1 and v ss capacitor between v c2 and v ss capacitor between v c3 and v ss capacitor between v c4 and v ss capacitor between v c5 and v ss capacitor between ca and cb capacitor between ca and cc capacitor between cd and ce resistor between v c1 and v ss v dd v dd v dd f osc1 f osc3 f osc1 f osc3 v c5 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 r 1 2.4 3.5 1.8 * 30.000 0.03 30.000 0.03 32.768 32.768 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 100 5.5 5.5 3.5 50.000 4.2 50.000 8.2 * 7.0 v v v khz mhz khz mhz v f f f f f f f f f k w v dd = 2.4 to 3.5v v dd = 3.5 to 5.5v note 5 5 3 3 3 3 3 3 3 3 3 4 note) 3 4 5 no capacitor is required when the lcd power supply is not used. in this case, leave the v c1 ? c5 and ca?e terminals open. it is necessary when the panel load is large and for 1/32 duty driving. the resistance value should be decided by connecting it to the actual panel to be used. the value with * may change without norice. it will affect the related characteristics. l dc characteristics item symbol min. typ. max. unit condition high level input voltage low level input voltage high level schmitt input voltage low level schmitt input voltage high level output current low level output current input leak current output leak current input pull-up resistance input terminal capacitance segment/common output current v ih v il v t+ v t- i oh i ol i li i lo r in c in i segh i segl 0.8v dd 0 0.5v dd 0.1v dd 0.5 -1 -1 100 5 v dd 0.2v dd 0.9v dd 0.5v dd -0.5 1 1 500 15 -5 v v v v ma ma a a k w pf a a kxx, pxx, xsprg, rxd, sclk, clkw, mcu/mpu kxx, pxx, xsprg, rxd, sclk, clkw, mcu/mpu reset reset pxx, rxx, txd, v oh = 0.9v dd pxx, rxx, txd, v ol = 0.1v dd kxx, pxx, xsprg, rxd, sclk, clkw, reset, mcu/mpu pxx, rxx, txd kxx, pxx, xsprg, rxd, sclk, clkw, reset, mcu/mpu kxx, pxx, xsprg, rxd, sclk, clkw segxx, comxx, v segh = v c5 -0.1v segxx, comxx, v segl = 0.1v note (unless otherwise specified: v dd =1.8 to 5.5v, v ss =0v, ta=25 c)
11 E0C88F360 l analog circuit characteristics lcd drive circuit lcd drive voltage v c1 v c2 v c3 v c4 v c5 type a (4.5v) v c5 type b (5.5v) 0.18v c5 0.39v c5 0.59v c5 0.80v c5 typ 0.94 typ 0.94 3.89 3.96 4.04 4.11 4.18 4.26 4.34 4.42 4.50 4.58 4.66 4.74 4.82 4.90 4.99 5.08 4.73 4.83 4.92 5.02 5.11 5.21 5.30 5.40 5.50 5.60 5.70 5.81 5.93 6.05 6.17 6.29 0.22v c5 0.43v c5 0.63v c5 0.84v c5 typ 1.06 typ 1.06 v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v # 1 # 2 # 3 # 4 # 5 # 5 lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh item symbol min. typ. max. unit condition note # 1 # 2 # 3 (unless otherwise specified: v dd =1.8 to 5.5v, v ss =0v, ta=25 c, c 1 ? 9 =0.1 f ) connects 1m w load resistor between v ss and v c1 . connects 1m w load resistor between v ss and v c2 . connects 1m w load resistor between v ss and v c3 . # 4 # 5 connects 1m w load resistor between v ss and v c4 . connects 1m w load resistor between v ss and v c5 . svd circuit item symbol min. typ. max. unit condition svd voltage v svd typ 0.92 typ 0.88 1.82 2.00 2.18 2.36 2.54 2.72 2.90 3.08 3.26 3.45 3.65 3.85 4.05 4.25 4.50 typ 1.08 typ 1.12 v v v v v v v v v v v v v v v level 1 ? level 0 level 2 ? level 1 level 3 ? level 2 level 4 ? level 3 level 5 ? level 4 level 6 ? level 5 level 7 ? level 6 level 8 ? level 7 level 9 ? level 8 level 10 ? level 9 level 11 ? level 10 level 12 ? level 11 level 13 ? level 12 level 14 ? level 13 level 15 ? level 14 note 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 note) v svd (level 0) < v svd (level 1) < v svd (level 2) < v svd (level 3) < v svd (level 4) < v svd (level 5) < v svd (level 6) < v svd (level 7) < v svd (level 8) < v svd (level 9) < v svd (level 10) < v svd (level 11) < v svd (level 12) < v svd (level 13) < v svd (level 14) < v svd (level 15) 6 7 8 low-power operation mode low-power or normal operation mode normal or high-speed operating mode (unless otherwise specified: v dd =1.8 to 5.5v, v ss =0v, ta=25 c)
12 E0C88F360 analog comparator note) 9 10 11 when "no pull-up resistor" (comparator input terminal) is selected by mask option. stability time is the time from turning the circuit on until the circuit is stabilized. response time is the time that the output result responds to the input si g nal. (unless otherwise specified: v dd =1.8 to 5.5v, v ss =0v, ta=25 c) item symbol min. typ. max. unit condition analog comparator operating voltage input range analog comparator offset voltage analog comparator stability time analog comparator response time v cmip v cmim v cmof t cmp1 t cmp2 0.7 0.7 v dd - 0.7 v dd - 0.7 20 1 2 v v mv ms ms non-inverted input (cmpp) inverted input (cmpm) v cmip = 0.7v to v dd - 0.7v v cmim = 0.7v to v dd - 0.7v v cmip = 0.7v to v dd - 0.7v v cmim = 0.7v to v dd - 0.7v v cmip = v cmim 0.025v note 9 9 9 10 11 a/d converter * zero-scale error: ezs = deviation from the ideal value at zero point * full-scale error: efs = deviation from the ideal value at the full scale point * non-linearity error: el = deviation of the real conversion curve from the end point line * total error: et = max(ezs, efs, eabs), eabs = deviation from the ideal line (including quantization error) (unless otherwise specified: v dd =av dd =av ref =5.0v, v ss =av ss =0v, f osc1 =32.768khz, f osc3 =4.0mhz, ta=25 c) symbol min. typ. max. unit zero-scale error full-scale error non-linearity error total error a/d converter current consumption input clock frequency ezs efs el et i ad f -1.50 -1.50 -1.50 -3.00 0.50 1.80 2 1.50 1.50 1.50 3.00 1.00 3.50 4 lsb lsb lsb lsb ma ma mhz v dd =av dd =av ref =2.7 to 5.5v, adclk=2mhz, ta=25 c v dd =av dd =av ref =3.0v, adclk=2mhz, ta=25 c av ref and adclk divider current not included v dd =av dd =av ref =5.0v, adclk=2mhz, ta=25 c av ref and adclk divider current not included v dd =av dd =av ref =2.7 to 5.5v, ta=25 c note item condition l power current consumption (the table shows objective values, so they may be changed.) item symbol min. typ. max. unit condition power current (normal mode) power current (high-speed mode) power current (low-power mode) lcd drive circuit current svd circuit current analog comparator circuit current i dd1 i dd2 i dd3 i dd4 i hvl i dd1 i dd2 i dd3 i dd4 i hvl i dd1 i dd2 i dd3 i hvl i lcdn i lcdh i svdn i svdh i cmp1 i cmp2 3 18 0.5 32 1 10 1 5 25 1 70 3 10 40 2 100 1 5 16 40 8 35 180 240 100 10 a a a ma a a a a ma a a a a a a a a a a a in sleep status in halt status cpu is in run status (v dd = 5.5v, 32.768khz) cpu is in run status (v dd = 5.5v, 1mhz) in heavy load protection mode in sleep status in halt status cpu is in run status (v dd = 5.5v, 32.768khz) cpu is in run status (v dd = 5.5v, 1mhz) in heavy load protection mode in sleep status in halt status cpu is in run status (v dd = 3.5v, 32.768khz) in heavy load protection mode v dd = 5.5v in heavy load protection mode v dd = 5.5v in heavy load protection mode cmpxdt="1" cmpxdt="0" note 12 12 12 12 13 12 # 1 # 2 # 3 # 4 12 13 # (unless otherwise specified: v dd =within the operating voltage in each operating mode, v ss =0v, ta=25 c, osc1=32.768khz crystal oscillation, c g =25pf, osc3=external clock input, non heavy load protection mode, c 1 ? 9 =0.1 f, no panel load) osc1: stop, osc1: oscillating, osc1: oscillating, osc1: oscillating, it is the value of current which flows in the heavy load protection circuit when in the heavy load protection mode (osc3 on or buzzer on). the value when v dd = x v can be found by the following expression: i svdn (v dd = x v) = ( x 60) - 150 (max. value) in the E0C88F360, cr option cannot be selected for the osc1 oscillation circuit. # 1 # 2 # 3 # 4 # 1 # 2 # 3 # 4 # 1 # 2 # 3 note) osc3: stop, osc3: stop, osc3: stop, osc3: oscillating, cpu, rom, ram: sleep status, cpu, rom, ram: halt status, cpu, rom, ram: runing in 32.768khz, cpu, rom, ram: runing in 1mhz, clock timer: stop, clock timer: runing, clock timer: runing, clock timer: runing, others: stop status others: stop status others: stop status others: stop status
13 E0C88F360 n package and pad layout l package dimensions l diagram of pad layout plastic qfp18-176pin pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 pin name seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 pin no. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 pin name seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 com31/seg51 com30/seg52 com29/seg53 com28/seg54 com27/seg55 com26/seg56 com25/seg57 com24/seg58 com23/seg59 com22/seg60 com21/seg61 com20/seg62 com19/seg63 com18/seg64 com17/seg65 com16/seg66 v d1f xsprg clkw vepext rxd sclk txd pin no. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 pin name ce cd cc cb ca v c5 v c4 v c3 v c2 v c1 osc3 osc4 v d1 v dd v ss v osc osc1 osc2 test reset mcu/mpu k11/breq k10/evin k07 k06 k05 k04 k03 k02 k01 k00 p17/cmpm1 p16/cmpp1 p15/cmpm0 p14/cmpp0 p13/srdy pin no. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pin name p12/sclk p11/sout p10/sin av dd av ss av ref v dd p07/d7 p06/d6 p05/d5 p04/d4 p03/d3 p02/d2 p01/d1 p00/d0 r00/a0 r01/a1 r02/a2 r03/a3 r04/a4 r05/a5 r06/a6 r07/a7 r10/a8 r11/a9 r12/a10 r13/a11 r14/a12 r15/a13 r16/a14 r17/a15 r20/a16 r21/a17 r22/a18 r23/rd r24/wr pin no. 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 pin name r25/cl r26/fr r27/tout r30/ce0 r31/ce1 r32/ce2 r33/ce3 r34/fout r35 r36 r37 v ss com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 r50/bz r51/back seg0 seg1 6.06 mm y x (0, 0) 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 176 6.06 mm die no. (unit: mm) the dimensions are subject to change without notice. 24 ?.1 26 ?.4 89 132 24 ?.1 26 ?.4 45 88 index 0.2 44 1 176 133 2.7 ?.1 0.1 3 max 0.5 ?.2 0 10 0.15 ?.05 0.5 +0.1 ?.05 1 l pin layout (qfp18-176pin) chip thickness: 400 m pad opening: 95 m
14 E0C88F360 l pad coordinates no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 name osc1 osc2 test reset mcu/mpu k11/breq k10/evin k07 k06 k05 k04 k03 k02 k01 k00 p17/cmpm1 p16/cmpp1 p15/cmpm0 p14/cmpp0 p13/srdy p12/sclk p11/sout p10/sin av dd av ss av ref v dd p07/d7 p06/d6 p05/d5 p04/d4 p03/d3 p02/d2 p01/d1 p00/d0 r00/a0 r01/a1 r02/a2 r03/a3 r04/a4 r05/a5 r06/a6 r07/a7 r10/a8 r11/a9 r12/a10 r13/a11 r14/a12 r15/a13 r16/a14 r17/a15 r20/a16 r21/a17 r22/a18 r23/rd r24/wr r25/cl r26/fr r27/tout x 2,533 2,417 2,302 2,186 2,059 1,943 1,828 1,712 1,597 1,481 1,366 1,250 1,135 1,019 904 776 661 545 430 314 199 83 -32 -163 -279 -394 -510 -641 -756 -872 -987 -1,103 -1,218 -1,334 -1,449 -1,565 -1,680 -1,796 -1,911 -2,027 -2,142 -2,258 -2,373 -2,489 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 x 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,578 2,463 2,347 2,232 2,116 2,001 1,885 1,770 1,654 1,539 1,423 1,308 1,192 1,077 961 pad coordinate no. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 name r30/ce0 r31/ce1 r32/ce2 r33/ce3 r34/fout r35 r36 r37 v ss r50/bz r51/back com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 x -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,600 -2,484 -2,358 -2,242 -2,116 -2,000 -1,874 -1,758 -1,631 -1,516 -1,389 -1,274 -1,147 -1,032 -905 -790 -663 -548 -421 -305 -179 -63 63 179 305 421 548 663 790 905 x 846 730 615 499 384 268 153 37 -93 -224 -340 -470 -586 -701 -817 -932 -1,048 -1,163 -1,279 -1,394 -1,510 -1,625 -1,741 -1,856 -1,972 -2,087 -2,203 -2,339 -2,455 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 pad coordinate no. 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 name seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 com31/seg51 com30/seg52 com29/seg53 com28/seg54 com27/seg55 com26/seg56 com25/seg57 com24/seg58 com23/seg59 com22/seg60 com21/seg61 com20/seg62 com19/seg63 com18/seg64 com17/seg65 com16/seg66 v d1f xsprg clkw vepext rxd sclk txd ce cd cc cb ca v c5 v c4 v c3 v c2 v c1 osc3 osc4 v d1 v dd v ss v osc x 1,032 1,147 1,274 1,389 1,516 1,631 1,758 1,874 2,000 2,116 2,242 2,358 2,484 2,600 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 x -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,896 -2,456 -2,341 -2,214 -2,099 -1,976 -1,845 -1,730 -1,614 -1,499 -1,383 -1,268 -1,152 -1,037 -921 -806 -690 -575 -459 -344 -228 -113 3 118 234 361 489 616 732 862 978 1,093 1,209 1,324 1,440 1,555 1,671 1,786 1,902 2,017 2,133 2,248 2,364 2,479 2,595 pad coordinate (unit: m)
15 E0C88F360 n pin description pin no. v dd v ss v d1 v d1f v osc v c1 ? c5 ca?e osc1 osc2 osc3 osc4 mcu/mpu k00?07 k10/evin k11/breq r00?07/a0?7 r10?17/a8?15 r20?22/a16?18 r23/rd r24/wr r25/cl r26/fr/tout * r27/tout r30?33/ce0?e3 r34/fout r35?37 r50/bz r51/back/bz * p00?07/d0?7 p10/sin p11/sout p12/sclk p13/srdy p14/cmpp0 p15/cmpm0 p16/cmpp1 p17/cmpm1 com0?om15 com16?om31 /seg66?eg51 seg0?eg50 reset test av dd av ss av ref txd rxd sclk clkw xsprg vepext pin name in/out function 86, 115 87, 156 85 66 88 82?8 77?3 89 90 83 84 93 103?6 95 94 124?31 132?39 140?42 143 144 145 146 147 148?51 152 153?55 157 158 123?16 111 110 109 108 107 106 105 104 159?74 65?0 175?76, 1?9 92 91 112 113 114 72 70 71 68 67 69 pad no. 27, 174 68, 175 173 154 176 170?66 165?61 1 2 171 172 5 15? 7 6 36?3 44?1 52?4 55 56 57 58 59 60?3 64 65?7 69 70 35?8 23 22 21 20 19 18 17 16 71?6 153?38 87?37 4 3 24 25 26 160 158 159 156 155 157 o i o i o i i i i o o o o o o o o o o o o o i/o i/o i/o i/o i/o i/o i/o i/o i/o o o o i i o i i/o i i power supply (+) terminal power supply (gnd) terminal internal logic system voltage regulator output terminal internal logic/flash block voltage regulator output terminal (normal: v d1f =v d1 ) oscillation voltage regulator output terminal lcd drive voltage output terminals booster capacitor connection terminals for lcd osc1 crystal oscillation input terminal osc1 crystal oscillation output terminal osc3 ceramic or cr oscillation input terminal osc3 ceramic or cr oscillation output terminal terminal for setting mcu or mpu modes input terminals (k00?07) input terminal (k10) or event counter external clock input terminal (evin) input terminal (k11) or bus request signal input terminal (breq) output terminals (r00?07) or address bus (a0?7) output terminals (r10?17) or address bus (a8?15) output terminals (r20?22) or address bus (a16?18) output terminal (r23) or read signal output terminal (rd) output terminal (r24) or write signal output terminal (wr) output terminal (r25) or lcd synchronous signal output terminal (cl) output terminal (r26) or lcd frame signal (fr) output terminal * tout output is available for using as the e0c888xx. output terminal (r27) or programmable timer underflow signal output terminal (tout) output terminals (r30?33) or chip enable output terminals (ce0?e3) output terminal (r34) or clock output terminal (fout) output terminals (r35?37) output terminal (r50) or buzzer output terminal (bz) output terminal (r51) or bus acknowledge signal output terminal (back) * bz output is available for using as the e0c888xx. i/o terminals (p00?07) or data bus (d0?7) i/o terminal (p10) or serial i/f data input terminal (sin) i/o terminal (p11) or serial i/f data output terminal (sout) i/o terminal (p12) or serial i/f clock i/o terminal (sclk) i/o terminal (p13) or serial i/f ready signal output terminal (srdy) i/o terminal (p14) ,comparator 0 non-inverted input terminal or a/d converter input terminal i/o terminal (p15) ,comparator 0 inverted input terminal or a/d converter input terminal i/o terminal (p16) ,comparator 1 non-inverted input terminal or a/d converter input terminal i/o terminal (p17) ,comparator 1 inverted input terminal or a/d converter input terminal lcd common output terminals lcd common output terminals (when 1/32 duty is selected) or lcd segment output terminal (when 1/16 duty is selected) lcd segment output terminals initial reset input terminal test input terminal analog circuit system power supply (+) terminal analog circuit system power supply (? terminal analog circuit system reference voltage terminal serial data output terminal for flash programming serial data input terminal for flash programming serial clock i/o terminal for flash programming clock input terminal for flash programming test input terminal for flash programming flash test terminal (high voltage circuit monitor terminal ) notes: ? the pin assignment of the E0C88F360 (qfp18-176pin) is incompatible with the e0c883xx/e0c888xx. ?" * " indicates that the pin function of the e0c888xx differs from that of the e0c883xx. ? the flash memory in the E0C88F360 can be programmed with a single power source (4.5 v to 5 v).
E0C88F360 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ n epson electronic devices website

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