si9978 vishay siliconix document number: 70011 s-40804?rev. e, 26-apr-04 www.vishay.com 1 configurable h-bridge driver features h-bridge or dual half-bridge operation 20- to 40-v supply static (dc) operation cross-conduction protected current limit undervoltage lockout esd protected fault output description the si9978 is an integrated driver for an n-channel mosfet h-bridge. the mode control allows operation as either a full h-bridge driver or as two independent half-bridges. the dir/pwm input configuration allows easy implementation of either sign/magnitude or anti-phase pwm drive schemes for full h-bridges. schmitt triggers on the inputs provide logic signal compatibility and hysteresis for increased noise immunity. an internal low-voltage regulator allows the device to be powered directly from a system supply of 20 to 40 volts. all n-channel gates are driven directly from low-impedance outputs. the addition of one external capacitor per half-bridge allows internal circuitry to level shift both the power supply and logic signal for the high-side n-channel gate drives. internal charge pumps replace leakage current lost in the high-side driver circuits to provide ?static? (dc) operation in any output condition. protection features include an undervoltage lockout, cross-conduction prevention logic, and overcurrent monitors. the si9978 is available in both standard and lead (pb)-free, 24-pin wide-body soic (surface mount) packages, specified to operate over the industrial ( ? 40 to +85 c) temperature range. functional block diagram dir/in a qs/in b mode brk fault /fault a cl /fault b v+ gt a ? + il a + pwm/en b en/en a v dd r a /c a v dd input logic v dd v dd v dd v dd v dd v dd cap a cap b ? + il b + r b /c b 24 1 3 5 4 6 7 2 8 9 11 12 21 13 14 high-side u.v. lockout bootstrap reg. charge pump s a 22 gt b 17 bootstrap reg. charge pump s b 18 cap a 23 cap b 19 gb a 20 gb b 16 v dd v dd 15 gnd one shot one shot low-side u.v. lockout low-voltage regulator
si9978 vishay siliconix www.vishay.com 2 document number: 70011 s-40804?rev. e, 26-apr-04 absolute maximum ratings voltage on pins 2 ? 7 with respect to ground ? 0.3 to v dd + 0.3 v . . . . . . . . . . . voltage on pin 24 ? 0.3 to 50 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage on pins 17, 19, 21, 23 ? 0.3 to +60 v . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage on pins 18, 22 ? 2 to 50 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating temperature (t a ) ? 40 to +85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature ? 65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum junction temperature (t j ) 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation 500 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions v+ +20 to 40 v dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . r a , r b 100 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . specifications test conditions unless otherwise s p ecified limits ? 40 to 85 c parameter symbol unless otherwise specified v+ = 20 to 40 v min a typ b max a unit power supply voltage range v+ 20 40 v logic voltage v dd 14.5 16 17.5 v supply current i+ i dd = 0 ma 3 5 ma inputs (dir, pwm, en, qs, mode, brk) high-state v ih 4.0 v low-state v il 1.0 v high-state input current i ih v ih = v dd 10 a low-state input current i il v il = 0 v ? 100 ? 50 ? 25 a outputs low-side gate drive, high state v gbh 14 16 17.5 low-side gate drive, low state v gbl 1 v high-side gate drive, high state v gth s a b = 0 v 14 16 18 v high-side gate drive, low state v gtl s a, b = 0 v 1 low-side switching, rise time t rl 110 low-side switching, fall time t fl rise time = 1 to 10 v fall time = 10 to 1 v 50 high-side switching, rise time t rh fall time = 10 to 1 v c l = 600 pf 110 ns high-side switching, fall time t fh c l = 600 pf 50 break-before-make time 250 fault , cl v ol i ol = 1 ma 0.4 v fault , cl leakage current i oh fault , cl = v dd 0.2 10 a protection low-side undervoltage lockout uvll 0.8 v dd low-side hysteresis v h 0.8 v high-side undervoltage lockout uvlh s a, b = 0 v v dd ? 3.3 v current limit comparator input bias current i ib ? 5 ? 0.2 5 a comparator threshold voltage v th t a = 25 c 90 100 110 mv comparator threshold voltage v th 85 115 mv one shot pulse width t r a , r b = 100 k , c a , c b = 100 pf 8 10 12 s one shot pulse width t p r a , r b = 100 k , c a , c b = 0.001 f 80 100 120 s propagation delay t pd c l = 600 pf 600 ns notes: a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. b. typical values are for design aid only, not guaranteed nor subject to production testing.
si9978 vishay siliconix document number: 70011 s-40804?rev. e, 26-apr-04 www.vishay.com 3 truth table h-bridge mode mode dir/ in a en/ en a qs/ in b pwm/ en b brk il a + il b + gt a gb a gt b gb b cl / fault b fault/ fault a condition 1 1 1 1 0 l x h l l 1 1 1 1 1 0 0 l x l l 1 1 normal 1 0 1 1 0 l x l h l 1 1 normal operation 1 0 1 0 0 l x l l 1 1 1 x 1 x x 1 l x l h l h 1 1 brake 1 x 0 x x x l x l l l l 1 1 disable 1 x 1 x x 0 x l l l l overcurrent 1 x x x x x x x l l l l 1 0 undervoltage on v dd truth table half-bridge mode mode dir/ in a en/ en a qs/ in b pwm/ en b brk il a + il b + gt a gb a gt b gb b cl / fault b fault/ fault a condition 0 1 1 x 0 x l l h l l l 1 1 0 0 1 x 0 x l l l h l l 1 1 normal 0 x 0 1 1 x l l l l h l 1 1 normal operation 0 x 0 0 1 x l l l l l h 1 1 0 x 1 x x x x l l x x 1 overcurrent on a 0 x x x 1 x x x x l l 1 overcurrent on b 0 x x x x x x x l l l l 0 0 undervoltage on v dd
v dd v+ en/en a cap a dir/in a s a pwm/en b 21 gt a qs/in b mode brk gb a cap b s b cl /fault b gt b fault /fault a gb b nc gnd r a /c a il b + r b /c b il a + so-24 (wide body) 22 23 24 2 3 4 1 18 19 20 5 6 7 17 8 14 15 16 9 10 11 13 12 top view si9978 vishay siliconix www.vishay.com 4 document number: 70011 s-40804?rev. e, 26-apr-04 pin configuration and ordering information ordering information part number lead (pb)-free part number temperature range package si9978dw 40 to 85 c soic-24 si9978dw-t1 si9978dw-t1?e3 ? 40 to 85 c soic-24 (wide body) pin description pin 1: v dd v dd is an internally generated voltage. it is connected to this pin to allow connection of a decoupling capacitor. a minimum of 1 f is recommended. pin 2: en/en a the en input allows normal operation when at logic ?1?, and turns all gate drive outputs off when at logic ?0?. when the mode pin is at logic ?1?, en controls the entire h-bridge. when the mode pin is at logic ?0?, this pin becomes the enable pin for half-bridge a. pin 3: dir/in a the function of this pin is determined by the mode pin. when the mode pin is at logic ?1?, it is the dir pin, and when mode is at logic ?0?, it is the in a pin. as the dir input, it is the direction control for the h-bridge, and determines which diagonal pair of power mosfets is active. a logic ?1? turns on gt a and enables gb b , while a logic ?0? turns on gt b and enables gb a . when implementing an anti-phase pwm control, the dir input serves as the pwm input. as the in a pin, it is the input that controls the ?a? half-bridge. when at logic ?1?, the high-side mosfet is turned on, and when at logic ?0?, the low-side mosfet is turned on. pin 4: pwm/en b with the mode pin at logic ?1?, this pin is the pwm input. it controls the switching of the active diagonal pair. a logic ?1? turns the active mosfets on, while a logic ?0? turns it off. the qs input determines whether the bottom or both bottom and top mosfets are switched. when implementing an anti-phase pwm control, the pwm input is connected to a logic ?1?. when the mode pin is at logic ?0?, this pin becomes the enable pin for half-bridge b. pin 5: qs/in b with the mode pin at logic ?1?, this input determines whether the bottom mosfets of the h-bridge or both bottom and top mosfets switch in response to the pwm signal. a logic ?1? on this input enables only the bottom mosfets. this is the default condition as this pin is pulled up internally. when this pin is pulled to ground, both the bottom and top mosfets are enabled. this input controls the b half-bridge when the mode pin is at logic ?0?. when at logic ?1?, the high-side mosfet is turned on, and when at logic ?0?, the low-side mosfet is turned on.
si9978 vishay siliconix document number: 70011 s-40804?rev. e, 26-apr-04 www.vishay.com 5 pin description (contd) pin 6: mode this input determines whether the si9978 functions as an h-bridge or as two independent half-bridges. when the mode pin is at logic ?1?, the si9978 functions as an h-bridge, and when mode is at logic ?0?, it functions as two independent half-bridges. pin 7: brk when this input and mode are at logic ?1?, both bottom gate drives are switched high, turning on the bottom mosfets. when this input is at logic ?0?, the si9978 operates normally. pin 8: cl /fault b this is an open drain output which is active low. when the mode pin is at logic ?1?, this pin functions as cl and indicates that the h-bridge is in current limit. it stays low for the duration of the current limit one-shot. with the mode pin at logic ?0?, it serves as the fault output for half-bridge b to indicate when an undervoltage or overcurrent condition is detected. when indicating an overcurrent condition, the output stays low for the duration of the current limit one-shot. the fault output resets automatically when the condition clears. pin 9: fault /fault a this is an open drain output which is switched low when an undervoltage or overcurrent condition is detected. when indicating an overcurrent condition, the output stays low for the duration of the current limit one-shot. when the mode pin is at logic ?1?, this pin is the h-bridge fault output. with the mode pin at logic ?0?, it serves as the fault output for half-bridge a. the fault output resets automatically when the condition clears. pin 10: nc no internal connection. pin 11: r a /c a the timing resistor and ca pacitor for the current limit one-shot are connected to this pin. the values of the resistor and capacitor determine the off time set by the one-shot. the one-shot is triggered when the current limit comparator detects an overcurrent condition. pin 12: r b /c b the timing resistor and ca pacitor for the current limit one-shot are connected to this pin. the values of the resistor and capacitor determine the off time set by the one-shot. the one-shot is triggered when the current limit comparator detects an overcurrent condition. pin 13: il a + and pin 14, il b + these are the overcurrent sense inputs. internally, they are connected to the noninverting inputs of the current limit comparators. externally they are connected to the source(s) of the low-side mosfet(s) and the current sense resistor. pin 15: gnd the gnd pin is the ground return for v+ and the ground reference for the logic. also, this is the ground reference input for the current limit comparators and is connected to the ground side of the internal 100-mv references. this pin should be connected directly to the ground side of the current sensing resistors. pin 16: gb b and pin 20, gb a these pins drive the gates of the low-side power mosfets. pin 17: gt b and pin 21, gt a these pins drive the gates of the high-side power mosfets. pin 18: s b and pin 22, s a these are the source connections of the high-side power mosfets, the drain of the external low-side power mosfet, the negative terminal of the bootstrap capacitor, and the output for each half-bridge. pin 19: cap b and pin 23, cap a these are the connections for the positive terminals of the bootstrap capacitors c ba and c bb . a 0.01- f capacitor can be used for most applications. pin 24: v+ this is the only external power supply required for the si9978, and must be the same supply used to power the h-bridge it is driving. the si9978 powers the low-voltage logic, low-side gate driver, and bootstrap/ charge pump circuits from self-contained voltage regulators which require only a bootstrap capacitor on the cap pins. no voltage sensing circuitry monitors v+ directly; however, the low-voltage, internally generated supply and the bootstrap voltage (which are derived from v+) are directly protected by undervoltage monitors.
si9978 vishay siliconix www.vishay.com 6 document number: 70011 s-40804?rev. e, 26-apr-04 application circuit r 3 r 4 figure 1. basic h-bridge circuit 24 v+ v dd 1 en 23 cap a en/en a 2 dir 22 s a dir/in a 3 pwm 21 gt a pwm/en b 4 qs 20 gb a qs/in b 5 19 cap b mode 6 18 s b brk 7 brk 17 gt b cl /f b 8 cl 16 gb b f /f a 9 fault 15 gnd nc 10 14 il b + r a /c a 11 13 il a + r b /c b 12 u1 si9978 c 2 c 3 r 2 100 k c 8 v+ c 1 c 4 c 5 q 1 c 6 q 2 q 3 c 7 q 4 a out b out gnd r 1 little foot v cc
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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