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1/42 AN1262 application note may 2001 1 flyback basics flyback operation will be illustrated with reference to the basic circuit and the waveforms of fig. 1. it is a two- step process. during the on-time of the switch, energy is taken from the input and stored in the primary winding of the flyback transformer (actually, two coupled inductors). at the secondary side, the catch diode is reverse- biased, thus the load is being supplied by the energy stored in the output bulk capacitor. figure 1. flyback topology and associated waveforms. q clock ip is vdrain vin n vout dcm operation q clock ip is vdrain d ip ccm operation q clock ip is vdrain transition vin isolated feedback lp vout is l6590 l6590d l6590a clock + - drain gnd 1 1/100 s r q max. dut y c y cle oscillator driver rsense ocp + - 0.5 v + - e/a 2.5 v vfb comp frequency compensation vcc leb vac ls n:1 ip pwm clock by claudio adragna offline flyback converters design methodology with the l6590 family the design of flyback converters is quite a demanding task that requires smps engineers to cope with sev- eral problem areas such as magnetics, control loop analysis, power devices, as well as regulations concern- ing safety, emc and the emerging standby consumption requirements. lots of variable are involved and complex tradeoffs are necessary to meet the goal. in this scenario, the high-voltage monolithic switchers of the l6590 family greatly simplify the task and, at the same time, allow to build robust and cost-effective low-power systems. in this application note, after a review of flyback topology, a step-by-step design procedure of an offline sin- gle-output flyback converter will be outlined. as an example, the design of the test board will be carried out in details.
AN1262 application note 2/42 when the switch turns off, the primary circuit is open and the energy stored in the primary is transferred to the secondary by magnetic coupling. the catch diode is forward-biased, and the stored energy is delivered to the output capacitor and the load. the output voltage v out is reflected back to the primary through the turns ratio n (v r , reflected voltage) and adds up to the input voltage v in , giving origin to a much higher voltage on the drain of the mosfet. flyback is operated in dcm (discontinuous conduction mode) when the input -or primary - current starts from zero at the beginning of each switching cycle. this happens because the secondary of the transformer has dis- charged all the energy stored in the previous period. if this energy transfer is not complete, the primary current will start from a value greater than zero at the beginning of each cycle. then flyback is said to be operated in ccm (continuous conduction mode). dcm is characterized by currents shaped in a triangular fashion, whereas ccm features trapezoidal currents. the boundary between these two types of operation depends on several parameters. for a given converter, that is, as the switching frequency, inductance of the primary winding, transformer turns ratio and regulated out- put voltage are defined, it depends on the input voltage and the output load. at design time, whether the converter will be operated in ccm or in dcm and where the boundary will be located is up to the designer. usually ccm is selected with the objective of maximizing converter's power capab ility or minimiz- ing primary rms current. however, in ccm operation the system's dynamic behavior is considerably worse. usually, the converters based on the l6590 family devices are able to deliver the desired output power even with dcm operation, thus ccm will not be considered. table 1. converter specification data and pre-design choices converter electrical specification v acmin minimum mains voltage v acmax maximum mains voltage f l mains frequency (@ min. mains) n h number of holdup cycles v out regulated output voltage d v out% percent output voltage tolerance ( ) v r% percent output voltage ripple p outmax maximum output power h expected converter efficiency t amb maximum ambient temperature pre-design choices v r reflected voltage h t transformer efficiency v spike leakage inductance overvoltage v cc ic supply voltage v f secondary diode forward drop v bf bridge rectifier + emi filter voltage drop 3/42 AN1262 application note 2 converter electrical specification the starting point of the design procedure is the properties of the converter as a black-box, that is the set of data listed in the electrical specification table (table 1). additional requirements, such as efficiency at zero load or line/load regulation or maximum junction temperature, etc., can be added to that list and their impact will be con- sidered where appropriate. n mains voltage: range and frequency. there are basically the three possible options listed in table 2, where a variation of 20% is assumed, according to common practice. there are exceptions like some distribution lines rated at 277 v ac , where a 10% spread can be considered, or other special cases for specific applications. table 2 shows also the line frequency to be considered in the standard cases at the minimum specified mains voltages. an additional specification may require the converter to be shut down if the mains voltage falls below a "brownout level". this additional specification will be used for setting up the brownout protection on the types where it is available. table 2. mains voltage specifications n number of holdup cycles. the holdup requirement is the ability of the converter to keep the output volt- age in regulation even in case of mains interruption (missing cycles). this is usually specified in terms of number of mains cycles n h . this feature is not always demanded (in which case, n h = 0), otherwise the typical requirement is 1 mains cycle, that is n h = 1. it impacts on the input bulk capacitor selection. n output voltage tolerance. it can be expressed either in absolute value or as a percentage of the nominal voltage. this requirement, as well as the ones on line and load regulation, if specified, will affect the choice of the feedback technique (primary or secondary). n output voltage ripple. the ripple superimposed on top of the dc output voltage is specified as the peak- to-peak amplitude and includes both low frequency (at 2f l ) and high frequency (f sw ) component. switching noise due to parasitics of the printed circuit board and random noise are beyond the scope of this procedure. this requirement, if tight, may require the use of an additional filtering cell at the out- put. n converter efficiency. the efficiency is, by definition, the ratio of the output power to the input power. this figure is strongly dependent on the output voltage, because of the losses on the secondary diode. it should be set based on experience, using numbers of similar converters as a reference. as a rule of thumb, 75% ( h = 0.75) can be used for a low voltage output (3.3 v or 5 v) and 80% ( h = 0.8) for higher output voltages (12 v and above). 3 pre-design choices before starting the design calculations of the various parts of the converter, some parameters not defined at the "black-box level" need to be fixed. there is some degree of freedom in the selection of these parameters, pro- vided some constraints are taken into account. n reflected voltage. in principle, the reflected voltage should be as high as possible. in fact this leads to a greater duty cycle, which minimizes the rms current through the ic's mosfet for a given power throughput. there are two possible limitations to the maximum reflected voltage. one is the maximum duty cycle d max allowed by the devices (67% min.); some margin should be considered for load tran- sients, thus the reflected voltage should be such that the maximum duty cycle (at minimum input voltage input (v ac )v acmin (v ac )v acmax (v ac )f l (hz) 110 88 132 60 220 176 264 50 wrm (wide range mains) 88 264 60 AN1262 application note 4/42 and maximum output power) does not exceed 62-64%. the other limitation is that the sum of the max- imum input voltage, reflected voltage and overvoltage spike - due to the leakage inductance - must be below the breakdown of the internal mosfet (700 v min.). some margin needs also to be considered: at least 50v is recommended to take the forward recovery of the diode of the clamp circuit and param- eter spread into account. figure 2 illustrates schematically how the drain voltage is apportioned. the suggested value of v r is 130 v: it leads to a maximum drain voltage slightly exceeding 500 v in 220v ac or wrm applications, and about 320 v in 110 v ac application, thus leaving enough room for an efficient leakage inductance demagnetization (see below). the maximum duty cycle will be about 60% in 110v ac and wrm applications, and close to 36% in 220 v ac applications. figure 2. drain voltage composition. n leakage inductance overvoltage. the energy stored in the mutual inductance of the transformer at the primary side is not completely transferred to the secondary, after mosfet turn-off, until the leakage inductance is demagnetized. this delays and makes inefficient the energy transfer from primary to sec- ondary. to minimize this noxious effect the voltage across the leakage inductance (the leakage induct- ance spike) that resets the inductance itself should be as high as possible. obviously, this is limited by the maximum allowable drain voltage. with the reflected voltage selected as previously discussed, it is possible to allow about 140 v extra voltage in 220 v ac or wrm applications and much more in 110 v ac applications (see fig. 2). this will affect the design of the clamp circuit. n transformer efficiency. by definition, it is the ratio of the power delivered by the secondary winding to the power entering the primary. the secondary power includes the converter output power and the one dissipated in the secondary rectifier. besides the secondary one, the primary power includes the one dissipated inside the transformer and that not transferred to the secondary side and dissipated on the leakage inductance. for typical transformers used in converters based on the l6590 family ic's, typical values of efficiency ranges between 88% and 95%, depending on the power level and on the construc- tion technique. efficiency increases with the power level and by using winding interleaving construction technique. for consistency, check that the input power of the transformer be less than the converter input power. n device supply voltage. the supply voltage range of the ic spans from 7 to 16.5 v. such a wide range is envisaged to accommodate the variation that the voltage generated by the self-supply winding may vin v r v spike clamp diode forward recover y 700 v 374 v 187 v 504 v 317 v 650 v mar g in on off leak. inductance dema g netization current flows at the secondar y side prim. inductance resonates with drain capacitance leak. inductance resonates with drain capacitance transformer dema g netised 5/42 AN1262 application note experience in converters with opto-isolated feedback. this variation is a result of the poor magnetic cou- pling with the secondary winding. it is then recommended to design the turns ratio of the self-supply winding so as to get a voltage approximately in the middle of this range (e.g. 11-12 v). this will give allowance for increasing at heavy load and dropping at zero load. n secondary diode forward drop . the type of secondary diode will be selected basically depending on the output voltage. in fact this determines the maximum reverse voltage applied to the diode while the mos- fet is switched on. for low output voltages 15 v) a schottky diode can be used and a typical forward drop of 0.5v can be considered; for higher output voltages an ultrafast pn diode will be used, with a typical forward drop of 0.8 v. n bridge rectifier + emi filter voltage drop. this drop is subtracted to the peak of the input ac voltage and affects the peak voltage of the ripple superimposed on top of the dc voltage across the input bulk ca- pacitor. a typical value can be 3 v. 4 preliminary calculations (step 1) there are a few quantities that need to be calculated before starting the individual design of each functional block of the converter. they are summarized in table 3. table 3. preliminary calculations (step 1). 5 bridge rectifier selection due to the limited power range that the device is able to handle, no special considerations are needed to select the diodes of the bridge rectifier. any 1a rated standard diodes with 400/600 v reverse voltage are suitable. some man- ufacturers make integrated bridge rectifiers housed in small packages. see table 4 for some suggested parts. table 4. 1a standard silicon rectifier and bridge selection symbol parameter definition p in converter input power i out dc output current v pkmin minimum peak input voltage v pkmin = v acmin v pkmax maximum peak input voltage type part number rated voltage package manufacturer(s) diode 1n4004 400 do41 gi, gs, fagor, hta, on, tsc diode 1n4005 600 do41 gi, gs, fagor, hta, on, tsc bridge df04m 400 dil4 gi,tsc bridge df06m 600 dil4 gi,tsc bridge kbp104g 400 sil4 tsc bridge kbp105g 600 sil4 tsc bridge dfs04m 400 dil4 (smd) hta bridge dfs06m 600 dil4 (smd) hta p in p outmax h --------------------- = i out p outmax v out --------------------- = 2v bf C v pkmax v acmax 2 = AN1262 application note 6/42 6 input bulk capacitor selection the input bulk capacitor c in , along with the bridge rectifier, converts the ac mains voltage to an unregulated dc bus, v in , which is the input voltage for the downstream flyback converter. c in must be large enough to have a relatively low ripple superimposed on top of the dc level, as shown in fig. 3. at minimum specified mains volt- age, the value of c in determines the absolute minimum, v inmin , of the dc input voltage of the converter. the maximum duty cycle and the maximum peak current allowed by the ic must not be exceeded at this voltage. however, as to thermal consideration, the bus dc voltage (v dcmin @ v acmin ) should be considered. figure 3. input voltage waveforms: a) without holdup capability; b) with holdup capability. large values of c in result in higher v dcmin and v inmin , lower peak and rms current through the power mosfet (i.e. less power dissipation in the device) and less duty cycle range to achieve regulation but, on the other hand, also in bigger capacitor size, higher peak and rms current drawn from the mains (i.e. more power dissipation in the bridge rectifier). small values of c in give origin to the opposite situation. experience shows that a good compromise between these contrasting requirements is a c in value that causes the peak-to-peak ripple amplitude to be 25-30% of the peak mains voltage (@ v acmin ), which means that v inmin will be 70-75% of the peak value. anyway, if holdup capability is required, a much larger capacitance values will be needed: the voltage ripple across c in is expected to be 25-30% of the peak value, after 1 mains cycle miss- ing, which means that in normal operation the ripple will be much less. table 5 summarizes the required capacitance per watt of input power for a given value of v inmin , with and with- out holdup requirement, and shows the resulting values of v dcmin . this allows to calculate the minimum capac- itance needed, by multiplying the value taken from the table times p in . then a standard value will be selected, taking also the tolerance into account. a) v in v pkmin v inmin v dcmin t c 1 f l v in v pkmin v inmin after fail v dcmin t c after fail 1 missin g c y cle b) v inmin t c 7/42 AN1262 application note table 5. cin values for 1w input power the actual values of v inmin and v dcmin need to be recalculated with the actual capacitance value. since the evaluation of v inmin involves an equation having no closed form solution, an iterative cycle needs to be established: ; (1) where t c is the recharging time of c in , that is the time while the bridge diodes are conducting, which can be initially assumed equal to zero. after few iterations both v inmin and t c will converge to their respective values. in case of holdup requirement the cycle should be executed twice. the first time with n h = 1 to find v inmin after one mains cycle missing (which will be used to check for maximum duty cycle and maximum peak current) the second one with n h = 0 to find v inmin in normal operation (to be used for steady state and thermal calculations). v dcmin will be simply the average of v inmin (calculated with n h = 0 anyway) and v pkmin : (2) the voltage rating of c in is selected depending on v pkmax : it is usually 200 v for 110 v ac applications and 400v for 220 v ac or wrm applications. 7 preliminary calculations (step 2) the next step is to check for not exceeding the limits imposed by the ic. prior to this, the power processed by the transformer (p int ) and the average voltage drop across the on-resistance of the internal mosfet (v ds(on)x ) will be evaluated. v ds(on)x is subtracted to v inmin and the resulting value is the voltage actually applied to the primary winding of the transformer. the r ds(on) used must take temperature into account. use the max- imum value defined at 125c. the first limit to be checked is the maximum duty cycle d x . if it exceeds 62-64%, either the reflected voltage v r should be lowered or the minimum input dc voltage v inmin should be increased by selecting a larger input ca- pacitance. the second limit to be checked is the maximum drain voltage during the off-state of the mosfet. at least 50v margin should be ensured. the overvoltage spike can be reduced to allow more reflected voltage if neces- sary, keeping in mind that it cannot be much lower than v r not to hurt the primary-to-secondary energy transfer. the last check concerns the peak primary current that must not exceed the minimum guaranteed ocp threshold (0.55a). if this is exceeded, a higher maximum duty cycle d x should be used, if possible. also a higher v inmin is beneficial. some iterations, involving a recheck of the first two points, may be necessary to find the optimum compromise. if no solution can be found, either ccm operation should be considered or the power handled by the converter should be derated. 110 v ac or wrm 220 v ac n h =0 2.0 f/w 3.0 f/w 0.55 f/w 0.8 f/w v inmin = 90v v dcmin = 105v v inmin = 100v v dcmin = 110v v inmin = 180v v dcmin = 210v v inmin = 200v v dcmin =220v n h =1 7.2 f/w 10.4 f/w 1.8 f/w 2.8 f/w v inmin = 90v v dcmin = 116v v inmin = 100v v dcmin = 117v v inmin = 180v v dcmin = 236v v inmin = 200v v dcmin =239v v inmin v pkmin 2 p in c in -------- C 12n h + f l ------------------------- 2 C t c ? ?? = t c arccos v inmin v pkmin ------------------- ? ?? 2 p f l --------------------------------------------- = v dcmin 1 2 -- - v pkmin v inmin + () = AN1262 application note 8/42 all of the above mentioned calculation steps are summarized in table 6. table 6. preliminary calculations (step 2) 8 operating conditions @ v in = v dcmin from the thermal point of view the heaviest operating conditions for the ic, and for most of the other parts of the converter as well, are usually encountered at minimum input voltage. that is why the operating conditions @ v in = v dcmin need being evaluated. this will be done with the aid of the relationships in table 7. table 7. relationship useful for calculating converter's operating conditions @ v in = v dcmin symbol parameter definition p int transformer input power v ds(on)x max. average drop on r ds(on) in on-state d x maximum duty cycle v dsmax maximum drain voltage in off-state v dsmax = v pkmax + v r + v spike ip pkx max. peak primary current symbol description definition d duty cycle (switch on-time to switching period ratio) ip pk peak primary current ip pk = ip pkx ip dc dc primary current ip rms total rms primary current ip ac rms primary current (ac component only) d secondary diode conduction time to switching period ratio is pk peak secondary current is dc dc secondary current is dc = i out p int v out v f + () i out h t ------------------------------------------- = v ds on () v inmin v r + 1 v inmin v r p in r ds on () --------------------------------- - + ------------------------------------------- - ? d x v r v inmin v ds on () x C () v r + ----------------------------------------------------------------- = ip pkx p int v inmin v ds on () x C ---------------------------------------------- 2 d x ------- = d v inmin v ds on () x C v dcmin v ds on () x C ------------------------------------------------- = d x ip dc dip pk 2 ------------------- = ip rms ip pk d 3 --- - = ip ac ip rms 2 ip dc 2 C = d ' v dcmin v ds on () x C v r ------------------------------------------------- d = is pk 2i out d ' ---------------- - = 9/42 AN1262 application note once this information has been found, it is possible to evaluate the power dissipation of the ic and check for thermal limitations. table 8 summarizes the relationships that can be used for this evaluation. in those formulae: - t c is the crossover time of the voltage and current waveforms at mosfet's turn off; - c drain is the total capacitance of the drain, composed of the c oss of the mosfet, the parasitic capacitance of the primary winding and, in case, some external capacitance. as previously said, the worst-case operating conditions for the ic usually occur at v in = v dcmin , however it is worthwhile checking the losses also at maximum input voltage, that is at v in = v pkmax , especially if an external capacitor is added on the drain. with the worst-case total losses in the ic it is possible to find the maximum junction-to-ambient thermal resis- tance allowed for safe operation at maximum ambient temperature. the operating temperature range of the devices extends to 150 c, however designing for such high tempera- ture is not recommended. a reasonable target can be to design for 125 c maximum die temperature: (3) table 8. ic's power losses estimate with the aid of the diagrams shown in fig. 20 it is possible to estimate whether the required thermal resistance is feasible or not and, in the positive case, how large the on-board copper area is supposed to be. consider that copper areas larger than 4 cm 2 do not give significant reduction of thermal resistance and may cause pcb lay- outing to become a serious issue. if the thermal check does not give positive results, a different heatsinking strategy may be considered, otherwise a higher maximum duty cycle d x should be used, if possible, to reduce the rms current. also a higher v inmin symbol description definition is rms total rms secondary current is ac rms secondary current (ac component only) symbol description definition p cond conduction losses p sw switching losses p cap capacitive losses p q quiescent losses p q = v cc i op assume: r ds(on) max = 28 w (@ t j = 125 c) t c = 50ns f sw = 65khz c drain = 100pf i op = 7ma is rms is pk d ' 3 ----- = is ac is rms 2 is dc 2 C = r thmax 125 t amb C p q p cond p sw p cap +++ ----------------------------------------------------------------- = p cond ip rms 2 r ds on () max = p sw 1 3 -- - v in v r + () ip pk t c ? f sw p cap 1 2 -- - c drain v in v r + () 2 ? f sw table 7. (continued) AN1262 application note 10/42 (that is a larger input capacitor) is of help. some iterations, involving a recheck of the points mentioned in "pre- liminary calculations - step 2", may be necessary. if no solution can be found, either some specification should be relaxed or the power handled by the converter should be derated. 9 flyback transformer design to complete the set of data needed to design the flyback transformer, the primary inductance value (l p ) and the primary-to-secondary turns ratio (n) are still to be defined. the primary inductance will be chosen so that the converter is operated on the boundary between dcm and ccm at v in = v inmin : (4) while the primary-to-secondary turns ratio is defined so as to get the desired reflected voltage v r : (5) with the complete set of specification, the transformer design can start with the selection of the magnetic core material and geometry. table 9. ferrite materials selection as to the magnetic material, a standard soft ferrite for power applications (gapped core-set with bobbin) is the usual choice: the switching frequency is not so high thus special grades for high frequency operation are not required. table 9 shows some suitable materials. the geometry will be usually a popular e or e-derived type. other configurations, such as rm or pq cores, are not recommended because they are inherently high leakage geometries, since they result in narrower and thicker wind- ings. consider that minimizing leakage inductance is one of the major tasks in the design of a flyback transformer. among the various shapes and styles offered by manufacturers the most suitable one will be selected with technical and economic considerations. table 10 shows some possible choices with the relevant data useful for the design. the next quantity to be defined is the peak flux density b max which the transformer will be operated at. being this a dcm design, b max will also equal the maximum flux density swing d b max . grade saturation flux density [t] specific power losses @100 c [w/cm 3 ] manufacturer b2 0.36 thomson 3c85 0.33 philips n67 0.38 epcos (ex s+m) pc30 0.39 tdk f44 0.4 mmg lp v inmin v ds on ) x () C () d x [] 2 2f sw p int ------------------------------------------------------------------------- = n v r v out v f + ------------------------ - = p fe 1.15 10 5 C b 2.26 d f sw 1.11 = p fe 1.54 10 7 C b 2.62 d f sw 1.54 = p fe 8.53 10 7 C b 2.54 d f sw 1.36 = p fe 1.59 10 6 C b 2.58 d f sw 1.32 = p fe 2.39 10 6 C b 2.23 d f sw 1.26 = 11/42 AN1262 application note due to the moderate switching frequency, b max will be limited by core saturation and not by core losses. this means that transformer's power losses will be located mostly in the windings. as shown in table 9, ferrites saturate above 0.3 t thus a value of b max equal to 0.28-0.30 t may be selected to maximize core utilization, or b max = 0.25 t can be chosen for a more conservative design. this maximum peak flux density will occur when the peak primary current is maximum. however, it is not suffi- cient to consider the peak current ip pkx resulting from table 6. to guarantee that the transformer does not sat- urate even under short circuit conditions, the maximum peak primary current to be considered is the maximum value of the ocp threshold (i lim = 0.7a, from the datasheet). now a step-by-step procedure for the design of the transformer will be given. table 10. core list and significant design data 1) choose core size. transformer's core must be able to handle the power throughput p int without saturating and with acceptable power losses, with the minimum size. determining its optimum size is a trial-and-error process and a proper starting point may reduce considerably the number of iterations needed. a most common way of describing core size is the so-called area product (ap), which is the product of the effective cross-sectional area of the core times the window area available to accommodate the windings. it is possible to define the minimum ap required by a specific application. the following equation can be useful to estimate the minimum ap (in cm 4 ) required: core ve [cm 3 ] ae [cm 2 ] aw [cm 2 ] ap [cm 4 ] k1 k2 lt [cm] wb [cm] rth [c/w] thomson (b2) ef1505a 0.51 0.15 0.15 0.022 29.7 -0.68 2.63 0.92 75 ef2007a 1.46 0.31 0.26 0.081 61.1 -0.7 3.65 1.32 45 ef2509a 3.3 0.58 0.4 0.232 103 -0.73 4.64 1.64 30 e2006a 1.5 0.32 0.35 0.112 62.2 -0.7 3.9 1.18 46 e2507a 3.2 0.55 0.6 0.33 90 -0.73 5.2 1.54 40 philips (3c85) e16/8/5 0.75 0.201 0.216 0.043 42.2 -0.7 3.3 0.94 65 e20/10/6 1.49 0.32 0.35 0.112 62.2 -0.69 3.9 1.18 46 e25/13/7 2.99 0.52 0.56 0.291 90 -0.73 4.9 1.56 40 epcos (ex s+m) (n67) e16/8/5 0.76 0.2 0.22 0.044 42.2 -0.7 3.4 1 65 e20/10/6 1.49 0.32 0.34 0.109 62.2 -0.69 4.12 1.25 46 e25/13/7 3.02 0.52 0.61 0.317 90 -0.73 5 1.56 40 tdk (pc30) ei16-z 0.67 0.198 0.267 0.053 66 -0.57 3.31 0.86 44 ei22-z 1.63 0.42 0.2 0.084 85.4 -0.71 3.86 0.845 33 ei25-z 1.93 0.41 0.425 0.174 119 -0.57 4.94 0.98 31 mmg - neosid (f44) ef16 0.754 0.225 0.216 0.049 42.2 -0.7 3.3 1 65 ef20 1.5 0.314 0.348 0.109 62.2 -0.69 3.9 1.2 46 ef25 3.02 0.515 0.564 0.29 90 -0.73 4.8 1.6 40 AN1262 application note 12/42 (6) in this equation d t is the hot-spot temperature rise (located in the core center leg, where heat can be re- moved more difficultly), defined as d t = t max - t amb . for reliability reasons t max is usually limited at 100c where, by the way, ferrites usually feature minimum losses. k u is the window utilization factor, that is the por- tion of the total core window area occupied by the windings, which can be estimated equal to 0.4 for margin wound construction and to 0.7 for triple insulated wire construction. the smallest core with an ap greater then ap min will be chosen from the catalog data (the core list of table 10 can be used as a reference). if there is a core with an ap < ap min but very close to, it might be worthwhile trying to design with this smaller core before trying the larger one. 2) calculate the required minimum number of primary turns of the primary winding. it will be given by: 3) define primary and secondary windings' turns number. in the case of single-output under consideration, the secondary winding turns number ns will be simply: , that is, the result of the division will be rounded up to the next larger integer. the actual primary turns will then be calculated, rounding the result to the closest integer. np = [ns n + 0.5]. it can be convenient to round to the next even number when interleaved winding technique is to be used for transformer construction, so as to split the primary in two equal halves. 4) calculate the air gap length. the gap length (l g ) needed to get the desired inductance lp will be calculated with the following empirical formula: (7) if the calculated value is not available as a standard part, if possible, the primary turns number can be adjust- ed a little bit to get an off-the-shelf part. the air gap should be located on the core center leg only, to minimize radiated fields. in prototyping, center leg grinding to get nonstandard gap values can be avoided by keeping the two half-cores apart by about half the calculated value with spacers. 5) calculate transformer total losses. the allowed total transformer losses (p tot ) can be calculated by dividing the hot-spot temperature rise d t by the thermal resistance of the wound core r th(core) : if the manufacturer does not provide thermal data, r th(core) can be estimated. it has been shown [1] that there is a good correlation between core's area product and thermal resistance, regardless of its shape: r th(core) ? 23 ap -0.37 [c/w]; ap min 10 3 l p ip rms t 1 2 -- - d k u b max --------------------------------------- - ? ? ? ? ?? 1.316 cm 4 [] = np min lp 0.7 b max a e ------------------------ - 10 4 = n s np n ------- - 1 + = i g lp np 2 ---------- 10 9 k1 --------- ? ? ?? 1 k2 ------ mm [] = p tot t d r th core () ---------------------- - w [] = 13/42 AN1262 application note this best-fit equation refers to natural convection cooling. 6) calculate the actual flux swing, the actual core losses and the allowed copper losses. the flux swing will be given by: (8) and the corresponding core losses can be calculated with the formulae in table 9: (9) the allowed copper losses will obviously be: p cu = p tot - p fe [w] (10) 7) design windings. the goal is to find the right wire size so that copper losses are within the limit stated by (10). at this moment, losses due to skin and proximity effect will not be accounted for. the construction tech- nique of the transformer will be such that these effects will be minimized. copper losses will be equally apportioned to the primary and the secondary winding (the power handled by the auxiliary one is negligible). therefore the maximum primary and secondary winding resistance will be re- spectively: ; (11) the primary and secondary conductor copper cross-section area will be obtained considering the resistivity of copper at 100c ( r 100 = 2.30310 -6 w cm) and the average length-per-turn (4) of the bobbin associated to the selected core: (12) (13) a wire table (like the sample one shown in table 11) will be looked up and a wire with a copper area (ap cu , as cu ) equal or greater than the minimum above calculated will be selected. anyway, to minimize skin effect, the selected wire diameter should not exceed 2 d , where d is the skin depth of copper (about 0.3 mm at 65 khz and 100c). in practice, the maximum wire size for minimum skin effect is awg23 ( ? 0.57 mm, a cu = 0.2573 mm 2 ). if ap cu is larger, a number (nwp, nws) of such (or smaller) wires will be paralleled so as to achieve the desired total area: where the results will be rounded up to the next larger integer. b d lp lp pk np a e ---------------------- 10 4 t [] = p fe v e kb p d f sw q [w ] = rp p cu 2ip rms 2 ------------------------ [ w] = rs p cu 2is rms 2 ------------------------ [ w] = ap cumin r 100 np l t rp -------------------------------- - [cm 2 ] = as cumin r 100 ns l t rs -------------------------------- - cm 2 [] = nwp ap cumin ap cu ---------------------- - = nws as cumin as cu ---------------------- = AN1262 application note 14/42 table 11. wire table (rs-214). copper wire. heavy insulation. finally the total winding area must be checked to make sure they fit the bobbin window aw: api nwp np + as i nws ns k u aw (14) where api and asi are the individual wire cross-section, primary and secondary respectively, including isola- tion. if the above inequality is not verified there are the following options: a) if np is quite larger than np min , try decreasing np and go back to step 3; b) choose a smaller wire, recalculate nwp and nws and recheck window fitting; c) use fewer wires in a strand accepting a likely larger temperature rise; d) use the next size core and restart from step 2. finally, the auxiliary winding will be defined. it has not been considered before because it handles a very low power, thus it will be made with a single thin wire (e.g. awg32 or awg33) which gives a negligible contribu- tion to winding build and losses. just the turns number needs to be defined: (15) where 0.7 v is the typical forward drop on the auxiliary (small signal) diode. 8) calculate actual power dissipation and hot-spot temperature rise. the actual resistance of the primary and secondary windings has to be calculated first: ; , awg diameter copper [cm] diameter insulated [cm] area copper [cm 2 ] area insulated [cm 2 ] 22 0.064 0.071 0.003255 0.004013 23 0.057 0.064 0.002582 0.003221 24 0.051 0.057 0.002047 0.002586 25 0.045 0.051 0.001624 0.002078 26 0.040 0.046 0.001287 0.001671 27 0.036 0.041 0.001021 0.001344 28 0.032 0.037 0.000810 0.001083 29 0.029 0.033 0.000642 0.000872 30 0.025 0.030 0.000509 0.000704 31 0.023 0.027 0.000404 0.000568 32 0.020 0.024 0.000320 0.000459 33 0.018 0.022 0.000254 0.000371 n aux ns v cc 0.7 + v out v f + ------------------------- - = rp r 100 np l t nwp ap cu ------------------------------- = rs r 100 ns l t nws as cu ------------------------------ - = 15/42 AN1262 application note then the total power dissipation and the hot spot temperature rise will be respectively: finally, some suggestions on the transformer construction techniques. when building a transformer, the general rule is to minimize parasitics, basically leakage inductance and winding capacitance. in order for a transformer to meet isolation and safety norms, primary and secondary windings must be sepa- rated by isolation layers, thus their coupling cannot be intimate. moreover, in a margin wound construction the entire window breadth cannot be used (2.5 to 3 mm margin on each side must be considered to achieve suffi- cient creepage distance) thus the winding becomes shorter and thicker, which hurts coupling. this is why triple insulation construction is recommended. figure 4. interleaved winding technique as a result, it is not possible to reduce leakage inductance below a certain extent. practically, for a well assem- bled transformer, leakage inductance will be about 1 to 3% of the primary inductance. interleaved windings technique (putting on half the primary turns first, then the secondary and finally the other half of the primary, see fig. 4) may considerably reduce leakage inductance (theoretically almost four times). the two primary halves must be series connected, never paralleled. other tricks, such as spacing windings evenly across a layer (when they do not completely fill it), or using multiple strands of wire, or keeping isolation between windings to a minimum are also effective. besides, the use of split bobbins is not recommended. primary winding capacitance is the major component of the c drain capacitance earlier mentioned. besides con- tributing to internal mosfet power losses, it causes ringing and noise problems that may force the use of ad- ditional damping networks to comply with emc requirements. to achieve a low capacitance, always wind first the primary winding and, in particular, the half whose end is to be connected to the drain of the mosfet. in this way the second half primary has a shielding effect that reduces the capacitive coupling. in case of multiple layer windings, which exhibit higher capacitance, it is useful to embed one layer of isolation between two adjacent winding layers. this, however, tends to increase leakage inductance and therefore should be done with care. p tot p fe rp ip rms 2 rs is rms 2 + + = t d p tot r th = 1/2 primar y turns 1/2 primar y turns secondar y turns air g ap on centre le g AN1262 application note 16/42 10 clamp circuit design the drain pin of the ic needs to be properly clamped to prevent the spike due to the transformer leakage induc- tance from exceeding the breakdown voltage (700v minimum). an rcd clamp (see fig. 5a) is a popular cheap solution, however it dissipates power even under no-load conditions: there is at least the reflected voltage v r across the clamp resistor at all times. if minimizing the light load losses is a must, the use of a zener or transil clamp (see fig. 5b) is recommended whenever possible. such circuit gives also a better defined clamping level but dissipates more power at full load. figure 5. suggested clamp circuit topologies the clamp may not be necessary in a 110v ac operated converter but, before giving up this circuit, it is important to check carefully the spike under overload and start-up conditions to make sure that the voltage rating of the mosfet is never exceeded. rcd clamp . the clamp capacitor is charged by the energy stored in the leakage inductance and must ensure that the maximum allowed overvoltage v spike is never exceeded, even under short circuit conditions (when the peak primary current is i lim = 0.7 a). its minimum value will be then: the capacitor must be low-loss type (with polypropylene or polystyrene film dielectric) to reduce power dissipa- tion and prevent overheating due to the high peak currents it experiences. the minimum value of the clamp resistance is: , a ) r c d rcd clamp l6590 l6590d l6590a drain gnd b ) d zener clamp d z drain gnd l6590 l6590d l6590a c min l lk i lim 2 v r v spike + () 2 v r 2 C --------------------------------------------------- - = r min 1 f sw c min 1 v spike v r ---------------- + ? ?? ln ------------------------------------------------------------------- = 17/42 AN1262 application note and its power rating has to be: usually the resistor value will be selected much higher than the minimum to reduce losses. the clamp capacitor will then be quite larger than the minimum as well. the blocking diode must be not only very fast-recovery but also very fast-turn-on type to avoid additional drain overvoltage. a 1a rated diode with a breakdown voltage at least v pkmax + v r is needed. table 12 shows the suggested st parts. table 12. recommended st parts for blocking diode. zener clamp. the transil (or zener) clamp voltage should be equal to: v cl = v r + v spike (16) usually transils are rated by their stand-off voltage v rm at 25c temperature, which is defined at low current, whereas the desired clamp voltage is to be considered at operating junction temperature and i lim current. to take this into consideration, as a rule of thumb the stand-off voltage can be selected as high as 70% of the desired clamp level. please refer to [2] and [3] to see how these problems are handled. the transil or zener must have an adequate power handling capability in steady state operation: . table 13 lists some recommended devices available from st. the same recommendations as in the rcd clamp case apply to the blocking diode in series to the transil. only the breakdown voltage could be derated to v pkmax . table 13. recommended st parts for clamping. 110 v ac 220 v ac or wrm diode v rrm package diode v rrm package byt01-400 400 f126 stta106 600 f126 smbyt01-400 400 smb stta106u 600 smb v r pz 0.75 w pz = 1w pz = 1.5w 100 v bzw04-154 bzw06-154 smaj154a-tr bzw04-154 bzw06-154 smbj154a-tr p6ke180a 1.5ke180a smcj154a-tr 130 v bzw04-188 bzw06-188 smaj188a-tr bzw04-188 bzw06-188 smbj188a-tr p6ke200a 1.5ke200a smcj188a-tr p r v r 2 r min ------------ 1 2 -- - l lk i lim 2 f sw + = p z 1 2 -- - v cl v cl v r C ----------------------- - l lk i lim 2 f sw = AN1262 application note 18/42 11 secondary rectifier selection although the converter is operated in dcm, it is recommended to use an ultrafast p-n diode or, whenever al- lowed by the reverse voltage, a schottky type. the latter, besides optimizing the reverse recovery, minimizes conduction losses as well. the voltage rating will be higher than the maximum reverse voltage it experiences: , (17) with a suitable safety margin (usually 20-25%). as to its current rating, it is a common design practice to choose a diode rated for 2-3 times the dc output current i out . table 14 lists some recommended devices available from st assuming v r = 130 v. in each cell of the table there are two recommended devices, the first one is an axial or through-hole diode and the second one is in smd package. the sale types in italic are p-n diodes, the others are schottky type. table 14. recommended st parts for secondary rectification. 12 output capacitor selection and post filter large, low-esr electrolytic capacitors usually do the filtering work. the parameters to be considered for their selection are the working voltage, rms ripple rating and esr, the actual capacitance value is of secondary im- portance. obviously, the dc working voltage must be greater than v out . a margin of 25% is recommended for the sake of reliability. the ac current the output capacitor undergoes causes power dissipation on its esr and a resulting tempera- ture rise. this is the major responsible for capacitor degrading. thus it is important not to operate the capacitor beyond its ac current ripple rating, otherwise its lifetime will be considerably shortened. this parameter is usu- ally specified at 85c or 105c ambient temperature, depending on capacitor's quality. the value could be de- rated considering the actual maximum ambient temperature (t amb ) and the capacitor's target lifetime. for a conservative design no derating will be applied. the ac current capability must then be larger than is ac and 110 v ac 220 v ac or wrm v out (v) p out 5w p out =7.5w p out =10w p out 5w p out =7.5w p ou t =10w 3.3 1n5820 stps5l25b stps5l25b-1 stps5l25b stps10l25d stps10l25g 1n58210 stps3l25s stps5l25b-1 stps5l25b stps10l25d stps10l25g 5 1n5820 stps5l25b 1n5820 stps5l25b stps10l25d stps10l25g 1n5821 stps340c 1n5822 stps340b stps640ct stps640cb 9 1n5821 stps2l30a 1n5821 stps340b 1n5822 stps340b C stps160u C stps3l60s stps5h100-1 stps3l60s 12 1n5819 stps1l40a 1n5822 stps3l60s C stps3l60s C stps1h100u C stps2h100u stps5h100b-1 stps2h100u 15 byv10-60 stps160a byv10-60 stps160a C stps3l60s C stps1h100u C stps2h100u stps5h100b-1 stps2h100u 18 byv10-60 stps160a byv10-60 stps1h100u byw98-100 stps2h100u C stps1h100u C stps2h100u stps5h100b-1 stps2h100u 24 bat49 stps1h100a C stps1h100u C stps1h100u byw100-200 stpr120a byw100-200 stpr120a byw100-200 smbyw02-200 v rev v out 1 v pkmax v r -------------------- + ? ?? = 19/42 AN1262 application note may be achieved by using paralleled capacitors. esr, besides being responsible for capacitor heating, is what basically determines the switching frequency volt- age ripple superimposed on top of the dc value. this is true as long as the capacitive contribution to the ripple is negligible, that is if: (18) the specification on the maximum allowed output ripple is then translated into a requirement on the maximum esr of the capacitor: (19) anyway, once the specification on either the ac ripple current or the esr is fulfilled, the resulting capacitance value definitely meets condition (18). if the requirement on esr is very tight, there is an alternative to using a large number of output capacitors: it is possible to tolerate a higher ripple on c out (provided the ac ripple requirement is met) and add an lc post filter, like the one shown in fig. 6, that attenuates the ripple to the desired level. figure 6. output post filter for ripple reduction the attenuation factor of such filter is approximately given by: which is the same for complementary duty cycles and minimum for d=0.5. thus, to get the desired attenuation factor the following design equations can be applied: it is convenient to choose an off-the-shelf choke and then select a capacitor with an esr low enough to get the desired attenuation level. for low output current (less than 1 a) ferrite beads may be used. at any rate, the dc current rating of the choke should be oversized to minimize dc voltage drop. in fact, the feedback should be connected upstream the post filter to avoid stability problems (see "control loop compensation" section). c out > > 100 i out d x v r% v out f sw -------------------------------------- esrx v r% 100 --------- - v out is pk ----------- = l c out c' esr esr' d vo d v out post filter ka v out pp C d d v op p C ----------------------- d1d C () esr ' f sw l --------------- ? = ka esr ' 4f sw l ----------------------- for dx > 0.5 = ka dx 1 dx C () esr ' f sw l --------------- for dx < 0.5 = AN1262 application note 20/42 13 self-supply circuit design to define the self-supply circuit it is necessary to select the bias rectifier and the supply capacitor (see fig. 7) since the turns number of the auxiliary winding has been defined already. the bias rectifier has to withstand a reverse voltage equal to: with an appropriate safety margin of 20-25%. the current rating is of little concern since the diode has to carry few ma. a popular 1n4148 (75v rating) or an uf4003 (200v rating) may be suitable choices. the supply capacitor has to be large enough to keep the device running during the time needed for the auxiliary winding to develop its correct voltage at start-up. a minimum value of 10 f is recommended and any low cost electrolytic capacitor will do the job. the resistor rs in series to d filters the voltage spike appearing on the pos- itive-going edge of the voltage generated by the self-supply winding that causes the voltage vcc to increase with the converter's output load. the optimum value depends on the transformer's stray parameters (mainly the cou- pling between the auxiliary and the secondary winding) and can be found empirically once the transformer spec and construction have been frozen. a small and inexpensive axial inductor in the range of 1 to 10 m h may be used instead of r s , with even better results. figure 7. self-supply circuit 14 brownout protection design (l6590a and l6590d only) with reference to the schematic of fig. 8, the following relationships can be established for the on (v inon ) and off (v inoff ) thresholds of the input voltage: . solving for r1 and r2: for a proper operation of this function, v inon must be less than v pkmin and v inoff less than v inmin (see the timing diagram of figure 8). v rev v cc 1 v pkmax v r -------------------- + ? ?? = l6590 l6590d l6590a vcc d c n aux rs v inon r2 r1 r2 + ---------------------- 2.5, = v inoff 2.5 C r1 -------------------------------- - 50 10 6 C + 2.5 r2 ------- - = r1 v inon v inoff C 50 10 6 C ---------------------------------------- = r2 r1 2.5 v inon 2.5 C ------------------------------ = 21/42 AN1262 application note figure 8. brownout protection circuit and timing diagram 15 control loop design the control loop can be summarized as shown in figure 9, where each block is described by its transfer function in the complex frequency domain represented by means of a bode plot. figure 9. control loop block diagram the set pwm modulator + power stage is what, in control theory terminology, is called the "plant", while the compensated error amplifier is the "controller". + - l6590a l6590d 2.5 v vinok 50 a vin 6.4 v r1 r2 vcc v in v pkmin v inmin v inoff v inon vinok vcc pwm vout output divider + - vref vo compensated error amplifier v comp pwm modulator power stage g2 (j w ) vin d g1 (j w ) AN1262 application note 22/42 the transfer function g2(j w ) of the plant is defined by the control method (voltage mode), the topology of the converter (flyback) and its operating mode (dcm in the specific case). the task of the control loop design is then to determine the transfer function g1(j w ) of the error amplifier and define the relevant frequency compensation network. the objective of the design is to ensure that the resulting closed-loop system will be stable and well performing in terms of dynamic response, line and load regulation. the characteristics of the closed-loop system can be inferred from its open-loop properties. provided the open- loop gain crosses the 0 db axis only once at f= f c (crossover frequency), stability will be ensured if the gain phase shift (besides the 180 due to negative feedback) is less than 180 at f = f c . this is the well-known nyquist's stability criterion. anyway, adequate margin to this boundary condition must be provided to prevent instability due to parameter variations and to optimize the dynamic response that would be severely underdamped otherwise. under worst case condition this "phase margin" f m should never go below 20 or 30. typically, f m = 45 in nominal condi- tions is used as a design guideline: this ensures fast transient response with very little ringing. sometimes a higher margin (up to 60 or 75) is required to account for very large spreads in line, load and temperature changes as well as manufacturing tolerances. although nyquist's criterion allows the phase shift to be over 180 at a frequency below f c , this is not recom- mended because it would result in a conditionally stable system. a reduction of the gain (which may temporarily happen during large load transients) would cause the system to oscillate, therefore the phase shift should not get close to 180 at any frequency below f c . optimum dynamic performance requires a large gain bandwidth, that is the crossover frequency f c to be pushed as high as possible ( f sw /4). when optimum dynamic performance is not a concern, f c will be typically chosen equal to f sw /10. good load and line regulation implies a high dc gain, thus the open loop gain should have a pole at the origin. in this way the theoretical dc gain would tend to infinity, whereas the real-world one will be limited by the low- frequency gain of the error amplifier. since voltage mode control has poor open-loop line regulation, the overall gain should be still high also at frequencies around 100-120 hz to maximize rejection of the input voltage ripple. this is related to phase margin: a higher phase margin leads to a lower low-frequency gain. once the goal of the design has been established in terms of crossover frequency and phase margin, the next step is to determine the transfer function of the plant g2(j w ) in order to select an appropriate structure for g1(j w ). the transfer function g2(j w ) of the plant is described in tab. 15, while its asymptotic bode plot is illustrated in fig.10. in g2 0 definition the ratio d max /vs is the pwm modulator gain, while d max = 0.7 is the maximum duty cycle and v s = (3.5-1.5) = 2 v is the oscillator peak-to-valley swing (see the relevant section). r out = v out /i out is the equiv- alent load resistor. this kind of plant will be stabilized in closed-loop operation by what is commonly known as a type 2 amplifier. its transfer function g1(j w ), which comprises a pole at the origin and a zero-pole pair, is defined as: its asymptotic bode plot is illustrated in fig. 11. the main task of this correction is to boost the phase of the overall loop (actually, to reduce the phase lag of g2(j w )) in the neighborhood of the crossover frequency. g1 j w () g1 0 j w ---------- - 1 j w w z ------ - + 1 j w w p ------- + ----------------- = 23/42 AN1262 application note figure 10. plant transfer function g2(j w ) of dcm flyback (bode plots) table 15. plant transfer function and its main quantities figure 11. controller transfer function g1(j w ) (bode plots) symbol definition g2(j w ) g2 0 f esr f out gain [db] phase [] gain phase 0 -90 0 f out g2 0 f esr g2 j w () g2 0 1 j w w esr -------------- + 1 j w w out ----------- + ------------------------ = g2 0 d max v s ------------- - v in r out 2lpf sw --------------------------- = f esr w esr 2 p -------------- = 1 2 p esr c out -------------------------------------------- - = f out w out 2 p ----------- 1 p r out c out ----------------------------------- - == gain [db] phase [] gain phase 0 -90 0 f f z f p AN1262 application note 24/42 the synthesis of g1(j w ) can be done by following the following step-by-step procedure: a) calculate gain and phase of g2(j w ) at the desired crossover frequency (f c ). that is: ; g2(j w ) will be calculated at maximum input voltage and maximum load, where the gain-bandwidth product is maximum. b) calculate gain and phase of g1(j w ) at f = f c in order for the overall open-loop gain to cross the 0 db axis at f = f c with the phase margin f m : ; , c) cancel the pole of g2(j w ) by placing the zero of g1(j w ) in the neighborhood: ( a = 1 to 5) d) place the pole of g1(j w ) so as to get the desired phase margin: , e) calculate the unity gain frequency g1 0 : the synthesis of g1(j w ) is completed. the following step will concern the practical implementation of such func- tion, that is the realization of a type 2 amplifier. this will be done considering two cases, the secondary and the primary sensing feedback. 16 secondary feedback implementation this kind of feedback, shown in fig. 12, uses a popular arrangement with a tl431 as secondary reference/error amplifier and an optocoupler to transfer the control signal to the primary side. the error amplifier of the ic is then used as a current source whose characteristic is shown in fig. 12 as well: the voltage v comp is changed (and the duty cycle is controlled) by modulating the current ic sunk from the pin. a change of ic causes a change of v comp corresponding to a resistance r comp = 9 k w . the resulting transfer function is: and table 16 shows how its quantities are defined g2 c g2 2 p f c () = f 2 c 180 p --------- - g2 2 p f c () [] arg = g1 c g1 2 p f c () 1 g2 c ---------- - == f 1 c 180 p --------- - g1 2 p f c () [] arg 180 C f m f 2 c C + == f z w z 2 p ---------- - a w out 2 p ----------- == f p w p 2 p ---------- - = f c p 180 --------- - f 1 c ? ?? tan ------------------------------------------- ? g1 0 2 p g1 c f c f z f p ------------- ? g1 j w () v comp d v out d ---------------------- - v comp d i c d ---------------------- - i c d i f d -------- i f d v k d ---------- - v k d v out d -------------- - ctr max r comp r b r h c f ----------------------------------------------- 1 j w ----- 1j w r h r f + () c f + 1j w r comp c comp + --------------------------------------------------------------- - == = 25/42 AN1262 application note figure 12. secondary feedback: tl431 + optocoupler circuit (i) table 16. g1(j w ) implementation: secondary feedback (i) this technique provides very good regulation of the output voltage and galvanic isolation from the primary side at the same time. in table 16 it is possible to find the design relationships useful to derive the part values. icmax is specified in the datasheet (2.5ma). the following condition should be met: , (20) otherwise t will not be possible to find a positive value for r f . if the condition (20) is not met, an optocoupler with a narrower ctr min - ctr max spread should be selected. if that is not possible, either a higher f c or a lower f m should be selected and the calculations from step a) to step e) redone. symbol definition r l r l ? 0.27 to 2.7 [k w ] r h r b c f r f c comp vout r b r h r l tl431 c f l6590 l6590d l6590a comp v k i f i c c comp i c v comp 1.5 3.5 r comp = d v comp d i c 1 ma vfb not needed in the l6590a r f r h v out 2.5 C 2.5 ------------------------- r l = r b ctr min v out 3.5 C i cmax ------------------------- < c f ctr max r comp r b r h g1 0 ---------------------------------------------- - = r f 1 2 p f z c f ------------------------------- - r h C = c comp 1 2 p f p r comp -------------------------------------------- - = ctr max ctr min ---------------------- - g1 c p 180 --------- - f 1 c ? ?? tan r comp ------------------------------------------- v out 3.5 C i cmax ------------------------- AN1262 application note 26/42 figure 13. pwm gain reduction by r c (secondary feedback ii). a resistor r c in parallel to c comp , as shown in fig. 13, is useful to reduce the pwm gain d v comp / d i c . in fact, the resistor comes dynamically in parallel to r comp , thus reducing the equivalent value appearing at the numer- ator of the gain. moreover, since it diverts part of the current sourced by the pin comp, the opto's transistor carries less current and a slightly higher bias resistor r b can be used, thus giving some extra gain reduction. an additional resistor, r b1 , of some k w could be needed to guarantee sufficient bias to the tl431. to be able to exploit the full dynamics of the error amplifier under worst case conditions, r c must not be lower than 7 k w , which reduces the gain by a 1/0.35 @ 2.86 factor. r c values lower than 7 k w will reduce the gain further on but will reduce also the maximum duty cycle allowed (worst case). depending on the maximum duty cycle specified for a given application, this can be acceptable. table 17 summarizes the situation for different values of r c . table 17. pwm gain reduction for different r c values in this case the design procedure outlined in table 16 should be slightly modified as shown in table 18. r c (k w )r c // r comp (k w ) d max pwm gain reduction k b (r b multiplier) total gain reduction 7.5 4.09 0.7 2.2 1.24 2.73 7 3.94 0.7 2.29 1.25 2.86 6.8 3.87 0.68 2.32 1.25 2.91 6.2 3.67 0.62 2.45 1.27 3.11 5.6 3.45 0.55 2.61 1.28 3.34 5.1 3.26 0.49 2.76 1.29 3.58 4.7 3.09 0.44 2.91 1.31 3.8 4.3 2.91 0.38 3.09 1.32 4.07 3.9 2.72 0.32 3.31 1.33 4.4 3.6 2.57 0.28 3.5 1.34 4.69 vout r b r h r l tl431 c f l6590 l6590d l6590a comp v k i f i c c comp vfb not needed in the l6590a r f r c r b1 27/42 AN1262 application note table 18. g1(j w ) implementation: secondary feedback (ii) more flexibility is given by the network illustrated in figure 14, applicable with the l6590 and l6590d which have the error amplifier on board. for this circuit, to be able to find a positive value for r f , the condition is: , which is less stringent than (20). the resulting function is: , and table 19 shows how its quantities are defined. figure 14. secondary feedback: tl431 + optocoupler circuit (iii) symbol definition r l r l ? 0.27 to 2.7 [k w ] r h r c , k b select from table 17 r b c f r f c comp r h v out 2.5 C 2.5 ------------------------- r l = r b ctr min v out 3.5 C i cmax ------------------------- k b < c f ctr max r comp // r c () r b r h g1 0 ----------------------------------------------------------------- = r f 1 2 p f z c f ------------------------------- - r h C = c comp 1 2 p f p r comp // r c () -------------------------------------------------------------- - = ctr max ctr min ---------------------- - g1 c p 180 --------- - f 1 c ? ?? tan r f2 ------------------------------------------- 1 r c r e ------- + ? ?? v out 3.5 C i cmax ------------------------- g1 j w () v comp d v out d ---------------------- - v comp d v e d ---------------------- - v e d i c d ---------- - = i c d i f d -------- i f d v k d ---------- - v k d v out d -------------- - ctr max r e r f2 r e r c + () r b r h c f1 -------------------------------------------------------------------- 1 j w ----- 1j w r h r f1 + () c f1 + 1j w r f2 c f2 + ---------------------------------------------------------------- == vo ut r b r h r l tl431 c f1 l6590 l6590d vcc v k comp vfb r e r c r f2 c f2 i f i c v e r f1 AN1262 application note 28/42 table 19. g1(j w ) implementation: secondary feedback (iii) figure 15 shows a special configuration, with the optocoupler connected in series to the supply pin of the ic that provides the following benefits: a) a large range of the voltage generated by the auxiliary winding can be allowed since the changes are "damped" by the phototransistor and vcc is stabilized by the error amplifier; this is useful with a poor quality transformer or when the output voltage (tracked by the auxiliary voltage) may decrease because of constant current regulation (e.g. battery chargers, see fig.40 on l6590s datasheet). b) during overload and short circuit the power throughput is automatically reduced because the operation of the device becomes intermittent. in fact, the phototransistor carries the quiescent current i q of the ic and, if the output voltage is too low, there will not be enough current through the photodiode at the secondary side to maintain i q . the device will be switched off as it goes into uvlo. c) despite the ic's ovp protection is bypassed by such configuration, the system is still protected against op- tocoupler's failures: if that happens, the phototransistor will no longer be able to supply the ic, which will go into uvlo just like in case of overload or short circuit. the transfer function of the schematic of fig. 15 is: the v cc capacitor has a significant effect on the frequency characteristic of this circuit: in particular, it introduces a low-frequency pole that causes a phase lag noxious for the phase margin. this pole needs to be compensated by a zero, which requires an additional resistor (r c ) in series to the capacitor. the zero (r h1 + r f1 ) c f1 will be placed close to the pole due to the v cc capacitor, (r h2 +r c )c s so as to com- pensate it. the pole at the origin and the other zero-pole pair realize a type 2 amplifier (see table 20 to see how symbol definition r f2 ; r c ; r e r e > 1k w r l r l ? 0.27 to 2.7 [k w ] r h r b c f1 r f1 c f2 r f2 2k w > r c 2.5 r f2 < r h v out 2.5 C 2.5 ------------------------- r l = r b ctr min v out 3.5 C 2.5 ------------------------- r e < c f1 ctr max r e r f2 r e r c + () r b r h g1 0 -------------------------------------------------------------------- = r f1 1 2 p f z c f1 ---------------------------------- - r h C = c f2 1 2 p f p r f2 ----------------------------------- = g1 j w () v comp d v out d ---------------------- - v comp d v cc d ---------------------- - v cc d i c d -------------- - i c d i f d -------- i f d v k d ---------- - v k d v out d -------------- - = = = = ctr max r f2 r b ---------- 1 j w r h1 c f1 ----------------------------------- - 1j w r c c s + () 1j + w r h1 r f1 + () c f1 [] 1j + w r h2 r c + () c s [] 1j + w r f2 c f2 () ------------------------------------------------------------------------------------------------------------------------ . 29/42 AN1262 application note figure 15. secondary feedback: tl431 + optocoupler circuit (iv) table 20. g1(j w ) implementation: secondary feedback (iv) this network can be designed). the bias resistor of the photodiode will be selected so as to sustain the quiescent current of the l6590 and the current through the divider r h2 +r l2 . please note that the steady state supply volt- age vcc (used in table 20 to choose r l2 and r h2 ) has to be sufficiently higher than the uvlo threshold (say 3- 4 v, depending on c s ). in fact, the pwm starts only when the vcc voltage has decayed from the start-up thresh- old to the neighborhood of the steady state value. during this time the pwm is inhibited by the error amplifier, saturated low because the voltage at the pin v fb is higher than 2.5v. the turn number of the auxiliary winding will be such that the v ce across the phototransistor never falls below 1-2 v, to let it work in its active region. in case of constant current regulation, the variation of the output voltage symbol definition r l2 ; r h2 ; r f2 r f2 > 0.4 r h2 r l1 r l1 ? 0.27 to 2.7 [k w ]; r b r c c f1 r f1 c f2 l6590 l6590d vcc n aux r h2 r l2 r f2 vfb comp c f2 r c i c 470 nf cs tl431 vo ut r b r h1 r l1 c f1 v k i f r f1 r l2 15v v cc ----------- k w [] > r h2 v cc 2.5 C 2.5 ------------------------- r l2 = r h1 v out 2.5 C 2.5 ------------------------- r l1 = r b ctr min v out 3.5 C i q 2.5 r l2 --------- - + ------------------------- < r c 1 2 p f z c s -------------------------------- = c f1 ctr max r f2 r b r h1 g 10 ------------------------------------- - = r f1 r h2 r c + () c s c f1 ------------------------------------------ r h1 C = c f2 1 2 p r f2 f p ----------------------------------- = AN1262 application note 30/42 must be accounted for as well (the minimum specified value will be considered) and the turn number may result quite high. 17 primary feedback implementation in this approach, which will be considered with regards to the l6590 and the l6590d only, the voltage generated by the self-supply winding is sensed and regulated. this solution, shown in fig. 16, is cheap because no opto- coupler is needed, but provides poor regulation, especially as a result of load changes. ideally, the voltage generated by the self supply winding and the output voltage should be related by the n aux / ns turn ratio only. actually, numerous non-idealities, mainly transformer's parasitics, cause the actual ratio to deviate from the ideal one. line regulation is quite good, in the range of 2%, whereas load regulation is about 5%. output voltage tolerance is instead in the range of 10%. the resulting transfer function is: table 21 shows how its quantities are defined. as to the selection of vcc, the same considerations concerning the circuit of fig. 15 apply to the circuit in fig. 16a. such limitation is not in the circuit of fig. 16b. figure 16. primary feedback: circuits table 21. g1(j w ) implementation: primary feedback the value of the resistor rs (rs for the circuit of fig. 16b) in series to the bias diode will be selected to achieve minimum load regulation and its value may range from few units to some hundred ohm. symbol definition r l r h c fp c fs r f g1 j w () v comp d v out d ---------------------- - n aux n s ------------ v comp d v cc d ---------------------- - = n aux n s ------------ 1 r h c fs c fp + () ------------------------------------------- - 1 j w ----- 1j + w r f c fs 1j + w r f c fs c fp c fs c fp + -------------------------- - ---------------------------------------------------------- - . == a ) b ) l6590 l6590d vcc n aux r h r l r f c fs r s vfb comp c fp 22 f l6590 l6590d vcc n aux r h r l r f c fs r' s vfb comp c fp r s 22 f 220 nf r l 15 v v cc ----------- k w [] > r h v cc 2.5 C 2.5 ------------------------- r l = c fp n aux n s ------------ f z f p ---- - 1 g1 0 r h ----------------------- = c fs c fp f p f z ---- - 1 C ? ?? = r f 1 2 p f z c fs ---------------------------------- - = 31/42 AN1262 application note the optimum value will be found empirically once the transformer construction has been frozen. also the divider r h , r l that sets the v cc voltage (and as a consequence, the output voltage) is likely to need adjustment after bench verification. some improvement in terms of load regulation can be achieved by using an inductor (typi- cally, between 1 and 10 m h) instead of a resistor. any inexpensive axial inductor able to carry few ma will serve the purpose. figure 17. leading edge blanking (leb) circuit for leakage inductance spikes filtering however, the most effective way to improve regulation is to use the circuit shown in figure 17, which blanks the spike appearing at the leading edges of the voltage generated by the self-supply winding. this spike, due to the transformer's leakage inductance, is the major responsible for the poor load regulation. 18 layout recommendations a proper printed circuit board (pcb) layout is essential for correct operation of any switch-mode converter and this is true for the devices of the l6590 family as well. careful component placing, correct traces routing, appro- priate traces widths and compliance with isolation distances are the major issues. figure 18. suggested ground routing for converters with secondary feedback. vcc gnd l6590 l6590d l6590a 1n4148 bc327 10 k w 100 pf 22 f iout [a] vout [v] 0.01 0.1 1 11 12 13 14 15 16 17 18 rs leb vin vout l6590 l6590d l6590a drain gnd comp vcc vac vfb primar y power gnd secondar y si g nal gnd primar y si g nal gnd one-point gnd bok secondar y power gnd l6590a and l6590d onl y l6590 and l6590d onl y c y1 AN1262 application note 32/42 some fundamental rules will be given to enable the designer to successfully produce a good layout. all of traces carrying high currents, especially if pulsed (the bold ones in figures 18 and 19), should be as short and fat as possible. this will keep both resistive and inductive effects to a minimum, in favor of efficiency as well as radiated rfi. if a two layer pcb is used, some of these traces could be routed parallel on both sides. noise coupling and radiation will also be reduced by minimizing the area circumscribed by current loops where high pulsed currents flow, that is the bolded ones in figures 18 and 19. the most critical loop is that including the input bulk capacitor, the transformer and the l6590, thus these components should be next to one other. in figure 20 an example of possible component placement is given. figure 19. suggested ground routing for converters with primary feedback current returns (or ground) routing is also very important. all of them (signal ground, power ground, shielding, etc.) should be routed separately and should be connected only at a single ground point, as suggested in figures 18 and 19. generally, traces carrying signal currents should run far from others carrying pulsed currents or with quickly swinging voltages like the bolded ones of figures 18 and 19. from this viewpoint, particular care should be taken of the feedback path. in case of two layer pcb, it is a good practice to route signal traces on one pcb side and power traces on the other side. some crucial points of the circuit need or may need filtering, such as the v cc pin or the bok pin. in case, high- frequency filter capacitors (with plastic film or ceramic dielectric) should be placed between these pins and the "signal ground" route, as close to the ic as possible. reduction of common mode emissions requires a y1 class capacitor (or two series connected y2 class ones) connected between the primary and secondary ground. this decoupling capacitor should be connected as close to the transformer as possible. another important point is related to creepage distance: this must be observed between primary and secondary ground (8mm), between the phases of the input voltage (4 mm) and the opposite ends of the primary winding of the transformer (4mm). concerning the primary-to-secondary ground separation, no component or traces vin vout l6590 l6590d drain gnd vcc vac vfb primary power gnd primary signal gnd one-point gnd bok secondary gnd l6590d only c y1 33/42 AN1262 application note must be placed in this region, except the above mentioned common mode suppression capacitor and any op- tocoupler for secondary feedback. filling any unused space in the pcb with a ground plane helps reduce noise emission, but does not exempt from using the above mentioned care in component placing and traces routing. for instance, if a signal ground is connected to a ground plane along a pulsed current path between two components, (it is usually the most direct one) noise will be injected into the signal circuitry. figure 20. possible component placement. 19 test board: design and evaluation in order to show how to proceed with the design of an application based on the l6590 family, the design of the test board, used to evaluate the device's performance, will be illustrated in details. finally, the resulting electrical schematic and a bench evaluation of the test board will be presented. the electrical specifications of the test board and some preliminary choices are listed in table 22. table 23a) shows the results of some preliminary calculations needed to go further with the design steps. table 22. test board's electrical specification and pre-design choices electrical specification v acmin 88 v minimum mains voltage v acmax 264 v maximum mains voltage f l 60 hz mains frequency (@ min. mains) n h 0 number of holdup cycles v out 5 v regulated output voltage d v out% 2 % percent output voltage tolerance ( ) v r% 1 % percent output voltage ripple p outmax 10 w maximum output power h 0,75 expected converter efficiency t amb 40 maximum ambient temperature + to input brid g e si g nal g round + jumper transformer cin c y l6590 l6590d c suppl y zener clamp AN1262 application note 34/42 bridge rectifier selection. an integrated bridge (df06m, 4x1a/600v, gi) has been selected. input bulk capacitor. from table 5, in order for the valley voltage on the input cap to be around 90 v, a minimum capacitance of about 27 f should be used. a standard 22 f/400v electrolytic capacitor will be chosen. after few iterations, the (1) cycle converges at v inmin = 84.9v, t c = 2.11 ms. from eqn. 2, v dcmin = 103.2 v. table 23b) shows the results of a second step of calculations, aimed at checking that no limit of the device is violated. the result is ok. operating conditions @ v in = v dcmin and thermal check. the results are listed in table 23c). with these data the power dissipated by the l6590 is calculated and the result is shown in table 23d). from eqn. 3, the maximum junction-to-ambient thermal resistance needed for reaching thermal balance at tj = 125 c is 51.2 c/w. from the diagrams of fig. 21 it is possible to see that this can be obtained with about 1 cm 2 copper area on the pcb. figure 21. l6590 family packages junction-to-ambient thermal resistance pre-design choices v r 120 v reflected voltage h t 0,9 transformer efficiency v spike 80 v leakage inductance overvoltage v cc 12 v l6590 supply voltage v f 0.6 v secondary diode forward drop v bf 3 v bridge rectifier + emi filter voltage drop so16w rthja vs. pcb copper area pdiss = 1.4 w 0.511.522.533.544.5 46 48 50 52 54 56 [cm^2] [c/w] 1 oz 2 oz minidip rthja vs. pcb copper area pdiss = 1.4 w 0.511.522.533.544.5 46 47 48 49 50 51 52 [cm^2] [c/w] 1 oz 2 oz table 22. (continued) 35/42 AN1262 application note table 23. test board design calculations results. a) preliminary calculations results (step 1) symbol parameter value p in converter input power 13.33 w i out dc output current 2 a v pkmin minimum peak input voltage 121.5 v v pkmax maximum peak input voltage 373.4 v b) preliminary calculations results (step 2) v inmin absolute minimum input dc voltage 84.9 v v dcmin minimum input dc bus voltage 103.2 v p int transformer input power 12.44 w v ds(on)x max. average drop on r ds(on) in on- state 7.24 v d x maximum duty cycle 0.607 v dsmax maximum drain voltage in off-state 573.4 v i ppkx max. peak primary current 0.528 a c) operating conditions @ vin = v dcmin v ds(on) average drop on r ds(on) in on-state 7.24 v d duty cycle (switch on-time to switch- ing period ratio) 0.496 ip pk peak primary current 0.528 a ip dc dc primary current 0.131 a ip rms total rms primary current 0.215 a ip ac rms primary current (ac component only) 0.170 a d secondary diode conduction time to switching period ratio 0.397 is pk peak secondary current 10.08 a is dc dc secondary current 2 a is rms total rms secondary current 3.67 a is ac rms secondary current (ac compo- nent only) 3.08 a d) device power dissipation @ vin = v dcmin p cond conduction losses 1.29 w p sw switching losses 0.13 w p cap capacitive losses 0.16 w p q quiescent losses 0.08 w p tot total losses 1.66 w r thj-amb maximum junction-ambient thermal resistance 51.2 c/w AN1262 application note 36/42 flyback transformer design eqn. 4 gives the primary inductance (lp = 1.37 mh, rounded up to 1.4 mh), while eqn. (5) gives the primary-to- secondary turns ratio (n = 21.4). the design will be done considering philip's e-cores in 3c85 ferrite and as- suming a maximum peak flux of 0.25t, a temperature rise of 40 c and 40% window utilization factor. going step-by-step: 1) eqn. 6 provides a minimum ap of 0.042 cm 4 . table 10 shows that an e20/10/6 core could fit the design. 2) the primary turns number will be np min = 122.5. 3) the resulting secondary turn number will be 122.5/21.4=5.7 which will rounded up to 6. the primary turns number will then become 621.4=128.4. finally, the choice will be np=128 turns and ns=6 turns, which yields an actual turns ratio of 128/6 = 21.33, very close to the target. 4) from eqn. 7, the air gap needed to get the desired value of lp will be 0.63 mm. 5) table 10 shows that the thermal resistance of the finished core is 46 c/w, thus the maximum power dissi- pation inside the transformer shall not exceed 40/46 = 0.87 w. 6) equations 8, 9 and 10 will provide the actual flux swing (which will be lower than 0.25 t because np>npmin), the actual core losses and the allowed copper losses respectively. the resulting flux swing is d b=180 mt: the relevant core losses amount at 66 mw, thus it is possible to dissipate up to 0.8 w in the windings. 7) the required primary and secondary winding resistance will be 8.65 w and 30 m w respectively (resulting from eqns. 11). the resulting primary resistance is quite high and the drop across it reduces significantly the actual voltage applied at the primary inductance. the target primary resistance is then reduced at 4 w and the secondary will be increased at 46m w to maintain the same total copper losses. the required primary and secondary copper area will be 2.8710 -4 cm 2 and 1.210 -3 cm 2 respectively (eqns. 12, 13). table 11 shows that this can be done with one awg32 wire at the primary and four paralleled (twist- ed) awg32 wires at the secondary. this will both minimize high frequency effects and simplify the bom. the total occupied area will be 7 mm 2 (eqn. 14), 20% of the total available area, thus the windings will fit. on top of the primary and secondary winding, 14 turns of awg32 wire will be wound to make the auxiliary winding (eqn. 15). 8) the actual resistance of the primary and secondary windings will be 3.6 w and 42 m w respectively, for total copper losses of 0.73 w. the total losses will be about 0.8 w and the resulting temperature rise 36.8 c. zener clamp to optimize losses at light load a zener clamp will be used. the clamp voltage should be around 200 v (eqn. 16), thus a bzw06-154 is first selected. assuming a leakage inductance of 30 h (about 2% of the primary inductance), power dissipation will be about 0.6 w in normal operation and about 1.1 w in overcurrent limitation. the relevant clamping voltages would be 196 v and 209 v respectively. the initial choice will then be confirmed. an stta106 (1a / 600v turboswitch diode) will be used as the blocking diode. secondary rectifier according to eqn. 17, and considering 25% margin, the blocking voltage of the diode should exceed 28 v, while its current rating should be in excess of 4 a. although table 14 suggests a bigger device, an 1n5822 (3a/40v) schottky diode is selected for this test board. 37/42 AN1262 application note output capacitor capacitor's ripple current rating should exceed 3 a. the minimum capacitance value should be 373 f (eqn. 18) and the maximum esr should be less than 5 m w . for long-time reliability the capacitor(s) should also be able to withstand at least 3.08 a current ripple. three rubycon's zl series 470 f/16v paralleled capacitors were selected, for a total ripple capability of nearly 3 a and a total esr of about 20 m w . to meet the requirement on the output voltage ripple an lc post filter is needed that attenuates ripple at least four times. choosing a standard value of l = 4.7 h, the maximum esr of the additional capacitor should not exceed 300m w . an additional 220 f/10v zl capacitor has been added. self-supply circuit the self supply circuit will include an 1n4148 diode and a 22 f supply capacitor. a 10 w resistor will be added in series to the diode to reduce vcc voltage variations with the load current. this value is likely to be adjusted after bench verification. control loop design the crossover frequency will be selected as high as 10 khz, worst case. the objective will be to get 70 phase margin. the plant transfer function is: with g2o = 11.5, f esr = 5464 hz, f out = 90.3 hz (@ max. load and max. v in ). a type 2 amplifier will be used for g1(j w ). going step-by-step: a) the gain and phase of g2 at f=10 khz are 0.281 and -29 respectively; b) in order for the overall open-loop gain to cross the 0 db axis at f=10 khz with 70 phase margin, the gain and phase of g1(j w ) will be 3.56 and -81 respectively; c) the compensating zero will be placed at 360 hz ( a = 4, to maximize 100hz gain); d) the compensating pole will be placed at 2270 hz; e) the unity gain factor is 35.410 4 s/rad. since a tight tolerance on the output voltage is required, an optoisolated feedback will be used and g1(j w ) will be realized with the schematic of figure 13. the tl431 and an optocoupler pc817a from sharp will be used. the ctr is specified between 0.8 and 1.6. using a 6.8k w resistor as r c , the resulting part values are: r l = r h = 2.43 k w ; r b = 560 w ; r f = 2k w ; c f = 100 nf; c comp = 22 nf. electrical schematic, bom and evaluation results in fig. 22 the electrical schematic of the test board is illustrated and table 24 lists the relevant bom. the dia- grams of figure 23 show the evaluation results of the board, figure 24 shows some typical waveforms and figure 25 the effect of the frequency change on the output voltage transient. g2 j w () g2 0 1 j w w esr -------------- + 1 j w w out ----------- + ------------------------ = AN1262 application note 38/42 figure 22. test board electrical schematic table 24. test board bill of material symbol value notes r1 10 w ? w, 5% r2 6.8k w ? w, 1% r3 560 w ? w, 1% r4, r6 2.43k w ? w, 1% r5 2k w ? w, 1% c1 22 f 400 v, electrolytic, elna re3 or equivalent c2 22 f 25 v, electrolytic c3 22 nf plastic film c4 2.2 nf 250v y class c5, c6, c7 470 f 16 v, electrolytic, rubycon zl or equivalent c8 220 f 10 v, electrolytic, rubycon zl or equivalent c9 100 nf 10v electrolytic l1 4.7 h uk ltd., elc8d4r7e d1 bzw06-154 154v / 600w peak transil, st 3 1 5 4 6, 7, 8 5 vdc / 2 a c2 c4 c8 r3 r4 d1 d3 d4 op1 l6590 ic1 4 3 1 2 3 c5 r1 c3 r6 l1 t1 d2 c6 bdg vinac 88 to 264 v c9 2 1 ic2 c7 r5 r2 c1 f1 39/42 AN1262 application note figure 23. test board evaluation results symbol value notes d2 stta106 1a / 600v turboswitch, st d3 1n4148 d4 1n5822 3a / 40v schottky, st ic1 l6590 monolithic hv switcher, st op1 pc817a optocoupler, sharp bd1 df06m gi, or equivalent 1a, 600 v t1 --- core e20/10/6, 3c85 ferrite, philips or equivalent ? 0.6 mm air gap for a primary inductance of 1.4 mh (l lk <30 h) pri: 64t+64t, series conneceted, awg32 ( ? 0.22 mm) sec: 6t, 4xawg32 ( ? 0.22 mm) aux: 14t, awg32 ( ? 0.22 mm) f1 t2a250v 2a, 250v elu test board load & line regulation 0.003 0.01 0.03 0.1 0.3 1 3 4.9 4.92 4.94 4.96 4.98 5 load current [a] output voltage [v] 264 v ac 88 v ac 110 v ac 220 v ac test board efficiency 0.003 0.01 0.03 0.1 0.3 1 3 20 30 40 50 60 70 80 load current [a] efficiency [%] 88 v ac 264 v ac 220 v ac 110 v ac test board light-load consumption 50 100 150 200 250 300 350 400 450 0 200 400 600 800 1,000 dc input voltage [v] input power [mw] p out 0.5 w 0.25 w 0.1 w 0.05 w 0 w device power dissipation rth j -amb= 58 c/w @ 1.5w 0.003 0.01 0.03 0.1 0.3 1 3 0.05 0.1 0.2 0.5 1 2 5 load current [a] device dissipation [w] 88 v ac 110 v ac 264 v ac 220 v ac table 24. (continued) AN1262 application note 40/42 figure 24. test board main waveforms under different operating conditions figure 25. test board load transient response; effect of frequency change (left). 20 references [1] lloyd h. dixon, jr. "filter inductor and flyback transformer design for switching power supplies", uni- trode power supply design seminar manual, 1994 (sem-1000) [2]"calculation of transil apparent dynamic resistence" (an575) [3]"transistor protection by transil" (an587) [4]"getting familiar with the l6590 family high-voltage fully integrated power supply" (an1261) a1: idrain ch1: vdrain vin = 100 v iout = 2 a vin = 100 v iout = 50 ma a1: idrain ch1: vdrain vin = 400 v iout = 2 a vin = 400 v iout = 50 ma a1: idrain ch1: vdrain a1: idrain ch1: vdrain vin = 200 v iout = 0.2 ? 0.4 a vout iout vin = 200 v iout = 0.1 ? 0.3 a vout iout transition 22 t 65 khz transition 65 t 22 khz 41/42 AN1262 application note summary 1 flyback basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 converter electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 pre-design choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 preliminary calculations (step 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 bridge rectifier selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 input bulk capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 preliminary calculations (step 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 operating conditions @ v in = v dcmin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 flyback transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 clamp circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11 secondary rectifier selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12 output capacitor selection and post filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13 self-supply circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14 brownout protection design (l6590a and l6590d only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 15 control loop design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16 secondary feedback implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 17 primary feedback implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18 layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 19 test board: design and evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 20 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 42/42 AN1262 application note |
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