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general description the DS4426 contains four i 2 c-adjustable current dacs capable of sinking or sourcing current. external resis- tors set the full-scale range of each output. each dac output has 127 sink and 127 source steps that are pro- grammed by the i 2 c interface. power-supply tracking functionality is provided for three channels using dedi- cated control inputs. once power-supply tracking is accomplished, the current outputs default to zero. two address pins allow up to four DS4426 devices to exist on the same i 2 c bus. applications power-supply adjustment power-supply margining power-supply tracking adjustable current sink or source features ? four current dacs 50? to 200? adjustable full-scale range 127 settings each for sink and source ? power-supply tracking power-supply sequencing ramp-up and ramp-down tracking control ratiometric tracking support ? +2.7v to +5.5v operation ? i 2 c-compatible serial interface ? two address input pins allow up to four devices on same i 2 c bus ? lead-free, 28-pin tqfn package (4mm x 4mm) with exposed pad ? industrial temperature range: -40? to +85? DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking ________________________________________________________________ maxim integrated products 1 26 27 25 24 10 9 11 scl out0 out1 out2 out3 12 sda thr1 dnc thr3 fs0 inn3 inp3 12 gain3 4567 20 21 19 17 16 15 gain2 gain1 inn1 inp1 a1 a0 v cc thr2 3 18 28 8 n.c. gnd fs3 23 13 inp2 fs2 22 14 inn2 fs1 thin qfn (4mm ) top view DS4426 *ep *exposed pad. + pin configuration ordering information 19-4541; rev 0; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part temp range pin-package DS4426t+ -40c to +85c 28 tqfn-ep* DS4426t+t&r -40c to +85c 28 tqfn-ep* functional diagram appears at end of data sheet.
DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking 2 _______________________________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on sda, scl relative to gnd ......-0.5v to +6.0v voltage range on v cc relative to gnd ...............-0.5v to +6.0v voltage range on a0, a1, fs[3:0], gain[3:1], inn[3:1], inp[3:1], and thr[3:1] relative to gnd ......................................-0.5v to (v cc + 0.5v)* operating temperature range ...........................-40 c to +85 c storage temperature range .............................-55 c to +125 c soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.7 5.5 v input logic 1 (sda, scl, a0, a1) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl, a0, a1) v il -0.3 0.3 x v cc v full-scale resistor values r fs[3:0] (note 2) 40 160 k dc electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units supply current i cc v cc = +5.5v (note 3) 0.9 ma input leakage current (sda, scl) i il v cc = +5.5v -1 +1 a rfs voltage v rfs t a = +25c 0.940 0.990 1.040 v reference voltage v ref 1.24 v temperature coefficient 100 ppm/c output leakage current (sda) i l -1 +1 a v ol = +0.4v 3 output-current low (sda) i ol v ol = +0.6v 6 ma i/o capacitance c i/o 10 pf dac output current characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units dc source, v out measured at +1.2v 0.33 output current variation due to power-supply change dc sink, v out measured at +1.2v 0.33 %/v dc source, v cc = +3.6v 0.15 output current variation due to output-voltage change dc sink, v cc = +3.6v 0.30 %/v * not to exceed +6.0v.
DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking _______________________________________________________________________________________ 3 dac output current characteristics (continued) (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units output voltage for sinking current v out:sink (note 4) 0.5 3.5 v output voltage for sourcing current v out:source (note 4) 0 v cc - 0.75 v full-scale sink output current i out:sink (note 4) 50 200 a full-scale source output current i out:source (note 4) -200 -50 a output-current full-scale accuracy i out:fs t a = +25c 5 % output-current temperature coefficient i out:tc (note 5) 130 ppm/ c output-current power-supply rejection ratio 0.33 %/v output-leakage current at zero current setting i zero -1 +1 a output-current differential linearity dnl (note 6) 0.5 lsb output-current integral linearity inl (note 7) 1 lsb i 2 c electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?. timing referenced to v il(max) and v ih(min) . see figure 6.) parameter symbol conditions min typ max units scl clock frequency f scl (note 8) 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd:sta 0.6 s low period of scl t low 1.3 s high period of scl t high 0.6 s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s sda and scl rise time t r (note 9) 20 + 0.1c b 300 ns sda and scl fall time t f (note 9) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s sda and scl capacitive loading c b (note 9) 400 pf
DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking 4 _______________________________________________________________________________________ note 1: all voltages are referenced to gnd. current entering the ic is specified positive, and current exiting the ic is negative. note 2: input resistors (r fs[3:0] ) must be between the specified values to ensure the device meets its accuracy and linearity specifi- cations. note 3: supply current specified with all outputs set to zero current setting and with all inputs at v cc or gnd. sda and scl are connected to v cc . excludes current through r fs resistors (i rfs ). total current including i rfs is i cc + (2 x i rfs ). note 4: the output-voltage full-scale ranges must be satisfied to ensure the device meets its accuracy and linearity specifications. only applies to current dac operation, not power-supply tracking operation. note 5: temperature drift excludes drift caused by external resistors. note 6: differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. the expected incremental increase is the full-scale range divided by 127. note 7: integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. the expected value is a straight line between the zero and the full-scale values proportional to the setting. note 8: timing shown is for fast-mode operation (400khz). this device is also backward-compatible with i 2 c standard-mode timing. note 9: c b ?otal capacitance of one bus line in pf. power-supply tracking characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?, see figure 5.) parameter symbol conditions min typ max units input divider ratio r div r a /r b and r c /r d 0.5 1 output load r l r l = (r f x r e )/(r f +r e ) 1 20 k feedback resistor ratio r f /r b 0.5 4.5 gain resistor r g 0.8 10 k gain setting ratio r l /r g 1.4 5 r l /r g = 2, r l = 5k , v cc = +3.6v, t a = +25c 2.4 power-supply tracking gain g vi r l /r g = 5, r l = 5k , v cc = +3.6v, t a = +25c 3.8 6.2 10 ma/v power-supply tracking input bias current i b 1 a power-supply tracking input voltage v in inp[3:1] and inn[3:1] 0 v cc - 1.4 v unity gain bandwidth gbw r l /r g = 1.4; r l = 5k 12 mhz output voltage while tracking v out:trk switch closed, v cc = +3.0v, measured at out[3:1], r l = 5k 0 1.5 v output current while tracking i out:trk r l /r g = 1.4, r g = 1k , v cc = +3.0v, v fb = +0.8v 1 ma tracking accuracy 600 mv output leakage i bc switch open 0.5 a comparator input bias current i off 1 a comparator input offset v os 5 mv switch delay t dc 5 s comparator hysteresis v hys 12.5 mv
DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking _______________________________________________________________________________________ 5 supply current vs. supply voltage DS4426 toc01 supply voltage (v) supply current ( a) 5.0 4.5 3.0 3.5 4.0 425 450 475 500 525 550 575 600 400 2.5 5.5 sda = scl = thr[3:1] = v cc gain[3:1] = fs[3:0] = out[3:0] = open inp[3:1] = inn[3:1] = gnd supply current vs. temperature DS4426 toc02 temperature ( c) supply current ( a) 80 60 -20 0 20 40 425 450 475 500 525 550 575 600 400 -40 sda = scl = thr[3:1] = v cc gain[3:1] = fs[3:0] = out[3:0] = open inp[3:1] = inn[3:1] = gnd v cc = +5.5v v cc = +3.3v v cc = +2.7v voltco (source) DS4426 toc03 v out (v) i out ( a) 4 3 2 1 -225 -200 -175 -150 -250 05 sda = scl = thr[3:1] = v cc gain[3:1] = open inp[3:1] = inn[3:1] = gnd 40k load on fs[3:0]. v cc = +5.5v voltco (sink) DS4426 toc04 v out (v) i out ( a) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 175 200 225 250 150 0 4.0 sda = scl = thr[3:1] = v cc gain[3:1] = open inp[3:1] = inn[3:1] = gnd 40k load on fs[3:0]. v cc = +5.5v temperature coefficient vs. setting (source) DS4426 toc05 setting (dec) temperature coefficient ( c/ppm) 125 100 75 50 25 0 50 100 150 200 250 300 -50 0 range for the 50 a to 200 a current source range +25 c to -40 c +25 c to +85 c temperature coefficient vs. setting (sink) DS4426 toc06 setting (dec) temperature coefficient ( c/ppm) 125 100 75 50 25 -150 -50 50 150 250 350 450 550 650 -250 0 range for the 50 a to 200 a current sink range +25 c to -40 c +25 c to +85 c integral linearity DS4426 toc07 setting (dec) inl (lsb) 125 100 75 50 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 range for the 50 a to 200 a current source and sink range differential linearity DS4426 toc08 setting (dec) dnl (lsb) 125 100 75 50 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 range for the 50 a to 200 a current source and sink range typical operating characteristics (t a = +25?, unless otherwise noted.)
detailed description the DS4426 contains four i 2 c-adjustable current sources that are each capable of sinking and sourcing current. three of the current outputs (out[3:1]) also have power-supply tracking circuitry that allows addi- tional current to be sourced during power-up. adjustable current dacs each output (out[3:0]) has 127 sink and 127 source settings that are programmed through the i 2 c interface. the full-scale current ranges (and corresponding step sizes) of the outputs are determined by external resis- tors connected to the corresponding fs pins (see figure 1). the formula to determine the external resistor values (r fs ) for each output is given by: where i fs is the desired full-scale current value, v rfs is the r fs voltage (see the dc electrical characteristics table), and r fs is the external resistor value. to calculate the output-current value (i out ) based on the corresponding dac value (see table 2 for correspond- ing memory addresses), use the following equation: on power-up, the DS4426 current dac outputs are set to zero current. this is done to prevent the device from sinking or sourcing an incorrect current before the sys- tem host controller has a chance to modify its setting. note, however, that if power-supply tracking is enabled (see the power-supply tracking circuit section), then the DS4426 can still source current at power-up. when used in adjustable power-supply applications (see figure 8), the DS4426 does not affect the initial power-up voltage of the supply because it defaults to providing zero output current on power-up unless power-supply tracking is enabled. as it sources or sinks current into the feedback voltage node, it changes the amount of output voltage required by the regulator to reach its steady-state operating point. i dacvalue dec i out fs = () 127 r v i fs rfs fs = 16 127 DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking 6 _______________________________________________________________________________________ pin description pin name function 1 sda serial data input/output. i 2 c data pin. 2 scl serial clock input. i 2 c clock input. 3 v cc voltage supply 4 out0 current dac output 5, 6, 7 out1, out2, out3 current dac and tracking control output 8 gnd ground 9 a0 i 2 c address input 0 10 a1 i 2 c address input 1 11, 13, 15 inp1, inp2, inp3 power-supply tracking positive input 12, 14, 16 inn1, inn2, inn3 power-supply tracking negative input 17, 19, 20 thr3, thr2, thr1 threshold input. comparator input used to set threshold for tracking enable/disable based on v ref /2. 18 dnc do not connect 21C24 fs0, fs1, fs2, fs3 full-scale calibration input. a resistor-to-ground on this input determines full- scale output current on the associated output. 25, 26, 27 gain3, gain2, gain1 gain adjustment pin. connect a resistor between this pin and v cc . 28 n.c. no connection ep exposed pad. no connection.
DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking _______________________________________________________________________________________ 7 using the external resistors r fs[3:0] to set the output- current range, the DS4426 provides some flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be con- trolled or margined. as a source for biasing instrumentation or other circuits, the DS4426 provides a simple and inexpensive current source with an i 2 c interface for control. the adjustable, full-scale range allows the application to get the most out of its 7-bit sink or source resolution. power-supply tracking circuit by making use of the power-supply tracking circuitry, the DS4426 has the ability to source current on power- up. this current is additive with the current dac source/sink currents and is determined by the value of the gain resistor, r g , and the supply voltage, v cc . this current is controlled by the voltages presented to the corresponding inp and inn pins, and the voltages pre- sented to the corresponding threshold (thr) pins. maximum source current the maximum current the DS4426 can source at power-up using the power-supply tracking circuitry depends on the value of the supply voltage, v cc , and the gain resistor, r g , connected from the correspond- ing gain pin to v cc . the maximum current (i max ) that can be sourced to the corresponding out pin can be estimated using the following equation: the power-supply tracking circuit can be estimated with figure 2. inputs for power-supply tracking: inp and inn each pair of power-supply tracking inputs, inp and inn, determines if and how much of the i max current is sourced when the power-supply tracking circuit is enabled. when the difference between the voltage pre- sented to inp (v inp ) and inn (v inn ) is more than approximately +0.3v, then the maximum source cur- rent, as determined by the value i max , is sourced into the out pin connection. when the difference between v inp and v inn is less than approximately -0.2v, then no current is sourced into the corresponding out pin. the change in current from no current to i max can be esti- mated by the power-supply tracking gain, g vi (see the power-supply tracking characteristics table). figure 3 shows the typical current behavior of the power-supply tracking circuit with respect to the volt- age difference seen at the inp and inn inputs. i vv r max cc out g ? ? () msb lsb current dac[3:0] out[3:0] fs[3:0] tracking out[3:1] only i 2 c control 127 positions each for source and sink mode source or sink mode r fs[3:0] figure 1. current dac detail + inp gain v cc dac out slave feedback node g vi r g - inn shutdown figure 2. gain stage i -0.2 +0.3 at v cc = +5.0v i max g vi v (v inp - v inn ) figure 3. inp and inn differential inputs
DS4426 thr inputs for enabling power-supply tracking comparators are used to individually enable/disable power-supply tracking based on the voltage presented to the corresponding thr pin relative to a fixed internal reference (v ref /2 = +0.62v). figure 4 shows a typical startup and shutdown plot based on the voltage pre- sented to the thr pin. tracking can be disabled by connecting the corresponding thr pin to a voltage greater than v ref /2. below this threshold, the tracking circuit is active. power-supply tracking in dc-dc power applications the DS4426 provides several options for power-supply tracking control of dc-dc power supplies. in many cases, it is desirable to prevent certain dc-dc supplies from exceeding the voltage of other supplies. this is often the case with the voltages applied to a digital core and i/o. each DS4426 supports one master with three slave dc-dcs. see figure 5 for more information. loop bandwidth consideration power-supply tracking is used to override each slave dc-dc? feedback loop during power-up and power- down. power-supply tracking is capable of slewing at a much faster rate than most dc-dc converters. care must be exercised when selecting the loop bandwidth of the master dc-dc, slave dc-dc, and power-supply tracking control loop such that oscillations and over- shoot are minimized. while the slave dc-dc supplies are tracking the master dc-dc supply, there are three time constants of concern: 1) master bw. the master dc-dc control loop band- width, power-up ramp rate, and power-down ramp rate. 2) slave bw. the slave dc-dc supplies control loop bandwidths. 3) tracking bw. the DS4426 tracking circuit band- width. to ensure stable operation and minimize peaking, the bandwidths should follow the following rule: master bw and slave bw < (tracking bw/10) quad-channel, i 2 c-margining idacs with three channels of power-supply tracking 8 _______________________________________________________________________________________ v DS4426 tracking disabled gain error tracking range: DS4426 overrides slave's feedback loop v master v slave v threshold t figure 4. enabling power-supply tracking using the thr input
ratiometric tracking the DS4426 can maintain a defined ratio between a slave voltage and the master voltage where: k sm = v slave /v master . in figure 5, this ratio is given by the following: k sm = [r b[3:1] /(r a[3:1] + r b[3:1] )]/[r d[3:1] /(r c[3:1] + r d[3:1] )]. nonratiometric tracking is the special case where k sm = 1. power-supply tracking loop gain stability slave dc-dc output tracking is controlled by the DS4426 sourcing current into the slave dc-dc's feed- back loop. this changes the stability of the loop during tracking. the amount of gain used can be adjusted by changing the ratio of r l /r g . if oscillations occur, increasing r g reduces gain and increases the system? phase margin. if the slave dc-dc has a compensation pin, the rc network connected to this pin can also be adjusted to improve phase margin. this pin is often labeled comp or ith. a larger compensation time con- stant (increased r and/or increased c) often increases the stability of the system during tracking; however, this also modifies the dc-dc's transient response. in order to prevent modification of the slave dc-dc? transient response after power-supply tracking is complete, r g should first be modified before adjusting the compen- sation network. the higher the gain, the less the gain error. reducing the gain increases the gain error during tracking. see figure 4 for more information. DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking _______________________________________________________________________________________ 9 DS4426 r fs0 r fs[3:1] r c[3:1] r g[3:1] 10k 10k r b[3:1] r thr[3:1] r a[3:1] 10k r e0 r f0 r d[3:1] 0.1 f sda v cc scl a0 a1 fs0 out0 i 2 c control interface v cc 5.0v 5.0v i 2 c v ref ref 1.24v inp[3:1] fs[3:1] out[3:1] inn[3:1] thr[3:1] gain[3:1] v ref /2 10k vout fb master dc-dc converter r e[3:1] r f[3:1] vout fb slave dc-dc converter comp x3 figure 5. typical dc-dc power-supply tracking application
inputs for tracking in dc-dc power applications when enabling/disabling the power-supply tracking, a resistor-divider connected to the thr input sets the dis- able threshold (see v threshold in figure 4). the top of the resistor-divider must be connected to the master dc-dc voltage for correct operation. below this thresh- old, the tracking circuit is active. power-supply sequencing the DS4426 can be used to perform power-supply sequencing. this is a subset of power-supply tracking with modifications to the external resistor network. the basic concept is that the DS4426 sources maximum current into the slave power supply's feedback node until a voltage in the system has risen above a specific voltage level. by sourcing the maximum current into the feedback node, the power supply's output is held off. maximum sourcing current is achieved with two steps: 1) apply the maximum allowed input voltage across inp and inn. connect inp to v cc - 1.4v using a voltage-divider to ground. connect inn to ground. 2) set the gain to the maximum allowed (r l /r g = 5). the slave power supply is allowed to turn on once the voltage on thr is greater than v ref /2. use a resistor- divider connected to the rising system voltage to scale the trip point to v ref /2. i 2 c slave address the DS4426 responds to one of four i 2 c slave address- es determined by the state of the input on the two address inputs. the two input states are connected to v cc or connected to ground. memory organization the DS4426? current sources are controlled by writing to memory addresses listed in table 2. the format of each of the output control registers is given by: where: for example: r fs0 = 80k and register 0xf8h is written to a value of 0xaah. use the following formula to calculate the out- put current: i fs = (1.0v/80k ) x (127/16) = 99.22? the msb of the output register is 1, so the output is sourcing the value corresponding to position 2ah (42 decimal). the magnitude of the output current is equal to the following: 99.22? x (42/127) = 32.8125? DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking 10 ______________________________________________________________________________________ a1 a0 slave address (hex) gnd gnd 90h gnd v cc 92h v cc gnd 94h v cc v cc 96h table 1. slave addresses memory address (hex) current source f8h out0 f9h out1 fah out2 fbh out3 table 2. memory addresses bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) s d 6 d 5 d 4 d 3 d 2 d 1 d 0 bit name description power-on default s sign bit determines if dac sources or sinks current. for sink, s = 0. for source, s = 1. 0b d x data 7-bit data word controlling dac output. setting 0000000b outputs zero current regardless of the state of the sign bit. 0000000b
i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers: i 2 c slave address: the slave address of the DS4426 is determined by the state of the a0 and a1 pins (see table 1). master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac- tive and in their logic-high states. when the bus is idle it often initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 3 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 3 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see figure 6 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl, plus the setup-and-hold time requirements (figure 6). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (figure 6) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse, and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledgement (ack) or not acknowledge (nack) is always the ninth bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the ninth bit. a device performs a nack by transmitting a 1 during the ninth bit. timing for the ack and nack is identical to all other bit writes (figure 6). an ack is the acknowledgment that the device is prop- erly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit-write def- inition, and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information trans- fer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition, and the master transmits an ack using the bit-write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the DS4426? slave address is determined by the state of the a0 and a1 pins (see table 1). when the r/ w bit is 0 (such as in 90h), the master is indicating it will write data to the slave. if r/ w = 1 (91h in this case), the master is indicating it wants to read from the slave. if an incorrect slave address is written, the DS4426 assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to iden- tify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking ______________________________________________________________________________________ 11
DS4426 i 2 c communication writing to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and gener- ate a stop condition. remember that the master must read the slave? acknowledgement during all byte-write operations. reading from a slave: to read from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. quad-channel, i 2 c-margining idacs with three channels of power-supply tracking 12 ______________________________________________________________________________________ slave address* start start 1 0 0 1 0 a1 a0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register/memory address b7 b6 b5 b4 b3 b2 b1 b0 data stop start repeated start 91h master nack stop 10010000 11111 000 f8h 10010 001 10010000 11111 001 00000000 90h f9h stop data example i 2 c transactions (when a0 and a1 are grounded) *the slave address is determined by address pins a0 and a1. typical i 2 c write transaction 90h single-byte write -write register f9h to 00h a) single-byte read -read register f8h b) slave ack slave ack slave ack slave ack slave ack slave ack figure 7. i 2 c communication examples scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 6. i 2 c timing diagram
applications information example calculations for an adjustable power supply in this example, the circuit shown in figure 8 is used to margin a +2.0v supply by ?0%. the margined power supply has a dc-dc converter output voltage, v out , of +2.0v and a dc-dc converter feedback voltage, v fb , of +0.8v. to determine the relationship of r 0a and r 0b , start with the equation: substituting v fb = +0.8v and v out = +2.0v, the rela- tionship between r 0a and r 0b is determined to be: r 0a = 1.5 x r 0b i out0 is chosen to be 100? (midrange source/sink current for the DS4426). summing the currents into the feedback node, we have the following: i out0 = i r0b - i r0a where: and to create a ?0% margin in the supply voltage, the value of v out is set to +2.4v. with these values in place, r 0b is calculated to be 2.67k , and r 0a is i vv r ra out fb a 0 0 = ? i v r rb fb b 0 0 = v r rr v fb b ab out = + 0 00 DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking ______________________________________________________________________________________ 13 dc-dc converter fb out sda scl out0 gnd r fs0 = 80k 4.7k 4.7k v cc v cc v out = 2.0v* fs0 r 0b = 2.67k r 0a = 4k v fb = 0.8v* i r0a i r0b i out0 DS4426 *v out and v fb values are determined by the dc-dc converter and should not be confused with v out and v ref of the DS4426. figure 8. example typical application circuit
DS4426 quad-channel, i 2 c-margining idacs with three channels of power-supply tracking maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. calculated to be 4.00k . the current dac in this con- figuration allows the output voltage to be moved linearly from +1.6v to +2.4v using 127 settings. this corre- sponds to a resolution of 6.3mv/step. v cc decoupling to achieve the best results when using the DS4426, decouple the power supply with a 0.01? (or 0.1?) capacitor. use a high-quality, ceramic, surface-mount capacitor if possible. surface-mount components mini- mize lead inductance, which improves performance. ceramic capacitors tend to have adequate high-fre- quency response for decoupling applications. DS4426 sda v cc scl a0 a1 fs0 out0 i 2 c control interface v cc v ref ref 1.24v inp1 fs1 out1 inn1 thr1 gain1 v ref /2 inp2 fs2 out2 inn2 thr2 gain2 v ref /2 inp3 fs3 out3 inn3 thr3 gnd gain3 v ref /2 functional diagram package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 28 tqfn t2844+1 21-0139

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