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h anb it HDD16M64B8 ur l : www.hbe.co.kr 1 hanbit electronics co.,ltd. rev 1.0 (august. 2002) general description th e HDD16M64B8 is a 16 m x 64 bit double data rate(ddr) synchronous dynamic ram high - density memory module. the module consists of eight cmos 16 m x 8 bit with 4banks ddr sdram s in 66pin tsop - ii 400mil package s and 2k eeprom in 8 - pin tssop package on a 200 - pin glass - epoxy. four 0. 1 uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the HDD16M64B8 is a so - di mm ( small outline dual in line memory module ) . synchronous design allows precise cycl e control with the use of system clock. data i/o transactions are possible on both edges of dqs . range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications . a ll module components may be powered from a single 2.5 v dc power supply and all inputs and outputs are sstl_2 compatible. features ? p art identification HDD16M64B8 C 10a : 1 00 mhz (cl= 2 ) HDD16M64B8 C 13a : 1 33 mhz (cl= 2 ) HDD16M64B8 C 13b : 1 33 mhz (cl= 2.5 ) ? 128mb(16mx64) un buffered ddr s o - dimm based on 16 mx8 ddr sdrsm ? 2.5v 0.2v vdd and vddq power supply ? auto & self refresh capability ( 4096 cycles/64ms) ? all input and output are compatible with sstl_2 interface ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control inputs except data(dq), data strobes and data masks latched on the rising edge s of the clock ? mrs cycle with address key programs - latency (access from column address) : 2, 2.5 - burst length : 2, 4, 8 - data scramble : sequential & interleave ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control inpu ts except data(dq), data strobes and data masks latched on the rising edge s of the clock ? the used device is 4m x 8bit x 4banks ddr sdram ddr sdram module 128mbyte (16mx64bit), based on16mx8,4banks, 4k ref. so - dimm part no . h dd16m64b8
h anb it HDD16M64B8 ur l : www.hbe.co.kr 2 hanbit electronics co.,ltd. rev 1.0 (august. 2002) pin assignment * these pins should be nc in the system which does not support spd pin pin description pin pin description a0~a11 address input vdd power supply(2.5v) ba0~ba1 bank select address vddq power supply for d qs(2.5v) dq0~dq63 data input/output vref power supply for reference dqs0~dqs7 data strobe input/output vspd serial eeprom power supply(3.3) dm0~dm7 data - in mask vss ground ck0~ck2,/ck0~/ck2 clock input sa0~sa2 address in eeprom cke0~cke1 clock enable input sda serial data i/o /cs0 chip select input scl serial clock /ras , /cas row / column address strobe wp write protection nc no connection vddid vdd identification flag pin front pin back pin frontl pin back pin front pin back 1 vref 2 vref 67 dq27 68 dq31 133 dq s4 134 dm4 3 vss 4 vss 69 vdd 70 vdd 135 dq34 136 dq38 5 dq0 6 dq4 71 nc 72 nc 137 vss 138 vss 7 dq1 8 dq5 73 nc 74 nc 139 dq35 140 dq39 9 vdd 10 vdd 75 vss 76 vss 141 dq40 142 dq44 11 dqs0 12 dm0 77 nc 78 nc 143 vdd 144 vdd 13 dq2 14 dq6 79 nc 80 nc 145 dq41 146 dq45 15 vss 16 vss 81 vdd 82 vdd 147 dqs5 148 dm5 17 dq3 18 dq7 83 nc 84 nc 149 vss 150 vss 19 dq8 20 dq12 85 nc 86 nc (/reset) 151 dq42 152 dq46 21 vdd 22 vdd 87 vss 88 vss 153 dq43 154 dq47 23 dq9 24 dq13 89 ck2 90 vss 155 vdd 156 vdd 25 dqs1 26 dm1 91 /ck2 92 vdd 157 vdd 158 /ck1 27 vss 28 vss 93 vdd 94 vdd 159 vss 160 ck1 29 dq10 30 dq14 95 cke1 96 cke0 161 vss 162 vss 31 dq11 32 dq15 97 nc(a13) 98 nc (ba2) 163 dq48 164 dq52 33 vdd 34 vdd 99 nc (a12) 100 a11 165 dq49 166 dq53 35 ck0 36 vdd 101 a9 102 a8 167 vdd 168 vdd 37 /ck0 38 vss 103 vss 104 vss 169 dqs6 170 dm6 39 vss 40 vss 105 a7 106 a6 171 dq50 172 dq54 41 dq16 42 dq20 107 a5 108 a4 173 vss 174 vss 43 dq17 44 dq21 109 a3 110 a2 175 dq51 176 dq55 45 vdd 46 vdd 111 a1 112 a0 177 dq56 178 dq60 47 dqs2 48 dm2 113 vdd 114 vdd 179 vdd 180 vdd 49 dq18 50 dq22 115 a10/ap 116 ba1 181 dq57 182 dq61 51 vss 52 vss 117 ba0 118 /ras 183 dqs7 184 dm7 53 dq19 54 dq23 119 /we 120 /cas 185 vss 186 vss 55 dq24 56 dq28 121 /cs0 122 nc 187 dq58 188 dq62 57 vdd 58 vdd 123 nc 124 nc 189 dq59 190 dq63 59 dq25 60 dq29 125 vss 126 vss 191 vdd 192 vdd 61 dqs3 62 dm3 127 dq32 128 dq36 193 *sda 194 *sa0 63 vss 64 vss 129 dq33 130 dq37 195 *scl 196 *sa1 65 dq26 66 dq30 131 vdd 132 vdd 197 *vspd 198 *sa2 199 vddid 200 nc
h anb it HDD16M64B8 ur l : www.hbe.co.kr 3 hanbit electronics co.,ltd. rev 1.0 (august. 2002) v spd f unctional block diag ram / cs 0 a11 a11
h anb it HDD16M64B8 ur l : www.hbe.co.kr 4 hanbit electronics co.,ltd. rev 1.0 (august. 2002) pin function descrip tion pin name input function ck, / ck clock ck and ck are differential clock inputs. all address and control input signals are sam - pled on the positive edge of ck and negative edge of ck. output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ck. cke clock enable cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power - down and self refresh operation (all banks idle), or active power - down(row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke are disabled during power - down and self r efresh modes, providing low standby power. cke will recognizean lvcmos low level prior to vref being stable on power - up. /cs chip select cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is regis tered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. a0 ~ a1 1 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra1 1 , column address : ca0 ~ ca 9 ba 0 ~ ba1 bank select address b a0 and ba1 define to which bank an active, read, write or pre - charge command is being applied. / ras row address strobe latches row addresses on the positive going edge of the clk with / ras low. enables row access & precharge. / cas column address strobe latches column addresses on the positive going edge of the clk with / cas low. enables column access. / we write enable enables write operation and row precharge. latches data in starting from / cas, / we active. dq s 0 ~ 7 data st robe output with read data, input with write data. edge - aligned with read data, cen - tered in write data. used to capture write data. dm0~7 input data mask dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs load - ing. dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. vddq supply dq power supply : +2.5v 0.2v. vdd supply power supply : +2.5v 0.2v (device specific). vss supply dq ground. vref supply sstl_2 reference voltage. vspd supply serial eeprom power supply : 3.3v vddid vdd identification flag
h anb it HDD16M64B8 ur l : www.hbe.co.kr 5 hanbit electronics co.,ltd. rev 1.0 (august. 2002) absolute maximum rat ings pa rameter symbol rating unte voltage on any pin relative to vss v in , v out - 0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd - 1.0 ~ 3.6 v voltage on v ddq supply relative to vss v ddq - 0.5 ~ 3.6 v storage temperature t stg - 55 ~ +150 c power dissipati on p d 8.0 w short circuit current i os 50 ma notes: operation at above absolute maximum rating can adversely affect device reliability dc operating con ditions ( recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) ) paramete r symbol min max unit note supply voltage v dd 2.3 2.7 v i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref 1.15 1.35 v 1 i/o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v 2 input high voltage v ih (dc) v ref + 0.15 v ref + 0.3 v input low voltage v il (dc) - 0.3 v ref - 0.15 v input voltage level, ck and /ck inputs v in (dc) - 0.3 v ddq + 0.3 v input differential voltage , ck and /ck inputs v id (dc) 0.3 v ddq + 0.6 v input leakage current i l i - 2 2 ua 3 out put leakage current i o z - 5 5 ua out put high current (v out = 1.95v) i oh - 16.8 ma out put low current (v out = 0.35v) i o l 16.8 ma notes : 1.typically, the value of v ref is expected to be about 0.5* v dd of the transmitting device . v ref is expected to track variation in v dd q . 2. peak to peak ac noise on v ref may not exceed 2% v ref (dc). 3. v tt of the transmitting device must track v ref of the receiving device. capacitance ( v dd = min to max, v ddq = 2.5v to 2.7v, t a = 2 5 c, f = 1 00 mhz ) description symbo l min max units inpu t capacitance(a0~a11, ba0~ba1, / ras, / cas ,/we) c in1 36 44 pf input capacitance(cke0,cke1) c in2 36 44 pf input capacitance(/cs0) c in3 34 42 pf input capacitance(ck0~ck2, /ck0~/ck2) c in4 34 38 pf input capacitance(dm0~dm7) c in5 8 9 pf d ata input/output capacitance (dq0 ~ dq 63, dqs0~dqs7 ) c out1 8 9 pf
h anb it HDD16M64B8 ur l : www.hbe.co.kr 6 hanbit electronics co.,ltd. rev 1.0 (august. 2002) d c characteristics (recommended operating condition unless otherwise noted, v dd = 2.5v, t = 25 c) version parameter symbol test condition - 10a - 13a - 13b unit note operating current (one bank active ) i dd1 burst length = 2 t rc 3 t rc (min) , cl=2.5 i o ut = 0ma , active - read - presharge 720 800 800 ma precharge standby current in power - down mode i dd2p cke v il (max) t c k = t ck (min) , all banks idle 24 28 28 ma precharge standby current in non power - down mo de i dd2n cke 3 v ih (min) / c s 3 v ih (min), t c k = t ck (min) 104 104 104 ma active standby current in power - down mode i dd 3 p all banks idle, cke v il (max), t c k = t ck (min) 240 240 240 ma active standby current in non power - down mode (one bank active) i dd 3 n o nel banks, active - read - presharge, t rc = t ras (max) , t c k = t ck (min) 328 360 360 ma cl=2.5 operating current ( read ) i dd 4r burst length = 2 t rc = t rc (min) , i o ut = 0ma , cl=2 1040 1200 1200 ma cl=2.5 operating current ( write) i dd 4w burst length = 2 t rc = t rc (min) cl=2 1040 1240 1240 ma auto refre sh current i dd 5 t rc 3 t ref (min) 1200 1440 1440 ma normal 16 16 16 ma self refresh current low power i dd 6 cke 0.2v 80 8 8 ma notes: operation at above absolute maximum rating can adve rsely affect device reliability ac operating condition s parameter s tmbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih (ac) vref + 0.35 input low (logic 0) voltage, dq, dqs and dm signals. v il (ac) vref - 0.35 v in put differential voltage, ck and ck inputs v id (ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs v ix (ac) 0.5*vddq - 0.2 0.5*vddq+0.2 v 2 notes: 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and must track variations in the dc level of the s ame
h anb it HDD16M64B8 ur l : www.hbe.co.kr 7 hanbit electronics co.,ltd. rev 1.0 (august. 2002) ac operating test conditions parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal ma ximum peak swing 1.5 v input signal minimum slew rate 1.0 v input levels( v i h / v i l ) v re f +0.35/ v re f v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit v a c c haracteristics (these ac charicteristics were tested on the component) ddr200 ddr266a ddr266b - 10a - 13a - 13b parameter symbol min max min max min max unit note row cycle time t rc 70 65 65 ns 1 refresh row cycle time t rfc 80 75 75 ns 1,2 row active time t ras 48 120k 45 120k 45 120k ns 1,2 / ras to / cas delay t rcd 20 20 20 ns 3 row precharge time t rp 20 20 20 ns 3 row active to row active delay t rrd 15 15 15 ns 3 write recovery time t wr 2 2 2 t ck 3 last data in t o read command t cdlr 1 1 1 t ck 2 col. address to col. address delay t ccd 1 1 1 t ck cl=2.0 10 12 7.5 12 10 12 ns clock cycle time cl=2.5 t ck 12 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck
h anb it HDD16M64B8 ur l : www.hbe.co.kr 8 hanbit electronics co.,ltd. rev 1.0 (august. 2002) clock low level w idth t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs - out access time from ck/ck t dqsck - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns output data access time from ck/ck t ac - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns data strobe edge to ouput data edge t dqsq - +0.6 - +0.5 - +0.5 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck data out high impedence time from ck - /ck t hzq - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns 2 ck to valid dqs - in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t c k dqs - in setup time t wpres 0 0 0 ns 3 dqs - in hold time t wpreh 0.25 0.25 0.25 t ck dqs - in falling edge to ck rising - setup time t d ss 0.2 0.2 0.2 t ck dqs - in falling edge to ck rising hold time t dsh 0.2 0.2 0.2 t ck dqs - in high level width t dqsh 0.35 0.35 0.35 t ck dqs - in low level width t dqsl 0.35 0.35 0.35 t ck dqs - in cycle time t dsc 0.9 1.1 0.9 1.1 0.9 1.1 t ck address and control input setup time t is 1.1 0.9 0.9 ns address and control input hold time t ih 1.1 0.9 0.9 ns mode register set cycle time t mrd 16 15 15 ns dq & dm setup time to dqs t ds 0.6 0.5 0.5 ns dq & dm hold time to dqs t dh 0.6 0.5 0.5 ns dq & dm input pulse width t dipw 2 1.75 1.75 ns power down exit time t pdex 10 10 10 ns exit self refresh to write command t xsw 116 95 ns exit self refresh to bank active command t xs a 80 75 75 ns exit self refresh to read command t xs r 200 200 200 cycle refresh interval time t ref 15.6 15.6 15.6 us 1 output dqs valid window t q h 0.35 0.35 0.35 t ck dqs write postamble time t w pst 0.25 0.25 0.25 t ck 4 notes : 1. maximum burst refresh of 8. 2. t hzq transitions occurs in the same assess time windows as valid data transitions. these parameters are not referenced to a specific voltage leve l, but specify when the device output is no longer driving . 3. the specific requirement is that dqs be valid (high - low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dqss .
h anb it HDD16M64B8 ur l : www.hbe.co.kr 9 hanbit electronics co.,ltd. rev 1.0 (august. 2002) 4. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) w ill degrade accordingly. simplified truth tab le command ck e n - 1 ck e n /cs /r a s /c a s /we dm ba 0,1 a10/ ap a11 a9~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x x x 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge e able h x l h l h x v h column address (a0 ~ a9 ) 4 auto precharge disable h l 4 write & column address auto precharge en able h x l h l l x v h column address (a0 ~ a 9 ) 4,6 burst stop h x l h h l x x 7 bank selection v l precharg e all banks h x l l h l x x h x 5 h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dm h x v x 8 h x x x no operation command h x l h h h x x (v=valid, x=don't care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a1 1 & ba0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba 1 : bank select addresses. if both ba0 and ba1 are "low" at read, write, row active and precharge, bank a is selected. if both ba0 is "low" and ba1 is "high" at read, write, row active and precharge, bank b is selected. if both ba0 is "high" an d ba1 is "low" at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are "high" at read, write, row active and precharge, bank d is selected. if a10/ap is "high" at row precharge, ba0 and ba1 is ignored and all banks are selecte d. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length.
h anb it HDD16M64B8 ur l : www.hbe.co.kr 10 hanbit electronics co.,ltd. rev 1.0 (august. 2002) 7. dm sampled at the rising and falling edges of the dqs and data - in are masked at the both edges ( write dm latency is 0 ) p ackaging information unit : mm front C side pcb ?? : 1.0 0.1mm
h anb it HDD16M64B8 ur l : www.hbe.co.kr 11 hanbit electronics co.,ltd. rev 1.0 (august. 2002) o r dering information part number density org. package ref. vcc mode max.frq HDD16M64B8 - 10a 128mbyte 16m x 64 200pin so - dimm 4k 2.5v ddr 100mhz/cl2 HDD16M64B8 - 13a 128mbyte 16m x 64 200pin so - dimm 4k 2.5v ddr 133mhz/cl2 HDD16M64B8 - 13b 128mbyte 16m x 64 200pin so - dimm 4k 2.5v ddr 133mhz/cl2.5

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