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ultral ow noise , 200 ma, cmos linear regulator adp151 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no licens e is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.32 9.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2011 analog devices, inc. all rights reserved. features ultra low noise: 9 v rms no noise bypass capacitor required stable with 1 f ceramic input and output capacitors maximum output current: 200 ma input voltage range: 2. 2 v to 5.5 v l ow q uiescent c urrent i gnd = 1 0 a with 0 load i gnd = 2 6 5 a with 2 00 ma load low shutdown current: < 1 a low dropout voltage: 1 4 0 mv at 200 ma load initial a ccuracy: 1 % accuracy over line, load , and temperature: 2.5 % 16 fi xed output voltage options: 1.1 v to 3.3 v psrr p erformance of 70 db at 1 0 khz current - limit and t hermal overload prot ection logic controlled enable internal pull - down resistor on en input 5 - l ead tsot package 6 - lead lfcsp package 4 - bal l , 0.4 mm pitch wlcsp applications rf, vco , and pll power supplies mobile phones digital camera and audio devices porta ble and battery - powered equipment post dc - to - dc regulation portable medical devices typical application circuit nc = no connect 1 2 3 5 4 1f 1f v out = 1.8v v in = 2.3v vout nc vin gnd en off on 08627-001 figure 1 . tsot adp151 with fixed output voltage, 1.8 v vin vout 1 2 en gnd c out 1f c in v out = 1.8v v in = 2.3v top view (not to scale) a b off on 08627-002 figure 2 . wlcsp adp151 with fixed output voltage, 1.8 v adp151 t op view (not to scale) 4 6 5 gnd vout nc 3 1 2 en vin nc 08627-047 nc = no connect. do not connect to this pin. on off 1f 1f v in = 2.3v v out = 1.8v figure 3. lfcsp adp151 with fixed output voltage, 1.8 v general description the adp151 is an ultra low noise, low dropout linear regulator that operates from 2. 2 v to 5.5 v and provide s up to 200 ma of o utput current. the low 1 4 0 mv dropout volta ge at 200 ma load improves efficiency and allows operation over a wide input voltage range. using an innovative circuit topology, the adp151 achieves ultra low noise performance without the necessity of a bypass ca pacitor , making it ideal for no ise - sensitive analog and rf applications . the adp151 also achieves ultralow noise per - formance without compromising psrr or transient line and load performance. the low 2 6 5 a of quiescent current at 200 ma load makes the adp151 suitable for battery - operated portable equipment . the adp151 also includes an internal pull - down resistor on the en input. the adp151 is specifically designed fo r stable operation with tiny 1 f , 30 % ceramic input and output capacitors to meet the requirements of high performance, space constrained applications. the adp151 is capable of 16 fixed output voltage options, ranging from 1. 1 v to 3.3 v. short - circuit a nd thermal overload protection circui ts prevent damage in adverse conditions. the adp151 is available in tiny 5 - lead tsot , 6 - lead lfcsp, and 4 - b all , 0. 4 mm pitch , halide - free wlcsp packages for the smallest footprint solution to meet a variet y of portable power application requirements .
adp151 rev. d | page 2 of 24 tab le of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 11 applications information .............................................................. 12 capacitor selection .................................................................... 12 enable feature ............................................................................ 13 adjustable output voltage operation ..................................... 13 current - limit and thermal overload protection ................. 15 thermal considerations ............................................................ 15 printed circuit board layout considerations ............................ 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 22 revision history 3 /1 1 rev. c to rev. d changes to current - limit threshold temperature range ......... 4 added epad notation ..................................................................... 6 changes to ordering guide .......................................................... 22 1 /1 1 rev. b to r ev. c changes to figure 23 ........................................................................ 9 1 2 /10 rev. a to rev. b added lfcsp package ....................................................... universal added figure 3 ; renumbered sequentially .................................. 1 added table 2 caption ; renumbered sequentially ..................... 4 changes to table 4 ............................................................................ 5 added figure 6, changes to table 5 ............................................... 6 changes to figure 23 ........................................................................ 9 c hanges to figure 3 7 and figure 38 ............................................. 14 added figure 51 to figure 56 ........................................................ 18 added figure 59 .............................................................................. 19 added figure 62 .............................................................................. 20 added figure 65 ............................................................................. 21 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 23 8/10 rev. 0 to rev. a changes to figure 8 ........................................................................... 7 changes to figure 15 capti on and figure 16 caption ................. 8 changes to figure 17 caption and figure 18 caption ................. 9 changes to ordering guide .......................................................... 21 3 / 1 0 rev ision 0 : initial version
adp151 rev. d | page 3 of 24 specifications v in = (v out + 0. 4 v) or 2. 2 v , whichever is greater ; en = v in , i out = 1 0 m a , c in = c out = 1 f , t a = 25c , unless otherwise noted. table 1 . parameter symbol conditions min typ max unit input voltage range v in t j = ?40c to +125c 2.2 5.5 v operating supply current i gnd i out = 0 a 1 0 a i out = 0 a, t j = ?40c to +125c 20 a i out = 100 a 2 0 a i out = 100 a, t j = ?40c to +125c 40 a i out = 10 ma 60 a i out = 10 ma, t j = ?40c to +125c 90 a i out = 200 ma 2 65 a i out = 200 ma , t j = ?40c to +125c 3 5 0 a shutdown current i gn d - sd en = gnd 0.2 a en = gnd, t j = ?40c to +125c 1.0 a output voltage accuracy v out i out = 1 0 m a ?1 +1 % tsot /lfcsp v out t j = ?40c to +125c v out < 1.8 v 100 a < i out < 200 ma , v in = ( v out + 0.4 v ) to 5.5 v ? 3 +2 % v out 1.8 v 100 a < i out < 200 ma , v in = ( v out + 0.4 v ) to 5.5 v ? 2.5 +1.5 % wlcsp v out t j = ?40c to +125c v out < 1.8 v 100 a < i out < 200 ma , v in = ( v out + 0.4 v ) to 5.5 v ? 2.5 +2 % v out 1.8 v 100 a < i out < 200 ma , v in = ( v out + 0.4 v ) to 5.5 v ? 2 +1.5 % regulation line regulation ?v out / ?v in v in = ( v out + 0.4 v ) to 5.5 v, t j = ?40c to +125c ?0. 05 +0. 05 %/ v load regulation (tsot /lfcsp ) 1 ?v out / ?i out v out < 1.8 v %/ma i out = 100 a to 200 ma 0.006 %/ma i out = 100 a to 200 ma , t j = ?40c to +125c 0.012 %/ma v out 1.8 v i out = 100 a to 200 ma 0.00 3 %/ma i out = 100 a to 200 ma , t j = ?40c to +125c 0.008 %/ma load regulation (wlcsp) 1 ?v out / ? i out v out < 1.8 v %/ma i out = 100 a to 200 ma 0.004 %/ma i out = 100 a to 200 ma , t j = ?40c to +125c 0.0 09 %/ma v out 1.8 v i out = 100 a to 200 ma 0.002 %/ma i out = 100 a to 200 ma , t j = ?40c to +125c 0.006 %/ma dropou t v o ltage 2 v dropout i out = 10 ma 1 0 mv i out = 10 ma, t j = ?40c to +125c 3 0 mv tsot /lfcsp i out = 200 ma 150 mv i out = 200 ma , t j = ?40c to +125c 230 mv wlcsp i out = 200 ma 135 mv i out = 200 ma , t j = ?40c to +125c 200 mv
adp151 rev. d | page 4 of 24 parameter symbol conditions min typ max unit start - up time 3 t start - up v out = 3.3 v 180 s current - limit threshold 4 i limit t j = 0c to +125c 220 300 400 ma undervoltage lockout t j = ?40c to +125c input voltage rising uvlo rise 1.96 v input voltage falling uvlo fal l 1.28 v hysteresis uvlo hys 120 mv thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c en input e n input logic high v ih 2.2 v v in 5.5 v 1.2 v en input logic low v il 2.2 v v in 5.5 v 0.4 v en inpu t pull - down resistance r en v in = v e n = 5.5 v 2. 6 m output noise out noise 10 hz to 100 khz, v in = 5 v, v out = 3.3 v 9 v rms 10 hz to 100 khz, v in = 5 v, v out = 2.5 v 9 v rms 10 hz to 100 khz, v in = 5 v, v out = 1. 1 v 9 v rms pow er supply rejection ratio psrr v in = v out + 0.5 v 10 khz, v in = 3.8 v, v out = 3.3 v, i out = 10 ma 70 db 100 khz, v in = 3.8 v, v out = 3.3 v, i out = 10 ma 55 db v in = v out + 1 v 10 khz, v in = 4.3 v, v out = 3.3 v, i out = 10 ma 7 0 db 100 k hz, v in = 4.3 v, v out = 3.3 v, i out = 10 ma 55 db 10 khz, v in = 2.2 v, v out = 1.1 v, i out = 10 ma 70 db 100 khz, v in = 2.2 v, v out = 1.1 v, i out = 10 ma 55 db 1 based on an end - point calcu lation using 0.1 ma and 20 0 ma loads. see figure 8 for typical load re gulation performance for loads less than 1 ma. 2 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nom inal output voltage. this applies only for output voltages above 2.2 v. 3 start - up time is defined as the time between the rising edge of en and v out being at 90 % of its nominal value. 4 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 3 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v (that is, 2.7 v). input and output cap acitor, recommended specifications table 2 . parameter symbol conditions min typ max unit m inimum i nput and o utput c apacitance 1 c min t a = ?40c to +125c 0. 7 f c apacitor esr r esr t a = ?40c to +125c 0 .001 0.2 1 the minimum input and output capacitance sh ould be greater than 0.7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum cap acitance specification is met. x7r and x5r type capa citors are recommended ; y5v and z5u capacitors are not recommended for use with any ldo.
adp151 rev. d | page 5 of 24 absolute maximum ratings table 3. parameter rating vin to gnd ?0.3 v to +6.5 v vout to gnd ?0.3 v to vin en to gnd ?0.3 v to +6.5v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c operating ambient temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp151 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). the maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) the junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in. 3 in. circuit board. see jesd51-7 and jesd51-9 for detailed information on the board construction. for additional information, see the an-617 application note, microcsp ? wafer l e vel chip s cale package , available at www.analog.com . jb is the junction-to-board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a 4-layer board. the jesd51-12, guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real-world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) see jesd51-8 and jesd51-12 for more detailed information about jb . thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jb unit 5-lead tsot 170 43 c/w 4-ball, 0.4 mm pitch wlcsp 260 58 c/w 6-lead 2 mm 2 mm lfcsp 63.6 28.3 c/w esd caution
adp151 rev. d | page 6 of 24 pin configuration s and function descrip tions nc = no connect top view (not to scale) adp151 1 2 3 5 4 vin gnd en vout nc 08627-003 1 2 a b top view (not to scale) vin vout en gnd 08627-004 adp151 t op view (not to scale) 3 1 2 gnd vout nc 4 6 5 en vin nc 08627-048 notes 1. nc = no connect. do not connect to this pin. 2. the exposed pad must be connected to ground. figure 4. 5 - lead tsot pin configuration figure 5. 4 - ball wlcsp pin configuration figure 6. 6 - lead lfcsp pi n configuration table 5 . pin function descriptions pin no. mnemonic description tsot wlcsp lfcsp 1 a 1 6 vin regulator input supply. bypass vin to gnd with a 1 f or greater capacitor. 2 b 2 3 gnd ground. 3 b 1 4 en enable inpu t. drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin. 4 n/a 2 nc no connect. not connected internally. 5 a 2 1 vout regulated output voltage. bypass vout to gnd with a 1 f or greater capacitor. n/a n/a 5 nc no connect. not connected internally. n/a n/a epad exposed pad. the exposed pad must be connected to ground. the exposed pad enhances the thermal performance of the package.
adp151 rev. d | page 7 of 24 typical performance characteristics v in = 5 v, v out = 3.3 v , i out = 1 ma , c in = c out = 1 f , t a = 25c, unless otherwise noted . 3.35 3.25 3.27 3.29 3.31 3.33 ?40 ?5 25 85 125 v out (v) junction temperature (c) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 08627-005 figure 7 . output voltage vs. junction temperature 3.35 3.25 3.27 3.29 3.31 3.33 0.01 1000 100 10 1 0.1 v out (v) i load (ma) 08627-006 figure 8 . output voltage vs. load current 3.35 3.25 3.27 3.29 3.31 3.33 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v out (v) v in (v) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 08627-007 figure 9 . output voltage vs. input voltage 1k 100 10 1 ?40 ?5 25 85 125 ground current (a) junction temperature (c) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 08627-008 figure 10 . ground current vs. junction temperature 1k 10 100 0.01 1000 100 10 1 0.1 ground current (a) i load (ma) 08627-009 figure 11 . ground current vs. load current ground current (a) v in (v) 1k 10 100 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 08627-010 figure 12 . ground current vs. inpu t voltage
adp151 rev. d | page 8 of 24 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 ?50 ?25 125 100 75 50 25 0 shutdown current (a) temperature (c) v in = 3.6v v in = 3.8v v in = 4.2v v in = 4.4v v in = 4.8v v in = 5.5v 08627-011 figure 13 . shutdown current vs. temperature at various input voltages 120 100 80 60 40 20 0 1 10 100 1000 dropout voltage (ma) i load (ma) 08627-012 figure 14 . dropout voltage vs. load current 3.40 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 v out (v) v in (v) i out = 1ma i out = 5ma i out = 10ma i out = 50ma i out = 100ma i out = 200ma 08627-013 figure 15 . output voltage vs. input voltage ( in dropout) 800 700 600 500 400 300 200 100 0 3.10 3.55 3.50 3.45 3.40 3.35 3.30 3.25 3.20 3.15 ground current (a) v in (v) i out = 1ma i out = 5ma i out = 10ma i out = 50ma i out = 100ma i out = 200ma 08627-014 figure 16 . gro und current vs. input voltage (i n dropout) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 200ma 100ma 10ma 1ma 100a 08627-015 figure 17 . power supply rejection ratio vs. frequency, v out = 1.2 v , v in = 2.2 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 200ma 100ma 10ma 1ma 100a 08627-016 figure 18 . power su pply rejection ratio vs. frequency, v out = 2. 8 v , v in = 3.3 v
adp151 rev. d | page 9 of 24 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 200ma 100ma 10ma 1ma 100a 08627-017 figure 19 . power supply rejection ratio vs. frequency, v out = 3.3 v , v in = 3.8 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) v out = 3.3v, i out = 200ma v out = 3.3v, i out = 10ma v out = 2.8v, i out = 200ma v out = 2.8v, i out = 10ma v out = 1.1v, i out = 200ma v out = 1.1v, i out = 10ma 08627-018 figure 20 . power supply rejection ratio vs. frequenc y a t various output voltages and load currents , v out ? v in = 0.5 v, except for v out = 1.1 v, v in = 2.2 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i out = 200ma, v in = 3.3v i out = 10ma, v in =3.3v i out = 200ma, v in = 3.8v i out = 10ma, v in = 3.8v 08627-019 figure 21 . power supply rejection ratio vs. frequency at various voltages and load currents , v out = 2.8 v 14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0.001 0.01 0.1 1 10 100 1k noise (v rms) load current (ma) 3.3v 2.8v 1.2v 1.1v 08627-020 figure 22 . output noise vs. load curren t and output voltage , v in = 5 v, c out = 1 f 1000 10 100 10 100k 10k 1k 100 noise spectral density (nv/ hz) frequency (hz) 3.3v 2.8v 1.2v 1.1v 08627-021 figure 23 . output noise spectral density vs. frequency , v in = 5 v, i load = 10 ma, c out = 1 f ch1 200ma ch2 50mv m20s a ch1 64.0ma t 10.00% 1 2 t load current v out 08627-022 figure 24 . load transient response, c in , c out = 1 f , i loa d = 1 ma to 20 0 ma
adp151 rev. d | page 10 of 24 ch1 1v ch2 2mv m10s a ch1 4.56v t 10.80% 1 2 t input voltage v out 08627-023 figure 25 . line transient response, c in , c out = 1 f , i load = 200 ma ch1 1v ch2 2mv m10s a ch1 4.56v t 10.80% 1 2 t input voltage v out 08627-024 figure 26 . line transient response, c in , c out = 1 f , i load = 1 ma
adp151 rev. d | page 11 of 24 theory of operation the adp151 is a n u ltra low noise, low quiescent current, low dropout linear regulator that operates from 2. 2 v to 5.5 v and can provide up to 200 ma of output current. drawing a low 2 6 5 a of quiescent current (typical) at full load makes the adp151 ideal for battery - operate d portable equipment. shutdown current consumption is typically 2 00 na. using new innovative design techniques, the adp151 provides superior noise performance for noise - sensitive analog and rf applications without the need for a noise bypass capacitor. the adp151 is also o ptimized for use with small 1 f ceramic capacitors . 08627-025 reference short-circuit, uvlo, and thermal protect shutdown r1 r2 r en vout vin gnd en figure 27 . internal block diagram internally, the adp151 consist s of a reference, an error amplifier, a feedback voltage divider , and a pmos pass transistor. o utput current is delivered via the pmos pass device , which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower tha n the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass an d increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing le ss current to pass and decreasing the output voltage. an internal pull - down resistor on the en input holds the input low when the pin is left open. the adp151 is available in 16 output voltage options , ranging from 1.1 v to 3. 3 v . the adp151 uses the en pin to enable and disable the v out pin under normal operating conditions. when en is high, v out turns on; when en is low, v out turns off. for automatic startup, en can be tied to v in .
adp151 rev. d | page 12 of 24 application s information capacitor selection output capacitor the adp151 is designed for operation with small, space - saving ceramic capacitors but can function with most commonly used capacitors as long as care is taken with regard to the effective series resistance ( esr ) value. the esr of the output capaci tor affects the stabi lity of the ldo control loop . a minimum of 1 f capacitance with an esr of 1 ? or less is recommended to ensure the stability of the adp151 . t ransient response to changes in load current is also a ffected by output capacitance . using a larger value of output capacitance improve s the transient response of the adp151 to large changes in load current. figure 28 show s the transient responses for an o utput capacitance value of 1 f . ch1 200ma ch2 50mv m20s a ch1 64ma t 10.00% 1 2 t load current v out 08627-026 figure 28 . output transient response, c out = 1 f input bypass capacitor connecting a 1 f capacitor fro m v in to gnd reduces the circuit sensitivity to the printed circuit board (pcb) layout, especially when long input traces or high source impedance are encountered. if greater than 1 f of output capacitance is required, the input capacitor should be incr eased to match it . input and output capacitor properties any good quality ceramic capacitor can be used with the adp151 , as long as it meet s the minimum capacitance and maximum esr requirements. ceramic capacitors are manufac - tured with a variety of dielec trics, each with different behavior over temperature and applied voltage. c apacitors must have a n adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions . x5r or x7r dielectrics with a voltage ratin g of 6.3 v or 10 v are recommended . y5v and z5u dielectrics are not recommended , due to their poor temperature and dc bias characteristics. figure 29 depicts the capacitance vs . voltage bias characteristic of an 0402 , 1 f , 10 v x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capa citor size and voltage rating. in general, a capacitor in a larger packag e or higher voltage rating exhibit s better stability. the temperature variation of the x5r diel ectric is ~ 15% over the ? 40c to + 85 c temperature range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 capacitance (f) voltage bias 08627-027 figure 29 . capacitance vs . voltage bias characteristic use equation 1 to determine the worst - case capacitance , accounti ng for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol i s the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40 c to +85 c is assumed to be 15% for an x5r dielectric . the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 0.94 f at 1.8 v , as shown in figure 29. substituting these values in equation 1 yields c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over t emper a - ture and tolerance at the chosen output voltage. to guarantee the performance of the adp151 , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each application.
adp151 rev. d | page 13 of 24 enable featur e the adp151 use s the en pin to enable and disable the v out pin under normal operating conditions. as shown in figure 30, when a rising voltage on en crosses the active threshold, v out turns on. when a falling voltage on en crosses t he inactive threshold, v out turns off. 3.0 2.5 2.0 1.5 0.5 1.0 0 0 0.5 1.0 1.5 2.0 2.5 v out enable voltage 08627-028 figure 30 . adp151 typical en pin operation as shown in figure 30 , the en pin has hysteresis built in. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. the en pin active/inactive thresholds are derived from the v in voltage. therefore, these thresholds vary with changing input voltage. figure 31 shows typical en active/in active thresholds when the input voltage varies from 2. 2 v to 5.5 v . 1200 1000 800 600 200 400 0 2.0 2.5 3.0 3.5 4.5 5.0 4.0 5.5 enable voltage input voltage v en rise v en fall 08627-029 figure 31 . typical en pin thresholds vs. input voltage the adp 151 uses an internal soft start to limit the inrush current when the output is enabled. the start - up time for the 3.3 v option is approximately 160 s from the time the en active threshold is crossed to when the output reaches 90% of its final value. as shown in figure 32 , the start- up time is dependent on the output voltage s etting. 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 450 400 350 300 250 200 150 100 50 enable voltage time (s) enable 3.3v 2.8v 1.1v 08627-030 figure 32 . typical start - up behavior adjustable output vo ltage operation the unique architecture of the adp151 makes an adjustable version difficult to implement in silicon. however, it is possible to create an adjustable regulator at the expense of increasing the quiescent current of the regulator circuit. the adp151 , and similar ldos, are designed to regulate the output voltage, v out , appearing at the vout pin with respect to the gnd pin. if the gnd pin is at a potential other than 0 v (for example, at v offset ), the adp151 output voltage is v out + v offset . by taking advantage of this behavior, it is possible to create an adjustable adp151 circuit that retains most of the desirable characteristics of the adp151. 08627-131 u1 1 2 3 5 4 c2 c1 v out v in vout nc vin gnd en c3 r2 v offset r1 v out = v ldo (1 + r1/r2) figure 33 . adjustable ldo using the adp151 the circuit shown in figure 33 is an example of an adjustable ldo using the adp151. a stable v offset voltage is created by passing a known current through r2. the current through r2 is determined by the voltage across r1. because the voltage across r1 is set by the voltage between vout and gnd, the current passing through r2 is fixed , and v offset is stable. to minimize the effect variation of the adp151 ground current ( i gn d ) with load, it is best to keep r1 as small as possible. it is also best to size the current passing through r2 to at least 20 greater than the maximum expected ground current. to create a 4 v ldo circuit, start with the 3.3 v version of the adp151 to mi nimize the value of r2. because v out is 4 v, v offset must be 0.7 v, and the current through r2 must be 7 ma. r1 is, therefore, 3.3 v/7 ma or 471 . a 470 standard value introduces less than 1% error. capacitor c3 is necessary to stabilize the ldo; a valu e of 1 f is adequate.
adp151 rev. d | page 14 of 24 figure 34 through figure 38 show the typical performance of the 4 v ldo circuit. the noise performance of the 4 v ldo circuit is only about 1 v worse than the same ldo used at 3.3 v because the output noise of the circuit is almost solely determined by the ldo and not the external components. the small difference may be attributed to the internally generated noise in the ldo ground current working with r2. by keeping r2 small, this noise contribution can be minimized. the psrr of the 4 v circuit is as mu ch as 10 db poorer than the 3.3 v ldo with 500 mv of headroom because the ground current of the ldo varies slightly with input voltage. this, in turn, modulates v offset and reduces t he psrr of the regulator. by increasing the headroom to 1 v, the psrr performance is nearly restored to the perf ormance of the fixed output ldo. 4.04 4.03 4.02 4.01 4.00 3.99 3.98 3.97 3.96 ?40 ?5 25 85 125 v out (v) junction temperature (c) 08627-132 load = 10ma load = 20ma load = 50ma load = 100ma load = 150ma load = 200ma figure 34 . 4 v ldo circuit, typical load regulation over temperature v out (v) v in (v) 08627-133 load = 10ma load = 20ma load = 50ma load = 100ma load = 150ma load = 200ma 4.040 4.035 4.030 4.025 4.020 4.015 4.010 4.005 4.000 4.4 5.2 5.4 4.8 4.6 5.0 figure 35 . 4 v ldo circuit, typical line regulation over load current 11 10 9 8 1 100 1k 10 noise (v rms) load current (ma) 08627-134 figure 36 . 4 v ldo circuit, typical rms output noise, 10 hz to 100 khz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08627-049 200ma 100ma 50ma 10ma figure 37 . 4 v ldo circuit, typical psrr vs. loa d current, 1 v headroom 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08627-050 200ma 100ma 50ma 10ma figure 38 . 4 v ldo circuit, typical psrr vs. load current, 500 mv headroom
adp151 rev. d | page 15 of 24 current-limit and thermal overload protection the adp151 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the adp151 is designed to current limit when the output load reaches 300 ma (typical). when the output load exceeds 300 ma, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing the output current to 0. when the junction temperature drops below 135c, the output is turned on again, and output current is restored to its nominal value. consider the case where a hard short from vout to ground occurs. at first, the adp151 current limits, so that only 300 ma is conducted into the short. if self-heating of the junction causes its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to 0. as the junction temperature cools and drops below 135c, the output turns on and conducts 300 ma into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 300 ma and 0 ma that continues as long as the short remains at the output. current- and thermal-limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125c. thermal considerations in most applications, the adp151 does not dissipate much heat due to its high efficiency. however, in applications with a high ambient temperature and a high supply voltage to output voltage differential, the heat dissipated in the package can cause the junction temperature of the die to exceed the maximum junction temperature of 125c. when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the junction temperature has decreased below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera- ture rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp151 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pins to the pcb. table 6 shows typical ja values of the 5-lead tsot, 6-lead lfcsp, and 4-ball wlcsp packages for various pcb copper sizes. table 7 shows the typical jb values of the 5-lead tsot, 6-lead lfcsp, and 4-ball wlcsp. table 6. typical ja values copper size (mm 2 ) ja (c/w) tsot wlcsp lfcsp 0 1 170 260 231.2 50 152 159 161.8 100 146 157 150.1 300 134 153 111.5 500 131 151 91.8 1 device soldered to minimum size pin traces. table 7. typical jb values model jb (c/w) tsot 43 wlcsp 58 lfcsp 28.3 the junction temperature of the adp151 can be calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: i load is the load current. i gnd is the ground current. v in and v out are input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input-to- output voltage differential, and continuous load current, there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 125c. figure 39 through figure 59 show junction temperature calculations for various ambient temperatures, load currents, v in -to-v out differentials, and areas of pcb copper.
adp151 rev. d | page 16 of 24 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) maximum junction temperature i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma 08627-031 figure 39 . wlcsp 500 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) maximum junction temperature i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma 08627-032 figure 40 . wlcsp 100 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) maximum junction temperature i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma 08627-033 figure 41 . wlcsp 50 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-034 figure 42 . wlcsp 500 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-035 figure 43 . wlcsp 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-036 figure 44 . wlcsp 50 mm 2 of pcb copper, t a = 50c
adp151 rev. d | page 17 of 24 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-037 figure 45 . tsot 500 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-038 figure 46 . tsot 100 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-039 figure 47 . tsot 50 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-040 figure 48 . tsot 500 mm 2 of pcb c opper, t a = 50c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-041 figure 49 . tsot 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-042 figure 50 . tsot 50 mm 2 of pcb copper, t a = 50c
adp151 rev. d | page 18 of 24 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-051 figure 51 . lfcsp 500 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-052 f igure 52 . lfcsp 100 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-053 figure 53 . lfcsp 50 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-055 figure 54 . lfcsp 500 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-056 figure 55 . lfcsp 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-057 figure 56 . lfcsp 50 mm 2 of pcb copper, t a = 50c
adp151 rev. d | page 19 of 24 in the case where the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction temperature rise (see figure 57 and figure 58). maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) the typical value of jb is 58c/w for the 4-ball wlcsp package, 43c/w for the 5-lead tsot package, and 28.3c/w for the 6-lead lfcsp package. 140 120 100 80 60 40 20 0 0.3 4.8 4.33.83.32.82.31.81.30.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-043 figure 57. wlcsp, t a = 85c 140 120 100 80 60 40 20 0 0.3 4.8 4.33.83.32.82.31.81.30.8 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-044 figure 58. tsot, t a = 85c 140 120 100 80 60 40 20 0 0.3 5.3 4.3 3.3 2.3 1.3 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 200ma maximum junction temperature 08627-059 figure 59. lfcsp, t a = 85c
adp151 rev. d | page 20 of 24 printed circuit b oard layout consideration s heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp151 . however, as listed in table 6 , a point of diminishing returns is eventually reached, beyond which an increas e in the co pper size does not yield significant heat dissipation benefits . place t he input capacitor as close as possible to the v in and gnd pins. pla ce t he output capacitor as close as possible to the v out and gnd pins . use of 0402 or 0603 size capacitors and resistors achieve s the smallest possible footprint solution on boards where area is limited . 08627-045 figure 60 . example tsot p cb layout 08627-046 figure 61 . example wlcsp pcb layout 08627-054 figure 62 . example lfcsp pcb layout
adp151 rev. d | page 21 of 24 outline dimensions 100708-a * compliant to jedec standards mo-193-ab with the exception of package height and thickness. 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max * 1.00 max * 0.90 max 0.70 min 2.90 bsc 5 4 1 2 3 sea ting plane figure 63 . 5 - lead thin small outline transistor package [tsot] (uj - 5) di mensions show in millimeters 01 1509- a 0.050 nom coplanarity 0.800 0.760 sq 0.720 0.230 0.200 0.170 0.280 0.260 0.240 0.660 0.600 0.540 0.430 0.400 0.370 bot t om view (bal l side up) t op view (bal l side down) a 1 2 b sea ting plane 0.40 bal l pitch bal l a1 identifier figure 64 . 4- ball w afer l evel c hip s cale p ackage [wlcsp] (cb - 4 - 3) dimensions show in millimeters 1.70 1.60 1.50 0.425 0.350 0 .275 t op view 6 1 4 3 0.35 0.30 0.25 b o t t o m v i e w pin 1 index area sea ting plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.05 max 0.02 nom 2.00 bsc sq 0.65 bsc e x p o s e d p a d pin 1 indica t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 05-04- 2010-a figure 65 . 6 - lead lead frame chip scale package [lfcsp _ud ] 2.00 mm 2.00 mm body, ultra thin, dual lead (cp - 6 - 3) dimensions show in millimeters
adp151 rev. d | page 22 of 24 ordering guide model 1 temperature range output voltage (v) 2 package description package option 3 branding adp151acbz - 1.2-r7 C 40c to +125c 1.2 4 - ball wlcsp cb -4 -3 4r adp151acbz - 1.5-r7 C 40c to +125c 1.5 4 - ball wlcsp cb -4 -3 4s adp151acbz - 1.8-r7 C 40c to +125c 1.8 4 - ball wlcsp cb -4 -3 4t adp151acbz - 2.5-r7 C 40c to +125c 2.5 4 - ball wlcsp cb -4 -3 4u adp151acbz - 2.75-r7 C 40c to +125c 2.75 4 - ball wlcsp cb -4 -3 4v adp151acbz - 2.8-r7 C 40c to +125c 2.8 4 - ball wlcsp cb -4 -3 4x adp151acbz - 2.85-r7 C 40c to +125c 2.85 4 - ball wlcsp cb -4 -3 4y adp151acbz - 3.0-r7 C 40c to +125c 3.0 4 - ball wlcsp cb -4 -3 4z adp151acbz - 3.3-r7 C 40c to +125c 3.3 4 - ball wlcsp cb -4 -3 50 adp151acbz - 2.1-r7 C 40c to +12 5c 2.1 4 - ball wlcsp cb -4 -3 5e adp151aujz - 1.2- r7 C 40c to +125c 1.2 5 - lead tsot uj -5 lf6 adp151aujz - 1.5- r7 C 40c to +125c 1.5 5 - lead tsot uj -5 lf7 adp151aujz - 1.8- r7 C 40c to +125c 1.8 5 - lead tsot uj -5 lf8 adp151aujz - 2.5- r7 C 40c to +125c 2.5 5 - lead tsot uj -5 lf9 adp151aujz - 2.8- r7 C 40c to +125c 2.8 5 - lead tsot uj -5 lfg adp151aujz - 3.0- r7 C 40c to +125c 3.0 5 - lead tsot uj -5 lfh adp151aujz - 3.3- r7 C 40c to +125c 3.3 5 - lead tsot uj -5 lfj adp151acpz - 1.2-r7 C 40c to +125c 1.2 6 - lead lfcsp_ud cp -6 -3 lf6 adp151acpz - 1.5-r7 C 40c to +125c 1.5 6 - lead lfcsp_ud cp -6 -3 lf7 adp151acpz - 1.8-r7 C 40c to +125c 1.8 6 - lead lfcsp_ud cp -6 -3 lf8 adp151acpz - 2.5-r7 C 40c to +125c 2.5 6 - lead lfcsp_ud cp -6 -3 lf9 adp151acpz - 2.7-r7 C 40c to +125c 2.7 6 - lead lfcsp_ud cp -6 -3 lkz adp151acpz - 2.8-r7 C 40c to +125 c 2.8 6 - lead lfcsp_ud cp -6 -3 lfg adp151acpz - 3.0-r7 C 40c to +125 c 3.0 6 - lead lfcsp_ud cp -6 -3 lfh adp151acpz - 3.3-r7 C 40c to +125 c 3.3 6 - lead lfcsp_ud cp -6 -3 lfj adp151ujz - redykit evaluation board kit adp151cpz - redykit evaluation board kit adp151cb - 3.3- evalz evaluation board 1 z = rohs compliant part. 2 for additional voltage options for the adp151acbz package option , contact a local analog devices, inc., sales or distribution representative . 3 the adp151acbz package option is halide free.
adp151 rev. d | page 23 of 24 notes
adp151 rev. d | page 24 of 24 notes ? 2010 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their res pective owners. d08627 - 0- 3/11(d)

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