4-1 tm file number 2793.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 CD22M3494 16 x 8 x 1 bimos-e crosspoint switch the intersil CD22M3494 is an array of 128 analog switches capable of handling signals from dc to video. because of the switch structure, input signals may swing through the total supply voltage range, v dd to v ee . each of the 128 switches may be addressed via the address input to the 7 to 128 line decoder. the state of the addressed switch is established by the signal to the data input. a low or zero input will open the switch, while a high logic level or a one will result in closure of the addressed switch when the strobe input goes high from its normally low state. any number or combination of connections may be active at one time. each connection, however, must be made or broken individually in the manner previously described. all switches may be reset by taking the reset input from a zero state to a one state and then returning it to its normal low state. cs allows crosspoint array to be cascaded for matrix expansion. features 128 analog switches ?ow r on guaranteed r on matching analog signal input voltage equal to the supply voltage wide operating voltage . . . . . . . . . . . . . . . . . . 4v to 15v parallel input addressing high latch up current . . . . . . . . . . . . . . . . . . 50ma (min) very low crosstalk pin and functionally compatible with the following types: sgs m3494 and mitel mt8816 applications pbx systems instrumentation analog and digital multiplexers video switching networks block diagram ordering information part number temp. range ( o c) package pkg. no. CD22M3494e -40 to 85 40 ld pdip e40.6 CD22M3494mq -40 to 85 44 ld plcc (mitel ld compatible) n44.65 CD22M3494sq -40 to 85 44 ld plcc (sgs ld compatible) n44.65 ax0 ax1 ax2 ax3 ay 0 ay 1 ay 2 128 1 1 strobe data reset 128 x0 - x15 y0 - y7 level shifters 128 1 7 to 128 decoder latches 16 x 8 switch array cs v ee v ss v dd data sheet january 1997
4-2 absolute maximum ratings thermal information dc supply voltage (v dd ) voltages referenced to v ee . . . . . . . . . . . . . . . . . . . . -0.5 to 16v dc supply voltage (v dd ) voltages referenced to v ss . . . . . . . . . . . . . . . . . . . . . -0.5, 16v dc input diode current, i in for v i , digital < v ss -0.5v or v i , analog < v ee -0.5v or v i > v dd 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o , digital < v ss -0.5v or v o , analog < v ee -0.5v or v o > v dd 0.5v . . . . . . . . . . . . . . . . . . . 20ma dc transmission gate current . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma power dissipation per package (po) for t a = -40 o c to 85 o c (pdip) . . . . . . . . . . . . . . . . . . . . .500mw for t a = 60 o c to 85 o c derate linearly . . . . . . .12mw/ o c to 200mw for t a = -40 o c to 85 o c (plcc). . . . . . . . . . . . . . . . . . . . . . .600mw thermal resistance (typical, note 1) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 maximum junction temperature plastic package . . . . . . . . . .150 o c maximum storage temperature range (t stg ). . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (plcc - lead tips only) operating conditions operating temperature range (t a ) package type e and q. . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c supply voltage range for t a = full package temperature range v ss = 0v, v ee = 0v, v dd . . . . . . . . . . . . . . . . . . . . . . . 4v to 15v dc input or output voltage v i or v o . . . . . . . . . . . . . . . v ee to v dd digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss to v dd caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations t a = -40 o c to 85 o c, v dd = 5v, v ss = 0v, v ee = 0v, unless otherwise speci?d parameter symbol test conditions min typ max units static controls supply current i dd v dd = 5v, logic inputs = v dd -- 2ma v dd = 15v, logic inputs = v dd -- 5ma high-level input voltage v ih v dd = 5v 2.4 (note 2) --v low-level input voltage v il - - 0.8 (note 2) v input leakage current, digital i in reset = low (note 3) - - 10 (note 4) a electrical speci?ations t a = -40 o c to 85 o c, v dd = 12v, v ss = 0v, v ee = 0v, unless otherwise specified. parameter symbol test conditions min typ max units static crosspoints on resistance r on v ss = v ee = 0v, t a =25 o c, v in =v dd /2, vx - vy = 0.2v v dd = 10v - 40 75 ? v dd = 12v - 36 65 ? on resistance r on t a = -40 o c to 85 o c, v in = v dd /2, vx -vy = 0.2v, v ss = v ee = 0v v dd = 10v - 50 75 ? v dd = 12v - 45 65 ? difference in on resistance between any two switches ? r on t a = 25 o c, v in = v dd /2, vx - vy = 0.2v, v ss = v ee = 0v, v dd = 12v -610 ? CD22M3494
4-3 difference in on resistance between any two switches ? r on t a = -40 o c to 85 o c, v in = v dd /2, vx - vy = 0.2v, v dd = 12v v ss = v ee = 0v, vdd = 12v --10 ? off-state leakage current i l |vx - vy| = 12v - - 10 (note 4) a electrical speci?ations t a = -40 o c to 85 o c, v dd = 12v, v ss = 0v, v ee = 0v, unless otherwise specified. (continued) parameter symbol test conditions min typ max units electrical speci?ations t a = 25 o c, v ss = 0v, v ee = 0v, v dd = 14v, c l = 50pf, unless otherwise speci?d. parameter test conditions min typ max units dynamic crosspoints switch i/o capacitance v in = v dd /2, f = 1mhz - - 20 pf switch feedthrough capacitance v in = v dd /2, f = 1mhz - 0.3 - pf propagation delay time (switch on) signal input to output, t phl or t plh - 5 30 ns frequency response channel on f = 20log (vx/vy) = -3db c l = 3pf, r l = 75 ? , v in = 2v p-p - 50 - mhz total harmonic, thd v in = 2v p-p , f = 1khz - 0.01 - % feedthrough channel off feedthrough = 20log (vx/vy) = f dt v in = 2v p-p , f = 1khz - -95 - db frequency for signal crosstalk, f ct attenuation of: 40db v in = 2v p-p , r l = 75 ? - 10 - mhz 110db v in = 2v p-p , r l = 1k ? || 10pf - 5 - khz control crosstalk data-input, address, or strobe to output control input = 3v p-p square wave, t r = t f = 10ns r in = 1k, r out = 10k ? || 10pf -75-mv peak electrical speci?ations t a = 25 o c, v ss = 0v, v ee = 0v, v dd = 14v, r l = 1k ? || 50pf, unless otherwise specified. parameter symbol test conditions min typ max units dynamic controls digital input capacitance c in v in = 5v, f = 1mhz - 5 - pf propagation delay time strobe to output switch turn-on t psn - 50 100 ns switch turn-off t psf - 50 100 ns data-in to output turn-on to high level t pzh - 60 100 ns turn-on to low level t pzl - 70 100 ns address to output turn-on to high level t pa n -70-ns turn-off to low level t pa f -70-ns CD22M3494
4-4 timing diagram setup time cs to strobe t cs 10 - - ns data-in to strobe t ds 10 - - ns address to strobe t as 10 - - ns hold time strobe to cs t ch 10 - - ns address to cs 10 - - ns strobe to data-in t dh 20 - - ns strobe to address t ah 10 - - ns data-in to cs 20 - - ns pulse width strobe t spw 20 - - ns reset t rpw 20 - - ns reset turn-off to output delay t phz - 70 100 ns notes: 2. operation of v ih at 2.4v or v il at 0.8v will result in much higher supply current (i dd ) than for logic inputs equal to v dd or v ss respectively. 3. reset i ih < 20 a, reset = v ih . 4. at 25 o c limit is 100na. electrical speci?ations t a = 25 o c, v ss = 0v, v ee = 0v, v dd = 14v, r l = 1k ? || 50pf, unless otherwise specified. (continued) parameter symbol test conditions min typ max units address strobe data reset 50% 50% t spw t as t ah 50% t dh t ds 50% 50% t rpw 50% 50% 90% t pa f t pzl switch output 90% 10% t pa n t phz t pzh t psf t psn 50% 50% t cs t ch cs 10% CD22M3494
4-5 to make a connection (close switch) between any two points, specify an ? address, a ? address, set ?ata high, and switch ?trobe?from low to high. to break a connection, follow this same procedure with ?ata?low. typical performance curve truth table x axis x address ax3 ax2 ax1 ax0 x switch 0000 x0 0001 x1 0010 x2 0011 x3 0100 x4 0101 x5 0110 x12 0111 x13 1000 x6 1001 x7 1010 x8 1011 x9 1100 x10 1101 x11 1110 x14 1111 x15 truth table y axis y address ay2 ay1 ay0 y switch 000y0 001y1 010y2 011y3 100y4 101y5 110y6 111y7 truth table x axis (continued) x address ax3 ax2 ax1 ax0 x switch example: data x address y address ax3 ax2 ax1 ax0 ay2 ay1 ay0 to connect switch x3 to switch y4: 1 0011100 to connect switch x6 to switch y7: 1 1000111 to break connection from x3 to y4: 0 0011100 70 60 50 40 30 20 10 0 on resistance ( ? ) -8 -6 -4 -2 0 2 4 6 8 v in (v) 25 o c -40 o c 85 o c r on vs v in at -55 o c, 25 o c and 85 o c v ee = -6v, v ss = 0v, v dd = 6v CD22M3494
4-6 pin descriptions symbol 40 lead pdip pin no. 44 lead plcc pin no. description mq sq power supplies v dd 40 44 44 positive supply. v ss 16 18 17 negative supply (digital). v ee 20 22 22 negative supply (analog). address ax0 - ax3 5, 22, 23 and 4 5, 24, 25 and 4 x address lines. these pins select one of the 16 rows of switches. see the truth table for the valid addresses. ay0 - ay2 24, 25 and 2 26, 27 and 2 y address lines. these pins select one of the 8 columns of switches. see the truth table for the valid addresses. control data 38 42 data input determines the state of the addressed switch. a high or one will close the switch. a low or zero will open the switch. strobe 18 20 strobe input enables the action defined by the data and address inputs. a low or zero results in no action. the address input must be stable before the strobe input goes to the active high level. the data input must be stable on the failing edge of the strobe. reset 3 3 master reset. a high or one on this line opens all switches. cs 36 40 39 chip select. device is selected when cs is at a high level, allows the crosspoint array to be cascaded for matrix expansion. inputs/outputs x0 - x5 x6 - x11 x12 - x15 33 - 28, 8 - 13, 27, 26, 6, 7 37 - 32 9 - 14, 31, 30, 7, 8 analog or digital inputs/outputs. these pins are the rows x0 - x15. y0 - y7 i/o 35, 37, 39, 1, 21, 19, 17 and 15 40, 41, 43, 1, 23, 21, 19 and 18 analog or digital inputs/outputs. these pins are the columns y0 - y7. pinouts CD22M3494e (pdip) top view CD22M3494mq (plcc) (mitel lead compatible) top view CD22M3494sq (plcc) (sgs lead compatible) top view data y2 y1 y0 x1 x0 nc x3 ax2 y4 ay 0 ax1 ay 1 x13 x12 x5 x4 cs v dd x2 y6 strobe y5 x11 x10 x7 x6 x15 x14 ax0 nc y7 x8 y3 ay 2 reset x9 ax3 v ss v ee 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 40 65 32144434241 4 18 19 20 21 22 23 24 25 26 27 28 7 17 16 15 12 13 14 9 10 11 8 38 37 39 35 34 33 36 31 30 29 32 y0 x1 x0 nc x3 x13 x12 x5 x4 x2 nc ax2 y4 ay 0 ax1 ay 1 y6 strobe y5 v ss v ee nc data y2 y1 cs v dd ax0 y3 ay 2 reset ax3 nc x11 x10 x7 x6 x15 x14 nc y7 x8 x9 nc 7 17 16 15 12 13 14 9 10 11 8 38 37 39 35 34 33 36 31 30 29 32 x1 x0 nc x3 x13 x12 x5 x4 x2 nc cs strobe 20 y7 18 y6 19 y5 21 v ee 22 y4 23 ax1 24 ax2 25 ay 0 26 ay 1 27 nc 28 ax0 5 nc 6 ax3 4 reset 3 ay 2 2 y3 1 v dd 44 y2 43 data 42 y1 41 y0 40 x11 x10 x7 x6 x15 x14 nc x8 x9 nc v ss CD22M3494
4-7 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 CD22M3494
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