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18mb 1x1lp, hstl, rev 1.0 1 / 30 july 19, 2002 CXK79M72C160GB sony ? ram 33/4/5 cxk79m36c160gb cxk79m18c160gb 18mb 1x1lp hstl high speed synchronous srams (256kb x 72 or 512kb x 36 or 1mb x 18) preliminary description the CXK79M72C160GB (organized as 262,144 words by 72 bits), cxk79m36c160gb (organized as 524,288 words by 36 bits), and the cxk79m18c160gb (organized as 1,048,576 words by 18 bits) are high speed cmos synchronous static rams with common i/o pins. they are manufactured in compliance with the jedec-standard 209 pin bga package pinouts defined for sigmarams. they integrate input registers, high speed ram, output registers, and a two-deep write buffer onto a single monolithic ic. single data rate (sdr) pipelined (pl) read operations and late write (lw) write operations are supported, providing a high-performance user interface. positive and negative output clocks are provided for applications requiring source- synchronous operation. all address and control input signals are registered on the rising edge of the ck differential input clock. during read operations, output data is driven valid once, from the rising edge of ck, one full cycle after the address and control signals are registered. during write operations, input data is registered once, on the rising edge of ck, one full cycle after the address and control signals are registered. output drivers are series-terminated, and output impedance is programmable via the zq control pin. when an external resistor rq is connected between zq and v ss , the impedance of the sram?s output drivers is set to ~rq/5. 300 mhz operation (300 mbps) is obtained from a single 1.8v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol. features 3 speed bins cycletime/data access time -33 3.3ns / 1.8ns -4 4.0ns / 2.1ns -5 5.0ns / 2.3ns single 1.8v power supply (v dd ): 1.7v (min) to 1.95v (max) dedicated output supply voltage (v ddq ): 1.4v (min) to v dd (max) hstl-compatible i/o interface with dedicated input reference voltage (v ref ): v ddq /2 typical common i/o single data rate (sdr) data transfers pipelined (pl) read operations late write (lw) write operations burst capability with internally controlled linear burst address sequencing burst length of two, three, or four, with automatic address wrap full read/write data coherency byte write capability differential input clocks (ck and ck ) data-referenced output clocks (cq1, cq1 , cq2, cq2 ) programmable output driver impedance via dedicated control pin (zq) depth expansion capability (2 or 4 banks) via programmable chip enables (e2, e3, ep2, ep3) jtag boundary scan (subset of ieee standard 1149.1) 209 pin (11x19), 1mm pitch, 14mm x 22mm ball grid array (bga) package
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 2 / 30 july 19, 2002 256kb x 72 pin assignment (top view) 1234567891011 a dqg dqg a e2 a adv a e3 a dqb dqb b dqg dqg bc bg nc (x36) w abb bf dqb dqb c dqg dqg bh bd nc (144m) e1 nc (x18) be ba dqb dqb d dqg dqg v ss v ref nc mcl nc v ref v ss dqb dqb e dqg dqc v ddq v ddq v dd v dd v dd v ddq v ddq dqf dqb f dqc dqc v ss v ss v ss zq v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss ep3 v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd mcl v dd v ddq v ddq dqf dqf kcq2cq2 ck ck v ss mcl v ss nc nc cq1 cq1 l dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss mch v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqd dqh v ddq v ddq v dd v dd v dd v ddq v ddq dqa dqe t dqd dqd v ss v ref nc mcl nc v ref v ss dqe dqe u dqd dqd nc a nc (72m) anc (36m) ancdqedqe v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 3 / 30 july 19, 2002 512kb x 36 pin assignment (top view) 1234567891011 a nc nc a e2 a adv a e3 a dqb dqb bncncbc nc a (x36) w abb nc dqb dqb c ncncnc bd nc (144m) e1 nc (x18) nc ba dqb dqb dncncv ss v ref nc mcl nc v ref v ss dqb dqb e nc dqc v ddq v ddq v dd v dd v dd v ddq v ddq nc dqb f dqc dqc v ss v ss v ss zq v ss v ss v ss nc nc g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqc dqc v ss v ss v ss ep3 v ss v ss v ss nc nc j dqc dqc v ddq v ddq v dd mcl v dd v ddq v ddq nc nc kcq2cq2 ck ck v ss mcl v ss nc nc cq1 cq1 lncncv ddq v ddq v dd mch v dd v ddq v ddq dqa dqa mncncv ss v ss v ss mch v ss v ss v ss dqa dqa nncncv ddq v ddq v dd mch v dd v ddq v ddq dqa dqa pncncv ss v ss v ss mcl v ss v ss v ss dqa dqa r dqd nc v ddq v ddq v dd v dd v dd v ddq v ddq dqa nc t dqd dqd v ss v ref nc mcl nc v ref v ss nc nc u dqd dqd nc a nc (72m) anc (36m) a ncncnc v dqd dqd a a a a1 a a a nc nc w dqd dqd tms tdi a a0 a tdo tck nc nc
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 4 / 30 july 19, 2002 1mb x 18 pin assignment (top view) 1234567891011 a nc nc a e2 a adv a e3 a nc nc bncncbb nc a (x36) w a ncncncnc c ncncncncnc (144m) e1 a (x18) nc ba nc nc dncncv ss v ref nc mcl nc v ref v ss nc nc e nc dqb v ddq v ddq v dd v dd v dd v ddq v ddq nc nc f dqb dqb v ss v ss v ss zq v ss v ss v ss nc nc g dqb dqb v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqb dqb v ss v ss v ss ep3 v ss v ss v ss nc nc j dqb dqb v ddq v ddq v dd mcl v dd v ddq v ddq nc nc kcq2cq2 ck ck v ss mcl v ss nc nc cq1 cq1 lncncv ddq v ddq v dd mch v dd v ddq v ddq dqa dqa mncncv ss v ss v ss mch v ss v ss v ss dqa dqa nncncv ddq v ddq v dd mch v dd v ddq v ddq dqa dqa pncncv ss v ss v ss mcl v ss v ss v ss dqa dqa rncncv ddq v ddq v dd v dd v dd v ddq v ddq dqa nc tncncv ss v ref nc mcl nc v ref v ss nc nc u ncncnc a nc (72m) anc (36m) a ncncnc v nc nc a a a a1 a a a nc nc w nc nc tms tdi a a0 a tdo tck nc nc
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 5 / 30 july 19, 2002 pin description symbol type quantity description a input x72 = 16 x36 = 17 x18 = 18 address inputs - registered on the rising edge of ck. a1, a0 input 2 address inputs 1,0 - registered on the rising edge of ck. initialize burst counter. dqa, dqb dqc, dqd dqe, dqf dqg, dqh i/o x72 = 72 x36 = 36 x18 = 18 data inputs / outputs - registered on the rising edge of ck during write operations. driven from the rising edge of ck during read operations. dqa - indicates data byte a dqb - indicates data byte b dqc - indicates data byte c dqd - indicates data byte d dqe - indicates data byte e dqf - indicates data byte f dqg - indicates data byte g dqh - indicates data byte h ck, ck input 2 differential input clocks cq1, cq1 cq2, cq2 output 4 output clocks e1 input 1 chip enable control input - registered on the rising edge of ck. e1 = 0 enables the device to accept read and write commands. e1 = 1 disables the device. see the clock truth table section for further information. e2, e3 input 2 programmable chip enable control inputs - registered on the rising edge of ck. see the clock truth table and depth expansion sections for further information. ep2, ep3 input 2 programmable chip enable active-level select inputs - these pins must be tied ?high? or ?low? at power-up. see the clock truth table and depth expansion sec- tions for further information. adv input 1 address advance control input - registered on the rising edge of ck. adv = 0 loads a new address and begins a new operation when the device is enabled. adv = 1 increments the address and continues the previous operation when the device is enabled. see the clock truth table section for further information. w input 1 write enable control input - registered on the rising edge of ck. w = 0 specifies a write operation when adv = 0 and the device is enabled. w = 1 specifies a read operation when adv = 0 and the device is enabled. see the clock truth table section for further information. ba ,bb ,bc bd ,be ,bf bg ,bh input x72 = 8 x36 = 4 x18 = 2 byte write enable control inputs - registered on the rising edge of ck. ba = 0 specifies write data byte a during a write operation bb = 0 specifies write data byte b during a write operation bc = 0 specifies write data byte c during a write operation bd = 0 specifies write data byte d during a write operation be = 0 specifies write data byte e during a write operation bf = 0 specifies write data byte f during a write operation bg = 0 specifies write data byte g during a write operation bh = 0 specifies write data byte h during a write operation see the clock truth table section for further information. zq input 1 output impedance control resistor input - this pin must be tied to v ss through an external resistor rq at power-up. output driver impedance is set to one-fifth the value of rq, nominally. see the output driver impedance control section for further information.
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 6 / 30 july 19, 2002 v dd 14 1.8v core power supply - core supply voltage. v ddq 24 output power supply - output buffer supply voltage. v ref 4 input reference voltage - input buffer threshold voltage. v ss 30 ground tck input 1 jtag clock tms input 1 jtag mode select - weakly pulled ?high? internally. tdi input 1 jtag data in - weakly pulled ?high? internally. tdo output 1 jtag data out mcl *input* 5 must connect ?low? - may not be actual input pins. mch *input* 3 must connect ?high? - may not be actual input pins. nc x72 = 13 x36 = 52 x18 = 71 no connect - these pins are true no-connects, i.e. there is no internal chip connection to these pins. they can be left unconnected or tied directly to v dd ,v ddq ,orv ss . symbol type quantity description
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 7 / 30 july 19, 2002 clock truth table notes : 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. ?***? indicates that the dq input requirement or output state and the cq output state are determined by the previous operation. 3. if e2 = ep2 and e3 = ep3 then e = ?t? else e = ?f?. 4. if one or more bx = 0 then b = ?t? else b = ?f?. 5. dqs are tri-stated in response to bank deselect, deselect, and write commands, one full cycle after the command is sampled. 6. cqs are tri-stated in response to bank deselect commands only, one full cycle after the command is sampled. 7. up to three (3) continue operations may be initiated after a read or write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. if a fourth (4th) continue operation is initiated, the internal ad- dress wraps back to the initial external (base) address. ck e1 (t n ) e (t n ) adv (t n ) w (t n ) b (t n ) previous operation current operation dq/cq (t n ) dq/cq (t n+1 ) x f 0 x x x bank deselect *** hi-z x x 1 x x bank deselect bank deselect (continue) hi-z hi-z 1 t 0 x x x deselect *** hi-z/cq x x 1 x x deselect deselect (continue) hi-z/cq hi-z/cq 0t 0 0t x write loads new address stores dqx if bx =0 *** d1/cq 0t 0 0f x write (abort) loads new address no data stored *** x/cq x x 1 x t write write continue increments address by 1 stores dqx if bx =0 d1/cq d2/cq x x 1 x f write write continue (abort) increments address by 1 no data stored d1/cq x/cq 0t 0 1x x read loads new address *** q1/cq x x 1 x x read read continue increments address by 1 q1/cq q2/cq
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 8 / 30 july 19, 2002 state diagram notes : 1. the notation ?x,x,x,x? controlling the state transitions above indicate the states of inputs e1 ,e,adv,andw respectively. 2. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 3. if e2 = ep2 and e3 = ep3 then e = ?t? else e = ?f?. deselect bank deselect read read write write continue x,f,0,x or x,x,1,x continue x,f,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x or x,x,1,x 0,t,0,0 0,t,0,1 0,t,0,0 0,t,0,1 x,f,0,x x,f,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,0 0,t,0,1 1,t,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,1 0,t,0,0
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 9 / 30 july 19, 2002 ? burst (continue) operations burst operations follow the linear burst address sequence depicted in the table below: up to three (3) continue operations may be initiated after a read or write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. if a fourth (4th) continue operation is initiated, the internal ad- dress wraps back to the initial external (base) address. depth expansion depth expansion in these devices is supported via programmable chip enables e2 and e3. the active levels of e2 and e3 are programmable through the static inputs ep2 and ep3 respectively. when ep2 is tied ?high?, e2 functions as an active-high input. when ep2 is tied ?low?, e2 functions as an active-low input. similarly, when ep3 is tied ?high?, e3 functions as an active-high input. and, when ep3 is tied ?low?, e3 functions as an active-low input. the programmability of e2 and e3 allows four banks of depth expansion to be accomplished with no additional logic. by programming e2 and e3 of four devices in a binary sequence (00, 01, 10, 11), and by driving e2 and e3 with external address signals, the four devices can be made to look like one larger device. when these devices are deselected via chip enable e1 , the output clocks continue to toggle. however, when these devices are deselected via programmable chip enables e2 or e3, the output clocks are forced to a hi-z state. see the clock truth table for further information. output driver impedance control the impedance of the data and clock output drivers in these devices can be controlled via the static input zq. when an ex- ternal impedance matching resistor (rq) is connected between zq and v ss , output driver impedance is set to one-fifth the value of the resistor, nominally. see the dc electrical characteristics section for further information. output driver impedance is updated whenever the data output drivers are in an inactive (high-z) state. see the clock truth table section for information concerning which commands deactivate the data output drivers. at power up, 8192 clock cycles followed by any command that deactivates the data output drivers are required to ensure that the output impedance has reached the desired value. note : the impedance of the output drivers will drift somewhat due to changes in temperature and voltage. consequently, during operation, the output drivers should be deactivated periodically in order to update the output impedance and ensure that it remains within specified tolerances. power-up sequence for reliability purposes, sony recommends that power supplies power up in the following sequence: v ss ,v dd ,v ddq ,v ref , and inputs. v ddq should never exceed v dd . if this power supply sequence cannot be met, a large bypass diode may be re- quired between v dd and v ddq . please contact sony memory application department for further information. a(1:0) sequence key 1st (base) address 00 01 10 11 a1, a0 2nd address 01 10 11 00 (a1 xor a0), a0 3rd address 10 11 00 01 a1 ,a0 4th address 11 00 01 10 (a1 xor a0) ,a0
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 10 / 30 july 19, 2002 absolute maximum ratings note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. bga package thermal characteristics i/o capacitance (t a =25 o c, f = 1 mhz) note : these parameters are sampled and are not 100% tested. parameter symbol rating units supply voltage v dd -0.5 to +2.5 v output supply voltage v ddq -0.5 to +2.3 v input voltage (address, control, data, clock) v in -0.5 to v ddq +0.5 (2.3v max) v input voltage (ep2, ep3, mcl, mch) v min -0.5 to v dd +0.5 (2.5v max) v input voltage (tck, tms, tdi) v tin -0.5 to v dd +0.5 (2.5v max) v operating temperature t a 0to85 c junction temperature t j 0to110 c storage temperature t stg -55 to 150 c parameter symbol rating units junction to case temperature jc 3.6 c/w parameter symbol test conditions min max units input capacitance address c in v in =0v --- 3.5 pf control c in v in =0v --- 3.5 pf ck clock c kin v kin =0v --- 4.0 pf output capacitance data c out v out =0v --- 4.5 pf cq clock c out v out =0v --- 4.5 pf
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 11 / 30 july 19, 2002 dc recommended operating conditions (v ss =0v,t a =0to85 o c) 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component. 2. v ih (max) ac = v ddq + 0.9v for pulse widths less than one-quarter of the cycle time (t cyc /4). 3. v il (min) ac = -0.9v for pulse widths less than one-quarter of the cycle time (t cyc /4). parameter symbol min typ max units notes supply voltage v dd 1.7 1.8 1.95 v output supply voltage v ddq 1.4 --- v dd v input reference voltage v ref v ddq /2 - 0.1 v ddq /2 v ddq /2 + 0.1 v 1 input high voltage (address, control, data) v ih v ref + 0.2 --- v ddq +0.3 v 2 input low voltage (address, control, data) v il -0.3 --- v ref -0.2 v 3 input high voltage (ep2, ep3, mch) v mih v ref + 0.3 --- v dd +0.3 v input low voltage (ep2, ep3, mcl) v mil -0.3 --- v ref -0.3 v clock input signal voltage v kin -0.3 --- v ddq +0.3 v 2,3 clock input differential voltage v dif 0.4 --- v ddq +0.6 v clock input common mode voltage v cm v ddq /2 - 0.1 v ddq /2 v ddq /2 + 0.1 v
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 12 / 30 july 19, 2002 dc electrical characteristics (v dd =1.8v 0.1v, v ss =0v,t a =0to85 o c) 1. for maximum output drive (i.e. minimum impedance), the zq pin can be tied directly to v ss . 2. for minimum output drive (i.e. minimum impedance), the zq pin can be left unconnected or tied directly to v ddq . parameter symbol test conditions min typ max units notes input leakage current (address, control, clock) i li v in =v ss to v ddq -5 --- 5 ua input leakage current (ep2, ep3) i mli1 v min =v ss to v dd -10 --- 10 ua input leakage current (mch) i mli2 v min =v mih (min) to v dd -10 --- 10 ua input leakage current (mcl) i mli3 v min =v ss to v mil (min) -10 --- 10 ua output leakage current i lo v out =v ss to v ddq -10 --- 10 ua average power supply operating current (x72) i dd-33 i dd-4 i dd-5 i out =0ma v in =v ih or v il --- --- --- --- --- --- 750 650 550 ma average power supply operating current (x36) i dd-33 i dd-4 i dd-5 i out =0ma v in =v ih or v il --- --- --- --- --- --- 580 500 420 ma average power supply operating current (x18) i dd-33 i dd-4 i dd-5 i out =0ma v in =v ih or v il --- --- --- --- --- --- 490 430 380 ma power supply deselect operating current i dd2 i out =0ma v in =v ih or v il --- --- 250 ma output high voltage v oh i oh =-7.0ma rq = 250 ? v ddq - 0.4 --- --- v output low voltage v ol i ol =7.0ma rq = 250 ? --- --- 0.4 v output driver impedance r out v oh ,v ol =v ddq /2 rq < 150 ? --- --- 35 (30*1.15) ? 1 v oh ,v ol =v ddq /2 150 ? rq 300 ? (rq/5)* 0.85 rq/5 (rq/5)* 1.15 ? v oh ,v ol =v ddq /2 rq > 300 ? 51 (60*0.85) --- --- ? 2
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 13 / 30 july 19, 2002 ac electrical characteristics ( v dd =1.8v 0.1v, v ss =0v,t a =0to85 o c) all parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted. 1. these parameters apply to control inputs e1 , e2, e3, adv, w ,andbx . 2. these parameters are guaranteed by design through extensive corner lot characterization. 3. these parameters are measured at 50mv from steady state voltage. parameter symbol -33 -4 -5 units notes minmaxminmaxminmax input clock cycle time t khkh 3.3 --- 4.0 --- 5.0 --- ns input clock high pulse width t khkl 1.3 --- 1.5 --- 2.0 --- ns input clock low pulse width t klkh 1.3 --- 1.5 --- 2.0 --- ns address input setup time t avkh 0.7 --- 0.8 --- 1.0 --- ns address input hold time t khax 0.4 --- 0.5 --- 0.5 --- ns control input setup time t bvkh 0.7 --- 0.8 --- 1.0 --- ns 1 control input hold time t khbx 0.4 --- 0.5 --- 0.5 --- ns 1 data input setup time t dvkh 0.7 --- 0.8 --- 1.0 --- ns data input hold time t khdx 0.4 --- 0.5 --- 0.5 --- ns input clock high to output data valid t khqv --- 1.8 --- 2.1 --- 2.3 ns input clock high to output data hold t khqx 0.5 --- 0.5 --- 0.5 --- ns 2 input clock high to output data low-z t khqx1 0.5 --- 0.5 --- 0.5 --- ns 2,3 input clock high to output data high-z t khqz --- 1.8 --- 2.1 --- 2.3 ns 2,3 input clock high to output clock high t khch 0.5 1.8 0.5 2.1 0.5 2.3 ns input clock high to output clock low-z t khcx1 0.5 --- 0.5 --- 0.5 --- ns 2,3 input clock high to output clock high-z t khcz --- 1.8 --- 2.1 --- 2.3 ns 2,3 output clock high to output data valid t chqv --- 0.4 --- 0.5 --- 0.6 ns 2 output clock high to output data hold t chqx -0.4 --- -0.5 --- -0.6 --- ns 2 output clock high pulse width t chcl t khkl 0.2 t khkl 0.2 t khkl 0.2 ns 2 output clock low pulse width t clch t klkh 0.2 t klkh 0.2 t klkh 0.2 ns 2
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 14 / 30 july 19, 2002 ac electrical characteristics (note) the two ac timing parameters listed below are tested according to specific combinations of output clocks (cqs) and out- put data (dqs): 1. t chqv - output clock high to output data valid (max) 2. t chqx - output clock high to output data hold (min) the specific cq / dq combinations are defined as follows: 256kb x 72 512kb x 36 1mb x 18 cqs dqs cqs dqs cqs dqs 1k,2k 1a,2a,1b,2b,1c,2c, 1d, 2d, 1e, 2e, 1f, 2f, 1g,2g,1h,2h,1j,2j,1l, 2l, 1m, 2m, 1n, 2n, 1p, 2p, 2r, 1r, 1t, 2t, 1u, 2u, 1v, 2v, 1w, 2w 1k, 2k 2e, 1f, 2f, 1g, 2g, 1h, 2h,1j,2j,1r,1t,2t, 1u, 2u, 1v, 2v, 1w, 2w 1k, 2k 2e, 1f, 2f, 1g, 2g, 1h, 2h, 1j, 2j 10k, 11k 10a, 11a, 10b, 11b, 10c, 11c, 10d, 11d, 11e, 10e, 10f, 11f, 10g, 11g, 10h, 11h, 10j, 11j, 10l, 11l, 10m, 11m, 10n, 11n, 10p, 11p, 10r, 11r, 10t, 11t, 10u, 11u, 10v, 11v, 10w, 11w 10k, 11k 10a, 11a, 10b, 11b, 10c, 11c, 10d, 11d, 11e, 10l, 11l, 10m, 11m, 10n, 11n, 10p, 11p, 10r 10k, 11k 10l, 11l, 10m, 11m, 10n, 11n, 10p, 11p, 10r
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 15 / 30 july 19, 2002 ac test conditions (v ddq = 1.8v) (v dd =1.8v0.1v,v ddq =1.8v0.1v,t a =0to85 c ) parameter symbol conditions units notes input reference voltage v ref 0.9 v input high level v ih 1.4 v input low level v il 0.4 v input rise & fall time 2.0 v/ns input reference level 0.9 v clock input high voltage v kih 1.4 v v dif =1.0v clock input low voltage v kil 0.4 v v dif =1.0v clock input common mode voltage v cm 0.9 v clock input rise & fall time 2.0 v/ns clock input reference level ck/ck cross v output reference level 0.9 v output load conditions rq = 250 ? see figure 1 below dq 0.9 v figure 1: ac test output load (v ddq = 1.8v) 50 ? 50 ? 5pf 16.7 ? 0.9 v 50 ? 50 ? 5pf 16.7 ? 16.7 ?
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 16 / 30 july 19, 2002 ac test conditions (v ddq = 1.5v) (v dd =1.8v0.1v,v ddq =1.5v0.1v,t a =0to85 c ) parameter symbol conditions units notes input reference voltage v ref 0.75 v input high level v ih 1.25 v input low level v il 0.25 v input rise & fall time 2.0 v/ns input reference level 0.75 v clock input high voltage v kih 1.25 v v dif =1.0v clock input low voltage v kil 0.25 v v dif =1.0v clock input common mode voltage v cm 0.75 v clock input rise & fall time 2.0 v/ns clock input reference level ck/ck cross v output reference level 0.75 v output load conditions rq = 250 ? see figure 2 below dq 0.75 v figure 2: ac test output load (v ddq = 1.5v) 50 ? 50 ? 5pf 16.7 ? 0.75 v 50 ? 50 ? 5pf 16.7 ? 16.7 ?
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 17 / 30 july 19, 2002 one bank read-write-read timing diagram note : in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the application, one deselect op- eration may be sufficient. note : e1 = ep1 and e2 = ep2 in this example (not shown). a2 a3 a4 a5 a e1 dq q11 d32 d41 q12 q21 t khax t avkh t khbx t bvkh d31 t khdx t dvkh a1 q51 read read continue read deselect deselect write write continue write read deselect deselect figure 3 ck cq cq adv w t khch t chcl t clch t khkh t khkl t klkh bx (continue) t khqx1 t khqz t khqv t khqx t chqx t chqv ck
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 18 / 30 july 19, 2002 two bank read-write-read timing diagram note : in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the application, one deselect op- eration may be sufficient. note : bank 1 ep1 = ?low?, bank 2 ep1 ?high?, and bank 1 and bank 2 e2 = ep2 in this example (not shown). a2 a3 a4 a5 a e1 dq (b1) q11 d41 q12 a1 b-deselect r-continue b-deselect read b-deselect deselect write b-deselect w-continue b-deselect read deselect b-deselect deselect figure 4 ck cq (b1) cq (b1) adv w bx e2 b1: b2: read b-deselect deselect b-deselect b-deselect write b-deselect b-deselect dq (b2) d32 q21 d31 q51 cq (b2) cq (b2) t khcz t khcx1 ck
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 19 / 30 july 19, 2002 test mode description these devices provide a jtag test access port (tap) and boundary scan interface using a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism for testing the interconnect between master (processor, con- troller, etc.), srams, other components, and the printed circuit board. in conformance with a subset of ieee std. 1149.1, these devices contain a tap controller and four tap registers. the tap registers consist of one instruction register and three data registers (id, bypass, and boundary scan registers). the tap consists of the following four signals: tck: test clock induces (clocks) tap controller state transitions. tms: test mode select inputs commands to the tap controller. sampled on the rising edge of tck. tdi: test data in inputs data serially to the tap registers. sampled on the rising edge of tck. tdo: test data out outputs data serially from the tap registers. driven from the falling edge of tck. disabling the tap when jtag is not used, tck should be tied ?low? to prevent clocking the sram. tms and tdi should either be tied ?high? through a pull-up resistor or left unconnected. tdo should be left unconnected. note : operation of the tap does not disrupt normal sram operation except when the extest-a or sample-z instruc- tion is selected. consequently, tck, tms, and tdi can be controlled any number of ways without adversely affecting the functionality of the device. jtag dc recommended operating conditions (v dd =1.8v0.1v,t a =0to85 c ) jtag ac test conditions (v dd =1.8v0.1v,t a =0to85 c ) parameter symbol test conditions min max units jtag input high voltage (tck, tms, tdi) v tih --- v dd /2 + 0.3 v dd +0.3 v jtag input low voltage (tck, tms, tdi) v til --- -0.3 v dd /2 - 0.3 v jtag output high voltage (tdo) v toh i toh = -100ua v dd -0.1 --- v jtag output low voltage (tdo) v tol i tol = 100ua --- 0.1 v jtag output high voltage (tdo) v toh i toh =-8ma v dd -0.4 --- v jtag output low voltage (tdo) v tol i tol =8ma --- 0.4 v jtag input leakage current i tli v tin =v ss to v dd -20 10 ua jtag output leakage current i tlo v tout =v ss to v dd -10 10 ua parameter symbol conditions units notes jtag input high level v tih 1.8 v jtag input low level v til 0.0 v jtag input rise & fall time 1.0 v/ns jtag input reference level 0.9 v jtag output reference level 0.9 v jtag output load condition see fig. 1 (page 15)
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 20 / 30 july 19, 2002 jtag ac electrical characteristics jtag timing diagram parameter symbol min max units tck cycle time t thth 50 ns tck high pulse width t thtl 20 ns tck low pulse width t tlth 20 ns tms setup time t mvth 5ns tms hold time t thmx 5ns tdi setup time t dvth 5ns tdi hold time t thdx 5ns capture setup time (address, control, data, clock) t cs 5ns capture hold time (address, control, data, clock) t ch 5ns tck low to tdo valid t tlqv 10 ns tck low to tdo hold t tlqx 0ns figure 5 t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlqv t tlqx tck tms tdi tdi tdo
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 21 / 30 july 19, 2002 tap controller the tap controller is a 16-state state machine that controls access to the various tap registers and executes the operations associated with each tap instruction (see figure 7 below). state transitions are controlled by tms and occur on the rising edge of tck. the tap controller enters the ?test-logic reset? state in one of two ways: 1. at power up. 2. when a logic ?1? is applied to tms for at least 5 consecutive rising edges of tck. the tdi input receiver is sampled only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. the tdo output driver is active only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. tap controller state diagram figure 6 test-logic reset run-test / idle select dr-scan select ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 22 / 30 july 19, 2002 tap registers tap registers are serial shift registers that capture serial input data (from tdi) on the rising edge of tck, and drive serial output data (to tdo) on the subsequent falling edge of tck. they are divided into two groups: ?instruction registers? (ir), which are manipulated via the ?ir? states in the tap controller, and ?data registers? (dr), which are manipulated via the ?dr? states in the tap controller. instruction register (ir - 3 bits) the instruction register stores the various tap instructions supported by these devices. it is loaded with the idcode in- struction at power-up, and when the tap controller is in the ?test-logic reset? and ?capture-ir? states. it is inserted be- tween tdi and tdo when the tap controller is in the ?shift-ir? state, at which time it can be loaded with a new instruction. however, newly loaded instructions are not executed until the tap controller has reached the ?update-ir? state. the instruction register is 3 bits wide, and is encoded as follows: bit 0 is the lsb of the instruction register, and bit 2 is the msb. when the instruction register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. code (2:0) instruction description 000 extest-a loads the individual logic states of all signals composing the sram?s i/o ring into the boundary scan register when the tap controller is in the ?capture-dr? state, and inserts the b-scan register between tdi and tdo when the tap controller is in the ?shift-dr? state. also enables the sram?s data and clock output drivers, and moves the contents of the b-scan register associated with the data and clock output signals to the input side of the sram?s out- put register. the sram?s input clock can then be used to transfer the b-scan register contents directly to the data and clock output pins (the input clock controls the sram?s output regis- ter). note that newly captured and/or shifted b-scan register contents do not appear at the input side of the sram?s output register until the tap controller has reached the ?update- dr? state. see the boundary scan register description for more information. 001 idcode loads a predefined device- and manufacturer-specific identification code into the id register when the tap controller is in the ?capture-dr? state, and inserts the id register between tdi and tdo when the tap controller is in the ?shift-dr? state. see the id register description for more information. 010 sample-z loads the individual logic states of all signals composing the sram?s i/o ring into the boundary scan register when the tap controller is in the ?capture-dr? state, and inserts the b-scan register between tdi and tdo when the tap controller is in the ?shift-dr? state. also disables the sram?s data and clock output drivers. see the boundary scan register description for more information. 011 private do not use. reserved for manufacturer use only. 100 sample loads the individual logic states of all signals composing the sram?s i/o ring into the boundary scan register when the tap controller is in the ?capture-dr? state, and inserts the boundary scan register between tdi and tdo when the tap controller is in the ?shift-dr? state. see the boundary scan register description for more information. 101 private do not use. reserved for manufacturer use only. 110 private do not use. reserved for manufacturer use only. 111 bypass loads a logic ?0? into the bypass register when the tap controller is in the ?capture-dr? state, and inserts the bypass register between tdi and tdo when the tap controller is in the ?shift-dr? state. see the bypass register description for more information.
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 23 / 30 july 19, 2002 bypass register (dr - 1 bit) the bypass register is one bit wide, and provides the minimum length serial path between tdi and tdo. it is loaded with a logic ?0? when the bypass instruction has been loaded in the instruction register and the tap controller is in the ?cap- ture-dr? state. it is inserted between tdi and tdo when the bypass instruction has been loaded into the instruction reg- ister and the tap controller is in the ?shift-dr? state. id register (dr - 32 bits) the id register is loaded with a predetermined device- and manufacturer-specific identification code when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?shift-dr? state. the id register is 32 bits wide, and is encoded as follows: bit 0 is the lsb of the id register, and bit 31 is the msb. when the id register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. boundary scan register (dr - 123 bits for x72, 84 bits for x36, 65 bits for x18) the boundary scan register is equal in length to the number of active signal connections to the sram (excluding the tap pins) plus a number of place holder locations reserved for functional and/or density upgrades. it is loaded with the individual logic states of all signals composing the sram?s i/o ring when the extest-a, sample, or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the extest-a, sample, or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?shift-dr? state. the boundary scan register contains the following bits: note :ckandck are connected to a differential input receiver that generates a single-ended input clock to these devices. therefore, in order to capture deterministic values for these signals in the boundary scan register, they must be at opposite logic levels when sampled. note : when an external resistor rq is connected between the zq pin and v ss , the value of the zq signal captured in the boundary scan register is non-deterministic. device revision number (31:28) part number (27:12) sony id (11:1) start bit (0) 256kb x 72 xxxx 0000 0000 0101 0101 0000 1110 001 1 512kb x 36 xxxx 0000 0000 0101 1001 0000 1110 001 1 1mb x 18 xxxx 0000 0000 0101 1111 0000 1110 001 1 256kb x 72 512kb x 36 1mb x 18 dqx 72 dqx 36 dqx 18 a, a1, a0 18 a, a1, a0 19 a, a1, a0 20 ck, ck 2ck,ck 2ck,ck 2 cq1, cq2, cq1 ,cq2 4 cq1, cq2, cq1 ,cq2 4 cq1, cq2, cq1 ,cq2 4 e1 , adv, w ,bx 11 e1 , adv, w ,bx 7e1 , adv, w ,bx 5 e2, e3, ep2, ep3 4 e2, e3, ep2, ep3 4 e2, e3, ep2, ep3 4 zq 1 zq 1 zq 1 place holder 11 place holder 11 place holder 11
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 24 / 30 july 19, 2002 boundary scan register bit order assignments the tables below depict the order in which the bits are arranged in the boundary scan register. bit 1 is the lsb and bit 123 (for x72) or bit 84 (for x36) or bit 65 (for x18) is the msb. when the boundary scan register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. note 1 : nc and mcl pins at pad locations 5c, 5u, 7u, 6d, 6k, 6p, and 6t are connected to v ss internally, regardless of pin connection externally. note 2 : mch pin at pad location 6n is connected to v dd internally, regardless of pin connection externally. 256kb x 72 bit signal pad bit signal pad bit signal pad bit signal pad 1nc (1) 5c 36 dqf 11g 71 dqg 1a 106 dqd 2v 2nc (1) 5u 37 dqf 10f 72 dqg 1b 107 dqd 1v 3nc (1) 7u 38 dqf 11f 73 dqg 2b 108 dqd 1w 4mcl (1) 6d 39 dqf 10e 74 dqg 1c 109 dqd 2w 5mcl (1) 6k 40 dqb 11e 75 dqg 2c 110 mcl 6j 6mcl (1) 6p 41 dqb 10d 76 dqg 1d 111 a 3v 7mcl (1) 6t 42 dqb 11d 77 dqg 2d 112 a 4v 8mch (2) 6n 43 dqb 10c 78 dqg 1e 113 a 4u 9 mch 6m 44 dqb 11c 79 dqc 2e 114 a 5v 10 mch 6l 45 dqb 10b 80 dqc 1f 115 a 6u 11 dqe 10w 46 dqb 11b 81 dqc 2f 116 a 5w 12 dqe 11w 47 dqb 11a 82 dqc 1g 117 a0 6w 13 dqe 11v 48 dqb 10a 83 dqc 2g 118 a1 6v 14 dqe 10v 49 bf 9b 84 dqc 1h 119 a 7v 15 dqe 11u 50 ba 9c 85 dqc 2h 120 a 8v 16 dqe 10u 51 bb 8b 86 dqc 1j 121 a 7w 17 dqe 11t 52 be 8c 87 dqc 2j 122 a 8u 18 dqe 10t 53 ep3 6h 88 cq2 1k 123 a 9v 19 dqe 11r 54 ep2 6g 89 ck 3k 20 dqa 10r 55 a 9a 90 ck 4k 21 dqa 11p 56 e3 8a 91 cq2 2k 22 dqa 10p 57 a 7b 92 dqh 2l 22 dqa 11n 58 a 7a 93 dqh 1l 24 dqa 10n 59 w 6b 94 dqh 2m 25 dqa 11m 60 adv 6a 95 dqh 1m 26 dqa 10m 61 e1 6c 96 dqh 2n 27 dqa 11l 62 a 5a 97 dqh 1n 28 dqa 10l 63 e2 4a 98 dqh 2p 29 cq1 11k 64 a 3a 99 dqh 1p 30 cq1 10k 65 zq 6f 100 dqh 2r 31 dqf 10j 66 bd 4c 101 dqd 1r 32 dqf 11j 67 bg 4b 102 dqd 2t 33 dqf 10h 68 bh 3c 103 dqd 1t 34 dqf 11h 69 bc 3b 104 dqd 2u 35 dqf 10g 70 dqg 2a 105 dqd 1u
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 25 / 30 july 19, 2002 . note 1 : nc and mcl pins at pad locations 5c, 5u, 7u, 6d, 6k, 6p, and 6t are connected to v ss internally, regardless of pin connection externally. note 2 : mch pin at pad location 6n is connected to v dd internally, regardless of pin connection externally. 512kb x 36 bitsignal pad bitsignal pad bitsignal pad 1nc (1) 5c 36 e3 8a 71 mcl 6j 2nc (1) 5u 37 a 7b 72 a 3v 3nc (1) 7u 38 a 7a 73 a 4v 4mcl (1) 6d 39 w 6b 74 a 4u 5mcl (1) 6k 40 adv 6a 75 a 5v 6mcl (1) 6p 41 e1 6c 76 a 6u 7mcl (1) 6t 42 a 5a 77 a 5w 8mch (2) 6n 43 a 5b 78 a0 6w 9 mch 6m 44 e2 4a 79 a1 6v 10 mch 6l 45 a 3a 80 a 7v 11 dqa 10r 46 zq 6f 81 a 8v 12 dqa 11p 47 bd 4c 82 a 7w 13 dqa 10p 48 bc 3b 83 a 8u 14 dqa 11n 49 dqc 2e 84 a 9v 15 dqa 10n 50 dqc 1f 16 dqa 11m 51 dqc 2f 17 dqa 10m 52 dqc 1g 18 dqa 11l 53 dqc 2g 19 dqa 10l 54 dqc 1h 20 cq1 11k 55 dqc 2h 21 cq1 10k 56 dqc 1j 22 dqb 11e 57 dqc 2j 22 dqb 10d 58 cq2 1k 24 dqb 11d 59 ck 3k 25 dqb 10c 60 ck 4k 26 dqb 11c 61 cq2 2k 27 dqb 10b 62 dqd 1r 28 dqb 11b 63 dqd 2t 29 dqb 11a 64 dqd 1t 30 dqb 10a 65 dqd 2u 31 ba 9c 66 dqd 1u 32 bb 8b 67 dqd 2v 33 ep3 6h 68 dqd 1v 34 ep2 6g 69 dqd 1w 35 a 9a 70 dqd 2w
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 26 / 30 july 19, 2002 . note 1 : nc and mcl pins at pad locations 5c, 5u, 7u, 6d, 6k, 6p, and 6t are connected to v ss internally, regardless of pin connection externally. note 2 : mch pin at pad location 6n is connected to v dd internally, regardless of pin connection externally. 1mb x 18 bit signal pad bit signal pad 1nc (1) 5c 36 a 3a 2nc (1) 5u 37 zq 6f 3nc (1) 7u 38 bb 3b 4mcl (1) 6d 39 dqb 2e 5mcl (1) 6k 40 dqb 1f 6mcl (1) 6p 41 dqb 2f 7mcl (1) 6t 42 dqb 1g 8mch (2) 6n 43 dqb 2g 9 mch 6m 44 dqb 1h 10 mch 6l 45 dqb 2h 11 dqa 10r 46 dqb 1j 12 dqa 11p 47 dqb 2j 13 dqa 10p 48 cq2 1k 14 dqa 11n 49 ck 3k 15 dqa 10n 50 ck 4k 16 dqa 11m 51 cq2 2k 17 dqa 10m 52 mcl 6j 18 dqa 11l 53 a 3v 19 dqa 10l 54 a 4v 20 cq1 11k 55 a 4u 21 cq1 10k 56 a 5v 22 ba 9c 57 a 6u 22 ep3 6h 58 a 5w 24 ep2 6g 59 a0 6w 25 a 9a 60 a1 6v 26 e3 8a 61 a 7v 27 a 7c 62 a 8v 28 a 7b 63 a 7w 29 a 7a 64 a 8u 30 w 6b 65 a 9v 31 adv 6a 32 e1 6c 33 a 5a 34 a 5b 35 e2 4a
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 27 / 30 july 19, 2002 ordering information part number v dd i/o type configuration speed (cycle time / data access time) CXK79M72C160GB-33 1.8v hstl 256kb x 72 3.3ns / 1.8ns CXK79M72C160GB-4 1.8v hstl 256kb x 72 4.0ns / 2.1ns CXK79M72C160GB-5 1.8v hstl 256kb x 72 5.0ns / 2.3ns cxk79m36c160gb-33 1.8v hstl 512kb x 36 3.3ns / 1.8ns cxk79m36c160gb-4 1.8v hstl 512kb x 36 4.0ns / 2.1ns cxk79m36c160gb-5 1.8v hstl 512kb x 36 5.0ns / 2.3ns cxk79m18c160gb-33 1.8v hstl 1mb x 18 3.3ns / 1.8ns cxk79m18c160gb-4 1.8v hstl 1mb x 18 4.0ns / 2.1ns cxk79m18c160gb-5 1.8v hstl 1mb x 18 5.0ns / 2.3ns sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illus- trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 28 / 30 july 19, 2002 (11x19) 209 pin bga package dimensions sony code jeita code jedec code bga-209p-01 p-bga209-14x22-1.0 package material terminal treatment terminal material package mass epoxy resin copper-clad laminate solder 1.1g package structure 2.0 0.30 s a 0.20 0.30 s b s 0.15 s b a 0.10 s ab m 0.35 s 209pin bga (plastic) detail x 4-c1.7 3-c1.0 c 1.5 1234567 b a c d e f g h j k l m n p r t u x4 89 2.0 0.3 209 - 0.6 0.1 2.0 14.0 22.0 13.0 0.5 0.1 21.0 x pin 1 index 1.0 1.0 10 11 v w preliminary
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 29 / 30 july 19, 2002 revision history rev. # rev. date description of modifications rev 0.0 02/23/01 initial version. rev 0.1 07/06/01 1. modified dc electrical characteristics section (p. 11). added i dd-33 and i dd-44 average power supply operating current specifications. 2. added 209 pin bga package dimensions (p. 26). rev 0.2 02/22/02 1. added bga package thermal characteristics (p. 10). 2. modified ac electrical characteristics section (p. 13). removed ?-44? bin. added ?-5? bin. -4 t chcl t khkl 0.25 to t khkl 0.2 t clch t klkh 0.25 to t klkh 0.2 3. added jtag id codes (p. 23). 4. added jtag boundary scan register bit order assignments (pp. 24-26). rev 1.0 07/19/02 1. modified pin assignment section (p. 2-4). byte write enable control inputs bwx to bx pin1k cqtocq2 pin 2k cq to cq2 pin 10k cq to cq1 pin 11k cq to cq1 pin6j m4tomcl pin6l m2tomch pin6m m3tomch 2. modified i/o capacitance section (p. 10). c kin 3.5pf to 4.0pf 3. modified dc recommended operating conditions section (p. 11). combined -1.8 and -1.5 line items into one for v ddq ,v ref ,andv cm . v ref (min), v cm (min) 0.65v to v ddq /2 - 0.1v v ref (max), v cm (max) 1.0v to v ddq /2 + 0.1v removed notes 1 and 2. 4. modified dc electrical characteristics section (p. 12). added mch and mcl input leakage current specifications. reduced x72 average power supply operating currents by 100ma. reduced x36 average power supply operating currents by 50ma. reduced x18 average power supply operating currents by 20ma. 5. modified ac electrical characteristics section (p. 13). -33 t khch (max), t khcz 1.7ns to 1.8ns -4 t khch (max), t khcz 2.0ns to 2.1ns -5 t khch (max), t khcz 2.2ns to 2.3ns 6. modified jtag dc recommended operating conditions section (p. 19). v tih (min) 1.2v to v dd /2 + 0.3v v til (max) 0.6v to v dd /2 - 0.3v i tli (min) -10ua to -20ua 7. modified jtag ac electrical characteristics section (p. 20). t thth 20ns to 50ns t thtl ,t tlth 8ns to 20ns added t cs capture setup and t ch capture hold specifications. 8. modified tap registers section (p. 22). instruction register codes 011, 110 bypass to private
sony ? ram CXK79M72C160GB / cxk79m36c160gb / cxk79m18c160gb preliminary 18mb 1x1lp, hstl, rev 1.0 30 / 30 july 19, 2002 9. modified boundary scan register bit order assignments section (p. 24-25). x72 bit 47 10a to 11a x72 bit 48 11a to 10a x36 bit 29 10a to 11a x36 bit 30 11a to 10a rev. # rev. date description of modifications

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