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wirelessusb? ls 2.4-ghz dsss radio soc cywusb6932 cywusb6934 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document 38-16007 rev. *i revised august 3, 2005 1.0 features ? 2.4-ghz radio transceiver ? operates in the unlicensed industrial, scientific, and medical (ism) band (2.4 ghz?2.483 ghz) ? -90-dbm receive sensitivity ? up to 0 dbm output power ? range of up to 10 meters or more ? data throughput of up to 62.5 kbits/sec ? highly integrated low cost, minimal number of external components required ? dual dsss reconfigurable baseband correlators ? spi microcontroller interfac e (up to 2-mhz data rate) ? 13-mhz 50-ppm input clock operation ? low standby current < 1 a ? integrated 30-bit manufacturing id ? operating voltage from 2.7v to 3.6v ? operating temperature from 0 to 70c ? offered in a small footprint 48 quad flat pack no leads (qfn) 2.0 functional description the cywusb6932/cywusb6934 integrated circuits (ics) are highly integrated 2.4-ghz direct sequence spread spectrum (dsss) radio system-o n-chip (soc) ics. from the serial peripheral interface (spi ) to the antenna, these ics are single-chip 2.4-ghz dsss gau ssian frequency shift keying (gfsk) baseband modems that connect directly to a micro- controller via simple serial interface. the cywusb6932 transmit-only ic and the cywusb6934 transceiver ic are available in a small footprint 48-pin qfn package. 3.0 applications ? pc human interface devices (hids) ?mice ? keyboards ? joysticks ? peripheral gaming devices ? game controllers ? console keyboards ? general ? presenter tools ? remote controls ? consumer electronics ? barcode scanners ? pos peripherals ?toys figure 3-1. cywusb6932/cywusb 6934 simplified block diagram digital synthesizer gfsk demodulator gfsk modulator irq ss sck mi so mosi reset p d dio dioval rfout rfin x13in x13 x13out cy wusb6934 only serdes b serdes a dsss baseband a dsss baseband b
cywusb6932 cywusb6934 document 38-16007 rev. *i page 2 of 30 3.1 applications support the cywusb6932/cywusb6934 ics are supported by the cy3632 wirelessusb development kit. the development kit provides all of the materials and documents needed to cut the cord on wired applications including two radio modules that connect directly to two prototyping platform boards, compre- hensive wirelessusb protocol code examples a wirelessusb listener tool and all of the asso ciated schematics, gerber files and bill of materials. the cy4632 wirelessusb ls keyboard mouse reference design provides a production-worthy example of a wireless mouse and keyboard system. the cy3633 wirelessusb ls gaming development kit provides support for designing a wireless gamepad for the major gaming consoles and is offered as an accessory to the cy3632 wirelessusb. 4.0 functional overview the cywusb6932/cywusb6934 ics provide a complete wirelessusb ls spi to antenna radio modem. the soc is designed to implement wirele ss devices operating in the worldwide 2.4-ghz industrial, scientific, and medical (ism) frequency band (2.400 ghz?2.4835 ghz). it is intended for systems compliant with world-wide regulations covered by etsi en 301 489-1 v1.4.1, etsi en 300 328-1 v1.3.1 (european countries); fcc cfr 47 part 15 (usa and industry canada) and arib std-t66 (japan). the cywusb6934 ic contains a 2.4-ghz radio transceiver, a gfsk modem and a dual dsss reconfigurable baseband. the cywusb6932 ic contains a 2.4-ghz radio transmit-only, a gfsk modem and a dsss baseband. the radio and baseband are both code- and frequency-agile. forty-nine spreading codes selected for optimal performance (gold codes) are supported across 78 1-mhz channels yielding a theoretical spectral capacity of 3822 channels. both ics support a range of up to 10 meters or more. 4.1 2.4-ghz radio the receiver and transmitter are a single-conversion low-inter- mediate frequency (low-if) architecture with fully integrated if channel matched filters to achieve high performance in the presence of interference. an integrated power amplifier (pa) provides an output power contro l range of 30 db in seven steps. both the receiver and transmitter integrated voltage controlled oscillator (vco) and synthesizer have the agility to cover the complete 2.4-gh z gfsk radio transmitter ism band. the synthesizer provides the frequency-hopping local oscillator for the transmitter and receiver. the vco loop filter is also integrated on-chip. 4.2 gfsk modem the transmitter uses a dsp-based vector modulator to convert the 1-mhz chips to an accurate gfsk carrier. the receiver uses a fully integrated frequency modulator (fm) detector with automatic data slicer to demodulate the gfsk signal. 4.3 dual dsss baseband data is converted to dsss chips by a digital spreader. de-spreading is performed by an oversampled correlator. the dsss baseband cancels spurious noise and assembles properly correlated data bytes. the dsss baseband has three ope rating modes: 64 chips/bit single channel, 32 chips/bit single channel, and 32 chips/bit single channel dual data rate (ddr). 4.3.1 64 chips/bit single channel the baseband supports a single data stream operating at 15.625 kbits/sec. the advantage of selecting this mode is its ability to tolerate a noisy envir onment. this is because the 15.625 kbits/sec data stream utilizes the longest pn code resulting in the highest probability for recovering packets over the air. this mode can also be selected for systems requiring data transmissions over longer ranges. 4.3.2 32 chips/bit single channel the baseband supports a single data stream operating at 31.25 kbits/sec. 4.3.3 32 chips/bit single channel dual data rate (ddr) the baseband spreads bits in pairs and supports a single data stream operating at 62.5 kbits/sec. 4.4 serializer/deserializer (serdes) the cywusb6934 ic has a data serializer/deserializer (serdes), which provides byte-level framing of transmit and receive data. bytes for transmission are loaded into the serdes and receive bytes are read from the serdes via the spi interface. the serdes provides double buffering of transmit and receive data. while one byte is being transmitted by the radio the next byte ca n be written to the serdes data register insuring there are no breaks in transmitted data. after a receive byte has been received it is loaded into the serdes data register and can be read at any time until the next byte is received, at which time the old contents of the serdes data register will be overwritten. the cywusb6932 ic only has a data serializer. table 4-1. internal pa output power step table pa setting typical ou tput power (dbm) 70 6?2.4 5?5.6 4?9.7 3 ?16.4 2 ?20.8 1 ?24.8 0 ?29.0
cywusb6932 cywusb6934 document 38-16007 rev. *i page 3 of 30 4.5 application interfaces both ics have a fully synchronous spi slave interface for connectivity to the applicat ion mcu. configuration and byte-oriented data transfer can be performed over this interface. an interrupt is provided to trigger real time events. an optional serdes bypass mode (dio) is provided for appli- cations that require a synchronous serial bit-oriented data path. this interface is for data only. 4.6 clocking and power management a 13-mhz crystal (50 ppm or better) is directly connected to x13in and x13 without the need for external capacitors. both ics have a programmable trim capability for adjusting the on-chip load capacitance supplied to the crystal. the radio frequency (rf) circuitry has on-chip decoupling capacitors. both devices are powered from a 2.7v to 3.6v dc supply. both devices can be shutdown to a fully static state using the pd pin. below are the requirements for the crystal to be directly connected to x13in and x13: ? nominal frequency: 13 mhz ? operating mode: fundamental mode ? resonance mode: parallel resonant ? frequency stability: 50 ppm ? series resistance: 100 ohms ? load capacitance: 10 pf ? drive level: 10 uw?100 uw 4.7 receive signal strength indicator (rssi) the rssi register (reg 0x22) (applies only to the cywusb6934 ic) returns the relative signal strength of the on-channel signal power and can be used to: 1. determine the connection quality 2. determine the value of the noise floor 3. check for a quiet channel before transmitting. the internal rssi voltage is sampled through a 5-bit analog-to-digital converter (adc). a state machine controls the conversion process. under normal conditions, the rssi state machine initiates a conversion when an on-channel carrier is detected and remains above the noise floor for over 50 s. the conversion produces a 5-bit value in the rssi register (reg 0x22, bits 4:0) along with a valid bit, rssi register (reg 0x22, bit 5). the state machine then remains in halt mode and does not reset for a new conversion until the receive mode is toggled off and on. once a connection has been established, the rssi regi ster can be read to determine the relative connection quality of the channel. a rssi register value lower than 10 indicates that the received signal strength is low, a value greater than 28 indicates a strong signal level. to check for a quiet channel before transmitting, first set up receive mode properly and read the rssi register (reg 0x22). if the valid bit is zero, then force the carrier detect register (reg 0x2f, bit 7=1) to initiate an adc conversion. then, wait greater than 50 s and read the rssi register again. next, clear the carrier detect register (reg 0x2f, bit 7=0) and turn the receiver off. measuring th e noise floor of a quiet channel is inherently a 'noisy' process so, for best results, this procedure should be repeated several times (~20) to compute an average noise floor level. a rssi register value of 0-10 indicates a channel that is relatively quiet. a rssi register value greater than 10 indicates the channel is probably being used. a rssi register value greater than 28 indicates the presence of a strong signal. 5.0 application interfaces 5.1 spi interface the cywusb6932/cywusb6934 ics have a four-wire spi communication interface between an application mcu and one or more slave devices. the spi interface supports single-byte and multi-byte serial transfers. the four-wire spi communications interface consists of master out-slave in (mosi), master in-slave out (mi so), serial clock (sck), and slave select (ss ). the spi receives sck from an application mcu on the sck pin. data from the application mcu is shifted in on the mosi pin. data to the application mcu is shifted out on the miso pin. the active-low slave select (ss) pin must be asserted to initiate a spi transfer. the application mcu can initiate a spi data transfer via a multi-byte transaction. the firs t byte is the command/address byte, and the following bytes are the data bytes as shown in figure 5-1 through figure 5-4 . the ss signal should not be deasserted between bytes. the spi communications is as follows: ? command direction (bit 7) = ?0? enables spi read transac- tion. a ?1? enables spi write transactions. ? command increment (bit 6) = ?1? enables spi auto address increment. when set, the address field automatically incre- ments at the end of each data byte in a burst access, oth- erwise the same address is accessed. ? six bits of address. ? eight bits of data. the spi communications interface has a burst mechanism, where the command byte can be followed by as many data bytes as desired. a burst tr ansaction is terminated by deasserting the slave select (ss = 1). for burst read transac- tions, the application mcu must abide by the timing shown in figure 12-2 . the spi communications interf ace single read and burst read sequences are shown in figure 5-2 and figure 5-3 , respec- tively. the spi communications interfac e single write and burst write sequences are shown in figure 5-4 and figure 5-5 , respec- tively.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 4 of 30 byte 1 byte 1+n bit # 7 6 [5:0] [7:0] bit name dir inc address data figure 5-1. spi transaction format figure 5-2. spi single read sequence figure 5-3. spi burst read sequence figure 5-4. spi single write sequence figure 5-5. spi burst write sequence ss mosi miso sck dir inc a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 data to mcu addr cm d 00 ss mosi miso sck a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data to mcu 1 data to mcu 1+n addr cmd dir inc 01 ss mosi miso sck dir inc a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 data from mcu addr cmd 10 ss mosi miso sck a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data from mcu 1 data from mcu 1+n addr cmd dir inc 11
cywusb6932 cywusb6934 document 38-16007 rev. *i page 5 of 30 5.2 dio interface the dio communications interface is an optional serdes bypass data-only transfer interface. in receive mode, dio and dioval are valid after the falling edge of irq, which clocks the data as shown in figure 5-6 . in transmit mode, dio and dioval are sampled on the falling edge of the irq, which clocks the data as shown in figure 5-7 . the application mcu samples the dio and dioval on the rising edge of irq. 5.3 interrupts the cywusb6932/cywusb6934 ics feature three sets of interrupts: transmit, receive (cywusb6934 only), and a wake interrupt. these interrupts all share a single pin (irq), but can be independently enabled/disabled. in transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. however, the contents of the enable registers are preserved when switching between transmit and receive modes. interrupts are enabled and the status read through 6 registers: receive interrupt enable (reg 0x07), receive interrupt status (reg 0x08), transmit interrupt enable (reg 0x0d), transmit interrupt status (reg 0x0e), wake enable (reg 0x1c), wake status (reg 0x1d). if more than 1 interrupt is enabled at any time, it is necessary to read the relevant interrupt status register to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate interrupt status register. it is therefore possible to use the devices without making use of the irq pin at all. firmware can poll the interrupt status register(s) to wait for an event, rather than using the irq pin. the polarity of all interrupts can be set by writing to the config- uration register (reg 0x05), and it is possible to configure the irq pin to be open drain (if active low) or open source (if active high). 5.3.1 wake interrupt when the pd pin is low, the oscillator is stopped. after pd is deasserted, the oscillator takes time to start, and until it has done so, it is not safe to use the spi interface. the wake interrupt indicates that the osc illator has started, and that the device is ready to receive spi transfers. the wake interrupt is enabled by setting bit 0 of the wake enable register (reg 0x1c, bi t 0=1). whether or not a wake interrupt is pending is indicated by the state of bit 0 of the wake status register (reg 0x1d, bit 0). reading the wake status register (reg 0x1d) clears the interrupt. 5.3.2 transmit interrupts four interrupts are provided to flag the occurrence of transmit events. the interrupts are enabled by writing to the transmit interrupt enable register (reg 0x0d), and their status may be determined by reading the transmit interrupt status register (reg 0x0e). if more than 1 interrupt is enabled, it is necessary to read the transmit interrupt status register (reg 0x0e) to determine which event caused the irq pin to assert. the function and operation of these interrupts are described in detail in section 7.0 . 5.3.3 receive interrupts eight interrupts are provided to flag the occurrence of receive events, four each for serdes a and b. in 64 chips/bit and 32 chips/bit ddr modes, only the serdes a interrupts are available, and the serdes b interrupts will never trigger, even if enabled. the interrupts are enabled by writing to the receive interrupt enable regist er (reg 0x07), and their status may be determined by reading the receive interrupt status register (reg 0x08). if more than one interrupt is enabled, it is necessary to read the receive interrupt status register (reg 0x08) to determine which event caused the irq pin to assert. the function and operation of these interrupts are described in detail in section 7.0 . figure 5-6. dio receive sequence figure 5-7. dio transmit sequence dioval dio irq d7 d6 d5 d4 d3 d2 d... d14 d13 d12 d11 d10 d9 d8 d1 d0 data to mcu v7 v6 v5 v4 v3 v2 v... v14 v13 v12 v11 v10 v9 v8 v1 v0 dioval dio irq d7 d6 d5 d4 d3 d2 d... d14 d13 d12 d11 d10 d9 d8 d1 d0 data from mcu v7 v6 v5 v4 v3 v2 v... v14 v13 v12 v11 v10 v9 v8 v1 v0
cywusb6932 cywusb6934 document 38-16007 rev. *i page 6 of 30 6.0 application examples figure 6-1. cywusb6932 transm it-only battery-powered device wusb ls application mcu irq spi 4 pd reset vcc vcc ldo/ dc2dc battery + - 0.1 f buttons optical mouse sensor 13mhz crystal 10pf 3.3 v rfout pcb trace inverted ?f ? antenna (pifa) figure 6-2. cywusb6934 usb bridge transceiver cypress encore ? usb mcu wirelessusb ls 13mhz cr y s tal vcc ldo 0.1 f usb i/f 1.3k d+/d- 2 reset irq miso sck 2.2k mosi 2.2k 1f 0.1f 4.7f 3.3v rfout rfin 5v ss pd 3.3 nh pcb trace antenna 27 pf 2.2 nh 2.0 pf 1.2 pf 2.0 pf
cywusb6932 cywusb6934 document 38-16007 rev. *i page 7 of 30 7.0 register descriptions table 7-1 displays the list of registers inside the cywusb6932/cywusb6934 ics that are addressable through the spi interface. all registers are read and writable, except where noted. table 7-1. cywusb6932/cywusb6934 register map [2] register name mnemonic address page default access revision id reg_id 0x00 8 0x07 ro control reg_control 0x03 8 0x00 rw data rate reg_data_rate 0x04 9 0x00 rw configuration reg_config 0x05 9 0x01 rw serdes control reg_ser des_ctl 0x06 10 0x03 rw receive serdes interrupt enable reg_rx_int_en 0x07 [1] 11 0x00 rw receive serdes interrupt status reg_rx_int_stat 0x08 [1] 12 0x00 ro receive serdes data a reg_rx_data_a 0x09 [1] 13 0x00 ro receive serdes valid a reg_rx_valid_a 0x0a [1] 13 0x00 ro receive serdes data b reg_rx_data_b 0x0b [1] 13 0x00 ro receive serdes valid b reg_rx_valid_b 0x0c [1] 13 0x00 ro transmit serdes interrupt enable reg_tx_int_en 0x0d 14 0x00 rw transmit serdes interrupt status reg_tx_int_stat 0x0e 15 0x00 ro transmit serdes data reg_tx_data 0x0f 16 0x00 rw transmit serdes valid reg_tx_valid 0x10 16 0x00 rw pn code reg_pn_code 0x18?0x11 16 0x1e8b6a3de0e9b222 rw threshold low reg_threshold_l 0x19 [1] 17 0x08 rw threshold high reg_threshold_h 0x1a [1] 17 0x38 rw wake enable reg_wake_en 0x1c 17 0x00 rw wake status reg_wake_stat 0x1d 18 0x01 ro analog control reg_analog_ctl 0x20 18 0x04 rw channel reg_channel 0x21 19 0x00 rw receive signal strength indicator reg_rssi 0x22 [1] 19 0x00 ro pa bias reg_pa 0x23 19 0x00 rw crystal adjust reg_crystal_adj 0x24 20 0x00 rw vco calibration reg_vco_cal 0x26 20 0x00 rw reg power control reg_pwr_ctl 0x2e 20 0x00 rw carrier detect reg_carrier_detect 0x2f 21 0x00 rw clock manual reg_clock_manual 0x32 21 0x00 rw clock enable reg_clock_enable 0x33 21 0x00 rw synthesizer lock count reg _syn_lock_cnt 0x38 21 0x64 rw manufacturing id reg_mid 0x3c?0x3f 21 ? ro notes: 1. register not applicable to cywusb6932. 2. all registers are accessed little endian.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 8 of 30 figure 7-1. revision id register addr: 0x00 reg_id default: 0x07 76543210 silicon id product id bit name description 7:4 silicon id these are the silicon id revision bits. 0000 = rev a, 0001 = rev b, etc. these bits are read-only. 3:0 product id these are the product id revision bits. fix ed at value 0111. these bits are read-only. figure 7-2. control addr: 0x03 reg_control default: 0x00 765 4 3210 rx enable tx enable pn code select bypass internal syn lock signal auto internal pa disable internal pa enable reserved reserved bit name description 7 rx enable the receive enable bit is us ed to place the ic in receive mode. 1 = receive enabled 0 = receive disabled 6 tx enable the transmit enable bit is us ed to place the ic in transmit mode. 1 = transmit enabled 0 = transmit disabled 5 pn code select the pseudo-noise code select bit selects between the upper or lower half of the 64 chips/bit pn code. 1 = 32 most significant bits of pn code are used 0 = 32 least significant bits of pn code are used this bit applies only when the c ode width bit is set to 32 chips/bit pn codes (reg 0x04, bit 2=1). 4 bypass internal syn lock signal this bit controls whether the state machine waits for the in ternal syn lock signal before wa iting for the amount of time specified in the syn lock count register (reg 0x38), in units of 2 s. if the internal syn lock signal is used then set syn lock count to 25 to provide additional assu rance that the synthesizer has settled. 1 = bypass the internal syn lock signal and wait the amount of time in syn lock count register (reg 0x38) 0 = wait for the syn lock signal and then wait the amo unt of time specified in syn lock count register (reg 0x38) it is recommended that the application mcu sets this bit to 1 in order to guarantee a consistent settle time for the synthesizer. 3 auto internal pa disable the auto internal pa disable bit is used to determine the me thod of controlling the internal power amplifier. the two options are automatic control by the baseband or by firmware through register writes. for external pa usage, please see the description of the reg_analog_ctl register (reg 0x20). 1 = register controlled internal pa enable 0 = auto controlled internal pa enable when this bit is set to 1, the enabled state of the internal pa is directly controll ed by bit internal pa enable (reg 0x03, bit 2). it is recommended that this bit is set to 0, leaving the pa control to the baseband. 2 internal pa enable the internal pa enable bit is used to enable or disable the internal power amplifier. 1 = internal power amplifier enabled 0 = internal power amplifier disabled this bit only applies when the auto internal pa disable bit is selected (reg 0x03, bi t 3=1), otherwise this bit is don?t care. 1 reserved this bit is reserved and should be written with a zero. 0 reserved this bit is reserved and should be written with a zero.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 9 of 30 note: 3. the following reg 0x04, bits 2:0 values are not valid: ? 001 ? not valid ? 010 ? not valid ? 011 ? not valid ? 111 ? not valid. addr: 0x04 reg_data_rate default: 0x00 76543210 reserved code width data rate sample rate figure 7-3. data rate bit name description 7:3 reserved these bits are reserved and should be written with zeroes. 2 [3] code width the code width bit is used to select between 32 chips/bit and 64 chips/bit pn codes. 1 = 32 chips/bit pn codes 0 = 64 chips/bit pn codes the number of chips/bit used impacts a number of factors such as data throughput, range and robustness to inter- ference. by choosing a 32 chips/bit pn-code, the dat a throughput can be doubled or even quadrupled (when double data rate is set). a 64 chips/bit pn code offers improved ra nge over its 32 chips/bit counterpart as well as more robustness to interference. by selecting to use a 32 chip s/bit pn code a number of other register bits are impacted and need to be addressed. these are pn code select (reg 0x03, bit 5), data rate (reg 0x04, bit 1), and sample rate (reg 0x04, bit 0). 1 [3] data rate the data rate bit allows the user to select doubl e data rate mode of operation which delivers a raw data rate of 62.5 kbits/sec. 1 = double data rate - 2 bits per pn code (no odd bit transmissions) 0 = normal data rate - 1 bit per pn code this bit is applicable only when usi ng 32 chips/bit pn codes which can be sele cted by setting the code width bit (reg 0x04, bit 2=1). when using double data rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit pn code is interpreted as 2 bits of data. when using this mode a single 64 chips/bit pn code is placed in the pn code register. this 64 chips/bit pn code is then split into two and used by the baseband to offer the double data rate capability. when using normal data rate, t he raw data throughput is 32kbits/sec. additionally, normal data rate enables the user to potentially correlate dat a using two differing 32 chips/bit pn codes. 0 [3] sample rate the sample rate bit allows the use of the 12x sampli ng when using 32 chips/bit pn codes and normal data rate. 1 = 12x oversampling 0 = 6x oversampling using 12x oversampling improves the co rrelators receive sensitivity. when us ing 64 chips/bit pn codes or double data rate this bit is don?t care. the only time when 12x oversampling can be selected is when a 32 chips/bit pn code is being used with normal data rate. figure 7-4. configuration addr: 0x05 reg_config default: 0x01 76543210 reserved irq pin select bit name description 7:2 reserved these bits are reserved and should be written with zeroes. 1:0 irq pin select the interrupt request pin select bits are used to determine the drive method of the irq pin. 11 = open source (irq asserted = 1, irq deasserted = hi-z) 10 = open drain (irq asserted = 0, irq deasserted = hi-z) 01 = cmos (irq asserted = 1, irq deasserted = 0) 00 = cmos inverted (irq asserted = 0, irq deasserted = 1)
cywusb6932 cywusb6934 document 38-16007 rev. *i page 10 of 30 addr: 0x06 reg_serdes_ctl default: 0x03 76543210 reserved serdes enable eof length figure 7-5. serdes control bit name description 7:4 reserved these bits are reserved and should be written with zeroes. 3 serdes enable the serdes enable bit is used to switch between bit-serial mode and serdes mode. 1 = serdes enabled. 0 = serdes disabled, bit-serial mode enabled. when the serdes is enabled data can be written to and read fr om the ic one byte at a time, through the use of the serdes data registers. the bit-serial mode requires bits to be written one bit at a time through the use of the dio/dioval pins, refer to section 3.2. it is recommended that serdes mode be used to avoid the need to manage the timing required by the bit-serial mode. 2:0 eof length the end of frame length bits are used to set the number of sequential bit times for an inter-frame gap without val id data before an eof event will be generated. when in rece ive mode and a valid bit has been received the eof event can then be identified by the number of bi t times that expire without correlati ng any new data. the eof event causes data to be moved to the proper serdes data register and can also be used to generate interrupts. if 0 is the eof length, an eof condition will occur at the first invalid bit after a valid reception.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 11 of 30 addr: 0x07 reg_rx_int_en default: 0x00 76543210 underflow b overflow b eof b full b underflow a overflow a eof a full a figure 7-6. receive serdes interrupt enable bit name description 7 underflow b the underflow b bit is used to enable the interrupt associated with an underflow c ondition with the receive serdes data b register (reg 0x0b) 1 = underflow b interrupt enabled for receive serdes data b 0 = underflow b interrupt disabled for receive serdes data b an underflow condition occurs when attempting to read the receive serdes data b register (reg 0x0b) when it is empty. 6 overflow b the overflow b bit is used to enable the interrupt a ssociated with an overflow condit ion with the receive serdes dat a b register (reg 0x0b) 1 = overflow b interrupt enabled for receive serdes data b 0 = overflow b interrupt disabled for receive serdes data b an overflow condition occurs when new received data is written into the rece ive serdes data b register (reg 0x0b) before the prior data is read out. 5 eof b the end of frame b bit is used to enable the interr upt associated with the channel b receiver eof condition. 1 = eof b interrupt enabled for channel b receiver. 0 = eof b interrupt disabled for channel b receiver. the eof irq asserts during an end of frame condition. end of frame conditions occur af ter at least one bit has been detected, and then the number of invalid bits in the frame exc eeds the number in the eof length field. if 0 is the eof length, and eof condition will occur at the first invalid bit after a valid reception. this irq is cleared by reading the receive status register 4 full b the full b bit is used to enable the interrupt associat ed with the receive serdes data b register (reg 0x0b) having data placed in it. 1 = full b interrupt enabled for receive serdes data b 0 = full b interrupt disabled for receive serdes data b a full b condition occurs when data is transferred from t he channel b receiver into the receive serdes data b register (reg 0x0b). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received. 3 underflow a the underflow a bit is used to enable the interrupt associated with an underflow c ondition with the receive serdes data a register (reg 0x09) 1 = underflow a interrupt enabled for receive serdes data a 0 = underflow a interrupt disabled for receive serdes data a an underflow condition occurs when attempting to read the receive serdes data a register (reg 0x09) when it is empty. 2 overflow a the overflow a bit is used to enable the interrupt a ssociated with an overflow condit ion with the receive serdes dat a a register (0x09) 1 = overflow a interrupt enabled for receive serdes data a 0 = overflow a interrupt disabled for receive serdes data a an overflow condition occurs when new receive data is written into the rece ive serdes data a register (reg 0x09) before the prior data is read out. 1 eof a the end of frame a bit is used to enable the interrupt associated with an end of frame condition with the channel a receiver. 1 = eof a interrupt enabled for channel a receiver. 0 = eof a interrupt disabled for channel a receiver. the eof irq asserts during an end of frame condition. end of frame conditions occur af ter at least one bit has been detected, and then the number of invalid bits in a frame exce eds the number in the eof length field. if 0 is the eof length, an eof condition will occu r at the first invalid bit after a valid recept ion. this irq is cleared by reading the receiv e status register. 0 full a the full a bit is used to enable the interrupt associat ed with the receive serdes data a register (0x09) having data written into it. 1 = full a interrupt enabled for receive serdes data a 0 = full a interrupt disabled for receive serdes data a a full a condition occurs when data is transferred from t he channel a receiver into the receive serdes data a register (reg 0x09). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 12 of 30 note: 4. all status bits are set and readable in the registers regardless of irq enable status. this allows a polling scheme to be imp lemented without enabling irqs. the status bits are affected by tx enable and rx enable (reg 0x03, bits 7:6). for example, the receive status will read 0 if the ic is not in receive mode. these registers are read-only. addr: 0x08 reg_rx_int_stat default: 0x00 76543210 valid b flow violation b eof b full b valid a flow violation a eof a full a figure 7-7. receive serdes interrupt status [4] bit name description 7 valid b the valid b bit is true when all the bits in the receive serdes data b register (reg 0x0b) are valid. 1 = all bits are valid for receive serdes data b. 0 = not all bits are valid for receive serdes data b. when data is written into the receive serdes data b register (reg 0x0b) this bit is set if all of the bits within the byte that has been written are valid. this bit cannot generate an interrupt. 6 flow violation b the flow violation b bit is used to signal whether an overflow or underflow condition has occurred for the receive serdes data b register (reg 0x0b). 1 = overflow/underflow interrupt pending for receive serdes data b. 0 = no overflow/underflow interrupt pending for receive serdes data b. overflow conditions occur when the radio loads new data into the receive serdes data b register (reg 0x0b) before the prior data has been read. underflow conditions occur wh en trying to read the receive serdes data b register (reg 0x0b) when the register is empty. this bit is cleared by reading the receive interrupt status register (reg 0x08) 5 eof b the end of frame b bit is used to signal wh ether an eof event has occurred on the channel b receive. 1 = eof interrupt pending for channel b. 0 = no eof interrupt pending for channel b. an eof condition occurs for the channel b receiver when receive has begun and then the number of bit times specified in the serdes control register (reg 0x06) elapse without any valid bits being re ceived. this bit is cleared by reading the receive interrupt status register (reg 0x08) 4 full b the full b bit is used to signal when the receive serdes data b register (reg 0x0b) is filled with data. 1 = receive serdes data b full interrupt pending. 0 = no receive serdes data b full interrupt pending. a full b condition occurs when data is transferred from t he channel b receiver into the receive serdes data b register (reg 0x0b). this c ould occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received. 3 valid a the valid a bit is true when all of the bits in the receive serdes data a register (reg 0x09) are valid. 1 = all bits are valid for receive serdes data a. 0 = not all bits are valid for receive serdes data a. when data is written into the receive serdes data a register (reg 0x09) this bit is set if all of the bits within the byte that has been written are valid. this bit cannot generate an interrupt. 2 flow violation a the flow violation a bit is used to signal whether an overflow or underflow condition has occurred for the receive serdes data a register (reg 0x09). 1 = overflow/underflow interrupt pending for receive serdes data a. 0 = no overflow/underflow interrupt pending for receive serdes data a. overflow conditions occur when the radi o loads new data into the receive serdes data a register (reg 0x09) before the prior data has been read. underflow conditions occur wh en trying to read the receive serdes data a register (reg 0x09) when the register is empty. this bit is clear ed by reading the receive interrupt status register (reg 0x08) 1 eof a the end of frame a bit is used to signal wh ether an eof event has occurred on the channel a receive. 1 = eof interrupt pending for channel a. 0 = no eof interrupt pending for channel a. an eof condition occurs for the channel a receiver when receive has begun and then the number of bit times specified in the serdes control register (0x06) elapse wi thout any valid bits being rece ived. this bit is cleared by reading the receive interrupt status register (reg 0x08). 0 full a the full a bit is used to signal when the receive serdes data a register (reg 0x09) is filled with data. 1 = receive serdes data a full interrupt pending. 0 = no receive serdes data a full interrupt pending. a full a condition occurs when data is transferred from t he channel a receiver into the receive serdes data a register (reg 0x09). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 13 of 30 addr: 0x09 reg_rx_data_a default: 0x00 76543210 data figure 7-8. receive serdes data a bit name description 7:0 data received data for channel a. the over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bi t 6, followed by bit 7. this register is read-only. addr: 0x0a reg_rx_valid_a default: 0x00 76543210 valid figure 7-9. receive serdes valid a bit name description 7:0 valid these bits indicate which of the bits in the receive serdes da ta a register (reg 0x09) are valid. a ?1? indicates that the corresponding data bit is valid for channel a. if the valid data bit is set in the receive interrupt status regi ster (reg 0x08) all eight bits in the receive serdes data a re gister (reg 0x0a) are valid. therefore, it is not necessary to read the receive serdes valid a register (r eg 0x0c). this register is read-only. addr: 0x0b reg_rx_data_b default: 0x00 76543210 data figure 7-10. receive serdes data b bit name description 7:0 data received data for channel b. the over-the-air received order is bi t 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. this register is read-only. figure 7-11. receive serdes valid b addr: 0x0c reg_rx_valid_b default: 0x00 76543210 valid bit name description 7:0 valid these bits indicate which of the bits in the receive serdes da ta b register (reg 0x0b) are valid. a ?1? indicates that the corresponding data bit is valid for channel b. if the valid data bit is set in the receive interrupt status regi ster (0x08) all eight bits in the receive serdes data b regist er (reg 0x0b) are valid. therefore, it is not necessary to read t he receive serdes valid b register (reg 0x0c). this register is read-only.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 14 of 30 addr: 0x0d reg_tx_int_en default: 0x00 76543210 reserved underflow overflow done empty figure 7-12. transmit serdes interrupt enable bit name description 7:4 reserved these bits are reserved and should be written with zeroes. 3 underflow the underflow bit is used to enable the interrupt associated with an underflow condition associated with the transmit serdes data register (reg 0x0f) 1 = underflow interrupt enabled. 0 = underflow interrupt disabled. an underflow condition occurs when attempting to transmit wh ile the transmit serdes data register (reg 0x0f) does not have any data. 2overflow the overflow bit is used to enabled the interrupt associated wi th an overflow condition with the transmit serdes data register (0x0f). 1 = overflow interrupt enabled. 0 = overflow interrupt disabled. an overflow condition occurs w hen attempting to write new data to the transmit serdes data register (reg 0x0f) before the preceding data has been transferred to the transmit shift register. 1 done the done bit is used to enable the interrupt t hat signals the end of the transmission of data. 1 = done interrupt enabled. 0 = done interrupt disabled. the done condition occurs when the transmit serdes data regi ster (reg 0x0f) has transmitted all of its data and there is no more data for it to transmit. 0 empty the empty bit is used to enable the interrupt that signals when the transmit serdes register (reg 0x0f) is empty. 1 = empty interrupt enabled. 0 = empty interrupt disabled. the empty condition occurs when the transmit serdes data r egister (reg 0x0f) is loaded into the transmit buffer and it's safe to load the next byte
cywusb6932 cywusb6934 document 38-16007 rev. *i page 15 of 30 note: 5. all status bits are set and readable in the registers regardless of irq enable status. this allows a polling scheme to be imp lemented without enabling irqs. the status bits are affected by the tx enable and rx enable (reg 0x03, bits 7:6). for example, the transmit status will read 0 if t he ic is not in transmit mode. these registers are read-only. addr: 0x0e reg_tx_int_stat default: 0x00 76543210 reserved underflow overflow done empty figure 7-13. transmit serdes interrupt status [5] bit name description 7:4 reserved these bits are reserved. this register is read-only. 3 underflow the underflow bit is used to signal when an underflow condition associated with the transmit serdes data register (re g 0x0f) has occurred. 1 = underflow interrupt pending. 0 = no underflow interrupt pending. this irq will assert during an underflow condition to the tr ansmit serdes data register (reg 0x0f). an underflow occurs when the transmitter is ready to sample transmit data, but ther e is no data ready in the transmit serdes data register (reg 0x0f). this will only assert after the transmitter has transmitted at least one bit. th is bit is cleared by reading the transmi t interrupt status register (reg 0x0e). 2 overflow the overflow bit is used to signal when an overflow condition associated with the transmit serdes data register (0x0f) has occurred. 1 = overflow interrupt pending. 0 = no overflow interrupt pending. this irq will assert during an overflow c ondition to the transmit serdes data regist er (reg 0x0f). an overflow occurs when the new data is loaded into the transmit serdes data r egister (reg 0x0f) before the previous data has been sent. this bit is cleared by reading the transmi t interrupt status register (reg 0x0e). 1 done the done bit is used to signal the end of a data transmission. 1 = done interrupt pending. 0 = no done interrupt pending. this irq will assert when the data is fini shed sending a byte of data and there is no more data to be sent. this will only asse rt after the transmitter has transmitted as leas t one bit. this bit is cleared by reading th e transmit interrupt status register ( reg 0x0e) 0 empty the empty bit is used to signal when the transmit serdes data register (reg 0x0f) has been emptied. 1 = empty interrupt pending. 0 = no empty interrupt pending. this irq will assert when the transmit se rdes is empty. when this irq is asserted it is ok to write to the transmit serdes data register (reg 0x0f). writing the transmit serdes data regi ster (reg 0x0f) will clear this irq. it will be set when the data is loaded into the transmitter, and it is ok to write new data.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 16 of 30 note: 6. the valid bit in the transmit serdes valid register (reg 0x10) is used to mark whether the radio will send data or preamble d uring that bit time of the data byte. data is sent lsb first. the serdes will continue to send data until there are no more valid bits in the shifter. for exam ple, writing 0x0f to the transmit serdes valid register (reg 0x10) will send half a byte. addr: 0x0f reg_tx_data default: 0x00 76543210 data figure 7-14. transmit serdes data bit name description 7:0 data transmit data. the over-the-air transmi tted order is bit 0 followed by bit 1, fo llowed by bit 2, followed by bit 3, foll owed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. addr: 0x10 reg_tx_v alid default: 0x00 76543210 valid figure 7-15. transmit serdes valid bit name description 7:0 valid [6] the valid bits are used to determine which of the bits in the transmit serdes data register (reg 0x0f) are valid. 1 = valid transmit bit. 0 = invalid transmit bit. addr: 0x11-18 reg_pn_code default: 0x1e8b6a3de0e9b222 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 address 0x18 address 0x17 address 0x16 address 0x15 figure 7-16. pn code 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 address 0x14 address 0x13 address 0x12 address 0x11 bit name description 63:0 pn codes the value inside the 8 byte pn code register is used as the spreading code for dsss communication. all 8 bytes can be used together for 64 chips/bit pn code communication, or the registers can be split into two sets of 32 chips/bit pn codes and these can be used alone or with each other to acco mplish faster data rates. not any 64 chips/bit value can be used as a pn code as there are certain characteristics t hat are needed to minimize the possibility of multiple pn codes interfering with each other or the possibility of invali d correlation. the over-the-air order is bit 0 followed by bit 1. .. followed by bit 62, followed by bit 63.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 17 of 30 addr: 0x19 reg_threshold_l default: 0x08 76543210 reserved threshold low figure 7-17. threshold low bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 threshold low the threshold low value is us ed to determine the number of missed chips allowed when attempting to correlate a single data bit of value ?0?. a perfect re ception of a data bit of ?0? with a 64 chips/bit pn code would result in zero correlation matches, meaning the exact inverse of the pn code has been rece ived. by setting the threshold low value to 0x08 for example, up to eight chips can be erro neous while still identifying the value of the received data bit. this value along with the threshold high value determine the correlator count values for logic ?1? and logic ?0?. the threshold values used determine th e sensitivity of the receiver to interference and the dependability of the received data. by allowing a minimal number of erroneou s chips the dependability of the received data increases while the robustness to interference decreases. on the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. addr: 0x1a reg_threshold_h default: 0x38 76543210 reserved threshold high figure 7-18. threshold high bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 threshold high the threshold high value is used to determine the number of matched chips allowed when attempting to correlate a single data bit of value ?1?. a perfect reception of a data bi t of ?1? with a 64 chips/bit or a 32 chips/bit pn code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. by setting the threshold high value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying the value of the received data bit. th is value along with the threshold low value determine the correlator count values for logic ?1? and logic ?0?. the th reshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. by allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to in terference decreases. on th e other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. addr: 0x1c reg_wake_en default: 0x00 76543210 reserved wakeup en- able figure 7-19. wake enable bit name description 7:1 reserved these bits are reserved and should be written with zeroes. 0 wakeup enable wakeup interrupt enable. 0 = disabled 1 = enabled a wakeup event is triggered when the pd pin is deasserted and once the ic is ready to receive spi communications.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 18 of 30 addr: 0x1d reg_wake_stat default: 0x01 76543210 reserved wakeup status figure 7-20. wake status bit name description 7:1 reserved these bits are reserved. this register is read-only. 0 wakeup status wakeup status. 0 = wake interrupt not pending 1 = wake interrupt pending this irq will assert when a wakeup co ndition occurs. this bit is cleared by reading the wake status register (reg 0x1d). this register is read-only. addr: 0x20 reg_analog_ctl default: 0x00 76543210 reserved reg write control mid read enable reserved reserved pa output enable pa invert reset figure 7-21. analog control bit name description 7 reserved this bit is reserved and should be written with zero. 6 reg write control enables write access to reg 0x2e and reg 0x2f. 1 = enables write access to reg 0x2e and reg 0x2f 0 = reg 0x2e and reg 0x2f are read-only 5 mid read enable the mid read enable bit must be set to read t he contents of the manufacturing id register (reg 0x3c-0x3f). enabling the manufacturing id register (reg 0x3c-0x3f) consumes power. this bit should only be set when reading the contents of the manufacturing id register (reg 0x3c-0x3f). 1 = enables read of mid registers 0 = disables read of mid registers 4:3 reserved these bits are reserved and should be written with zeroes. 2 pa output enable the power amplifier output enable bit is used to enable the pactl pin for control of an external power amplifi er. 1 = pa control output enabled on pactl pin 0 = pa control output disabled on pactl pin 1 pa invert the power amplifier invert bit is used to specify the polarity of the pactl signal when the pa output enable bit is set high. pa output enable and pa invert cannot be simultaneously changed. 1 = pactl active low 0 = pactl active high 0 reset the reset bit is used to g enerate a self-clearing device reset. 1 = device reset. all registers are restored to their default values. 0 = no device reset.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 19 of 30 note: 7. the rssi will collect a single value each time the part is put into receive mode via control register (reg 0x03, bit 7=1). se e section 4.7 for more details. addr: 0x21 reg_channel default: 0x00 76543210 reserved channel figure 7-22. channel bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 channel the channel register (reg 0x21) is used to determine the synthesizer frequency. a va lue of 2 corresponds to a communication frequency of 2.402 ghz, while a value of 79 corresponds to a frequency of 2.479ghz. the channels are separated from each other by 1 mhz intervals. limit application usage to channels 2-79 to adhere to fcc r egulations. fcc regulations require that channels 0 and 1 and any channel greater than 79 be avoided. us e of other channels may be restricted by other regulatory agencies. the application mcu must ensure that this register is modified bef ore transmitting data over t he air for the first time. addr: 0x22 reg_rssi default: 0x00 76543210 reserved valid rssi figure 7-23. receive signal strength indicator (rssi) [7] bit name description 7:6 reserved these bits are reserved. th is register is read-only. 5 valid the valid bit indicates whether the rssi value in bits [4:0] are valid. this register is read only. 1 = rssi value is valid 0 = rssi value is invalid 4:0 rssi the receive strength signal indicator (rssi) value indicates the strength of the received signal. this is a read only value with the higher values indicating stronger re ceived signals meaning more reliable transmissions. addr: 0x23 reg_pa default: 0x00 76543210 reserved pa bias figure 7-24. pa bias bit name description 7:3 reserved these bits are reserved an d should be written with zeroes. 2:0 pa bias the power amplifier bias (pa bias) bits are used to set the transmit power of the ic through increasing (values up to 7) or decreasing (values down to 0) the gain of the on-chip power ampl ifier. the higher the register value the higher the transmit power. by changing the pa bias value signal strength mana gement functions can be acco mplished. for general purpose communication a value of 7 is recommended.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 20 of 30 addr: 0x24 reg_crystal_adj default: 0x00 76543210 reserved clock output disable crystal adjust figure 7-25. crystal adjust bit name description 7 reserved this bit is reserved and should be written with zero. 6 clock output disable the clock output disable bit disables the 13 mhz clock driven on the x13out pin. 1 = no 13-mhz clock driven externa ll y . 0 = 13-mhz clock driven externally . if the 13-mhz clock is driven on the x13out pin then receive sensitivity will be reduced by ?4 dbm on channels 5+13 n . by default the 13-mhz clock output pin is enabled. this pin is useful for adjusting the 13-mhz clock, but it interfere with every 13th channel beginn ing with 2.405ghz channel. therefore, it is recommended that the 13-mhz clock output pin be disabled when not in use. 5:0 crystal adjust the crystal adjust value is used to calibrate the on-chip parallel load capacit ance supplied to the crystal. e ach increment of the crystal adjust value typically adds 0.135 pf of parallel load capacitance. the total range is 8.5 pf, starting at 8.65 pf. these numbers do not incl ude pcb parasitics, which can add an additional 1?2 pf. addr: 0x26 reg_vco_cal default: 0x00 76543210 vco slope enable reserved figure 7-26. vco calibration bit name description 7:6 vco slope enable (write-only) the voltage controlled oscillator (vco) slope enable bits are used to specify the amount of variance automatically added to the vco. 11 = ?5/+5 vco adjust. the application mcu must configure this option during initialization. 10 = ?2/+3 vco adjust. 01 = reserved. 00 = no vco adjust. these bits are undefined for read operations. 5:0 reserved these bits are reserved and should be written with zeroes. addr: 0x2e reg_pwr_ctl default: 0x00 76543210 reg power control reserved figure 7-27. reg power control bit name description 7 reg power control when set, this bit disables unus ed circuitry and saves radio power. the user must set reg 0x20, bit 6=1 to enable writes to reg 0x2e. the application mcu must set this bit during initialization. 6:0 reserved these bits are reserved and should be written with zeroes.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 21 of 30 addr: 0x2f reg_carrier_detect default: 0x00 76543210 carrier detect override reserved figure 7-28. carrier detect bit name description 7 carrier detect override when set, this bit ov errides carrier detect. the user must set re g 0x20, bit 6=1 to enable writes to reg 0x2f. 6:0 reserved these bits are reserved and should be written with zeroes. addr: 0x32 reg_clock_manual default: 0x00 76543210 manual clock overrides figure 7-29. clock manual bit name description 7:0 manual clock overrides this register must be written with 0x41 after reset for correct operation addr: 0x33 reg_clock_enable default: 0x00 76543210 manual clock enables figure 7-30. clock enable bit name description 7:0 manual clock enables this register must be writ ten with 0x41 after reset for correct operation addr: 0x38 reg_syn_lock_cnt default: 0x64 76543210 count figure 7-31. synthesizer lock count bit name description 7:0 count determines the length of delay in 2s increm ents for the synthesizer to lock when auto synthesizer is enabled via control regis ter (0x03, bit 1=0) and not using the pll lock signal. t he default register setting is typically sufficient. addr: 0x3c-3f reg_mid 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 address 0x3f address 0x3e address 0x3d address 0x3c figure 7-32. manufacturing id bit name description 31:30 address[31:30] these bits are read back as zeroes. 29:0 address[29:0] these bits are the manufacturing id (mid) for eac h ic. the contents of these bits cannot be read unless the mi d read enable bit (bit 5) is set in the analog control regist er (reg 0x20). enabling the manufacturing id register (reg 0x3c-0x3f) consumes power. the mid read enable bit in the analog control register (reg 0x20, bit 5) should only be set when reading the contents of the manufacturing id register (reg 0x3c-0x3f). this register is read-only.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 22 of 30 8.0 pin definitions table 8-1. pin description ta ble for the cywusb6932/cywusb6934 pin qfn name type default description 46 rfin input input rf input . modulated rf signal received (cywusb6934 only). 5 rfout output n/a rf output . modulated rf signal to be transmitted. 38 x13 input n/a crystal input . (refer to section 4.6 ). 35 x13in input n/a crystal input . (refer to section 4.6 ). 26 x13out output/hi-z output system clock . buffered 13-mhz system clock. 33 pd input n/a power down . asserting this input (low), will put the cywusb6932/cywusb6934 in the suspend mode (x13out is 0 when pd is low). 14 reset input n/a active low reset . device reset. 34 pactl i/o input pactl . external power amplifier control. pull-down or make output. 20 dio i/o input data input/output. serdes bypass mode data transmit/receive. 19 dioval i/o input data i/o valid . serdes bypass mode data transmit/receive valid. 21 irq output /hi-z output irq . interrupt and serdes bypass mode dioclk. 23 mosi input n/a master-output-slave-input data . spi data input pin. 24 miso output/hi-z hi-z master-input-slave-output data . spi data output pin. 25 sck input n/a spi input clock . spi clock. 22 ss input n/a slave select enable . spi enable. 6, 9, 16, 28, 29, 32, 41, 42, 44, 45 vcc vcc h v cc = 2.7v to 3.6v. 13 gnd gnd l ground = 0v . 1, 2, 3, 4, 7, 8, 10, 11, 12, 15, 17, 18, 27, 30, 31, 36, 37, 39, 40, 43, 47, 48 nc n/a n/a must be tied to ground. exposed paddle gnd gnd l must be tied to ground.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 23 of 30 figure 8-1. cywusb6934/cywusb6932, 48 qfn ? top view cywusb6934/cywusb6932 48 qfn v cc nc nc v cc nc nc rfout nc **rfin v cc v cc nc v cc v cc nc nc nc x13 nc nc nc v cc nc nc dioval dio irq miso ss mosi reset gnd sck x13out nc v cc x13in v cc nc nc nc pactl v cc pd * e-pad bottom side cywusb6934/cywusb6932 top view* nc nc 15 16 17 18 19 20 21 24 22 23 14 13 48 47 46 45 38 44 43 42 37 39 41 40 12 11 10 9 2 8 7 6 1 3 5 4 27 28 29 30 31 32 33 36 34 35 26 25 nc nc ** cywusb6934 only
cywusb6932 cywusb6934 document 38-16007 rev. *i page 24 of 30 9.0 absolute maximum ratings storage temperature ............................................................................................................ ................................?65c to +150c ambient temperature with power applied ......................................................................................... ...................?55c to +125c supply voltage on v cc relative to vss............................................................................................................... .....?0.3v to +3.9v dc voltage to logic inputs [8] ........................................................................................................................... ?0.3 v to v cc +0.3v dc voltage applied to outputs in high-z state........................................................................................................ ............................ ?0.3v to v cc +0.3v static discharge voltage (digital) [9] ............................................................................................................................... ..... >2000v static discharge voltage (rf) [9] ............................................................................................................................... .............. 500v latch-up current ............................................................................................................... ................................+200 ma, ?200 ma 10.0 operating conditions v cc (supply voltage) .............................................................................................................. ..................................... 2.7v to 3.6v t a (ambient temperature under bias) .............................................................................................. .........................0c to +70c ground voltage ................................................................................................................. .......................................................... 0v f osc (oscillator or crystal frequency) .............................................................................................. .................. 13 mhz 50 ppm 11.0 dc characteristics (over the operating range) table 11-1. dc parameters parameter description conditions min. typ. [11] max. unit v cc supply voltage 2.7 3.0 3.6 v v oh1 output high voltage condition 1 at i oh = ?100.0 a v cc ? 0.1 v cc v v oh2 output high voltage condition 2 at i oh = ?2.0 ma 2.4 3.0 v v ol output low voltage at i ol = 2.0 ma 0.0 0.4 v v ih input high voltage 2.0 v cc [10] v v il input low voltage ?0.3 0.8 v i il input leakage current 0 < v in < v cc ?1 0.26 +1 a c in pin input capacitance (except x13, x13in, rfin) 3.5 10 pf i sleep current consumption during power-down mode pd = low 0.24 10 [14] a idle i cc current consumption without synthesizer pd = high 3 ma startup i cc icc from pd high to oscillator stable. 1.8 ma tx avg i cc1 average transmitter current consumption [12] no handshake 5.9 ma tx avg i cc2 average transmitter current consumption [13] with handshaking 8.1 ma rx i cc (peak) current consumption during receive 57.7 ma tx i cc (peak) current consumption during transmit 69.1 ma synth settle i cc current consumption with synthesizer on, no transmit or receive 28.7 ma notes: 8. it is permissible to connect voltages above vcc to inputs th rough a series resistor limiting input current to 1 ma. this can? t be done during power down mode. ac timing not guaranteed. 9. human body model (hbm). 10. it is permissible to connect voltages above vcc to inputs through a series re sistor limiting input current to 1 ma. 11. typ. values measured with v cc = 3.0v @ 25c 12. average icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the wirelessusb ls 1-wa y protocol. 13. average icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the wirelessusb ls 2-wa y protocol. 14. max. value measured with v cc = 3.3v
cywusb6932 cywusb6934 document 38-16007 rev. *i page 25 of 30 12.0 ac characteristics [15] notes: 15. ac values are not guaranteed if voltages on any pin exceed vcc. 16. this stretch only applies to every 9th sck hi pulse for spi burst reads only. 17. for f osc = 13 mhz 50 ppm, 3.3v @ 25c. 18. sck must start low, otherwise the su ccess of spi transactions are not guaranteed. table 12-1. spi interface [17] parameter description min. typ. max. unit t sck_cyc spi clock period 476 ns t sck_hi (burst read) [16] spi clock high time 238 ns t sck_hi spi clock high time 158 ns t sck_lo spi clock low time 158 ns t dat_su spi input data set-up time 10 ns t dat_hld spi input data hold time 97 [17] ns t dat_val spi output data valid time 77 [17] 174 [17] ns t ss_su spi slave select set-up time before first positive edge of sck [18] 250 ns t ss_hld spi slave select hold time after last negative edge of sck 80 ns figure 12-1. spi timing diagram figure 12-2. spi burst read every 9th sck hi stretch timing diagram data from mcu mosi t sck_cyc sck t sck_hi t sck_lo t dat_su t dat_hld miso ss t ss_su t ss_hld t dat_val data data s a m p l e d r i v e data from mcu data from mcu data to mcu data to mcu data to mcu miso t sck_cyc sck t sck_hi t sck_lo ss t dat_val data d r i v e data to mcu data to mcu every 8 th sck_hi every 9 th sck_hi every 10 th sck_hi t sck_hi (burst read) d r i v e d r i v e
cywusb6932 cywusb6934 document 38-16007 rev. *i page 26 of 30 table 12-2. dio interface parameter description transmit min. typ. max. unit t tx_dioval_su dioval set-up time 2.1 s t tx_dio_su dio set-up time 2.1 s t tx_dioval_hld dioval hold time 0 s t tx_dio_hld dio hold time 0 s t tx_irq_hi minimum irq high time - 32 chips/bit ddr 8 s minimum irq high time - 32 chips/bit 16 s minimum irq high time - 64 chips/bit 32 s t tx_irq_lo minimum irq low time - 32 chips/bit ddr 8 s minimum irq low time - 32 chips/bit 16 s minimum irq low time - 64 chips/bit 32 s receive min. typ. max. unit t rx_dioval_vld dioval valid time - 32 chips/bit ddr ?0.01 6.1 s dioval valid time - 32 chips/bit ?0.01 8.2 s dioval valid time - 64 chips/bit ?0.01 16.1 s t rx_dio_vld dio valid time - 32 chips/bit ddr ?0.01 6.1 s dio valid time - 32 chips/bit ?0.01 8.2 s dio valid time - 64 chips/bit ?0.01 16.1 s t rx_irq_hi minimum irq high time - 32 chips/bit ddr 1 s minimum irq high time - 32 chips/bit 1 s minimum irq high time - 64 chips/bit 1 s t rx_irq_lo minimum irq low time - 32 chips/bit ddr 8 s minimum irq low time - 32 chips/bit 16 s minimum irq low time - 64 chips/bit 32 s figure 12-3. dio receive timing diagram figure 12-4. dio transmit timing diagram data dio/ dioval irq data t rx_irq_hi t rx_irq_lo s a m p l e t rx_dioval_vld t rx_dio_vld data s a m p l e dio/ dioval irq data data t tx_irq_hi t tx_irq_lo t tx_dio_su t tx_dioval_su t tx_dioval_hld t tx_dio_hld s a m p l e s a m p l e
cywusb6932 cywusb6934 document 38-16007 rev. *i page 27 of 30 12.1 radio parameters table 12-3. radio parameters parameter description conditions min. typ. max. unit rf frequency range [19] 2.400 2.483 ghz radio receiver (t = 25c, v cc = 3.3v, fosc = 13.000 mhz, x13out off, 64 chips/bit, threshold low = 8, threshold high = 56, ber < 10 ?3 ) sensitivity ?90 dbm maximum received signal ?20 ?10 dbm rssi value for pwr in > ?40 dbm 28?31 rssi value for pwr in < ?95 dbm 0?10 receive ready [20] 35 s interference performance co-channel interference rejection carrier-to-interference (c/i) c = ?60 dbm 11 db adjacent (1 mhz) channel selectivity c/i 1 mhz c = ?60 dbm 3 db adjacent (2 mhz) channel selectivity c/i 2 mhz c = ?60 dbm ?30 db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = ?67 dbm ?40 db image [21] frequency interference, c/i image c = ?67 dbm ?20 db adjacent (1 mhz) interference to in-band image frequency, c/i image 1 mhz c = ?67 dbm ?25 db out-of-band blocking interference signal frequency 30 mhz ? 2399 mhz, exc ept (fo/n & fo/n1 mhz) [22] c = ?67 dbm ?30 dbm 2498 mhz ? 12.75 ghz, except (fo*n & fo*n1 mhz) [22] c = ?67 dbm ?20 dbm intermodulation c = ?64 dbm, ? f = 5,10 mhz ?39 dbm spurious emission 30 mhz?1 ghz ?57 dbm 1 ghz?12.75 ghz except (4.8 ghz - 5.0 ghz) ?54 dbm 4.8 ghz?5.0 ghz ?40 [23] dbm radio transmitter (t = 25c, v cc = 3.3v, fosc = 13.000 mhz) maximum rf transmit power pa = 7 0 dbm rf power control range 30 db rf power range control step size seven steps, monotonic 4.3 db frequency deviation pn code pattern 10101010 270 khz frequency deviation pn code pattern 1111 0000 320 khz zero crossing error 125 ns occupied bandwidth 100-khz resolution bandwidth, ?6 dbc 500 khz initial frequency offset 75 khz in-band spurious second channel power ( 2 mhz) ?30 dbm > third channel power (> 3 mhz) ?40 dbm non-harmonically related spurs 30 mhz?12.75 ghz ?54 dbm harmonic spurs second harmonic ?28 dbm third harmonic ?25 dbm fourth and greater harmonics ?42 dbm notes: 19. subject to regulation. 20. max. time after receive enable and the synthes izer has settled before receiver is ready. 21. image frequency is +4 mhz from desired channel (2 mhz low if, high side injection). 22. fo = tuned frequency, n = integer. 23. antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements.
cywusb6932 cywusb6934 document 38-16007 rev. *i page 28 of 30 12.2 power management timing notes: 24. the pd pin must be asserted at power up to ensure proper crystal startup. 25. when x13out is enabled. 26. both the polarity and the drive method of the irq pin are programmable. see page 9 for more details. figure 12-6 illustrates default values for the configuration register (reg 0x05, bits 1:0). 27. a wakeup event is triggered when the pd pin is deasserted. figure 12-6 illustrates a wakeup event configured to tr igger an irq pin event via the wake enable register (reg 0x1c, bit 0=1). 28. measured with cts atxn6077a crystal. table 12-4. power management timing (the values below are dependent upon oscillator network component selection) [28] parameter description conditions min. typ max. unit t pdn_x13 time from pd deassert to x13out 2000 s t spi_rdy time from oscillator stable to start of spi transactions 1 s t pwr_rst power on to reset deasserted v cc @ 2.7v 1300 s t rst minimum reset asserted pulse width 1 s t pwr_pd power on to pd deasserted [24] 1300 s t wake pd deassert to clocks running [25] 2000 s t pd minimum pd asserted pulse width 10 s t sleep pd assert to low power mode 50 ns t wake_int pd deassert to irq [26] assert (wake interrupt) [27] 2000 s t stable pd deassert to clock stable to within 10 ppm 2100 s t stable2 irq assert (wake interrupt) to clock stable to within 10 ppm 2100 s figure 12-5. power on reset/reset timing figure 12-6. sleep / wake timing vcc reset pd x13out t pwr_rst t pwr_pd t spi_rdy t rst t pdn_x13 s t a r t u p irq x13out t wa ke_int t wake t pd t sl eep pd s l e e p w a k e i r q t stable t stable2
cywusb6932 cywusb6934 document 38-16007 rev. *i page 29 of 30 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 12.3 ac test loads and waveforms for digital pins 13.0 ordering information 14.0 package description the recommended dimension of the pcb pad size for the e-pad underneath the qfn is 209 mils 209 mils (width x length). this document is subject to change, and may be found to contain errors of omission or changes in parameters. for feedback or technical support regarding cypress wirelessusb products plea se contact cypress at www. cypress.com. wi relessusb, psoc, and encore are trademarks of cypress semiconductor. all produ ct and company names mentioned in this document are the trademarks of their respective holders. 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: venin equivalent v th th rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 ? r2 937 ? r th 500 ? v th 1.4 v v cc 3.00 v v cc output r1 r2 ac test loads dc test load figure 12-7. ac test loads and waveforms for digital pins table 13-1. ordering information part number radio package name package type operating range CYWUSB6932-48LFXC transmitter 48 qfn 48 quad flat package no leads lead-free commercial cywusb6934-48lfxc transceiver 48 qfn 48 quad flat package no leads lead-free commercial figure 14-1. 48-pin lead-free qfn 7 x 7 mm ly48 0.80 dia. 6.70 6.90 c 1.00 max. n seating plane n 2 2 0.230.05 0.50 1 1 0.08 0-12 0.30-0.45 0.05 max. c 0.20 ref. 0.80 max. pin1 id 5.45 0.420.18 (4x) 7.10 6.80 6.70 6.80 7.10 6.90 5.55 5.45 5.55 0.20 r. 0.45 y x top view bottom view side view e-pad dimensions in mm min. max. e-pad size paddle size 5.1 x 5.1 3.8 x 3.8 4.0 x 4.0 5.3 x 5.3 (x, y max.) reference jedec mo-220 pkg. weight 0.13 gms 51-85152-*b
cywusb6932 cywusb6934 document 38-16007 rev. *i page 30 of 30 document history page document title: cywusb6932/cywusb6934 wi relessusb? ls 2.4-ghz dsss radio soc document number: 38-16007 rev. ecn no. issue date orig. of change description of change ** 123907 01/20/03 lxa new data sheet *a 125470 04/28/03 xgr preliminary release *b 127076 07/30/03 kku updated pinouts, timing diagrams, ac test loads, dc characteristics, radio characteristics removed die *c 128886 08/04/03 kkv minor change: removed table of contents and fixed layout of section 10. *d 129180 12/04/03 tge updated ac and dc characteristics from char. results updated register entries changed package type from 56-pin qfn to 48-pin qfn updated all pinouts and timing diagrams updated block diagram and functional description updated application interfaces added interrupt descriptions *e 131851 12/15/03 tge changed static discharge voltage (digital) specification of section 9.0 *f 241471 see ecn ztk removed static discharge voltage (digital) specification of section 9.0 footnote updated reg_data_rate (0x04), 111?not valid swapped bit field descriptions of reg_config corrected figure 3-1 and figure 6-2 minor edits throughout *g 284810 see ecn ztk removed soic package option updated ordering information section added ta ble 4-1 internal pa output power step table added t stable2 parameter to table 12-4 and figure 12-6 corrected figure 14-1 caption corrected figure 6-2 to show qfn matching network removed addr 0x01 and 0x02 - unused updated figure 8-1 updated spurious emissions parameters *h 335758 see ecn tge corrected figure 6-2 - swap rfin / rfout corrected reg_control - bit 1 description added ta ble 11 -1 footnote 14 - max. value measured with vcc = 3.3v *i 391306 see ecn tge added receive ready parameter to table 12-3

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